1 //===- RegisterCoalescer.cpp - Generic Register Coalescing Interface -------==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the generic RegisterCoalescer interface which
11 // is used as the common interface used by all clients and
12 // implementations of register coalescing.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "regalloc"
17 #include "RegisterCoalescer.h"
18 #include "LiveDebugVariables.h"
19 #include "RegisterClassInfo.h"
20 #include "VirtRegMap.h"
22 #include "llvm/Pass.h"
23 #include "llvm/Value.h"
24 #include "llvm/ADT/OwningPtr.h"
25 #include "llvm/ADT/STLExtras.h"
26 #include "llvm/ADT/SmallSet.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Analysis/AliasAnalysis.h"
29 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
30 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
31 #include "llvm/CodeGen/LiveRangeEdit.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineInstr.h"
34 #include "llvm/CodeGen/MachineInstr.h"
35 #include "llvm/CodeGen/MachineLoopInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/ErrorHandling.h"
42 #include "llvm/Support/raw_ostream.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetInstrInfo.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/Target/TargetRegisterInfo.h"
52 STATISTIC(numJoins , "Number of interval joins performed");
53 STATISTIC(numCrossRCs , "Number of cross class joins performed");
54 STATISTIC(numCommutes , "Number of instruction commuting performed");
55 STATISTIC(numExtends , "Number of copies extended");
56 STATISTIC(NumReMats , "Number of instructions re-materialized");
57 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
58 STATISTIC(NumInflated , "Number of register classes inflated");
61 EnableJoining("join-liveintervals",
62 cl::desc("Coalesce copies (default=true)"),
66 VerifyCoalescing("verify-coalescing",
67 cl::desc("Verify machine instrs before and after register coalescing"),
71 class RegisterCoalescer : public MachineFunctionPass,
72 private LiveRangeEdit::Delegate {
74 MachineRegisterInfo* MRI;
75 const TargetMachine* TM;
76 const TargetRegisterInfo* TRI;
77 const TargetInstrInfo* TII;
79 LiveDebugVariables *LDV;
80 const MachineLoopInfo* Loops;
82 RegisterClassInfo RegClassInfo;
84 /// JoinedCopies - Keep track of copies eliminated due to coalescing.
86 SmallPtrSet<MachineInstr*, 32> JoinedCopies;
88 /// ReMatDefs - Keep track of definition instructions which have
90 SmallPtrSet<MachineInstr*, 8> ReMatDefs;
92 /// WorkList - Copy instructions yet to be coalesced.
93 SmallVector<MachineInstr*, 8> WorkList;
95 /// ErasedInstrs - Set of instruction pointers that have been erased, and
96 /// that may be present in WorkList.
97 SmallPtrSet<MachineInstr*, 8> ErasedInstrs;
99 /// Dead instructions that are about to be deleted.
100 SmallVector<MachineInstr*, 8> DeadDefs;
102 /// Virtual registers to be considered for register class inflation.
103 SmallVector<unsigned, 8> InflateRegs;
105 /// Recursively eliminate dead defs in DeadDefs.
106 void eliminateDeadDefs();
108 /// LiveRangeEdit callback.
109 void LRE_WillEraseInstruction(MachineInstr *MI);
111 /// joinAllIntervals - join compatible live intervals
112 void joinAllIntervals();
114 /// copyCoalesceInMBB - Coalesce copies in the specified MBB, putting
115 /// copies that cannot yet be coalesced into WorkList.
116 void copyCoalesceInMBB(MachineBasicBlock *MBB);
118 /// copyCoalesceWorkList - Try to coalesce all copies in WorkList after
119 /// position From. Return true if any progress was made.
120 bool copyCoalesceWorkList(unsigned From = 0);
122 /// joinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
123 /// which are the src/dst of the copy instruction CopyMI. This returns
124 /// true if the copy was successfully coalesced away. If it is not
125 /// currently possible to coalesce this interval, but it may be possible if
126 /// other things get coalesced, then it returns true by reference in
128 bool joinCopy(MachineInstr *TheCopy, bool &Again);
130 /// joinIntervals - Attempt to join these two intervals. On failure, this
131 /// returns false. The output "SrcInt" will not have been modified, so we
132 /// can use this information below to update aliases.
133 bool joinIntervals(CoalescerPair &CP);
135 /// Attempt joining with a reserved physreg.
136 bool joinReservedPhysReg(CoalescerPair &CP);
138 /// adjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
139 /// the source value number is defined by a copy from the destination reg
140 /// see if we can merge these two destination reg valno# into a single
141 /// value number, eliminating a copy.
142 bool adjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
144 /// hasOtherReachingDefs - Return true if there are definitions of IntB
145 /// other than BValNo val# that can reach uses of AValno val# of IntA.
146 bool hasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
147 VNInfo *AValNo, VNInfo *BValNo);
149 /// removeCopyByCommutingDef - We found a non-trivially-coalescable copy.
150 /// If the source value number is defined by a commutable instruction and
151 /// its other operand is coalesced to the copy dest register, see if we
152 /// can transform the copy into a noop by commuting the definition.
153 bool removeCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI);
155 /// reMaterializeTrivialDef - If the source of a copy is defined by a
156 /// trivial computation, replace the copy by rematerialize the definition.
157 bool reMaterializeTrivialDef(LiveInterval &SrcInt, unsigned DstReg,
158 MachineInstr *CopyMI);
160 /// canJoinPhys - Return true if a physreg copy should be joined.
161 bool canJoinPhys(CoalescerPair &CP);
163 /// updateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
164 /// update the subregister number if it is not zero. If DstReg is a
165 /// physical register and the existing subregister number of the def / use
166 /// being updated is not zero, make sure to set it to the correct physical
168 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
170 /// removeDeadDef - If a def of a live interval is now determined dead,
171 /// remove the val# it defines. If the live interval becomes empty, remove
173 bool removeDeadDef(LiveInterval &li, MachineInstr *DefMI);
175 /// markAsJoined - Remember that CopyMI has already been joined.
176 void markAsJoined(MachineInstr *CopyMI);
178 /// eliminateUndefCopy - Handle copies of undef values.
179 bool eliminateUndefCopy(MachineInstr *CopyMI, const CoalescerPair &CP);
182 static char ID; // Class identification, replacement for typeinfo
183 RegisterCoalescer() : MachineFunctionPass(ID) {
184 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
187 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
189 virtual void releaseMemory();
191 /// runOnMachineFunction - pass entry point
192 virtual bool runOnMachineFunction(MachineFunction&);
194 /// print - Implement the dump method.
195 virtual void print(raw_ostream &O, const Module* = 0) const;
197 } /// end anonymous namespace
199 char &llvm::RegisterCoalescerID = RegisterCoalescer::ID;
201 INITIALIZE_PASS_BEGIN(RegisterCoalescer, "simple-register-coalescing",
202 "Simple Register Coalescing", false, false)
203 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
204 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
205 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
206 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
207 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
208 INITIALIZE_PASS_END(RegisterCoalescer, "simple-register-coalescing",
209 "Simple Register Coalescing", false, false)
211 char RegisterCoalescer::ID = 0;
213 static unsigned compose(const TargetRegisterInfo &tri, unsigned a, unsigned b) {
216 return tri.composeSubRegIndices(a, b);
219 static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI,
220 unsigned &Src, unsigned &Dst,
221 unsigned &SrcSub, unsigned &DstSub) {
223 Dst = MI->getOperand(0).getReg();
224 DstSub = MI->getOperand(0).getSubReg();
225 Src = MI->getOperand(1).getReg();
226 SrcSub = MI->getOperand(1).getSubReg();
227 } else if (MI->isSubregToReg()) {
228 Dst = MI->getOperand(0).getReg();
229 DstSub = compose(tri, MI->getOperand(0).getSubReg(),
230 MI->getOperand(3).getImm());
231 Src = MI->getOperand(2).getReg();
232 SrcSub = MI->getOperand(2).getSubReg();
238 bool CoalescerPair::setRegisters(const MachineInstr *MI) {
242 Flipped = CrossClass = false;
244 unsigned Src, Dst, SrcSub, DstSub;
245 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
247 Partial = SrcSub || DstSub;
249 // If one register is a physreg, it must be Dst.
250 if (TargetRegisterInfo::isPhysicalRegister(Src)) {
251 if (TargetRegisterInfo::isPhysicalRegister(Dst))
254 std::swap(SrcSub, DstSub);
258 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
260 if (TargetRegisterInfo::isPhysicalRegister(Dst)) {
261 // Eliminate DstSub on a physreg.
263 Dst = TRI.getSubReg(Dst, DstSub);
264 if (!Dst) return false;
268 // Eliminate SrcSub by picking a corresponding Dst superregister.
270 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
271 if (!Dst) return false;
273 } else if (!MRI.getRegClass(Src)->contains(Dst)) {
277 // Both registers are virtual.
278 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
279 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
281 // Both registers have subreg indices.
282 if (SrcSub && DstSub) {
283 // Copies between different sub-registers are never coalescable.
284 if (Src == Dst && SrcSub != DstSub)
287 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
292 // SrcReg will be merged with a sub-register of DstReg.
294 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
296 // DstReg will be merged with a sub-register of SrcReg.
298 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
300 // This is a straight copy without sub-registers.
301 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
304 // The combined constraint may be impossible to satisfy.
308 // Prefer SrcReg to be a sub-register of DstReg.
309 // FIXME: Coalescer should support subregs symmetrically.
310 if (DstIdx && !SrcIdx) {
312 std::swap(SrcIdx, DstIdx);
316 CrossClass = NewRC != DstRC || NewRC != SrcRC;
318 // Check our invariants
319 assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual");
320 assert(!(TargetRegisterInfo::isPhysicalRegister(Dst) && DstSub) &&
321 "Cannot have a physical SubIdx");
327 bool CoalescerPair::flip() {
328 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
330 std::swap(SrcReg, DstReg);
331 std::swap(SrcIdx, DstIdx);
336 bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
339 unsigned Src, Dst, SrcSub, DstSub;
340 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
343 // Find the virtual register that is SrcReg.
346 std::swap(SrcSub, DstSub);
347 } else if (Src != SrcReg) {
351 // Now check that Dst matches DstReg.
352 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
353 if (!TargetRegisterInfo::isPhysicalRegister(Dst))
355 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state.");
356 // DstSub could be set for a physreg from INSERT_SUBREG.
358 Dst = TRI.getSubReg(Dst, DstSub);
361 return DstReg == Dst;
362 // This is a partial register copy. Check that the parts match.
363 return TRI.getSubReg(DstReg, SrcSub) == Dst;
365 // DstReg is virtual.
368 // Registers match, do the subregisters line up?
369 return compose(TRI, SrcIdx, SrcSub) == compose(TRI, DstIdx, DstSub);
373 void RegisterCoalescer::getAnalysisUsage(AnalysisUsage &AU) const {
374 AU.setPreservesCFG();
375 AU.addRequired<AliasAnalysis>();
376 AU.addRequired<LiveIntervals>();
377 AU.addPreserved<LiveIntervals>();
378 AU.addRequired<LiveDebugVariables>();
379 AU.addPreserved<LiveDebugVariables>();
380 AU.addPreserved<SlotIndexes>();
381 AU.addRequired<MachineLoopInfo>();
382 AU.addPreserved<MachineLoopInfo>();
383 AU.addPreservedID(MachineDominatorsID);
384 MachineFunctionPass::getAnalysisUsage(AU);
387 void RegisterCoalescer::markAsJoined(MachineInstr *CopyMI) {
388 /// Joined copies are not deleted immediately, but kept in JoinedCopies.
389 JoinedCopies.insert(CopyMI);
391 /// Mark all register operands of CopyMI as <undef> so they won't affect dead
392 /// code elimination.
393 for (MachineInstr::mop_iterator I = CopyMI->operands_begin(),
394 E = CopyMI->operands_end(); I != E; ++I)
399 void RegisterCoalescer::eliminateDeadDefs() {
400 SmallVector<LiveInterval*, 8> NewRegs;
401 LiveRangeEdit(0, NewRegs, *MF, *LIS, 0, this).eliminateDeadDefs(DeadDefs);
404 // Callback from eliminateDeadDefs().
405 void RegisterCoalescer::LRE_WillEraseInstruction(MachineInstr *MI) {
406 // MI may be in WorkList. Make sure we don't visit it.
407 ErasedInstrs.insert(MI);
410 /// adjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
411 /// being the source and IntB being the dest, thus this defines a value number
412 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
413 /// see if we can merge these two pieces of B into a single value number,
414 /// eliminating a copy. For example:
418 /// B1 = A3 <- this copy
420 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
421 /// value number to be replaced with B0 (which simplifies the B liveinterval).
423 /// This returns true if an interval was modified.
425 bool RegisterCoalescer::adjustCopiesBackFrom(const CoalescerPair &CP,
426 MachineInstr *CopyMI) {
427 assert(!CP.isPartial() && "This doesn't work for partial copies.");
429 // Bail if there is no dst interval - can happen when merging physical subreg
431 if (!LIS->hasInterval(CP.getDstReg()))
435 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
437 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
438 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
440 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
441 // the example above.
442 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
443 if (BLR == IntB.end()) return false;
444 VNInfo *BValNo = BLR->valno;
446 // Get the location that B is defined at. Two options: either this value has
447 // an unknown definition point or it is defined at CopyIdx. If unknown, we
449 if (BValNo->def != CopyIdx) return false;
451 // AValNo is the value number in A that defines the copy, A3 in the example.
452 SlotIndex CopyUseIdx = CopyIdx.getRegSlot(true);
453 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
454 // The live range might not exist after fun with physreg coalescing.
455 if (ALR == IntA.end()) return false;
456 VNInfo *AValNo = ALR->valno;
458 // If AValNo is defined as a copy from IntB, we can potentially process this.
459 // Get the instruction that defines this value number.
460 MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def);
461 if (!CP.isCoalescable(ACopyMI))
464 // Get the LiveRange in IntB that this value number starts with.
465 LiveInterval::iterator ValLR =
466 IntB.FindLiveRangeContaining(AValNo->def.getPrevSlot());
467 if (ValLR == IntB.end())
470 // Make sure that the end of the live range is inside the same block as
472 MachineInstr *ValLREndInst =
473 LIS->getInstructionFromIndex(ValLR->end.getPrevSlot());
474 if (!ValLREndInst || ValLREndInst->getParent() != CopyMI->getParent())
477 // Okay, we now know that ValLR ends in the same block that the CopyMI
478 // live-range starts. If there are no intervening live ranges between them in
479 // IntB, we can merge them.
480 if (ValLR+1 != BLR) return false;
482 // If a live interval is a physical register, conservatively check if any
483 // of its aliases is overlapping the live interval of the virtual register.
484 // If so, do not coalesce.
485 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
486 for (const uint16_t *AS = TRI->getAliasSet(IntB.reg); *AS; ++AS)
487 if (LIS->hasInterval(*AS) && IntA.overlaps(LIS->getInterval(*AS))) {
489 dbgs() << "\t\tInterfere with alias ";
490 LIS->getInterval(*AS).print(dbgs(), TRI);
497 dbgs() << "Extending: ";
498 IntB.print(dbgs(), TRI);
501 SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
502 // We are about to delete CopyMI, so need to remove it as the 'instruction
503 // that defines this value #'. Update the valnum with the new defining
505 BValNo->def = FillerStart;
507 // Okay, we can merge them. We need to insert a new liverange:
508 // [ValLR.end, BLR.begin) of either value number, then we merge the
509 // two value numbers.
510 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
512 // If the IntB live range is assigned to a physical register, and if that
513 // physreg has sub-registers, update their live intervals as well.
514 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
515 for (const uint16_t *SR = TRI->getSubRegisters(IntB.reg); *SR; ++SR) {
516 if (!LIS->hasInterval(*SR))
518 LiveInterval &SRLI = LIS->getInterval(*SR);
519 SRLI.addRange(LiveRange(FillerStart, FillerEnd,
520 SRLI.getNextValue(FillerStart,
521 LIS->getVNInfoAllocator())));
525 // Okay, merge "B1" into the same value number as "B0".
526 if (BValNo != ValLR->valno) {
527 // If B1 is killed by a PHI, then the merged live range must also be killed
528 // by the same PHI, as B0 and B1 can not overlap.
529 bool HasPHIKill = BValNo->hasPHIKill();
530 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
532 ValLR->valno->setHasPHIKill(true);
535 dbgs() << " result = ";
536 IntB.print(dbgs(), TRI);
540 // If the source instruction was killing the source register before the
541 // merge, unset the isKill marker given the live range has been extended.
542 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
544 ValLREndInst->getOperand(UIdx).setIsKill(false);
547 // Rewrite the copy. If the copy instruction was killing the destination
548 // register before the merge, find the last use and trim the live range. That
549 // will also add the isKill marker.
550 CopyMI->substituteRegister(IntA.reg, IntB.reg, 0, *TRI);
551 if (ALR->end == CopyIdx)
552 LIS->shrinkToUses(&IntA);
558 /// hasOtherReachingDefs - Return true if there are definitions of IntB
559 /// other than BValNo val# that can reach uses of AValno val# of IntA.
560 bool RegisterCoalescer::hasOtherReachingDefs(LiveInterval &IntA,
564 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
566 if (AI->valno != AValNo) continue;
567 LiveInterval::Ranges::iterator BI =
568 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
569 if (BI != IntB.ranges.begin())
571 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
572 if (BI->valno == BValNo)
574 if (BI->start <= AI->start && BI->end > AI->start)
576 if (BI->start > AI->start && BI->start < AI->end)
583 /// removeCopyByCommutingDef - We found a non-trivially-coalescable copy with
584 /// IntA being the source and IntB being the dest, thus this defines a value
585 /// number in IntB. If the source value number (in IntA) is defined by a
586 /// commutable instruction and its other operand is coalesced to the copy dest
587 /// register, see if we can transform the copy into a noop by commuting the
588 /// definition. For example,
590 /// A3 = op A2 B0<kill>
592 /// B1 = A3 <- this copy
594 /// = op A3 <- more uses
598 /// B2 = op B0 A2<kill>
600 /// B1 = B2 <- now an identify copy
602 /// = op B2 <- more uses
604 /// This returns true if an interval was modified.
606 bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
607 MachineInstr *CopyMI) {
608 // FIXME: For now, only eliminate the copy by commuting its def when the
609 // source register is a virtual register. We want to guard against cases
610 // where the copy is a back edge copy and commuting the def lengthen the
611 // live interval of the source register to the entire loop.
612 if (CP.isPhys() && CP.isFlipped())
615 // Bail if there is no dst interval.
616 if (!LIS->hasInterval(CP.getDstReg()))
619 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
622 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
624 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
626 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
627 // the example above.
628 VNInfo *BValNo = IntB.getVNInfoAt(CopyIdx);
629 if (!BValNo || BValNo->def != CopyIdx)
632 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
634 // AValNo is the value number in A that defines the copy, A3 in the example.
635 VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx.getRegSlot(true));
636 assert(AValNo && "COPY source not live");
638 // If other defs can reach uses of this def, then it's not safe to perform
640 if (AValNo->isPHIDef() || AValNo->isUnused() || AValNo->hasPHIKill())
642 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
645 if (!DefMI->isCommutable())
647 // If DefMI is a two-address instruction then commuting it will change the
648 // destination register.
649 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
650 assert(DefIdx != -1);
652 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
654 unsigned Op1, Op2, NewDstIdx;
655 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
659 else if (Op2 == UseOpIdx)
664 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
665 unsigned NewReg = NewDstMO.getReg();
666 if (NewReg != IntB.reg || !NewDstMO.isKill())
669 // Make sure there are no other definitions of IntB that would reach the
670 // uses which the new definition can reach.
671 if (hasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
674 // Abort if the aliases of IntB.reg have values that are not simply the
675 // clobbers from the superreg.
676 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
677 for (const uint16_t *AS = TRI->getAliasSet(IntB.reg); *AS; ++AS)
678 if (LIS->hasInterval(*AS) &&
679 hasOtherReachingDefs(IntA, LIS->getInterval(*AS), AValNo, 0))
682 // If some of the uses of IntA.reg is already coalesced away, return false.
683 // It's not possible to determine whether it's safe to perform the coalescing.
684 for (MachineRegisterInfo::use_nodbg_iterator UI =
685 MRI->use_nodbg_begin(IntA.reg),
686 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
687 MachineInstr *UseMI = &*UI;
688 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI);
689 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
690 if (ULR == IntA.end())
692 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
696 DEBUG(dbgs() << "\tremoveCopyByCommutingDef: " << AValNo->def << '\t'
699 // At this point we have decided that it is legal to do this
700 // transformation. Start by commuting the instruction.
701 MachineBasicBlock *MBB = DefMI->getParent();
702 MachineInstr *NewMI = TII->commuteInstruction(DefMI);
705 if (TargetRegisterInfo::isVirtualRegister(IntA.reg) &&
706 TargetRegisterInfo::isVirtualRegister(IntB.reg) &&
707 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
709 if (NewMI != DefMI) {
710 LIS->ReplaceMachineInstrInMaps(DefMI, NewMI);
711 MachineBasicBlock::iterator Pos = DefMI;
712 MBB->insert(Pos, NewMI);
715 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
716 NewMI->getOperand(OpIdx).setIsKill();
718 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
727 // Update uses of IntA of the specific Val# with IntB.
728 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(IntA.reg),
729 UE = MRI->use_end(); UI != UE;) {
730 MachineOperand &UseMO = UI.getOperand();
731 MachineInstr *UseMI = &*UI;
733 if (JoinedCopies.count(UseMI))
735 if (UseMI->isDebugValue()) {
736 // FIXME These don't have an instruction index. Not clear we have enough
737 // info to decide whether to do this replacement or not. For now do it.
738 UseMO.setReg(NewReg);
741 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true);
742 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
743 if (ULR == IntA.end() || ULR->valno != AValNo)
745 if (TargetRegisterInfo::isPhysicalRegister(NewReg))
746 UseMO.substPhysReg(NewReg, *TRI);
748 UseMO.setReg(NewReg);
751 if (!UseMI->isCopy())
753 if (UseMI->getOperand(0).getReg() != IntB.reg ||
754 UseMI->getOperand(0).getSubReg())
757 // This copy will become a noop. If it's defining a new val#, merge it into
759 SlotIndex DefIdx = UseIdx.getRegSlot();
760 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
763 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
764 assert(DVNI->def == DefIdx);
765 BValNo = IntB.MergeValueNumberInto(BValNo, DVNI);
769 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
771 VNInfo *ValNo = BValNo;
772 ValNo->def = AValNo->def;
773 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
775 if (AI->valno != AValNo) continue;
776 IntB.addRange(LiveRange(AI->start, AI->end, ValNo));
778 DEBUG(dbgs() << "\t\textended: " << IntB << '\n');
780 IntA.removeValNo(AValNo);
781 DEBUG(dbgs() << "\t\ttrimmed: " << IntA << '\n');
786 /// reMaterializeTrivialDef - If the source of a copy is defined by a trivial
787 /// computation, replace the copy by rematerialize the definition.
788 bool RegisterCoalescer::reMaterializeTrivialDef(LiveInterval &SrcInt,
790 MachineInstr *CopyMI) {
791 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot(true);
792 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
793 assert(SrcLR != SrcInt.end() && "Live range not found!");
794 VNInfo *ValNo = SrcLR->valno;
795 if (ValNo->isPHIDef() || ValNo->isUnused())
797 MachineInstr *DefMI = LIS->getInstructionFromIndex(ValNo->def);
800 assert(DefMI && "Defining instruction disappeared");
801 if (!DefMI->isAsCheapAsAMove())
803 if (!TII->isTriviallyReMaterializable(DefMI, AA))
805 bool SawStore = false;
806 if (!DefMI->isSafeToMove(TII, AA, SawStore))
808 const MCInstrDesc &MCID = DefMI->getDesc();
809 if (MCID.getNumDefs() != 1)
811 if (!DefMI->isImplicitDef()) {
812 // Make sure the copy destination register class fits the instruction
813 // definition register class. The mismatch can happen as a result of earlier
814 // extract_subreg, insert_subreg, subreg_to_reg coalescing.
815 const TargetRegisterClass *RC = TII->getRegClass(MCID, 0, TRI, *MF);
816 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
817 if (MRI->getRegClass(DstReg) != RC)
819 } else if (!RC->contains(DstReg))
823 MachineBasicBlock *MBB = CopyMI->getParent();
824 MachineBasicBlock::iterator MII =
825 llvm::next(MachineBasicBlock::iterator(CopyMI));
826 TII->reMaterialize(*MBB, MII, DstReg, 0, DefMI, *TRI);
827 MachineInstr *NewMI = prior(MII);
829 // NewMI may have dead implicit defs (E.g. EFLAGS for MOV<bits>r0 on X86).
830 // We need to remember these so we can add intervals once we insert
831 // NewMI into SlotIndexes.
832 SmallVector<unsigned, 4> NewMIImplDefs;
833 for (unsigned i = NewMI->getDesc().getNumOperands(),
834 e = NewMI->getNumOperands(); i != e; ++i) {
835 MachineOperand &MO = NewMI->getOperand(i);
837 assert(MO.isDef() && MO.isImplicit() && MO.isDead() &&
838 TargetRegisterInfo::isPhysicalRegister(MO.getReg()));
839 NewMIImplDefs.push_back(MO.getReg());
843 // CopyMI may have implicit operands, transfer them over to the newly
844 // rematerialized instruction. And update implicit def interval valnos.
845 for (unsigned i = CopyMI->getDesc().getNumOperands(),
846 e = CopyMI->getNumOperands(); i != e; ++i) {
847 MachineOperand &MO = CopyMI->getOperand(i);
849 assert(MO.isImplicit() && "No explicit operands after implict operands.");
850 // Discard VReg implicit defs.
851 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
852 NewMI->addOperand(MO);
857 LIS->ReplaceMachineInstrInMaps(CopyMI, NewMI);
859 SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
860 for (unsigned i = 0, e = NewMIImplDefs.size(); i != e; ++i) {
861 unsigned reg = NewMIImplDefs[i];
862 LiveInterval &li = LIS->getInterval(reg);
863 VNInfo *DeadDefVN = li.getNextValue(NewMIIdx.getRegSlot(),
864 LIS->getVNInfoAllocator());
865 LiveRange lr(NewMIIdx.getRegSlot(), NewMIIdx.getDeadSlot(), DeadDefVN);
869 CopyMI->eraseFromParent();
870 ErasedInstrs.insert(CopyMI);
871 ReMatDefs.insert(DefMI);
872 DEBUG(dbgs() << "Remat: " << *NewMI);
875 // The source interval can become smaller because we removed a use.
876 LIS->shrinkToUses(&SrcInt, &DeadDefs);
877 if (!DeadDefs.empty())
883 /// eliminateUndefCopy - ProcessImpicitDefs may leave some copies of <undef>
884 /// values, it only removes local variables. When we have a copy like:
886 /// %vreg1 = COPY %vreg2<undef>
888 /// We delete the copy and remove the corresponding value number from %vreg1.
889 /// Any uses of that value number are marked as <undef>.
890 bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI,
891 const CoalescerPair &CP) {
892 SlotIndex Idx = LIS->getInstructionIndex(CopyMI);
893 LiveInterval *SrcInt = &LIS->getInterval(CP.getSrcReg());
894 if (SrcInt->liveAt(Idx))
896 LiveInterval *DstInt = &LIS->getInterval(CP.getDstReg());
897 if (DstInt->liveAt(Idx))
900 // No intervals are live-in to CopyMI - it is undef.
905 VNInfo *DeadVNI = DstInt->getVNInfoAt(Idx.getRegSlot());
906 assert(DeadVNI && "No value defined in DstInt");
907 DstInt->removeValNo(DeadVNI);
909 // Find new undef uses.
910 for (MachineRegisterInfo::reg_nodbg_iterator
911 I = MRI->reg_nodbg_begin(DstInt->reg), E = MRI->reg_nodbg_end();
913 MachineOperand &MO = I.getOperand();
914 if (MO.isDef() || MO.isUndef())
916 MachineInstr *MI = MO.getParent();
917 SlotIndex Idx = LIS->getInstructionIndex(MI);
918 if (DstInt->liveAt(Idx))
921 DEBUG(dbgs() << "\tnew undef: " << Idx << '\t' << *MI);
926 /// updateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
927 /// update the subregister number if it is not zero. If DstReg is a
928 /// physical register and the existing subregister number of the def / use
929 /// being updated is not zero, make sure to set it to the correct physical
931 void RegisterCoalescer::updateRegDefsUses(unsigned SrcReg,
934 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
935 LiveInterval &DstInt = LIS->getInterval(DstReg);
937 // Update LiveDebugVariables.
938 LDV->renameRegister(SrcReg, DstReg, SubIdx);
940 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(SrcReg);
941 MachineInstr *UseMI = I.skipInstruction();) {
942 bool AlreadyJoined = JoinedCopies.count(UseMI);
943 SmallVector<unsigned,8> Ops;
945 tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
947 // If SrcReg wasn't read, it may still be the case that DstReg is live-in
948 // because SrcReg is a sub-register.
949 if (!Reads && SubIdx && !AlreadyJoined)
950 Reads = DstInt.liveAt(LIS->getInstructionIndex(UseMI));
952 // Replace SrcReg with DstReg in all UseMI operands.
953 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
954 MachineOperand &MO = UseMI->getOperand(Ops[i]);
956 // Adjust <undef> flags in case of sub-register joins. We don't want to
957 // turn a full def into a read-modify-write sub-register def and vice
959 if (SubIdx && !AlreadyJoined && MO.isDef())
960 MO.setIsUndef(!Reads);
963 MO.substPhysReg(DstReg, *TRI);
965 MO.substVirtReg(DstReg, SubIdx, *TRI);
968 // This instruction is a copy that will be removed.
973 dbgs() << "\t\tupdated: ";
974 if (!UseMI->isDebugValue())
975 dbgs() << LIS->getInstructionIndex(UseMI) << "\t";
981 /// removeIntervalIfEmpty - Check if the live interval of a physical register
982 /// is empty, if so remove it and also remove the empty intervals of its
983 /// sub-registers. Return true if live interval is removed.
984 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *LIS,
985 const TargetRegisterInfo *TRI) {
987 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
988 for (const uint16_t* SR = TRI->getSubRegisters(li.reg); *SR; ++SR) {
989 if (!LIS->hasInterval(*SR))
991 LiveInterval &sli = LIS->getInterval(*SR);
993 LIS->removeInterval(*SR);
995 LIS->removeInterval(li.reg);
1001 /// removeDeadDef - If a def of a live interval is now determined dead, remove
1002 /// the val# it defines. If the live interval becomes empty, remove it as well.
1003 bool RegisterCoalescer::removeDeadDef(LiveInterval &li, MachineInstr *DefMI) {
1004 SlotIndex DefIdx = LIS->getInstructionIndex(DefMI).getRegSlot();
1005 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
1006 if (DefIdx != MLR->valno->def)
1008 li.removeValNo(MLR->valno);
1009 return removeIntervalIfEmpty(li, LIS, TRI);
1012 /// canJoinPhys - Return true if a copy involving a physreg should be joined.
1013 bool RegisterCoalescer::canJoinPhys(CoalescerPair &CP) {
1014 /// Always join simple intervals that are defined by a single copy from a
1015 /// reserved register. This doesn't increase register pressure, so it is
1016 /// always beneficial.
1017 if (!RegClassInfo.isReserved(CP.getDstReg())) {
1018 DEBUG(dbgs() << "\tCan only merge into reserved registers.\n");
1022 LiveInterval &JoinVInt = LIS->getInterval(CP.getSrcReg());
1023 if (CP.isFlipped() && JoinVInt.containsOneValue())
1026 DEBUG(dbgs() << "\tCannot join defs into reserved register.\n");
1030 /// joinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1031 /// which are the src/dst of the copy instruction CopyMI. This returns true
1032 /// if the copy was successfully coalesced away. If it is not currently
1033 /// possible to coalesce this interval, but it may be possible if other
1034 /// things get coalesced, then it returns true by reference in 'Again'.
1035 bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
1038 if (JoinedCopies.count(CopyMI))
1039 return false; // Already done.
1041 DEBUG(dbgs() << LIS->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
1043 CoalescerPair CP(*TII, *TRI);
1044 if (!CP.setRegisters(CopyMI)) {
1045 DEBUG(dbgs() << "\tNot coalescable.\n");
1049 // Dead code elimination. This really should be handled by MachineDCE, but
1050 // sometimes dead copies slip through, and we can't generate invalid live
1052 if (!CP.isPhys() && CopyMI->allDefsAreDead()) {
1053 DEBUG(dbgs() << "\tCopy is dead.\n");
1054 DeadDefs.push_back(CopyMI);
1055 eliminateDeadDefs();
1059 // If they are already joined we continue.
1060 if (CP.getSrcReg() == CP.getDstReg()) {
1061 DEBUG(dbgs() << "\tCopy already coalesced.\n");
1062 LIS->RemoveMachineInstrFromMaps(CopyMI);
1063 CopyMI->eraseFromParent();
1064 return false; // Not coalescable.
1067 // Eliminate undefs.
1068 if (!CP.isPhys() && eliminateUndefCopy(CopyMI, CP)) {
1069 DEBUG(dbgs() << "\tEliminated copy of <undef> value.\n");
1070 LIS->RemoveMachineInstrFromMaps(CopyMI);
1071 CopyMI->eraseFromParent();
1072 return false; // Not coalescable.
1075 // Enforce policies.
1077 DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), TRI)
1078 << " with " << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx())
1080 if (!canJoinPhys(CP)) {
1081 // Before giving up coalescing, if definition of source is defined by
1082 // trivial computation, try rematerializing it.
1083 if (!CP.isFlipped() &&
1084 reMaterializeTrivialDef(LIS->getInterval(CP.getSrcReg()),
1085 CP.getDstReg(), CopyMI))
1091 dbgs() << "\tConsidering merging to " << CP.getNewRC()->getName()
1093 if (CP.getDstIdx() && CP.getSrcIdx())
1094 dbgs() << PrintReg(CP.getDstReg()) << " in "
1095 << TRI->getSubRegIndexName(CP.getDstIdx()) << " and "
1096 << PrintReg(CP.getSrcReg()) << " in "
1097 << TRI->getSubRegIndexName(CP.getSrcIdx()) << '\n';
1099 dbgs() << PrintReg(CP.getSrcReg(), TRI) << " in "
1100 << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n';
1103 // When possible, let DstReg be the larger interval.
1104 if (!CP.isPartial() && LIS->getInterval(CP.getSrcReg()).ranges.size() >
1105 LIS->getInterval(CP.getDstReg()).ranges.size())
1109 // Okay, attempt to join these two intervals. On failure, this returns false.
1110 // Otherwise, if one of the intervals being joined is a physreg, this method
1111 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1112 // been modified, so we can use this information below to update aliases.
1113 if (!joinIntervals(CP)) {
1114 // Coalescing failed.
1116 // If definition of source is defined by trivial computation, try
1117 // rematerializing it.
1118 if (!CP.isFlipped() &&
1119 reMaterializeTrivialDef(LIS->getInterval(CP.getSrcReg()),
1120 CP.getDstReg(), CopyMI))
1123 // If we can eliminate the copy without merging the live ranges, do so now.
1124 if (!CP.isPartial()) {
1125 if (adjustCopiesBackFrom(CP, CopyMI) ||
1126 removeCopyByCommutingDef(CP, CopyMI)) {
1127 markAsJoined(CopyMI);
1128 DEBUG(dbgs() << "\tTrivial!\n");
1133 // Otherwise, we are unable to join the intervals.
1134 DEBUG(dbgs() << "\tInterference!\n");
1135 Again = true; // May be possible to coalesce later.
1139 // Coalescing to a virtual register that is of a sub-register class of the
1140 // other. Make sure the resulting register is set to the right register class.
1141 if (CP.isCrossClass()) {
1143 MRI->setRegClass(CP.getDstReg(), CP.getNewRC());
1146 // Removing sub-register copies can ease the register class constraints.
1147 // Make sure we attempt to inflate the register class of DstReg.
1148 if (!CP.isPhys() && RegClassInfo.isProperSubClass(CP.getNewRC()))
1149 InflateRegs.push_back(CP.getDstReg());
1151 // Remember to delete the copy instruction.
1152 markAsJoined(CopyMI);
1154 // Rewrite all SrcReg operands to DstReg.
1155 // Also update DstReg operands to include DstIdx if it is set.
1157 updateRegDefsUses(CP.getDstReg(), CP.getDstReg(), CP.getDstIdx());
1158 updateRegDefsUses(CP.getSrcReg(), CP.getDstReg(), CP.getSrcIdx());
1160 // SrcReg is guaranteed to be the register whose live interval that is
1162 LIS->removeInterval(CP.getSrcReg());
1164 // Update regalloc hint.
1165 TRI->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
1168 LiveInterval &DstInt = LIS->getInterval(CP.getDstReg());
1169 dbgs() << "\tJoined. Result = ";
1170 DstInt.print(dbgs(), TRI);
1178 /// Attempt joining with a reserved physreg.
1179 bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
1180 assert(CP.isPhys() && "Must be a physreg copy");
1181 assert(RegClassInfo.isReserved(CP.getDstReg()) && "Not a reserved register");
1182 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
1183 DEBUG({ dbgs() << "\t\tRHS = "; RHS.print(dbgs(), TRI); dbgs() << "\n"; });
1185 assert(CP.isFlipped() && RHS.containsOneValue() &&
1186 "Invalid join with reserved register");
1188 // Optimization for reserved registers like ESP. We can only merge with a
1189 // reserved physreg if RHS has a single value that is a copy of CP.DstReg().
1190 // The live range of the reserved register will look like a set of dead defs
1191 // - we don't properly track the live range of reserved registers.
1193 // Deny any overlapping intervals. This depends on all the reserved
1194 // register live ranges to look like dead defs.
1195 for (const uint16_t *AS = TRI->getOverlaps(CP.getDstReg()); *AS; ++AS) {
1196 if (!LIS->hasInterval(*AS)) {
1197 // Make sure at least DstReg itself exists before attempting a join.
1198 if (*AS == CP.getDstReg())
1199 LIS->getOrCreateInterval(CP.getDstReg());
1202 if (RHS.overlaps(LIS->getInterval(*AS))) {
1203 DEBUG(dbgs() << "\t\tInterference: " << PrintReg(*AS, TRI) << '\n');
1207 // Skip any value computations, we are not adding new values to the
1208 // reserved register. Also skip merging the live ranges, the reserved
1209 // register live range doesn't need to be accurate as long as all the
1214 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1215 /// compute what the resultant value numbers for each value in the input two
1216 /// ranges will be. This is complicated by copies between the two which can
1217 /// and will commonly cause multiple value numbers to be merged into one.
1219 /// VN is the value number that we're trying to resolve. InstDefiningValue
1220 /// keeps track of the new InstDefiningValue assignment for the result
1221 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1222 /// whether a value in this or other is a copy from the opposite set.
1223 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1224 /// already been assigned.
1226 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1227 /// contains the value number the copy is from.
1229 static unsigned ComputeUltimateVN(VNInfo *VNI,
1230 SmallVector<VNInfo*, 16> &NewVNInfo,
1231 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1232 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1233 SmallVector<int, 16> &ThisValNoAssignments,
1234 SmallVector<int, 16> &OtherValNoAssignments) {
1235 unsigned VN = VNI->id;
1237 // If the VN has already been computed, just return it.
1238 if (ThisValNoAssignments[VN] >= 0)
1239 return ThisValNoAssignments[VN];
1240 assert(ThisValNoAssignments[VN] != -2 && "Cyclic value numbers");
1242 // If this val is not a copy from the other val, then it must be a new value
1243 // number in the destination.
1244 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1245 if (I == ThisFromOther.end()) {
1246 NewVNInfo.push_back(VNI);
1247 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1249 VNInfo *OtherValNo = I->second;
1251 // Otherwise, this *is* a copy from the RHS. If the other side has already
1252 // been computed, return it.
1253 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1254 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1256 // Mark this value number as currently being computed, then ask what the
1257 // ultimate value # of the other value is.
1258 ThisValNoAssignments[VN] = -2;
1259 unsigned UltimateVN =
1260 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1261 OtherValNoAssignments, ThisValNoAssignments);
1262 return ThisValNoAssignments[VN] = UltimateVN;
1266 // Find out if we have something like
1269 // if so, we can pretend this is actually
1272 // which allows us to coalesce A and B.
1273 // VNI is the definition of B. LR is the life range of A that includes
1274 // the slot just before B. If we return true, we add "B = X" to DupCopies.
1275 // This implies that A dominates B.
1276 static bool RegistersDefinedFromSameValue(LiveIntervals &li,
1277 const TargetRegisterInfo &tri,
1281 SmallVector<MachineInstr*, 8> &DupCopies) {
1282 // FIXME: This is very conservative. For example, we don't handle
1283 // physical registers.
1285 MachineInstr *MI = li.getInstructionFromIndex(VNI->def);
1287 if (!MI || !MI->isFullCopy() || CP.isPartial() || CP.isPhys())
1290 unsigned Dst = MI->getOperand(0).getReg();
1291 unsigned Src = MI->getOperand(1).getReg();
1293 if (!TargetRegisterInfo::isVirtualRegister(Src) ||
1294 !TargetRegisterInfo::isVirtualRegister(Dst))
1297 unsigned A = CP.getDstReg();
1298 unsigned B = CP.getSrcReg();
1304 VNInfo *Other = LR->valno;
1305 const MachineInstr *OtherMI = li.getInstructionFromIndex(Other->def);
1307 if (!OtherMI || !OtherMI->isFullCopy())
1310 unsigned OtherDst = OtherMI->getOperand(0).getReg();
1311 unsigned OtherSrc = OtherMI->getOperand(1).getReg();
1313 if (!TargetRegisterInfo::isVirtualRegister(OtherSrc) ||
1314 !TargetRegisterInfo::isVirtualRegister(OtherDst))
1317 assert(OtherDst == B);
1319 if (Src != OtherSrc)
1322 // If the copies use two different value numbers of X, we cannot merge
1324 LiveInterval &SrcInt = li.getInterval(Src);
1325 // getVNInfoBefore returns NULL for undef copies. In this case, the
1326 // optimization is still safe.
1327 if (SrcInt.getVNInfoBefore(Other->def) != SrcInt.getVNInfoBefore(VNI->def))
1330 DupCopies.push_back(MI);
1335 /// joinIntervals - Attempt to join these two intervals. On failure, this
1337 bool RegisterCoalescer::joinIntervals(CoalescerPair &CP) {
1338 // Handle physreg joins separately.
1340 return joinReservedPhysReg(CP);
1342 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
1343 DEBUG({ dbgs() << "\t\tRHS = "; RHS.print(dbgs(), TRI); dbgs() << "\n"; });
1345 // Compute the final value assignment, assuming that the live ranges can be
1347 SmallVector<int, 16> LHSValNoAssignments;
1348 SmallVector<int, 16> RHSValNoAssignments;
1349 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
1350 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
1351 SmallVector<VNInfo*, 16> NewVNInfo;
1353 SmallVector<MachineInstr*, 8> DupCopies;
1355 LiveInterval &LHS = LIS->getOrCreateInterval(CP.getDstReg());
1356 DEBUG({ dbgs() << "\t\tLHS = "; LHS.print(dbgs(), TRI); dbgs() << "\n"; });
1358 // Loop over the value numbers of the LHS, seeing if any are defined from
1360 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1363 if (VNI->isUnused() || VNI->isPHIDef())
1365 MachineInstr *MI = LIS->getInstructionFromIndex(VNI->def);
1366 assert(MI && "Missing def");
1367 if (!MI->isCopyLike()) // Src not defined by a copy?
1370 // Figure out the value # from the RHS.
1371 LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot());
1372 // The copy could be to an aliased physreg.
1375 // DstReg is known to be a register in the LHS interval. If the src is
1376 // from the RHS interval, we can use its value #.
1377 if (!CP.isCoalescable(MI) &&
1378 !RegistersDefinedFromSameValue(*LIS, *TRI, CP, VNI, lr, DupCopies))
1381 LHSValsDefinedFromRHS[VNI] = lr->valno;
1384 // Loop over the value numbers of the RHS, seeing if any are defined from
1386 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1389 if (VNI->isUnused() || VNI->isPHIDef())
1391 MachineInstr *MI = LIS->getInstructionFromIndex(VNI->def);
1392 assert(MI && "Missing def");
1393 if (!MI->isCopyLike()) // Src not defined by a copy?
1396 // Figure out the value # from the LHS.
1397 LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot());
1398 // The copy could be to an aliased physreg.
1401 // DstReg is known to be a register in the RHS interval. If the src is
1402 // from the LHS interval, we can use its value #.
1403 if (!CP.isCoalescable(MI) &&
1404 !RegistersDefinedFromSameValue(*LIS, *TRI, CP, VNI, lr, DupCopies))
1407 RHSValsDefinedFromLHS[VNI] = lr->valno;
1410 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1411 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1412 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1414 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1417 unsigned VN = VNI->id;
1418 if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
1420 ComputeUltimateVN(VNI, NewVNInfo,
1421 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1422 LHSValNoAssignments, RHSValNoAssignments);
1424 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1427 unsigned VN = VNI->id;
1428 if (RHSValNoAssignments[VN] >= 0 || VNI->isUnused())
1430 // If this value number isn't a copy from the LHS, it's a new number.
1431 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
1432 NewVNInfo.push_back(VNI);
1433 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
1437 ComputeUltimateVN(VNI, NewVNInfo,
1438 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1439 RHSValNoAssignments, LHSValNoAssignments);
1442 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1443 // interval lists to see if these intervals are coalescable.
1444 LiveInterval::const_iterator I = LHS.begin();
1445 LiveInterval::const_iterator IE = LHS.end();
1446 LiveInterval::const_iterator J = RHS.begin();
1447 LiveInterval::const_iterator JE = RHS.end();
1449 // Skip ahead until the first place of potential sharing.
1450 if (I != IE && J != JE) {
1451 if (I->start < J->start) {
1452 I = std::upper_bound(I, IE, J->start);
1453 if (I != LHS.begin()) --I;
1454 } else if (J->start < I->start) {
1455 J = std::upper_bound(J, JE, I->start);
1456 if (J != RHS.begin()) --J;
1460 while (I != IE && J != JE) {
1461 // Determine if these two live ranges overlap.
1463 if (I->start < J->start) {
1464 Overlaps = I->end > J->start;
1466 Overlaps = J->end > I->start;
1469 // If so, check value # info to determine if they are really different.
1471 // If the live range overlap will map to the same value number in the
1472 // result liverange, we can still coalesce them. If not, we can't.
1473 if (LHSValNoAssignments[I->valno->id] !=
1474 RHSValNoAssignments[J->valno->id])
1478 if (I->end < J->end)
1484 // Update kill info. Some live ranges are extended due to copy coalescing.
1485 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
1486 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
1487 VNInfo *VNI = I->first;
1488 unsigned LHSValID = LHSValNoAssignments[VNI->id];
1489 if (VNI->hasPHIKill())
1490 NewVNInfo[LHSValID]->setHasPHIKill(true);
1493 // Update kill info. Some live ranges are extended due to copy coalescing.
1494 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
1495 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
1496 VNInfo *VNI = I->first;
1497 unsigned RHSValID = RHSValNoAssignments[VNI->id];
1498 if (VNI->hasPHIKill())
1499 NewVNInfo[RHSValID]->setHasPHIKill(true);
1502 if (LHSValNoAssignments.empty())
1503 LHSValNoAssignments.push_back(-1);
1504 if (RHSValNoAssignments.empty())
1505 RHSValNoAssignments.push_back(-1);
1507 SmallVector<unsigned, 8> SourceRegisters;
1508 for (SmallVector<MachineInstr*, 8>::iterator I = DupCopies.begin(),
1509 E = DupCopies.end(); I != E; ++I) {
1510 MachineInstr *MI = *I;
1512 // We have pretended that the assignment to B in
1515 // was actually a copy from A. Now that we decided to coalesce A and B,
1516 // transform the code into
1519 // and mark the X as coalesced to keep the illusion.
1520 unsigned Src = MI->getOperand(1).getReg();
1521 SourceRegisters.push_back(Src);
1522 MI->getOperand(0).substVirtReg(Src, 0, *TRI);
1527 // If B = X was the last use of X in a liverange, we have to shrink it now
1528 // that B = X is gone.
1529 for (SmallVector<unsigned, 8>::iterator I = SourceRegisters.begin(),
1530 E = SourceRegisters.end(); I != E; ++I) {
1531 LIS->shrinkToUses(&LIS->getInterval(*I));
1534 // If we get here, we know that we can coalesce the live ranges. Ask the
1535 // intervals to coalesce themselves now.
1536 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
1542 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1543 // depth of the basic block (the unsigned), and then on the MBB number.
1544 struct DepthMBBCompare {
1545 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1546 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1547 // Deeper loops first
1548 if (LHS.first != RHS.first)
1549 return LHS.first > RHS.first;
1551 // Prefer blocks that are more connected in the CFG. This takes care of
1552 // the most difficult copies first while intervals are short.
1553 unsigned cl = LHS.second->pred_size() + LHS.second->succ_size();
1554 unsigned cr = RHS.second->pred_size() + RHS.second->succ_size();
1558 // As a last resort, sort by block number.
1559 return LHS.second->getNumber() < RHS.second->getNumber();
1564 // Try joining WorkList copies starting from index From.
1565 // Null out any successful joins.
1566 bool RegisterCoalescer::copyCoalesceWorkList(unsigned From) {
1567 assert(From <= WorkList.size() && "Out of range");
1568 bool Progress = false;
1569 for (unsigned i = From, e = WorkList.size(); i != e; ++i) {
1572 // Skip instruction pointers that have already been erased, for example by
1573 // dead code elimination.
1574 if (ErasedInstrs.erase(WorkList[i])) {
1579 bool Success = joinCopy(WorkList[i], Again);
1580 Progress |= Success;
1581 if (Success || !Again)
1588 RegisterCoalescer::copyCoalesceInMBB(MachineBasicBlock *MBB) {
1589 DEBUG(dbgs() << MBB->getName() << ":\n");
1591 // Collect all copy-like instructions in MBB. Don't start coalescing anything
1592 // yet, it might invalidate the iterator.
1593 const unsigned PrevSize = WorkList.size();
1594 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1596 if (MII->isCopyLike())
1597 WorkList.push_back(MII);
1599 // Try coalescing the collected copies immediately, and remove the nulls.
1600 // This prevents the WorkList from getting too large since most copies are
1601 // joinable on the first attempt.
1602 if (copyCoalesceWorkList(PrevSize))
1603 WorkList.erase(std::remove(WorkList.begin() + PrevSize, WorkList.end(),
1604 (MachineInstr*)0), WorkList.end());
1607 void RegisterCoalescer::joinAllIntervals() {
1608 DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
1609 assert(WorkList.empty() && "Old data still around.");
1611 if (Loops->empty()) {
1612 // If there are no loops in the function, join intervals in function order.
1613 for (MachineFunction::iterator I = MF->begin(), E = MF->end();
1615 copyCoalesceInMBB(I);
1617 // Otherwise, join intervals in inner loops before other intervals.
1618 // Unfortunately we can't just iterate over loop hierarchy here because
1619 // there may be more MBB's than BB's. Collect MBB's for sorting.
1621 // Join intervals in the function prolog first. We want to join physical
1622 // registers with virtual registers before the intervals got too long.
1623 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
1624 for (MachineFunction::iterator I = MF->begin(), E = MF->end();I != E;++I){
1625 MachineBasicBlock *MBB = I;
1626 MBBs.push_back(std::make_pair(Loops->getLoopDepth(MBB), I));
1629 // Sort by loop depth.
1630 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1632 // Finally, join intervals in loop nest order.
1633 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1634 copyCoalesceInMBB(MBBs[i].second);
1637 // Joining intervals can allow other intervals to be joined. Iteratively join
1638 // until we make no progress.
1639 while (copyCoalesceWorkList())
1643 void RegisterCoalescer::releaseMemory() {
1644 JoinedCopies.clear();
1645 ErasedInstrs.clear();
1649 InflateRegs.clear();
1652 bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
1654 MRI = &fn.getRegInfo();
1655 TM = &fn.getTarget();
1656 TRI = TM->getRegisterInfo();
1657 TII = TM->getInstrInfo();
1658 LIS = &getAnalysis<LiveIntervals>();
1659 LDV = &getAnalysis<LiveDebugVariables>();
1660 AA = &getAnalysis<AliasAnalysis>();
1661 Loops = &getAnalysis<MachineLoopInfo>();
1663 DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
1664 << "********** Function: "
1665 << ((Value*)MF->getFunction())->getName() << '\n');
1667 if (VerifyCoalescing)
1668 MF->verify(this, "Before register coalescing");
1670 RegClassInfo.runOnMachineFunction(fn);
1672 // Join (coalesce) intervals if requested.
1673 if (EnableJoining) {
1676 dbgs() << "********** INTERVALS POST JOINING **********\n";
1677 for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end();
1679 I->second->print(dbgs(), TRI);
1685 // Perform a final pass over the instructions and compute spill weights
1686 // and remove identity moves.
1687 SmallVector<unsigned, 4> DeadDefs;
1688 for (MachineFunction::iterator mbbi = MF->begin(), mbbe = MF->end();
1689 mbbi != mbbe; ++mbbi) {
1690 MachineBasicBlock* mbb = mbbi;
1691 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
1693 MachineInstr *MI = mii;
1694 if (JoinedCopies.count(MI)) {
1695 // Delete all coalesced copies.
1696 bool DoDelete = true;
1697 assert(MI->isCopyLike() && "Unrecognized copy instruction");
1698 unsigned SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg();
1700 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
1701 MI->getNumOperands() > 2)
1702 // Do not delete extract_subreg, insert_subreg of physical
1703 // registers unless the definition is dead. e.g.
1704 // %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
1705 // or else the scavenger may complain. LowerSubregs will
1706 // delete them later.
1709 if (MI->allDefsAreDead()) {
1710 if (TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1711 LIS->hasInterval(SrcReg))
1712 LIS->shrinkToUses(&LIS->getInterval(SrcReg));
1716 // We need the instruction to adjust liveness, so make it a KILL.
1717 if (MI->isSubregToReg()) {
1718 MI->RemoveOperand(3);
1719 MI->RemoveOperand(1);
1721 MI->setDesc(TII->get(TargetOpcode::KILL));
1722 mii = llvm::next(mii);
1724 LIS->RemoveMachineInstrFromMaps(MI);
1725 mii = mbbi->erase(mii);
1731 // Now check if this is a remat'ed def instruction which is now dead.
1732 if (ReMatDefs.count(MI)) {
1734 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1735 const MachineOperand &MO = MI->getOperand(i);
1738 unsigned Reg = MO.getReg();
1741 DeadDefs.push_back(Reg);
1744 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
1745 !MRI->use_nodbg_empty(Reg)) {
1751 while (!DeadDefs.empty()) {
1752 unsigned DeadDef = DeadDefs.back();
1753 DeadDefs.pop_back();
1754 removeDeadDef(LIS->getInterval(DeadDef), MI);
1756 LIS->RemoveMachineInstrFromMaps(mii);
1757 mii = mbbi->erase(mii);
1765 // Check for now unnecessary kill flags.
1766 if (LIS->isNotInMIMap(MI)) continue;
1767 SlotIndex DefIdx = LIS->getInstructionIndex(MI).getRegSlot();
1768 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1769 MachineOperand &MO = MI->getOperand(i);
1770 if (!MO.isReg() || !MO.isKill()) continue;
1771 unsigned reg = MO.getReg();
1772 if (!reg || !LIS->hasInterval(reg)) continue;
1773 if (!LIS->getInterval(reg).killedAt(DefIdx)) {
1774 MO.setIsKill(false);
1777 // When leaving a kill flag on a physreg, check if any subregs should
1779 if (!TargetRegisterInfo::isPhysicalRegister(reg))
1781 for (const uint16_t *SR = TRI->getSubRegisters(reg);
1782 unsigned S = *SR; ++SR)
1783 if (LIS->hasInterval(S) && LIS->getInterval(S).liveAt(DefIdx))
1784 MI->addRegisterDefined(S, TRI);
1789 // After deleting a lot of copies, register classes may be less constrained.
1790 // Removing sub-register operands may allow GR32_ABCD -> GR32 and DPR_VFP2 ->
1792 array_pod_sort(InflateRegs.begin(), InflateRegs.end());
1793 InflateRegs.erase(std::unique(InflateRegs.begin(), InflateRegs.end()),
1795 DEBUG(dbgs() << "Trying to inflate " << InflateRegs.size() << " regs.\n");
1796 for (unsigned i = 0, e = InflateRegs.size(); i != e; ++i) {
1797 unsigned Reg = InflateRegs[i];
1798 if (MRI->reg_nodbg_empty(Reg))
1800 if (MRI->recomputeRegClass(Reg, *TM)) {
1801 DEBUG(dbgs() << PrintReg(Reg) << " inflated to "
1802 << MRI->getRegClass(Reg)->getName() << '\n');
1809 if (VerifyCoalescing)
1810 MF->verify(this, "After register coalescing");
1814 /// print - Implement the dump method.
1815 void RegisterCoalescer::print(raw_ostream &O, const Module* m) const {