1 //===- RegisterCoalescer.cpp - Generic Register Coalescing Interface -------==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the generic RegisterCoalescer interface which
11 // is used as the common interface used by all clients and
12 // implementations of register coalescing.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "regalloc"
17 #include "RegisterCoalescer.h"
18 #include "llvm/ADT/OwningPtr.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/Analysis/AliasAnalysis.h"
23 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
24 #include "llvm/CodeGen/LiveRangeEdit.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/MachineLoopInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/CodeGen/RegisterClassInfo.h"
31 #include "llvm/CodeGen/VirtRegMap.h"
32 #include "llvm/IR/Value.h"
33 #include "llvm/Pass.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetSubtargetInfo.h"
46 STATISTIC(numJoins , "Number of interval joins performed");
47 STATISTIC(numCrossRCs , "Number of cross class joins performed");
48 STATISTIC(numCommutes , "Number of instruction commuting performed");
49 STATISTIC(numExtends , "Number of copies extended");
50 STATISTIC(NumReMats , "Number of instructions re-materialized");
51 STATISTIC(NumInflated , "Number of register classes inflated");
52 STATISTIC(NumLaneConflicts, "Number of dead lane conflicts tested");
53 STATISTIC(NumLaneResolves, "Number of dead lane conflicts resolved");
56 EnableJoining("join-liveintervals",
57 cl::desc("Coalesce copies (default=true)"),
60 // Temporary flag to test critical edge unsplitting.
62 EnableJoinSplits("join-splitedges",
63 cl::desc("Coalesce copies on split edges (default=subtarget)"), cl::Hidden);
65 // Temporary flag to test global copy optimization.
66 static cl::opt<cl::boolOrDefault>
67 EnableGlobalCopies("join-globalcopies",
68 cl::desc("Coalesce copies that span blocks (default=subtarget)"),
69 cl::init(cl::BOU_UNSET), cl::Hidden);
72 VerifyCoalescing("verify-coalescing",
73 cl::desc("Verify machine instrs before and after register coalescing"),
77 class RegisterCoalescer : public MachineFunctionPass,
78 private LiveRangeEdit::Delegate {
80 MachineRegisterInfo* MRI;
81 const TargetMachine* TM;
82 const TargetRegisterInfo* TRI;
83 const TargetInstrInfo* TII;
85 const MachineLoopInfo* Loops;
87 RegisterClassInfo RegClassInfo;
89 /// \brief True if the coalescer should aggressively coalesce global copies
90 /// in favor of keeping local copies.
91 bool JoinGlobalCopies;
93 /// \brief True if the coalescer should aggressively coalesce fall-thru
94 /// blocks exclusively containing copies.
97 /// WorkList - Copy instructions yet to be coalesced.
98 SmallVector<MachineInstr*, 8> WorkList;
99 SmallVector<MachineInstr*, 8> LocalWorkList;
101 /// ErasedInstrs - Set of instruction pointers that have been erased, and
102 /// that may be present in WorkList.
103 SmallPtrSet<MachineInstr*, 8> ErasedInstrs;
105 /// Dead instructions that are about to be deleted.
106 SmallVector<MachineInstr*, 8> DeadDefs;
108 /// Virtual registers to be considered for register class inflation.
109 SmallVector<unsigned, 8> InflateRegs;
111 /// Recursively eliminate dead defs in DeadDefs.
112 void eliminateDeadDefs();
114 /// LiveRangeEdit callback.
115 void LRE_WillEraseInstruction(MachineInstr *MI);
117 /// coalesceLocals - coalesce the LocalWorkList.
118 void coalesceLocals();
120 /// joinAllIntervals - join compatible live intervals
121 void joinAllIntervals();
123 /// copyCoalesceInMBB - Coalesce copies in the specified MBB, putting
124 /// copies that cannot yet be coalesced into WorkList.
125 void copyCoalesceInMBB(MachineBasicBlock *MBB);
127 /// copyCoalesceWorkList - Try to coalesce all copies in CurrList. Return
128 /// true if any progress was made.
129 bool copyCoalesceWorkList(MutableArrayRef<MachineInstr*> CurrList);
131 /// joinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
132 /// which are the src/dst of the copy instruction CopyMI. This returns
133 /// true if the copy was successfully coalesced away. If it is not
134 /// currently possible to coalesce this interval, but it may be possible if
135 /// other things get coalesced, then it returns true by reference in
137 bool joinCopy(MachineInstr *TheCopy, bool &Again);
139 /// joinIntervals - Attempt to join these two intervals. On failure, this
140 /// returns false. The output "SrcInt" will not have been modified, so we
141 /// can use this information below to update aliases.
142 bool joinIntervals(CoalescerPair &CP);
144 /// Attempt joining two virtual registers. Return true on success.
145 bool joinVirtRegs(CoalescerPair &CP);
147 /// Attempt joining with a reserved physreg.
148 bool joinReservedPhysReg(CoalescerPair &CP);
150 /// adjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
151 /// the source value number is defined by a copy from the destination reg
152 /// see if we can merge these two destination reg valno# into a single
153 /// value number, eliminating a copy.
154 bool adjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
156 /// hasOtherReachingDefs - Return true if there are definitions of IntB
157 /// other than BValNo val# that can reach uses of AValno val# of IntA.
158 bool hasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
159 VNInfo *AValNo, VNInfo *BValNo);
161 /// removeCopyByCommutingDef - We found a non-trivially-coalescable copy.
162 /// If the source value number is defined by a commutable instruction and
163 /// its other operand is coalesced to the copy dest register, see if we
164 /// can transform the copy into a noop by commuting the definition.
165 bool removeCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI);
167 /// reMaterializeTrivialDef - If the source of a copy is defined by a
168 /// trivial computation, replace the copy by rematerialize the definition.
169 bool reMaterializeTrivialDef(CoalescerPair &CP, MachineInstr *CopyMI,
172 /// canJoinPhys - Return true if a physreg copy should be joined.
173 bool canJoinPhys(const CoalescerPair &CP);
175 /// updateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
176 /// update the subregister number if it is not zero. If DstReg is a
177 /// physical register and the existing subregister number of the def / use
178 /// being updated is not zero, make sure to set it to the correct physical
180 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
182 /// eliminateUndefCopy - Handle copies of undef values.
183 bool eliminateUndefCopy(MachineInstr *CopyMI, const CoalescerPair &CP);
186 static char ID; // Class identification, replacement for typeinfo
187 RegisterCoalescer() : MachineFunctionPass(ID) {
188 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
191 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
193 virtual void releaseMemory();
195 /// runOnMachineFunction - pass entry point
196 virtual bool runOnMachineFunction(MachineFunction&);
198 /// print - Implement the dump method.
199 virtual void print(raw_ostream &O, const Module* = 0) const;
201 } /// end anonymous namespace
203 char &llvm::RegisterCoalescerID = RegisterCoalescer::ID;
205 INITIALIZE_PASS_BEGIN(RegisterCoalescer, "simple-register-coalescing",
206 "Simple Register Coalescing", false, false)
207 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
208 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
209 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
210 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
211 INITIALIZE_PASS_END(RegisterCoalescer, "simple-register-coalescing",
212 "Simple Register Coalescing", false, false)
214 char RegisterCoalescer::ID = 0;
216 static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI,
217 unsigned &Src, unsigned &Dst,
218 unsigned &SrcSub, unsigned &DstSub) {
220 Dst = MI->getOperand(0).getReg();
221 DstSub = MI->getOperand(0).getSubReg();
222 Src = MI->getOperand(1).getReg();
223 SrcSub = MI->getOperand(1).getSubReg();
224 } else if (MI->isSubregToReg()) {
225 Dst = MI->getOperand(0).getReg();
226 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(),
227 MI->getOperand(3).getImm());
228 Src = MI->getOperand(2).getReg();
229 SrcSub = MI->getOperand(2).getSubReg();
235 // Return true if this block should be vacated by the coalescer to eliminate
236 // branches. The important cases to handle in the coalescer are critical edges
237 // split during phi elimination which contain only copies. Simple blocks that
238 // contain non-branches should also be vacated, but this can be handled by an
239 // earlier pass similar to early if-conversion.
240 static bool isSplitEdge(const MachineBasicBlock *MBB) {
241 if (MBB->pred_size() != 1 || MBB->succ_size() != 1)
244 for (MachineBasicBlock::const_iterator MII = MBB->begin(), E = MBB->end();
246 if (!MII->isCopyLike() && !MII->isUnconditionalBranch())
252 bool CoalescerPair::setRegisters(const MachineInstr *MI) {
256 Flipped = CrossClass = false;
258 unsigned Src, Dst, SrcSub, DstSub;
259 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
261 Partial = SrcSub || DstSub;
263 // If one register is a physreg, it must be Dst.
264 if (TargetRegisterInfo::isPhysicalRegister(Src)) {
265 if (TargetRegisterInfo::isPhysicalRegister(Dst))
268 std::swap(SrcSub, DstSub);
272 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
274 if (TargetRegisterInfo::isPhysicalRegister(Dst)) {
275 // Eliminate DstSub on a physreg.
277 Dst = TRI.getSubReg(Dst, DstSub);
278 if (!Dst) return false;
282 // Eliminate SrcSub by picking a corresponding Dst superregister.
284 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
285 if (!Dst) return false;
287 } else if (!MRI.getRegClass(Src)->contains(Dst)) {
291 // Both registers are virtual.
292 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
293 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
295 // Both registers have subreg indices.
296 if (SrcSub && DstSub) {
297 // Copies between different sub-registers are never coalescable.
298 if (Src == Dst && SrcSub != DstSub)
301 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
306 // SrcReg will be merged with a sub-register of DstReg.
308 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
310 // DstReg will be merged with a sub-register of SrcReg.
312 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
314 // This is a straight copy without sub-registers.
315 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
318 // The combined constraint may be impossible to satisfy.
322 // Prefer SrcReg to be a sub-register of DstReg.
323 // FIXME: Coalescer should support subregs symmetrically.
324 if (DstIdx && !SrcIdx) {
326 std::swap(SrcIdx, DstIdx);
330 CrossClass = NewRC != DstRC || NewRC != SrcRC;
332 // Check our invariants
333 assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual");
334 assert(!(TargetRegisterInfo::isPhysicalRegister(Dst) && DstSub) &&
335 "Cannot have a physical SubIdx");
341 bool CoalescerPair::flip() {
342 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
344 std::swap(SrcReg, DstReg);
345 std::swap(SrcIdx, DstIdx);
350 bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
353 unsigned Src, Dst, SrcSub, DstSub;
354 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
357 // Find the virtual register that is SrcReg.
360 std::swap(SrcSub, DstSub);
361 } else if (Src != SrcReg) {
365 // Now check that Dst matches DstReg.
366 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
367 if (!TargetRegisterInfo::isPhysicalRegister(Dst))
369 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state.");
370 // DstSub could be set for a physreg from INSERT_SUBREG.
372 Dst = TRI.getSubReg(Dst, DstSub);
375 return DstReg == Dst;
376 // This is a partial register copy. Check that the parts match.
377 return TRI.getSubReg(DstReg, SrcSub) == Dst;
379 // DstReg is virtual.
382 // Registers match, do the subregisters line up?
383 return TRI.composeSubRegIndices(SrcIdx, SrcSub) ==
384 TRI.composeSubRegIndices(DstIdx, DstSub);
388 void RegisterCoalescer::getAnalysisUsage(AnalysisUsage &AU) const {
389 AU.setPreservesCFG();
390 AU.addRequired<AliasAnalysis>();
391 AU.addRequired<LiveIntervals>();
392 AU.addPreserved<LiveIntervals>();
393 AU.addPreserved<SlotIndexes>();
394 AU.addRequired<MachineLoopInfo>();
395 AU.addPreserved<MachineLoopInfo>();
396 AU.addPreservedID(MachineDominatorsID);
397 MachineFunctionPass::getAnalysisUsage(AU);
400 void RegisterCoalescer::eliminateDeadDefs() {
401 SmallVector<unsigned, 8> NewRegs;
402 LiveRangeEdit(0, NewRegs, *MF, *LIS, 0, this).eliminateDeadDefs(DeadDefs);
405 // Callback from eliminateDeadDefs().
406 void RegisterCoalescer::LRE_WillEraseInstruction(MachineInstr *MI) {
407 // MI may be in WorkList. Make sure we don't visit it.
408 ErasedInstrs.insert(MI);
411 /// adjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
412 /// being the source and IntB being the dest, thus this defines a value number
413 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
414 /// see if we can merge these two pieces of B into a single value number,
415 /// eliminating a copy. For example:
419 /// B1 = A3 <- this copy
421 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
422 /// value number to be replaced with B0 (which simplifies the B liveinterval).
424 /// This returns true if an interval was modified.
426 bool RegisterCoalescer::adjustCopiesBackFrom(const CoalescerPair &CP,
427 MachineInstr *CopyMI) {
428 assert(!CP.isPartial() && "This doesn't work for partial copies.");
429 assert(!CP.isPhys() && "This doesn't work for physreg copies.");
432 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
434 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
435 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
437 // BValNo is a value number in B that is defined by a copy from A. 'B1' in
438 // the example above.
439 LiveInterval::iterator BS = IntB.FindSegmentContaining(CopyIdx);
440 if (BS == IntB.end()) return false;
441 VNInfo *BValNo = BS->valno;
443 // Get the location that B is defined at. Two options: either this value has
444 // an unknown definition point or it is defined at CopyIdx. If unknown, we
446 if (BValNo->def != CopyIdx) return false;
448 // AValNo is the value number in A that defines the copy, A3 in the example.
449 SlotIndex CopyUseIdx = CopyIdx.getRegSlot(true);
450 LiveInterval::iterator AS = IntA.FindSegmentContaining(CopyUseIdx);
451 // The live segment might not exist after fun with physreg coalescing.
452 if (AS == IntA.end()) return false;
453 VNInfo *AValNo = AS->valno;
455 // If AValNo is defined as a copy from IntB, we can potentially process this.
456 // Get the instruction that defines this value number.
457 MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def);
458 // Don't allow any partial copies, even if isCoalescable() allows them.
459 if (!CP.isCoalescable(ACopyMI) || !ACopyMI->isFullCopy())
462 // Get the Segment in IntB that this value number starts with.
463 LiveInterval::iterator ValS =
464 IntB.FindSegmentContaining(AValNo->def.getPrevSlot());
465 if (ValS == IntB.end())
468 // Make sure that the end of the live segment is inside the same block as
470 MachineInstr *ValSEndInst =
471 LIS->getInstructionFromIndex(ValS->end.getPrevSlot());
472 if (!ValSEndInst || ValSEndInst->getParent() != CopyMI->getParent())
475 // Okay, we now know that ValS ends in the same block that the CopyMI
476 // live-range starts. If there are no intervening live segments between them
477 // in IntB, we can merge them.
478 if (ValS+1 != BS) return false;
480 DEBUG(dbgs() << "Extending: " << PrintReg(IntB.reg, TRI));
482 SlotIndex FillerStart = ValS->end, FillerEnd = BS->start;
483 // We are about to delete CopyMI, so need to remove it as the 'instruction
484 // that defines this value #'. Update the valnum with the new defining
486 BValNo->def = FillerStart;
488 // Okay, we can merge them. We need to insert a new liverange:
489 // [ValS.end, BS.begin) of either value number, then we merge the
490 // two value numbers.
491 IntB.addSegment(LiveInterval::Segment(FillerStart, FillerEnd, BValNo));
493 // Okay, merge "B1" into the same value number as "B0".
494 if (BValNo != ValS->valno)
495 IntB.MergeValueNumberInto(BValNo, ValS->valno);
496 DEBUG(dbgs() << " result = " << IntB << '\n');
498 // If the source instruction was killing the source register before the
499 // merge, unset the isKill marker given the live range has been extended.
500 int UIdx = ValSEndInst->findRegisterUseOperandIdx(IntB.reg, true);
502 ValSEndInst->getOperand(UIdx).setIsKill(false);
505 // Rewrite the copy. If the copy instruction was killing the destination
506 // register before the merge, find the last use and trim the live range. That
507 // will also add the isKill marker.
508 CopyMI->substituteRegister(IntA.reg, IntB.reg, 0, *TRI);
509 if (AS->end == CopyIdx)
510 LIS->shrinkToUses(&IntA);
516 /// hasOtherReachingDefs - Return true if there are definitions of IntB
517 /// other than BValNo val# that can reach uses of AValno val# of IntA.
518 bool RegisterCoalescer::hasOtherReachingDefs(LiveInterval &IntA,
522 // If AValNo has PHI kills, conservatively assume that IntB defs can reach
524 if (LIS->hasPHIKill(IntA, AValNo))
527 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
529 if (AI->valno != AValNo) continue;
530 LiveInterval::iterator BI =
531 std::upper_bound(IntB.begin(), IntB.end(), AI->start);
532 if (BI != IntB.begin())
534 for (; BI != IntB.end() && AI->end >= BI->start; ++BI) {
535 if (BI->valno == BValNo)
537 if (BI->start <= AI->start && BI->end > AI->start)
539 if (BI->start > AI->start && BI->start < AI->end)
546 /// removeCopyByCommutingDef - We found a non-trivially-coalescable copy with
547 /// IntA being the source and IntB being the dest, thus this defines a value
548 /// number in IntB. If the source value number (in IntA) is defined by a
549 /// commutable instruction and its other operand is coalesced to the copy dest
550 /// register, see if we can transform the copy into a noop by commuting the
551 /// definition. For example,
553 /// A3 = op A2 B0<kill>
555 /// B1 = A3 <- this copy
557 /// = op A3 <- more uses
561 /// B2 = op B0 A2<kill>
563 /// B1 = B2 <- now an identify copy
565 /// = op B2 <- more uses
567 /// This returns true if an interval was modified.
569 bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
570 MachineInstr *CopyMI) {
571 assert (!CP.isPhys());
573 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
576 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
578 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
580 // BValNo is a value number in B that is defined by a copy from A. 'B1' in
581 // the example above.
582 VNInfo *BValNo = IntB.getVNInfoAt(CopyIdx);
583 if (!BValNo || BValNo->def != CopyIdx)
586 // AValNo is the value number in A that defines the copy, A3 in the example.
587 VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx.getRegSlot(true));
588 assert(AValNo && "COPY source not live");
589 if (AValNo->isPHIDef() || AValNo->isUnused())
591 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
594 if (!DefMI->isCommutable())
596 // If DefMI is a two-address instruction then commuting it will change the
597 // destination register.
598 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
599 assert(DefIdx != -1);
601 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
603 unsigned Op1, Op2, NewDstIdx;
604 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
608 else if (Op2 == UseOpIdx)
613 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
614 unsigned NewReg = NewDstMO.getReg();
615 if (NewReg != IntB.reg || !IntB.Query(AValNo->def).isKill())
618 // Make sure there are no other definitions of IntB that would reach the
619 // uses which the new definition can reach.
620 if (hasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
623 // If some of the uses of IntA.reg is already coalesced away, return false.
624 // It's not possible to determine whether it's safe to perform the coalescing.
625 for (MachineRegisterInfo::use_nodbg_iterator UI =
626 MRI->use_nodbg_begin(IntA.reg),
627 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
628 MachineInstr *UseMI = &*UI;
629 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI);
630 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx);
631 if (US == IntA.end() || US->valno != AValNo)
633 // If this use is tied to a def, we can't rewrite the register.
634 if (UseMI->isRegTiedToDefOperand(UI.getOperandNo()))
638 DEBUG(dbgs() << "\tremoveCopyByCommutingDef: " << AValNo->def << '\t'
641 // At this point we have decided that it is legal to do this
642 // transformation. Start by commuting the instruction.
643 MachineBasicBlock *MBB = DefMI->getParent();
644 MachineInstr *NewMI = TII->commuteInstruction(DefMI);
647 if (TargetRegisterInfo::isVirtualRegister(IntA.reg) &&
648 TargetRegisterInfo::isVirtualRegister(IntB.reg) &&
649 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
651 if (NewMI != DefMI) {
652 LIS->ReplaceMachineInstrInMaps(DefMI, NewMI);
653 MachineBasicBlock::iterator Pos = DefMI;
654 MBB->insert(Pos, NewMI);
657 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
658 NewMI->getOperand(OpIdx).setIsKill();
660 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
669 // Update uses of IntA of the specific Val# with IntB.
670 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(IntA.reg),
671 UE = MRI->use_end(); UI != UE;) {
672 MachineOperand &UseMO = UI.getOperand();
673 MachineInstr *UseMI = &*UI;
675 if (UseMI->isDebugValue()) {
676 // FIXME These don't have an instruction index. Not clear we have enough
677 // info to decide whether to do this replacement or not. For now do it.
678 UseMO.setReg(NewReg);
681 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true);
682 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx);
683 if (US == IntA.end() || US->valno != AValNo)
685 // Kill flags are no longer accurate. They are recomputed after RA.
686 UseMO.setIsKill(false);
687 if (TargetRegisterInfo::isPhysicalRegister(NewReg))
688 UseMO.substPhysReg(NewReg, *TRI);
690 UseMO.setReg(NewReg);
693 if (!UseMI->isCopy())
695 if (UseMI->getOperand(0).getReg() != IntB.reg ||
696 UseMI->getOperand(0).getSubReg())
699 // This copy will become a noop. If it's defining a new val#, merge it into
701 SlotIndex DefIdx = UseIdx.getRegSlot();
702 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
705 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
706 assert(DVNI->def == DefIdx);
707 BValNo = IntB.MergeValueNumberInto(BValNo, DVNI);
708 ErasedInstrs.insert(UseMI);
709 LIS->RemoveMachineInstrFromMaps(UseMI);
710 UseMI->eraseFromParent();
713 // Extend BValNo by merging in IntA live segments of AValNo. Val# definition
715 VNInfo *ValNo = BValNo;
716 ValNo->def = AValNo->def;
717 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
719 if (AI->valno != AValNo) continue;
720 IntB.addSegment(LiveInterval::Segment(AI->start, AI->end, ValNo));
722 DEBUG(dbgs() << "\t\textended: " << IntB << '\n');
724 IntA.removeValNo(AValNo);
725 DEBUG(dbgs() << "\t\ttrimmed: " << IntA << '\n');
730 /// reMaterializeTrivialDef - If the source of a copy is defined by a trivial
731 /// computation, replace the copy by rematerialize the definition.
732 bool RegisterCoalescer::reMaterializeTrivialDef(CoalescerPair &CP,
733 MachineInstr *CopyMI,
736 unsigned SrcReg = CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg();
737 unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx();
738 unsigned DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg();
739 unsigned DstIdx = CP.isFlipped() ? CP.getSrcIdx() : CP.getDstIdx();
740 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
743 LiveInterval &SrcInt = LIS->getInterval(SrcReg);
744 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI);
745 VNInfo *ValNo = SrcInt.Query(CopyIdx).valueIn();
746 assert(ValNo && "CopyMI input register not live");
747 if (ValNo->isPHIDef() || ValNo->isUnused())
749 MachineInstr *DefMI = LIS->getInstructionFromIndex(ValNo->def);
752 if (DefMI->isCopyLike()) {
756 if (!DefMI->isAsCheapAsAMove())
758 if (!TII->isTriviallyReMaterializable(DefMI, AA))
760 bool SawStore = false;
761 if (!DefMI->isSafeToMove(TII, AA, SawStore))
763 const MCInstrDesc &MCID = DefMI->getDesc();
764 if (MCID.getNumDefs() != 1)
766 // Only support subregister destinations when the def is read-undef.
767 MachineOperand &DstOperand = CopyMI->getOperand(0);
768 unsigned CopyDstReg = DstOperand.getReg();
769 if (DstOperand.getSubReg() && !DstOperand.isUndef())
772 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF);
773 if (!DefMI->isImplicitDef()) {
774 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
775 unsigned NewDstReg = DstReg;
777 unsigned NewDstIdx = TRI->composeSubRegIndices(CP.getSrcIdx(),
778 DefMI->getOperand(0).getSubReg());
780 NewDstReg = TRI->getSubReg(DstReg, NewDstIdx);
782 // Finally, make sure that the physical subregister that will be
783 // constructed later is permitted for the instruction.
784 if (!DefRC->contains(NewDstReg))
787 // Theoretically, some stack frame reference could exist. Just make sure
788 // it hasn't actually happened.
789 assert(TargetRegisterInfo::isVirtualRegister(DstReg) &&
790 "Only expect to deal with virtual or physical registers");
794 MachineBasicBlock *MBB = CopyMI->getParent();
795 MachineBasicBlock::iterator MII =
796 llvm::next(MachineBasicBlock::iterator(CopyMI));
797 TII->reMaterialize(*MBB, MII, DstReg, SrcIdx, DefMI, *TRI);
798 MachineInstr *NewMI = prior(MII);
800 LIS->ReplaceMachineInstrInMaps(CopyMI, NewMI);
801 CopyMI->eraseFromParent();
802 ErasedInstrs.insert(CopyMI);
804 // NewMI may have dead implicit defs (E.g. EFLAGS for MOV<bits>r0 on X86).
805 // We need to remember these so we can add intervals once we insert
806 // NewMI into SlotIndexes.
807 SmallVector<unsigned, 4> NewMIImplDefs;
808 for (unsigned i = NewMI->getDesc().getNumOperands(),
809 e = NewMI->getNumOperands(); i != e; ++i) {
810 MachineOperand &MO = NewMI->getOperand(i);
812 assert(MO.isDef() && MO.isImplicit() && MO.isDead() &&
813 TargetRegisterInfo::isPhysicalRegister(MO.getReg()));
814 NewMIImplDefs.push_back(MO.getReg());
818 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
819 MRI->setRegClass(DstReg, CP.getNewRC());
821 unsigned NewIdx = NewMI->getOperand(0).getSubReg();
822 updateRegDefsUses(DstReg, DstReg, DstIdx);
823 NewMI->getOperand(0).setSubReg(NewIdx);
824 } else if (NewMI->getOperand(0).getReg() != CopyDstReg) {
825 // The New instruction may be defining a sub-register of what's actually
826 // been asked for. If so it must implicitly define the whole thing.
827 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
828 "Only expect virtual or physical registers in remat");
829 NewMI->getOperand(0).setIsDead(true);
830 NewMI->addOperand(MachineOperand::CreateReg(CopyDstReg,
836 if (NewMI->getOperand(0).getSubReg())
837 NewMI->getOperand(0).setIsUndef();
839 // CopyMI may have implicit operands, transfer them over to the newly
840 // rematerialized instruction. And update implicit def interval valnos.
841 for (unsigned i = CopyMI->getDesc().getNumOperands(),
842 e = CopyMI->getNumOperands(); i != e; ++i) {
843 MachineOperand &MO = CopyMI->getOperand(i);
845 assert(MO.isImplicit() && "No explicit operands after implict operands.");
846 // Discard VReg implicit defs.
847 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
848 NewMI->addOperand(MO);
853 SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
854 for (unsigned i = 0, e = NewMIImplDefs.size(); i != e; ++i) {
855 unsigned Reg = NewMIImplDefs[i];
856 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
857 if (LiveRange *LR = LIS->getCachedRegUnit(*Units))
858 LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());
861 DEBUG(dbgs() << "Remat: " << *NewMI);
864 // The source interval can become smaller because we removed a use.
865 LIS->shrinkToUses(&SrcInt, &DeadDefs);
866 if (!DeadDefs.empty())
872 /// eliminateUndefCopy - ProcessImpicitDefs may leave some copies of <undef>
873 /// values, it only removes local variables. When we have a copy like:
875 /// %vreg1 = COPY %vreg2<undef>
877 /// We delete the copy and remove the corresponding value number from %vreg1.
878 /// Any uses of that value number are marked as <undef>.
879 bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI,
880 const CoalescerPair &CP) {
881 SlotIndex Idx = LIS->getInstructionIndex(CopyMI);
882 LiveInterval *SrcInt = &LIS->getInterval(CP.getSrcReg());
883 if (SrcInt->liveAt(Idx))
885 LiveInterval *DstInt = &LIS->getInterval(CP.getDstReg());
886 if (DstInt->liveAt(Idx))
889 // No intervals are live-in to CopyMI - it is undef.
894 VNInfo *DeadVNI = DstInt->getVNInfoAt(Idx.getRegSlot());
895 assert(DeadVNI && "No value defined in DstInt");
896 DstInt->removeValNo(DeadVNI);
898 // Find new undef uses.
899 for (MachineRegisterInfo::reg_nodbg_iterator
900 I = MRI->reg_nodbg_begin(DstInt->reg), E = MRI->reg_nodbg_end();
902 MachineOperand &MO = I.getOperand();
903 if (MO.isDef() || MO.isUndef())
905 MachineInstr *MI = MO.getParent();
906 SlotIndex Idx = LIS->getInstructionIndex(MI);
907 if (DstInt->liveAt(Idx))
910 DEBUG(dbgs() << "\tnew undef: " << Idx << '\t' << *MI);
915 /// updateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
916 /// update the subregister number if it is not zero. If DstReg is a
917 /// physical register and the existing subregister number of the def / use
918 /// being updated is not zero, make sure to set it to the correct physical
920 void RegisterCoalescer::updateRegDefsUses(unsigned SrcReg,
923 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
924 LiveInterval *DstInt = DstIsPhys ? 0 : &LIS->getInterval(DstReg);
926 SmallPtrSet<MachineInstr*, 8> Visited;
927 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(SrcReg);
928 MachineInstr *UseMI = I.skipInstruction();) {
929 // Each instruction can only be rewritten once because sub-register
930 // composition is not always idempotent. When SrcReg != DstReg, rewriting
931 // the UseMI operands removes them from the SrcReg use-def chain, but when
932 // SrcReg is DstReg we could encounter UseMI twice if it has multiple
933 // operands mentioning the virtual register.
934 if (SrcReg == DstReg && !Visited.insert(UseMI))
937 SmallVector<unsigned,8> Ops;
939 tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
941 // If SrcReg wasn't read, it may still be the case that DstReg is live-in
942 // because SrcReg is a sub-register.
943 if (DstInt && !Reads && SubIdx)
944 Reads = DstInt->liveAt(LIS->getInstructionIndex(UseMI));
946 // Replace SrcReg with DstReg in all UseMI operands.
947 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
948 MachineOperand &MO = UseMI->getOperand(Ops[i]);
950 // Adjust <undef> flags in case of sub-register joins. We don't want to
951 // turn a full def into a read-modify-write sub-register def and vice
953 if (SubIdx && MO.isDef())
954 MO.setIsUndef(!Reads);
957 MO.substPhysReg(DstReg, *TRI);
959 MO.substVirtReg(DstReg, SubIdx, *TRI);
963 dbgs() << "\t\tupdated: ";
964 if (!UseMI->isDebugValue())
965 dbgs() << LIS->getInstructionIndex(UseMI) << "\t";
971 /// canJoinPhys - Return true if a copy involving a physreg should be joined.
972 bool RegisterCoalescer::canJoinPhys(const CoalescerPair &CP) {
973 /// Always join simple intervals that are defined by a single copy from a
974 /// reserved register. This doesn't increase register pressure, so it is
975 /// always beneficial.
976 if (!MRI->isReserved(CP.getDstReg())) {
977 DEBUG(dbgs() << "\tCan only merge into reserved registers.\n");
981 LiveInterval &JoinVInt = LIS->getInterval(CP.getSrcReg());
982 if (CP.isFlipped() && JoinVInt.containsOneValue())
985 DEBUG(dbgs() << "\tCannot join defs into reserved register.\n");
989 /// joinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
990 /// which are the src/dst of the copy instruction CopyMI. This returns true
991 /// if the copy was successfully coalesced away. If it is not currently
992 /// possible to coalesce this interval, but it may be possible if other
993 /// things get coalesced, then it returns true by reference in 'Again'.
994 bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
997 DEBUG(dbgs() << LIS->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
999 CoalescerPair CP(*TRI);
1000 if (!CP.setRegisters(CopyMI)) {
1001 DEBUG(dbgs() << "\tNot coalescable.\n");
1005 // Dead code elimination. This really should be handled by MachineDCE, but
1006 // sometimes dead copies slip through, and we can't generate invalid live
1008 if (!CP.isPhys() && CopyMI->allDefsAreDead()) {
1009 DEBUG(dbgs() << "\tCopy is dead.\n");
1010 DeadDefs.push_back(CopyMI);
1011 eliminateDeadDefs();
1015 // Eliminate undefs.
1016 if (!CP.isPhys() && eliminateUndefCopy(CopyMI, CP)) {
1017 DEBUG(dbgs() << "\tEliminated copy of <undef> value.\n");
1018 LIS->RemoveMachineInstrFromMaps(CopyMI);
1019 CopyMI->eraseFromParent();
1020 return false; // Not coalescable.
1023 // Coalesced copies are normally removed immediately, but transformations
1024 // like removeCopyByCommutingDef() can inadvertently create identity copies.
1025 // When that happens, just join the values and remove the copy.
1026 if (CP.getSrcReg() == CP.getDstReg()) {
1027 LiveInterval &LI = LIS->getInterval(CP.getSrcReg());
1028 DEBUG(dbgs() << "\tCopy already coalesced: " << LI << '\n');
1029 LiveQueryResult LRQ = LI.Query(LIS->getInstructionIndex(CopyMI));
1030 if (VNInfo *DefVNI = LRQ.valueDefined()) {
1031 VNInfo *ReadVNI = LRQ.valueIn();
1032 assert(ReadVNI && "No value before copy and no <undef> flag.");
1033 assert(ReadVNI != DefVNI && "Cannot read and define the same value.");
1034 LI.MergeValueNumberInto(DefVNI, ReadVNI);
1035 DEBUG(dbgs() << "\tMerged values: " << LI << '\n');
1037 LIS->RemoveMachineInstrFromMaps(CopyMI);
1038 CopyMI->eraseFromParent();
1042 // Enforce policies.
1044 DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), TRI)
1045 << " with " << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx())
1047 if (!canJoinPhys(CP)) {
1048 // Before giving up coalescing, if definition of source is defined by
1049 // trivial computation, try rematerializing it.
1051 if (reMaterializeTrivialDef(CP, CopyMI, IsDefCopy))
1054 Again = true; // May be possible to coalesce later.
1059 dbgs() << "\tConsidering merging to " << CP.getNewRC()->getName()
1061 if (CP.getDstIdx() && CP.getSrcIdx())
1062 dbgs() << PrintReg(CP.getDstReg()) << " in "
1063 << TRI->getSubRegIndexName(CP.getDstIdx()) << " and "
1064 << PrintReg(CP.getSrcReg()) << " in "
1065 << TRI->getSubRegIndexName(CP.getSrcIdx()) << '\n';
1067 dbgs() << PrintReg(CP.getSrcReg(), TRI) << " in "
1068 << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n';
1071 // When possible, let DstReg be the larger interval.
1072 if (!CP.isPartial() && LIS->getInterval(CP.getSrcReg()).size() >
1073 LIS->getInterval(CP.getDstReg()).size())
1077 // Okay, attempt to join these two intervals. On failure, this returns false.
1078 // Otherwise, if one of the intervals being joined is a physreg, this method
1079 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1080 // been modified, so we can use this information below to update aliases.
1081 if (!joinIntervals(CP)) {
1082 // Coalescing failed.
1084 // If definition of source is defined by trivial computation, try
1085 // rematerializing it.
1087 if (reMaterializeTrivialDef(CP, CopyMI, IsDefCopy))
1090 // If we can eliminate the copy without merging the live segments, do so
1092 if (!CP.isPartial() && !CP.isPhys()) {
1093 if (adjustCopiesBackFrom(CP, CopyMI) ||
1094 removeCopyByCommutingDef(CP, CopyMI)) {
1095 LIS->RemoveMachineInstrFromMaps(CopyMI);
1096 CopyMI->eraseFromParent();
1097 DEBUG(dbgs() << "\tTrivial!\n");
1102 // Otherwise, we are unable to join the intervals.
1103 DEBUG(dbgs() << "\tInterference!\n");
1104 Again = true; // May be possible to coalesce later.
1108 // Coalescing to a virtual register that is of a sub-register class of the
1109 // other. Make sure the resulting register is set to the right register class.
1110 if (CP.isCrossClass()) {
1112 MRI->setRegClass(CP.getDstReg(), CP.getNewRC());
1115 // Removing sub-register copies can ease the register class constraints.
1116 // Make sure we attempt to inflate the register class of DstReg.
1117 if (!CP.isPhys() && RegClassInfo.isProperSubClass(CP.getNewRC()))
1118 InflateRegs.push_back(CP.getDstReg());
1120 // CopyMI has been erased by joinIntervals at this point. Remove it from
1121 // ErasedInstrs since copyCoalesceWorkList() won't add a successful join back
1122 // to the work list. This keeps ErasedInstrs from growing needlessly.
1123 ErasedInstrs.erase(CopyMI);
1125 // Rewrite all SrcReg operands to DstReg.
1126 // Also update DstReg operands to include DstIdx if it is set.
1128 updateRegDefsUses(CP.getDstReg(), CP.getDstReg(), CP.getDstIdx());
1129 updateRegDefsUses(CP.getSrcReg(), CP.getDstReg(), CP.getSrcIdx());
1131 // SrcReg is guaranteed to be the register whose live interval that is
1133 LIS->removeInterval(CP.getSrcReg());
1135 // Update regalloc hint.
1136 TRI->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
1139 dbgs() << "\tJoined. Result = ";
1141 dbgs() << PrintReg(CP.getDstReg(), TRI);
1143 dbgs() << LIS->getInterval(CP.getDstReg());
1151 /// Attempt joining with a reserved physreg.
1152 bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
1153 assert(CP.isPhys() && "Must be a physreg copy");
1154 assert(MRI->isReserved(CP.getDstReg()) && "Not a reserved register");
1155 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
1156 DEBUG(dbgs() << "\t\tRHS = " << RHS << '\n');
1158 assert(CP.isFlipped() && RHS.containsOneValue() &&
1159 "Invalid join with reserved register");
1161 // Optimization for reserved registers like ESP. We can only merge with a
1162 // reserved physreg if RHS has a single value that is a copy of CP.DstReg().
1163 // The live range of the reserved register will look like a set of dead defs
1164 // - we don't properly track the live range of reserved registers.
1166 // Deny any overlapping intervals. This depends on all the reserved
1167 // register live ranges to look like dead defs.
1168 for (MCRegUnitIterator UI(CP.getDstReg(), TRI); UI.isValid(); ++UI)
1169 if (RHS.overlaps(LIS->getRegUnit(*UI))) {
1170 DEBUG(dbgs() << "\t\tInterference: " << PrintRegUnit(*UI, TRI) << '\n');
1174 // Skip any value computations, we are not adding new values to the
1175 // reserved register. Also skip merging the live ranges, the reserved
1176 // register live range doesn't need to be accurate as long as all the
1179 // Delete the identity copy.
1180 MachineInstr *CopyMI = MRI->getVRegDef(RHS.reg);
1181 LIS->RemoveMachineInstrFromMaps(CopyMI);
1182 CopyMI->eraseFromParent();
1184 // We don't track kills for reserved registers.
1185 MRI->clearKillFlags(CP.getSrcReg());
1190 //===----------------------------------------------------------------------===//
1191 // Interference checking and interval joining
1192 //===----------------------------------------------------------------------===//
1194 // In the easiest case, the two live ranges being joined are disjoint, and
1195 // there is no interference to consider. It is quite common, though, to have
1196 // overlapping live ranges, and we need to check if the interference can be
1199 // The live range of a single SSA value forms a sub-tree of the dominator tree.
1200 // This means that two SSA values overlap if and only if the def of one value
1201 // is contained in the live range of the other value. As a special case, the
1202 // overlapping values can be defined at the same index.
1204 // The interference from an overlapping def can be resolved in these cases:
1206 // 1. Coalescable copies. The value is defined by a copy that would become an
1207 // identity copy after joining SrcReg and DstReg. The copy instruction will
1208 // be removed, and the value will be merged with the source value.
1210 // There can be several copies back and forth, causing many values to be
1211 // merged into one. We compute a list of ultimate values in the joined live
1212 // range as well as a mappings from the old value numbers.
1214 // 2. IMPLICIT_DEF. This instruction is only inserted to ensure all PHI
1215 // predecessors have a live out value. It doesn't cause real interference,
1216 // and can be merged into the value it overlaps. Like a coalescable copy, it
1217 // can be erased after joining.
1219 // 3. Copy of external value. The overlapping def may be a copy of a value that
1220 // is already in the other register. This is like a coalescable copy, but
1221 // the live range of the source register must be trimmed after erasing the
1222 // copy instruction:
1225 // %dst = COPY %ext <-- Remove this COPY, trim the live range of %ext.
1227 // 4. Clobbering undefined lanes. Vector registers are sometimes built by
1228 // defining one lane at a time:
1230 // %dst:ssub0<def,read-undef> = FOO
1232 // %dst:ssub1<def> = COPY %src
1234 // The live range of %src overlaps the %dst value defined by FOO, but
1235 // merging %src into %dst:ssub1 is only going to clobber the ssub1 lane
1236 // which was undef anyway.
1238 // The value mapping is more complicated in this case. The final live range
1239 // will have different value numbers for both FOO and BAR, but there is no
1240 // simple mapping from old to new values. It may even be necessary to add
1243 // 5. Clobbering dead lanes. A def may clobber a lane of a vector register that
1244 // is live, but never read. This can happen because we don't compute
1245 // individual live ranges per lane.
1249 // %dst:ssub1<def> = COPY %src
1251 // This kind of interference is only resolved locally. If the clobbered
1252 // lane value escapes the block, the join is aborted.
1255 /// Track information about values in a single virtual register about to be
1256 /// joined. Objects of this class are always created in pairs - one for each
1257 /// side of the CoalescerPair.
1261 // Location of this register in the final joined register.
1262 // Either CP.DstIdx or CP.SrcIdx.
1265 // Values that will be present in the final live range.
1266 SmallVectorImpl<VNInfo*> &NewVNInfo;
1268 const CoalescerPair &CP;
1270 SlotIndexes *Indexes;
1271 const TargetRegisterInfo *TRI;
1273 // Value number assignments. Maps value numbers in LI to entries in NewVNInfo.
1274 // This is suitable for passing to LiveInterval::join().
1275 SmallVector<int, 8> Assignments;
1277 // Conflict resolution for overlapping values.
1278 enum ConflictResolution {
1279 // No overlap, simply keep this value.
1282 // Merge this value into OtherVNI and erase the defining instruction.
1283 // Used for IMPLICIT_DEF, coalescable copies, and copies from external
1287 // Merge this value into OtherVNI but keep the defining instruction.
1288 // This is for the special case where OtherVNI is defined by the same
1292 // Keep this value, and have it replace OtherVNI where possible. This
1293 // complicates value mapping since OtherVNI maps to two different values
1294 // before and after this def.
1295 // Used when clobbering undefined or dead lanes.
1298 // Unresolved conflict. Visit later when all values have been mapped.
1301 // Unresolvable conflict. Abort the join.
1305 // Per-value info for LI. The lane bit masks are all relative to the final
1306 // joined register, so they can be compared directly between SrcReg and
1309 ConflictResolution Resolution;
1311 // Lanes written by this def, 0 for unanalyzed values.
1312 unsigned WriteLanes;
1314 // Lanes with defined values in this register. Other lanes are undef and
1316 unsigned ValidLanes;
1318 // Value in LI being redefined by this def.
1321 // Value in the other live range that overlaps this def, if any.
1324 // Is this value an IMPLICIT_DEF that can be erased?
1326 // IMPLICIT_DEF values should only exist at the end of a basic block that
1327 // is a predecessor to a phi-value. These IMPLICIT_DEF instructions can be
1328 // safely erased if they are overlapping a live value in the other live
1331 // Weird control flow graphs and incomplete PHI handling in
1332 // ProcessImplicitDefs can very rarely create IMPLICIT_DEF values with
1333 // longer live ranges. Such IMPLICIT_DEF values should be treated like
1335 bool ErasableImplicitDef;
1337 // True when the live range of this value will be pruned because of an
1338 // overlapping CR_Replace value in the other live range.
1341 // True once Pruned above has been computed.
1342 bool PrunedComputed;
1344 Val() : Resolution(CR_Keep), WriteLanes(0), ValidLanes(0),
1345 RedefVNI(0), OtherVNI(0), ErasableImplicitDef(false),
1346 Pruned(false), PrunedComputed(false) {}
1348 bool isAnalyzed() const { return WriteLanes != 0; }
1351 // One entry per value number in LI.
1352 SmallVector<Val, 8> Vals;
1354 unsigned computeWriteLanes(const MachineInstr *DefMI, bool &Redef);
1355 VNInfo *stripCopies(VNInfo *VNI);
1356 ConflictResolution analyzeValue(unsigned ValNo, JoinVals &Other);
1357 void computeAssignment(unsigned ValNo, JoinVals &Other);
1358 bool taintExtent(unsigned, unsigned, JoinVals&,
1359 SmallVectorImpl<std::pair<SlotIndex, unsigned> >&);
1360 bool usesLanes(MachineInstr *MI, unsigned, unsigned, unsigned);
1361 bool isPrunedValue(unsigned ValNo, JoinVals &Other);
1364 JoinVals(LiveInterval &li, unsigned subIdx,
1365 SmallVectorImpl<VNInfo*> &newVNInfo,
1366 const CoalescerPair &cp,
1368 const TargetRegisterInfo *tri)
1369 : LI(li), SubIdx(subIdx), NewVNInfo(newVNInfo), CP(cp), LIS(lis),
1370 Indexes(LIS->getSlotIndexes()), TRI(tri),
1371 Assignments(LI.getNumValNums(), -1), Vals(LI.getNumValNums())
1374 /// Analyze defs in LI and compute a value mapping in NewVNInfo.
1375 /// Returns false if any conflicts were impossible to resolve.
1376 bool mapValues(JoinVals &Other);
1378 /// Try to resolve conflicts that require all values to be mapped.
1379 /// Returns false if any conflicts were impossible to resolve.
1380 bool resolveConflicts(JoinVals &Other);
1382 /// Prune the live range of values in Other.LI where they would conflict with
1383 /// CR_Replace values in LI. Collect end points for restoring the live range
1385 void pruneValues(JoinVals &Other, SmallVectorImpl<SlotIndex> &EndPoints);
1387 /// Erase any machine instructions that have been coalesced away.
1388 /// Add erased instructions to ErasedInstrs.
1389 /// Add foreign virtual registers to ShrinkRegs if their live range ended at
1390 /// the erased instrs.
1391 void eraseInstrs(SmallPtrSet<MachineInstr*, 8> &ErasedInstrs,
1392 SmallVectorImpl<unsigned> &ShrinkRegs);
1394 /// Get the value assignments suitable for passing to LiveInterval::join.
1395 const int *getAssignments() const { return Assignments.data(); }
1397 } // end anonymous namespace
1399 /// Compute the bitmask of lanes actually written by DefMI.
1400 /// Set Redef if there are any partial register definitions that depend on the
1401 /// previous value of the register.
1402 unsigned JoinVals::computeWriteLanes(const MachineInstr *DefMI, bool &Redef) {
1404 for (ConstMIOperands MO(DefMI); MO.isValid(); ++MO) {
1405 if (!MO->isReg() || MO->getReg() != LI.reg || !MO->isDef())
1407 L |= TRI->getSubRegIndexLaneMask(
1408 TRI->composeSubRegIndices(SubIdx, MO->getSubReg()));
1415 /// Find the ultimate value that VNI was copied from.
1416 VNInfo *JoinVals::stripCopies(VNInfo *VNI) {
1417 while (!VNI->isPHIDef()) {
1418 MachineInstr *MI = Indexes->getInstructionFromIndex(VNI->def);
1419 assert(MI && "No defining instruction");
1420 if (!MI->isFullCopy())
1422 unsigned Reg = MI->getOperand(1).getReg();
1423 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1425 LiveQueryResult LRQ = LIS->getInterval(Reg).Query(VNI->def);
1428 VNI = LRQ.valueIn();
1433 /// Analyze ValNo in this live range, and set all fields of Vals[ValNo].
1434 /// Return a conflict resolution when possible, but leave the hard cases as
1436 /// Recursively calls computeAssignment() on this and Other, guaranteeing that
1437 /// both OtherVNI and RedefVNI have been analyzed and mapped before returning.
1438 /// The recursion always goes upwards in the dominator tree, making loops
1440 JoinVals::ConflictResolution
1441 JoinVals::analyzeValue(unsigned ValNo, JoinVals &Other) {
1442 Val &V = Vals[ValNo];
1443 assert(!V.isAnalyzed() && "Value has already been analyzed!");
1444 VNInfo *VNI = LI.getValNumInfo(ValNo);
1445 if (VNI->isUnused()) {
1450 // Get the instruction defining this value, compute the lanes written.
1451 const MachineInstr *DefMI = 0;
1452 if (VNI->isPHIDef()) {
1453 // Conservatively assume that all lanes in a PHI are valid.
1454 V.ValidLanes = V.WriteLanes = TRI->getSubRegIndexLaneMask(SubIdx);
1456 DefMI = Indexes->getInstructionFromIndex(VNI->def);
1458 V.ValidLanes = V.WriteLanes = computeWriteLanes(DefMI, Redef);
1460 // If this is a read-modify-write instruction, there may be more valid
1461 // lanes than the ones written by this instruction.
1462 // This only covers partial redef operands. DefMI may have normal use
1463 // operands reading the register. They don't contribute valid lanes.
1465 // This adds ssub1 to the set of valid lanes in %src:
1467 // %src:ssub1<def> = FOO
1469 // This leaves only ssub1 valid, making any other lanes undef:
1471 // %src:ssub1<def,read-undef> = FOO %src:ssub2
1473 // The <read-undef> flag on the def operand means that old lane values are
1476 V.RedefVNI = LI.Query(VNI->def).valueIn();
1477 assert(V.RedefVNI && "Instruction is reading nonexistent value");
1478 computeAssignment(V.RedefVNI->id, Other);
1479 V.ValidLanes |= Vals[V.RedefVNI->id].ValidLanes;
1482 // An IMPLICIT_DEF writes undef values.
1483 if (DefMI->isImplicitDef()) {
1484 // We normally expect IMPLICIT_DEF values to be live only until the end
1485 // of their block. If the value is really live longer and gets pruned in
1486 // another block, this flag is cleared again.
1487 V.ErasableImplicitDef = true;
1488 V.ValidLanes &= ~V.WriteLanes;
1492 // Find the value in Other that overlaps VNI->def, if any.
1493 LiveQueryResult OtherLRQ = Other.LI.Query(VNI->def);
1495 // It is possible that both values are defined by the same instruction, or
1496 // the values are PHIs defined in the same block. When that happens, the two
1497 // values should be merged into one, but not into any preceding value.
1498 // The first value defined or visited gets CR_Keep, the other gets CR_Merge.
1499 if (VNInfo *OtherVNI = OtherLRQ.valueDefined()) {
1500 assert(SlotIndex::isSameInstr(VNI->def, OtherVNI->def) && "Broken LRQ");
1502 // One value stays, the other is merged. Keep the earlier one, or the first
1504 if (OtherVNI->def < VNI->def)
1505 Other.computeAssignment(OtherVNI->id, *this);
1506 else if (VNI->def < OtherVNI->def && OtherLRQ.valueIn()) {
1507 // This is an early-clobber def overlapping a live-in value in the other
1508 // register. Not mergeable.
1509 V.OtherVNI = OtherLRQ.valueIn();
1510 return CR_Impossible;
1512 V.OtherVNI = OtherVNI;
1513 Val &OtherV = Other.Vals[OtherVNI->id];
1514 // Keep this value, check for conflicts when analyzing OtherVNI.
1515 if (!OtherV.isAnalyzed())
1517 // Both sides have been analyzed now.
1518 // Allow overlapping PHI values. Any real interference would show up in a
1519 // predecessor, the PHI itself can't introduce any conflicts.
1520 if (VNI->isPHIDef())
1522 if (V.ValidLanes & OtherV.ValidLanes)
1523 // Overlapping lanes can't be resolved.
1524 return CR_Impossible;
1529 // No simultaneous def. Is Other live at the def?
1530 V.OtherVNI = OtherLRQ.valueIn();
1532 // No overlap, no conflict.
1535 assert(!SlotIndex::isSameInstr(VNI->def, V.OtherVNI->def) && "Broken LRQ");
1537 // We have overlapping values, or possibly a kill of Other.
1538 // Recursively compute assignments up the dominator tree.
1539 Other.computeAssignment(V.OtherVNI->id, *this);
1540 Val &OtherV = Other.Vals[V.OtherVNI->id];
1542 // Check if OtherV is an IMPLICIT_DEF that extends beyond its basic block.
1543 // This shouldn't normally happen, but ProcessImplicitDefs can leave such
1544 // IMPLICIT_DEF instructions behind, and there is nothing wrong with it
1547 // WHen it happens, treat that IMPLICIT_DEF as a normal value, and don't try
1548 // to erase the IMPLICIT_DEF instruction.
1549 if (OtherV.ErasableImplicitDef && DefMI &&
1550 DefMI->getParent() != Indexes->getMBBFromIndex(V.OtherVNI->def)) {
1551 DEBUG(dbgs() << "IMPLICIT_DEF defined at " << V.OtherVNI->def
1552 << " extends into BB#" << DefMI->getParent()->getNumber()
1553 << ", keeping it.\n");
1554 OtherV.ErasableImplicitDef = false;
1557 // Allow overlapping PHI values. Any real interference would show up in a
1558 // predecessor, the PHI itself can't introduce any conflicts.
1559 if (VNI->isPHIDef())
1562 // Check for simple erasable conflicts.
1563 if (DefMI->isImplicitDef())
1566 // Include the non-conflict where DefMI is a coalescable copy that kills
1567 // OtherVNI. We still want the copy erased and value numbers merged.
1568 if (CP.isCoalescable(DefMI)) {
1569 // Some of the lanes copied from OtherVNI may be undef, making them undef
1571 V.ValidLanes &= ~V.WriteLanes | OtherV.ValidLanes;
1575 // This may not be a real conflict if DefMI simply kills Other and defines
1577 if (OtherLRQ.isKill() && OtherLRQ.endPoint() <= VNI->def)
1580 // Handle the case where VNI and OtherVNI can be proven to be identical:
1582 // %other = COPY %ext
1583 // %this = COPY %ext <-- Erase this copy
1585 if (DefMI->isFullCopy() && !CP.isPartial() &&
1586 stripCopies(VNI) == stripCopies(V.OtherVNI))
1589 // If the lanes written by this instruction were all undef in OtherVNI, it is
1590 // still safe to join the live ranges. This can't be done with a simple value
1591 // mapping, though - OtherVNI will map to multiple values:
1593 // 1 %dst:ssub0 = FOO <-- OtherVNI
1594 // 2 %src = BAR <-- VNI
1595 // 3 %dst:ssub1 = COPY %src<kill> <-- Eliminate this copy.
1597 // 5 QUUX %src<kill>
1599 // Here OtherVNI will map to itself in [1;2), but to VNI in [2;5). CR_Replace
1600 // handles this complex value mapping.
1601 if ((V.WriteLanes & OtherV.ValidLanes) == 0)
1604 // If the other live range is killed by DefMI and the live ranges are still
1605 // overlapping, it must be because we're looking at an early clobber def:
1607 // %dst<def,early-clobber> = ASM %src<kill>
1609 // In this case, it is illegal to merge the two live ranges since the early
1610 // clobber def would clobber %src before it was read.
1611 if (OtherLRQ.isKill()) {
1612 // This case where the def doesn't overlap the kill is handled above.
1613 assert(VNI->def.isEarlyClobber() &&
1614 "Only early clobber defs can overlap a kill");
1615 return CR_Impossible;
1618 // VNI is clobbering live lanes in OtherVNI, but there is still the
1619 // possibility that no instructions actually read the clobbered lanes.
1620 // If we're clobbering all the lanes in OtherVNI, at least one must be read.
1621 // Otherwise Other.LI wouldn't be live here.
1622 if ((TRI->getSubRegIndexLaneMask(Other.SubIdx) & ~V.WriteLanes) == 0)
1623 return CR_Impossible;
1625 // We need to verify that no instructions are reading the clobbered lanes. To
1626 // save compile time, we'll only check that locally. Don't allow the tainted
1627 // value to escape the basic block.
1628 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
1629 if (OtherLRQ.endPoint() >= Indexes->getMBBEndIdx(MBB))
1630 return CR_Impossible;
1632 // There are still some things that could go wrong besides clobbered lanes
1633 // being read, for example OtherVNI may be only partially redefined in MBB,
1634 // and some clobbered lanes could escape the block. Save this analysis for
1635 // resolveConflicts() when all values have been mapped. We need to know
1636 // RedefVNI and WriteLanes for any later defs in MBB, and we can't compute
1637 // that now - the recursive analyzeValue() calls must go upwards in the
1639 return CR_Unresolved;
1642 /// Compute the value assignment for ValNo in LI.
1643 /// This may be called recursively by analyzeValue(), but never for a ValNo on
1645 void JoinVals::computeAssignment(unsigned ValNo, JoinVals &Other) {
1646 Val &V = Vals[ValNo];
1647 if (V.isAnalyzed()) {
1648 // Recursion should always move up the dominator tree, so ValNo is not
1649 // supposed to reappear before it has been assigned.
1650 assert(Assignments[ValNo] != -1 && "Bad recursion?");
1653 switch ((V.Resolution = analyzeValue(ValNo, Other))) {
1656 // Merge this ValNo into OtherVNI.
1657 assert(V.OtherVNI && "OtherVNI not assigned, can't merge.");
1658 assert(Other.Vals[V.OtherVNI->id].isAnalyzed() && "Missing recursion");
1659 Assignments[ValNo] = Other.Assignments[V.OtherVNI->id];
1660 DEBUG(dbgs() << "\t\tmerge " << PrintReg(LI.reg) << ':' << ValNo << '@'
1661 << LI.getValNumInfo(ValNo)->def << " into "
1662 << PrintReg(Other.LI.reg) << ':' << V.OtherVNI->id << '@'
1663 << V.OtherVNI->def << " --> @"
1664 << NewVNInfo[Assignments[ValNo]]->def << '\n');
1668 // The other value is going to be pruned if this join is successful.
1669 assert(V.OtherVNI && "OtherVNI not assigned, can't prune");
1670 Other.Vals[V.OtherVNI->id].Pruned = true;
1673 // This value number needs to go in the final joined live range.
1674 Assignments[ValNo] = NewVNInfo.size();
1675 NewVNInfo.push_back(LI.getValNumInfo(ValNo));
1680 bool JoinVals::mapValues(JoinVals &Other) {
1681 for (unsigned i = 0, e = LI.getNumValNums(); i != e; ++i) {
1682 computeAssignment(i, Other);
1683 if (Vals[i].Resolution == CR_Impossible) {
1684 DEBUG(dbgs() << "\t\tinterference at " << PrintReg(LI.reg) << ':' << i
1685 << '@' << LI.getValNumInfo(i)->def << '\n');
1692 /// Assuming ValNo is going to clobber some valid lanes in Other.LI, compute
1693 /// the extent of the tainted lanes in the block.
1695 /// Multiple values in Other.LI can be affected since partial redefinitions can
1696 /// preserve previously tainted lanes.
1698 /// 1 %dst = VLOAD <-- Define all lanes in %dst
1699 /// 2 %src = FOO <-- ValNo to be joined with %dst:ssub0
1700 /// 3 %dst:ssub1 = BAR <-- Partial redef doesn't clear taint in ssub0
1701 /// 4 %dst:ssub0 = COPY %src <-- Conflict resolved, ssub0 wasn't read
1703 /// For each ValNo in Other that is affected, add an (EndIndex, TaintedLanes)
1704 /// entry to TaintedVals.
1706 /// Returns false if the tainted lanes extend beyond the basic block.
1708 taintExtent(unsigned ValNo, unsigned TaintedLanes, JoinVals &Other,
1709 SmallVectorImpl<std::pair<SlotIndex, unsigned> > &TaintExtent) {
1710 VNInfo *VNI = LI.getValNumInfo(ValNo);
1711 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
1712 SlotIndex MBBEnd = Indexes->getMBBEndIdx(MBB);
1714 // Scan Other.LI from VNI.def to MBBEnd.
1715 LiveInterval::iterator OtherI = Other.LI.find(VNI->def);
1716 assert(OtherI != Other.LI.end() && "No conflict?");
1718 // OtherI is pointing to a tainted value. Abort the join if the tainted
1719 // lanes escape the block.
1720 SlotIndex End = OtherI->end;
1721 if (End >= MBBEnd) {
1722 DEBUG(dbgs() << "\t\ttaints global " << PrintReg(Other.LI.reg) << ':'
1723 << OtherI->valno->id << '@' << OtherI->start << '\n');
1726 DEBUG(dbgs() << "\t\ttaints local " << PrintReg(Other.LI.reg) << ':'
1727 << OtherI->valno->id << '@' << OtherI->start
1728 << " to " << End << '\n');
1729 // A dead def is not a problem.
1732 TaintExtent.push_back(std::make_pair(End, TaintedLanes));
1734 // Check for another def in the MBB.
1735 if (++OtherI == Other.LI.end() || OtherI->start >= MBBEnd)
1738 // Lanes written by the new def are no longer tainted.
1739 const Val &OV = Other.Vals[OtherI->valno->id];
1740 TaintedLanes &= ~OV.WriteLanes;
1743 } while (TaintedLanes);
1747 /// Return true if MI uses any of the given Lanes from Reg.
1748 /// This does not include partial redefinitions of Reg.
1749 bool JoinVals::usesLanes(MachineInstr *MI, unsigned Reg, unsigned SubIdx,
1751 if (MI->isDebugValue())
1753 for (ConstMIOperands MO(MI); MO.isValid(); ++MO) {
1754 if (!MO->isReg() || MO->isDef() || MO->getReg() != Reg)
1756 if (!MO->readsReg())
1758 if (Lanes & TRI->getSubRegIndexLaneMask(
1759 TRI->composeSubRegIndices(SubIdx, MO->getSubReg())))
1765 bool JoinVals::resolveConflicts(JoinVals &Other) {
1766 for (unsigned i = 0, e = LI.getNumValNums(); i != e; ++i) {
1768 assert (V.Resolution != CR_Impossible && "Unresolvable conflict");
1769 if (V.Resolution != CR_Unresolved)
1771 DEBUG(dbgs() << "\t\tconflict at " << PrintReg(LI.reg) << ':' << i
1772 << '@' << LI.getValNumInfo(i)->def << '\n');
1774 assert(V.OtherVNI && "Inconsistent conflict resolution.");
1775 VNInfo *VNI = LI.getValNumInfo(i);
1776 const Val &OtherV = Other.Vals[V.OtherVNI->id];
1778 // VNI is known to clobber some lanes in OtherVNI. If we go ahead with the
1779 // join, those lanes will be tainted with a wrong value. Get the extent of
1780 // the tainted lanes.
1781 unsigned TaintedLanes = V.WriteLanes & OtherV.ValidLanes;
1782 SmallVector<std::pair<SlotIndex, unsigned>, 8> TaintExtent;
1783 if (!taintExtent(i, TaintedLanes, Other, TaintExtent))
1784 // Tainted lanes would extend beyond the basic block.
1787 assert(!TaintExtent.empty() && "There should be at least one conflict.");
1789 // Now look at the instructions from VNI->def to TaintExtent (inclusive).
1790 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
1791 MachineBasicBlock::iterator MI = MBB->begin();
1792 if (!VNI->isPHIDef()) {
1793 MI = Indexes->getInstructionFromIndex(VNI->def);
1794 // No need to check the instruction defining VNI for reads.
1797 assert(!SlotIndex::isSameInstr(VNI->def, TaintExtent.front().first) &&
1798 "Interference ends on VNI->def. Should have been handled earlier");
1799 MachineInstr *LastMI =
1800 Indexes->getInstructionFromIndex(TaintExtent.front().first);
1801 assert(LastMI && "Range must end at a proper instruction");
1802 unsigned TaintNum = 0;
1804 assert(MI != MBB->end() && "Bad LastMI");
1805 if (usesLanes(MI, Other.LI.reg, Other.SubIdx, TaintedLanes)) {
1806 DEBUG(dbgs() << "\t\ttainted lanes used by: " << *MI);
1809 // LastMI is the last instruction to use the current value.
1810 if (&*MI == LastMI) {
1811 if (++TaintNum == TaintExtent.size())
1813 LastMI = Indexes->getInstructionFromIndex(TaintExtent[TaintNum].first);
1814 assert(LastMI && "Range must end at a proper instruction");
1815 TaintedLanes = TaintExtent[TaintNum].second;
1820 // The tainted lanes are unused.
1821 V.Resolution = CR_Replace;
1827 // Determine if ValNo is a copy of a value number in LI or Other.LI that will
1831 // %src = COPY %dst <-- This value to be pruned.
1832 // %dst = COPY %src <-- This value is a copy of a pruned value.
1834 bool JoinVals::isPrunedValue(unsigned ValNo, JoinVals &Other) {
1835 Val &V = Vals[ValNo];
1836 if (V.Pruned || V.PrunedComputed)
1839 if (V.Resolution != CR_Erase && V.Resolution != CR_Merge)
1842 // Follow copies up the dominator tree and check if any intermediate value
1844 V.PrunedComputed = true;
1845 V.Pruned = Other.isPrunedValue(V.OtherVNI->id, *this);
1849 void JoinVals::pruneValues(JoinVals &Other,
1850 SmallVectorImpl<SlotIndex> &EndPoints) {
1851 for (unsigned i = 0, e = LI.getNumValNums(); i != e; ++i) {
1852 SlotIndex Def = LI.getValNumInfo(i)->def;
1853 switch (Vals[i].Resolution) {
1857 // This value takes precedence over the value in Other.LI.
1858 LIS->pruneValue(&Other.LI, Def, &EndPoints);
1859 // Check if we're replacing an IMPLICIT_DEF value. The IMPLICIT_DEF
1860 // instructions are only inserted to provide a live-out value for PHI
1861 // predecessors, so the instruction should simply go away once its value
1862 // has been replaced.
1863 Val &OtherV = Other.Vals[Vals[i].OtherVNI->id];
1864 bool EraseImpDef = OtherV.ErasableImplicitDef &&
1865 OtherV.Resolution == CR_Keep;
1866 if (!Def.isBlock()) {
1867 // Remove <def,read-undef> flags. This def is now a partial redef.
1868 // Also remove <def,dead> flags since the joined live range will
1869 // continue past this instruction.
1870 for (MIOperands MO(Indexes->getInstructionFromIndex(Def));
1872 if (MO->isReg() && MO->isDef() && MO->getReg() == LI.reg) {
1873 MO->setIsUndef(EraseImpDef);
1874 MO->setIsDead(false);
1876 // This value will reach instructions below, but we need to make sure
1877 // the live range also reaches the instruction at Def.
1879 EndPoints.push_back(Def);
1881 DEBUG(dbgs() << "\t\tpruned " << PrintReg(Other.LI.reg) << " at " << Def
1882 << ": " << Other.LI << '\n');
1887 if (isPrunedValue(i, Other)) {
1888 // This value is ultimately a copy of a pruned value in LI or Other.LI.
1889 // We can no longer trust the value mapping computed by
1890 // computeAssignment(), the value that was originally copied could have
1892 LIS->pruneValue(&LI, Def, &EndPoints);
1893 DEBUG(dbgs() << "\t\tpruned all of " << PrintReg(LI.reg) << " at "
1894 << Def << ": " << LI << '\n');
1899 llvm_unreachable("Unresolved conflicts");
1904 void JoinVals::eraseInstrs(SmallPtrSet<MachineInstr*, 8> &ErasedInstrs,
1905 SmallVectorImpl<unsigned> &ShrinkRegs) {
1906 for (unsigned i = 0, e = LI.getNumValNums(); i != e; ++i) {
1907 // Get the def location before markUnused() below invalidates it.
1908 SlotIndex Def = LI.getValNumInfo(i)->def;
1909 switch (Vals[i].Resolution) {
1911 // If an IMPLICIT_DEF value is pruned, it doesn't serve a purpose any
1912 // longer. The IMPLICIT_DEF instructions are only inserted by
1913 // PHIElimination to guarantee that all PHI predecessors have a value.
1914 if (!Vals[i].ErasableImplicitDef || !Vals[i].Pruned)
1916 // Remove value number i from LI. Note that this VNInfo is still present
1917 // in NewVNInfo, so it will appear as an unused value number in the final
1919 LI.getValNumInfo(i)->markUnused();
1920 LI.removeValNo(LI.getValNumInfo(i));
1921 DEBUG(dbgs() << "\t\tremoved " << i << '@' << Def << ": " << LI << '\n');
1925 MachineInstr *MI = Indexes->getInstructionFromIndex(Def);
1926 assert(MI && "No instruction to erase");
1928 unsigned Reg = MI->getOperand(1).getReg();
1929 if (TargetRegisterInfo::isVirtualRegister(Reg) &&
1930 Reg != CP.getSrcReg() && Reg != CP.getDstReg())
1931 ShrinkRegs.push_back(Reg);
1933 ErasedInstrs.insert(MI);
1934 DEBUG(dbgs() << "\t\terased:\t" << Def << '\t' << *MI);
1935 LIS->RemoveMachineInstrFromMaps(MI);
1936 MI->eraseFromParent();
1945 bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) {
1946 SmallVector<VNInfo*, 16> NewVNInfo;
1947 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
1948 LiveInterval &LHS = LIS->getInterval(CP.getDstReg());
1949 JoinVals RHSVals(RHS, CP.getSrcIdx(), NewVNInfo, CP, LIS, TRI);
1950 JoinVals LHSVals(LHS, CP.getDstIdx(), NewVNInfo, CP, LIS, TRI);
1952 DEBUG(dbgs() << "\t\tRHS = " << RHS
1953 << "\n\t\tLHS = " << LHS
1956 // First compute NewVNInfo and the simple value mappings.
1957 // Detect impossible conflicts early.
1958 if (!LHSVals.mapValues(RHSVals) || !RHSVals.mapValues(LHSVals))
1961 // Some conflicts can only be resolved after all values have been mapped.
1962 if (!LHSVals.resolveConflicts(RHSVals) || !RHSVals.resolveConflicts(LHSVals))
1965 // All clear, the live ranges can be merged.
1967 // The merging algorithm in LiveInterval::join() can't handle conflicting
1968 // value mappings, so we need to remove any live ranges that overlap a
1969 // CR_Replace resolution. Collect a set of end points that can be used to
1970 // restore the live range after joining.
1971 SmallVector<SlotIndex, 8> EndPoints;
1972 LHSVals.pruneValues(RHSVals, EndPoints);
1973 RHSVals.pruneValues(LHSVals, EndPoints);
1975 // Erase COPY and IMPLICIT_DEF instructions. This may cause some external
1976 // registers to require trimming.
1977 SmallVector<unsigned, 8> ShrinkRegs;
1978 LHSVals.eraseInstrs(ErasedInstrs, ShrinkRegs);
1979 RHSVals.eraseInstrs(ErasedInstrs, ShrinkRegs);
1980 while (!ShrinkRegs.empty())
1981 LIS->shrinkToUses(&LIS->getInterval(ShrinkRegs.pop_back_val()));
1983 // Join RHS into LHS.
1984 LHS.join(RHS, LHSVals.getAssignments(), RHSVals.getAssignments(), NewVNInfo);
1986 // Kill flags are going to be wrong if the live ranges were overlapping.
1987 // Eventually, we should simply clear all kill flags when computing live
1988 // ranges. They are reinserted after register allocation.
1989 MRI->clearKillFlags(LHS.reg);
1990 MRI->clearKillFlags(RHS.reg);
1992 if (EndPoints.empty())
1995 // Recompute the parts of the live range we had to remove because of
1996 // CR_Replace conflicts.
1997 DEBUG(dbgs() << "\t\trestoring liveness to " << EndPoints.size()
1998 << " points: " << LHS << '\n');
1999 LIS->extendToIndices(LHS, EndPoints);
2003 /// joinIntervals - Attempt to join these two intervals. On failure, this
2005 bool RegisterCoalescer::joinIntervals(CoalescerPair &CP) {
2006 return CP.isPhys() ? joinReservedPhysReg(CP) : joinVirtRegs(CP);
2010 // Information concerning MBB coalescing priority.
2011 struct MBBPriorityInfo {
2012 MachineBasicBlock *MBB;
2016 MBBPriorityInfo(MachineBasicBlock *mbb, unsigned depth, bool issplit)
2017 : MBB(mbb), Depth(depth), IsSplit(issplit) {}
2021 // C-style comparator that sorts first based on the loop depth of the basic
2022 // block (the unsigned), and then on the MBB number.
2024 // EnableGlobalCopies assumes that the primary sort key is loop depth.
2025 static int compareMBBPriority(const MBBPriorityInfo *LHS,
2026 const MBBPriorityInfo *RHS) {
2027 // Deeper loops first
2028 if (LHS->Depth != RHS->Depth)
2029 return LHS->Depth > RHS->Depth ? -1 : 1;
2031 // Try to unsplit critical edges next.
2032 if (LHS->IsSplit != RHS->IsSplit)
2033 return LHS->IsSplit ? -1 : 1;
2035 // Prefer blocks that are more connected in the CFG. This takes care of
2036 // the most difficult copies first while intervals are short.
2037 unsigned cl = LHS->MBB->pred_size() + LHS->MBB->succ_size();
2038 unsigned cr = RHS->MBB->pred_size() + RHS->MBB->succ_size();
2040 return cl > cr ? -1 : 1;
2042 // As a last resort, sort by block number.
2043 return LHS->MBB->getNumber() < RHS->MBB->getNumber() ? -1 : 1;
2046 /// \returns true if the given copy uses or defines a local live range.
2047 static bool isLocalCopy(MachineInstr *Copy, const LiveIntervals *LIS) {
2048 if (!Copy->isCopy())
2051 if (Copy->getOperand(1).isUndef())
2054 unsigned SrcReg = Copy->getOperand(1).getReg();
2055 unsigned DstReg = Copy->getOperand(0).getReg();
2056 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)
2057 || TargetRegisterInfo::isPhysicalRegister(DstReg))
2060 return LIS->intervalIsInOneMBB(LIS->getInterval(SrcReg))
2061 || LIS->intervalIsInOneMBB(LIS->getInterval(DstReg));
2064 // Try joining WorkList copies starting from index From.
2065 // Null out any successful joins.
2066 bool RegisterCoalescer::
2067 copyCoalesceWorkList(MutableArrayRef<MachineInstr*> CurrList) {
2068 bool Progress = false;
2069 for (unsigned i = 0, e = CurrList.size(); i != e; ++i) {
2072 // Skip instruction pointers that have already been erased, for example by
2073 // dead code elimination.
2074 if (ErasedInstrs.erase(CurrList[i])) {
2079 bool Success = joinCopy(CurrList[i], Again);
2080 Progress |= Success;
2081 if (Success || !Again)
2088 RegisterCoalescer::copyCoalesceInMBB(MachineBasicBlock *MBB) {
2089 DEBUG(dbgs() << MBB->getName() << ":\n");
2091 // Collect all copy-like instructions in MBB. Don't start coalescing anything
2092 // yet, it might invalidate the iterator.
2093 const unsigned PrevSize = WorkList.size();
2094 if (JoinGlobalCopies) {
2095 // Coalesce copies bottom-up to coalesce local defs before local uses. They
2096 // are not inherently easier to resolve, but slightly preferable until we
2097 // have local live range splitting. In particular this is required by
2098 // cmp+jmp macro fusion.
2099 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
2101 if (!MII->isCopyLike())
2103 if (isLocalCopy(&(*MII), LIS))
2104 LocalWorkList.push_back(&(*MII));
2106 WorkList.push_back(&(*MII));
2110 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
2112 if (MII->isCopyLike())
2113 WorkList.push_back(MII);
2115 // Try coalescing the collected copies immediately, and remove the nulls.
2116 // This prevents the WorkList from getting too large since most copies are
2117 // joinable on the first attempt.
2118 MutableArrayRef<MachineInstr*>
2119 CurrList(WorkList.begin() + PrevSize, WorkList.end());
2120 if (copyCoalesceWorkList(CurrList))
2121 WorkList.erase(std::remove(WorkList.begin() + PrevSize, WorkList.end(),
2122 (MachineInstr*)0), WorkList.end());
2125 void RegisterCoalescer::coalesceLocals() {
2126 copyCoalesceWorkList(LocalWorkList);
2127 for (unsigned j = 0, je = LocalWorkList.size(); j != je; ++j) {
2128 if (LocalWorkList[j])
2129 WorkList.push_back(LocalWorkList[j]);
2131 LocalWorkList.clear();
2134 void RegisterCoalescer::joinAllIntervals() {
2135 DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
2136 assert(WorkList.empty() && LocalWorkList.empty() && "Old data still around.");
2138 std::vector<MBBPriorityInfo> MBBs;
2139 MBBs.reserve(MF->size());
2140 for (MachineFunction::iterator I = MF->begin(), E = MF->end();I != E;++I){
2141 MachineBasicBlock *MBB = I;
2142 MBBs.push_back(MBBPriorityInfo(MBB, Loops->getLoopDepth(MBB),
2143 JoinSplitEdges && isSplitEdge(MBB)));
2145 array_pod_sort(MBBs.begin(), MBBs.end(), compareMBBPriority);
2147 // Coalesce intervals in MBB priority order.
2148 unsigned CurrDepth = UINT_MAX;
2149 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
2150 // Try coalescing the collected local copies for deeper loops.
2151 if (JoinGlobalCopies && MBBs[i].Depth < CurrDepth) {
2153 CurrDepth = MBBs[i].Depth;
2155 copyCoalesceInMBB(MBBs[i].MBB);
2159 // Joining intervals can allow other intervals to be joined. Iteratively join
2160 // until we make no progress.
2161 while (copyCoalesceWorkList(WorkList))
2165 void RegisterCoalescer::releaseMemory() {
2166 ErasedInstrs.clear();
2169 InflateRegs.clear();
2172 bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
2174 MRI = &fn.getRegInfo();
2175 TM = &fn.getTarget();
2176 TRI = TM->getRegisterInfo();
2177 TII = TM->getInstrInfo();
2178 LIS = &getAnalysis<LiveIntervals>();
2179 AA = &getAnalysis<AliasAnalysis>();
2180 Loops = &getAnalysis<MachineLoopInfo>();
2182 const TargetSubtargetInfo &ST = TM->getSubtarget<TargetSubtargetInfo>();
2183 if (EnableGlobalCopies == cl::BOU_UNSET)
2184 JoinGlobalCopies = ST.useMachineScheduler();
2186 JoinGlobalCopies = (EnableGlobalCopies == cl::BOU_TRUE);
2188 // The MachineScheduler does not currently require JoinSplitEdges. This will
2189 // either be enabled unconditionally or replaced by a more general live range
2190 // splitting optimization.
2191 JoinSplitEdges = EnableJoinSplits;
2193 DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
2194 << "********** Function: " << MF->getName() << '\n');
2196 if (VerifyCoalescing)
2197 MF->verify(this, "Before register coalescing");
2199 RegClassInfo.runOnMachineFunction(fn);
2201 // Join (coalesce) intervals if requested.
2205 // After deleting a lot of copies, register classes may be less constrained.
2206 // Removing sub-register operands may allow GR32_ABCD -> GR32 and DPR_VFP2 ->
2208 array_pod_sort(InflateRegs.begin(), InflateRegs.end());
2209 InflateRegs.erase(std::unique(InflateRegs.begin(), InflateRegs.end()),
2211 DEBUG(dbgs() << "Trying to inflate " << InflateRegs.size() << " regs.\n");
2212 for (unsigned i = 0, e = InflateRegs.size(); i != e; ++i) {
2213 unsigned Reg = InflateRegs[i];
2214 if (MRI->reg_nodbg_empty(Reg))
2216 if (MRI->recomputeRegClass(Reg, *TM)) {
2217 DEBUG(dbgs() << PrintReg(Reg) << " inflated to "
2218 << MRI->getRegClass(Reg)->getName() << '\n');
2224 if (VerifyCoalescing)
2225 MF->verify(this, "After register coalescing");
2229 /// print - Implement the dump method.
2230 void RegisterCoalescer::print(raw_ostream &O, const Module* m) const {