1 //===- RegisterCoalescer.cpp - Generic Register Coalescing Interface -------==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the generic RegisterCoalescer interface which
11 // is used as the common interface used by all clients and
12 // implementations of register coalescing.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "regalloc"
17 #include "RegisterCoalescer.h"
18 #include "llvm/ADT/OwningPtr.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/Analysis/AliasAnalysis.h"
23 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
24 #include "llvm/CodeGen/LiveRangeEdit.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/MachineLoopInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/CodeGen/RegisterClassInfo.h"
31 #include "llvm/CodeGen/VirtRegMap.h"
32 #include "llvm/IR/Value.h"
33 #include "llvm/Pass.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetSubtargetInfo.h"
46 STATISTIC(numJoins , "Number of interval joins performed");
47 STATISTIC(numCrossRCs , "Number of cross class joins performed");
48 STATISTIC(numCommutes , "Number of instruction commuting performed");
49 STATISTIC(numExtends , "Number of copies extended");
50 STATISTIC(NumReMats , "Number of instructions re-materialized");
51 STATISTIC(NumInflated , "Number of register classes inflated");
52 STATISTIC(NumLaneConflicts, "Number of dead lane conflicts tested");
53 STATISTIC(NumLaneResolves, "Number of dead lane conflicts resolved");
56 EnableJoining("join-liveintervals",
57 cl::desc("Coalesce copies (default=true)"),
60 // Temporary flag to test critical edge unsplitting.
62 EnableJoinSplits("join-splitedges",
63 cl::desc("Coalesce copies on split edges (default=subtarget)"), cl::Hidden);
65 // Temporary flag to test global copy optimization.
66 static cl::opt<cl::boolOrDefault>
67 EnableGlobalCopies("join-globalcopies",
68 cl::desc("Coalesce copies that span blocks (default=subtarget)"),
69 cl::init(cl::BOU_UNSET), cl::Hidden);
72 VerifyCoalescing("verify-coalescing",
73 cl::desc("Verify machine instrs before and after register coalescing"),
77 class RegisterCoalescer : public MachineFunctionPass,
78 private LiveRangeEdit::Delegate {
80 MachineRegisterInfo* MRI;
81 const TargetMachine* TM;
82 const TargetRegisterInfo* TRI;
83 const TargetInstrInfo* TII;
85 const MachineLoopInfo* Loops;
87 RegisterClassInfo RegClassInfo;
89 /// \brief True if the coalescer should aggressively coalesce global copies
90 /// in favor of keeping local copies.
91 bool JoinGlobalCopies;
93 /// \brief True if the coalescer should aggressively coalesce fall-thru
94 /// blocks exclusively containing copies.
97 /// WorkList - Copy instructions yet to be coalesced.
98 SmallVector<MachineInstr*, 8> WorkList;
99 SmallVector<MachineInstr*, 8> LocalWorkList;
101 /// ErasedInstrs - Set of instruction pointers that have been erased, and
102 /// that may be present in WorkList.
103 SmallPtrSet<MachineInstr*, 8> ErasedInstrs;
105 /// Dead instructions that are about to be deleted.
106 SmallVector<MachineInstr*, 8> DeadDefs;
108 /// Virtual registers to be considered for register class inflation.
109 SmallVector<unsigned, 8> InflateRegs;
111 /// Recursively eliminate dead defs in DeadDefs.
112 void eliminateDeadDefs();
114 /// LiveRangeEdit callback.
115 void LRE_WillEraseInstruction(MachineInstr *MI);
117 /// coalesceLocals - coalesce the LocalWorkList.
118 void coalesceLocals();
120 /// joinAllIntervals - join compatible live intervals
121 void joinAllIntervals();
123 /// copyCoalesceInMBB - Coalesce copies in the specified MBB, putting
124 /// copies that cannot yet be coalesced into WorkList.
125 void copyCoalesceInMBB(MachineBasicBlock *MBB);
127 /// copyCoalesceWorkList - Try to coalesce all copies in CurrList. Return
128 /// true if any progress was made.
129 bool copyCoalesceWorkList(MutableArrayRef<MachineInstr*> CurrList);
131 /// joinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
132 /// which are the src/dst of the copy instruction CopyMI. This returns
133 /// true if the copy was successfully coalesced away. If it is not
134 /// currently possible to coalesce this interval, but it may be possible if
135 /// other things get coalesced, then it returns true by reference in
137 bool joinCopy(MachineInstr *TheCopy, bool &Again);
139 /// joinIntervals - Attempt to join these two intervals. On failure, this
140 /// returns false. The output "SrcInt" will not have been modified, so we
141 /// can use this information below to update aliases.
142 bool joinIntervals(CoalescerPair &CP);
144 /// Attempt joining two virtual registers. Return true on success.
145 bool joinVirtRegs(CoalescerPair &CP);
147 /// Attempt joining with a reserved physreg.
148 bool joinReservedPhysReg(CoalescerPair &CP);
150 /// adjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
151 /// the source value number is defined by a copy from the destination reg
152 /// see if we can merge these two destination reg valno# into a single
153 /// value number, eliminating a copy.
154 bool adjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
156 /// hasOtherReachingDefs - Return true if there are definitions of IntB
157 /// other than BValNo val# that can reach uses of AValno val# of IntA.
158 bool hasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
159 VNInfo *AValNo, VNInfo *BValNo);
161 /// removeCopyByCommutingDef - We found a non-trivially-coalescable copy.
162 /// If the source value number is defined by a commutable instruction and
163 /// its other operand is coalesced to the copy dest register, see if we
164 /// can transform the copy into a noop by commuting the definition.
165 bool removeCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI);
167 /// reMaterializeTrivialDef - If the source of a copy is defined by a
168 /// trivial computation, replace the copy by rematerialize the definition.
169 bool reMaterializeTrivialDef(CoalescerPair &CP, MachineInstr *CopyMI,
172 /// canJoinPhys - Return true if a physreg copy should be joined.
173 bool canJoinPhys(const CoalescerPair &CP);
175 /// updateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
176 /// update the subregister number if it is not zero. If DstReg is a
177 /// physical register and the existing subregister number of the def / use
178 /// being updated is not zero, make sure to set it to the correct physical
180 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
182 /// eliminateUndefCopy - Handle copies of undef values.
183 bool eliminateUndefCopy(MachineInstr *CopyMI, const CoalescerPair &CP);
186 static char ID; // Class identification, replacement for typeinfo
187 RegisterCoalescer() : MachineFunctionPass(ID) {
188 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
191 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
193 virtual void releaseMemory();
195 /// runOnMachineFunction - pass entry point
196 virtual bool runOnMachineFunction(MachineFunction&);
198 /// print - Implement the dump method.
199 virtual void print(raw_ostream &O, const Module* = 0) const;
201 } /// end anonymous namespace
203 char &llvm::RegisterCoalescerID = RegisterCoalescer::ID;
205 INITIALIZE_PASS_BEGIN(RegisterCoalescer, "simple-register-coalescing",
206 "Simple Register Coalescing", false, false)
207 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
208 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
209 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
210 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
211 INITIALIZE_PASS_END(RegisterCoalescer, "simple-register-coalescing",
212 "Simple Register Coalescing", false, false)
214 char RegisterCoalescer::ID = 0;
216 static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI,
217 unsigned &Src, unsigned &Dst,
218 unsigned &SrcSub, unsigned &DstSub) {
220 Dst = MI->getOperand(0).getReg();
221 DstSub = MI->getOperand(0).getSubReg();
222 Src = MI->getOperand(1).getReg();
223 SrcSub = MI->getOperand(1).getSubReg();
224 } else if (MI->isSubregToReg()) {
225 Dst = MI->getOperand(0).getReg();
226 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(),
227 MI->getOperand(3).getImm());
228 Src = MI->getOperand(2).getReg();
229 SrcSub = MI->getOperand(2).getSubReg();
235 // Return true if this block should be vacated by the coalescer to eliminate
236 // branches. The important cases to handle in the coalescer are critical edges
237 // split during phi elimination which contain only copies. Simple blocks that
238 // contain non-branches should also be vacated, but this can be handled by an
239 // earlier pass similar to early if-conversion.
240 static bool isSplitEdge(const MachineBasicBlock *MBB) {
241 if (MBB->pred_size() != 1 || MBB->succ_size() != 1)
244 for (MachineBasicBlock::const_iterator MII = MBB->begin(), E = MBB->end();
246 if (!MII->isCopyLike() && !MII->isUnconditionalBranch())
252 bool CoalescerPair::setRegisters(const MachineInstr *MI) {
256 Flipped = CrossClass = false;
258 unsigned Src, Dst, SrcSub, DstSub;
259 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
261 Partial = SrcSub || DstSub;
263 // If one register is a physreg, it must be Dst.
264 if (TargetRegisterInfo::isPhysicalRegister(Src)) {
265 if (TargetRegisterInfo::isPhysicalRegister(Dst))
268 std::swap(SrcSub, DstSub);
272 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
274 if (TargetRegisterInfo::isPhysicalRegister(Dst)) {
275 // Eliminate DstSub on a physreg.
277 Dst = TRI.getSubReg(Dst, DstSub);
278 if (!Dst) return false;
282 // Eliminate SrcSub by picking a corresponding Dst superregister.
284 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
285 if (!Dst) return false;
287 } else if (!MRI.getRegClass(Src)->contains(Dst)) {
291 // Both registers are virtual.
292 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
293 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
295 // Both registers have subreg indices.
296 if (SrcSub && DstSub) {
297 // Copies between different sub-registers are never coalescable.
298 if (Src == Dst && SrcSub != DstSub)
301 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
306 // SrcReg will be merged with a sub-register of DstReg.
308 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
310 // DstReg will be merged with a sub-register of SrcReg.
312 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
314 // This is a straight copy without sub-registers.
315 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
318 // The combined constraint may be impossible to satisfy.
322 // Prefer SrcReg to be a sub-register of DstReg.
323 // FIXME: Coalescer should support subregs symmetrically.
324 if (DstIdx && !SrcIdx) {
326 std::swap(SrcIdx, DstIdx);
330 CrossClass = NewRC != DstRC || NewRC != SrcRC;
332 // Check our invariants
333 assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual");
334 assert(!(TargetRegisterInfo::isPhysicalRegister(Dst) && DstSub) &&
335 "Cannot have a physical SubIdx");
341 bool CoalescerPair::flip() {
342 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
344 std::swap(SrcReg, DstReg);
345 std::swap(SrcIdx, DstIdx);
350 bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
353 unsigned Src, Dst, SrcSub, DstSub;
354 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
357 // Find the virtual register that is SrcReg.
360 std::swap(SrcSub, DstSub);
361 } else if (Src != SrcReg) {
365 // Now check that Dst matches DstReg.
366 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
367 if (!TargetRegisterInfo::isPhysicalRegister(Dst))
369 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state.");
370 // DstSub could be set for a physreg from INSERT_SUBREG.
372 Dst = TRI.getSubReg(Dst, DstSub);
375 return DstReg == Dst;
376 // This is a partial register copy. Check that the parts match.
377 return TRI.getSubReg(DstReg, SrcSub) == Dst;
379 // DstReg is virtual.
382 // Registers match, do the subregisters line up?
383 return TRI.composeSubRegIndices(SrcIdx, SrcSub) ==
384 TRI.composeSubRegIndices(DstIdx, DstSub);
388 void RegisterCoalescer::getAnalysisUsage(AnalysisUsage &AU) const {
389 AU.setPreservesCFG();
390 AU.addRequired<AliasAnalysis>();
391 AU.addRequired<LiveIntervals>();
392 AU.addPreserved<LiveIntervals>();
393 AU.addPreserved<SlotIndexes>();
394 AU.addRequired<MachineLoopInfo>();
395 AU.addPreserved<MachineLoopInfo>();
396 AU.addPreservedID(MachineDominatorsID);
397 MachineFunctionPass::getAnalysisUsage(AU);
400 void RegisterCoalescer::eliminateDeadDefs() {
401 SmallVector<unsigned, 8> NewRegs;
402 LiveRangeEdit(0, NewRegs, *MF, *LIS, 0, this).eliminateDeadDefs(DeadDefs);
405 // Callback from eliminateDeadDefs().
406 void RegisterCoalescer::LRE_WillEraseInstruction(MachineInstr *MI) {
407 // MI may be in WorkList. Make sure we don't visit it.
408 ErasedInstrs.insert(MI);
411 /// adjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
412 /// being the source and IntB being the dest, thus this defines a value number
413 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
414 /// see if we can merge these two pieces of B into a single value number,
415 /// eliminating a copy. For example:
419 /// B1 = A3 <- this copy
421 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
422 /// value number to be replaced with B0 (which simplifies the B liveinterval).
424 /// This returns true if an interval was modified.
426 bool RegisterCoalescer::adjustCopiesBackFrom(const CoalescerPair &CP,
427 MachineInstr *CopyMI) {
428 assert(!CP.isPartial() && "This doesn't work for partial copies.");
429 assert(!CP.isPhys() && "This doesn't work for physreg copies.");
432 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
434 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
435 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
437 // BValNo is a value number in B that is defined by a copy from A. 'B1' in
438 // the example above.
439 LiveInterval::iterator BS = IntB.FindSegmentContaining(CopyIdx);
440 if (BS == IntB.end()) return false;
441 VNInfo *BValNo = BS->valno;
443 // Get the location that B is defined at. Two options: either this value has
444 // an unknown definition point or it is defined at CopyIdx. If unknown, we
446 if (BValNo->def != CopyIdx) return false;
448 // AValNo is the value number in A that defines the copy, A3 in the example.
449 SlotIndex CopyUseIdx = CopyIdx.getRegSlot(true);
450 LiveInterval::iterator AS = IntA.FindSegmentContaining(CopyUseIdx);
451 // The live segment might not exist after fun with physreg coalescing.
452 if (AS == IntA.end()) return false;
453 VNInfo *AValNo = AS->valno;
455 // If AValNo is defined as a copy from IntB, we can potentially process this.
456 // Get the instruction that defines this value number.
457 MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def);
458 // Don't allow any partial copies, even if isCoalescable() allows them.
459 if (!CP.isCoalescable(ACopyMI) || !ACopyMI->isFullCopy())
462 // Get the Segment in IntB that this value number starts with.
463 LiveInterval::iterator ValS =
464 IntB.FindSegmentContaining(AValNo->def.getPrevSlot());
465 if (ValS == IntB.end())
468 // Make sure that the end of the live segment is inside the same block as
470 MachineInstr *ValSEndInst =
471 LIS->getInstructionFromIndex(ValS->end.getPrevSlot());
472 if (!ValSEndInst || ValSEndInst->getParent() != CopyMI->getParent())
475 // Okay, we now know that ValS ends in the same block that the CopyMI
476 // live-range starts. If there are no intervening live segments between them
477 // in IntB, we can merge them.
478 if (ValS+1 != BS) return false;
480 DEBUG(dbgs() << "Extending: " << PrintReg(IntB.reg, TRI));
482 SlotIndex FillerStart = ValS->end, FillerEnd = BS->start;
483 // We are about to delete CopyMI, so need to remove it as the 'instruction
484 // that defines this value #'. Update the valnum with the new defining
486 BValNo->def = FillerStart;
488 // Okay, we can merge them. We need to insert a new liverange:
489 // [ValS.end, BS.begin) of either value number, then we merge the
490 // two value numbers.
491 IntB.addSegment(LiveInterval::Segment(FillerStart, FillerEnd, BValNo));
493 // Okay, merge "B1" into the same value number as "B0".
494 if (BValNo != ValS->valno)
495 IntB.MergeValueNumberInto(BValNo, ValS->valno);
496 DEBUG(dbgs() << " result = " << IntB << '\n');
498 // If the source instruction was killing the source register before the
499 // merge, unset the isKill marker given the live range has been extended.
500 int UIdx = ValSEndInst->findRegisterUseOperandIdx(IntB.reg, true);
502 ValSEndInst->getOperand(UIdx).setIsKill(false);
505 // Rewrite the copy. If the copy instruction was killing the destination
506 // register before the merge, find the last use and trim the live range. That
507 // will also add the isKill marker.
508 CopyMI->substituteRegister(IntA.reg, IntB.reg, 0, *TRI);
509 if (AS->end == CopyIdx)
510 LIS->shrinkToUses(&IntA);
516 /// hasOtherReachingDefs - Return true if there are definitions of IntB
517 /// other than BValNo val# that can reach uses of AValno val# of IntA.
518 bool RegisterCoalescer::hasOtherReachingDefs(LiveInterval &IntA,
522 // If AValNo has PHI kills, conservatively assume that IntB defs can reach
524 if (LIS->hasPHIKill(IntA, AValNo))
527 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
529 if (AI->valno != AValNo) continue;
530 LiveInterval::iterator BI =
531 std::upper_bound(IntB.begin(), IntB.end(), AI->start);
532 if (BI != IntB.begin())
534 for (; BI != IntB.end() && AI->end >= BI->start; ++BI) {
535 if (BI->valno == BValNo)
537 if (BI->start <= AI->start && BI->end > AI->start)
539 if (BI->start > AI->start && BI->start < AI->end)
546 /// removeCopyByCommutingDef - We found a non-trivially-coalescable copy with
547 /// IntA being the source and IntB being the dest, thus this defines a value
548 /// number in IntB. If the source value number (in IntA) is defined by a
549 /// commutable instruction and its other operand is coalesced to the copy dest
550 /// register, see if we can transform the copy into a noop by commuting the
551 /// definition. For example,
553 /// A3 = op A2 B0<kill>
555 /// B1 = A3 <- this copy
557 /// = op A3 <- more uses
561 /// B2 = op B0 A2<kill>
563 /// B1 = B2 <- now an identify copy
565 /// = op B2 <- more uses
567 /// This returns true if an interval was modified.
569 bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
570 MachineInstr *CopyMI) {
571 assert (!CP.isPhys());
573 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
576 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
578 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
580 // BValNo is a value number in B that is defined by a copy from A. 'B1' in
581 // the example above.
582 VNInfo *BValNo = IntB.getVNInfoAt(CopyIdx);
583 if (!BValNo || BValNo->def != CopyIdx)
586 // AValNo is the value number in A that defines the copy, A3 in the example.
587 VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx.getRegSlot(true));
588 assert(AValNo && "COPY source not live");
589 if (AValNo->isPHIDef() || AValNo->isUnused())
591 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
594 if (!DefMI->isCommutable())
596 // If DefMI is a two-address instruction then commuting it will change the
597 // destination register.
598 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
599 assert(DefIdx != -1);
601 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
603 unsigned Op1, Op2, NewDstIdx;
604 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
608 else if (Op2 == UseOpIdx)
613 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
614 unsigned NewReg = NewDstMO.getReg();
615 if (NewReg != IntB.reg || !IntB.Query(AValNo->def).isKill())
618 // Make sure there are no other definitions of IntB that would reach the
619 // uses which the new definition can reach.
620 if (hasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
623 // If some of the uses of IntA.reg is already coalesced away, return false.
624 // It's not possible to determine whether it's safe to perform the coalescing.
625 for (MachineRegisterInfo::use_nodbg_iterator UI =
626 MRI->use_nodbg_begin(IntA.reg),
627 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
628 MachineInstr *UseMI = &*UI;
629 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI);
630 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx);
631 if (US == IntA.end() || US->valno != AValNo)
633 // If this use is tied to a def, we can't rewrite the register.
634 if (UseMI->isRegTiedToDefOperand(UI.getOperandNo()))
638 DEBUG(dbgs() << "\tremoveCopyByCommutingDef: " << AValNo->def << '\t'
641 // At this point we have decided that it is legal to do this
642 // transformation. Start by commuting the instruction.
643 MachineBasicBlock *MBB = DefMI->getParent();
644 MachineInstr *NewMI = TII->commuteInstruction(DefMI);
647 if (TargetRegisterInfo::isVirtualRegister(IntA.reg) &&
648 TargetRegisterInfo::isVirtualRegister(IntB.reg) &&
649 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
651 if (NewMI != DefMI) {
652 LIS->ReplaceMachineInstrInMaps(DefMI, NewMI);
653 MachineBasicBlock::iterator Pos = DefMI;
654 MBB->insert(Pos, NewMI);
657 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
658 NewMI->getOperand(OpIdx).setIsKill();
660 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
669 // Update uses of IntA of the specific Val# with IntB.
670 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(IntA.reg),
671 UE = MRI->use_end(); UI != UE;) {
672 MachineOperand &UseMO = UI.getOperand();
673 MachineInstr *UseMI = &*UI;
675 if (UseMI->isDebugValue()) {
676 // FIXME These don't have an instruction index. Not clear we have enough
677 // info to decide whether to do this replacement or not. For now do it.
678 UseMO.setReg(NewReg);
681 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true);
682 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx);
683 if (US == IntA.end() || US->valno != AValNo)
685 // Kill flags are no longer accurate. They are recomputed after RA.
686 UseMO.setIsKill(false);
687 if (TargetRegisterInfo::isPhysicalRegister(NewReg))
688 UseMO.substPhysReg(NewReg, *TRI);
690 UseMO.setReg(NewReg);
693 if (!UseMI->isCopy())
695 if (UseMI->getOperand(0).getReg() != IntB.reg ||
696 UseMI->getOperand(0).getSubReg())
699 // This copy will become a noop. If it's defining a new val#, merge it into
701 SlotIndex DefIdx = UseIdx.getRegSlot();
702 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
705 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
706 assert(DVNI->def == DefIdx);
707 BValNo = IntB.MergeValueNumberInto(BValNo, DVNI);
708 ErasedInstrs.insert(UseMI);
709 LIS->RemoveMachineInstrFromMaps(UseMI);
710 UseMI->eraseFromParent();
713 // Extend BValNo by merging in IntA live segments of AValNo. Val# definition
715 VNInfo *ValNo = BValNo;
716 ValNo->def = AValNo->def;
717 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
719 if (AI->valno != AValNo) continue;
720 IntB.addSegment(LiveInterval::Segment(AI->start, AI->end, ValNo));
722 DEBUG(dbgs() << "\t\textended: " << IntB << '\n');
724 IntA.removeValNo(AValNo);
725 DEBUG(dbgs() << "\t\ttrimmed: " << IntA << '\n');
730 /// reMaterializeTrivialDef - If the source of a copy is defined by a trivial
731 /// computation, replace the copy by rematerialize the definition.
732 bool RegisterCoalescer::reMaterializeTrivialDef(CoalescerPair &CP,
733 MachineInstr *CopyMI,
736 unsigned SrcReg = CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg();
737 unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx();
738 unsigned DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg();
739 unsigned DstIdx = CP.isFlipped() ? CP.getSrcIdx() : CP.getDstIdx();
740 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
743 LiveInterval &SrcInt = LIS->getInterval(SrcReg);
744 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI);
745 VNInfo *ValNo = SrcInt.Query(CopyIdx).valueIn();
746 assert(ValNo && "CopyMI input register not live");
747 if (ValNo->isPHIDef() || ValNo->isUnused())
749 MachineInstr *DefMI = LIS->getInstructionFromIndex(ValNo->def);
752 if (DefMI->isCopyLike()) {
756 if (!DefMI->isAsCheapAsAMove())
758 if (!TII->isTriviallyReMaterializable(DefMI, AA))
760 bool SawStore = false;
761 if (!DefMI->isSafeToMove(TII, AA, SawStore))
763 const MCInstrDesc &MCID = DefMI->getDesc();
764 if (MCID.getNumDefs() != 1)
766 // Only support subregister destinations when the def is read-undef.
767 MachineOperand &DstOperand = CopyMI->getOperand(0);
768 unsigned CopyDstReg = DstOperand.getReg();
769 if (DstOperand.getSubReg() && !DstOperand.isUndef())
772 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF);
773 if (!DefMI->isImplicitDef()) {
774 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
775 unsigned NewDstReg = DstReg;
777 unsigned NewDstIdx = TRI->composeSubRegIndices(CP.getSrcIdx(),
778 DefMI->getOperand(0).getSubReg());
780 NewDstReg = TRI->getSubReg(DstReg, NewDstIdx);
782 // Finally, make sure that the physical subregister that will be
783 // constructed later is permitted for the instruction.
784 if (!DefRC->contains(NewDstReg))
787 // Theoretically, some stack frame reference could exist. Just make sure
788 // it hasn't actually happened.
789 assert(TargetRegisterInfo::isVirtualRegister(DstReg) &&
790 "Only expect to deal with virtual or physical registers");
794 MachineBasicBlock *MBB = CopyMI->getParent();
795 MachineBasicBlock::iterator MII =
796 llvm::next(MachineBasicBlock::iterator(CopyMI));
797 TII->reMaterialize(*MBB, MII, DstReg, SrcIdx, DefMI, *TRI);
798 MachineInstr *NewMI = prior(MII);
800 LIS->ReplaceMachineInstrInMaps(CopyMI, NewMI);
801 CopyMI->eraseFromParent();
802 ErasedInstrs.insert(CopyMI);
804 // NewMI may have dead implicit defs (E.g. EFLAGS for MOV<bits>r0 on X86).
805 // We need to remember these so we can add intervals once we insert
806 // NewMI into SlotIndexes.
807 SmallVector<unsigned, 4> NewMIImplDefs;
808 for (unsigned i = NewMI->getDesc().getNumOperands(),
809 e = NewMI->getNumOperands(); i != e; ++i) {
810 MachineOperand &MO = NewMI->getOperand(i);
812 assert(MO.isDef() && MO.isImplicit() && MO.isDead() &&
813 TargetRegisterInfo::isPhysicalRegister(MO.getReg()));
814 NewMIImplDefs.push_back(MO.getReg());
818 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
819 unsigned NewIdx = NewMI->getOperand(0).getSubReg();
820 const TargetRegisterClass *RCForInst;
822 RCForInst = TRI->getMatchingSuperRegClass(MRI->getRegClass(DstReg), DefRC,
825 if (MRI->constrainRegClass(DstReg, DefRC)) {
826 // The materialized instruction is quite capable of setting DstReg
827 // directly, but it may still have a now-trivial subregister index which
829 NewMI->getOperand(0).setSubReg(0);
830 } else if (NewIdx && RCForInst) {
831 // The subreg index on NewMI is essential; we still have to make sure
832 // DstReg:idx is in a class that NewMI can use.
833 MRI->constrainRegClass(DstReg, RCForInst);
835 // DstReg is actually incompatible with NewMI, we have to move to a
836 // super-reg's class. This could come from a sequence like:
838 // GR8 = COPY GR32:sub_8
839 MRI->setRegClass(DstReg, CP.getNewRC());
840 updateRegDefsUses(DstReg, DstReg, DstIdx);
841 NewMI->getOperand(0).setSubReg(
842 TRI->composeSubRegIndices(SrcIdx, DefMI->getOperand(0).getSubReg()));
844 } else if (NewMI->getOperand(0).getReg() != CopyDstReg) {
845 // The New instruction may be defining a sub-register of what's actually
846 // been asked for. If so it must implicitly define the whole thing.
847 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
848 "Only expect virtual or physical registers in remat");
849 NewMI->getOperand(0).setIsDead(true);
850 NewMI->addOperand(MachineOperand::CreateReg(CopyDstReg,
856 if (NewMI->getOperand(0).getSubReg())
857 NewMI->getOperand(0).setIsUndef();
859 // CopyMI may have implicit operands, transfer them over to the newly
860 // rematerialized instruction. And update implicit def interval valnos.
861 for (unsigned i = CopyMI->getDesc().getNumOperands(),
862 e = CopyMI->getNumOperands(); i != e; ++i) {
863 MachineOperand &MO = CopyMI->getOperand(i);
865 assert(MO.isImplicit() && "No explicit operands after implict operands.");
866 // Discard VReg implicit defs.
867 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
868 NewMI->addOperand(MO);
873 SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
874 for (unsigned i = 0, e = NewMIImplDefs.size(); i != e; ++i) {
875 unsigned Reg = NewMIImplDefs[i];
876 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
877 if (LiveInterval *LI = LIS->getCachedRegUnit(*Units))
878 LI->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());
881 DEBUG(dbgs() << "Remat: " << *NewMI);
884 // The source interval can become smaller because we removed a use.
885 LIS->shrinkToUses(&SrcInt, &DeadDefs);
886 if (!DeadDefs.empty())
892 /// eliminateUndefCopy - ProcessImpicitDefs may leave some copies of <undef>
893 /// values, it only removes local variables. When we have a copy like:
895 /// %vreg1 = COPY %vreg2<undef>
897 /// We delete the copy and remove the corresponding value number from %vreg1.
898 /// Any uses of that value number are marked as <undef>.
899 bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI,
900 const CoalescerPair &CP) {
901 SlotIndex Idx = LIS->getInstructionIndex(CopyMI);
902 LiveInterval *SrcInt = &LIS->getInterval(CP.getSrcReg());
903 if (SrcInt->liveAt(Idx))
905 LiveInterval *DstInt = &LIS->getInterval(CP.getDstReg());
906 if (DstInt->liveAt(Idx))
909 // No intervals are live-in to CopyMI - it is undef.
914 VNInfo *DeadVNI = DstInt->getVNInfoAt(Idx.getRegSlot());
915 assert(DeadVNI && "No value defined in DstInt");
916 DstInt->removeValNo(DeadVNI);
918 // Find new undef uses.
919 for (MachineRegisterInfo::reg_nodbg_iterator
920 I = MRI->reg_nodbg_begin(DstInt->reg), E = MRI->reg_nodbg_end();
922 MachineOperand &MO = I.getOperand();
923 if (MO.isDef() || MO.isUndef())
925 MachineInstr *MI = MO.getParent();
926 SlotIndex Idx = LIS->getInstructionIndex(MI);
927 if (DstInt->liveAt(Idx))
930 DEBUG(dbgs() << "\tnew undef: " << Idx << '\t' << *MI);
935 /// updateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
936 /// update the subregister number if it is not zero. If DstReg is a
937 /// physical register and the existing subregister number of the def / use
938 /// being updated is not zero, make sure to set it to the correct physical
940 void RegisterCoalescer::updateRegDefsUses(unsigned SrcReg,
943 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
944 LiveInterval *DstInt = DstIsPhys ? 0 : &LIS->getInterval(DstReg);
946 SmallPtrSet<MachineInstr*, 8> Visited;
947 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(SrcReg);
948 MachineInstr *UseMI = I.skipInstruction();) {
949 // Each instruction can only be rewritten once because sub-register
950 // composition is not always idempotent. When SrcReg != DstReg, rewriting
951 // the UseMI operands removes them from the SrcReg use-def chain, but when
952 // SrcReg is DstReg we could encounter UseMI twice if it has multiple
953 // operands mentioning the virtual register.
954 if (SrcReg == DstReg && !Visited.insert(UseMI))
957 SmallVector<unsigned,8> Ops;
959 tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
961 // If SrcReg wasn't read, it may still be the case that DstReg is live-in
962 // because SrcReg is a sub-register.
963 if (DstInt && !Reads && SubIdx)
964 Reads = DstInt->liveAt(LIS->getInstructionIndex(UseMI));
966 // Replace SrcReg with DstReg in all UseMI operands.
967 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
968 MachineOperand &MO = UseMI->getOperand(Ops[i]);
970 // Adjust <undef> flags in case of sub-register joins. We don't want to
971 // turn a full def into a read-modify-write sub-register def and vice
973 if (SubIdx && MO.isDef())
974 MO.setIsUndef(!Reads);
977 MO.substPhysReg(DstReg, *TRI);
979 MO.substVirtReg(DstReg, SubIdx, *TRI);
983 dbgs() << "\t\tupdated: ";
984 if (!UseMI->isDebugValue())
985 dbgs() << LIS->getInstructionIndex(UseMI) << "\t";
991 /// canJoinPhys - Return true if a copy involving a physreg should be joined.
992 bool RegisterCoalescer::canJoinPhys(const CoalescerPair &CP) {
993 /// Always join simple intervals that are defined by a single copy from a
994 /// reserved register. This doesn't increase register pressure, so it is
995 /// always beneficial.
996 if (!MRI->isReserved(CP.getDstReg())) {
997 DEBUG(dbgs() << "\tCan only merge into reserved registers.\n");
1001 LiveInterval &JoinVInt = LIS->getInterval(CP.getSrcReg());
1002 if (CP.isFlipped() && JoinVInt.containsOneValue())
1005 DEBUG(dbgs() << "\tCannot join defs into reserved register.\n");
1009 /// joinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1010 /// which are the src/dst of the copy instruction CopyMI. This returns true
1011 /// if the copy was successfully coalesced away. If it is not currently
1012 /// possible to coalesce this interval, but it may be possible if other
1013 /// things get coalesced, then it returns true by reference in 'Again'.
1014 bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
1017 DEBUG(dbgs() << LIS->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
1019 CoalescerPair CP(*TRI);
1020 if (!CP.setRegisters(CopyMI)) {
1021 DEBUG(dbgs() << "\tNot coalescable.\n");
1025 // Dead code elimination. This really should be handled by MachineDCE, but
1026 // sometimes dead copies slip through, and we can't generate invalid live
1028 if (!CP.isPhys() && CopyMI->allDefsAreDead()) {
1029 DEBUG(dbgs() << "\tCopy is dead.\n");
1030 DeadDefs.push_back(CopyMI);
1031 eliminateDeadDefs();
1035 // Eliminate undefs.
1036 if (!CP.isPhys() && eliminateUndefCopy(CopyMI, CP)) {
1037 DEBUG(dbgs() << "\tEliminated copy of <undef> value.\n");
1038 LIS->RemoveMachineInstrFromMaps(CopyMI);
1039 CopyMI->eraseFromParent();
1040 return false; // Not coalescable.
1043 // Coalesced copies are normally removed immediately, but transformations
1044 // like removeCopyByCommutingDef() can inadvertently create identity copies.
1045 // When that happens, just join the values and remove the copy.
1046 if (CP.getSrcReg() == CP.getDstReg()) {
1047 LiveInterval &LI = LIS->getInterval(CP.getSrcReg());
1048 DEBUG(dbgs() << "\tCopy already coalesced: " << LI << '\n');
1049 LiveQueryResult LRQ = LI.Query(LIS->getInstructionIndex(CopyMI));
1050 if (VNInfo *DefVNI = LRQ.valueDefined()) {
1051 VNInfo *ReadVNI = LRQ.valueIn();
1052 assert(ReadVNI && "No value before copy and no <undef> flag.");
1053 assert(ReadVNI != DefVNI && "Cannot read and define the same value.");
1054 LI.MergeValueNumberInto(DefVNI, ReadVNI);
1055 DEBUG(dbgs() << "\tMerged values: " << LI << '\n');
1057 LIS->RemoveMachineInstrFromMaps(CopyMI);
1058 CopyMI->eraseFromParent();
1062 // Enforce policies.
1064 DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), TRI)
1065 << " with " << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx())
1067 if (!canJoinPhys(CP)) {
1068 // Before giving up coalescing, if definition of source is defined by
1069 // trivial computation, try rematerializing it.
1071 if (reMaterializeTrivialDef(CP, CopyMI, IsDefCopy))
1074 Again = true; // May be possible to coalesce later.
1079 dbgs() << "\tConsidering merging to " << CP.getNewRC()->getName()
1081 if (CP.getDstIdx() && CP.getSrcIdx())
1082 dbgs() << PrintReg(CP.getDstReg()) << " in "
1083 << TRI->getSubRegIndexName(CP.getDstIdx()) << " and "
1084 << PrintReg(CP.getSrcReg()) << " in "
1085 << TRI->getSubRegIndexName(CP.getSrcIdx()) << '\n';
1087 dbgs() << PrintReg(CP.getSrcReg(), TRI) << " in "
1088 << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n';
1091 // When possible, let DstReg be the larger interval.
1092 if (!CP.isPartial() && LIS->getInterval(CP.getSrcReg()).size() >
1093 LIS->getInterval(CP.getDstReg()).size())
1097 // Okay, attempt to join these two intervals. On failure, this returns false.
1098 // Otherwise, if one of the intervals being joined is a physreg, this method
1099 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1100 // been modified, so we can use this information below to update aliases.
1101 if (!joinIntervals(CP)) {
1102 // Coalescing failed.
1104 // If definition of source is defined by trivial computation, try
1105 // rematerializing it.
1107 if (reMaterializeTrivialDef(CP, CopyMI, IsDefCopy))
1110 // If we can eliminate the copy without merging the live segments, do so
1112 if (!CP.isPartial() && !CP.isPhys()) {
1113 if (adjustCopiesBackFrom(CP, CopyMI) ||
1114 removeCopyByCommutingDef(CP, CopyMI)) {
1115 LIS->RemoveMachineInstrFromMaps(CopyMI);
1116 CopyMI->eraseFromParent();
1117 DEBUG(dbgs() << "\tTrivial!\n");
1122 // Otherwise, we are unable to join the intervals.
1123 DEBUG(dbgs() << "\tInterference!\n");
1124 Again = true; // May be possible to coalesce later.
1128 // Coalescing to a virtual register that is of a sub-register class of the
1129 // other. Make sure the resulting register is set to the right register class.
1130 if (CP.isCrossClass()) {
1132 MRI->setRegClass(CP.getDstReg(), CP.getNewRC());
1135 // Removing sub-register copies can ease the register class constraints.
1136 // Make sure we attempt to inflate the register class of DstReg.
1137 if (!CP.isPhys() && RegClassInfo.isProperSubClass(CP.getNewRC()))
1138 InflateRegs.push_back(CP.getDstReg());
1140 // CopyMI has been erased by joinIntervals at this point. Remove it from
1141 // ErasedInstrs since copyCoalesceWorkList() won't add a successful join back
1142 // to the work list. This keeps ErasedInstrs from growing needlessly.
1143 ErasedInstrs.erase(CopyMI);
1145 // Rewrite all SrcReg operands to DstReg.
1146 // Also update DstReg operands to include DstIdx if it is set.
1148 updateRegDefsUses(CP.getDstReg(), CP.getDstReg(), CP.getDstIdx());
1149 updateRegDefsUses(CP.getSrcReg(), CP.getDstReg(), CP.getSrcIdx());
1151 // SrcReg is guaranteed to be the register whose live interval that is
1153 LIS->removeInterval(CP.getSrcReg());
1155 // Update regalloc hint.
1156 TRI->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
1159 dbgs() << "\tJoined. Result = " << PrintReg(CP.getDstReg(), TRI);
1161 dbgs() << LIS->getInterval(CP.getDstReg());
1169 /// Attempt joining with a reserved physreg.
1170 bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
1171 assert(CP.isPhys() && "Must be a physreg copy");
1172 assert(MRI->isReserved(CP.getDstReg()) && "Not a reserved register");
1173 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
1174 DEBUG(dbgs() << "\t\tRHS = " << PrintReg(CP.getSrcReg()) << ' ' << RHS
1177 assert(CP.isFlipped() && RHS.containsOneValue() &&
1178 "Invalid join with reserved register");
1180 // Optimization for reserved registers like ESP. We can only merge with a
1181 // reserved physreg if RHS has a single value that is a copy of CP.DstReg().
1182 // The live range of the reserved register will look like a set of dead defs
1183 // - we don't properly track the live range of reserved registers.
1185 // Deny any overlapping intervals. This depends on all the reserved
1186 // register live ranges to look like dead defs.
1187 for (MCRegUnitIterator UI(CP.getDstReg(), TRI); UI.isValid(); ++UI)
1188 if (RHS.overlaps(LIS->getRegUnit(*UI))) {
1189 DEBUG(dbgs() << "\t\tInterference: " << PrintRegUnit(*UI, TRI) << '\n');
1193 // Skip any value computations, we are not adding new values to the
1194 // reserved register. Also skip merging the live ranges, the reserved
1195 // register live range doesn't need to be accurate as long as all the
1198 // Delete the identity copy.
1199 MachineInstr *CopyMI = MRI->getVRegDef(RHS.reg);
1200 LIS->RemoveMachineInstrFromMaps(CopyMI);
1201 CopyMI->eraseFromParent();
1203 // We don't track kills for reserved registers.
1204 MRI->clearKillFlags(CP.getSrcReg());
1209 //===----------------------------------------------------------------------===//
1210 // Interference checking and interval joining
1211 //===----------------------------------------------------------------------===//
1213 // In the easiest case, the two live ranges being joined are disjoint, and
1214 // there is no interference to consider. It is quite common, though, to have
1215 // overlapping live ranges, and we need to check if the interference can be
1218 // The live range of a single SSA value forms a sub-tree of the dominator tree.
1219 // This means that two SSA values overlap if and only if the def of one value
1220 // is contained in the live range of the other value. As a special case, the
1221 // overlapping values can be defined at the same index.
1223 // The interference from an overlapping def can be resolved in these cases:
1225 // 1. Coalescable copies. The value is defined by a copy that would become an
1226 // identity copy after joining SrcReg and DstReg. The copy instruction will
1227 // be removed, and the value will be merged with the source value.
1229 // There can be several copies back and forth, causing many values to be
1230 // merged into one. We compute a list of ultimate values in the joined live
1231 // range as well as a mappings from the old value numbers.
1233 // 2. IMPLICIT_DEF. This instruction is only inserted to ensure all PHI
1234 // predecessors have a live out value. It doesn't cause real interference,
1235 // and can be merged into the value it overlaps. Like a coalescable copy, it
1236 // can be erased after joining.
1238 // 3. Copy of external value. The overlapping def may be a copy of a value that
1239 // is already in the other register. This is like a coalescable copy, but
1240 // the live range of the source register must be trimmed after erasing the
1241 // copy instruction:
1244 // %dst = COPY %ext <-- Remove this COPY, trim the live range of %ext.
1246 // 4. Clobbering undefined lanes. Vector registers are sometimes built by
1247 // defining one lane at a time:
1249 // %dst:ssub0<def,read-undef> = FOO
1251 // %dst:ssub1<def> = COPY %src
1253 // The live range of %src overlaps the %dst value defined by FOO, but
1254 // merging %src into %dst:ssub1 is only going to clobber the ssub1 lane
1255 // which was undef anyway.
1257 // The value mapping is more complicated in this case. The final live range
1258 // will have different value numbers for both FOO and BAR, but there is no
1259 // simple mapping from old to new values. It may even be necessary to add
1262 // 5. Clobbering dead lanes. A def may clobber a lane of a vector register that
1263 // is live, but never read. This can happen because we don't compute
1264 // individual live ranges per lane.
1268 // %dst:ssub1<def> = COPY %src
1270 // This kind of interference is only resolved locally. If the clobbered
1271 // lane value escapes the block, the join is aborted.
1274 /// Track information about values in a single virtual register about to be
1275 /// joined. Objects of this class are always created in pairs - one for each
1276 /// side of the CoalescerPair.
1280 // Location of this register in the final joined register.
1281 // Either CP.DstIdx or CP.SrcIdx.
1284 // Values that will be present in the final live range.
1285 SmallVectorImpl<VNInfo*> &NewVNInfo;
1287 const CoalescerPair &CP;
1289 SlotIndexes *Indexes;
1290 const TargetRegisterInfo *TRI;
1292 // Value number assignments. Maps value numbers in LI to entries in NewVNInfo.
1293 // This is suitable for passing to LiveInterval::join().
1294 SmallVector<int, 8> Assignments;
1296 // Conflict resolution for overlapping values.
1297 enum ConflictResolution {
1298 // No overlap, simply keep this value.
1301 // Merge this value into OtherVNI and erase the defining instruction.
1302 // Used for IMPLICIT_DEF, coalescable copies, and copies from external
1306 // Merge this value into OtherVNI but keep the defining instruction.
1307 // This is for the special case where OtherVNI is defined by the same
1311 // Keep this value, and have it replace OtherVNI where possible. This
1312 // complicates value mapping since OtherVNI maps to two different values
1313 // before and after this def.
1314 // Used when clobbering undefined or dead lanes.
1317 // Unresolved conflict. Visit later when all values have been mapped.
1320 // Unresolvable conflict. Abort the join.
1324 // Per-value info for LI. The lane bit masks are all relative to the final
1325 // joined register, so they can be compared directly between SrcReg and
1328 ConflictResolution Resolution;
1330 // Lanes written by this def, 0 for unanalyzed values.
1331 unsigned WriteLanes;
1333 // Lanes with defined values in this register. Other lanes are undef and
1335 unsigned ValidLanes;
1337 // Value in LI being redefined by this def.
1340 // Value in the other live range that overlaps this def, if any.
1343 // Is this value an IMPLICIT_DEF that can be erased?
1345 // IMPLICIT_DEF values should only exist at the end of a basic block that
1346 // is a predecessor to a phi-value. These IMPLICIT_DEF instructions can be
1347 // safely erased if they are overlapping a live value in the other live
1350 // Weird control flow graphs and incomplete PHI handling in
1351 // ProcessImplicitDefs can very rarely create IMPLICIT_DEF values with
1352 // longer live ranges. Such IMPLICIT_DEF values should be treated like
1354 bool ErasableImplicitDef;
1356 // True when the live range of this value will be pruned because of an
1357 // overlapping CR_Replace value in the other live range.
1360 // True once Pruned above has been computed.
1361 bool PrunedComputed;
1363 Val() : Resolution(CR_Keep), WriteLanes(0), ValidLanes(0),
1364 RedefVNI(0), OtherVNI(0), ErasableImplicitDef(false),
1365 Pruned(false), PrunedComputed(false) {}
1367 bool isAnalyzed() const { return WriteLanes != 0; }
1370 // One entry per value number in LI.
1371 SmallVector<Val, 8> Vals;
1373 unsigned computeWriteLanes(const MachineInstr *DefMI, bool &Redef);
1374 VNInfo *stripCopies(VNInfo *VNI);
1375 ConflictResolution analyzeValue(unsigned ValNo, JoinVals &Other);
1376 void computeAssignment(unsigned ValNo, JoinVals &Other);
1377 bool taintExtent(unsigned, unsigned, JoinVals&,
1378 SmallVectorImpl<std::pair<SlotIndex, unsigned> >&);
1379 bool usesLanes(MachineInstr *MI, unsigned, unsigned, unsigned);
1380 bool isPrunedValue(unsigned ValNo, JoinVals &Other);
1383 JoinVals(LiveInterval &li, unsigned subIdx,
1384 SmallVectorImpl<VNInfo*> &newVNInfo,
1385 const CoalescerPair &cp,
1387 const TargetRegisterInfo *tri)
1388 : LI(li), SubIdx(subIdx), NewVNInfo(newVNInfo), CP(cp), LIS(lis),
1389 Indexes(LIS->getSlotIndexes()), TRI(tri),
1390 Assignments(LI.getNumValNums(), -1), Vals(LI.getNumValNums())
1393 /// Analyze defs in LI and compute a value mapping in NewVNInfo.
1394 /// Returns false if any conflicts were impossible to resolve.
1395 bool mapValues(JoinVals &Other);
1397 /// Try to resolve conflicts that require all values to be mapped.
1398 /// Returns false if any conflicts were impossible to resolve.
1399 bool resolveConflicts(JoinVals &Other);
1401 /// Prune the live range of values in Other.LI where they would conflict with
1402 /// CR_Replace values in LI. Collect end points for restoring the live range
1404 void pruneValues(JoinVals &Other, SmallVectorImpl<SlotIndex> &EndPoints);
1406 /// Erase any machine instructions that have been coalesced away.
1407 /// Add erased instructions to ErasedInstrs.
1408 /// Add foreign virtual registers to ShrinkRegs if their live range ended at
1409 /// the erased instrs.
1410 void eraseInstrs(SmallPtrSet<MachineInstr*, 8> &ErasedInstrs,
1411 SmallVectorImpl<unsigned> &ShrinkRegs);
1413 /// Get the value assignments suitable for passing to LiveInterval::join.
1414 const int *getAssignments() const { return Assignments.data(); }
1416 } // end anonymous namespace
1418 /// Compute the bitmask of lanes actually written by DefMI.
1419 /// Set Redef if there are any partial register definitions that depend on the
1420 /// previous value of the register.
1421 unsigned JoinVals::computeWriteLanes(const MachineInstr *DefMI, bool &Redef) {
1423 for (ConstMIOperands MO(DefMI); MO.isValid(); ++MO) {
1424 if (!MO->isReg() || MO->getReg() != LI.reg || !MO->isDef())
1426 L |= TRI->getSubRegIndexLaneMask(
1427 TRI->composeSubRegIndices(SubIdx, MO->getSubReg()));
1434 /// Find the ultimate value that VNI was copied from.
1435 VNInfo *JoinVals::stripCopies(VNInfo *VNI) {
1436 while (!VNI->isPHIDef()) {
1437 MachineInstr *MI = Indexes->getInstructionFromIndex(VNI->def);
1438 assert(MI && "No defining instruction");
1439 if (!MI->isFullCopy())
1441 unsigned Reg = MI->getOperand(1).getReg();
1442 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1444 LiveQueryResult LRQ = LIS->getInterval(Reg).Query(VNI->def);
1447 VNI = LRQ.valueIn();
1452 /// Analyze ValNo in this live range, and set all fields of Vals[ValNo].
1453 /// Return a conflict resolution when possible, but leave the hard cases as
1455 /// Recursively calls computeAssignment() on this and Other, guaranteeing that
1456 /// both OtherVNI and RedefVNI have been analyzed and mapped before returning.
1457 /// The recursion always goes upwards in the dominator tree, making loops
1459 JoinVals::ConflictResolution
1460 JoinVals::analyzeValue(unsigned ValNo, JoinVals &Other) {
1461 Val &V = Vals[ValNo];
1462 assert(!V.isAnalyzed() && "Value has already been analyzed!");
1463 VNInfo *VNI = LI.getValNumInfo(ValNo);
1464 if (VNI->isUnused()) {
1469 // Get the instruction defining this value, compute the lanes written.
1470 const MachineInstr *DefMI = 0;
1471 if (VNI->isPHIDef()) {
1472 // Conservatively assume that all lanes in a PHI are valid.
1473 V.ValidLanes = V.WriteLanes = TRI->getSubRegIndexLaneMask(SubIdx);
1475 DefMI = Indexes->getInstructionFromIndex(VNI->def);
1477 V.ValidLanes = V.WriteLanes = computeWriteLanes(DefMI, Redef);
1479 // If this is a read-modify-write instruction, there may be more valid
1480 // lanes than the ones written by this instruction.
1481 // This only covers partial redef operands. DefMI may have normal use
1482 // operands reading the register. They don't contribute valid lanes.
1484 // This adds ssub1 to the set of valid lanes in %src:
1486 // %src:ssub1<def> = FOO
1488 // This leaves only ssub1 valid, making any other lanes undef:
1490 // %src:ssub1<def,read-undef> = FOO %src:ssub2
1492 // The <read-undef> flag on the def operand means that old lane values are
1495 V.RedefVNI = LI.Query(VNI->def).valueIn();
1496 assert(V.RedefVNI && "Instruction is reading nonexistent value");
1497 computeAssignment(V.RedefVNI->id, Other);
1498 V.ValidLanes |= Vals[V.RedefVNI->id].ValidLanes;
1501 // An IMPLICIT_DEF writes undef values.
1502 if (DefMI->isImplicitDef()) {
1503 // We normally expect IMPLICIT_DEF values to be live only until the end
1504 // of their block. If the value is really live longer and gets pruned in
1505 // another block, this flag is cleared again.
1506 V.ErasableImplicitDef = true;
1507 V.ValidLanes &= ~V.WriteLanes;
1511 // Find the value in Other that overlaps VNI->def, if any.
1512 LiveQueryResult OtherLRQ = Other.LI.Query(VNI->def);
1514 // It is possible that both values are defined by the same instruction, or
1515 // the values are PHIs defined in the same block. When that happens, the two
1516 // values should be merged into one, but not into any preceding value.
1517 // The first value defined or visited gets CR_Keep, the other gets CR_Merge.
1518 if (VNInfo *OtherVNI = OtherLRQ.valueDefined()) {
1519 assert(SlotIndex::isSameInstr(VNI->def, OtherVNI->def) && "Broken LRQ");
1521 // One value stays, the other is merged. Keep the earlier one, or the first
1523 if (OtherVNI->def < VNI->def)
1524 Other.computeAssignment(OtherVNI->id, *this);
1525 else if (VNI->def < OtherVNI->def && OtherLRQ.valueIn()) {
1526 // This is an early-clobber def overlapping a live-in value in the other
1527 // register. Not mergeable.
1528 V.OtherVNI = OtherLRQ.valueIn();
1529 return CR_Impossible;
1531 V.OtherVNI = OtherVNI;
1532 Val &OtherV = Other.Vals[OtherVNI->id];
1533 // Keep this value, check for conflicts when analyzing OtherVNI.
1534 if (!OtherV.isAnalyzed())
1536 // Both sides have been analyzed now.
1537 // Allow overlapping PHI values. Any real interference would show up in a
1538 // predecessor, the PHI itself can't introduce any conflicts.
1539 if (VNI->isPHIDef())
1541 if (V.ValidLanes & OtherV.ValidLanes)
1542 // Overlapping lanes can't be resolved.
1543 return CR_Impossible;
1548 // No simultaneous def. Is Other live at the def?
1549 V.OtherVNI = OtherLRQ.valueIn();
1551 // No overlap, no conflict.
1554 assert(!SlotIndex::isSameInstr(VNI->def, V.OtherVNI->def) && "Broken LRQ");
1556 // We have overlapping values, or possibly a kill of Other.
1557 // Recursively compute assignments up the dominator tree.
1558 Other.computeAssignment(V.OtherVNI->id, *this);
1559 Val &OtherV = Other.Vals[V.OtherVNI->id];
1561 // Check if OtherV is an IMPLICIT_DEF that extends beyond its basic block.
1562 // This shouldn't normally happen, but ProcessImplicitDefs can leave such
1563 // IMPLICIT_DEF instructions behind, and there is nothing wrong with it
1566 // WHen it happens, treat that IMPLICIT_DEF as a normal value, and don't try
1567 // to erase the IMPLICIT_DEF instruction.
1568 if (OtherV.ErasableImplicitDef && DefMI &&
1569 DefMI->getParent() != Indexes->getMBBFromIndex(V.OtherVNI->def)) {
1570 DEBUG(dbgs() << "IMPLICIT_DEF defined at " << V.OtherVNI->def
1571 << " extends into BB#" << DefMI->getParent()->getNumber()
1572 << ", keeping it.\n");
1573 OtherV.ErasableImplicitDef = false;
1576 // Allow overlapping PHI values. Any real interference would show up in a
1577 // predecessor, the PHI itself can't introduce any conflicts.
1578 if (VNI->isPHIDef())
1581 // Check for simple erasable conflicts.
1582 if (DefMI->isImplicitDef())
1585 // Include the non-conflict where DefMI is a coalescable copy that kills
1586 // OtherVNI. We still want the copy erased and value numbers merged.
1587 if (CP.isCoalescable(DefMI)) {
1588 // Some of the lanes copied from OtherVNI may be undef, making them undef
1590 V.ValidLanes &= ~V.WriteLanes | OtherV.ValidLanes;
1594 // This may not be a real conflict if DefMI simply kills Other and defines
1596 if (OtherLRQ.isKill() && OtherLRQ.endPoint() <= VNI->def)
1599 // Handle the case where VNI and OtherVNI can be proven to be identical:
1601 // %other = COPY %ext
1602 // %this = COPY %ext <-- Erase this copy
1604 if (DefMI->isFullCopy() && !CP.isPartial() &&
1605 stripCopies(VNI) == stripCopies(V.OtherVNI))
1608 // If the lanes written by this instruction were all undef in OtherVNI, it is
1609 // still safe to join the live ranges. This can't be done with a simple value
1610 // mapping, though - OtherVNI will map to multiple values:
1612 // 1 %dst:ssub0 = FOO <-- OtherVNI
1613 // 2 %src = BAR <-- VNI
1614 // 3 %dst:ssub1 = COPY %src<kill> <-- Eliminate this copy.
1616 // 5 QUUX %src<kill>
1618 // Here OtherVNI will map to itself in [1;2), but to VNI in [2;5). CR_Replace
1619 // handles this complex value mapping.
1620 if ((V.WriteLanes & OtherV.ValidLanes) == 0)
1623 // If the other live range is killed by DefMI and the live ranges are still
1624 // overlapping, it must be because we're looking at an early clobber def:
1626 // %dst<def,early-clobber> = ASM %src<kill>
1628 // In this case, it is illegal to merge the two live ranges since the early
1629 // clobber def would clobber %src before it was read.
1630 if (OtherLRQ.isKill()) {
1631 // This case where the def doesn't overlap the kill is handled above.
1632 assert(VNI->def.isEarlyClobber() &&
1633 "Only early clobber defs can overlap a kill");
1634 return CR_Impossible;
1637 // VNI is clobbering live lanes in OtherVNI, but there is still the
1638 // possibility that no instructions actually read the clobbered lanes.
1639 // If we're clobbering all the lanes in OtherVNI, at least one must be read.
1640 // Otherwise Other.LI wouldn't be live here.
1641 if ((TRI->getSubRegIndexLaneMask(Other.SubIdx) & ~V.WriteLanes) == 0)
1642 return CR_Impossible;
1644 // We need to verify that no instructions are reading the clobbered lanes. To
1645 // save compile time, we'll only check that locally. Don't allow the tainted
1646 // value to escape the basic block.
1647 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
1648 if (OtherLRQ.endPoint() >= Indexes->getMBBEndIdx(MBB))
1649 return CR_Impossible;
1651 // There are still some things that could go wrong besides clobbered lanes
1652 // being read, for example OtherVNI may be only partially redefined in MBB,
1653 // and some clobbered lanes could escape the block. Save this analysis for
1654 // resolveConflicts() when all values have been mapped. We need to know
1655 // RedefVNI and WriteLanes for any later defs in MBB, and we can't compute
1656 // that now - the recursive analyzeValue() calls must go upwards in the
1658 return CR_Unresolved;
1661 /// Compute the value assignment for ValNo in LI.
1662 /// This may be called recursively by analyzeValue(), but never for a ValNo on
1664 void JoinVals::computeAssignment(unsigned ValNo, JoinVals &Other) {
1665 Val &V = Vals[ValNo];
1666 if (V.isAnalyzed()) {
1667 // Recursion should always move up the dominator tree, so ValNo is not
1668 // supposed to reappear before it has been assigned.
1669 assert(Assignments[ValNo] != -1 && "Bad recursion?");
1672 switch ((V.Resolution = analyzeValue(ValNo, Other))) {
1675 // Merge this ValNo into OtherVNI.
1676 assert(V.OtherVNI && "OtherVNI not assigned, can't merge.");
1677 assert(Other.Vals[V.OtherVNI->id].isAnalyzed() && "Missing recursion");
1678 Assignments[ValNo] = Other.Assignments[V.OtherVNI->id];
1679 DEBUG(dbgs() << "\t\tmerge " << PrintReg(LI.reg) << ':' << ValNo << '@'
1680 << LI.getValNumInfo(ValNo)->def << " into "
1681 << PrintReg(Other.LI.reg) << ':' << V.OtherVNI->id << '@'
1682 << V.OtherVNI->def << " --> @"
1683 << NewVNInfo[Assignments[ValNo]]->def << '\n');
1687 // The other value is going to be pruned if this join is successful.
1688 assert(V.OtherVNI && "OtherVNI not assigned, can't prune");
1689 Other.Vals[V.OtherVNI->id].Pruned = true;
1692 // This value number needs to go in the final joined live range.
1693 Assignments[ValNo] = NewVNInfo.size();
1694 NewVNInfo.push_back(LI.getValNumInfo(ValNo));
1699 bool JoinVals::mapValues(JoinVals &Other) {
1700 for (unsigned i = 0, e = LI.getNumValNums(); i != e; ++i) {
1701 computeAssignment(i, Other);
1702 if (Vals[i].Resolution == CR_Impossible) {
1703 DEBUG(dbgs() << "\t\tinterference at " << PrintReg(LI.reg) << ':' << i
1704 << '@' << LI.getValNumInfo(i)->def << '\n');
1711 /// Assuming ValNo is going to clobber some valid lanes in Other.LI, compute
1712 /// the extent of the tainted lanes in the block.
1714 /// Multiple values in Other.LI can be affected since partial redefinitions can
1715 /// preserve previously tainted lanes.
1717 /// 1 %dst = VLOAD <-- Define all lanes in %dst
1718 /// 2 %src = FOO <-- ValNo to be joined with %dst:ssub0
1719 /// 3 %dst:ssub1 = BAR <-- Partial redef doesn't clear taint in ssub0
1720 /// 4 %dst:ssub0 = COPY %src <-- Conflict resolved, ssub0 wasn't read
1722 /// For each ValNo in Other that is affected, add an (EndIndex, TaintedLanes)
1723 /// entry to TaintedVals.
1725 /// Returns false if the tainted lanes extend beyond the basic block.
1727 taintExtent(unsigned ValNo, unsigned TaintedLanes, JoinVals &Other,
1728 SmallVectorImpl<std::pair<SlotIndex, unsigned> > &TaintExtent) {
1729 VNInfo *VNI = LI.getValNumInfo(ValNo);
1730 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
1731 SlotIndex MBBEnd = Indexes->getMBBEndIdx(MBB);
1733 // Scan Other.LI from VNI.def to MBBEnd.
1734 LiveInterval::iterator OtherI = Other.LI.find(VNI->def);
1735 assert(OtherI != Other.LI.end() && "No conflict?");
1737 // OtherI is pointing to a tainted value. Abort the join if the tainted
1738 // lanes escape the block.
1739 SlotIndex End = OtherI->end;
1740 if (End >= MBBEnd) {
1741 DEBUG(dbgs() << "\t\ttaints global " << PrintReg(Other.LI.reg) << ':'
1742 << OtherI->valno->id << '@' << OtherI->start << '\n');
1745 DEBUG(dbgs() << "\t\ttaints local " << PrintReg(Other.LI.reg) << ':'
1746 << OtherI->valno->id << '@' << OtherI->start
1747 << " to " << End << '\n');
1748 // A dead def is not a problem.
1751 TaintExtent.push_back(std::make_pair(End, TaintedLanes));
1753 // Check for another def in the MBB.
1754 if (++OtherI == Other.LI.end() || OtherI->start >= MBBEnd)
1757 // Lanes written by the new def are no longer tainted.
1758 const Val &OV = Other.Vals[OtherI->valno->id];
1759 TaintedLanes &= ~OV.WriteLanes;
1762 } while (TaintedLanes);
1766 /// Return true if MI uses any of the given Lanes from Reg.
1767 /// This does not include partial redefinitions of Reg.
1768 bool JoinVals::usesLanes(MachineInstr *MI, unsigned Reg, unsigned SubIdx,
1770 if (MI->isDebugValue())
1772 for (ConstMIOperands MO(MI); MO.isValid(); ++MO) {
1773 if (!MO->isReg() || MO->isDef() || MO->getReg() != Reg)
1775 if (!MO->readsReg())
1777 if (Lanes & TRI->getSubRegIndexLaneMask(
1778 TRI->composeSubRegIndices(SubIdx, MO->getSubReg())))
1784 bool JoinVals::resolveConflicts(JoinVals &Other) {
1785 for (unsigned i = 0, e = LI.getNumValNums(); i != e; ++i) {
1787 assert (V.Resolution != CR_Impossible && "Unresolvable conflict");
1788 if (V.Resolution != CR_Unresolved)
1790 DEBUG(dbgs() << "\t\tconflict at " << PrintReg(LI.reg) << ':' << i
1791 << '@' << LI.getValNumInfo(i)->def << '\n');
1793 assert(V.OtherVNI && "Inconsistent conflict resolution.");
1794 VNInfo *VNI = LI.getValNumInfo(i);
1795 const Val &OtherV = Other.Vals[V.OtherVNI->id];
1797 // VNI is known to clobber some lanes in OtherVNI. If we go ahead with the
1798 // join, those lanes will be tainted with a wrong value. Get the extent of
1799 // the tainted lanes.
1800 unsigned TaintedLanes = V.WriteLanes & OtherV.ValidLanes;
1801 SmallVector<std::pair<SlotIndex, unsigned>, 8> TaintExtent;
1802 if (!taintExtent(i, TaintedLanes, Other, TaintExtent))
1803 // Tainted lanes would extend beyond the basic block.
1806 assert(!TaintExtent.empty() && "There should be at least one conflict.");
1808 // Now look at the instructions from VNI->def to TaintExtent (inclusive).
1809 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
1810 MachineBasicBlock::iterator MI = MBB->begin();
1811 if (!VNI->isPHIDef()) {
1812 MI = Indexes->getInstructionFromIndex(VNI->def);
1813 // No need to check the instruction defining VNI for reads.
1816 assert(!SlotIndex::isSameInstr(VNI->def, TaintExtent.front().first) &&
1817 "Interference ends on VNI->def. Should have been handled earlier");
1818 MachineInstr *LastMI =
1819 Indexes->getInstructionFromIndex(TaintExtent.front().first);
1820 assert(LastMI && "Range must end at a proper instruction");
1821 unsigned TaintNum = 0;
1823 assert(MI != MBB->end() && "Bad LastMI");
1824 if (usesLanes(MI, Other.LI.reg, Other.SubIdx, TaintedLanes)) {
1825 DEBUG(dbgs() << "\t\ttainted lanes used by: " << *MI);
1828 // LastMI is the last instruction to use the current value.
1829 if (&*MI == LastMI) {
1830 if (++TaintNum == TaintExtent.size())
1832 LastMI = Indexes->getInstructionFromIndex(TaintExtent[TaintNum].first);
1833 assert(LastMI && "Range must end at a proper instruction");
1834 TaintedLanes = TaintExtent[TaintNum].second;
1839 // The tainted lanes are unused.
1840 V.Resolution = CR_Replace;
1846 // Determine if ValNo is a copy of a value number in LI or Other.LI that will
1850 // %src = COPY %dst <-- This value to be pruned.
1851 // %dst = COPY %src <-- This value is a copy of a pruned value.
1853 bool JoinVals::isPrunedValue(unsigned ValNo, JoinVals &Other) {
1854 Val &V = Vals[ValNo];
1855 if (V.Pruned || V.PrunedComputed)
1858 if (V.Resolution != CR_Erase && V.Resolution != CR_Merge)
1861 // Follow copies up the dominator tree and check if any intermediate value
1863 V.PrunedComputed = true;
1864 V.Pruned = Other.isPrunedValue(V.OtherVNI->id, *this);
1868 void JoinVals::pruneValues(JoinVals &Other,
1869 SmallVectorImpl<SlotIndex> &EndPoints) {
1870 for (unsigned i = 0, e = LI.getNumValNums(); i != e; ++i) {
1871 SlotIndex Def = LI.getValNumInfo(i)->def;
1872 switch (Vals[i].Resolution) {
1876 // This value takes precedence over the value in Other.LI.
1877 LIS->pruneValue(&Other.LI, Def, &EndPoints);
1878 // Check if we're replacing an IMPLICIT_DEF value. The IMPLICIT_DEF
1879 // instructions are only inserted to provide a live-out value for PHI
1880 // predecessors, so the instruction should simply go away once its value
1881 // has been replaced.
1882 Val &OtherV = Other.Vals[Vals[i].OtherVNI->id];
1883 bool EraseImpDef = OtherV.ErasableImplicitDef &&
1884 OtherV.Resolution == CR_Keep;
1885 if (!Def.isBlock()) {
1886 // Remove <def,read-undef> flags. This def is now a partial redef.
1887 // Also remove <def,dead> flags since the joined live range will
1888 // continue past this instruction.
1889 for (MIOperands MO(Indexes->getInstructionFromIndex(Def));
1891 if (MO->isReg() && MO->isDef() && MO->getReg() == LI.reg) {
1892 MO->setIsUndef(EraseImpDef);
1893 MO->setIsDead(false);
1895 // This value will reach instructions below, but we need to make sure
1896 // the live range also reaches the instruction at Def.
1898 EndPoints.push_back(Def);
1900 DEBUG(dbgs() << "\t\tpruned " << PrintReg(Other.LI.reg) << " at " << Def
1901 << ": " << Other.LI << '\n');
1906 if (isPrunedValue(i, Other)) {
1907 // This value is ultimately a copy of a pruned value in LI or Other.LI.
1908 // We can no longer trust the value mapping computed by
1909 // computeAssignment(), the value that was originally copied could have
1911 LIS->pruneValue(&LI, Def, &EndPoints);
1912 DEBUG(dbgs() << "\t\tpruned all of " << PrintReg(LI.reg) << " at "
1913 << Def << ": " << LI << '\n');
1918 llvm_unreachable("Unresolved conflicts");
1923 void JoinVals::eraseInstrs(SmallPtrSet<MachineInstr*, 8> &ErasedInstrs,
1924 SmallVectorImpl<unsigned> &ShrinkRegs) {
1925 for (unsigned i = 0, e = LI.getNumValNums(); i != e; ++i) {
1926 // Get the def location before markUnused() below invalidates it.
1927 SlotIndex Def = LI.getValNumInfo(i)->def;
1928 switch (Vals[i].Resolution) {
1930 // If an IMPLICIT_DEF value is pruned, it doesn't serve a purpose any
1931 // longer. The IMPLICIT_DEF instructions are only inserted by
1932 // PHIElimination to guarantee that all PHI predecessors have a value.
1933 if (!Vals[i].ErasableImplicitDef || !Vals[i].Pruned)
1935 // Remove value number i from LI. Note that this VNInfo is still present
1936 // in NewVNInfo, so it will appear as an unused value number in the final
1938 LI.getValNumInfo(i)->markUnused();
1939 LI.removeValNo(LI.getValNumInfo(i));
1940 DEBUG(dbgs() << "\t\tremoved " << i << '@' << Def << ": " << LI << '\n');
1944 MachineInstr *MI = Indexes->getInstructionFromIndex(Def);
1945 assert(MI && "No instruction to erase");
1947 unsigned Reg = MI->getOperand(1).getReg();
1948 if (TargetRegisterInfo::isVirtualRegister(Reg) &&
1949 Reg != CP.getSrcReg() && Reg != CP.getDstReg())
1950 ShrinkRegs.push_back(Reg);
1952 ErasedInstrs.insert(MI);
1953 DEBUG(dbgs() << "\t\terased:\t" << Def << '\t' << *MI);
1954 LIS->RemoveMachineInstrFromMaps(MI);
1955 MI->eraseFromParent();
1964 bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) {
1965 SmallVector<VNInfo*, 16> NewVNInfo;
1966 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
1967 LiveInterval &LHS = LIS->getInterval(CP.getDstReg());
1968 JoinVals RHSVals(RHS, CP.getSrcIdx(), NewVNInfo, CP, LIS, TRI);
1969 JoinVals LHSVals(LHS, CP.getDstIdx(), NewVNInfo, CP, LIS, TRI);
1971 DEBUG(dbgs() << "\t\tRHS = " << PrintReg(CP.getSrcReg()) << ' ' << RHS
1972 << "\n\t\tLHS = " << PrintReg(CP.getDstReg()) << ' ' << LHS
1975 // First compute NewVNInfo and the simple value mappings.
1976 // Detect impossible conflicts early.
1977 if (!LHSVals.mapValues(RHSVals) || !RHSVals.mapValues(LHSVals))
1980 // Some conflicts can only be resolved after all values have been mapped.
1981 if (!LHSVals.resolveConflicts(RHSVals) || !RHSVals.resolveConflicts(LHSVals))
1984 // All clear, the live ranges can be merged.
1986 // The merging algorithm in LiveInterval::join() can't handle conflicting
1987 // value mappings, so we need to remove any live ranges that overlap a
1988 // CR_Replace resolution. Collect a set of end points that can be used to
1989 // restore the live range after joining.
1990 SmallVector<SlotIndex, 8> EndPoints;
1991 LHSVals.pruneValues(RHSVals, EndPoints);
1992 RHSVals.pruneValues(LHSVals, EndPoints);
1994 // Erase COPY and IMPLICIT_DEF instructions. This may cause some external
1995 // registers to require trimming.
1996 SmallVector<unsigned, 8> ShrinkRegs;
1997 LHSVals.eraseInstrs(ErasedInstrs, ShrinkRegs);
1998 RHSVals.eraseInstrs(ErasedInstrs, ShrinkRegs);
1999 while (!ShrinkRegs.empty())
2000 LIS->shrinkToUses(&LIS->getInterval(ShrinkRegs.pop_back_val()));
2002 // Join RHS into LHS.
2003 LHS.join(RHS, LHSVals.getAssignments(), RHSVals.getAssignments(), NewVNInfo);
2005 // Kill flags are going to be wrong if the live ranges were overlapping.
2006 // Eventually, we should simply clear all kill flags when computing live
2007 // ranges. They are reinserted after register allocation.
2008 MRI->clearKillFlags(LHS.reg);
2009 MRI->clearKillFlags(RHS.reg);
2011 if (EndPoints.empty())
2014 // Recompute the parts of the live range we had to remove because of
2015 // CR_Replace conflicts.
2016 DEBUG(dbgs() << "\t\trestoring liveness to " << EndPoints.size()
2017 << " points: " << LHS << '\n');
2018 LIS->extendToIndices(LHS, EndPoints);
2022 /// joinIntervals - Attempt to join these two intervals. On failure, this
2024 bool RegisterCoalescer::joinIntervals(CoalescerPair &CP) {
2025 return CP.isPhys() ? joinReservedPhysReg(CP) : joinVirtRegs(CP);
2029 // Information concerning MBB coalescing priority.
2030 struct MBBPriorityInfo {
2031 MachineBasicBlock *MBB;
2035 MBBPriorityInfo(MachineBasicBlock *mbb, unsigned depth, bool issplit)
2036 : MBB(mbb), Depth(depth), IsSplit(issplit) {}
2040 // C-style comparator that sorts first based on the loop depth of the basic
2041 // block (the unsigned), and then on the MBB number.
2043 // EnableGlobalCopies assumes that the primary sort key is loop depth.
2044 static int compareMBBPriority(const MBBPriorityInfo *LHS,
2045 const MBBPriorityInfo *RHS) {
2046 // Deeper loops first
2047 if (LHS->Depth != RHS->Depth)
2048 return LHS->Depth > RHS->Depth ? -1 : 1;
2050 // Try to unsplit critical edges next.
2051 if (LHS->IsSplit != RHS->IsSplit)
2052 return LHS->IsSplit ? -1 : 1;
2054 // Prefer blocks that are more connected in the CFG. This takes care of
2055 // the most difficult copies first while intervals are short.
2056 unsigned cl = LHS->MBB->pred_size() + LHS->MBB->succ_size();
2057 unsigned cr = RHS->MBB->pred_size() + RHS->MBB->succ_size();
2059 return cl > cr ? -1 : 1;
2061 // As a last resort, sort by block number.
2062 return LHS->MBB->getNumber() < RHS->MBB->getNumber() ? -1 : 1;
2065 /// \returns true if the given copy uses or defines a local live range.
2066 static bool isLocalCopy(MachineInstr *Copy, const LiveIntervals *LIS) {
2067 if (!Copy->isCopy())
2070 if (Copy->getOperand(1).isUndef())
2073 unsigned SrcReg = Copy->getOperand(1).getReg();
2074 unsigned DstReg = Copy->getOperand(0).getReg();
2075 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)
2076 || TargetRegisterInfo::isPhysicalRegister(DstReg))
2079 return LIS->intervalIsInOneMBB(LIS->getInterval(SrcReg))
2080 || LIS->intervalIsInOneMBB(LIS->getInterval(DstReg));
2083 // Try joining WorkList copies starting from index From.
2084 // Null out any successful joins.
2085 bool RegisterCoalescer::
2086 copyCoalesceWorkList(MutableArrayRef<MachineInstr*> CurrList) {
2087 bool Progress = false;
2088 for (unsigned i = 0, e = CurrList.size(); i != e; ++i) {
2091 // Skip instruction pointers that have already been erased, for example by
2092 // dead code elimination.
2093 if (ErasedInstrs.erase(CurrList[i])) {
2098 bool Success = joinCopy(CurrList[i], Again);
2099 Progress |= Success;
2100 if (Success || !Again)
2107 RegisterCoalescer::copyCoalesceInMBB(MachineBasicBlock *MBB) {
2108 DEBUG(dbgs() << MBB->getName() << ":\n");
2110 // Collect all copy-like instructions in MBB. Don't start coalescing anything
2111 // yet, it might invalidate the iterator.
2112 const unsigned PrevSize = WorkList.size();
2113 if (JoinGlobalCopies) {
2114 // Coalesce copies bottom-up to coalesce local defs before local uses. They
2115 // are not inherently easier to resolve, but slightly preferable until we
2116 // have local live range splitting. In particular this is required by
2117 // cmp+jmp macro fusion.
2118 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
2120 if (!MII->isCopyLike())
2122 if (isLocalCopy(&(*MII), LIS))
2123 LocalWorkList.push_back(&(*MII));
2125 WorkList.push_back(&(*MII));
2129 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
2131 if (MII->isCopyLike())
2132 WorkList.push_back(MII);
2134 // Try coalescing the collected copies immediately, and remove the nulls.
2135 // This prevents the WorkList from getting too large since most copies are
2136 // joinable on the first attempt.
2137 MutableArrayRef<MachineInstr*>
2138 CurrList(WorkList.begin() + PrevSize, WorkList.end());
2139 if (copyCoalesceWorkList(CurrList))
2140 WorkList.erase(std::remove(WorkList.begin() + PrevSize, WorkList.end(),
2141 (MachineInstr*)0), WorkList.end());
2144 void RegisterCoalescer::coalesceLocals() {
2145 copyCoalesceWorkList(LocalWorkList);
2146 for (unsigned j = 0, je = LocalWorkList.size(); j != je; ++j) {
2147 if (LocalWorkList[j])
2148 WorkList.push_back(LocalWorkList[j]);
2150 LocalWorkList.clear();
2153 void RegisterCoalescer::joinAllIntervals() {
2154 DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
2155 assert(WorkList.empty() && LocalWorkList.empty() && "Old data still around.");
2157 std::vector<MBBPriorityInfo> MBBs;
2158 MBBs.reserve(MF->size());
2159 for (MachineFunction::iterator I = MF->begin(), E = MF->end();I != E;++I){
2160 MachineBasicBlock *MBB = I;
2161 MBBs.push_back(MBBPriorityInfo(MBB, Loops->getLoopDepth(MBB),
2162 JoinSplitEdges && isSplitEdge(MBB)));
2164 array_pod_sort(MBBs.begin(), MBBs.end(), compareMBBPriority);
2166 // Coalesce intervals in MBB priority order.
2167 unsigned CurrDepth = UINT_MAX;
2168 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
2169 // Try coalescing the collected local copies for deeper loops.
2170 if (JoinGlobalCopies && MBBs[i].Depth < CurrDepth) {
2172 CurrDepth = MBBs[i].Depth;
2174 copyCoalesceInMBB(MBBs[i].MBB);
2178 // Joining intervals can allow other intervals to be joined. Iteratively join
2179 // until we make no progress.
2180 while (copyCoalesceWorkList(WorkList))
2184 void RegisterCoalescer::releaseMemory() {
2185 ErasedInstrs.clear();
2188 InflateRegs.clear();
2191 bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
2193 MRI = &fn.getRegInfo();
2194 TM = &fn.getTarget();
2195 TRI = TM->getRegisterInfo();
2196 TII = TM->getInstrInfo();
2197 LIS = &getAnalysis<LiveIntervals>();
2198 AA = &getAnalysis<AliasAnalysis>();
2199 Loops = &getAnalysis<MachineLoopInfo>();
2201 const TargetSubtargetInfo &ST = TM->getSubtarget<TargetSubtargetInfo>();
2202 if (EnableGlobalCopies == cl::BOU_UNSET)
2203 JoinGlobalCopies = ST.useMachineScheduler();
2205 JoinGlobalCopies = (EnableGlobalCopies == cl::BOU_TRUE);
2207 // The MachineScheduler does not currently require JoinSplitEdges. This will
2208 // either be enabled unconditionally or replaced by a more general live range
2209 // splitting optimization.
2210 JoinSplitEdges = EnableJoinSplits;
2212 DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
2213 << "********** Function: " << MF->getName() << '\n');
2215 if (VerifyCoalescing)
2216 MF->verify(this, "Before register coalescing");
2218 RegClassInfo.runOnMachineFunction(fn);
2220 // Join (coalesce) intervals if requested.
2224 // After deleting a lot of copies, register classes may be less constrained.
2225 // Removing sub-register operands may allow GR32_ABCD -> GR32 and DPR_VFP2 ->
2227 array_pod_sort(InflateRegs.begin(), InflateRegs.end());
2228 InflateRegs.erase(std::unique(InflateRegs.begin(), InflateRegs.end()),
2230 DEBUG(dbgs() << "Trying to inflate " << InflateRegs.size() << " regs.\n");
2231 for (unsigned i = 0, e = InflateRegs.size(); i != e; ++i) {
2232 unsigned Reg = InflateRegs[i];
2233 if (MRI->reg_nodbg_empty(Reg))
2235 if (MRI->recomputeRegClass(Reg, *TM)) {
2236 DEBUG(dbgs() << PrintReg(Reg) << " inflated to "
2237 << MRI->getRegClass(Reg)->getName() << '\n');
2243 if (VerifyCoalescing)
2244 MF->verify(this, "After register coalescing");
2248 /// print - Implement the dump method.
2249 void RegisterCoalescer::print(raw_ostream &O, const Module* m) const {