1 //===-- RegisterCoalescer.h - Register Coalescing Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the abstract interface for register coalescers,
11 // allowing them to interact with and query register allocators.
13 //===----------------------------------------------------------------------===//
15 #include "RegisterClassInfo.h"
16 #include "llvm/Support/IncludeFile.h"
17 #include "llvm/CodeGen/LiveInterval.h"
18 #include "llvm/ADT/SmallPtrSet.h"
20 #ifndef LLVM_CODEGEN_REGISTER_COALESCER_H
21 #define LLVM_CODEGEN_REGISTER_COALESCER_H
25 class MachineFunction;
29 class TargetRegisterInfo;
30 class TargetRegisterClass;
31 class TargetInstrInfo;
32 class LiveDebugVariables;
34 class MachineLoopInfo;
38 /// An abstract interface for register coalescers. Coalescers must
39 /// implement this interface to be part of the coalescer analysis
41 class RegisterCoalescer : public MachineFunctionPass {
43 MachineRegisterInfo* mri_;
44 const TargetMachine* tm_;
45 const TargetRegisterInfo* tri_;
46 const TargetInstrInfo* tii_;
48 LiveDebugVariables *ldv_;
49 const MachineLoopInfo* loopInfo;
51 RegisterClassInfo RegClassInfo;
53 /// JoinedCopies - Keep track of copies eliminated due to coalescing.
55 SmallPtrSet<MachineInstr*, 32> JoinedCopies;
57 /// ReMatCopies - Keep track of copies eliminated due to remat.
59 SmallPtrSet<MachineInstr*, 32> ReMatCopies;
61 /// ReMatDefs - Keep track of definition instructions which have
63 SmallPtrSet<MachineInstr*, 8> ReMatDefs;
65 /// joinIntervals - join compatible live intervals
68 /// CopyCoalesceInMBB - Coalesce copies in the specified MBB, putting
69 /// copies that cannot yet be coalesced into the "TryAgain" list.
70 void CopyCoalesceInMBB(MachineBasicBlock *MBB,
71 std::vector<MachineInstr*> &TryAgain);
73 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
74 /// which are the src/dst of the copy instruction CopyMI. This returns true
75 /// if the copy was successfully coalesced away. If it is not currently
76 /// possible to coalesce this interval, but it may be possible if other
77 /// things get coalesced, then it returns true by reference in 'Again'.
78 bool JoinCopy(MachineInstr *TheCopy, bool &Again);
80 /// JoinIntervals - Attempt to join these two intervals. On failure, this
81 /// returns false. The output "SrcInt" will not have been modified, so we can
82 /// use this information below to update aliases.
83 bool JoinIntervals(CoalescerPair &CP);
85 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
86 /// the source value number is defined by a copy from the destination reg
87 /// see if we can merge these two destination reg valno# into a single
88 /// value number, eliminating a copy.
89 bool AdjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
91 /// HasOtherReachingDefs - Return true if there are definitions of IntB
92 /// other than BValNo val# that can reach uses of AValno val# of IntA.
93 bool HasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
94 VNInfo *AValNo, VNInfo *BValNo);
96 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy.
97 /// If the source value number is defined by a commutable instruction and
98 /// its other operand is coalesced to the copy dest register, see if we
99 /// can transform the copy into a noop by commuting the definition.
100 bool RemoveCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI);
102 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
103 /// computation, replace the copy by rematerialize the definition.
104 /// If PreserveSrcInt is true, make sure SrcInt is valid after the call.
105 bool ReMaterializeTrivialDef(LiveInterval &SrcInt, bool PreserveSrcInt,
106 unsigned DstReg, unsigned DstSubIdx,
107 MachineInstr *CopyMI);
109 /// shouldJoinPhys - Return true if a physreg copy should be joined.
110 bool shouldJoinPhys(CoalescerPair &CP);
112 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
113 /// two virtual registers from different register classes.
114 bool isWinToJoinCrossClass(unsigned SrcReg,
116 const TargetRegisterClass *SrcRC,
117 const TargetRegisterClass *DstRC,
118 const TargetRegisterClass *NewRC);
120 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
121 /// update the subregister number if it is not zero. If DstReg is a
122 /// physical register and the existing subregister number of the def / use
123 /// being updated is not zero, make sure to set it to the correct physical
125 void UpdateRegDefsUses(const CoalescerPair &CP);
127 /// RemoveDeadDef - If a def of a live interval is now determined dead,
128 /// remove the val# it defines. If the live interval becomes empty, remove
130 bool RemoveDeadDef(LiveInterval &li, MachineInstr *DefMI);
132 /// RemoveCopyFlag - If DstReg is no longer defined by CopyMI, clear the
133 /// VNInfo copy flag for DstReg and all aliases.
134 void RemoveCopyFlag(unsigned DstReg, const MachineInstr *CopyMI);
136 /// markAsJoined - Remember that CopyMI has already been joined.
137 void markAsJoined(MachineInstr *CopyMI);
140 static char ID; // Class identification, replacement for typeinfo
141 RegisterCoalescer() : MachineFunctionPass(ID) {
142 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
145 /// Register allocators must call this from their own
146 /// getAnalysisUsage to cover the case where the coalescer is not
147 /// a Pass in the proper sense and isn't managed by PassManager.
148 /// PassManager needs to know which analyses to make available and
149 /// which to invalidate when running the register allocator or any
150 /// pass that might call coalescing. The long-term solution is to
151 /// allow hierarchies of PassManagers.
152 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
154 virtual void releaseMemory();
156 /// runOnMachineFunction - pass entry point
157 virtual bool runOnMachineFunction(MachineFunction&);
159 /// print - Implement the dump method.
160 virtual void print(raw_ostream &O, const Module* = 0) const;
163 /// An abstract interface for register allocators to interact with
168 /// This is simply an example of how to use the RegallocQuery
169 /// interface. It is not meant to be used in production.
171 /// class LinearScanRegallocQuery : public RegallocQuery {
173 /// const LiveIntervals \&li;
176 /// LinearScanRegallocQuery(LiveIntervals &intervals)
177 /// : li(intervals) {}
179 /// /// This is pretty slow and conservative, but since linear scan
180 /// /// allocation doesn't pre-compute interference information it's
181 /// /// the best we can do. Coalescers are always free to ignore this
182 /// /// and implement their own discovery strategy. See
183 /// /// RegisterCoalescer for an example.
184 /// void getInterferences(IntervalSet &interferences,
185 /// const LiveInterval &a) const {
186 /// for(LiveIntervals::const_iterator iv = li.begin(),
187 /// ivend = li.end();
190 /// if (interfere(a, iv->second)) {
191 /// interferences.insert(&iv->second);
196 /// /// This is *really* slow and stupid. See above.
197 /// int getNumberOfInterferences(const LiveInterval &a) const {
198 /// IntervalSet intervals;
199 /// getInterferences(intervals, a);
200 /// return intervals.size();
204 /// In the allocator:
206 /// RegisterCoalescer &coalescer = getAnalysis<RegisterCoalescer>();
208 /// // We don't reset the coalescer so if it's already been run this
209 /// // takes almost no time.
210 /// LinearScanRegallocQuery ifd(*li_);
212 class RegallocQuery {
214 typedef SmallPtrSet<const LiveInterval *, 8> IntervalSet;
216 virtual ~RegallocQuery() {}
218 /// Return whether two live ranges interfere.
219 virtual bool interfere(const LiveInterval &a,
220 const LiveInterval &b) const {
222 return a.overlaps(b);
225 /// Return the set of intervals that interfere with this one.
226 virtual void getInterferences(IntervalSet &interferences,
227 const LiveInterval &a) const = 0;
229 /// This can often be cheaper than actually returning the
231 virtual int getNumberOfInterferences(const LiveInterval &a) const = 0;
233 /// Make any data structure updates necessary to reflect
234 /// coalescing or other modifications.
235 virtual void updateDataForMerge(const LiveInterval &a,
236 const LiveInterval &b,
237 const MachineInstr ©) {}
239 /// Allow the register allocator to communicate when it doesn't
240 /// want a copy coalesced. This may be due to assumptions made by
241 /// the allocator about various invariants and so this question is
242 /// a matter of legality, not performance. Performance decisions
243 /// about which copies to coalesce should be made by the
245 virtual bool isLegalToCoalesce(const MachineInstr &inst) const {
251 /// CoalescerPair - A helper class for register coalescers. When deciding if
252 /// two registers can be coalesced, CoalescerPair can determine if a copy
253 /// instruction would become an identity copy after coalescing.
254 class CoalescerPair {
255 const TargetInstrInfo &tii_;
256 const TargetRegisterInfo &tri_;
258 /// dstReg_ - The register that will be left after coalescing. It can be a
259 /// virtual or physical register.
262 /// srcReg_ - the virtual register that will be coalesced into dstReg.
265 /// subReg_ - The subregister index of srcReg in dstReg_. It is possible the
266 /// coalesce srcReg_ into a subreg of the larger dstReg_ when dstReg_ is a
267 /// virtual register.
270 /// partial_ - True when the original copy was a partial subregister copy.
273 /// crossClass_ - True when both regs are virtual, and newRC is constrained.
276 /// flipped_ - True when DstReg and SrcReg are reversed from the oriignal copy
280 /// newRC_ - The register class of the coalesced register, or NULL if dstReg_
282 const TargetRegisterClass *newRC_;
285 CoalescerPair(const TargetInstrInfo &tii, const TargetRegisterInfo &tri)
286 : tii_(tii), tri_(tri), dstReg_(0), srcReg_(0), subIdx_(0),
287 partial_(false), crossClass_(false), flipped_(false), newRC_(0) {}
289 /// setRegisters - set registers to match the copy instruction MI. Return
290 /// false if MI is not a coalescable copy instruction.
291 bool setRegisters(const MachineInstr*);
293 /// flip - Swap srcReg_ and dstReg_. Return false if swapping is impossible
294 /// because dstReg_ is a physical register, or subIdx_ is set.
297 /// isCoalescable - Return true if MI is a copy instruction that will become
298 /// an identity copy after coalescing.
299 bool isCoalescable(const MachineInstr*) const;
301 /// isPhys - Return true if DstReg is a physical register.
302 bool isPhys() const { return !newRC_; }
304 /// isPartial - Return true if the original copy instruction did not copy the
305 /// full register, but was a subreg operation.
306 bool isPartial() const { return partial_; }
308 /// isCrossClass - Return true if DstReg is virtual and NewRC is a smaller register class than DstReg's.
309 bool isCrossClass() const { return crossClass_; }
311 /// isFlipped - Return true when getSrcReg is the register being defined by
312 /// the original copy instruction.
313 bool isFlipped() const { return flipped_; }
315 /// getDstReg - Return the register (virtual or physical) that will remain
316 /// after coalescing.
317 unsigned getDstReg() const { return dstReg_; }
319 /// getSrcReg - Return the virtual register that will be coalesced away.
320 unsigned getSrcReg() const { return srcReg_; }
322 /// getSubIdx - Return the subregister index in DstReg that SrcReg will be
323 /// coalesced into, or 0.
324 unsigned getSubIdx() const { return subIdx_; }
326 /// getNewRC - Return the register class of the coalesced register.
327 const TargetRegisterClass *getNewRC() const { return newRC_; }
329 } // End llvm namespace