1 //===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the machine register scavenger. It can provide
11 // information, such as unused registers, at any point in a machine basic block.
12 // It also provides a mechanism to make registers available by evicting them to
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "reg-scavenging"
18 #include "llvm/CodeGen/RegisterScavenging.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineBasicBlock.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/SmallPtrSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/STLExtras.h"
36 /// setUsed - Set the register and its sub-registers as being used.
37 void RegScavenger::setUsed(unsigned Reg) {
38 RegsAvailable.reset(Reg);
40 for (const uint16_t *SubRegs = TRI->getSubRegisters(Reg);
41 unsigned SubReg = *SubRegs; ++SubRegs)
42 RegsAvailable.reset(SubReg);
45 bool RegScavenger::isAliasUsed(unsigned Reg) const {
48 for (const uint16_t *R = TRI->getAliasSet(Reg); *R; ++R)
54 void RegScavenger::initRegState() {
57 ScavengeRestore = NULL;
59 // All registers started out unused.
65 // Live-in registers are in use.
66 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
67 E = MBB->livein_end(); I != E; ++I)
70 // Pristine CSRs are also unavailable.
71 BitVector PR = MBB->getParent()->getFrameInfo()->getPristineRegs(MBB);
72 for (int I = PR.find_first(); I>0; I = PR.find_next(I))
76 void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
77 MachineFunction &MF = *mbb->getParent();
78 const TargetMachine &TM = MF.getTarget();
79 TII = TM.getInstrInfo();
80 TRI = TM.getRegisterInfo();
81 MRI = &MF.getRegInfo();
83 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
86 // It is not possible to use the register scavenger after late optimization
87 // passes that don't preserve accurate liveness information.
88 assert(MRI->tracksLiveness() &&
89 "Cannot use register scavenger with inaccurate liveness");
93 NumPhysRegs = TRI->getNumRegs();
94 RegsAvailable.resize(NumPhysRegs);
95 KillRegs.resize(NumPhysRegs);
96 DefRegs.resize(NumPhysRegs);
98 // Create reserved registers bitvector.
99 ReservedRegs = TRI->getReservedRegs(MF);
101 // Create callee-saved registers bitvector.
102 CalleeSavedRegs.resize(NumPhysRegs);
103 const uint16_t *CSRegs = TRI->getCalleeSavedRegs(&MF);
105 for (unsigned i = 0; CSRegs[i]; ++i)
106 CalleeSavedRegs.set(CSRegs[i]);
115 void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) {
117 for (const uint16_t *R = TRI->getSubRegisters(Reg); *R; R++)
121 void RegScavenger::forward() {
127 assert(MBBI != MBB->end() && "Already past the end of the basic block!");
128 MBBI = llvm::next(MBBI);
130 assert(MBBI != MBB->end() && "Already at the end of the basic block!");
132 MachineInstr *MI = MBBI;
134 if (MI == ScavengeRestore) {
137 ScavengeRestore = NULL;
140 if (MI->isDebugValue())
143 // Find out which registers are early clobbered, killed, defined, and marked
144 // def-dead in this instruction.
145 // FIXME: The scavenger is not predication aware. If the instruction is
146 // predicated, conservatively assume "kill" markers do not actually kill the
147 // register. Similarly ignores "dead" markers.
148 bool isPred = TII->isPredicated(MI);
151 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
152 const MachineOperand &MO = MI->getOperand(i);
154 (isPred ? DefRegs : KillRegs).setBitsNotInMask(MO.getRegMask());
157 unsigned Reg = MO.getReg();
158 if (!Reg || isReserved(Reg))
162 // Ignore undef uses.
165 if (!isPred && MO.isKill())
166 addRegWithSubRegs(KillRegs, Reg);
169 if (!isPred && MO.isDead())
170 addRegWithSubRegs(KillRegs, Reg);
172 addRegWithSubRegs(DefRegs, Reg);
176 // Verify uses and defs.
178 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
179 const MachineOperand &MO = MI->getOperand(i);
182 unsigned Reg = MO.getReg();
183 if (!Reg || isReserved(Reg))
189 // Check if it's partial live: e.g.
190 // D0 = insert_subreg D0<undef>, S0
192 // The problem is the insert_subreg could be eliminated. The use of
193 // D0 is using a partially undef value. This is not *incorrect* since
194 // S1 is can be freely clobbered.
195 // Ideally we would like a way to model this, but leaving the
196 // insert_subreg around causes both correctness and performance issues.
197 bool SubUsed = false;
198 for (const uint16_t *SubRegs = TRI->getSubRegisters(Reg);
199 unsigned SubReg = *SubRegs; ++SubRegs)
200 if (isUsed(SubReg)) {
205 MBB->getParent()->verify(NULL, "In Register Scavenger");
206 llvm_unreachable("Using an undefined register!");
213 // FIXME: Enable this once we've figured out how to correctly transfer
214 // implicit kills during codegen passes like the coalescer.
215 assert((KillRegs.test(Reg) || isUnused(Reg) ||
216 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
217 "Re-defining a live register!");
223 // Commit the changes.
228 void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
229 used = RegsAvailable;
232 used |= ReservedRegs;
234 used.reset(ReservedRegs);
237 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
238 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
240 if (!isAliasUsed(*I)) {
241 DEBUG(dbgs() << "Scavenger found unused reg: " << TRI->getName(*I) <<
248 /// getRegsAvailable - Return all available registers in the register class
250 BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) {
251 BitVector Mask(TRI->getNumRegs());
252 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
254 if (!isAliasUsed(*I))
259 /// findSurvivorReg - Return the candidate register that is unused for the
260 /// longest after StargMII. UseMI is set to the instruction where the search
263 /// No more than InstrLimit instructions are inspected.
265 unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI,
266 BitVector &Candidates,
268 MachineBasicBlock::iterator &UseMI) {
269 int Survivor = Candidates.find_first();
270 assert(Survivor > 0 && "No candidates for scavenging");
272 MachineBasicBlock::iterator ME = MBB->getFirstTerminator();
273 assert(StartMI != ME && "MI already at terminator");
274 MachineBasicBlock::iterator RestorePointMI = StartMI;
275 MachineBasicBlock::iterator MI = StartMI;
277 bool inVirtLiveRange = false;
278 for (++MI; InstrLimit > 0 && MI != ME; ++MI, --InstrLimit) {
279 if (MI->isDebugValue()) {
280 ++InstrLimit; // Don't count debug instructions
283 bool isVirtKillInsn = false;
284 bool isVirtDefInsn = false;
285 // Remove any candidates touched by instruction.
286 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
287 const MachineOperand &MO = MI->getOperand(i);
289 Candidates.clearBitsNotInMask(MO.getRegMask());
290 if (!MO.isReg() || MO.isUndef() || !MO.getReg())
292 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
294 isVirtDefInsn = true;
295 else if (MO.isKill())
296 isVirtKillInsn = true;
299 Candidates.reset(MO.getReg());
300 for (const uint16_t *R = TRI->getAliasSet(MO.getReg()); *R; R++)
301 Candidates.reset(*R);
303 // If we're not in a virtual reg's live range, this is a valid
305 if (!inVirtLiveRange) RestorePointMI = MI;
307 // Update whether we're in the live range of a virtual register
308 if (isVirtKillInsn) inVirtLiveRange = false;
309 if (isVirtDefInsn) inVirtLiveRange = true;
311 // Was our survivor untouched by this instruction?
312 if (Candidates.test(Survivor))
315 // All candidates gone?
316 if (Candidates.none())
319 Survivor = Candidates.find_first();
321 // If we ran off the end, that's where we want to restore.
322 if (MI == ME) RestorePointMI = ME;
323 assert (RestorePointMI != StartMI &&
324 "No available scavenger restore location!");
326 // We ran out of candidates, so stop the search.
327 UseMI = RestorePointMI;
331 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
332 MachineBasicBlock::iterator I,
334 // Consider all allocatable registers in the register class initially
335 BitVector Candidates =
336 TRI->getAllocatableSet(*I->getParent()->getParent(), RC);
338 // Exclude all the registers being used by the instruction.
339 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
340 MachineOperand &MO = I->getOperand(i);
341 if (MO.isReg() && MO.getReg() != 0 &&
342 !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
343 Candidates.reset(MO.getReg());
346 // Try to find a register that's unused if there is one, as then we won't
347 // have to spill. Search explicitly rather than masking out based on
348 // RegsAvailable, as RegsAvailable does not take aliases into account.
349 // That's what getRegsAvailable() is for.
350 BitVector Available = getRegsAvailable(RC);
351 Available &= Candidates;
353 Candidates = Available;
355 // Find the register whose use is furthest away.
356 MachineBasicBlock::iterator UseMI;
357 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
359 // If we found an unused register there is no reason to spill it.
360 if (!isAliasUsed(SReg)) {
361 DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n");
365 assert(ScavengedReg == 0 &&
366 "Scavenger slot is live, unable to scavenge another register!");
368 // Avoid infinite regress
371 // If the target knows how to save/restore the register, let it do so;
372 // otherwise, use the emergency stack spill slot.
373 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {
374 // Spill the scavenged register before I.
375 assert(ScavengingFrameIndex >= 0 &&
376 "Cannot scavenge register without an emergency spill slot!");
377 TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC,TRI);
378 MachineBasicBlock::iterator II = prior(I);
379 TRI->eliminateFrameIndex(II, SPAdj, this);
381 // Restore the scavenged register before its use (or first terminator).
382 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC, TRI);
384 TRI->eliminateFrameIndex(II, SPAdj, this);
387 ScavengeRestore = prior(UseMI);
389 // Doing this here leads to infinite regress.
390 // ScavengedReg = SReg;
393 DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) <<