1 //===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the machine register scavenger. It can provide
11 // information, such as unused registers, at any point in a machine basic block.
12 // It also provides a mechanism to make registers available by evicting them to
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "reg-scavenging"
18 #include "llvm/CodeGen/RegisterScavenging.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineBasicBlock.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Target/TargetRegisterInfo.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/SmallPtrSet.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/ADT/STLExtras.h"
34 /// setUsed - Set the register and its sub-registers as being used.
35 void RegScavenger::setUsed(unsigned Reg) {
36 RegsAvailable.reset(Reg);
38 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
39 unsigned SubReg = *SubRegs; ++SubRegs)
40 RegsAvailable.reset(SubReg);
43 bool RegScavenger::isAliasUsed(unsigned Reg) const {
46 for (const unsigned *R = TRI->getAliasSet(Reg); *R; ++R)
52 void RegScavenger::initRegState() {
55 ScavengeRestore = NULL;
57 // All registers started out unused.
60 // Reserved registers are always used.
61 RegsAvailable ^= ReservedRegs;
66 // Live-in registers are in use.
67 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
68 E = MBB->livein_end(); I != E; ++I)
71 // Pristine CSRs are also unavailable.
72 BitVector PR = MBB->getParent()->getFrameInfo()->getPristineRegs(MBB);
73 for (int I = PR.find_first(); I>0; I = PR.find_next(I))
77 void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
78 MachineFunction &MF = *mbb->getParent();
79 const TargetMachine &TM = MF.getTarget();
80 TII = TM.getInstrInfo();
81 TRI = TM.getRegisterInfo();
82 MRI = &MF.getRegInfo();
84 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
89 NumPhysRegs = TRI->getNumRegs();
90 RegsAvailable.resize(NumPhysRegs);
92 // Create reserved registers bitvector.
93 ReservedRegs = TRI->getReservedRegs(MF);
95 // Create callee-saved registers bitvector.
96 CalleeSavedRegs.resize(NumPhysRegs);
97 const unsigned *CSRegs = TRI->getCalleeSavedRegs();
99 for (unsigned i = 0; CSRegs[i]; ++i)
100 CalleeSavedRegs.set(CSRegs[i]);
109 void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) {
111 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
115 void RegScavenger::addRegWithAliases(BitVector &BV, unsigned Reg) {
117 for (const unsigned *R = TRI->getAliasSet(Reg); *R; R++)
121 void RegScavenger::forward() {
127 assert(MBBI != MBB->end() && "Already at the end of the basic block!");
128 MBBI = llvm::next(MBBI);
131 MachineInstr *MI = MBBI;
133 if (MI == ScavengeRestore) {
136 ScavengeRestore = NULL;
139 if (MI->isDebugValue())
142 // Find out which registers are early clobbered, killed, defined, and marked
143 // def-dead in this instruction.
144 // FIXME: The scavenger is not predication aware. If the instruction is
145 // predicated, conservatively assume "kill" markers do not actually kill the
146 // register. Similarly ignores "dead" markers.
147 bool isPred = TII->isPredicated(MI);
148 BitVector EarlyClobberRegs(NumPhysRegs);
149 BitVector KillRegs(NumPhysRegs);
150 BitVector DefRegs(NumPhysRegs);
151 BitVector DeadRegs(NumPhysRegs);
152 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
153 const MachineOperand &MO = MI->getOperand(i);
154 if (!MO.isReg() || MO.isUndef())
156 unsigned Reg = MO.getReg();
157 if (!Reg || isReserved(Reg))
161 // Two-address operands implicitly kill.
162 if (!isPred && (MO.isKill() || MI->isRegTiedToDefOperand(i)))
163 addRegWithSubRegs(KillRegs, Reg);
166 if (!isPred && MO.isDead())
167 addRegWithSubRegs(DeadRegs, Reg);
169 addRegWithSubRegs(DefRegs, Reg);
170 if (MO.isEarlyClobber())
171 addRegWithAliases(EarlyClobberRegs, Reg);
175 // Verify uses and defs.
176 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
177 const MachineOperand &MO = MI->getOperand(i);
178 if (!MO.isReg() || MO.isUndef())
180 unsigned Reg = MO.getReg();
181 if (!Reg || isReserved(Reg))
185 // Check if it's partial live: e.g.
186 // D0 = insert_subreg D0<undef>, S0
188 // The problem is the insert_subreg could be eliminated. The use of
189 // D0 is using a partially undef value. This is not *incorrect* since
190 // S1 is can be freely clobbered.
191 // Ideally we would like a way to model this, but leaving the
192 // insert_subreg around causes both correctness and performance issues.
193 bool SubUsed = false;
194 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
195 unsigned SubReg = *SubRegs; ++SubRegs)
196 if (isUsed(SubReg)) {
200 assert(SubUsed && "Using an undefined register!");
202 assert((!EarlyClobberRegs.test(Reg) || MI->isRegTiedToDefOperand(i)) &&
203 "Using an early clobbered register!");
207 // FIXME: Enable this once we've figured out how to correctly transfer
208 // implicit kills during codegen passes like the coalescer.
209 assert((KillRegs.test(Reg) || isUnused(Reg) ||
210 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
211 "Re-defining a live register!");
216 // Commit the changes.
222 void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
224 used = ~RegsAvailable;
226 used = ~RegsAvailable & ~ReservedRegs;
229 /// CreateRegClassMask - Set the bits that represent the registers in the
230 /// TargetRegisterClass.
231 static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {
232 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E;
237 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
238 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
240 if (!isAliasUsed(*I))
245 /// findSurvivorReg - Return the candidate register that is unused for the
246 /// longest after MBBI. UseMI is set to the instruction where the search
249 /// No more than InstrLimit instructions are inspected.
251 unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI,
252 BitVector &Candidates,
254 MachineBasicBlock::iterator &UseMI) {
255 int Survivor = Candidates.find_first();
256 assert(Survivor > 0 && "No candidates for scavenging");
258 MachineBasicBlock::iterator ME = MBB->getFirstTerminator();
259 assert(StartMI != ME && "MI already at terminator");
260 MachineBasicBlock::iterator RestorePointMI = StartMI;
261 MachineBasicBlock::iterator MI = StartMI;
263 bool inVirtLiveRange = false;
264 for (++MI; InstrLimit > 0 && MI != ME; ++MI, --InstrLimit) {
265 if (MI->isDebugValue()) {
266 ++InstrLimit; // Don't count debug instructions
269 bool isVirtKillInsn = false;
270 bool isVirtDefInsn = false;
271 // Remove any candidates touched by instruction.
272 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
273 const MachineOperand &MO = MI->getOperand(i);
274 if (!MO.isReg() || MO.isUndef() || !MO.getReg())
276 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
278 isVirtDefInsn = true;
279 else if (MO.isKill())
280 isVirtKillInsn = true;
283 Candidates.reset(MO.getReg());
284 for (const unsigned *R = TRI->getAliasSet(MO.getReg()); *R; R++)
285 Candidates.reset(*R);
287 // If we're not in a virtual reg's live range, this is a valid
289 if (!inVirtLiveRange) RestorePointMI = MI;
291 // Update whether we're in the live range of a virtual register
292 if (isVirtKillInsn) inVirtLiveRange = false;
293 if (isVirtDefInsn) inVirtLiveRange = true;
295 // Was our survivor untouched by this instruction?
296 if (Candidates.test(Survivor))
299 // All candidates gone?
300 if (Candidates.none())
303 Survivor = Candidates.find_first();
305 // If we ran off the end, that's where we want to restore.
306 if (MI == ME) RestorePointMI = ME;
307 assert (RestorePointMI != StartMI &&
308 "No available scavenger restore location!");
310 // We ran out of candidates, so stop the search.
311 UseMI = RestorePointMI;
315 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
316 MachineBasicBlock::iterator I,
318 // Mask off the registers which are not in the TargetRegisterClass.
319 BitVector Candidates(NumPhysRegs, false);
320 CreateRegClassMask(RC, Candidates);
321 // Do not include reserved registers.
322 Candidates ^= ReservedRegs & Candidates;
324 // Exclude all the registers being used by the instruction.
325 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
326 MachineOperand &MO = I->getOperand(i);
327 if (MO.isReg() && MO.getReg() != 0 &&
328 !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
329 Candidates.reset(MO.getReg());
332 // Find the register whose use is furthest away.
333 MachineBasicBlock::iterator UseMI;
334 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
336 // If we found an unused register there is no reason to spill it. We have
337 // probably found a callee-saved register that has been saved in the
338 // prologue, but happens to be unused at this point.
339 if (!isAliasUsed(SReg))
342 assert(ScavengedReg == 0 &&
343 "Scavenger slot is live, unable to scavenge another register!");
345 // Avoid infinite regress
348 // If the target knows how to save/restore the register, let it do so;
349 // otherwise, use the emergency stack spill slot.
350 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {
351 // Spill the scavenged register before I.
352 assert(ScavengingFrameIndex >= 0 &&
353 "Cannot scavenge register without an emergency spill slot!");
354 TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC,TRI);
355 MachineBasicBlock::iterator II = prior(I);
356 TRI->eliminateFrameIndex(II, SPAdj, NULL, this);
358 // Restore the scavenged register before its use (or first terminator).
359 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC, TRI);
361 TRI->eliminateFrameIndex(II, SPAdj, NULL, this);
364 ScavengeRestore = prior(UseMI);
366 // Doing this here leads to infinite regress.
367 // ScavengedReg = SReg;