1 //===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the machine register scavenger. It can provide
11 // information, such as unused registers, at any point in a machine basic block.
12 // It also provides a mechanism to make registers available by evicting them to
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "reg-scavenging"
18 #include "llvm/CodeGen/RegisterScavenging.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineBasicBlock.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Target/TargetRegisterInfo.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/ADT/SmallPtrSet.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/STLExtras.h"
33 /// RedefinesSuperRegPart - Return true if the specified register is redefining
34 /// part of a super-register.
35 static bool RedefinesSuperRegPart(const MachineInstr *MI, unsigned SubReg,
36 const TargetRegisterInfo *TRI) {
37 bool SeenSuperUse = false;
38 bool SeenSuperDef = false;
39 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
40 const MachineOperand &MO = MI->getOperand(i);
41 if (!MO.isReg() || MO.isUndef())
43 if (TRI->isSuperRegister(SubReg, MO.getReg())) {
46 else if (MO.isImplicit())
51 return SeenSuperDef && SeenSuperUse;
54 static bool RedefinesSuperRegPart(const MachineInstr *MI,
55 const MachineOperand &MO,
56 const TargetRegisterInfo *TRI) {
57 assert(MO.isReg() && MO.isDef() && "Not a register def!");
58 return RedefinesSuperRegPart(MI, MO.getReg(), TRI);
61 bool RegScavenger::isSuperRegUsed(unsigned Reg) const {
62 for (const unsigned *SuperRegs = TRI->getSuperRegisters(Reg);
63 unsigned SuperReg = *SuperRegs; ++SuperRegs)
69 /// setUsed - Set the register and its sub-registers as being used.
70 void RegScavenger::setUsed(unsigned Reg) {
71 RegsAvailable.reset(Reg);
73 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
74 unsigned SubReg = *SubRegs; ++SubRegs)
75 RegsAvailable.reset(SubReg);
78 /// setUnused - Set the register and its sub-registers as being unused.
79 void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) {
80 RegsAvailable.set(Reg);
82 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
83 unsigned SubReg = *SubRegs; ++SubRegs)
84 if (!RedefinesSuperRegPart(MI, Reg, TRI))
85 RegsAvailable.set(SubReg);
88 void RegScavenger::initRegState() {
91 ScavengeRestore = NULL;
95 // All registers started out unused.
98 // Reserved registers are always used.
99 RegsAvailable ^= ReservedRegs;
101 // Live-in registers are in use.
102 if (!MBB || MBB->livein_empty())
104 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
105 E = MBB->livein_end(); I != E; ++I)
109 void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
110 MachineFunction &MF = *mbb->getParent();
111 const TargetMachine &TM = MF.getTarget();
112 TII = TM.getInstrInfo();
113 TRI = TM.getRegisterInfo();
114 MRI = &MF.getRegInfo();
116 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
121 NumPhysRegs = TRI->getNumRegs();
122 RegsAvailable.resize(NumPhysRegs);
124 // Create reserved registers bitvector.
125 ReservedRegs = TRI->getReservedRegs(MF);
127 // Create callee-saved registers bitvector.
128 CalleeSavedRegs.resize(NumPhysRegs);
129 const unsigned *CSRegs = TRI->getCalleeSavedRegs();
131 for (unsigned i = 0; CSRegs[i]; ++i)
132 CalleeSavedRegs.set(CSRegs[i]);
135 // RS used within emit{Pro,Epi}logue()
144 void RegScavenger::restoreScavengedReg() {
145 TII->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
146 ScavengingFrameIndex, ScavengedRC);
147 MachineBasicBlock::iterator II = prior(MBBI);
148 TRI->eliminateFrameIndex(II, 0, this);
149 setUsed(ScavengedReg);
155 /// isLiveInButUnusedBefore - Return true if register is livein the MBB not
156 /// not used before it reaches the MI that defines register.
157 static bool isLiveInButUnusedBefore(unsigned Reg, MachineInstr *MI,
158 MachineBasicBlock *MBB,
159 const TargetRegisterInfo *TRI,
160 MachineRegisterInfo* MRI) {
161 // First check if register is livein.
162 bool isLiveIn = false;
163 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
164 E = MBB->livein_end(); I != E; ++I)
165 if (Reg == *I || TRI->isSuperRegister(Reg, *I)) {
172 // Is there any use of it before the specified MI?
173 SmallPtrSet<MachineInstr*, 4> UsesInMBB;
174 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
175 UE = MRI->use_end(); UI != UE; ++UI) {
176 MachineOperand &UseMO = UI.getOperand();
177 if (UseMO.isReg() && UseMO.isUndef())
179 MachineInstr *UseMI = &*UI;
180 if (UseMI->getParent() == MBB)
181 UsesInMBB.insert(UseMI);
183 if (UsesInMBB.empty())
186 for (MachineBasicBlock::iterator I = MBB->begin(), E = MI; I != E; ++I)
187 if (UsesInMBB.count(&*I))
193 void RegScavenger::forward() {
199 assert(MBBI != MBB->end() && "Already at the end of the basic block!");
203 MachineInstr *MI = MBBI;
204 DistanceMap.insert(std::make_pair(MI, CurrDist++));
206 if (MI == ScavengeRestore) {
209 ScavengeRestore = NULL;
212 // Separate register operands into 3 classes: uses, defs, earlyclobbers.
213 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs;
214 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> DefMOs;
215 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> EarlyClobberMOs;
216 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
217 const MachineOperand &MO = MI->getOperand(i);
218 if (!MO.isReg() || MO.getReg() == 0 || MO.isUndef())
221 UseMOs.push_back(std::make_pair(&MO,i));
222 else if (MO.isEarlyClobber())
223 EarlyClobberMOs.push_back(std::make_pair(&MO,i));
226 DefMOs.push_back(std::make_pair(&MO,i));
230 // Process uses first.
231 BitVector KillRegs(NumPhysRegs);
232 for (unsigned i = 0, e = UseMOs.size(); i != e; ++i) {
233 const MachineOperand MO = *UseMOs[i].first;
234 unsigned Idx = UseMOs[i].second;
235 unsigned Reg = MO.getReg();
237 assert(isUsed(Reg) && "Using an undefined register!");
239 // Two-address operands implicitly kill.
240 if ((MO.isKill() || MI->isRegTiedToDefOperand(Idx)) && !isReserved(Reg)) {
243 // Mark sub-registers as used.
244 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
245 unsigned SubReg = *SubRegs; ++SubRegs)
246 KillRegs.set(SubReg);
250 // Change states of all registers after all the uses are processed to guard
251 // against multiple uses.
254 // Process early clobber defs then process defs. We can have a early clobber
255 // that is dead, it should not conflict with a def that happens one "slot"
256 // (see InstrSlots in LiveIntervalAnalysis.h) later.
257 unsigned NumECs = EarlyClobberMOs.size();
258 unsigned NumDefs = DefMOs.size();
260 for (unsigned i = 0, e = NumECs + NumDefs; i != e; ++i) {
261 const MachineOperand &MO = (i < NumECs)
262 ? *EarlyClobberMOs[i].first : *DefMOs[i-NumECs].first;
263 unsigned Reg = MO.getReg();
267 // If it's dead upon def, then it is now free.
273 // Skip if this is merely redefining part of a super-register.
274 if (RedefinesSuperRegPart(MI, MO, TRI))
277 assert((isReserved(Reg) || isUnused(Reg) || isSuperRegUsed(Reg) ||
278 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
279 "Re-defining a live register!");
284 void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
286 used = ~RegsAvailable;
288 used = ~RegsAvailable & ~ReservedRegs;
291 /// CreateRegClassMask - Set the bits that represent the registers in the
292 /// TargetRegisterClass.
293 static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {
294 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E;
299 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
300 const BitVector &Candidates) const {
301 // Mask off the registers which are not in the TargetRegisterClass.
302 BitVector RegsAvailableCopy(NumPhysRegs, false);
303 CreateRegClassMask(RegClass, RegsAvailableCopy);
304 RegsAvailableCopy &= RegsAvailable;
306 // Restrict the search to candidates.
307 RegsAvailableCopy &= Candidates;
309 // Returns the first unused (bit is set) register, or 0 is none is found.
310 int Reg = RegsAvailableCopy.find_first();
311 return (Reg == -1) ? 0 : Reg;
314 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
315 bool ExCalleeSaved) const {
316 // Mask off the registers which are not in the TargetRegisterClass.
317 BitVector RegsAvailableCopy(NumPhysRegs, false);
318 CreateRegClassMask(RegClass, RegsAvailableCopy);
319 RegsAvailableCopy &= RegsAvailable;
321 // If looking for a non-callee-saved register, mask off all the callee-saved
324 RegsAvailableCopy &= ~CalleeSavedRegs;
326 // Returns the first unused (bit is set) register, or 0 is none is found.
327 int Reg = RegsAvailableCopy.find_first();
328 return (Reg == -1) ? 0 : Reg;
331 /// findFirstUse - Calculate the distance to the first use of the
332 /// specified register.
334 RegScavenger::findFirstUse(MachineBasicBlock *MBB,
335 MachineBasicBlock::iterator I, unsigned Reg,
337 MachineInstr *UseMI = 0;
339 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(Reg),
340 RE = MRI->reg_end(); RI != RE; ++RI) {
341 MachineInstr *UDMI = &*RI;
342 if (UDMI->getParent() != MBB)
344 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UDMI);
345 if (DI == DistanceMap.end()) {
346 // If it's not in map, it's below current MI, let's initialize the
349 unsigned Dist = CurrDist + 1;
350 while (I != MBB->end()) {
351 DistanceMap.insert(std::make_pair(I, Dist++));
355 DI = DistanceMap.find(UDMI);
356 if (DI->second > CurrDist && DI->second < Dist) {
364 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
365 MachineBasicBlock::iterator I,
367 assert(ScavengingFrameIndex >= 0 &&
368 "Cannot scavenge a register without an emergency spill slot!");
370 // Mask off the registers which are not in the TargetRegisterClass.
371 BitVector Candidates(NumPhysRegs, false);
372 CreateRegClassMask(RC, Candidates);
373 // Do not include reserved registers.
374 Candidates ^= ReservedRegs & Candidates;
376 // Exclude all the registers being used by the instruction.
377 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
378 MachineOperand &MO = I->getOperand(i);
380 Candidates.reset(MO.getReg());
383 // Find the register whose use is furthest away.
385 unsigned MaxDist = 0;
386 MachineInstr *MaxUseMI = 0;
387 int Reg = Candidates.find_first();
390 MachineInstr *UseMI = findFirstUse(MBB, I, Reg, Dist);
391 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
393 MachineInstr *AsUseMI = findFirstUse(MBB, I, *AS, AsDist);
399 if (Dist >= MaxDist) {
404 Reg = Candidates.find_next(Reg);
407 assert(ScavengedReg == 0 &&
408 "Scavenger slot is live, unable to scavenge another register!");
410 // Avoid infinite regress
413 // Make sure SReg is marked as used. It could be considered available
414 // if it is one of the callee saved registers, but hasn't been spilled.
416 MBB->addLiveIn(SReg);
420 // Spill the scavenged register before I.
421 TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
422 MachineBasicBlock::iterator II = prior(I);
423 TRI->eliminateFrameIndex(II, SPAdj, this);
425 // Restore the scavenged register before its use (or first terminator).
427 ? MachineBasicBlock::iterator(MaxUseMI) : MBB->getFirstTerminator();
428 TII->loadRegFromStackSlot(*MBB, II, SReg, ScavengingFrameIndex, RC);
429 ScavengeRestore = prior(II);
430 // Doing this here leads to infinite regress.
431 // ScavengedReg = SReg;