1 //===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the machine register scavenger. It can provide
11 // information, such as unused registers, at any point in a machine basic block.
12 // It also provides a mechanism to make registers available by evicting them to
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "reg-scavenging"
18 #include "llvm/CodeGen/RegisterScavenging.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/ADT/SmallPtrSet.h"
27 #include "llvm/ADT/STLExtras.h"
30 /// RedefinesSuperRegPart - Return true if the specified register is redefining
31 /// part of a super-register.
32 static bool RedefinesSuperRegPart(const MachineInstr *MI, unsigned SubReg,
33 const TargetRegisterInfo *TRI) {
34 bool SeenSuperUse = false;
35 bool SeenSuperDef = false;
36 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
37 const MachineOperand &MO = MI->getOperand(i);
40 if (TRI->isSuperRegister(SubReg, MO.getReg())) {
43 else if (MO.isImplicit())
48 return SeenSuperDef && SeenSuperUse;
51 static bool RedefinesSuperRegPart(const MachineInstr *MI,
52 const MachineOperand &MO,
53 const TargetRegisterInfo *TRI) {
54 assert(MO.isReg() && MO.isDef() && "Not a register def!");
55 return RedefinesSuperRegPart(MI, MO.getReg(), TRI);
58 /// setUsed - Set the register and its sub-registers as being used.
59 void RegScavenger::setUsed(unsigned Reg, bool ImpDef) {
60 RegsAvailable.reset(Reg);
61 ImplicitDefed[Reg] = ImpDef;
63 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
64 unsigned SubReg = *SubRegs; ++SubRegs) {
65 RegsAvailable.reset(SubReg);
66 ImplicitDefed[SubReg] = ImpDef;
70 /// setUnused - Set the register and its sub-registers as being unused.
71 void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) {
72 RegsAvailable.set(Reg);
73 ImplicitDefed.reset(Reg);
75 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
76 unsigned SubReg = *SubRegs; ++SubRegs)
77 if (!RedefinesSuperRegPart(MI, Reg, TRI)) {
78 RegsAvailable.set(SubReg);
79 ImplicitDefed.reset(SubReg);
83 void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
84 MachineFunction &MF = *mbb->getParent();
85 const TargetMachine &TM = MF.getTarget();
86 TII = TM.getInstrInfo();
87 TRI = TM.getRegisterInfo();
88 MRI = &MF.getRegInfo();
90 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
94 NumPhysRegs = TRI->getNumRegs();
95 RegsAvailable.resize(NumPhysRegs);
96 ImplicitDefed.resize(NumPhysRegs);
98 // Create reserved registers bitvector.
99 ReservedRegs = TRI->getReservedRegs(MF);
101 // Create callee-saved registers bitvector.
102 CalleeSavedRegs.resize(NumPhysRegs);
103 const unsigned *CSRegs = TRI->getCalleeSavedRegs();
105 for (unsigned i = 0; CSRegs[i]; ++i)
106 CalleeSavedRegs.set(CSRegs[i]);
112 ScavengeRestore = NULL;
116 // All registers started out unused.
119 // Reserved registers are always used.
120 RegsAvailable ^= ReservedRegs;
122 // Live-in registers are in use.
123 if (!MBB->livein_empty())
124 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
125 E = MBB->livein_end(); I != E; ++I)
131 void RegScavenger::restoreScavengedReg() {
132 TII->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
133 ScavengingFrameIndex, ScavengedRC);
134 MachineBasicBlock::iterator II = prior(MBBI);
135 TRI->eliminateFrameIndex(II, 0, this);
136 setUsed(ScavengedReg);
141 /// isLiveInButUnusedBefore - Return true if register is livein the MBB not
142 /// not used before it reaches the MI that defines register.
143 static bool isLiveInButUnusedBefore(unsigned Reg, MachineInstr *MI,
144 MachineBasicBlock *MBB,
145 const TargetRegisterInfo *TRI,
146 MachineRegisterInfo* MRI) {
147 // First check if register is livein.
148 bool isLiveIn = false;
149 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
150 E = MBB->livein_end(); I != E; ++I)
151 if (Reg == *I || TRI->isSuperRegister(Reg, *I)) {
158 // Is there any use of it before the specified MI?
159 SmallPtrSet<MachineInstr*, 4> UsesInMBB;
160 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
161 UE = MRI->use_end(); UI != UE; ++UI) {
162 MachineInstr *UseMI = &*UI;
163 if (UseMI->getParent() == MBB)
164 UsesInMBB.insert(UseMI);
166 if (UsesInMBB.empty())
169 for (MachineBasicBlock::iterator I = MBB->begin(), E = MI; I != E; ++I)
170 if (UsesInMBB.count(&*I))
175 void RegScavenger::forward() {
181 assert(MBBI != MBB->end() && "Already at the end of the basic block!");
185 MachineInstr *MI = MBBI;
186 DistanceMap.insert(std::make_pair(MI, CurrDist++));
187 const TargetInstrDesc &TID = MI->getDesc();
189 if (MI == ScavengeRestore) {
192 ScavengeRestore = NULL;
195 bool IsImpDef = MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF;
197 // Separate register operands into 3 classes: uses, defs, earlyclobbers.
198 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs;
199 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> DefMOs;
200 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> EarlyClobberMOs;
201 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
202 const MachineOperand &MO = MI->getOperand(i);
203 if (!MO.isReg() || MO.getReg() == 0)
206 UseMOs.push_back(std::make_pair(&MO,i));
207 else if (MO.isEarlyClobber())
208 EarlyClobberMOs.push_back(std::make_pair(&MO,i));
210 DefMOs.push_back(std::make_pair(&MO,i));
213 // Process uses first.
214 BitVector UseRegs(NumPhysRegs);
215 for (unsigned i = 0, e = UseMOs.size(); i != e; ++i) {
216 const MachineOperand MO = *UseMOs[i].first;
217 unsigned Reg = MO.getReg();
219 assert(isUsed(Reg) && "Using an undefined register!");
221 if (MO.isKill() && !isReserved(Reg)) {
224 // Mark sub-registers as used.
225 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
226 unsigned SubReg = *SubRegs; ++SubRegs)
231 // Change states of all registers after all the uses are processed to guard
232 // against multiple uses.
235 // Process early clobber defs then process defs. We can have a early clobber
236 // that is dead, it should not conflict with a def that happens one "slot"
237 // (see InstrSlots in LiveIntervalAnalysis.h) later.
238 unsigned NumECs = EarlyClobberMOs.size();
239 unsigned NumDefs = DefMOs.size();
241 for (unsigned i = 0, e = NumECs + NumDefs; i != e; ++i) {
242 const MachineOperand &MO = (i < NumECs)
243 ? *EarlyClobberMOs[i].first : *DefMOs[i-NumECs].first;
244 unsigned Idx = (i < NumECs)
245 ? EarlyClobberMOs[i].second : DefMOs[i-NumECs].second;
246 unsigned Reg = MO.getReg();
248 // If it's dead upon def, then it is now free.
254 // Skip two-address destination operand.
255 if (TID.findTiedToSrcOperand(Idx) != -1) {
256 assert(isUsed(Reg) && "Using an undefined register!");
260 // Skip if this is merely redefining part of a super-register.
261 if (RedefinesSuperRegPart(MI, MO, TRI))
264 // Implicit def is allowed to "re-define" any register. Similarly,
265 // implicitly defined registers can be clobbered.
266 assert((isReserved(Reg) || isUnused(Reg) ||
267 IsImpDef || isImplicitlyDefined(Reg) ||
268 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
269 "Re-defining a live register!");
270 setUsed(Reg, IsImpDef);
274 void RegScavenger::backward() {
275 assert(Tracking && "Not tracking states!");
276 assert(MBBI != MBB->begin() && "Already at start of basic block!");
277 // Move ptr backward.
280 MachineInstr *MI = MBBI;
281 DistanceMap.erase(MI);
283 const TargetInstrDesc &TID = MI->getDesc();
285 // Separate register operands into 3 classes: uses, defs, earlyclobbers.
286 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs;
287 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> DefMOs;
288 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> EarlyClobberMOs;
289 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
290 const MachineOperand &MO = MI->getOperand(i);
291 if (!MO.isReg() || MO.getReg() == 0)
294 UseMOs.push_back(std::make_pair(&MO,i));
295 else if (MO.isEarlyClobber())
296 EarlyClobberMOs.push_back(std::make_pair(&MO,i));
298 DefMOs.push_back(std::make_pair(&MO,i));
302 // Process defs first.
303 unsigned NumECs = EarlyClobberMOs.size();
304 unsigned NumDefs = DefMOs.size();
305 for (unsigned i = 0, e = NumECs + NumDefs; i != e; ++i) {
306 const MachineOperand &MO = (i < NumDefs)
307 ? *DefMOs[i].first : *EarlyClobberMOs[i-NumDefs].first;
308 unsigned Idx = (i < NumECs)
309 ? DefMOs[i].second : EarlyClobberMOs[i-NumDefs].second;
311 // Skip two-address destination operand.
312 if (TID.findTiedToSrcOperand(Idx) != -1)
315 unsigned Reg = MO.getReg();
317 if (!isReserved(Reg))
322 BitVector UseRegs(NumPhysRegs);
323 for (unsigned i = 0, e = UseMOs.size(); i != e; ++i) {
324 const MachineOperand MO = *UseMOs[i].first;
325 unsigned Reg = MO.getReg();
326 assert(isUnused(Reg) || isReserved(Reg));
329 // Set the sub-registers as "used".
330 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
331 unsigned SubReg = *SubRegs; ++SubRegs)
337 void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
339 used = ~RegsAvailable;
341 used = ~RegsAvailable & ~ReservedRegs;
344 /// CreateRegClassMask - Set the bits that represent the registers in the
345 /// TargetRegisterClass.
346 static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {
347 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E;
352 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
353 const BitVector &Candidates) const {
354 // Mask off the registers which are not in the TargetRegisterClass.
355 BitVector RegsAvailableCopy(NumPhysRegs, false);
356 CreateRegClassMask(RegClass, RegsAvailableCopy);
357 RegsAvailableCopy &= RegsAvailable;
359 // Restrict the search to candidates.
360 RegsAvailableCopy &= Candidates;
362 // Returns the first unused (bit is set) register, or 0 is none is found.
363 int Reg = RegsAvailableCopy.find_first();
364 return (Reg == -1) ? 0 : Reg;
367 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
368 bool ExCalleeSaved) const {
369 // Mask off the registers which are not in the TargetRegisterClass.
370 BitVector RegsAvailableCopy(NumPhysRegs, false);
371 CreateRegClassMask(RegClass, RegsAvailableCopy);
372 RegsAvailableCopy &= RegsAvailable;
374 // If looking for a non-callee-saved register, mask off all the callee-saved
377 RegsAvailableCopy &= ~CalleeSavedRegs;
379 // Returns the first unused (bit is set) register, or 0 is none is found.
380 int Reg = RegsAvailableCopy.find_first();
381 return (Reg == -1) ? 0 : Reg;
384 /// findFirstUse - Calculate the distance to the first use of the
385 /// specified register.
387 RegScavenger::findFirstUse(MachineBasicBlock *MBB,
388 MachineBasicBlock::iterator I, unsigned Reg,
390 MachineInstr *UseMI = 0;
392 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(Reg),
393 RE = MRI->reg_end(); RI != RE; ++RI) {
394 MachineInstr *UDMI = &*RI;
395 if (UDMI->getParent() != MBB)
397 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UDMI);
398 if (DI == DistanceMap.end()) {
399 // If it's not in map, it's below current MI, let's initialize the
402 unsigned Dist = CurrDist + 1;
403 while (I != MBB->end()) {
404 DistanceMap.insert(std::make_pair(I, Dist++));
408 DI = DistanceMap.find(UDMI);
409 if (DI->second > CurrDist && DI->second < Dist) {
417 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
418 MachineBasicBlock::iterator I,
420 assert(ScavengingFrameIndex >= 0 &&
421 "Cannot scavenge a register without an emergency spill slot!");
423 // Mask off the registers which are not in the TargetRegisterClass.
424 BitVector Candidates(NumPhysRegs, false);
425 CreateRegClassMask(RC, Candidates);
426 Candidates ^= ReservedRegs; // Do not include reserved registers.
428 // Exclude all the registers being used by the instruction.
429 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
430 MachineOperand &MO = I->getOperand(i);
432 Candidates.reset(MO.getReg());
435 // Find the register whose use is furthest away.
437 unsigned MaxDist = 0;
438 MachineInstr *MaxUseMI = 0;
439 int Reg = Candidates.find_first();
442 MachineInstr *UseMI = findFirstUse(MBB, I, Reg, Dist);
443 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
445 MachineInstr *AsUseMI = findFirstUse(MBB, I, *AS, AsDist);
451 if (Dist >= MaxDist) {
456 Reg = Candidates.find_next(Reg);
459 if (ScavengedReg != 0) {
460 assert(0 && "Scavenger slot is live, unable to scavenge another register!");
464 // Spill the scavenged register before I.
465 TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
466 MachineBasicBlock::iterator II = prior(I);
467 TRI->eliminateFrameIndex(II, SPAdj, this);
469 // Restore the scavenged register before its use (or first terminator).
471 ? MachineBasicBlock::iterator(MaxUseMI) : MBB->getFirstTerminator();
472 TII->loadRegFromStackSlot(*MBB, II, SReg, ScavengingFrameIndex, RC);
473 ScavengeRestore = prior(II);