1 //===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the machine register scavenger. It can provide
11 // information, such as unused registers, at any point in a machine basic block.
12 // It also provides a mechanism to make registers available by evicting them to
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "reg-scavenging"
18 #include "llvm/CodeGen/RegisterScavenging.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/ADT/SmallPtrSet.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/ADT/STLExtras.h"
32 /// RedefinesSuperRegPart - Return true if the specified register is redefining
33 /// part of a super-register.
34 static bool RedefinesSuperRegPart(const MachineInstr *MI, unsigned SubReg,
35 const TargetRegisterInfo *TRI) {
36 bool SeenSuperUse = false;
37 bool SeenSuperDef = false;
38 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
39 const MachineOperand &MO = MI->getOperand(i);
40 if (!MO.isReg() || MO.isUndef())
42 if (TRI->isSuperRegister(SubReg, MO.getReg())) {
45 else if (MO.isImplicit())
50 return SeenSuperDef && SeenSuperUse;
53 static bool RedefinesSuperRegPart(const MachineInstr *MI,
54 const MachineOperand &MO,
55 const TargetRegisterInfo *TRI) {
56 assert(MO.isReg() && MO.isDef() && "Not a register def!");
57 return RedefinesSuperRegPart(MI, MO.getReg(), TRI);
60 /// setUsed - Set the register and its sub-registers as being used.
61 void RegScavenger::setUsed(unsigned Reg) {
62 RegsAvailable.reset(Reg);
64 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
65 unsigned SubReg = *SubRegs; ++SubRegs)
66 RegsAvailable.reset(SubReg);
69 /// setUnused - Set the register and its sub-registers as being unused.
70 void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) {
71 RegsAvailable.set(Reg);
73 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
74 unsigned SubReg = *SubRegs; ++SubRegs)
75 if (!RedefinesSuperRegPart(MI, Reg, TRI))
76 RegsAvailable.set(SubReg);
79 void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
80 MachineFunction &MF = *mbb->getParent();
81 const TargetMachine &TM = MF.getTarget();
82 TII = TM.getInstrInfo();
83 TRI = TM.getRegisterInfo();
84 MRI = &MF.getRegInfo();
86 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
90 NumPhysRegs = TRI->getNumRegs();
91 RegsAvailable.resize(NumPhysRegs);
93 // Create reserved registers bitvector.
94 ReservedRegs = TRI->getReservedRegs(MF);
96 // Create callee-saved registers bitvector.
97 CalleeSavedRegs.resize(NumPhysRegs);
98 const unsigned *CSRegs = TRI->getCalleeSavedRegs();
100 for (unsigned i = 0; CSRegs[i]; ++i)
101 CalleeSavedRegs.set(CSRegs[i]);
107 ScavengeRestore = NULL;
111 // All registers started out unused.
114 // Reserved registers are always used.
115 RegsAvailable ^= ReservedRegs;
117 // Live-in registers are in use.
118 if (!MBB->livein_empty())
119 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
120 E = MBB->livein_end(); I != E; ++I)
126 void RegScavenger::restoreScavengedReg() {
127 TII->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
128 ScavengingFrameIndex, ScavengedRC);
129 MachineBasicBlock::iterator II = prior(MBBI);
130 TRI->eliminateFrameIndex(II, 0, this);
131 setUsed(ScavengedReg);
137 /// isLiveInButUnusedBefore - Return true if register is livein the MBB not
138 /// not used before it reaches the MI that defines register.
139 static bool isLiveInButUnusedBefore(unsigned Reg, MachineInstr *MI,
140 MachineBasicBlock *MBB,
141 const TargetRegisterInfo *TRI,
142 MachineRegisterInfo* MRI) {
143 // First check if register is livein.
144 bool isLiveIn = false;
145 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
146 E = MBB->livein_end(); I != E; ++I)
147 if (Reg == *I || TRI->isSuperRegister(Reg, *I)) {
154 // Is there any use of it before the specified MI?
155 SmallPtrSet<MachineInstr*, 4> UsesInMBB;
156 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
157 UE = MRI->use_end(); UI != UE; ++UI) {
158 MachineOperand &UseMO = UI.getOperand();
159 if (UseMO.isReg() && UseMO.isUndef())
161 MachineInstr *UseMI = &*UI;
162 if (UseMI->getParent() == MBB)
163 UsesInMBB.insert(UseMI);
165 if (UsesInMBB.empty())
168 for (MachineBasicBlock::iterator I = MBB->begin(), E = MI; I != E; ++I)
169 if (UsesInMBB.count(&*I))
175 void RegScavenger::forward() {
181 assert(MBBI != MBB->end() && "Already at the end of the basic block!");
185 MachineInstr *MI = MBBI;
186 DistanceMap.insert(std::make_pair(MI, CurrDist++));
188 if (MI == ScavengeRestore) {
191 ScavengeRestore = NULL;
195 if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
199 // Separate register operands into 3 classes: uses, defs, earlyclobbers.
200 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs;
201 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> DefMOs;
202 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> EarlyClobberMOs;
203 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
204 const MachineOperand &MO = MI->getOperand(i);
205 if (!MO.isReg() || MO.getReg() == 0 || MO.isUndef())
208 UseMOs.push_back(std::make_pair(&MO,i));
209 else if (MO.isEarlyClobber())
210 EarlyClobberMOs.push_back(std::make_pair(&MO,i));
212 DefMOs.push_back(std::make_pair(&MO,i));
215 // Process uses first.
216 BitVector KillRegs(NumPhysRegs);
217 for (unsigned i = 0, e = UseMOs.size(); i != e; ++i) {
218 const MachineOperand MO = *UseMOs[i].first;
219 unsigned Reg = MO.getReg();
221 assert(isUsed(Reg) && "Using an undefined register!");
223 if (MO.isKill() && !isReserved(Reg)) {
226 // Mark sub-registers as used.
227 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
228 unsigned SubReg = *SubRegs; ++SubRegs)
229 KillRegs.set(SubReg);
233 // Change states of all registers after all the uses are processed to guard
234 // against multiple uses.
237 // Process early clobber defs then process defs. We can have a early clobber
238 // that is dead, it should not conflict with a def that happens one "slot"
239 // (see InstrSlots in LiveIntervalAnalysis.h) later.
240 unsigned NumECs = EarlyClobberMOs.size();
241 unsigned NumDefs = DefMOs.size();
243 for (unsigned i = 0, e = NumECs + NumDefs; i != e; ++i) {
244 const MachineOperand &MO = (i < NumECs)
245 ? *EarlyClobberMOs[i].first : *DefMOs[i-NumECs].first;
246 unsigned Idx = (i < NumECs)
247 ? EarlyClobberMOs[i].second : DefMOs[i-NumECs].second;
248 unsigned Reg = MO.getReg();
252 // If it's dead upon def, then it is now free.
258 // Skip two-address destination operand.
260 if (MI->isRegTiedToUseOperand(Idx, &UseIdx) &&
261 !MI->getOperand(UseIdx).isUndef()) {
262 assert(isUsed(Reg) && "Using an undefined register!");
266 // Skip if this is merely redefining part of a super-register.
267 if (RedefinesSuperRegPart(MI, MO, TRI))
270 // Implicit def is allowed to "re-define" any register. Similarly,
271 // implicitly defined registers can be clobbered.
272 assert((isReserved(Reg) || isUnused(Reg) ||
273 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
274 "Re-defining a live register!");
279 void RegScavenger::backward() {
280 assert(Tracking && "Not tracking states!");
281 assert(MBBI != MBB->begin() && "Already at start of basic block!");
282 // Move ptr backward.
285 MachineInstr *MI = MBBI;
286 DistanceMap.erase(MI);
289 // Separate register operands into 3 classes: uses, defs, earlyclobbers.
290 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs;
291 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> DefMOs;
292 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> EarlyClobberMOs;
293 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
294 const MachineOperand &MO = MI->getOperand(i);
295 if (!MO.isReg() || MO.getReg() == 0 || MO.isUndef())
298 UseMOs.push_back(std::make_pair(&MO,i));
299 else if (MO.isEarlyClobber())
300 EarlyClobberMOs.push_back(std::make_pair(&MO,i));
302 DefMOs.push_back(std::make_pair(&MO,i));
306 // Process defs first.
307 unsigned NumECs = EarlyClobberMOs.size();
308 unsigned NumDefs = DefMOs.size();
309 for (unsigned i = 0, e = NumECs + NumDefs; i != e; ++i) {
310 const MachineOperand &MO = (i < NumDefs)
311 ? *DefMOs[i].first : *EarlyClobberMOs[i-NumDefs].first;
312 unsigned Idx = (i < NumECs)
313 ? DefMOs[i].second : EarlyClobberMOs[i-NumDefs].second;
317 // Skip two-address destination operand.
318 if (MI->isRegTiedToUseOperand(Idx))
321 unsigned Reg = MO.getReg();
323 if (!isReserved(Reg))
328 BitVector UseRegs(NumPhysRegs);
329 for (unsigned i = 0, e = UseMOs.size(); i != e; ++i) {
330 const MachineOperand MO = *UseMOs[i].first;
331 unsigned Reg = MO.getReg();
332 assert(isUnused(Reg) || isReserved(Reg));
335 // Set the sub-registers as "used".
336 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
337 unsigned SubReg = *SubRegs; ++SubRegs)
343 void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
345 used = ~RegsAvailable;
347 used = ~RegsAvailable & ~ReservedRegs;
350 /// CreateRegClassMask - Set the bits that represent the registers in the
351 /// TargetRegisterClass.
352 static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {
353 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E;
358 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
359 const BitVector &Candidates) const {
360 // Mask off the registers which are not in the TargetRegisterClass.
361 BitVector RegsAvailableCopy(NumPhysRegs, false);
362 CreateRegClassMask(RegClass, RegsAvailableCopy);
363 RegsAvailableCopy &= RegsAvailable;
365 // Restrict the search to candidates.
366 RegsAvailableCopy &= Candidates;
368 // Returns the first unused (bit is set) register, or 0 is none is found.
369 int Reg = RegsAvailableCopy.find_first();
370 return (Reg == -1) ? 0 : Reg;
373 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
374 bool ExCalleeSaved) const {
375 // Mask off the registers which are not in the TargetRegisterClass.
376 BitVector RegsAvailableCopy(NumPhysRegs, false);
377 CreateRegClassMask(RegClass, RegsAvailableCopy);
378 RegsAvailableCopy &= RegsAvailable;
380 // If looking for a non-callee-saved register, mask off all the callee-saved
383 RegsAvailableCopy &= ~CalleeSavedRegs;
385 // Returns the first unused (bit is set) register, or 0 is none is found.
386 int Reg = RegsAvailableCopy.find_first();
387 return (Reg == -1) ? 0 : Reg;
390 /// findFirstUse - Calculate the distance to the first use of the
391 /// specified register.
393 RegScavenger::findFirstUse(MachineBasicBlock *MBB,
394 MachineBasicBlock::iterator I, unsigned Reg,
396 MachineInstr *UseMI = 0;
398 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(Reg),
399 RE = MRI->reg_end(); RI != RE; ++RI) {
400 MachineInstr *UDMI = &*RI;
401 if (UDMI->getParent() != MBB)
403 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UDMI);
404 if (DI == DistanceMap.end()) {
405 // If it's not in map, it's below current MI, let's initialize the
408 unsigned Dist = CurrDist + 1;
409 while (I != MBB->end()) {
410 DistanceMap.insert(std::make_pair(I, Dist++));
414 DI = DistanceMap.find(UDMI);
415 if (DI->second > CurrDist && DI->second < Dist) {
423 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
424 MachineBasicBlock::iterator I,
426 assert(ScavengingFrameIndex >= 0 &&
427 "Cannot scavenge a register without an emergency spill slot!");
429 // Mask off the registers which are not in the TargetRegisterClass.
430 BitVector Candidates(NumPhysRegs, false);
431 CreateRegClassMask(RC, Candidates);
432 Candidates ^= ReservedRegs & Candidates; // Do not include reserved registers.
434 // Exclude all the registers being used by the instruction.
435 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
436 MachineOperand &MO = I->getOperand(i);
438 Candidates.reset(MO.getReg());
441 // Find the register whose use is furthest away.
443 unsigned MaxDist = 0;
444 MachineInstr *MaxUseMI = 0;
445 int Reg = Candidates.find_first();
448 MachineInstr *UseMI = findFirstUse(MBB, I, Reg, Dist);
449 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
451 MachineInstr *AsUseMI = findFirstUse(MBB, I, *AS, AsDist);
457 if (Dist >= MaxDist) {
462 Reg = Candidates.find_next(Reg);
465 assert(ScavengedReg == 0 &&
466 "Scavenger slot is live, unable to scavenge another register!");
468 // Spill the scavenged register before I.
469 TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
470 MachineBasicBlock::iterator II = prior(I);
471 TRI->eliminateFrameIndex(II, SPAdj, this);
473 // Restore the scavenged register before its use (or first terminator).
475 ? MachineBasicBlock::iterator(MaxUseMI) : MBB->getFirstTerminator();
476 TII->loadRegFromStackSlot(*MBB, II, SReg, ScavengingFrameIndex, RC);
477 ScavengeRestore = prior(II);