1 //===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the machine register scavenger. It can provide
11 // information, such as unused registers, at any point in a machine basic block.
12 // It also provides a mechanism to make registers available by evicting them to
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "reg-scavenging"
18 #include "llvm/CodeGen/RegisterScavenging.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/ADT/SmallPtrSet.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/ADT/STLExtras.h"
32 /// RedefinesSuperRegPart - Return true if the specified register is redefining
33 /// part of a super-register.
34 static bool RedefinesSuperRegPart(const MachineInstr *MI, unsigned SubReg,
35 const TargetRegisterInfo *TRI) {
36 bool SeenSuperUse = false;
37 bool SeenSuperDef = false;
38 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
39 const MachineOperand &MO = MI->getOperand(i);
40 if (!MO.isReg() || MO.isUndef())
42 if (TRI->isSuperRegister(SubReg, MO.getReg())) {
45 else if (MO.isImplicit())
50 return SeenSuperDef && SeenSuperUse;
53 static bool RedefinesSuperRegPart(const MachineInstr *MI,
54 const MachineOperand &MO,
55 const TargetRegisterInfo *TRI) {
56 assert(MO.isReg() && MO.isDef() && "Not a register def!");
57 return RedefinesSuperRegPart(MI, MO.getReg(), TRI);
60 bool RegScavenger::isSuperRegUsed(unsigned Reg) const {
61 for (const unsigned *SuperRegs = TRI->getSuperRegisters(Reg);
62 unsigned SuperReg = *SuperRegs; ++SuperRegs)
68 /// setUsed - Set the register and its sub-registers as being used.
69 void RegScavenger::setUsed(unsigned Reg) {
70 RegsAvailable.reset(Reg);
72 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
73 unsigned SubReg = *SubRegs; ++SubRegs)
74 RegsAvailable.reset(SubReg);
77 /// setUnused - Set the register and its sub-registers as being unused.
78 void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) {
79 RegsAvailable.set(Reg);
81 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
82 unsigned SubReg = *SubRegs; ++SubRegs)
83 if (!RedefinesSuperRegPart(MI, Reg, TRI))
84 RegsAvailable.set(SubReg);
87 void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
88 MachineFunction &MF = *mbb->getParent();
89 const TargetMachine &TM = MF.getTarget();
90 TII = TM.getInstrInfo();
91 TRI = TM.getRegisterInfo();
92 MRI = &MF.getRegInfo();
94 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
98 NumPhysRegs = TRI->getNumRegs();
99 RegsAvailable.resize(NumPhysRegs);
101 // Create reserved registers bitvector.
102 ReservedRegs = TRI->getReservedRegs(MF);
104 // Create callee-saved registers bitvector.
105 CalleeSavedRegs.resize(NumPhysRegs);
106 const unsigned *CSRegs = TRI->getCalleeSavedRegs();
108 for (unsigned i = 0; CSRegs[i]; ++i)
109 CalleeSavedRegs.set(CSRegs[i]);
115 ScavengeRestore = NULL;
119 // All registers started out unused.
122 // Reserved registers are always used.
123 RegsAvailable ^= ReservedRegs;
125 // Live-in registers are in use.
126 if (!MBB->livein_empty())
127 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
128 E = MBB->livein_end(); I != E; ++I)
134 void RegScavenger::restoreScavengedReg() {
135 TII->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
136 ScavengingFrameIndex, ScavengedRC);
137 MachineBasicBlock::iterator II = prior(MBBI);
138 TRI->eliminateFrameIndex(II, 0, this);
139 setUsed(ScavengedReg);
145 /// isLiveInButUnusedBefore - Return true if register is livein the MBB not
146 /// not used before it reaches the MI that defines register.
147 static bool isLiveInButUnusedBefore(unsigned Reg, MachineInstr *MI,
148 MachineBasicBlock *MBB,
149 const TargetRegisterInfo *TRI,
150 MachineRegisterInfo* MRI) {
151 // First check if register is livein.
152 bool isLiveIn = false;
153 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
154 E = MBB->livein_end(); I != E; ++I)
155 if (Reg == *I || TRI->isSuperRegister(Reg, *I)) {
162 // Is there any use of it before the specified MI?
163 SmallPtrSet<MachineInstr*, 4> UsesInMBB;
164 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
165 UE = MRI->use_end(); UI != UE; ++UI) {
166 MachineOperand &UseMO = UI.getOperand();
167 if (UseMO.isReg() && UseMO.isUndef())
169 MachineInstr *UseMI = &*UI;
170 if (UseMI->getParent() == MBB)
171 UsesInMBB.insert(UseMI);
173 if (UsesInMBB.empty())
176 for (MachineBasicBlock::iterator I = MBB->begin(), E = MI; I != E; ++I)
177 if (UsesInMBB.count(&*I))
183 void RegScavenger::forward() {
189 assert(MBBI != MBB->end() && "Already at the end of the basic block!");
193 MachineInstr *MI = MBBI;
194 DistanceMap.insert(std::make_pair(MI, CurrDist++));
196 if (MI == ScavengeRestore) {
199 ScavengeRestore = NULL;
203 if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
207 // Separate register operands into 3 classes: uses, defs, earlyclobbers.
208 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs;
209 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> DefMOs;
210 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> EarlyClobberMOs;
211 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
212 const MachineOperand &MO = MI->getOperand(i);
213 if (!MO.isReg() || MO.getReg() == 0 || MO.isUndef())
216 UseMOs.push_back(std::make_pair(&MO,i));
217 else if (MO.isEarlyClobber())
218 EarlyClobberMOs.push_back(std::make_pair(&MO,i));
220 DefMOs.push_back(std::make_pair(&MO,i));
223 // Process uses first.
224 BitVector KillRegs(NumPhysRegs);
225 for (unsigned i = 0, e = UseMOs.size(); i != e; ++i) {
226 const MachineOperand MO = *UseMOs[i].first;
227 unsigned Idx = UseMOs[i].second;
228 unsigned Reg = MO.getReg();
230 assert(isUsed(Reg) && "Using an undefined register!");
232 // Two-address operands implicitly kill.
233 if ((MO.isKill() || MI->isRegTiedToDefOperand(Idx)) && !isReserved(Reg)) {
236 // Mark sub-registers as used.
237 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
238 unsigned SubReg = *SubRegs; ++SubRegs)
239 KillRegs.set(SubReg);
243 // Change states of all registers after all the uses are processed to guard
244 // against multiple uses.
247 // Process early clobber defs then process defs. We can have a early clobber
248 // that is dead, it should not conflict with a def that happens one "slot"
249 // (see InstrSlots in LiveIntervalAnalysis.h) later.
250 unsigned NumECs = EarlyClobberMOs.size();
251 unsigned NumDefs = DefMOs.size();
253 for (unsigned i = 0, e = NumECs + NumDefs; i != e; ++i) {
254 const MachineOperand &MO = (i < NumECs)
255 ? *EarlyClobberMOs[i].first : *DefMOs[i-NumECs].first;
256 unsigned Reg = MO.getReg();
260 // If it's dead upon def, then it is now free.
266 // Skip if this is merely redefining part of a super-register.
267 if (RedefinesSuperRegPart(MI, MO, TRI))
270 assert((isReserved(Reg) || isUnused(Reg) || isSuperRegUsed(Reg) ||
271 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
272 "Re-defining a live register!");
277 void RegScavenger::backward() {
278 assert(Tracking && "Not tracking states!");
279 assert(MBBI != MBB->begin() && "Already at start of basic block!");
280 // Move ptr backward.
283 MachineInstr *MI = MBBI;
284 DistanceMap.erase(MI);
287 // Separate register operands into 3 classes: uses, defs, earlyclobbers.
288 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs;
289 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> DefMOs;
290 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> EarlyClobberMOs;
291 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
292 const MachineOperand &MO = MI->getOperand(i);
293 if (!MO.isReg() || MO.getReg() == 0 || MO.isUndef())
296 UseMOs.push_back(std::make_pair(&MO,i));
297 else if (MO.isEarlyClobber())
298 EarlyClobberMOs.push_back(std::make_pair(&MO,i));
300 DefMOs.push_back(std::make_pair(&MO,i));
304 // Process defs first.
305 unsigned NumECs = EarlyClobberMOs.size();
306 unsigned NumDefs = DefMOs.size();
307 for (unsigned i = 0, e = NumECs + NumDefs; i != e; ++i) {
308 const MachineOperand &MO = (i < NumDefs)
309 ? *DefMOs[i].first : *EarlyClobberMOs[i-NumDefs].first;
310 unsigned Idx = (i < NumECs)
311 ? DefMOs[i].second : EarlyClobberMOs[i-NumDefs].second;
315 // Skip two-address destination operand.
316 if (MI->isRegTiedToUseOperand(Idx))
319 unsigned Reg = MO.getReg();
321 if (!isReserved(Reg))
326 BitVector UseRegs(NumPhysRegs);
327 for (unsigned i = 0, e = UseMOs.size(); i != e; ++i) {
328 const MachineOperand MO = *UseMOs[i].first;
329 unsigned Reg = MO.getReg();
330 assert(isUnused(Reg) || isReserved(Reg));
333 // Set the sub-registers as "used".
334 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
335 unsigned SubReg = *SubRegs; ++SubRegs)
341 void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
343 used = ~RegsAvailable;
345 used = ~RegsAvailable & ~ReservedRegs;
348 /// CreateRegClassMask - Set the bits that represent the registers in the
349 /// TargetRegisterClass.
350 static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {
351 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E;
356 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
357 const BitVector &Candidates) const {
358 // Mask off the registers which are not in the TargetRegisterClass.
359 BitVector RegsAvailableCopy(NumPhysRegs, false);
360 CreateRegClassMask(RegClass, RegsAvailableCopy);
361 RegsAvailableCopy &= RegsAvailable;
363 // Restrict the search to candidates.
364 RegsAvailableCopy &= Candidates;
366 // Returns the first unused (bit is set) register, or 0 is none is found.
367 int Reg = RegsAvailableCopy.find_first();
368 return (Reg == -1) ? 0 : Reg;
371 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
372 bool ExCalleeSaved) const {
373 // Mask off the registers which are not in the TargetRegisterClass.
374 BitVector RegsAvailableCopy(NumPhysRegs, false);
375 CreateRegClassMask(RegClass, RegsAvailableCopy);
376 RegsAvailableCopy &= RegsAvailable;
378 // If looking for a non-callee-saved register, mask off all the callee-saved
381 RegsAvailableCopy &= ~CalleeSavedRegs;
383 // Returns the first unused (bit is set) register, or 0 is none is found.
384 int Reg = RegsAvailableCopy.find_first();
385 return (Reg == -1) ? 0 : Reg;
388 /// findFirstUse - Calculate the distance to the first use of the
389 /// specified register.
391 RegScavenger::findFirstUse(MachineBasicBlock *MBB,
392 MachineBasicBlock::iterator I, unsigned Reg,
394 MachineInstr *UseMI = 0;
396 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(Reg),
397 RE = MRI->reg_end(); RI != RE; ++RI) {
398 MachineInstr *UDMI = &*RI;
399 if (UDMI->getParent() != MBB)
401 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UDMI);
402 if (DI == DistanceMap.end()) {
403 // If it's not in map, it's below current MI, let's initialize the
406 unsigned Dist = CurrDist + 1;
407 while (I != MBB->end()) {
408 DistanceMap.insert(std::make_pair(I, Dist++));
412 DI = DistanceMap.find(UDMI);
413 if (DI->second > CurrDist && DI->second < Dist) {
421 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
422 MachineBasicBlock::iterator I,
424 assert(ScavengingFrameIndex >= 0 &&
425 "Cannot scavenge a register without an emergency spill slot!");
427 // Mask off the registers which are not in the TargetRegisterClass.
428 BitVector Candidates(NumPhysRegs, false);
429 CreateRegClassMask(RC, Candidates);
430 Candidates ^= ReservedRegs & Candidates; // Do not include reserved registers.
432 // Exclude all the registers being used by the instruction.
433 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
434 MachineOperand &MO = I->getOperand(i);
436 Candidates.reset(MO.getReg());
439 // Find the register whose use is furthest away.
441 unsigned MaxDist = 0;
442 MachineInstr *MaxUseMI = 0;
443 int Reg = Candidates.find_first();
446 MachineInstr *UseMI = findFirstUse(MBB, I, Reg, Dist);
447 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
449 MachineInstr *AsUseMI = findFirstUse(MBB, I, *AS, AsDist);
455 if (Dist >= MaxDist) {
460 Reg = Candidates.find_next(Reg);
463 assert(ScavengedReg == 0 &&
464 "Scavenger slot is live, unable to scavenge another register!");
466 // Make sure SReg is marked as used. It could be considered available if it is
467 // one of the callee saved registers, but hasn't been spilled.
469 MBB->addLiveIn(SReg);
473 // Spill the scavenged register before I.
474 TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
475 MachineBasicBlock::iterator II = prior(I);
476 TRI->eliminateFrameIndex(II, SPAdj, this);
478 // Restore the scavenged register before its use (or first terminator).
480 ? MachineBasicBlock::iterator(MaxUseMI) : MBB->getFirstTerminator();
481 TII->loadRegFromStackSlot(*MBB, II, SReg, ScavengingFrameIndex, RC);
482 ScavengeRestore = prior(II);