1 //===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the machine register scavenger. It can provide
11 // information, such as unused registers, at any point in a machine basic block.
12 // It also provides a mechanism to make registers available by evicting them to
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "reg-scavenging"
18 #include "llvm/CodeGen/RegisterScavenging.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineBasicBlock.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/SmallPtrSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/STLExtras.h"
36 /// setUsed - Set the register and its sub-registers as being used.
37 void RegScavenger::setUsed(unsigned Reg) {
38 RegsAvailable.reset(Reg);
40 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
41 unsigned SubReg = *SubRegs; ++SubRegs)
42 RegsAvailable.reset(SubReg);
45 bool RegScavenger::isAliasUsed(unsigned Reg) const {
48 for (const unsigned *R = TRI->getAliasSet(Reg); *R; ++R)
54 void RegScavenger::initRegState() {
57 ScavengeRestore = NULL;
59 // All registers started out unused.
62 // Reserved registers are always used.
63 RegsAvailable ^= ReservedRegs;
68 // Live-in registers are in use.
69 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
70 E = MBB->livein_end(); I != E; ++I)
73 // Pristine CSRs are also unavailable.
74 BitVector PR = MBB->getParent()->getFrameInfo()->getPristineRegs(MBB);
75 for (int I = PR.find_first(); I>0; I = PR.find_next(I))
79 void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
80 MachineFunction &MF = *mbb->getParent();
81 const TargetMachine &TM = MF.getTarget();
82 TII = TM.getInstrInfo();
83 TRI = TM.getRegisterInfo();
84 MRI = &MF.getRegInfo();
86 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
91 NumPhysRegs = TRI->getNumRegs();
92 RegsAvailable.resize(NumPhysRegs);
94 // Create reserved registers bitvector.
95 ReservedRegs = TRI->getReservedRegs(MF);
97 // Create callee-saved registers bitvector.
98 CalleeSavedRegs.resize(NumPhysRegs);
99 const unsigned *CSRegs = TRI->getCalleeSavedRegs();
101 for (unsigned i = 0; CSRegs[i]; ++i)
102 CalleeSavedRegs.set(CSRegs[i]);
111 void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) {
113 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
117 void RegScavenger::addRegWithAliases(BitVector &BV, unsigned Reg) {
119 for (const unsigned *R = TRI->getAliasSet(Reg); *R; R++)
123 void RegScavenger::forward() {
129 assert(MBBI != MBB->end() && "Already at the end of the basic block!");
130 MBBI = llvm::next(MBBI);
133 MachineInstr *MI = MBBI;
135 if (MI == ScavengeRestore) {
138 ScavengeRestore = NULL;
141 if (MI->isDebugValue())
144 // Find out which registers are early clobbered, killed, defined, and marked
145 // def-dead in this instruction.
146 // FIXME: The scavenger is not predication aware. If the instruction is
147 // predicated, conservatively assume "kill" markers do not actually kill the
148 // register. Similarly ignores "dead" markers.
149 bool isPred = TII->isPredicated(MI);
150 BitVector EarlyClobberRegs(NumPhysRegs);
151 BitVector KillRegs(NumPhysRegs);
152 BitVector DefRegs(NumPhysRegs);
153 BitVector DeadRegs(NumPhysRegs);
154 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
155 const MachineOperand &MO = MI->getOperand(i);
156 if (!MO.isReg() || MO.isUndef())
158 unsigned Reg = MO.getReg();
159 if (!Reg || isReserved(Reg))
163 // Two-address operands implicitly kill.
164 if (!isPred && (MO.isKill() || MI->isRegTiedToDefOperand(i)))
165 addRegWithSubRegs(KillRegs, Reg);
168 if (!isPred && MO.isDead())
169 addRegWithSubRegs(DeadRegs, Reg);
171 addRegWithSubRegs(DefRegs, Reg);
172 if (MO.isEarlyClobber())
173 addRegWithAliases(EarlyClobberRegs, Reg);
177 // Verify uses and defs.
178 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
179 const MachineOperand &MO = MI->getOperand(i);
180 if (!MO.isReg() || MO.isUndef())
182 unsigned Reg = MO.getReg();
183 if (!Reg || isReserved(Reg))
187 // Check if it's partial live: e.g.
188 // D0 = insert_subreg D0<undef>, S0
190 // The problem is the insert_subreg could be eliminated. The use of
191 // D0 is using a partially undef value. This is not *incorrect* since
192 // S1 is can be freely clobbered.
193 // Ideally we would like a way to model this, but leaving the
194 // insert_subreg around causes both correctness and performance issues.
195 bool SubUsed = false;
196 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
197 unsigned SubReg = *SubRegs; ++SubRegs)
198 if (isUsed(SubReg)) {
202 assert(SubUsed && "Using an undefined register!");
204 assert((!EarlyClobberRegs.test(Reg) || MI->isRegTiedToDefOperand(i)) &&
205 "Using an early clobbered register!");
209 // FIXME: Enable this once we've figured out how to correctly transfer
210 // implicit kills during codegen passes like the coalescer.
211 assert((KillRegs.test(Reg) || isUnused(Reg) ||
212 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
213 "Re-defining a live register!");
218 // Commit the changes.
224 void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
226 used = ~RegsAvailable;
228 used = ~RegsAvailable & ~ReservedRegs;
231 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
232 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
234 if (!isAliasUsed(*I)) {
235 DEBUG(dbgs() << "Scavenger found unused reg: " << TRI->getName(*I) <<
242 /// getRegsAvailable - Return all available registers in the register class
244 BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) {
245 BitVector Mask(TRI->getNumRegs());
246 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
248 if (!isAliasUsed(*I))
253 /// findSurvivorReg - Return the candidate register that is unused for the
254 /// longest after StargMII. UseMI is set to the instruction where the search
257 /// No more than InstrLimit instructions are inspected.
259 unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI,
260 BitVector &Candidates,
262 MachineBasicBlock::iterator &UseMI) {
263 int Survivor = Candidates.find_first();
264 assert(Survivor > 0 && "No candidates for scavenging");
266 MachineBasicBlock::iterator ME = MBB->getFirstTerminator();
267 assert(StartMI != ME && "MI already at terminator");
268 MachineBasicBlock::iterator RestorePointMI = StartMI;
269 MachineBasicBlock::iterator MI = StartMI;
271 bool inVirtLiveRange = false;
272 for (++MI; InstrLimit > 0 && MI != ME; ++MI, --InstrLimit) {
273 if (MI->isDebugValue()) {
274 ++InstrLimit; // Don't count debug instructions
277 bool isVirtKillInsn = false;
278 bool isVirtDefInsn = false;
279 // Remove any candidates touched by instruction.
280 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
281 const MachineOperand &MO = MI->getOperand(i);
282 if (!MO.isReg() || MO.isUndef() || !MO.getReg())
284 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
286 isVirtDefInsn = true;
287 else if (MO.isKill())
288 isVirtKillInsn = true;
291 Candidates.reset(MO.getReg());
292 for (const unsigned *R = TRI->getAliasSet(MO.getReg()); *R; R++)
293 Candidates.reset(*R);
295 // If we're not in a virtual reg's live range, this is a valid
297 if (!inVirtLiveRange) RestorePointMI = MI;
299 // Update whether we're in the live range of a virtual register
300 if (isVirtKillInsn) inVirtLiveRange = false;
301 if (isVirtDefInsn) inVirtLiveRange = true;
303 // Was our survivor untouched by this instruction?
304 if (Candidates.test(Survivor))
307 // All candidates gone?
308 if (Candidates.none())
311 Survivor = Candidates.find_first();
313 // If we ran off the end, that's where we want to restore.
314 if (MI == ME) RestorePointMI = ME;
315 assert (RestorePointMI != StartMI &&
316 "No available scavenger restore location!");
318 // We ran out of candidates, so stop the search.
319 UseMI = RestorePointMI;
323 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
324 MachineBasicBlock::iterator I,
326 // Consider all allocatable registers in the register class initially
327 BitVector Candidates =
328 TRI->getAllocatableSet(*I->getParent()->getParent(), RC);
330 // Exclude all the registers being used by the instruction.
331 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
332 MachineOperand &MO = I->getOperand(i);
333 if (MO.isReg() && MO.getReg() != 0 &&
334 !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
335 Candidates.reset(MO.getReg());
338 // Try to find a register that's unused if there is one, as then we won't
339 // have to spill. Search explicitly rather than masking out based on
340 // RegsAvailable, as RegsAvailable does not take aliases into account.
341 // That's what getRegsAvailable() is for.
342 BitVector Available = getRegsAvailable(RC);
344 if ((Candidates & Available).any())
345 Candidates &= Available;
347 // Find the register whose use is furthest away.
348 MachineBasicBlock::iterator UseMI;
349 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
351 // If we found an unused register there is no reason to spill it.
352 if (!isAliasUsed(SReg)) {
353 DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n");
357 assert(ScavengedReg == 0 &&
358 "Scavenger slot is live, unable to scavenge another register!");
360 // Avoid infinite regress
363 // If the target knows how to save/restore the register, let it do so;
364 // otherwise, use the emergency stack spill slot.
365 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {
366 // Spill the scavenged register before I.
367 assert(ScavengingFrameIndex >= 0 &&
368 "Cannot scavenge register without an emergency spill slot!");
369 TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC,TRI);
370 MachineBasicBlock::iterator II = prior(I);
371 TRI->eliminateFrameIndex(II, SPAdj, this);
373 // Restore the scavenged register before its use (or first terminator).
374 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC, TRI);
376 TRI->eliminateFrameIndex(II, SPAdj, this);
379 ScavengeRestore = prior(UseMI);
381 // Doing this here leads to infinite regress.
382 // ScavengedReg = SReg;
385 DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) <<