1 //===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the machine register scavenger. It can provide
11 // information, such as unused registers, at any point in a machine basic block.
12 // It also provides a mechanism to make registers available by evicting them to
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "reg-scavenging"
18 #include "llvm/CodeGen/RegisterScavenging.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineBasicBlock.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Target/TargetRegisterInfo.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/ADT/SmallPtrSet.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/STLExtras.h"
33 /// RedefinesSuperRegPart - Return true if the specified register is redefining
34 /// part of a super-register.
35 static bool RedefinesSuperRegPart(const MachineInstr *MI, unsigned SubReg,
36 const TargetRegisterInfo *TRI) {
37 bool SeenSuperUse = false;
38 bool SeenSuperDef = false;
39 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
40 const MachineOperand &MO = MI->getOperand(i);
41 if (!MO.isReg() || MO.isUndef())
43 if (TRI->isSuperRegister(SubReg, MO.getReg())) {
46 else if (MO.isImplicit())
51 return SeenSuperDef && SeenSuperUse;
54 bool RegScavenger::isSuperRegUsed(unsigned Reg) const {
55 for (const unsigned *SuperRegs = TRI->getSuperRegisters(Reg);
56 unsigned SuperReg = *SuperRegs; ++SuperRegs)
62 /// setUsed - Set the register and its sub-registers as being used.
63 void RegScavenger::setUsed(unsigned Reg) {
64 RegsAvailable.reset(Reg);
66 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
67 unsigned SubReg = *SubRegs; ++SubRegs)
68 RegsAvailable.reset(SubReg);
71 /// setUnused - Set the register and its sub-registers as being unused.
72 void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) {
73 RegsAvailable.set(Reg);
75 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
76 unsigned SubReg = *SubRegs; ++SubRegs)
77 if (!RedefinesSuperRegPart(MI, Reg, TRI))
78 RegsAvailable.set(SubReg);
81 void RegScavenger::initRegState() {
84 ScavengeRestore = NULL;
88 // All registers started out unused.
91 // Reserved registers are always used.
92 RegsAvailable ^= ReservedRegs;
94 // Live-in registers are in use.
95 if (!MBB || MBB->livein_empty())
97 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
98 E = MBB->livein_end(); I != E; ++I)
102 void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
103 MachineFunction &MF = *mbb->getParent();
104 const TargetMachine &TM = MF.getTarget();
105 TII = TM.getInstrInfo();
106 TRI = TM.getRegisterInfo();
107 MRI = &MF.getRegInfo();
109 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
114 NumPhysRegs = TRI->getNumRegs();
115 RegsAvailable.resize(NumPhysRegs);
117 // Create reserved registers bitvector.
118 ReservedRegs = TRI->getReservedRegs(MF);
120 // Create callee-saved registers bitvector.
121 CalleeSavedRegs.resize(NumPhysRegs);
122 const unsigned *CSRegs = TRI->getCalleeSavedRegs();
124 for (unsigned i = 0; CSRegs[i]; ++i)
125 CalleeSavedRegs.set(CSRegs[i]);
128 // RS used within emit{Pro,Epi}logue()
137 void RegScavenger::restoreScavengedReg() {
138 TII->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
139 ScavengingFrameIndex, ScavengedRC);
140 MachineBasicBlock::iterator II = prior(MBBI);
141 TRI->eliminateFrameIndex(II, 0, this);
142 setUsed(ScavengedReg);
148 /// isLiveInButUnusedBefore - Return true if register is livein the MBB not
149 /// not used before it reaches the MI that defines register.
150 static bool isLiveInButUnusedBefore(unsigned Reg, MachineInstr *MI,
151 MachineBasicBlock *MBB,
152 const TargetRegisterInfo *TRI,
153 MachineRegisterInfo* MRI) {
154 // First check if register is livein.
155 bool isLiveIn = false;
156 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
157 E = MBB->livein_end(); I != E; ++I)
158 if (Reg == *I || TRI->isSuperRegister(Reg, *I)) {
165 // Is there any use of it before the specified MI?
166 SmallPtrSet<MachineInstr*, 4> UsesInMBB;
167 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
168 UE = MRI->use_end(); UI != UE; ++UI) {
169 MachineOperand &UseMO = UI.getOperand();
170 if (UseMO.isReg() && UseMO.isUndef())
172 MachineInstr *UseMI = &*UI;
173 if (UseMI->getParent() == MBB)
174 UsesInMBB.insert(UseMI);
176 if (UsesInMBB.empty())
179 for (MachineBasicBlock::iterator I = MBB->begin(), E = MI; I != E; ++I)
180 if (UsesInMBB.count(&*I))
186 void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) {
188 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
192 void RegScavenger::addRegWithAliases(BitVector &BV, unsigned Reg) {
194 for (const unsigned *R = TRI->getAliasSet(Reg); *R; R++)
198 void RegScavenger::forward() {
204 assert(MBBI != MBB->end() && "Already at the end of the basic block!");
208 MachineInstr *MI = MBBI;
209 DistanceMap.insert(std::make_pair(MI, CurrDist++));
211 if (MI == ScavengeRestore) {
214 ScavengeRestore = NULL;
217 // Find out which registers are early clobbered, killed, defined, and marked
218 // def-dead in this instruction.
219 BitVector EarlyClobberRegs(NumPhysRegs);
220 BitVector KillRegs(NumPhysRegs);
221 BitVector DefRegs(NumPhysRegs);
222 BitVector DeadRegs(NumPhysRegs);
223 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
224 const MachineOperand &MO = MI->getOperand(i);
225 if (!MO.isReg() || MO.isUndef())
227 unsigned Reg = MO.getReg();
228 if (!Reg || isReserved(Reg))
232 // Two-address operands implicitly kill.
233 if (MO.isKill() || MI->isRegTiedToDefOperand(i))
234 addRegWithSubRegs(KillRegs, Reg);
238 addRegWithSubRegs(DeadRegs, Reg);
240 addRegWithSubRegs(DefRegs, Reg);
241 if (MO.isEarlyClobber())
242 addRegWithAliases(EarlyClobberRegs, Reg);
246 // Verify uses and defs.
247 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
248 const MachineOperand &MO = MI->getOperand(i);
249 if (!MO.isReg() || MO.isUndef())
251 unsigned Reg = MO.getReg();
252 if (!Reg || isReserved(Reg))
255 assert(isUsed(Reg) && "Using an undefined register!");
256 assert(!EarlyClobberRegs.test(Reg) &&
257 "Using an early clobbered register!");
260 assert((KillRegs.test(Reg) || isUnused(Reg) || isSuperRegUsed(Reg) ||
261 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
262 "Re-defining a live register!");
266 // Commit the changes.
272 void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
274 used = ~RegsAvailable;
276 used = ~RegsAvailable & ~ReservedRegs;
279 /// CreateRegClassMask - Set the bits that represent the registers in the
280 /// TargetRegisterClass.
281 static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {
282 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E;
287 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
288 const BitVector &Candidates) const {
289 // Mask off the registers which are not in the TargetRegisterClass.
290 BitVector RegsAvailableCopy(NumPhysRegs, false);
291 CreateRegClassMask(RegClass, RegsAvailableCopy);
292 RegsAvailableCopy &= RegsAvailable;
294 // Restrict the search to candidates.
295 RegsAvailableCopy &= Candidates;
297 // Returns the first unused (bit is set) register, or 0 is none is found.
298 int Reg = RegsAvailableCopy.find_first();
299 return (Reg == -1) ? 0 : Reg;
302 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
303 bool ExCalleeSaved) const {
304 // Mask off the registers which are not in the TargetRegisterClass.
305 BitVector RegsAvailableCopy(NumPhysRegs, false);
306 CreateRegClassMask(RegClass, RegsAvailableCopy);
307 RegsAvailableCopy &= RegsAvailable;
309 // If looking for a non-callee-saved register, mask off all the callee-saved
312 RegsAvailableCopy &= ~CalleeSavedRegs;
314 // Returns the first unused (bit is set) register, or 0 is none is found.
315 int Reg = RegsAvailableCopy.find_first();
316 return (Reg == -1) ? 0 : Reg;
319 /// findFirstUse - Calculate the distance to the first use of the
320 /// specified register.
322 RegScavenger::findFirstUse(MachineBasicBlock *MBB,
323 MachineBasicBlock::iterator I, unsigned Reg,
325 MachineInstr *UseMI = 0;
327 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(Reg),
328 RE = MRI->reg_end(); RI != RE; ++RI) {
329 MachineInstr *UDMI = &*RI;
330 if (UDMI->getParent() != MBB)
332 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UDMI);
333 if (DI == DistanceMap.end()) {
334 // If it's not in map, it's below current MI, let's initialize the
337 unsigned Dist = CurrDist + 1;
338 while (I != MBB->end()) {
339 DistanceMap.insert(std::make_pair(I, Dist++));
343 DI = DistanceMap.find(UDMI);
344 if (DI->second > CurrDist && DI->second < Dist) {
352 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
353 MachineBasicBlock::iterator I,
355 assert(ScavengingFrameIndex >= 0 &&
356 "Cannot scavenge a register without an emergency spill slot!");
358 // Mask off the registers which are not in the TargetRegisterClass.
359 BitVector Candidates(NumPhysRegs, false);
360 CreateRegClassMask(RC, Candidates);
361 // Do not include reserved registers.
362 Candidates ^= ReservedRegs & Candidates;
364 // Exclude all the registers being used by the instruction.
365 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
366 MachineOperand &MO = I->getOperand(i);
368 Candidates.reset(MO.getReg());
371 // Find the register whose use is furthest away.
373 unsigned MaxDist = 0;
374 MachineInstr *MaxUseMI = 0;
375 int Reg = Candidates.find_first();
378 MachineInstr *UseMI = findFirstUse(MBB, I, Reg, Dist);
379 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
381 MachineInstr *AsUseMI = findFirstUse(MBB, I, *AS, AsDist);
387 if (Dist >= MaxDist) {
392 Reg = Candidates.find_next(Reg);
395 assert(ScavengedReg == 0 &&
396 "Scavenger slot is live, unable to scavenge another register!");
398 // Avoid infinite regress
401 // Make sure SReg is marked as used. It could be considered available
402 // if it is one of the callee saved registers, but hasn't been spilled.
404 MBB->addLiveIn(SReg);
408 // Spill the scavenged register before I.
409 TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
410 MachineBasicBlock::iterator II = prior(I);
411 TRI->eliminateFrameIndex(II, SPAdj, this);
413 // Restore the scavenged register before its use (or first terminator).
415 ? MachineBasicBlock::iterator(MaxUseMI) : MBB->getFirstTerminator();
416 TII->loadRegFromStackSlot(*MBB, II, SReg, ScavengingFrameIndex, RC);
417 ScavengeRestore = prior(II);
418 // Doing this here leads to infinite regress.
419 // ScavengedReg = SReg;