1 //===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the machine register scavenger. It can provide
11 // information, such as unused registers, at any point in a machine basic block.
12 // It also provides a mechanism to make registers available by evicting them to
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "reg-scavenging"
18 #include "llvm/CodeGen/RegisterScavenging.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/ADT/SmallPtrSet.h"
27 #include "llvm/ADT/STLExtras.h"
30 /// RedefinesSuperRegPart - Return true if the specified register is redefining
31 /// part of a super-register.
32 static bool RedefinesSuperRegPart(const MachineInstr *MI, unsigned SubReg,
33 const TargetRegisterInfo *TRI) {
34 bool SeenSuperUse = false;
35 bool SeenSuperDef = false;
36 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
37 const MachineOperand &MO = MI->getOperand(i);
40 if (TRI->isSuperRegister(SubReg, MO.getReg())) {
43 else if (MO.isImplicit())
48 return SeenSuperDef && SeenSuperUse;
51 static bool RedefinesSuperRegPart(const MachineInstr *MI,
52 const MachineOperand &MO,
53 const TargetRegisterInfo *TRI) {
54 assert(MO.isReg() && MO.isDef() && "Not a register def!");
55 return RedefinesSuperRegPart(MI, MO.getReg(), TRI);
58 /// setUsed - Set the register and its sub-registers as being used.
59 void RegScavenger::setUsed(unsigned Reg, bool ImpDef) {
60 RegsAvailable.reset(Reg);
61 ImplicitDefed[Reg] = ImpDef;
63 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
64 unsigned SubReg = *SubRegs; ++SubRegs) {
65 RegsAvailable.reset(SubReg);
66 ImplicitDefed[SubReg] = ImpDef;
70 /// setUnused - Set the register and its sub-registers as being unused.
71 void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) {
72 RegsAvailable.set(Reg);
73 ImplicitDefed.reset(Reg);
75 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
76 unsigned SubReg = *SubRegs; ++SubRegs)
77 if (!RedefinesSuperRegPart(MI, Reg, TRI)) {
78 RegsAvailable.set(SubReg);
79 ImplicitDefed.reset(SubReg);
83 void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
84 MachineFunction &MF = *mbb->getParent();
85 const TargetMachine &TM = MF.getTarget();
86 TII = TM.getInstrInfo();
87 TRI = TM.getRegisterInfo();
88 MRI = &MF.getRegInfo();
90 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
94 NumPhysRegs = TRI->getNumRegs();
95 RegsAvailable.resize(NumPhysRegs);
96 ImplicitDefed.resize(NumPhysRegs);
98 // Create reserved registers bitvector.
99 ReservedRegs = TRI->getReservedRegs(MF);
101 // Create callee-saved registers bitvector.
102 CalleeSavedRegs.resize(NumPhysRegs);
103 const unsigned *CSRegs = TRI->getCalleeSavedRegs();
105 for (unsigned i = 0; CSRegs[i]; ++i)
106 CalleeSavedRegs.set(CSRegs[i]);
112 ScavengeRestore = NULL;
115 ImplicitDefed.reset();
117 // All registers started out unused.
120 // Reserved registers are always used.
121 RegsAvailable ^= ReservedRegs;
123 // Live-in registers are in use.
124 if (!MBB->livein_empty())
125 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
126 E = MBB->livein_end(); I != E; ++I)
132 void RegScavenger::restoreScavengedReg() {
133 TII->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
134 ScavengingFrameIndex, ScavengedRC);
135 MachineBasicBlock::iterator II = prior(MBBI);
136 TRI->eliminateFrameIndex(II, 0, this);
137 setUsed(ScavengedReg);
143 /// isLiveInButUnusedBefore - Return true if register is livein the MBB not
144 /// not used before it reaches the MI that defines register.
145 static bool isLiveInButUnusedBefore(unsigned Reg, MachineInstr *MI,
146 MachineBasicBlock *MBB,
147 const TargetRegisterInfo *TRI,
148 MachineRegisterInfo* MRI) {
149 // First check if register is livein.
150 bool isLiveIn = false;
151 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
152 E = MBB->livein_end(); I != E; ++I)
153 if (Reg == *I || TRI->isSuperRegister(Reg, *I)) {
160 // Is there any use of it before the specified MI?
161 SmallPtrSet<MachineInstr*, 4> UsesInMBB;
162 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
163 UE = MRI->use_end(); UI != UE; ++UI) {
164 MachineInstr *UseMI = &*UI;
165 if (UseMI->getParent() == MBB)
166 UsesInMBB.insert(UseMI);
168 if (UsesInMBB.empty())
171 for (MachineBasicBlock::iterator I = MBB->begin(), E = MI; I != E; ++I)
172 if (UsesInMBB.count(&*I))
178 void RegScavenger::forward() {
184 assert(MBBI != MBB->end() && "Already at the end of the basic block!");
188 MachineInstr *MI = MBBI;
189 DistanceMap.insert(std::make_pair(MI, CurrDist++));
190 const TargetInstrDesc &TID = MI->getDesc();
192 if (MI == ScavengeRestore) {
195 ScavengeRestore = NULL;
198 bool IsImpDef = MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF;
200 // Separate register operands into 3 classes: uses, defs, earlyclobbers.
201 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs;
202 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> DefMOs;
203 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> EarlyClobberMOs;
204 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
205 const MachineOperand &MO = MI->getOperand(i);
206 if (!MO.isReg() || MO.getReg() == 0)
209 UseMOs.push_back(std::make_pair(&MO,i));
210 else if (MO.isEarlyClobber())
211 EarlyClobberMOs.push_back(std::make_pair(&MO,i));
213 DefMOs.push_back(std::make_pair(&MO,i));
216 // Process uses first.
217 BitVector UseRegs(NumPhysRegs);
218 for (unsigned i = 0, e = UseMOs.size(); i != e; ++i) {
219 const MachineOperand MO = *UseMOs[i].first;
220 unsigned Reg = MO.getReg();
222 assert(isUsed(Reg) && "Using an undefined register!");
224 if (MO.isKill() && !isReserved(Reg)) {
227 // Mark sub-registers as used.
228 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
229 unsigned SubReg = *SubRegs; ++SubRegs)
234 // Change states of all registers after all the uses are processed to guard
235 // against multiple uses.
238 // Process early clobber defs then process defs. We can have a early clobber
239 // that is dead, it should not conflict with a def that happens one "slot"
240 // (see InstrSlots in LiveIntervalAnalysis.h) later.
241 unsigned NumECs = EarlyClobberMOs.size();
242 unsigned NumDefs = DefMOs.size();
244 for (unsigned i = 0, e = NumECs + NumDefs; i != e; ++i) {
245 const MachineOperand &MO = (i < NumECs)
246 ? *EarlyClobberMOs[i].first : *DefMOs[i-NumECs].first;
247 unsigned Idx = (i < NumECs)
248 ? EarlyClobberMOs[i].second : DefMOs[i-NumECs].second;
249 unsigned Reg = MO.getReg();
251 // If it's dead upon def, then it is now free.
257 // Skip two-address destination operand.
258 if (TID.findTiedToSrcOperand(Idx) != -1) {
259 assert(isUsed(Reg) && "Using an undefined register!");
263 // Skip if this is merely redefining part of a super-register.
264 if (RedefinesSuperRegPart(MI, MO, TRI))
267 // Implicit def is allowed to "re-define" any register. Similarly,
268 // implicitly defined registers can be clobbered.
269 assert((isReserved(Reg) || isUnused(Reg) ||
270 IsImpDef || isImplicitlyDefined(Reg) ||
271 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
272 "Re-defining a live register!");
273 setUsed(Reg, IsImpDef);
277 void RegScavenger::backward() {
278 assert(Tracking && "Not tracking states!");
279 assert(MBBI != MBB->begin() && "Already at start of basic block!");
280 // Move ptr backward.
283 MachineInstr *MI = MBBI;
284 DistanceMap.erase(MI);
286 const TargetInstrDesc &TID = MI->getDesc();
288 // Separate register operands into 3 classes: uses, defs, earlyclobbers.
289 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs;
290 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> DefMOs;
291 SmallVector<std::pair<const MachineOperand*,unsigned>, 4> EarlyClobberMOs;
292 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
293 const MachineOperand &MO = MI->getOperand(i);
294 if (!MO.isReg() || MO.getReg() == 0)
297 UseMOs.push_back(std::make_pair(&MO,i));
298 else if (MO.isEarlyClobber())
299 EarlyClobberMOs.push_back(std::make_pair(&MO,i));
301 DefMOs.push_back(std::make_pair(&MO,i));
305 // Process defs first.
306 unsigned NumECs = EarlyClobberMOs.size();
307 unsigned NumDefs = DefMOs.size();
308 for (unsigned i = 0, e = NumECs + NumDefs; i != e; ++i) {
309 const MachineOperand &MO = (i < NumDefs)
310 ? *DefMOs[i].first : *EarlyClobberMOs[i-NumDefs].first;
311 unsigned Idx = (i < NumECs)
312 ? DefMOs[i].second : EarlyClobberMOs[i-NumDefs].second;
314 // Skip two-address destination operand.
315 if (TID.findTiedToSrcOperand(Idx) != -1)
318 unsigned Reg = MO.getReg();
320 if (!isReserved(Reg))
325 BitVector UseRegs(NumPhysRegs);
326 for (unsigned i = 0, e = UseMOs.size(); i != e; ++i) {
327 const MachineOperand MO = *UseMOs[i].first;
328 unsigned Reg = MO.getReg();
329 assert(isUnused(Reg) || isReserved(Reg));
332 // Set the sub-registers as "used".
333 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
334 unsigned SubReg = *SubRegs; ++SubRegs)
340 void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
342 used = ~RegsAvailable;
344 used = ~RegsAvailable & ~ReservedRegs;
347 /// CreateRegClassMask - Set the bits that represent the registers in the
348 /// TargetRegisterClass.
349 static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {
350 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E;
355 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
356 const BitVector &Candidates) const {
357 // Mask off the registers which are not in the TargetRegisterClass.
358 BitVector RegsAvailableCopy(NumPhysRegs, false);
359 CreateRegClassMask(RegClass, RegsAvailableCopy);
360 RegsAvailableCopy &= RegsAvailable;
362 // Restrict the search to candidates.
363 RegsAvailableCopy &= Candidates;
365 // Returns the first unused (bit is set) register, or 0 is none is found.
366 int Reg = RegsAvailableCopy.find_first();
367 return (Reg == -1) ? 0 : Reg;
370 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
371 bool ExCalleeSaved) const {
372 // Mask off the registers which are not in the TargetRegisterClass.
373 BitVector RegsAvailableCopy(NumPhysRegs, false);
374 CreateRegClassMask(RegClass, RegsAvailableCopy);
375 RegsAvailableCopy &= RegsAvailable;
377 // If looking for a non-callee-saved register, mask off all the callee-saved
380 RegsAvailableCopy &= ~CalleeSavedRegs;
382 // Returns the first unused (bit is set) register, or 0 is none is found.
383 int Reg = RegsAvailableCopy.find_first();
384 return (Reg == -1) ? 0 : Reg;
387 /// findFirstUse - Calculate the distance to the first use of the
388 /// specified register.
390 RegScavenger::findFirstUse(MachineBasicBlock *MBB,
391 MachineBasicBlock::iterator I, unsigned Reg,
393 MachineInstr *UseMI = 0;
395 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(Reg),
396 RE = MRI->reg_end(); RI != RE; ++RI) {
397 MachineInstr *UDMI = &*RI;
398 if (UDMI->getParent() != MBB)
400 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UDMI);
401 if (DI == DistanceMap.end()) {
402 // If it's not in map, it's below current MI, let's initialize the
405 unsigned Dist = CurrDist + 1;
406 while (I != MBB->end()) {
407 DistanceMap.insert(std::make_pair(I, Dist++));
411 DI = DistanceMap.find(UDMI);
412 if (DI->second > CurrDist && DI->second < Dist) {
420 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
421 MachineBasicBlock::iterator I,
423 assert(ScavengingFrameIndex >= 0 &&
424 "Cannot scavenge a register without an emergency spill slot!");
426 // Mask off the registers which are not in the TargetRegisterClass.
427 BitVector Candidates(NumPhysRegs, false);
428 CreateRegClassMask(RC, Candidates);
429 Candidates ^= ReservedRegs; // Do not include reserved registers.
431 // Exclude all the registers being used by the instruction.
432 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
433 MachineOperand &MO = I->getOperand(i);
435 Candidates.reset(MO.getReg());
438 // Find the register whose use is furthest away.
440 unsigned MaxDist = 0;
441 MachineInstr *MaxUseMI = 0;
442 int Reg = Candidates.find_first();
445 MachineInstr *UseMI = findFirstUse(MBB, I, Reg, Dist);
446 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
448 MachineInstr *AsUseMI = findFirstUse(MBB, I, *AS, AsDist);
454 if (Dist >= MaxDist) {
459 Reg = Candidates.find_next(Reg);
462 if (ScavengedReg != 0) {
463 assert(0 && "Scavenger slot is live, unable to scavenge another register!");
467 // Spill the scavenged register before I.
468 TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
469 MachineBasicBlock::iterator II = prior(I);
470 TRI->eliminateFrameIndex(II, SPAdj, this);
472 // Restore the scavenged register before its use (or first terminator).
474 ? MachineBasicBlock::iterator(MaxUseMI) : MBB->getFirstTerminator();
475 TII->loadRegFromStackSlot(*MBB, II, SReg, ScavengingFrameIndex, RC);
476 ScavengeRestore = prior(II);