1 //===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the machine register scavenger. It can provide
11 // information, such as unused registers, at any point in a machine basic block.
12 // It also provides a mechanism to make registers available by evicting them to
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "reg-scavenging"
18 #include "llvm/CodeGen/RegisterScavenging.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/ADT/SmallPtrSet.h"
27 #include "llvm/ADT/STLExtras.h"
30 /// RedefinesSuperRegPart - Return true if the specified register is redefining
31 /// part of a super-register.
32 static bool RedefinesSuperRegPart(const MachineInstr *MI, unsigned SubReg,
33 const TargetRegisterInfo *TRI) {
34 bool SeenSuperUse = false;
35 bool SeenSuperDef = false;
36 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
37 const MachineOperand &MO = MI->getOperand(i);
40 if (TRI->isSuperRegister(SubReg, MO.getReg())) {
43 else if (MO.isImplicit())
48 return SeenSuperDef && SeenSuperUse;
51 static bool RedefinesSuperRegPart(const MachineInstr *MI,
52 const MachineOperand &MO,
53 const TargetRegisterInfo *TRI) {
54 assert(MO.isReg() && MO.isDef() && "Not a register def!");
55 return RedefinesSuperRegPart(MI, MO.getReg(), TRI);
58 /// setUsed - Set the register and its sub-registers as being used.
59 void RegScavenger::setUsed(unsigned Reg, bool ImpDef) {
60 RegsAvailable.reset(Reg);
61 ImplicitDefed[Reg] = ImpDef;
63 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
64 unsigned SubReg = *SubRegs; ++SubRegs) {
65 RegsAvailable.reset(SubReg);
66 ImplicitDefed[SubReg] = ImpDef;
70 /// setUnused - Set the register and its sub-registers as being unused.
71 void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) {
72 RegsAvailable.set(Reg);
73 ImplicitDefed.reset(Reg);
75 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
76 unsigned SubReg = *SubRegs; ++SubRegs)
77 if (!RedefinesSuperRegPart(MI, Reg, TRI)) {
78 RegsAvailable.set(SubReg);
79 ImplicitDefed.reset(SubReg);
83 void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
84 MachineFunction &MF = *mbb->getParent();
85 const TargetMachine &TM = MF.getTarget();
86 TII = TM.getInstrInfo();
87 TRI = TM.getRegisterInfo();
88 MRI = &MF.getRegInfo();
90 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
94 NumPhysRegs = TRI->getNumRegs();
95 RegsAvailable.resize(NumPhysRegs);
96 ImplicitDefed.resize(NumPhysRegs);
98 // Create reserved registers bitvector.
99 ReservedRegs = TRI->getReservedRegs(MF);
101 // Create callee-saved registers bitvector.
102 CalleeSavedRegs.resize(NumPhysRegs);
103 const unsigned *CSRegs = TRI->getCalleeSavedRegs();
105 for (unsigned i = 0; CSRegs[i]; ++i)
106 CalleeSavedRegs.set(CSRegs[i]);
113 // All registers started out unused.
116 // Reserved registers are always used.
117 RegsAvailable ^= ReservedRegs;
119 // Live-in registers are in use.
120 if (!MBB->livein_empty())
121 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
122 E = MBB->livein_end(); I != E; ++I)
128 void RegScavenger::restoreScavengedReg() {
132 TII->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
133 ScavengingFrameIndex, ScavengedRC);
134 MachineBasicBlock::iterator II = prior(MBBI);
135 TRI->eliminateFrameIndex(II, 0, this);
136 setUsed(ScavengedReg);
141 /// isLiveInButUnusedBefore - Return true if register is livein the MBB not
142 /// not used before it reaches the MI that defines register.
143 static bool isLiveInButUnusedBefore(unsigned Reg, MachineInstr *MI,
144 MachineBasicBlock *MBB,
145 const TargetRegisterInfo *TRI,
146 MachineRegisterInfo* MRI) {
147 // First check if register is livein.
148 bool isLiveIn = false;
149 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
150 E = MBB->livein_end(); I != E; ++I)
151 if (Reg == *I || TRI->isSuperRegister(Reg, *I)) {
158 // Is there any use of it before the specified MI?
159 SmallPtrSet<MachineInstr*, 4> UsesInMBB;
160 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
161 UE = MRI->use_end(); UI != UE; ++UI) {
162 MachineInstr *UseMI = &*UI;
163 if (UseMI->getParent() == MBB)
164 UsesInMBB.insert(UseMI);
166 if (UsesInMBB.empty())
169 for (MachineBasicBlock::iterator I = MBB->begin(), E = MI; I != E; ++I)
170 if (UsesInMBB.count(&*I))
175 void RegScavenger::forward() {
181 assert(MBBI != MBB->end() && "Already at the end of the basic block!");
185 MachineInstr *MI = MBBI;
186 const TargetInstrDesc &TID = MI->getDesc();
188 // Reaching a terminator instruction. Restore a scavenged register (which
190 if (TID.isTerminator())
191 restoreScavengedReg();
193 bool IsImpDef = MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF;
195 // Separate register operands into 3 classes: uses, defs, earlyclobbers.
196 SmallVector<const MachineOperand*, 4> UseMOs;
197 SmallVector<const MachineOperand*, 4> DefMOs;
198 SmallVector<const MachineOperand*, 4> EarlyClobberMOs;
199 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
200 const MachineOperand &MO = MI->getOperand(i);
201 if (!MO.isReg() || MO.getReg() == 0)
204 UseMOs.push_back(&MO);
205 else if (MO.isEarlyClobber())
206 EarlyClobberMOs.push_back(&MO);
208 DefMOs.push_back(&MO);
211 // Process uses first.
212 BitVector UseRegs(NumPhysRegs);
213 for (unsigned i = 0, e = UseMOs.size(); i != e; ++i) {
214 const MachineOperand &MO = *UseMOs[i];
215 unsigned Reg = MO.getReg();
218 // Register has been scavenged. Restore it!
219 if (Reg == ScavengedReg)
220 restoreScavengedReg();
222 assert(false && "Using an undefined register!");
225 if (MO.isKill() && !isReserved(Reg)) {
228 // Mark sub-registers as used.
229 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
230 unsigned SubReg = *SubRegs; ++SubRegs)
235 // Change states of all registers after all the uses are processed to guard
236 // against multiple uses.
239 // Process early clobber defs then process defs. We can have a early clobber
240 // that is dead, it should not conflict with a def that happens one "slot"
241 // (see InstrSlots in LiveIntervalAnalysis.h) later.
242 unsigned NumECs = EarlyClobberMOs.size();
243 unsigned NumDefs = DefMOs.size();
245 for (unsigned i = 0, e = NumECs + NumDefs; i != e; ++i) {
246 const MachineOperand &MO = (i < NumECs)
247 ? *EarlyClobberMOs[i] : *DefMOs[i-NumECs];
248 unsigned Reg = MO.getReg();
250 // If it's dead upon def, then it is now free.
256 // Skip two-address destination operand.
257 if (TID.findTiedToSrcOperand(i) != -1) {
258 assert(isUsed(Reg) && "Using an undefined register!");
262 // Skip is this is merely redefining part of a super-register.
263 if (RedefinesSuperRegPart(MI, MO, TRI))
266 // Implicit def is allowed to "re-define" any register. Similarly,
267 // implicitly defined registers can be clobbered.
268 assert((isReserved(Reg) || isUnused(Reg) ||
269 IsImpDef || isImplicitlyDefined(Reg) ||
270 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
271 "Re-defining a live register!");
272 setUsed(Reg, IsImpDef);
276 void RegScavenger::backward() {
277 assert(Tracking && "Not tracking states!");
278 assert(MBBI != MBB->begin() && "Already at start of basic block!");
279 // Move ptr backward.
282 MachineInstr *MI = MBBI;
283 // Process defs first.
284 const TargetInstrDesc &TID = MI->getDesc();
285 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
286 const MachineOperand &MO = MI->getOperand(i);
287 if (!MO.isReg() || !MO.isDef())
289 // Skip two-address destination operand.
290 if (TID.findTiedToSrcOperand(i) != -1)
292 unsigned Reg = MO.getReg();
294 if (!isReserved(Reg))
299 BitVector UseRegs(NumPhysRegs);
300 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
301 const MachineOperand &MO = MI->getOperand(i);
302 if (!MO.isReg() || !MO.isUse())
304 unsigned Reg = MO.getReg();
307 assert(isUnused(Reg) || isReserved(Reg));
310 // Set the sub-registers as "used".
311 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
312 unsigned SubReg = *SubRegs; ++SubRegs)
318 void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
320 used = ~RegsAvailable;
322 used = ~RegsAvailable & ~ReservedRegs;
325 /// CreateRegClassMask - Set the bits that represent the registers in the
326 /// TargetRegisterClass.
327 static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {
328 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E;
333 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
334 const BitVector &Candidates) const {
335 // Mask off the registers which are not in the TargetRegisterClass.
336 BitVector RegsAvailableCopy(NumPhysRegs, false);
337 CreateRegClassMask(RegClass, RegsAvailableCopy);
338 RegsAvailableCopy &= RegsAvailable;
340 // Restrict the search to candidates.
341 RegsAvailableCopy &= Candidates;
343 // Returns the first unused (bit is set) register, or 0 is none is found.
344 int Reg = RegsAvailableCopy.find_first();
345 return (Reg == -1) ? 0 : Reg;
348 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
349 bool ExCalleeSaved) const {
350 // Mask off the registers which are not in the TargetRegisterClass.
351 BitVector RegsAvailableCopy(NumPhysRegs, false);
352 CreateRegClassMask(RegClass, RegsAvailableCopy);
353 RegsAvailableCopy &= RegsAvailable;
355 // If looking for a non-callee-saved register, mask off all the callee-saved
358 RegsAvailableCopy &= ~CalleeSavedRegs;
360 // Returns the first unused (bit is set) register, or 0 is none is found.
361 int Reg = RegsAvailableCopy.find_first();
362 return (Reg == -1) ? 0 : Reg;
365 /// calcDistanceToUse - Calculate the distance to the first use of the
366 /// specified register.
367 static unsigned calcDistanceToUse(MachineBasicBlock *MBB,
368 MachineBasicBlock::iterator I, unsigned Reg,
369 const TargetRegisterInfo *TRI) {
372 while (I != MBB->end()) {
374 if (I->readsRegister(Reg, TRI))
381 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
382 MachineBasicBlock::iterator I,
384 assert(ScavengingFrameIndex >= 0 &&
385 "Cannot scavenge a register without an emergency spill slot!");
387 // Mask off the registers which are not in the TargetRegisterClass.
388 BitVector Candidates(NumPhysRegs, false);
389 CreateRegClassMask(RC, Candidates);
390 Candidates ^= ReservedRegs; // Do not include reserved registers.
392 // Exclude all the registers being used by the instruction.
393 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
394 MachineOperand &MO = I->getOperand(i);
396 Candidates.reset(MO.getReg());
399 // Find the register whose use is furthest away.
401 unsigned MaxDist = 0;
402 int Reg = Candidates.find_first();
404 unsigned Dist = calcDistanceToUse(MBB, I, Reg, TRI);
405 if (Dist >= MaxDist) {
409 Reg = Candidates.find_next(Reg);
412 if (ScavengedReg != 0) {
413 // First restore previously scavenged register.
414 TII->loadRegFromStackSlot(*MBB, I, ScavengedReg,
415 ScavengingFrameIndex, ScavengedRC);
416 MachineBasicBlock::iterator II = prior(I);
417 TRI->eliminateFrameIndex(II, SPAdj, this);
420 TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
421 MachineBasicBlock::iterator II = prior(I);
422 TRI->eliminateFrameIndex(II, SPAdj, this);