1 //===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the ScheduleDAGInstrs class, which implements re-scheduling
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "sched-instrs"
16 #include "ScheduleDAGInstrs.h"
17 #include "llvm/Operator.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Analysis/ValueTracking.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineMemOperand.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/MC/MCInstrItineraries.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Target/TargetSubtargetInfo.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/ADT/SmallSet.h"
34 ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
35 const MachineLoopInfo &mli,
36 const MachineDominatorTree &mdt)
37 : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()),
38 InstrItins(mf.getTarget().getInstrItineraryData()),
39 Defs(TRI->getNumRegs()), Uses(TRI->getNumRegs()),
40 LoopRegs(MLI, MDT), FirstDbgValue(0) {
44 /// Run - perform scheduling.
46 void ScheduleDAGInstrs::Run(MachineBasicBlock *bb,
47 MachineBasicBlock::iterator begin,
48 MachineBasicBlock::iterator end,
52 InsertPosIndex = endcount;
54 ScheduleDAG::Run(bb, end);
57 /// getUnderlyingObjectFromInt - This is the function that does the work of
58 /// looking through basic ptrtoint+arithmetic+inttoptr sequences.
59 static const Value *getUnderlyingObjectFromInt(const Value *V) {
61 if (const Operator *U = dyn_cast<Operator>(V)) {
62 // If we find a ptrtoint, we can transfer control back to the
63 // regular getUnderlyingObjectFromInt.
64 if (U->getOpcode() == Instruction::PtrToInt)
65 return U->getOperand(0);
66 // If we find an add of a constant or a multiplied value, it's
67 // likely that the other operand will lead us to the base
68 // object. We don't have to worry about the case where the
69 // object address is somehow being computed by the multiply,
70 // because our callers only care when the result is an
71 // identifibale object.
72 if (U->getOpcode() != Instruction::Add ||
73 (!isa<ConstantInt>(U->getOperand(1)) &&
74 Operator::getOpcode(U->getOperand(1)) != Instruction::Mul))
80 assert(V->getType()->isIntegerTy() && "Unexpected operand type!");
84 /// getUnderlyingObject - This is a wrapper around GetUnderlyingObject
85 /// and adds support for basic ptrtoint+arithmetic+inttoptr sequences.
86 static const Value *getUnderlyingObject(const Value *V) {
87 // First just call Value::getUnderlyingObject to let it do what it does.
89 V = GetUnderlyingObject(V);
90 // If it found an inttoptr, use special code to continue climing.
91 if (Operator::getOpcode(V) != Instruction::IntToPtr)
93 const Value *O = getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0));
94 // If that succeeded in finding a pointer, continue the search.
95 if (!O->getType()->isPointerTy())
102 /// getUnderlyingObjectForInstr - If this machine instr has memory reference
103 /// information and it can be tracked to a normal reference to a known
104 /// object, return the Value for that object. Otherwise return null.
105 static const Value *getUnderlyingObjectForInstr(const MachineInstr *MI,
106 const MachineFrameInfo *MFI,
109 if (!MI->hasOneMemOperand() ||
110 !(*MI->memoperands_begin())->getValue() ||
111 (*MI->memoperands_begin())->isVolatile())
114 const Value *V = (*MI->memoperands_begin())->getValue();
118 V = getUnderlyingObject(V);
119 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
120 // For now, ignore PseudoSourceValues which may alias LLVM IR values
121 // because the code that uses this function has no way to cope with
123 if (PSV->isAliased(MFI))
126 MayAlias = PSV->mayAlias(MFI);
130 if (isIdentifiedObject(V))
136 void ScheduleDAGInstrs::StartBlock(MachineBasicBlock *BB) {
137 LoopRegs.Deps.clear();
138 if (MachineLoop *ML = MLI.getLoopFor(BB))
139 if (BB == ML->getLoopLatch()) {
140 MachineBasicBlock *Header = ML->getHeader();
141 for (MachineBasicBlock::livein_iterator I = Header->livein_begin(),
142 E = Header->livein_end(); I != E; ++I)
143 LoopLiveInRegs.insert(*I);
144 LoopRegs.VisitLoop(ML);
148 /// AddSchedBarrierDeps - Add dependencies from instructions in the current
149 /// list of instructions being scheduled to scheduling barrier by adding
150 /// the exit SU to the register defs and use list. This is because we want to
151 /// make sure instructions which define registers that are either used by
152 /// the terminator or are live-out are properly scheduled. This is
153 /// especially important when the definition latency of the return value(s)
154 /// are too high to be hidden by the branch or when the liveout registers
155 /// used by instructions in the fallthrough block.
156 void ScheduleDAGInstrs::AddSchedBarrierDeps() {
157 MachineInstr *ExitMI = InsertPos != BB->end() ? &*InsertPos : 0;
158 ExitSU.setInstr(ExitMI);
159 bool AllDepKnown = ExitMI &&
160 (ExitMI->getDesc().isCall() || ExitMI->getDesc().isBarrier());
161 if (ExitMI && AllDepKnown) {
162 // If it's a call or a barrier, add dependencies on the defs and uses of
164 for (unsigned i = 0, e = ExitMI->getNumOperands(); i != e; ++i) {
165 const MachineOperand &MO = ExitMI->getOperand(i);
166 if (!MO.isReg() || MO.isDef()) continue;
167 unsigned Reg = MO.getReg();
168 if (Reg == 0) continue;
170 assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!");
171 Uses[Reg].push_back(&ExitSU);
174 // For others, e.g. fallthrough, conditional branch, assume the exit
175 // uses all the registers that are livein to the successor blocks.
176 SmallSet<unsigned, 8> Seen;
177 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
178 SE = BB->succ_end(); SI != SE; ++SI)
179 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
180 E = (*SI)->livein_end(); I != E; ++I) {
182 if (Seen.insert(Reg))
183 Uses[Reg].push_back(&ExitSU);
188 void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
189 // We'll be allocating one SUnit for each instruction, plus one for
190 // the region exit node.
191 SUnits.reserve(BB->size());
193 // We build scheduling units by walking a block's instruction list from bottom
196 // Remember where a generic side-effecting instruction is as we procede.
197 SUnit *BarrierChain = 0, *AliasChain = 0;
199 // Memory references to specific known memory locations are tracked
200 // so that they can be given more precise dependencies. We track
201 // separately the known memory locations that may alias and those
202 // that are known not to alias
203 std::map<const Value *, SUnit *> AliasMemDefs, NonAliasMemDefs;
204 std::map<const Value *, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses;
206 // Check to see if the scheduler cares about latencies.
207 bool UnitLatencies = ForceUnitLatencies();
209 // Ask the target if address-backscheduling is desirable, and if so how much.
210 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
211 unsigned SpecialAddressLatency = ST.getSpecialAddressLatency();
213 // Remove any stale debug info; sometimes BuildSchedGraph is called again
214 // without emitting the info from the previous call.
216 FirstDbgValue = NULL;
218 // Model data dependencies between instructions being scheduled and the
220 AddSchedBarrierDeps();
222 for (int i = 0, e = TRI->getNumRegs(); i != e; ++i) {
223 assert(Defs[i].empty() && "Only BuildGraph should push/pop Defs");
226 // Walk the list of instructions, from bottom moving up.
227 MachineInstr *PrevMI = NULL;
228 for (MachineBasicBlock::iterator MII = InsertPos, MIE = Begin;
230 MachineInstr *MI = prior(MII);
232 DbgValues.push_back(std::make_pair(PrevMI, MI));
236 if (MI->isDebugValue()) {
241 const MCInstrDesc &MCID = MI->getDesc();
242 assert(!MCID.isTerminator() && !MI->isLabel() &&
243 "Cannot schedule terminators or labels!");
244 // Create the SUnit for this MI.
245 SUnit *SU = NewSUnit(MI);
246 SU->isCall = MCID.isCall();
247 SU->isCommutable = MCID.isCommutable();
249 // Assign the Latency field of SU using target-provided information.
255 // Add register-based dependencies (data, anti, and output).
256 for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
257 const MachineOperand &MO = MI->getOperand(j);
258 if (!MO.isReg()) continue;
259 unsigned Reg = MO.getReg();
260 if (Reg == 0) continue;
262 assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!");
264 std::vector<SUnit *> &UseList = Uses[Reg];
265 // Defs are push in the order they are visited and never reordered.
266 std::vector<SUnit *> &DefList = Defs[Reg];
267 // Optionally add output and anti dependencies. For anti
268 // dependencies we use a latency of 0 because for a multi-issue
269 // target we want to allow the defining instruction to issue
270 // in the same cycle as the using instruction.
271 // TODO: Using a latency of 1 here for output dependencies assumes
272 // there's no cost for reusing registers.
273 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
274 unsigned AOLatency = (Kind == SDep::Anti) ? 0 : 1;
275 for (unsigned i = 0, e = DefList.size(); i != e; ++i) {
276 SUnit *DefSU = DefList[i];
277 if (DefSU == &ExitSU)
280 (Kind != SDep::Output || !MO.isDead() ||
281 !DefSU->getInstr()->registerDefIsDead(Reg)))
282 DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/Reg));
284 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
285 std::vector<SUnit *> &MemDefList = Defs[*Alias];
286 for (unsigned i = 0, e = MemDefList.size(); i != e; ++i) {
287 SUnit *DefSU = MemDefList[i];
288 if (DefSU == &ExitSU)
291 (Kind != SDep::Output || !MO.isDead() ||
292 !DefSU->getInstr()->registerDefIsDead(*Alias)))
293 DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/ *Alias));
298 // Add any data dependencies.
299 unsigned DataLatency = SU->Latency;
300 for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
301 SUnit *UseSU = UseList[i];
304 unsigned LDataLatency = DataLatency;
305 // Optionally add in a special extra latency for nodes that
307 // TODO: Do this for register aliases too.
308 // TODO: Perhaps we should get rid of
309 // SpecialAddressLatency and just move this into
310 // adjustSchedDependency for the targets that care about it.
311 if (SpecialAddressLatency != 0 && !UnitLatencies &&
313 MachineInstr *UseMI = UseSU->getInstr();
314 const MCInstrDesc &UseMCID = UseMI->getDesc();
315 int RegUseIndex = UseMI->findRegisterUseOperandIdx(Reg);
316 assert(RegUseIndex >= 0 && "UseMI doesn's use register!");
317 if (RegUseIndex >= 0 &&
318 (UseMCID.mayLoad() || UseMCID.mayStore()) &&
319 (unsigned)RegUseIndex < UseMCID.getNumOperands() &&
320 UseMCID.OpInfo[RegUseIndex].isLookupPtrRegClass())
321 LDataLatency += SpecialAddressLatency;
323 // Adjust the dependence latency using operand def/use
324 // information (if any), and then allow the target to
325 // perform its own adjustments.
326 const SDep& dep = SDep(SU, SDep::Data, LDataLatency, Reg);
327 if (!UnitLatencies) {
328 ComputeOperandLatency(SU, UseSU, const_cast<SDep &>(dep));
329 ST.adjustSchedDependency(SU, UseSU, const_cast<SDep &>(dep));
333 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
334 std::vector<SUnit *> &UseList = Uses[*Alias];
335 for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
336 SUnit *UseSU = UseList[i];
339 const SDep& dep = SDep(SU, SDep::Data, DataLatency, *Alias);
340 if (!UnitLatencies) {
341 ComputeOperandLatency(SU, UseSU, const_cast<SDep &>(dep));
342 ST.adjustSchedDependency(SU, UseSU, const_cast<SDep &>(dep));
348 // If a def is going to wrap back around to the top of the loop,
350 if (!UnitLatencies && DefList.empty()) {
351 LoopDependencies::LoopDeps::iterator I = LoopRegs.Deps.find(Reg);
352 if (I != LoopRegs.Deps.end()) {
353 const MachineOperand *UseMO = I->second.first;
354 unsigned Count = I->second.second;
355 const MachineInstr *UseMI = UseMO->getParent();
356 unsigned UseMOIdx = UseMO - &UseMI->getOperand(0);
357 const MCInstrDesc &UseMCID = UseMI->getDesc();
358 // TODO: If we knew the total depth of the region here, we could
359 // handle the case where the whole loop is inside the region but
360 // is large enough that the isScheduleHigh trick isn't needed.
361 if (UseMOIdx < UseMCID.getNumOperands()) {
362 // Currently, we only support scheduling regions consisting of
363 // single basic blocks. Check to see if the instruction is in
364 // the same region by checking to see if it has the same parent.
365 if (UseMI->getParent() != MI->getParent()) {
366 unsigned Latency = SU->Latency;
367 if (UseMCID.OpInfo[UseMOIdx].isLookupPtrRegClass())
368 Latency += SpecialAddressLatency;
369 // This is a wild guess as to the portion of the latency which
370 // will be overlapped by work done outside the current
371 // scheduling region.
372 Latency -= std::min(Latency, Count);
373 // Add the artificial edge.
374 ExitSU.addPred(SDep(SU, SDep::Order, Latency,
375 /*Reg=*/0, /*isNormalMemory=*/false,
376 /*isMustAlias=*/false,
377 /*isArtificial=*/true));
378 } else if (SpecialAddressLatency > 0 &&
379 UseMCID.OpInfo[UseMOIdx].isLookupPtrRegClass()) {
380 // The entire loop body is within the current scheduling region
381 // and the latency of this operation is assumed to be greater
382 // than the latency of the loop.
383 // TODO: Recursively mark data-edge predecessors as
384 // isScheduleHigh too.
385 SU->isScheduleHigh = true;
388 LoopRegs.Deps.erase(I);
396 // Calls will not be reordered because of chain dependencies (see
397 // below). Since call operands are dead, calls may continue to be added
398 // to the DefList making dependence checking quadratic in the size of
399 // the block. Instead, we leave only one call at the back of the
402 while (!DefList.empty() && DefList.back()->isCall)
405 DefList.push_back(SU);
407 UseList.push_back(SU);
411 // Add chain dependencies.
412 // Chain dependencies used to enforce memory order should have
413 // latency of 0 (except for true dependency of Store followed by
414 // aliased Load... we estimate that with a single cycle of latency
415 // assuming the hardware will bypass)
416 // Note that isStoreToStackSlot and isLoadFromStackSLot are not usable
417 // after stack slots are lowered to actual addresses.
418 // TODO: Use an AliasAnalysis and do real alias-analysis queries, and
419 // produce more precise dependence information.
420 #define STORE_LOAD_LATENCY 1
421 unsigned TrueMemOrderLatency = 0;
422 if (MCID.isCall() || MI->hasUnmodeledSideEffects() ||
423 (MI->hasVolatileMemoryRef() &&
424 (!MCID.mayLoad() || !MI->isInvariantLoad(AA)))) {
425 // Be conservative with these and add dependencies on all memory
426 // references, even those that are known to not alias.
427 for (std::map<const Value *, SUnit *>::iterator I =
428 NonAliasMemDefs.begin(), E = NonAliasMemDefs.end(); I != E; ++I) {
429 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
431 for (std::map<const Value *, std::vector<SUnit *> >::iterator I =
432 NonAliasMemUses.begin(), E = NonAliasMemUses.end(); I != E; ++I) {
433 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
434 I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
436 NonAliasMemDefs.clear();
437 NonAliasMemUses.clear();
438 // Add SU to the barrier chain.
440 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
445 // Chain all possibly aliasing memory references though SU.
447 AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
449 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
450 PendingLoads[k]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
451 for (std::map<const Value *, SUnit *>::iterator I = AliasMemDefs.begin(),
452 E = AliasMemDefs.end(); I != E; ++I) {
453 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
455 for (std::map<const Value *, std::vector<SUnit *> >::iterator I =
456 AliasMemUses.begin(), E = AliasMemUses.end(); I != E; ++I) {
457 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
458 I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
460 PendingLoads.clear();
461 AliasMemDefs.clear();
462 AliasMemUses.clear();
463 } else if (MCID.mayStore()) {
464 bool MayAlias = true;
465 TrueMemOrderLatency = STORE_LOAD_LATENCY;
466 if (const Value *V = getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
467 // A store to a specific PseudoSourceValue. Add precise dependencies.
468 // Record the def in MemDefs, first adding a dep if there is
470 std::map<const Value *, SUnit *>::iterator I =
471 ((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
472 std::map<const Value *, SUnit *>::iterator IE =
473 ((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
475 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0, /*Reg=*/0,
476 /*isNormalMemory=*/true));
480 AliasMemDefs[V] = SU;
482 NonAliasMemDefs[V] = SU;
484 // Handle the uses in MemUses, if there are any.
485 std::map<const Value *, std::vector<SUnit *> >::iterator J =
486 ((MayAlias) ? AliasMemUses.find(V) : NonAliasMemUses.find(V));
487 std::map<const Value *, std::vector<SUnit *> >::iterator JE =
488 ((MayAlias) ? AliasMemUses.end() : NonAliasMemUses.end());
490 for (unsigned i = 0, e = J->second.size(); i != e; ++i)
491 J->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency,
492 /*Reg=*/0, /*isNormalMemory=*/true));
496 // Add dependencies from all the PendingLoads, i.e. loads
497 // with no underlying object.
498 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
499 PendingLoads[k]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
500 // Add dependence on alias chain, if needed.
502 AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
504 // Add dependence on barrier chain, if needed.
506 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
508 // Treat all other stores conservatively.
509 goto new_alias_chain;
512 if (!ExitSU.isPred(SU))
513 // Push store's up a bit to avoid them getting in between cmp
515 ExitSU.addPred(SDep(SU, SDep::Order, 0,
516 /*Reg=*/0, /*isNormalMemory=*/false,
517 /*isMustAlias=*/false,
518 /*isArtificial=*/true));
519 } else if (MCID.mayLoad()) {
520 bool MayAlias = true;
521 TrueMemOrderLatency = 0;
522 if (MI->isInvariantLoad(AA)) {
523 // Invariant load, no chain dependencies needed!
526 getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
527 // A load from a specific PseudoSourceValue. Add precise dependencies.
528 std::map<const Value *, SUnit *>::iterator I =
529 ((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
530 std::map<const Value *, SUnit *>::iterator IE =
531 ((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
533 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0, /*Reg=*/0,
534 /*isNormalMemory=*/true));
536 AliasMemUses[V].push_back(SU);
538 NonAliasMemUses[V].push_back(SU);
540 // A load with no underlying object. Depend on all
541 // potentially aliasing stores.
542 for (std::map<const Value *, SUnit *>::iterator I =
543 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I)
544 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
546 PendingLoads.push_back(SU);
550 // Add dependencies on alias and barrier chains, if needed.
551 if (MayAlias && AliasChain)
552 AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
554 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
559 FirstDbgValue = PrevMI;
561 for (int i = 0, e = TRI->getNumRegs(); i != e; ++i) {
565 PendingLoads.clear();
568 void ScheduleDAGInstrs::FinishBlock() {
572 void ScheduleDAGInstrs::ComputeLatency(SUnit *SU) {
573 // Compute the latency for the node.
574 if (!InstrItins || InstrItins->isEmpty()) {
577 // Simplistic target-independent heuristic: assume that loads take
579 if (SU->getInstr()->getDesc().mayLoad())
582 SU->Latency = TII->getInstrLatency(InstrItins, SU->getInstr());
586 void ScheduleDAGInstrs::ComputeOperandLatency(SUnit *Def, SUnit *Use,
588 if (!InstrItins || InstrItins->isEmpty())
591 // For a data dependency with a known register...
592 if ((dep.getKind() != SDep::Data) || (dep.getReg() == 0))
595 const unsigned Reg = dep.getReg();
597 // ... find the definition of the register in the defining
599 MachineInstr *DefMI = Def->getInstr();
600 int DefIdx = DefMI->findRegisterDefOperandIdx(Reg);
602 const MachineOperand &MO = DefMI->getOperand(DefIdx);
603 if (MO.isReg() && MO.isImplicit() &&
604 DefIdx >= (int)DefMI->getDesc().getNumOperands()) {
605 // This is an implicit def, getOperandLatency() won't return the correct
607 // %D6<def>, %D7<def> = VLD1q16 %R2<kill>, 0, ..., %Q3<imp-def>
608 // %Q1<def> = VMULv8i16 %Q1<kill>, %Q3<kill>, ...
609 // What we want is to compute latency between def of %D6/%D7 and use of
611 DefIdx = DefMI->findRegisterDefOperandIdx(Reg, false, true, TRI);
613 MachineInstr *UseMI = Use->getInstr();
614 // For all uses of the register, calculate the maxmimum latency
617 for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) {
618 const MachineOperand &MO = UseMI->getOperand(i);
619 if (!MO.isReg() || !MO.isUse())
621 unsigned MOReg = MO.getReg();
625 int UseCycle = TII->getOperandLatency(InstrItins, DefMI, DefIdx,
627 Latency = std::max(Latency, UseCycle);
630 // UseMI is null, then it must be a scheduling barrier.
631 if (!InstrItins || InstrItins->isEmpty())
633 unsigned DefClass = DefMI->getDesc().getSchedClass();
634 Latency = InstrItins->getOperandCycle(DefClass, DefIdx);
637 // If we found a latency, then replace the existing dependence latency.
639 dep.setLatency(Latency);
643 void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
644 SU->getInstr()->dump();
647 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
649 raw_string_ostream oss(s);
652 else if (SU == &ExitSU)
655 SU->getInstr()->print(oss);
659 // EmitSchedule - Emit the machine code in scheduled order.
660 MachineBasicBlock *ScheduleDAGInstrs::EmitSchedule() {
661 // For MachineInstr-based scheduling, we're rescheduling the instructions in
662 // the block, so start by removing them from the block.
663 while (Begin != InsertPos) {
664 MachineBasicBlock::iterator I = Begin;
669 // If first instruction was a DBG_VALUE then put it back.
671 BB->insert(InsertPos, FirstDbgValue);
673 // Then re-insert them according to the given schedule.
674 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
675 if (SUnit *SU = Sequence[i])
676 BB->insert(InsertPos, SU->getInstr());
678 // Null SUnit* is a noop.
682 // Update the Begin iterator, as the first instruction in the block
683 // may have been scheduled later.
684 if (!Sequence.empty())
685 Begin = Sequence[0]->getInstr();
687 // Reinsert any remaining debug_values.
688 for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
689 DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
690 std::pair<MachineInstr *, MachineInstr *> P = *prior(DI);
691 MachineInstr *DbgValue = P.first;
692 MachineInstr *OrigPrivMI = P.second;
693 BB->insertAfter(OrigPrivMI, DbgValue);
696 FirstDbgValue = NULL;