1 //===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the ScheduleDAGInstrs class, which implements re-scheduling
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "misched"
16 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
17 #include "llvm/ADT/MapVector.h"
18 #include "llvm/ADT/SmallPtrSet.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ValueTracking.h"
22 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/CodeGen/RegisterPressure.h"
28 #include "llvm/CodeGen/ScheduleDFS.h"
29 #include "llvm/IR/Operator.h"
30 #include "llvm/MC/MCInstrItineraries.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/Format.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetRegisterInfo.h"
38 #include "llvm/Target/TargetSubtargetInfo.h"
41 static cl::opt<bool> EnableAASchedMI("enable-aa-sched-mi", cl::Hidden,
42 cl::ZeroOrMore, cl::init(false),
43 cl::desc("Enable use of AA during MI GAD construction"));
45 ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
46 const MachineLoopInfo &mli,
47 const MachineDominatorTree &mdt,
50 : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()), LIS(lis),
51 IsPostRA(IsPostRAFlag), CanHandleTerminators(false), FirstDbgValue(0) {
52 assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
54 assert(!(IsPostRA && MRI.getNumVirtRegs()) &&
55 "Virtual registers must be removed prior to PostRA scheduling");
57 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
58 SchedModel.init(*ST.getSchedModel(), &ST, TII);
61 /// getUnderlyingObjectFromInt - This is the function that does the work of
62 /// looking through basic ptrtoint+arithmetic+inttoptr sequences.
63 static const Value *getUnderlyingObjectFromInt(const Value *V) {
65 if (const Operator *U = dyn_cast<Operator>(V)) {
66 // If we find a ptrtoint, we can transfer control back to the
67 // regular getUnderlyingObjectFromInt.
68 if (U->getOpcode() == Instruction::PtrToInt)
69 return U->getOperand(0);
70 // If we find an add of a constant, a multiplied value, or a phi, it's
71 // likely that the other operand will lead us to the base
72 // object. We don't have to worry about the case where the
73 // object address is somehow being computed by the multiply,
74 // because our callers only care when the result is an
75 // identifiable object.
76 if (U->getOpcode() != Instruction::Add ||
77 (!isa<ConstantInt>(U->getOperand(1)) &&
78 Operator::getOpcode(U->getOperand(1)) != Instruction::Mul &&
79 !isa<PHINode>(U->getOperand(1))))
85 assert(V->getType()->isIntegerTy() && "Unexpected operand type!");
89 /// getUnderlyingObjects - This is a wrapper around GetUnderlyingObjects
90 /// and adds support for basic ptrtoint+arithmetic+inttoptr sequences.
91 static void getUnderlyingObjects(const Value *V,
92 SmallVectorImpl<Value *> &Objects) {
93 SmallPtrSet<const Value*, 16> Visited;
94 SmallVector<const Value *, 4> Working(1, V);
96 V = Working.pop_back_val();
98 SmallVector<Value *, 4> Objs;
99 GetUnderlyingObjects(const_cast<Value *>(V), Objs);
101 for (SmallVector<Value *, 4>::iterator I = Objs.begin(), IE = Objs.end();
104 if (!Visited.insert(V))
106 if (Operator::getOpcode(V) == Instruction::IntToPtr) {
108 getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0));
109 if (O->getType()->isPointerTy()) {
110 Working.push_back(O);
114 Objects.push_back(const_cast<Value *>(V));
116 } while (!Working.empty());
119 /// getUnderlyingObjectsForInstr - If this machine instr has memory reference
120 /// information and it can be tracked to a normal reference to a known
121 /// object, return the Value for that object.
122 static void getUnderlyingObjectsForInstr(const MachineInstr *MI,
123 const MachineFrameInfo *MFI,
124 SmallVectorImpl<std::pair<const Value *, bool> > &Objects) {
125 if (!MI->hasOneMemOperand() ||
126 !(*MI->memoperands_begin())->getValue() ||
127 (*MI->memoperands_begin())->isVolatile())
130 const Value *V = (*MI->memoperands_begin())->getValue();
134 SmallVector<Value *, 4> Objs;
135 getUnderlyingObjects(V, Objs);
137 for (SmallVector<Value *, 4>::iterator I = Objs.begin(), IE = Objs.end();
139 bool MayAlias = true;
142 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
143 // For now, ignore PseudoSourceValues which may alias LLVM IR values
144 // because the code that uses this function has no way to cope with
147 if (PSV->isAliased(MFI)) {
152 MayAlias = PSV->mayAlias(MFI);
153 } else if (!isIdentifiedObject(V)) {
158 Objects.push_back(std::make_pair(V, MayAlias));
162 void ScheduleDAGInstrs::startBlock(MachineBasicBlock *bb) {
166 void ScheduleDAGInstrs::finishBlock() {
167 // Subclasses should no longer refer to the old block.
171 /// Initialize the map with the number of registers.
172 void Reg2SUnitsMap::setRegLimit(unsigned Limit) {
173 PhysRegSet.setUniverse(Limit);
174 SUnits.resize(Limit);
177 /// Clear the map without deallocating storage.
178 void Reg2SUnitsMap::clear() {
179 for (const_iterator I = reg_begin(), E = reg_end(); I != E; ++I) {
185 /// Initialize the DAG and common scheduler state for the current scheduling
186 /// region. This does not actually create the DAG, only clears it. The
187 /// scheduling driver may call BuildSchedGraph multiple times per scheduling
189 void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb,
190 MachineBasicBlock::iterator begin,
191 MachineBasicBlock::iterator end,
193 assert(bb == BB && "startBlock should set BB");
199 ScheduleDAG::clearDAG();
202 /// Close the current scheduling region. Don't clear any state in case the
203 /// driver wants to refer to the previous scheduling region.
204 void ScheduleDAGInstrs::exitRegion() {
208 /// addSchedBarrierDeps - Add dependencies from instructions in the current
209 /// list of instructions being scheduled to scheduling barrier by adding
210 /// the exit SU to the register defs and use list. This is because we want to
211 /// make sure instructions which define registers that are either used by
212 /// the terminator or are live-out are properly scheduled. This is
213 /// especially important when the definition latency of the return value(s)
214 /// are too high to be hidden by the branch or when the liveout registers
215 /// used by instructions in the fallthrough block.
216 void ScheduleDAGInstrs::addSchedBarrierDeps() {
217 MachineInstr *ExitMI = RegionEnd != BB->end() ? &*RegionEnd : 0;
218 ExitSU.setInstr(ExitMI);
219 bool AllDepKnown = ExitMI &&
220 (ExitMI->isCall() || ExitMI->isBarrier());
221 if (ExitMI && AllDepKnown) {
222 // If it's a call or a barrier, add dependencies on the defs and uses of
224 for (unsigned i = 0, e = ExitMI->getNumOperands(); i != e; ++i) {
225 const MachineOperand &MO = ExitMI->getOperand(i);
226 if (!MO.isReg() || MO.isDef()) continue;
227 unsigned Reg = MO.getReg();
228 if (Reg == 0) continue;
230 if (TRI->isPhysicalRegister(Reg))
231 Uses[Reg].push_back(PhysRegSUOper(&ExitSU, -1));
233 assert(!IsPostRA && "Virtual register encountered after regalloc.");
234 if (MO.readsReg()) // ignore undef operands
235 addVRegUseDeps(&ExitSU, i);
239 // For others, e.g. fallthrough, conditional branch, assume the exit
240 // uses all the registers that are livein to the successor blocks.
241 assert(Uses.empty() && "Uses in set before adding deps?");
242 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
243 SE = BB->succ_end(); SI != SE; ++SI)
244 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
245 E = (*SI)->livein_end(); I != E; ++I) {
247 if (!Uses.contains(Reg))
248 Uses[Reg].push_back(PhysRegSUOper(&ExitSU, -1));
253 /// MO is an operand of SU's instruction that defines a physical register. Add
254 /// data dependencies from SU to any uses of the physical register.
255 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
256 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
257 assert(MO.isDef() && "expect physreg def");
259 // Ask the target if address-backscheduling is desirable, and if so how much.
260 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
262 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
263 Alias.isValid(); ++Alias) {
264 if (!Uses.contains(*Alias))
266 std::vector<PhysRegSUOper> &UseList = Uses[*Alias];
267 for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
268 SUnit *UseSU = UseList[i].SU;
272 // Adjust the dependence latency using operand def/use information,
273 // then allow the target to perform its own adjustments.
274 int UseOp = UseList[i].OpIdx;
275 MachineInstr *RegUse = 0;
278 Dep = SDep(SU, SDep::Artificial);
280 Dep = SDep(SU, SDep::Data, *Alias);
281 RegUse = UseSU->getInstr();
283 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
284 RegUse, UseOp, /*FindMin=*/true));
287 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
288 RegUse, UseOp, /*FindMin=*/false));
290 ST.adjustSchedDependency(SU, UseSU, Dep);
296 /// addPhysRegDeps - Add register dependencies (data, anti, and output) from
297 /// this SUnit to following instructions in the same scheduling region that
298 /// depend the physical register referenced at OperIdx.
299 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
300 const MachineInstr *MI = SU->getInstr();
301 const MachineOperand &MO = MI->getOperand(OperIdx);
303 // Optionally add output and anti dependencies. For anti
304 // dependencies we use a latency of 0 because for a multi-issue
305 // target we want to allow the defining instruction to issue
306 // in the same cycle as the using instruction.
307 // TODO: Using a latency of 1 here for output dependencies assumes
308 // there's no cost for reusing registers.
309 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
310 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
311 Alias.isValid(); ++Alias) {
312 if (!Defs.contains(*Alias))
314 std::vector<PhysRegSUOper> &DefList = Defs[*Alias];
315 for (unsigned i = 0, e = DefList.size(); i != e; ++i) {
316 SUnit *DefSU = DefList[i].SU;
317 if (DefSU == &ExitSU)
320 (Kind != SDep::Output || !MO.isDead() ||
321 !DefSU->getInstr()->registerDefIsDead(*Alias))) {
322 if (Kind == SDep::Anti)
323 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias));
325 SDep Dep(SU, Kind, /*Reg=*/*Alias);
326 unsigned OutLatency =
327 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr());
328 Dep.setMinLatency(OutLatency);
329 Dep.setLatency(OutLatency);
337 // Either insert a new Reg2SUnits entry with an empty SUnits list, or
338 // retrieve the existing SUnits list for this register's uses.
339 // Push this SUnit on the use list.
340 Uses[MO.getReg()].push_back(PhysRegSUOper(SU, OperIdx));
343 addPhysRegDataDeps(SU, OperIdx);
345 // Either insert a new Reg2SUnits entry with an empty SUnits list, or
346 // retrieve the existing SUnits list for this register's defs.
347 std::vector<PhysRegSUOper> &DefList = Defs[MO.getReg()];
349 // clear this register's use list
350 if (Uses.contains(MO.getReg()))
351 Uses[MO.getReg()].clear();
356 // Calls will not be reordered because of chain dependencies (see
357 // below). Since call operands are dead, calls may continue to be added
358 // to the DefList making dependence checking quadratic in the size of
359 // the block. Instead, we leave only one call at the back of the
362 while (!DefList.empty() && DefList.back().SU->isCall)
365 // Defs are pushed in the order they are visited and never reordered.
366 DefList.push_back(PhysRegSUOper(SU, OperIdx));
370 /// addVRegDefDeps - Add register output and data dependencies from this SUnit
371 /// to instructions that occur later in the same scheduling region if they read
372 /// from or write to the virtual register defined at OperIdx.
374 /// TODO: Hoist loop induction variable increments. This has to be
375 /// reevaluated. Generally, IV scheduling should be done before coalescing.
376 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
377 const MachineInstr *MI = SU->getInstr();
378 unsigned Reg = MI->getOperand(OperIdx).getReg();
380 // Singly defined vregs do not have output/anti dependencies.
381 // The current operand is a def, so we have at least one.
382 // Check here if there are any others...
383 if (MRI.hasOneDef(Reg))
386 // Add output dependence to the next nearest def of this vreg.
388 // Unless this definition is dead, the output dependence should be
389 // transitively redundant with antidependencies from this definition's
390 // uses. We're conservative for now until we have a way to guarantee the uses
391 // are not eliminated sometime during scheduling. The output dependence edge
392 // is also useful if output latency exceeds def-use latency.
393 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
394 if (DefI == VRegDefs.end())
395 VRegDefs.insert(VReg2SUnit(Reg, SU));
397 SUnit *DefSU = DefI->SU;
398 if (DefSU != SU && DefSU != &ExitSU) {
399 SDep Dep(SU, SDep::Output, Reg);
400 unsigned OutLatency =
401 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr());
402 Dep.setMinLatency(OutLatency);
403 Dep.setLatency(OutLatency);
410 /// addVRegUseDeps - Add a register data dependency if the instruction that
411 /// defines the virtual register used at OperIdx is mapped to an SUnit. Add a
412 /// register antidependency from this SUnit to instructions that occur later in
413 /// the same scheduling region if they write the virtual register.
415 /// TODO: Handle ExitSU "uses" properly.
416 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
417 MachineInstr *MI = SU->getInstr();
418 unsigned Reg = MI->getOperand(OperIdx).getReg();
420 // Lookup this operand's reaching definition.
421 assert(LIS && "vreg dependencies requires LiveIntervals");
422 LiveRangeQuery LRQ(LIS->getInterval(Reg), LIS->getInstructionIndex(MI));
423 VNInfo *VNI = LRQ.valueIn();
425 // VNI will be valid because MachineOperand::readsReg() is checked by caller.
426 assert(VNI && "No value to read by operand");
427 MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def);
428 // Phis and other noninstructions (after coalescing) have a NULL Def.
430 SUnit *DefSU = getSUnit(Def);
432 // The reaching Def lives within this scheduling region.
433 // Create a data dependence.
434 SDep dep(DefSU, SDep::Data, Reg);
435 // Adjust the dependence latency using operand def/use information, then
436 // allow the target to perform its own adjustments.
437 int DefOp = Def->findRegisterDefOperandIdx(Reg);
439 SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx, false));
441 SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx, true));
443 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
444 ST.adjustSchedDependency(DefSU, SU, const_cast<SDep &>(dep));
449 // Add antidependence to the following def of the vreg it uses.
450 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
451 if (DefI != VRegDefs.end() && DefI->SU != SU)
452 DefI->SU->addPred(SDep(SU, SDep::Anti, Reg));
455 /// Return true if MI is an instruction we are unable to reason about
456 /// (like a call or something with unmodeled side effects).
457 static inline bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) {
458 if (MI->isCall() || MI->hasUnmodeledSideEffects() ||
459 (MI->hasOrderedMemoryRef() &&
460 (!MI->mayLoad() || !MI->isInvariantLoad(AA))))
465 // This MI might have either incomplete info, or known to be unsafe
466 // to deal with (i.e. volatile object).
467 static inline bool isUnsafeMemoryObject(MachineInstr *MI,
468 const MachineFrameInfo *MFI) {
469 if (!MI || MI->memoperands_empty())
471 // We purposefully do no check for hasOneMemOperand() here
472 // in hope to trigger an assert downstream in order to
473 // finish implementation.
474 if ((*MI->memoperands_begin())->isVolatile() ||
475 MI->hasUnmodeledSideEffects())
477 const Value *V = (*MI->memoperands_begin())->getValue();
481 SmallVector<Value *, 4> Objs;
482 getUnderlyingObjects(V, Objs);
483 for (SmallVector<Value *, 4>::iterator I = Objs.begin(),
484 IE = Objs.end(); I != IE; ++I) {
487 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
488 // Similarly to getUnderlyingObjectForInstr:
489 // For now, ignore PseudoSourceValues which may alias LLVM IR values
490 // because the code that uses this function has no way to cope with
492 if (PSV->isAliased(MFI))
496 // Does this pointer refer to a distinct and identifiable object?
497 if (!isIdentifiedObject(V))
504 /// This returns true if the two MIs need a chain edge betwee them.
505 /// If these are not even memory operations, we still may need
506 /// chain deps between them. The question really is - could
507 /// these two MIs be reordered during scheduling from memory dependency
509 static bool MIsNeedChainEdge(AliasAnalysis *AA, const MachineFrameInfo *MFI,
512 // Cover a trivial case - no edge is need to itself.
516 if (isUnsafeMemoryObject(MIa, MFI) || isUnsafeMemoryObject(MIb, MFI))
519 // If we are dealing with two "normal" loads, we do not need an edge
520 // between them - they could be reordered.
521 if (!MIa->mayStore() && !MIb->mayStore())
524 // To this point analysis is generic. From here on we do need AA.
528 MachineMemOperand *MMOa = *MIa->memoperands_begin();
529 MachineMemOperand *MMOb = *MIb->memoperands_begin();
531 // FIXME: Need to handle multiple memory operands to support all targets.
532 if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand())
533 llvm_unreachable("Multiple memory operands.");
535 // The following interface to AA is fashioned after DAGCombiner::isAlias
536 // and operates with MachineMemOperand offset with some important
538 // - LLVM fundamentally assumes flat address spaces.
539 // - MachineOperand offset can *only* result from legalization and
540 // cannot affect queries other than the trivial case of overlap
542 // - These offsets never wrap and never step outside
543 // of allocated objects.
544 // - There should never be any negative offsets here.
546 // FIXME: Modify API to hide this math from "user"
547 // FIXME: Even before we go to AA we can reason locally about some
548 // memory objects. It can save compile time, and possibly catch some
549 // corner cases not currently covered.
551 assert ((MMOa->getOffset() >= 0) && "Negative MachineMemOperand offset");
552 assert ((MMOb->getOffset() >= 0) && "Negative MachineMemOperand offset");
554 int64_t MinOffset = std::min(MMOa->getOffset(), MMOb->getOffset());
555 int64_t Overlapa = MMOa->getSize() + MMOa->getOffset() - MinOffset;
556 int64_t Overlapb = MMOb->getSize() + MMOb->getOffset() - MinOffset;
558 AliasAnalysis::AliasResult AAResult = AA->alias(
559 AliasAnalysis::Location(MMOa->getValue(), Overlapa,
560 MMOa->getTBAAInfo()),
561 AliasAnalysis::Location(MMOb->getValue(), Overlapb,
562 MMOb->getTBAAInfo()));
564 return (AAResult != AliasAnalysis::NoAlias);
567 /// This recursive function iterates over chain deps of SUb looking for
568 /// "latest" node that needs a chain edge to SUa.
570 iterateChainSucc(AliasAnalysis *AA, const MachineFrameInfo *MFI,
571 SUnit *SUa, SUnit *SUb, SUnit *ExitSU, unsigned *Depth,
572 SmallPtrSet<const SUnit*, 16> &Visited) {
573 if (!SUa || !SUb || SUb == ExitSU)
576 // Remember visited nodes.
577 if (!Visited.insert(SUb))
579 // If there is _some_ dependency already in place, do not
580 // descend any further.
581 // TODO: Need to make sure that if that dependency got eliminated or ignored
582 // for any reason in the future, we would not violate DAG topology.
583 // Currently it does not happen, but makes an implicit assumption about
584 // future implementation.
586 // Independently, if we encounter node that is some sort of global
587 // object (like a call) we already have full set of dependencies to it
588 // and we can stop descending.
589 if (SUa->isSucc(SUb) ||
590 isGlobalMemoryObject(AA, SUb->getInstr()))
593 // If we do need an edge, or we have exceeded depth budget,
594 // add that edge to the predecessors chain of SUb,
595 // and stop descending.
597 MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) {
598 SUb->addPred(SDep(SUa, SDep::MayAliasMem));
601 // Track current depth.
603 // Iterate over chain dependencies only.
604 for (SUnit::const_succ_iterator I = SUb->Succs.begin(), E = SUb->Succs.end();
607 iterateChainSucc (AA, MFI, SUa, I->getSUnit(), ExitSU, Depth, Visited);
611 /// This function assumes that "downward" from SU there exist
612 /// tail/leaf of already constructed DAG. It iterates downward and
613 /// checks whether SU can be aliasing any node dominated
615 static void adjustChainDeps(AliasAnalysis *AA, const MachineFrameInfo *MFI,
616 SUnit *SU, SUnit *ExitSU, std::set<SUnit *> &CheckList,
617 unsigned LatencyToLoad) {
621 SmallPtrSet<const SUnit*, 16> Visited;
624 for (std::set<SUnit *>::iterator I = CheckList.begin(), IE = CheckList.end();
628 if (MIsNeedChainEdge(AA, MFI, SU->getInstr(), (*I)->getInstr())) {
629 SDep Dep(SU, SDep::MayAliasMem);
630 Dep.setLatency(((*I)->getInstr()->mayLoad()) ? LatencyToLoad : 0);
633 // Now go through all the chain successors and iterate from them.
634 // Keep track of visited nodes.
635 for (SUnit::const_succ_iterator J = (*I)->Succs.begin(),
636 JE = (*I)->Succs.end(); J != JE; ++J)
638 iterateChainSucc (AA, MFI, SU, J->getSUnit(),
639 ExitSU, &Depth, Visited);
643 /// Check whether two objects need a chain edge, if so, add it
644 /// otherwise remember the rejected SU.
646 void addChainDependency (AliasAnalysis *AA, const MachineFrameInfo *MFI,
647 SUnit *SUa, SUnit *SUb,
648 std::set<SUnit *> &RejectList,
649 unsigned TrueMemOrderLatency = 0,
650 bool isNormalMemory = false) {
651 // If this is a false dependency,
652 // do not add the edge, but rememeber the rejected node.
653 if (!EnableAASchedMI ||
654 MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) {
655 SDep Dep(SUa, isNormalMemory ? SDep::MayAliasMem : SDep::Barrier);
656 Dep.setLatency(TrueMemOrderLatency);
660 // Duplicate entries should be ignored.
661 RejectList.insert(SUb);
662 DEBUG(dbgs() << "\tReject chain dep between SU("
663 << SUa->NodeNum << ") and SU("
664 << SUb->NodeNum << ")\n");
668 /// Create an SUnit for each real instruction, numbered in top-down toplological
669 /// order. The instruction order A < B, implies that no edge exists from B to A.
671 /// Map each real instruction to its SUnit.
673 /// After initSUnits, the SUnits vector cannot be resized and the scheduler may
674 /// hang onto SUnit pointers. We may relax this in the future by using SUnit IDs
675 /// instead of pointers.
677 /// MachineScheduler relies on initSUnits numbering the nodes by their order in
678 /// the original instruction list.
679 void ScheduleDAGInstrs::initSUnits() {
680 // We'll be allocating one SUnit for each real instruction in the region,
681 // which is contained within a basic block.
682 SUnits.reserve(BB->size());
684 for (MachineBasicBlock::iterator I = RegionBegin; I != RegionEnd; ++I) {
685 MachineInstr *MI = I;
686 if (MI->isDebugValue())
689 SUnit *SU = newSUnit(MI);
692 SU->isCall = MI->isCall();
693 SU->isCommutable = MI->isCommutable();
695 // Assign the Latency field of SU using target-provided information.
696 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
700 /// If RegPressure is non null, compute register pressure as a side effect. The
701 /// DAG builder is an efficient place to do it because it already visits
703 void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
704 RegPressureTracker *RPTracker) {
705 // Create an SUnit for each real instruction.
708 // We build scheduling units by walking a block's instruction list from bottom
711 // Remember where a generic side-effecting instruction is as we procede.
712 SUnit *BarrierChain = 0, *AliasChain = 0;
714 // Memory references to specific known memory locations are tracked
715 // so that they can be given more precise dependencies. We track
716 // separately the known memory locations that may alias and those
717 // that are known not to alias
718 MapVector<const Value *, SUnit *> AliasMemDefs, NonAliasMemDefs;
719 MapVector<const Value *, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses;
720 std::set<SUnit*> RejectMemNodes;
722 // Remove any stale debug info; sometimes BuildSchedGraph is called again
723 // without emitting the info from the previous call.
725 FirstDbgValue = NULL;
727 assert(Defs.empty() && Uses.empty() &&
728 "Only BuildGraph should update Defs/Uses");
729 Defs.setRegLimit(TRI->getNumRegs());
730 Uses.setRegLimit(TRI->getNumRegs());
732 assert(VRegDefs.empty() && "Only BuildSchedGraph may access VRegDefs");
733 // FIXME: Allow SparseSet to reserve space for the creation of virtual
734 // registers during scheduling. Don't artificially inflate the Universe
735 // because we want to assert that vregs are not created during DAG building.
736 VRegDefs.setUniverse(MRI.getNumVirtRegs());
738 // Model data dependencies between instructions being scheduled and the
740 addSchedBarrierDeps();
742 // Walk the list of instructions, from bottom moving up.
743 MachineInstr *DbgMI = NULL;
744 for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
746 MachineInstr *MI = prior(MII);
748 DbgValues.push_back(std::make_pair(DbgMI, MI));
752 if (MI->isDebugValue()) {
758 assert(RPTracker->getPos() == prior(MII) && "RPTracker can't find MI");
761 assert((!MI->isTerminator() || CanHandleTerminators) && !MI->isLabel() &&
762 "Cannot schedule terminators or labels!");
764 SUnit *SU = MISUnitMap[MI];
765 assert(SU && "No SUnit mapped to this MI");
767 // Add register-based dependencies (data, anti, and output).
768 bool HasVRegDef = false;
769 for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
770 const MachineOperand &MO = MI->getOperand(j);
771 if (!MO.isReg()) continue;
772 unsigned Reg = MO.getReg();
773 if (Reg == 0) continue;
775 if (TRI->isPhysicalRegister(Reg))
776 addPhysRegDeps(SU, j);
778 assert(!IsPostRA && "Virtual register encountered!");
781 addVRegDefDeps(SU, j);
783 else if (MO.readsReg()) // ignore undef operands
784 addVRegUseDeps(SU, j);
787 // If we haven't seen any uses in this scheduling region, create a
788 // dependence edge to ExitSU to model the live-out latency. This is required
789 // for vreg defs with no in-region use, and prefetches with no vreg def.
791 // FIXME: NumDataSuccs would be more precise than NumSuccs here. This
792 // check currently relies on being called before adding chain deps.
793 if (SU->NumSuccs == 0 && SU->Latency > 1
794 && (HasVRegDef || MI->mayLoad())) {
795 SDep Dep(SU, SDep::Artificial);
796 Dep.setLatency(SU->Latency - 1);
800 // Add chain dependencies.
801 // Chain dependencies used to enforce memory order should have
802 // latency of 0 (except for true dependency of Store followed by
803 // aliased Load... we estimate that with a single cycle of latency
804 // assuming the hardware will bypass)
805 // Note that isStoreToStackSlot and isLoadFromStackSLot are not usable
806 // after stack slots are lowered to actual addresses.
807 // TODO: Use an AliasAnalysis and do real alias-analysis queries, and
808 // produce more precise dependence information.
809 unsigned TrueMemOrderLatency = MI->mayStore() ? 1 : 0;
810 if (isGlobalMemoryObject(AA, MI)) {
811 // Be conservative with these and add dependencies on all memory
812 // references, even those that are known to not alias.
813 for (MapVector<const Value *, SUnit *>::iterator I =
814 NonAliasMemDefs.begin(), E = NonAliasMemDefs.end(); I != E; ++I) {
815 I->second->addPred(SDep(SU, SDep::Barrier));
817 for (MapVector<const Value *, std::vector<SUnit *> >::iterator I =
818 NonAliasMemUses.begin(), E = NonAliasMemUses.end(); I != E; ++I) {
819 for (unsigned i = 0, e = I->second.size(); i != e; ++i) {
820 SDep Dep(SU, SDep::Barrier);
821 Dep.setLatency(TrueMemOrderLatency);
822 I->second[i]->addPred(Dep);
825 // Add SU to the barrier chain.
827 BarrierChain->addPred(SDep(SU, SDep::Barrier));
829 // This is a barrier event that acts as a pivotal node in the DAG,
830 // so it is safe to clear list of exposed nodes.
831 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
832 TrueMemOrderLatency);
833 RejectMemNodes.clear();
834 NonAliasMemDefs.clear();
835 NonAliasMemUses.clear();
839 // Chain all possibly aliasing memory references though SU.
841 unsigned ChainLatency = 0;
842 if (AliasChain->getInstr()->mayLoad())
843 ChainLatency = TrueMemOrderLatency;
844 addChainDependency(AA, MFI, SU, AliasChain, RejectMemNodes,
848 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
849 addChainDependency(AA, MFI, SU, PendingLoads[k], RejectMemNodes,
850 TrueMemOrderLatency);
851 for (MapVector<const Value *, SUnit *>::iterator I = AliasMemDefs.begin(),
852 E = AliasMemDefs.end(); I != E; ++I)
853 addChainDependency(AA, MFI, SU, I->second, RejectMemNodes);
854 for (MapVector<const Value *, std::vector<SUnit *> >::iterator I =
855 AliasMemUses.begin(), E = AliasMemUses.end(); I != E; ++I) {
856 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
857 addChainDependency(AA, MFI, SU, I->second[i], RejectMemNodes,
858 TrueMemOrderLatency);
860 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
861 TrueMemOrderLatency);
862 PendingLoads.clear();
863 AliasMemDefs.clear();
864 AliasMemUses.clear();
865 } else if (MI->mayStore()) {
866 SmallVector<std::pair<const Value *, bool>, 4> Objs;
867 getUnderlyingObjectsForInstr(MI, MFI, Objs);
870 // Treat all other stores conservatively.
871 goto new_alias_chain;
874 bool MayAlias = false;
875 for (SmallVector<std::pair<const Value *, bool>, 4>::iterator
876 K = Objs.begin(), KE = Objs.end(); K != KE; ++K) {
877 const Value *V = K->first;
878 bool ThisMayAlias = K->second;
882 // A store to a specific PseudoSourceValue. Add precise dependencies.
883 // Record the def in MemDefs, first adding a dep if there is
885 MapVector<const Value *, SUnit *>::iterator I =
886 ((ThisMayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
887 MapVector<const Value *, SUnit *>::iterator IE =
888 ((ThisMayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
890 addChainDependency(AA, MFI, SU, I->second, RejectMemNodes, 0, true);
894 AliasMemDefs[V] = SU;
896 NonAliasMemDefs[V] = SU;
898 // Handle the uses in MemUses, if there are any.
899 MapVector<const Value *, std::vector<SUnit *> >::iterator J =
900 ((ThisMayAlias) ? AliasMemUses.find(V) : NonAliasMemUses.find(V));
901 MapVector<const Value *, std::vector<SUnit *> >::iterator JE =
902 ((ThisMayAlias) ? AliasMemUses.end() : NonAliasMemUses.end());
904 for (unsigned i = 0, e = J->second.size(); i != e; ++i)
905 addChainDependency(AA, MFI, SU, J->second[i], RejectMemNodes,
906 TrueMemOrderLatency, true);
911 // Add dependencies from all the PendingLoads, i.e. loads
912 // with no underlying object.
913 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
914 addChainDependency(AA, MFI, SU, PendingLoads[k], RejectMemNodes,
915 TrueMemOrderLatency);
916 // Add dependence on alias chain, if needed.
918 addChainDependency(AA, MFI, SU, AliasChain, RejectMemNodes);
919 // But we also should check dependent instructions for the
921 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
922 TrueMemOrderLatency);
924 // Add dependence on barrier chain, if needed.
925 // There is no point to check aliasing on barrier event. Even if
926 // SU and barrier _could_ be reordered, they should not. In addition,
927 // we have lost all RejectMemNodes below barrier.
929 BarrierChain->addPred(SDep(SU, SDep::Barrier));
931 if (!ExitSU.isPred(SU))
932 // Push store's up a bit to avoid them getting in between cmp
934 ExitSU.addPred(SDep(SU, SDep::Artificial));
935 } else if (MI->mayLoad()) {
936 bool MayAlias = true;
937 if (MI->isInvariantLoad(AA)) {
938 // Invariant load, no chain dependencies needed!
940 SmallVector<std::pair<const Value *, bool>, 4> Objs;
941 getUnderlyingObjectsForInstr(MI, MFI, Objs);
944 // A load with no underlying object. Depend on all
945 // potentially aliasing stores.
946 for (MapVector<const Value *, SUnit *>::iterator I =
947 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I)
948 addChainDependency(AA, MFI, SU, I->second, RejectMemNodes);
950 PendingLoads.push_back(SU);
956 for (SmallVector<std::pair<const Value *, bool>, 4>::iterator
957 J = Objs.begin(), JE = Objs.end(); J != JE; ++J) {
958 const Value *V = J->first;
959 bool ThisMayAlias = J->second;
964 // A load from a specific PseudoSourceValue. Add precise dependencies.
965 MapVector<const Value *, SUnit *>::iterator I =
966 ((ThisMayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
967 MapVector<const Value *, SUnit *>::iterator IE =
968 ((ThisMayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
970 addChainDependency(AA, MFI, SU, I->second, RejectMemNodes, 0, true);
972 AliasMemUses[V].push_back(SU);
974 NonAliasMemUses[V].push_back(SU);
977 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes, /*Latency=*/0);
978 // Add dependencies on alias and barrier chains, if needed.
979 if (MayAlias && AliasChain)
980 addChainDependency(AA, MFI, SU, AliasChain, RejectMemNodes);
982 BarrierChain->addPred(SDep(SU, SDep::Barrier));
987 FirstDbgValue = DbgMI;
992 PendingLoads.clear();
995 void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
996 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
997 SU->getInstr()->dump();
1001 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
1003 raw_string_ostream oss(s);
1006 else if (SU == &ExitSU)
1009 SU->getInstr()->print(oss);
1013 /// Return the basic block label. It is not necessarilly unique because a block
1014 /// contains multiple scheduling regions. But it is fine for visualization.
1015 std::string ScheduleDAGInstrs::getDAGName() const {
1016 return "dag." + BB->getFullName();
1019 //===----------------------------------------------------------------------===//
1020 // SchedDFSResult Implementation
1021 //===----------------------------------------------------------------------===//
1024 /// \brief Internal state used to compute SchedDFSResult.
1025 class SchedDFSImpl {
1028 /// Join DAG nodes into equivalence classes by their subtree.
1029 IntEqClasses SubtreeClasses;
1030 /// List PredSU, SuccSU pairs that represent data edges between subtrees.
1031 std::vector<std::pair<const SUnit*, const SUnit*> > ConnectionPairs;
1034 SchedDFSImpl(SchedDFSResult &r): R(r), SubtreeClasses(R.DFSData.size()) {}
1036 /// SubtreID is initialized to zero, set to itself to flag the root of a
1037 /// subtree, set to the parent to indicate an interior node,
1038 /// then set to a representative subtree ID during finalization.
1039 bool isVisited(const SUnit *SU) const {
1040 return R.DFSData[SU->NodeNum].SubtreeID;
1043 /// Initialize this node's instruction count. We don't need to flag the node
1044 /// visited until visitPostorder because the DAG cannot have cycles.
1045 void visitPreorder(const SUnit *SU) {
1046 R.DFSData[SU->NodeNum].InstrCount = SU->getInstr()->isTransient() ? 0 : 1;
1049 /// Mark this node as either the root of a subtree or an interior
1050 /// node. Increment the parent node's instruction count.
1051 void visitPostorder(const SUnit *SU, const SDep *PredDep, const SUnit *Parent) {
1052 R.DFSData[SU->NodeNum].SubtreeID = SU->NodeNum;
1054 // Join the child to its parent if they are connected via data dependence
1055 // and do not exceed the limit.
1056 if (!Parent || PredDep->getKind() != SDep::Data)
1059 unsigned PredCnt = R.DFSData[SU->NodeNum].InstrCount;
1060 if (PredCnt > R.SubtreeLimit)
1063 R.DFSData[SU->NodeNum].SubtreeID = Parent->NodeNum;
1065 // Add the recently finished predecessor's bottom-up descendent count.
1066 R.DFSData[Parent->NodeNum].InstrCount += PredCnt;
1067 SubtreeClasses.join(Parent->NodeNum, SU->NodeNum);
1070 /// Determine whether the DFS cross edge should be considered a subtree edge
1071 /// or a connection between subtrees.
1072 void visitCross(const SDep &PredDep, const SUnit *Succ) {
1073 if (PredDep.getKind() == SDep::Data) {
1074 // If this is a cross edge to a root, join the subtrees. This happens when
1075 // the root was first reached by a non-data dependence.
1076 unsigned NodeNum = PredDep.getSUnit()->NodeNum;
1077 unsigned PredCnt = R.DFSData[NodeNum].InstrCount;
1078 if (R.DFSData[NodeNum].SubtreeID == NodeNum && PredCnt < R.SubtreeLimit) {
1079 R.DFSData[NodeNum].SubtreeID = Succ->NodeNum;
1080 R.DFSData[Succ->NodeNum].InstrCount += PredCnt;
1081 SubtreeClasses.join(Succ->NodeNum, NodeNum);
1085 ConnectionPairs.push_back(std::make_pair(PredDep.getSUnit(), Succ));
1088 /// Set each node's subtree ID to the representative ID and record connections
1091 SubtreeClasses.compress();
1092 R.SubtreeConnections.resize(SubtreeClasses.getNumClasses());
1093 R.SubtreeConnectLevels.resize(SubtreeClasses.getNumClasses());
1094 DEBUG(dbgs() << R.getNumSubtrees() << " subtrees:\n");
1095 for (unsigned Idx = 0, End = R.DFSData.size(); Idx != End; ++Idx) {
1096 R.DFSData[Idx].SubtreeID = SubtreeClasses[Idx];
1097 DEBUG(dbgs() << " SU(" << Idx << ") in tree "
1098 << R.DFSData[Idx].SubtreeID << '\n');
1100 for (std::vector<std::pair<const SUnit*, const SUnit*> >::const_iterator
1101 I = ConnectionPairs.begin(), E = ConnectionPairs.end();
1103 unsigned PredTree = SubtreeClasses[I->first->NodeNum];
1104 unsigned SuccTree = SubtreeClasses[I->second->NodeNum];
1105 if (PredTree == SuccTree)
1107 unsigned Depth = I->first->getDepth();
1108 addConnection(PredTree, SuccTree, Depth);
1109 addConnection(SuccTree, PredTree, Depth);
1114 /// Called by finalize() to record a connection between trees.
1115 void addConnection(unsigned FromTree, unsigned ToTree, unsigned Depth) {
1119 SmallVectorImpl<SchedDFSResult::Connection> &Connections =
1120 R.SubtreeConnections[FromTree];
1121 for (SmallVectorImpl<SchedDFSResult::Connection>::iterator
1122 I = Connections.begin(), E = Connections.end(); I != E; ++I) {
1123 if (I->TreeID == ToTree) {
1124 I->Level = std::max(I->Level, Depth);
1128 Connections.push_back(SchedDFSResult::Connection(ToTree, Depth));
1134 /// \brief Manage the stack used by a reverse depth-first search over the DAG.
1135 class SchedDAGReverseDFS {
1136 std::vector<std::pair<const SUnit*, SUnit::const_pred_iterator> > DFSStack;
1138 bool isComplete() const { return DFSStack.empty(); }
1140 void follow(const SUnit *SU) {
1141 DFSStack.push_back(std::make_pair(SU, SU->Preds.begin()));
1143 void advance() { ++DFSStack.back().second; }
1145 const SDep *backtrack() {
1146 DFSStack.pop_back();
1147 return DFSStack.empty() ? 0 : llvm::prior(DFSStack.back().second);
1150 const SUnit *getCurr() const { return DFSStack.back().first; }
1152 SUnit::const_pred_iterator getPred() const { return DFSStack.back().second; }
1154 SUnit::const_pred_iterator getPredEnd() const {
1155 return getCurr()->Preds.end();
1160 /// Compute an ILP metric for all nodes in the subDAG reachable via depth-first
1161 /// search from this root.
1162 void SchedDFSResult::compute(ArrayRef<SUnit *> Roots) {
1164 llvm_unreachable("Top-down ILP metric is unimplemnted");
1166 SchedDFSImpl Impl(*this);
1167 for (ArrayRef<const SUnit*>::const_iterator
1168 RootI = Roots.begin(), RootE = Roots.end(); RootI != RootE; ++RootI) {
1169 SchedDAGReverseDFS DFS;
1170 Impl.visitPreorder(*RootI);
1173 // Traverse the leftmost path as far as possible.
1174 while (DFS.getPred() != DFS.getPredEnd()) {
1175 const SDep &PredDep = *DFS.getPred();
1177 // If the pred is already valid, skip it. We may preorder visit a node
1178 // with InstrCount==0 more than once, but it won't affect heuristics
1179 // because we don't care about cross edges to leaf copies.
1180 if (Impl.isVisited(PredDep.getSUnit())) {
1181 Impl.visitCross(PredDep, DFS.getCurr());
1184 Impl.visitPreorder(PredDep.getSUnit());
1185 DFS.follow(PredDep.getSUnit());
1187 // Visit the top of the stack in postorder and backtrack.
1188 const SUnit *Child = DFS.getCurr();
1189 const SDep *PredDep = DFS.backtrack();
1190 Impl.visitPostorder(Child, PredDep, PredDep ? DFS.getCurr() : 0);
1191 if (DFS.isComplete())
1198 /// The root of the given SubtreeID was just scheduled. For all subtrees
1199 /// connected to this tree, record the depth of the connection so that the
1200 /// nearest connected subtrees can be prioritized.
1201 void SchedDFSResult::scheduleTree(unsigned SubtreeID) {
1202 for (SmallVectorImpl<Connection>::const_iterator
1203 I = SubtreeConnections[SubtreeID].begin(),
1204 E = SubtreeConnections[SubtreeID].end(); I != E; ++I) {
1205 SubtreeConnectLevels[I->TreeID] =
1206 std::max(SubtreeConnectLevels[I->TreeID], I->Level);
1207 DEBUG(dbgs() << " Tree: " << I->TreeID
1208 << " @" << SubtreeConnectLevels[I->TreeID] << '\n');
1212 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1213 void ILPValue::print(raw_ostream &OS) const {
1214 OS << InstrCount << " / " << Length << " = ";
1218 OS << format("%g", ((double)InstrCount / Length));
1221 void ILPValue::dump() const {
1222 dbgs() << *this << '\n';
1227 raw_ostream &operator<<(raw_ostream &OS, const ILPValue &Val) {
1233 #endif // !NDEBUG || LLVM_ENABLE_DUMP