1 //===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the ScheduleDAGInstrs class, which implements re-scheduling
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "sched-instrs"
16 #include "llvm/Operator.h"
17 #include "llvm/Analysis/AliasAnalysis.h"
18 #include "llvm/Analysis/ValueTracking.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineMemOperand.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/CodeGen/RegisterPressure.h"
25 #include "llvm/CodeGen/ScheduleDAGILP.h"
26 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
27 #include "llvm/MC/MCInstrItineraries.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetRegisterInfo.h"
31 #include "llvm/Target/TargetSubtargetInfo.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/Format.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/ADT/MapVector.h"
37 #include "llvm/ADT/SmallSet.h"
38 #include "llvm/ADT/SmallPtrSet.h"
41 static cl::opt<bool> EnableAASchedMI("enable-aa-sched-mi", cl::Hidden,
42 cl::ZeroOrMore, cl::init(false),
43 cl::desc("Enable use of AA during MI GAD construction"));
45 ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
46 const MachineLoopInfo &mli,
47 const MachineDominatorTree &mdt,
50 : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()), LIS(lis),
51 IsPostRA(IsPostRAFlag), CanHandleTerminators(false), FirstDbgValue(0) {
52 assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
54 assert(!(IsPostRA && MRI.getNumVirtRegs()) &&
55 "Virtual registers must be removed prior to PostRA scheduling");
57 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
58 SchedModel.init(*ST.getSchedModel(), &ST, TII);
61 /// getUnderlyingObjectFromInt - This is the function that does the work of
62 /// looking through basic ptrtoint+arithmetic+inttoptr sequences.
63 static const Value *getUnderlyingObjectFromInt(const Value *V) {
65 if (const Operator *U = dyn_cast<Operator>(V)) {
66 // If we find a ptrtoint, we can transfer control back to the
67 // regular getUnderlyingObjectFromInt.
68 if (U->getOpcode() == Instruction::PtrToInt)
69 return U->getOperand(0);
70 // If we find an add of a constant or a multiplied value, it's
71 // likely that the other operand will lead us to the base
72 // object. We don't have to worry about the case where the
73 // object address is somehow being computed by the multiply,
74 // because our callers only care when the result is an
75 // identifiable object.
76 if (U->getOpcode() != Instruction::Add ||
77 (!isa<ConstantInt>(U->getOperand(1)) &&
78 Operator::getOpcode(U->getOperand(1)) != Instruction::Mul))
84 assert(V->getType()->isIntegerTy() && "Unexpected operand type!");
88 /// getUnderlyingObject - This is a wrapper around GetUnderlyingObject
89 /// and adds support for basic ptrtoint+arithmetic+inttoptr sequences.
90 static const Value *getUnderlyingObject(const Value *V) {
91 // First just call Value::getUnderlyingObject to let it do what it does.
93 V = GetUnderlyingObject(V);
94 // If it found an inttoptr, use special code to continue climing.
95 if (Operator::getOpcode(V) != Instruction::IntToPtr)
97 const Value *O = getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0));
98 // If that succeeded in finding a pointer, continue the search.
99 if (!O->getType()->isPointerTy())
106 /// getUnderlyingObjectForInstr - If this machine instr has memory reference
107 /// information and it can be tracked to a normal reference to a known
108 /// object, return the Value for that object. Otherwise return null.
109 static const Value *getUnderlyingObjectForInstr(const MachineInstr *MI,
110 const MachineFrameInfo *MFI,
113 if (!MI->hasOneMemOperand() ||
114 !(*MI->memoperands_begin())->getValue() ||
115 (*MI->memoperands_begin())->isVolatile())
118 const Value *V = (*MI->memoperands_begin())->getValue();
122 V = getUnderlyingObject(V);
123 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
124 // For now, ignore PseudoSourceValues which may alias LLVM IR values
125 // because the code that uses this function has no way to cope with
127 if (PSV->isAliased(MFI))
130 MayAlias = PSV->mayAlias(MFI);
134 if (isIdentifiedObject(V))
140 void ScheduleDAGInstrs::startBlock(MachineBasicBlock *bb) {
144 void ScheduleDAGInstrs::finishBlock() {
145 // Subclasses should no longer refer to the old block.
149 /// Initialize the map with the number of registers.
150 void Reg2SUnitsMap::setRegLimit(unsigned Limit) {
151 PhysRegSet.setUniverse(Limit);
152 SUnits.resize(Limit);
155 /// Clear the map without deallocating storage.
156 void Reg2SUnitsMap::clear() {
157 for (const_iterator I = reg_begin(), E = reg_end(); I != E; ++I) {
163 /// Initialize the DAG and common scheduler state for the current scheduling
164 /// region. This does not actually create the DAG, only clears it. The
165 /// scheduling driver may call BuildSchedGraph multiple times per scheduling
167 void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb,
168 MachineBasicBlock::iterator begin,
169 MachineBasicBlock::iterator end,
171 assert(bb == BB && "startBlock should set BB");
177 ScheduleDAG::clearDAG();
180 /// Close the current scheduling region. Don't clear any state in case the
181 /// driver wants to refer to the previous scheduling region.
182 void ScheduleDAGInstrs::exitRegion() {
186 /// addSchedBarrierDeps - Add dependencies from instructions in the current
187 /// list of instructions being scheduled to scheduling barrier by adding
188 /// the exit SU to the register defs and use list. This is because we want to
189 /// make sure instructions which define registers that are either used by
190 /// the terminator or are live-out are properly scheduled. This is
191 /// especially important when the definition latency of the return value(s)
192 /// are too high to be hidden by the branch or when the liveout registers
193 /// used by instructions in the fallthrough block.
194 void ScheduleDAGInstrs::addSchedBarrierDeps() {
195 MachineInstr *ExitMI = RegionEnd != BB->end() ? &*RegionEnd : 0;
196 ExitSU.setInstr(ExitMI);
197 bool AllDepKnown = ExitMI &&
198 (ExitMI->isCall() || ExitMI->isBarrier());
199 if (ExitMI && AllDepKnown) {
200 // If it's a call or a barrier, add dependencies on the defs and uses of
202 for (unsigned i = 0, e = ExitMI->getNumOperands(); i != e; ++i) {
203 const MachineOperand &MO = ExitMI->getOperand(i);
204 if (!MO.isReg() || MO.isDef()) continue;
205 unsigned Reg = MO.getReg();
206 if (Reg == 0) continue;
208 if (TRI->isPhysicalRegister(Reg))
209 Uses[Reg].push_back(PhysRegSUOper(&ExitSU, -1));
211 assert(!IsPostRA && "Virtual register encountered after regalloc.");
212 addVRegUseDeps(&ExitSU, i);
216 // For others, e.g. fallthrough, conditional branch, assume the exit
217 // uses all the registers that are livein to the successor blocks.
218 assert(Uses.empty() && "Uses in set before adding deps?");
219 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
220 SE = BB->succ_end(); SI != SE; ++SI)
221 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
222 E = (*SI)->livein_end(); I != E; ++I) {
224 if (!Uses.contains(Reg))
225 Uses[Reg].push_back(PhysRegSUOper(&ExitSU, -1));
230 /// MO is an operand of SU's instruction that defines a physical register. Add
231 /// data dependencies from SU to any uses of the physical register.
232 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
233 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
234 assert(MO.isDef() && "expect physreg def");
236 // Ask the target if address-backscheduling is desirable, and if so how much.
237 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
239 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
240 Alias.isValid(); ++Alias) {
241 if (!Uses.contains(*Alias))
243 std::vector<PhysRegSUOper> &UseList = Uses[*Alias];
244 for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
245 SUnit *UseSU = UseList[i].SU;
249 // Adjust the dependence latency using operand def/use information,
250 // then allow the target to perform its own adjustments.
251 int UseOp = UseList[i].OpIdx;
252 MachineInstr *RegUse = 0;
255 Dep = SDep(SU, SDep::Artificial);
257 Dep = SDep(SU, SDep::Data, *Alias);
258 RegUse = UseSU->getInstr();
260 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
261 RegUse, UseOp, /*FindMin=*/true));
264 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
265 RegUse, UseOp, /*FindMin=*/false));
267 ST.adjustSchedDependency(SU, UseSU, Dep);
273 /// addPhysRegDeps - Add register dependencies (data, anti, and output) from
274 /// this SUnit to following instructions in the same scheduling region that
275 /// depend the physical register referenced at OperIdx.
276 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
277 const MachineInstr *MI = SU->getInstr();
278 const MachineOperand &MO = MI->getOperand(OperIdx);
280 // Optionally add output and anti dependencies. For anti
281 // dependencies we use a latency of 0 because for a multi-issue
282 // target we want to allow the defining instruction to issue
283 // in the same cycle as the using instruction.
284 // TODO: Using a latency of 1 here for output dependencies assumes
285 // there's no cost for reusing registers.
286 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
287 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
288 Alias.isValid(); ++Alias) {
289 if (!Defs.contains(*Alias))
291 std::vector<PhysRegSUOper> &DefList = Defs[*Alias];
292 for (unsigned i = 0, e = DefList.size(); i != e; ++i) {
293 SUnit *DefSU = DefList[i].SU;
294 if (DefSU == &ExitSU)
297 (Kind != SDep::Output || !MO.isDead() ||
298 !DefSU->getInstr()->registerDefIsDead(*Alias))) {
299 if (Kind == SDep::Anti)
300 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias));
302 SDep Dep(SU, Kind, /*Reg=*/*Alias);
303 unsigned OutLatency =
304 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr());
305 Dep.setMinLatency(OutLatency);
306 Dep.setLatency(OutLatency);
314 // Either insert a new Reg2SUnits entry with an empty SUnits list, or
315 // retrieve the existing SUnits list for this register's uses.
316 // Push this SUnit on the use list.
317 Uses[MO.getReg()].push_back(PhysRegSUOper(SU, OperIdx));
320 addPhysRegDataDeps(SU, OperIdx);
322 // Either insert a new Reg2SUnits entry with an empty SUnits list, or
323 // retrieve the existing SUnits list for this register's defs.
324 std::vector<PhysRegSUOper> &DefList = Defs[MO.getReg()];
326 // clear this register's use list
327 if (Uses.contains(MO.getReg()))
328 Uses[MO.getReg()].clear();
333 // Calls will not be reordered because of chain dependencies (see
334 // below). Since call operands are dead, calls may continue to be added
335 // to the DefList making dependence checking quadratic in the size of
336 // the block. Instead, we leave only one call at the back of the
339 while (!DefList.empty() && DefList.back().SU->isCall)
342 // Defs are pushed in the order they are visited and never reordered.
343 DefList.push_back(PhysRegSUOper(SU, OperIdx));
347 /// addVRegDefDeps - Add register output and data dependencies from this SUnit
348 /// to instructions that occur later in the same scheduling region if they read
349 /// from or write to the virtual register defined at OperIdx.
351 /// TODO: Hoist loop induction variable increments. This has to be
352 /// reevaluated. Generally, IV scheduling should be done before coalescing.
353 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
354 const MachineInstr *MI = SU->getInstr();
355 unsigned Reg = MI->getOperand(OperIdx).getReg();
357 // Singly defined vregs do not have output/anti dependencies.
358 // The current operand is a def, so we have at least one.
359 // Check here if there are any others...
360 if (MRI.hasOneDef(Reg))
363 // Add output dependence to the next nearest def of this vreg.
365 // Unless this definition is dead, the output dependence should be
366 // transitively redundant with antidependencies from this definition's
367 // uses. We're conservative for now until we have a way to guarantee the uses
368 // are not eliminated sometime during scheduling. The output dependence edge
369 // is also useful if output latency exceeds def-use latency.
370 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
371 if (DefI == VRegDefs.end())
372 VRegDefs.insert(VReg2SUnit(Reg, SU));
374 SUnit *DefSU = DefI->SU;
375 if (DefSU != SU && DefSU != &ExitSU) {
376 SDep Dep(SU, SDep::Output, Reg);
377 unsigned OutLatency =
378 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr());
379 Dep.setMinLatency(OutLatency);
380 Dep.setLatency(OutLatency);
387 /// addVRegUseDeps - Add a register data dependency if the instruction that
388 /// defines the virtual register used at OperIdx is mapped to an SUnit. Add a
389 /// register antidependency from this SUnit to instructions that occur later in
390 /// the same scheduling region if they write the virtual register.
392 /// TODO: Handle ExitSU "uses" properly.
393 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
394 MachineInstr *MI = SU->getInstr();
395 unsigned Reg = MI->getOperand(OperIdx).getReg();
397 // Lookup this operand's reaching definition.
398 assert(LIS && "vreg dependencies requires LiveIntervals");
399 LiveRangeQuery LRQ(LIS->getInterval(Reg), LIS->getInstructionIndex(MI));
400 VNInfo *VNI = LRQ.valueIn();
402 // VNI will be valid because MachineOperand::readsReg() is checked by caller.
403 assert(VNI && "No value to read by operand");
404 MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def);
405 // Phis and other noninstructions (after coalescing) have a NULL Def.
407 SUnit *DefSU = getSUnit(Def);
409 // The reaching Def lives within this scheduling region.
410 // Create a data dependence.
411 SDep dep(DefSU, SDep::Data, Reg);
412 // Adjust the dependence latency using operand def/use information, then
413 // allow the target to perform its own adjustments.
414 int DefOp = Def->findRegisterDefOperandIdx(Reg);
416 SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx, false));
418 SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx, true));
420 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
421 ST.adjustSchedDependency(DefSU, SU, const_cast<SDep &>(dep));
426 // Add antidependence to the following def of the vreg it uses.
427 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
428 if (DefI != VRegDefs.end() && DefI->SU != SU)
429 DefI->SU->addPred(SDep(SU, SDep::Anti, Reg));
432 /// Return true if MI is an instruction we are unable to reason about
433 /// (like a call or something with unmodeled side effects).
434 static inline bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) {
435 if (MI->isCall() || MI->hasUnmodeledSideEffects() ||
436 (MI->hasOrderedMemoryRef() &&
437 (!MI->mayLoad() || !MI->isInvariantLoad(AA))))
442 // This MI might have either incomplete info, or known to be unsafe
443 // to deal with (i.e. volatile object).
444 static inline bool isUnsafeMemoryObject(MachineInstr *MI,
445 const MachineFrameInfo *MFI) {
446 if (!MI || MI->memoperands_empty())
448 // We purposefully do no check for hasOneMemOperand() here
449 // in hope to trigger an assert downstream in order to
450 // finish implementation.
451 if ((*MI->memoperands_begin())->isVolatile() ||
452 MI->hasUnmodeledSideEffects())
455 const Value *V = (*MI->memoperands_begin())->getValue();
459 V = getUnderlyingObject(V);
460 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
461 // Similarly to getUnderlyingObjectForInstr:
462 // For now, ignore PseudoSourceValues which may alias LLVM IR values
463 // because the code that uses this function has no way to cope with
465 if (PSV->isAliased(MFI))
468 // Does this pointer refer to a distinct and identifiable object?
469 if (!isIdentifiedObject(V))
475 /// This returns true if the two MIs need a chain edge betwee them.
476 /// If these are not even memory operations, we still may need
477 /// chain deps between them. The question really is - could
478 /// these two MIs be reordered during scheduling from memory dependency
480 static bool MIsNeedChainEdge(AliasAnalysis *AA, const MachineFrameInfo *MFI,
483 // Cover a trivial case - no edge is need to itself.
487 if (isUnsafeMemoryObject(MIa, MFI) || isUnsafeMemoryObject(MIb, MFI))
490 // If we are dealing with two "normal" loads, we do not need an edge
491 // between them - they could be reordered.
492 if (!MIa->mayStore() && !MIb->mayStore())
495 // To this point analysis is generic. From here on we do need AA.
499 MachineMemOperand *MMOa = *MIa->memoperands_begin();
500 MachineMemOperand *MMOb = *MIb->memoperands_begin();
502 // FIXME: Need to handle multiple memory operands to support all targets.
503 if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand())
504 llvm_unreachable("Multiple memory operands.");
506 // The following interface to AA is fashioned after DAGCombiner::isAlias
507 // and operates with MachineMemOperand offset with some important
509 // - LLVM fundamentally assumes flat address spaces.
510 // - MachineOperand offset can *only* result from legalization and
511 // cannot affect queries other than the trivial case of overlap
513 // - These offsets never wrap and never step outside
514 // of allocated objects.
515 // - There should never be any negative offsets here.
517 // FIXME: Modify API to hide this math from "user"
518 // FIXME: Even before we go to AA we can reason locally about some
519 // memory objects. It can save compile time, and possibly catch some
520 // corner cases not currently covered.
522 assert ((MMOa->getOffset() >= 0) && "Negative MachineMemOperand offset");
523 assert ((MMOb->getOffset() >= 0) && "Negative MachineMemOperand offset");
525 int64_t MinOffset = std::min(MMOa->getOffset(), MMOb->getOffset());
526 int64_t Overlapa = MMOa->getSize() + MMOa->getOffset() - MinOffset;
527 int64_t Overlapb = MMOb->getSize() + MMOb->getOffset() - MinOffset;
529 AliasAnalysis::AliasResult AAResult = AA->alias(
530 AliasAnalysis::Location(MMOa->getValue(), Overlapa,
531 MMOa->getTBAAInfo()),
532 AliasAnalysis::Location(MMOb->getValue(), Overlapb,
533 MMOb->getTBAAInfo()));
535 return (AAResult != AliasAnalysis::NoAlias);
538 /// This recursive function iterates over chain deps of SUb looking for
539 /// "latest" node that needs a chain edge to SUa.
541 iterateChainSucc(AliasAnalysis *AA, const MachineFrameInfo *MFI,
542 SUnit *SUa, SUnit *SUb, SUnit *ExitSU, unsigned *Depth,
543 SmallPtrSet<const SUnit*, 16> &Visited) {
544 if (!SUa || !SUb || SUb == ExitSU)
547 // Remember visited nodes.
548 if (!Visited.insert(SUb))
550 // If there is _some_ dependency already in place, do not
551 // descend any further.
552 // TODO: Need to make sure that if that dependency got eliminated or ignored
553 // for any reason in the future, we would not violate DAG topology.
554 // Currently it does not happen, but makes an implicit assumption about
555 // future implementation.
557 // Independently, if we encounter node that is some sort of global
558 // object (like a call) we already have full set of dependencies to it
559 // and we can stop descending.
560 if (SUa->isSucc(SUb) ||
561 isGlobalMemoryObject(AA, SUb->getInstr()))
564 // If we do need an edge, or we have exceeded depth budget,
565 // add that edge to the predecessors chain of SUb,
566 // and stop descending.
568 MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) {
569 SUb->addPred(SDep(SUa, SDep::MayAliasMem));
572 // Track current depth.
574 // Iterate over chain dependencies only.
575 for (SUnit::const_succ_iterator I = SUb->Succs.begin(), E = SUb->Succs.end();
578 iterateChainSucc (AA, MFI, SUa, I->getSUnit(), ExitSU, Depth, Visited);
582 /// This function assumes that "downward" from SU there exist
583 /// tail/leaf of already constructed DAG. It iterates downward and
584 /// checks whether SU can be aliasing any node dominated
586 static void adjustChainDeps(AliasAnalysis *AA, const MachineFrameInfo *MFI,
587 SUnit *SU, SUnit *ExitSU, std::set<SUnit *> &CheckList,
588 unsigned LatencyToLoad) {
592 SmallPtrSet<const SUnit*, 16> Visited;
595 for (std::set<SUnit *>::iterator I = CheckList.begin(), IE = CheckList.end();
599 if (MIsNeedChainEdge(AA, MFI, SU->getInstr(), (*I)->getInstr())) {
600 SDep Dep(SU, SDep::MayAliasMem);
601 Dep.setLatency(((*I)->getInstr()->mayLoad()) ? LatencyToLoad : 0);
604 // Now go through all the chain successors and iterate from them.
605 // Keep track of visited nodes.
606 for (SUnit::const_succ_iterator J = (*I)->Succs.begin(),
607 JE = (*I)->Succs.end(); J != JE; ++J)
609 iterateChainSucc (AA, MFI, SU, J->getSUnit(),
610 ExitSU, &Depth, Visited);
614 /// Check whether two objects need a chain edge, if so, add it
615 /// otherwise remember the rejected SU.
617 void addChainDependency (AliasAnalysis *AA, const MachineFrameInfo *MFI,
618 SUnit *SUa, SUnit *SUb,
619 std::set<SUnit *> &RejectList,
620 unsigned TrueMemOrderLatency = 0,
621 bool isNormalMemory = false) {
622 // If this is a false dependency,
623 // do not add the edge, but rememeber the rejected node.
624 if (!EnableAASchedMI ||
625 MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) {
626 SDep Dep(SUa, isNormalMemory ? SDep::MayAliasMem : SDep::Barrier);
627 Dep.setLatency(TrueMemOrderLatency);
631 // Duplicate entries should be ignored.
632 RejectList.insert(SUb);
633 DEBUG(dbgs() << "\tReject chain dep between SU("
634 << SUa->NodeNum << ") and SU("
635 << SUb->NodeNum << ")\n");
639 /// Create an SUnit for each real instruction, numbered in top-down toplological
640 /// order. The instruction order A < B, implies that no edge exists from B to A.
642 /// Map each real instruction to its SUnit.
644 /// After initSUnits, the SUnits vector cannot be resized and the scheduler may
645 /// hang onto SUnit pointers. We may relax this in the future by using SUnit IDs
646 /// instead of pointers.
648 /// MachineScheduler relies on initSUnits numbering the nodes by their order in
649 /// the original instruction list.
650 void ScheduleDAGInstrs::initSUnits() {
651 // We'll be allocating one SUnit for each real instruction in the region,
652 // which is contained within a basic block.
653 SUnits.reserve(BB->size());
655 for (MachineBasicBlock::iterator I = RegionBegin; I != RegionEnd; ++I) {
656 MachineInstr *MI = I;
657 if (MI->isDebugValue())
660 SUnit *SU = newSUnit(MI);
663 SU->isCall = MI->isCall();
664 SU->isCommutable = MI->isCommutable();
666 // Assign the Latency field of SU using target-provided information.
667 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
671 /// If RegPressure is non null, compute register pressure as a side effect. The
672 /// DAG builder is an efficient place to do it because it already visits
674 void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
675 RegPressureTracker *RPTracker) {
676 // Create an SUnit for each real instruction.
679 // We build scheduling units by walking a block's instruction list from bottom
682 // Remember where a generic side-effecting instruction is as we procede.
683 SUnit *BarrierChain = 0, *AliasChain = 0;
685 // Memory references to specific known memory locations are tracked
686 // so that they can be given more precise dependencies. We track
687 // separately the known memory locations that may alias and those
688 // that are known not to alias
689 MapVector<const Value *, SUnit *> AliasMemDefs, NonAliasMemDefs;
690 MapVector<const Value *, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses;
691 std::set<SUnit*> RejectMemNodes;
693 // Remove any stale debug info; sometimes BuildSchedGraph is called again
694 // without emitting the info from the previous call.
696 FirstDbgValue = NULL;
698 assert(Defs.empty() && Uses.empty() &&
699 "Only BuildGraph should update Defs/Uses");
700 Defs.setRegLimit(TRI->getNumRegs());
701 Uses.setRegLimit(TRI->getNumRegs());
703 assert(VRegDefs.empty() && "Only BuildSchedGraph may access VRegDefs");
704 // FIXME: Allow SparseSet to reserve space for the creation of virtual
705 // registers during scheduling. Don't artificially inflate the Universe
706 // because we want to assert that vregs are not created during DAG building.
707 VRegDefs.setUniverse(MRI.getNumVirtRegs());
709 // Model data dependencies between instructions being scheduled and the
711 addSchedBarrierDeps();
713 // Walk the list of instructions, from bottom moving up.
714 MachineInstr *PrevMI = NULL;
715 for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
717 MachineInstr *MI = prior(MII);
719 DbgValues.push_back(std::make_pair(PrevMI, MI));
723 if (MI->isDebugValue()) {
729 assert(RPTracker->getPos() == prior(MII) && "RPTracker can't find MI");
732 assert((!MI->isTerminator() || CanHandleTerminators) && !MI->isLabel() &&
733 "Cannot schedule terminators or labels!");
735 SUnit *SU = MISUnitMap[MI];
736 assert(SU && "No SUnit mapped to this MI");
738 // Add register-based dependencies (data, anti, and output).
739 for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
740 const MachineOperand &MO = MI->getOperand(j);
741 if (!MO.isReg()) continue;
742 unsigned Reg = MO.getReg();
743 if (Reg == 0) continue;
745 if (TRI->isPhysicalRegister(Reg))
746 addPhysRegDeps(SU, j);
748 assert(!IsPostRA && "Virtual register encountered!");
750 addVRegDefDeps(SU, j);
751 else if (MO.readsReg()) // ignore undef operands
752 addVRegUseDeps(SU, j);
756 // Add chain dependencies.
757 // Chain dependencies used to enforce memory order should have
758 // latency of 0 (except for true dependency of Store followed by
759 // aliased Load... we estimate that with a single cycle of latency
760 // assuming the hardware will bypass)
761 // Note that isStoreToStackSlot and isLoadFromStackSLot are not usable
762 // after stack slots are lowered to actual addresses.
763 // TODO: Use an AliasAnalysis and do real alias-analysis queries, and
764 // produce more precise dependence information.
765 unsigned TrueMemOrderLatency = MI->mayStore() ? 1 : 0;
766 if (isGlobalMemoryObject(AA, MI)) {
767 // Be conservative with these and add dependencies on all memory
768 // references, even those that are known to not alias.
769 for (MapVector<const Value *, SUnit *>::iterator I =
770 NonAliasMemDefs.begin(), E = NonAliasMemDefs.end(); I != E; ++I) {
771 I->second->addPred(SDep(SU, SDep::Barrier));
773 for (MapVector<const Value *, std::vector<SUnit *> >::iterator I =
774 NonAliasMemUses.begin(), E = NonAliasMemUses.end(); I != E; ++I) {
775 for (unsigned i = 0, e = I->second.size(); i != e; ++i) {
776 SDep Dep(SU, SDep::Barrier);
777 Dep.setLatency(TrueMemOrderLatency);
778 I->second[i]->addPred(Dep);
781 // Add SU to the barrier chain.
783 BarrierChain->addPred(SDep(SU, SDep::Barrier));
785 // This is a barrier event that acts as a pivotal node in the DAG,
786 // so it is safe to clear list of exposed nodes.
787 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
788 TrueMemOrderLatency);
789 RejectMemNodes.clear();
790 NonAliasMemDefs.clear();
791 NonAliasMemUses.clear();
795 // Chain all possibly aliasing memory references though SU.
797 unsigned ChainLatency = 0;
798 if (AliasChain->getInstr()->mayLoad())
799 ChainLatency = TrueMemOrderLatency;
800 addChainDependency(AA, MFI, SU, AliasChain, RejectMemNodes,
804 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
805 addChainDependency(AA, MFI, SU, PendingLoads[k], RejectMemNodes,
806 TrueMemOrderLatency);
807 for (MapVector<const Value *, SUnit *>::iterator I = AliasMemDefs.begin(),
808 E = AliasMemDefs.end(); I != E; ++I)
809 addChainDependency(AA, MFI, SU, I->second, RejectMemNodes);
810 for (MapVector<const Value *, std::vector<SUnit *> >::iterator I =
811 AliasMemUses.begin(), E = AliasMemUses.end(); I != E; ++I) {
812 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
813 addChainDependency(AA, MFI, SU, I->second[i], RejectMemNodes,
814 TrueMemOrderLatency);
816 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
817 TrueMemOrderLatency);
818 PendingLoads.clear();
819 AliasMemDefs.clear();
820 AliasMemUses.clear();
821 } else if (MI->mayStore()) {
822 bool MayAlias = true;
823 if (const Value *V = getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
824 // A store to a specific PseudoSourceValue. Add precise dependencies.
825 // Record the def in MemDefs, first adding a dep if there is
827 MapVector<const Value *, SUnit *>::iterator I =
828 ((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
829 MapVector<const Value *, SUnit *>::iterator IE =
830 ((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
832 addChainDependency(AA, MFI, SU, I->second, RejectMemNodes, 0, true);
836 AliasMemDefs[V] = SU;
838 NonAliasMemDefs[V] = SU;
840 // Handle the uses in MemUses, if there are any.
841 MapVector<const Value *, std::vector<SUnit *> >::iterator J =
842 ((MayAlias) ? AliasMemUses.find(V) : NonAliasMemUses.find(V));
843 MapVector<const Value *, std::vector<SUnit *> >::iterator JE =
844 ((MayAlias) ? AliasMemUses.end() : NonAliasMemUses.end());
846 for (unsigned i = 0, e = J->second.size(); i != e; ++i)
847 addChainDependency(AA, MFI, SU, J->second[i], RejectMemNodes,
848 TrueMemOrderLatency, true);
852 // Add dependencies from all the PendingLoads, i.e. loads
853 // with no underlying object.
854 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
855 addChainDependency(AA, MFI, SU, PendingLoads[k], RejectMemNodes,
856 TrueMemOrderLatency);
857 // Add dependence on alias chain, if needed.
859 addChainDependency(AA, MFI, SU, AliasChain, RejectMemNodes);
860 // But we also should check dependent instructions for the
862 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
863 TrueMemOrderLatency);
865 // Add dependence on barrier chain, if needed.
866 // There is no point to check aliasing on barrier event. Even if
867 // SU and barrier _could_ be reordered, they should not. In addition,
868 // we have lost all RejectMemNodes below barrier.
870 BarrierChain->addPred(SDep(SU, SDep::Barrier));
872 // Treat all other stores conservatively.
873 goto new_alias_chain;
876 if (!ExitSU.isPred(SU))
877 // Push store's up a bit to avoid them getting in between cmp
879 ExitSU.addPred(SDep(SU, SDep::Artificial));
880 } else if (MI->mayLoad()) {
881 bool MayAlias = true;
882 if (MI->isInvariantLoad(AA)) {
883 // Invariant load, no chain dependencies needed!
886 getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
887 // A load from a specific PseudoSourceValue. Add precise dependencies.
888 MapVector<const Value *, SUnit *>::iterator I =
889 ((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
890 MapVector<const Value *, SUnit *>::iterator IE =
891 ((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
893 addChainDependency(AA, MFI, SU, I->second, RejectMemNodes, 0, true);
895 AliasMemUses[V].push_back(SU);
897 NonAliasMemUses[V].push_back(SU);
899 // A load with no underlying object. Depend on all
900 // potentially aliasing stores.
901 for (MapVector<const Value *, SUnit *>::iterator I =
902 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I)
903 addChainDependency(AA, MFI, SU, I->second, RejectMemNodes);
905 PendingLoads.push_back(SU);
909 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes, /*Latency=*/0);
910 // Add dependencies on alias and barrier chains, if needed.
911 if (MayAlias && AliasChain)
912 addChainDependency(AA, MFI, SU, AliasChain, RejectMemNodes);
914 BarrierChain->addPred(SDep(SU, SDep::Barrier));
919 FirstDbgValue = PrevMI;
924 PendingLoads.clear();
927 void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
928 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
929 SU->getInstr()->dump();
933 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
935 raw_string_ostream oss(s);
938 else if (SU == &ExitSU)
941 SU->getInstr()->print(oss);
945 /// Return the basic block label. It is not necessarilly unique because a block
946 /// contains multiple scheduling regions. But it is fine for visualization.
947 std::string ScheduleDAGInstrs::getDAGName() const {
948 return "dag." + BB->getFullName();
952 /// \brief Manage the stack used by a reverse depth-first search over the DAG.
953 class SchedDAGReverseDFS {
954 std::vector<std::pair<const SUnit*, SUnit::const_pred_iterator> > DFSStack;
956 bool isComplete() const { return DFSStack.empty(); }
958 void follow(const SUnit *SU) {
959 DFSStack.push_back(std::make_pair(SU, SU->Preds.begin()));
961 void advance() { ++DFSStack.back().second; }
963 void backtrack() { DFSStack.pop_back(); }
965 const SUnit *getCurr() const { return DFSStack.back().first; }
967 SUnit::const_pred_iterator getPred() const { return DFSStack.back().second; }
969 SUnit::const_pred_iterator getPredEnd() const {
970 return getCurr()->Preds.end();
975 void ScheduleDAGILP::resize(unsigned NumSUnits) {
976 ILPValues.resize(NumSUnits);
979 ILPValue ScheduleDAGILP::getILP(const SUnit *SU) {
980 return ILPValues[SU->NodeNum];
983 // A leaf node has an ILP of 1/1.
984 static ILPValue initILP(const SUnit *SU) {
985 unsigned Cnt = SU->getInstr()->isTransient() ? 0 : 1;
986 return ILPValue(Cnt, 1 + SU->getDepth());
989 /// Compute an ILP metric for all nodes in the subDAG reachable via depth-first
990 /// search from this root.
991 void ScheduleDAGILP::computeILP(const SUnit *Root) {
993 llvm_unreachable("Top-down ILP metric is unimplemnted");
995 SchedDAGReverseDFS DFS;
996 // Mark a node visited by validating it.
997 ILPValues[Root->NodeNum] = initILP(Root);
1000 // Traverse the leftmost path as far as possible.
1001 while (DFS.getPred() != DFS.getPredEnd()) {
1002 const SUnit *PredSU = DFS.getPred()->getSUnit();
1004 // If the pred is already valid, skip it.
1005 if (ILPValues[PredSU->NodeNum].isValid())
1007 ILPValues[PredSU->NodeNum] = initILP(PredSU);
1010 // Visit the top of the stack in postorder and backtrack.
1011 unsigned PredCount = ILPValues[DFS.getCurr()->NodeNum].InstrCount;
1013 if (DFS.isComplete())
1015 // Add the recently finished predecessor's bottom-up descendent count.
1016 ILPValues[DFS.getCurr()->NodeNum].InstrCount += PredCount;
1020 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1021 void ILPValue::print(raw_ostream &OS) const {
1024 OS << InstrCount << " / " << Cycles << " = "
1025 << format("%g", ((double)InstrCount / Cycles));
1028 void ILPValue::dump() const {
1029 dbgs() << *this << '\n';
1034 raw_ostream &operator<<(raw_ostream &OS, const ILPValue &Val) {
1040 #endif // !NDEBUG || LLVM_ENABLE_DUMP