1 //===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the ScheduleDAGInstrs class, which implements re-scheduling
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "sched-instrs"
16 #include "ScheduleDAGInstrs.h"
17 #include "llvm/Operator.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/CodeGen/MachineFunctionPass.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Target/TargetRegisterInfo.h"
26 #include "llvm/Target/TargetSubtarget.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/SmallSet.h"
32 ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
33 const MachineLoopInfo &mli,
34 const MachineDominatorTree &mdt)
35 : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()),
36 InstrItins(mf.getTarget().getInstrItineraryData()),
37 Defs(TRI->getNumRegs()), Uses(TRI->getNumRegs()), LoopRegs(MLI, MDT) {
41 /// Run - perform scheduling.
43 void ScheduleDAGInstrs::Run(MachineBasicBlock *bb,
44 MachineBasicBlock::iterator begin,
45 MachineBasicBlock::iterator end,
49 InsertPosIndex = endcount;
51 ScheduleDAG::Run(bb, end);
54 /// getUnderlyingObjectFromInt - This is the function that does the work of
55 /// looking through basic ptrtoint+arithmetic+inttoptr sequences.
56 static const Value *getUnderlyingObjectFromInt(const Value *V) {
58 if (const Operator *U = dyn_cast<Operator>(V)) {
59 // If we find a ptrtoint, we can transfer control back to the
60 // regular getUnderlyingObjectFromInt.
61 if (U->getOpcode() == Instruction::PtrToInt)
62 return U->getOperand(0);
63 // If we find an add of a constant or a multiplied value, it's
64 // likely that the other operand will lead us to the base
65 // object. We don't have to worry about the case where the
66 // object address is somehow being computed by the multiply,
67 // because our callers only care when the result is an
68 // identifibale object.
69 if (U->getOpcode() != Instruction::Add ||
70 (!isa<ConstantInt>(U->getOperand(1)) &&
71 Operator::getOpcode(U->getOperand(1)) != Instruction::Mul))
77 assert(V->getType()->isIntegerTy() && "Unexpected operand type!");
81 /// getUnderlyingObject - This is a wrapper around Value::getUnderlyingObject
82 /// and adds support for basic ptrtoint+arithmetic+inttoptr sequences.
83 static const Value *getUnderlyingObject(const Value *V) {
84 // First just call Value::getUnderlyingObject to let it do what it does.
86 V = V->getUnderlyingObject();
87 // If it found an inttoptr, use special code to continue climing.
88 if (Operator::getOpcode(V) != Instruction::IntToPtr)
90 const Value *O = getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0));
91 // If that succeeded in finding a pointer, continue the search.
92 if (!O->getType()->isPointerTy())
99 /// getUnderlyingObjectForInstr - If this machine instr has memory reference
100 /// information and it can be tracked to a normal reference to a known
101 /// object, return the Value for that object. Otherwise return null.
102 static const Value *getUnderlyingObjectForInstr(const MachineInstr *MI,
103 const MachineFrameInfo *MFI,
106 if (!MI->hasOneMemOperand() ||
107 !(*MI->memoperands_begin())->getValue() ||
108 (*MI->memoperands_begin())->isVolatile())
111 const Value *V = (*MI->memoperands_begin())->getValue();
115 V = getUnderlyingObject(V);
116 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
117 // For now, ignore PseudoSourceValues which may alias LLVM IR values
118 // because the code that uses this function has no way to cope with
120 if (PSV->isAliased(MFI))
123 MayAlias = PSV->mayAlias(MFI);
127 if (isIdentifiedObject(V))
133 void ScheduleDAGInstrs::StartBlock(MachineBasicBlock *BB) {
134 if (MachineLoop *ML = MLI.getLoopFor(BB))
135 if (BB == ML->getLoopLatch()) {
136 MachineBasicBlock *Header = ML->getHeader();
137 for (MachineBasicBlock::livein_iterator I = Header->livein_begin(),
138 E = Header->livein_end(); I != E; ++I)
139 LoopLiveInRegs.insert(*I);
140 LoopRegs.VisitLoop(ML);
144 /// AddSchedBarrierDeps - Add dependencies from instructions in the current
145 /// list of instructions being scheduled to scheduling barrier by adding
146 /// the exit SU to the register defs and use list. This is because we want to
147 /// make sure instructions which define registers that are either used by
148 /// the terminator or are live-out are properly scheduled. This is
149 /// especially important when the definition latency of the return value(s)
150 /// are too high to be hidden by the branch or when the liveout registers
151 /// used by instructions in the fallthrough block.
152 void ScheduleDAGInstrs::AddSchedBarrierDeps() {
153 MachineInstr *ExitMI = InsertPos != BB->end() ? &*InsertPos : 0;
154 ExitSU.setInstr(ExitMI);
155 bool AllDepKnown = ExitMI &&
156 (ExitMI->getDesc().isCall() || ExitMI->getDesc().isBarrier());
157 if (ExitMI && AllDepKnown) {
158 // If it's a call or a barrier, add dependencies on the defs and uses of
160 for (unsigned i = 0, e = ExitMI->getNumOperands(); i != e; ++i) {
161 const MachineOperand &MO = ExitMI->getOperand(i);
162 if (!MO.isReg() || MO.isDef()) continue;
163 unsigned Reg = MO.getReg();
164 if (Reg == 0) continue;
166 assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!");
167 Uses[Reg].push_back(&ExitSU);
170 // For others, e.g. fallthrough, conditional branch, assume the exit
171 // uses all the registers.
172 for (int i = 0, e = TRI->getNumRegs(); i != e; ++i)
173 Uses[i].push_back(&ExitSU);
177 void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
178 // We'll be allocating one SUnit for each instruction, plus one for
179 // the region exit node.
180 SUnits.reserve(BB->size());
182 // We build scheduling units by walking a block's instruction list from bottom
185 // Remember where a generic side-effecting instruction is as we procede.
186 SUnit *BarrierChain = 0, *AliasChain = 0;
188 // Memory references to specific known memory locations are tracked
189 // so that they can be given more precise dependencies. We track
190 // separately the known memory locations that may alias and those
191 // that are known not to alias
192 std::map<const Value *, SUnit *> AliasMemDefs, NonAliasMemDefs;
193 std::map<const Value *, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses;
195 // Keep track of dangling debug references to registers.
196 std::vector<std::pair<MachineInstr*, unsigned> >
197 DanglingDebugValue(TRI->getNumRegs(),
198 std::make_pair(static_cast<MachineInstr*>(0), 0));
200 // Check to see if the scheduler cares about latencies.
201 bool UnitLatencies = ForceUnitLatencies();
203 // Ask the target if address-backscheduling is desirable, and if so how much.
204 const TargetSubtarget &ST = TM.getSubtarget<TargetSubtarget>();
205 unsigned SpecialAddressLatency = ST.getSpecialAddressLatency();
207 // Remove any stale debug info; sometimes BuildSchedGraph is called again
208 // without emitting the info from the previous call.
211 // Model data dependencies between instructions being scheduled and the
213 AddSchedBarrierDeps();
215 // Walk the list of instructions, from bottom moving up.
216 for (MachineBasicBlock::iterator MII = InsertPos, MIE = Begin;
218 MachineInstr *MI = prior(MII);
219 // DBG_VALUE does not have SUnit's built, so just remember these for later
221 if (MI->isDebugValue()) {
222 if (MI->getNumOperands()==3 && MI->getOperand(0).isReg() &&
223 MI->getOperand(0).getReg())
224 DanglingDebugValue[MI->getOperand(0).getReg()] =
225 std::make_pair(MI, DbgValueVec.size());
226 DbgValueVec.push_back(MI);
229 const TargetInstrDesc &TID = MI->getDesc();
230 assert(!TID.isTerminator() && !MI->isLabel() &&
231 "Cannot schedule terminators or labels!");
232 // Create the SUnit for this MI.
233 SUnit *SU = NewSUnit(MI);
235 // Assign the Latency field of SU using target-provided information.
241 // Add register-based dependencies (data, anti, and output).
242 for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
243 const MachineOperand &MO = MI->getOperand(j);
244 if (!MO.isReg()) continue;
245 unsigned Reg = MO.getReg();
246 if (Reg == 0) continue;
248 assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!");
250 if (MO.isDef() && DanglingDebugValue[Reg].first!=0) {
251 SU->DbgInstrList.push_back(DanglingDebugValue[Reg].first);
252 DbgValueVec[DanglingDebugValue[Reg].second] = 0;
253 DanglingDebugValue[Reg] = std::make_pair((MachineInstr*)0, 0);
256 std::vector<SUnit *> &UseList = Uses[Reg];
257 std::vector<SUnit *> &DefList = Defs[Reg];
258 // Optionally add output and anti dependencies. For anti
259 // dependencies we use a latency of 0 because for a multi-issue
260 // target we want to allow the defining instruction to issue
261 // in the same cycle as the using instruction.
262 // TODO: Using a latency of 1 here for output dependencies assumes
263 // there's no cost for reusing registers.
264 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
265 unsigned AOLatency = (Kind == SDep::Anti) ? 0 : 1;
266 for (unsigned i = 0, e = DefList.size(); i != e; ++i) {
267 SUnit *DefSU = DefList[i];
268 if (DefSU == &ExitSU)
271 (Kind != SDep::Output || !MO.isDead() ||
272 !DefSU->getInstr()->registerDefIsDead(Reg)))
273 DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/Reg));
275 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
276 std::vector<SUnit *> &DefList = Defs[*Alias];
277 for (unsigned i = 0, e = DefList.size(); i != e; ++i) {
278 SUnit *DefSU = DefList[i];
279 if (DefSU == &ExitSU)
282 (Kind != SDep::Output || !MO.isDead() ||
283 !DefSU->getInstr()->registerDefIsDead(*Alias)))
284 DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/ *Alias));
289 // Add any data dependencies.
290 unsigned DataLatency = SU->Latency;
291 for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
292 SUnit *UseSU = UseList[i];
295 unsigned LDataLatency = DataLatency;
296 // Optionally add in a special extra latency for nodes that
298 // TODO: Do this for register aliases too.
299 // TODO: Perhaps we should get rid of
300 // SpecialAddressLatency and just move this into
301 // adjustSchedDependency for the targets that care about it.
302 if (SpecialAddressLatency != 0 && !UnitLatencies &&
304 MachineInstr *UseMI = UseSU->getInstr();
305 const TargetInstrDesc &UseTID = UseMI->getDesc();
306 int RegUseIndex = UseMI->findRegisterUseOperandIdx(Reg);
307 assert(RegUseIndex >= 0 && "UseMI doesn's use register!");
308 if (RegUseIndex >= 0 &&
309 (UseTID.mayLoad() || UseTID.mayStore()) &&
310 (unsigned)RegUseIndex < UseTID.getNumOperands() &&
311 UseTID.OpInfo[RegUseIndex].isLookupPtrRegClass())
312 LDataLatency += SpecialAddressLatency;
314 // Adjust the dependence latency using operand def/use
315 // information (if any), and then allow the target to
316 // perform its own adjustments.
317 const SDep& dep = SDep(SU, SDep::Data, LDataLatency, Reg);
318 if (!UnitLatencies) {
319 ComputeOperandLatency(SU, UseSU, const_cast<SDep &>(dep));
320 ST.adjustSchedDependency(SU, UseSU, const_cast<SDep &>(dep));
324 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
325 std::vector<SUnit *> &UseList = Uses[*Alias];
326 for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
327 SUnit *UseSU = UseList[i];
330 const SDep& dep = SDep(SU, SDep::Data, DataLatency, *Alias);
331 if (!UnitLatencies) {
332 ComputeOperandLatency(SU, UseSU, const_cast<SDep &>(dep));
333 ST.adjustSchedDependency(SU, UseSU, const_cast<SDep &>(dep));
339 // If a def is going to wrap back around to the top of the loop,
341 if (!UnitLatencies && DefList.empty()) {
342 LoopDependencies::LoopDeps::iterator I = LoopRegs.Deps.find(Reg);
343 if (I != LoopRegs.Deps.end()) {
344 const MachineOperand *UseMO = I->second.first;
345 unsigned Count = I->second.second;
346 const MachineInstr *UseMI = UseMO->getParent();
347 unsigned UseMOIdx = UseMO - &UseMI->getOperand(0);
348 const TargetInstrDesc &UseTID = UseMI->getDesc();
349 // TODO: If we knew the total depth of the region here, we could
350 // handle the case where the whole loop is inside the region but
351 // is large enough that the isScheduleHigh trick isn't needed.
352 if (UseMOIdx < UseTID.getNumOperands()) {
353 // Currently, we only support scheduling regions consisting of
354 // single basic blocks. Check to see if the instruction is in
355 // the same region by checking to see if it has the same parent.
356 if (UseMI->getParent() != MI->getParent()) {
357 unsigned Latency = SU->Latency;
358 if (UseTID.OpInfo[UseMOIdx].isLookupPtrRegClass())
359 Latency += SpecialAddressLatency;
360 // This is a wild guess as to the portion of the latency which
361 // will be overlapped by work done outside the current
362 // scheduling region.
363 Latency -= std::min(Latency, Count);
364 // Add the artifical edge.
365 ExitSU.addPred(SDep(SU, SDep::Order, Latency,
366 /*Reg=*/0, /*isNormalMemory=*/false,
367 /*isMustAlias=*/false,
368 /*isArtificial=*/true));
369 } else if (SpecialAddressLatency > 0 &&
370 UseTID.OpInfo[UseMOIdx].isLookupPtrRegClass()) {
371 // The entire loop body is within the current scheduling region
372 // and the latency of this operation is assumed to be greater
373 // than the latency of the loop.
374 // TODO: Recursively mark data-edge predecessors as
375 // isScheduleHigh too.
376 SU->isScheduleHigh = true;
379 LoopRegs.Deps.erase(I);
386 DefList.push_back(SU);
388 UseList.push_back(SU);
392 // Add chain dependencies.
393 // Chain dependencies used to enforce memory order should have
394 // latency of 0 (except for true dependency of Store followed by
395 // aliased Load... we estimate that with a single cycle of latency
396 // assuming the hardware will bypass)
397 // Note that isStoreToStackSlot and isLoadFromStackSLot are not usable
398 // after stack slots are lowered to actual addresses.
399 // TODO: Use an AliasAnalysis and do real alias-analysis queries, and
400 // produce more precise dependence information.
401 #define STORE_LOAD_LATENCY 1
402 unsigned TrueMemOrderLatency = 0;
403 if (TID.isCall() || TID.hasUnmodeledSideEffects() ||
404 (MI->hasVolatileMemoryRef() &&
405 (!TID.mayLoad() || !MI->isInvariantLoad(AA)))) {
406 // Be conservative with these and add dependencies on all memory
407 // references, even those that are known to not alias.
408 for (std::map<const Value *, SUnit *>::iterator I =
409 NonAliasMemDefs.begin(), E = NonAliasMemDefs.end(); I != E; ++I) {
410 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
412 for (std::map<const Value *, std::vector<SUnit *> >::iterator I =
413 NonAliasMemUses.begin(), E = NonAliasMemUses.end(); I != E; ++I) {
414 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
415 I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
417 NonAliasMemDefs.clear();
418 NonAliasMemUses.clear();
419 // Add SU to the barrier chain.
421 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
426 // Chain all possibly aliasing memory references though SU.
428 AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
430 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
431 PendingLoads[k]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
432 for (std::map<const Value *, SUnit *>::iterator I = AliasMemDefs.begin(),
433 E = AliasMemDefs.end(); I != E; ++I) {
434 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
436 for (std::map<const Value *, std::vector<SUnit *> >::iterator I =
437 AliasMemUses.begin(), E = AliasMemUses.end(); I != E; ++I) {
438 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
439 I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
441 PendingLoads.clear();
442 AliasMemDefs.clear();
443 AliasMemUses.clear();
444 } else if (TID.mayStore()) {
445 bool MayAlias = true;
446 TrueMemOrderLatency = STORE_LOAD_LATENCY;
447 if (const Value *V = getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
448 // A store to a specific PseudoSourceValue. Add precise dependencies.
449 // Record the def in MemDefs, first adding a dep if there is
451 std::map<const Value *, SUnit *>::iterator I =
452 ((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
453 std::map<const Value *, SUnit *>::iterator IE =
454 ((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
456 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0, /*Reg=*/0,
457 /*isNormalMemory=*/true));
461 AliasMemDefs[V] = SU;
463 NonAliasMemDefs[V] = SU;
465 // Handle the uses in MemUses, if there are any.
466 std::map<const Value *, std::vector<SUnit *> >::iterator J =
467 ((MayAlias) ? AliasMemUses.find(V) : NonAliasMemUses.find(V));
468 std::map<const Value *, std::vector<SUnit *> >::iterator JE =
469 ((MayAlias) ? AliasMemUses.end() : NonAliasMemUses.end());
471 for (unsigned i = 0, e = J->second.size(); i != e; ++i)
472 J->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency,
473 /*Reg=*/0, /*isNormalMemory=*/true));
477 // Add dependencies from all the PendingLoads, i.e. loads
478 // with no underlying object.
479 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
480 PendingLoads[k]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
481 // Add dependence on alias chain, if needed.
483 AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
485 // Add dependence on barrier chain, if needed.
487 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
489 // Treat all other stores conservatively.
490 goto new_alias_chain;
493 if (!ExitSU.isPred(SU))
494 // Push store's up a bit to avoid them getting in between cmp
496 ExitSU.addPred(SDep(SU, SDep::Order, 0,
497 /*Reg=*/0, /*isNormalMemory=*/false,
498 /*isMustAlias=*/false,
499 /*isArtificial=*/true));
500 } else if (TID.mayLoad()) {
501 bool MayAlias = true;
502 TrueMemOrderLatency = 0;
503 if (MI->isInvariantLoad(AA)) {
504 // Invariant load, no chain dependencies needed!
507 getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
508 // A load from a specific PseudoSourceValue. Add precise dependencies.
509 std::map<const Value *, SUnit *>::iterator I =
510 ((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
511 std::map<const Value *, SUnit *>::iterator IE =
512 ((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
514 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0, /*Reg=*/0,
515 /*isNormalMemory=*/true));
517 AliasMemUses[V].push_back(SU);
519 NonAliasMemUses[V].push_back(SU);
521 // A load with no underlying object. Depend on all
522 // potentially aliasing stores.
523 for (std::map<const Value *, SUnit *>::iterator I =
524 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I)
525 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
527 PendingLoads.push_back(SU);
531 // Add dependencies on alias and barrier chains, if needed.
532 if (MayAlias && AliasChain)
533 AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
535 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
540 for (int i = 0, e = TRI->getNumRegs(); i != e; ++i) {
544 PendingLoads.clear();
547 void ScheduleDAGInstrs::FinishBlock() {
551 void ScheduleDAGInstrs::ComputeLatency(SUnit *SU) {
552 // Compute the latency for the node.
553 if (!InstrItins || InstrItins->isEmpty()) {
556 // Simplistic target-independent heuristic: assume that loads take
558 if (SU->getInstr()->getDesc().mayLoad())
562 InstrItins->getStageLatency(SU->getInstr()->getDesc().getSchedClass());
565 void ScheduleDAGInstrs::ComputeOperandLatency(SUnit *Def, SUnit *Use,
567 if (!InstrItins || InstrItins->isEmpty())
570 // For a data dependency with a known register...
571 if ((dep.getKind() != SDep::Data) || (dep.getReg() == 0))
574 const unsigned Reg = dep.getReg();
576 // ... find the definition of the register in the defining
578 MachineInstr *DefMI = Def->getInstr();
579 int DefIdx = DefMI->findRegisterDefOperandIdx(Reg);
581 const MachineOperand &MO = DefMI->getOperand(DefIdx);
582 if (MO.isReg() && MO.isImplicit() &&
583 DefIdx >= (int)DefMI->getDesc().getNumOperands()) {
584 // This is an implicit def, getOperandLatency() won't return the correct
586 // %D6<def>, %D7<def> = VLD1q16 %R2<kill>, 0, ..., %Q3<imp-def>
587 // %Q1<def> = VMULv8i16 %Q1<kill>, %Q3<kill>, ...
588 // What we want is to compute latency between def of %D6/%D7 and use of
590 DefIdx = DefMI->findRegisterDefOperandIdx(Reg, false, true, TRI);
592 MachineInstr *UseMI = Use->getInstr();
593 // For all uses of the register, calculate the maxmimum latency
596 for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) {
597 const MachineOperand &MO = UseMI->getOperand(i);
598 if (!MO.isReg() || !MO.isUse())
600 unsigned MOReg = MO.getReg();
604 int UseCycle = TII->getOperandLatency(InstrItins, DefMI, DefIdx,
606 Latency = std::max(Latency, UseCycle);
609 // UseMI is null, then it must be a scheduling barrier.
610 if (!InstrItins || InstrItins->isEmpty())
612 unsigned DefClass = DefMI->getDesc().getSchedClass();
613 Latency = InstrItins->getOperandCycle(DefClass, DefIdx);
616 // If we found a latency, then replace the existing dependence latency.
618 dep.setLatency(Latency);
622 void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
623 SU->getInstr()->dump();
626 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
628 raw_string_ostream oss(s);
631 else if (SU == &ExitSU)
634 SU->getInstr()->print(oss);
638 // EmitSchedule - Emit the machine code in scheduled order.
639 MachineBasicBlock *ScheduleDAGInstrs::EmitSchedule() {
640 // For MachineInstr-based scheduling, we're rescheduling the instructions in
641 // the block, so start by removing them from the block.
642 while (Begin != InsertPos) {
643 MachineBasicBlock::iterator I = Begin;
648 // First reinsert any remaining debug_values; these are either constants,
649 // or refer to live-in registers. The beginning of the block is the right
650 // place for the latter. The former might reasonably be placed elsewhere
651 // using some kind of ordering algorithm, but right now it doesn't matter.
652 for (int i = DbgValueVec.size()-1; i>=0; --i)
654 BB->insert(InsertPos, DbgValueVec[i]);
656 // Then re-insert them according to the given schedule.
657 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
658 SUnit *SU = Sequence[i];
660 // Null SUnit* is a noop.
665 BB->insert(InsertPos, SU->getInstr());
666 for (unsigned i = 0, e = SU->DbgInstrList.size() ; i < e ; ++i)
667 BB->insert(InsertPos, SU->DbgInstrList[i]);
670 // Update the Begin iterator, as the first instruction in the block
671 // may have been scheduled later.
672 if (!DbgValueVec.empty()) {
673 for (int i = DbgValueVec.size()-1; i>=0; --i)
674 if (DbgValueVec[i]!=0) {
675 Begin = DbgValueVec[DbgValueVec.size()-1];
678 } else if (!Sequence.empty())
679 Begin = Sequence[0]->getInstr();