1 //===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the ScheduleDAGInstrs class, which implements re-scheduling
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "sched-instrs"
16 #include "RegisterPressure.h"
17 #include "llvm/Operator.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Analysis/ValueTracking.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineMemOperand.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
26 #include "llvm/MC/MCInstrItineraries.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetRegisterInfo.h"
30 #include "llvm/Target/TargetSubtargetInfo.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/ADT/SmallSet.h"
35 #include "llvm/ADT/SmallPtrSet.h"
38 static cl::opt<bool> EnableAASchedMI("enable-aa-sched-mi", cl::Hidden,
39 cl::ZeroOrMore, cl::init(false),
40 cl::desc("Enable use of AA during MI GAD construction"));
42 ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
43 const MachineLoopInfo &mli,
44 const MachineDominatorTree &mdt,
47 : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()),
48 InstrItins(mf.getTarget().getInstrItineraryData()), LIS(lis),
49 IsPostRA(IsPostRAFlag), UnitLatencies(false), CanHandleTerminators(false),
50 LoopRegs(MLI, MDT), FirstDbgValue(0) {
51 assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
53 assert(!(IsPostRA && MRI.getNumVirtRegs()) &&
54 "Virtual registers must be removed prior to PostRA scheduling");
57 /// getUnderlyingObjectFromInt - This is the function that does the work of
58 /// looking through basic ptrtoint+arithmetic+inttoptr sequences.
59 static const Value *getUnderlyingObjectFromInt(const Value *V) {
61 if (const Operator *U = dyn_cast<Operator>(V)) {
62 // If we find a ptrtoint, we can transfer control back to the
63 // regular getUnderlyingObjectFromInt.
64 if (U->getOpcode() == Instruction::PtrToInt)
65 return U->getOperand(0);
66 // If we find an add of a constant or a multiplied value, it's
67 // likely that the other operand will lead us to the base
68 // object. We don't have to worry about the case where the
69 // object address is somehow being computed by the multiply,
70 // because our callers only care when the result is an
71 // identifibale object.
72 if (U->getOpcode() != Instruction::Add ||
73 (!isa<ConstantInt>(U->getOperand(1)) &&
74 Operator::getOpcode(U->getOperand(1)) != Instruction::Mul))
80 assert(V->getType()->isIntegerTy() && "Unexpected operand type!");
84 /// getUnderlyingObject - This is a wrapper around GetUnderlyingObject
85 /// and adds support for basic ptrtoint+arithmetic+inttoptr sequences.
86 static const Value *getUnderlyingObject(const Value *V) {
87 // First just call Value::getUnderlyingObject to let it do what it does.
89 V = GetUnderlyingObject(V);
90 // If it found an inttoptr, use special code to continue climing.
91 if (Operator::getOpcode(V) != Instruction::IntToPtr)
93 const Value *O = getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0));
94 // If that succeeded in finding a pointer, continue the search.
95 if (!O->getType()->isPointerTy())
102 /// getUnderlyingObjectForInstr - If this machine instr has memory reference
103 /// information and it can be tracked to a normal reference to a known
104 /// object, return the Value for that object. Otherwise return null.
105 static const Value *getUnderlyingObjectForInstr(const MachineInstr *MI,
106 const MachineFrameInfo *MFI,
109 if (!MI->hasOneMemOperand() ||
110 !(*MI->memoperands_begin())->getValue() ||
111 (*MI->memoperands_begin())->isVolatile())
114 const Value *V = (*MI->memoperands_begin())->getValue();
118 V = getUnderlyingObject(V);
119 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
120 // For now, ignore PseudoSourceValues which may alias LLVM IR values
121 // because the code that uses this function has no way to cope with
123 if (PSV->isAliased(MFI))
126 MayAlias = PSV->mayAlias(MFI);
130 if (isIdentifiedObject(V))
136 void ScheduleDAGInstrs::startBlock(MachineBasicBlock *bb) {
138 LoopRegs.Deps.clear();
139 if (MachineLoop *ML = MLI.getLoopFor(BB))
140 if (BB == ML->getLoopLatch())
141 LoopRegs.VisitLoop(ML);
144 void ScheduleDAGInstrs::finishBlock() {
145 // Subclasses should no longer refer to the old block.
149 /// Initialize the map with the number of registers.
150 void Reg2SUnitsMap::setRegLimit(unsigned Limit) {
151 PhysRegSet.setUniverse(Limit);
152 SUnits.resize(Limit);
155 /// Clear the map without deallocating storage.
156 void Reg2SUnitsMap::clear() {
157 for (const_iterator I = reg_begin(), E = reg_end(); I != E; ++I) {
163 /// Initialize the DAG and common scheduler state for the current scheduling
164 /// region. This does not actually create the DAG, only clears it. The
165 /// scheduling driver may call BuildSchedGraph multiple times per scheduling
167 void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb,
168 MachineBasicBlock::iterator begin,
169 MachineBasicBlock::iterator end,
171 assert(bb == BB && "startBlock should set BB");
177 // Check to see if the scheduler cares about latencies.
178 UnitLatencies = forceUnitLatencies();
180 ScheduleDAG::clearDAG();
183 /// Close the current scheduling region. Don't clear any state in case the
184 /// driver wants to refer to the previous scheduling region.
185 void ScheduleDAGInstrs::exitRegion() {
189 /// addSchedBarrierDeps - Add dependencies from instructions in the current
190 /// list of instructions being scheduled to scheduling barrier by adding
191 /// the exit SU to the register defs and use list. This is because we want to
192 /// make sure instructions which define registers that are either used by
193 /// the terminator or are live-out are properly scheduled. This is
194 /// especially important when the definition latency of the return value(s)
195 /// are too high to be hidden by the branch or when the liveout registers
196 /// used by instructions in the fallthrough block.
197 void ScheduleDAGInstrs::addSchedBarrierDeps() {
198 MachineInstr *ExitMI = RegionEnd != BB->end() ? &*RegionEnd : 0;
199 ExitSU.setInstr(ExitMI);
200 bool AllDepKnown = ExitMI &&
201 (ExitMI->isCall() || ExitMI->isBarrier());
202 if (ExitMI && AllDepKnown) {
203 // If it's a call or a barrier, add dependencies on the defs and uses of
205 for (unsigned i = 0, e = ExitMI->getNumOperands(); i != e; ++i) {
206 const MachineOperand &MO = ExitMI->getOperand(i);
207 if (!MO.isReg() || MO.isDef()) continue;
208 unsigned Reg = MO.getReg();
209 if (Reg == 0) continue;
211 if (TRI->isPhysicalRegister(Reg))
212 Uses[Reg].push_back(&ExitSU);
214 assert(!IsPostRA && "Virtual register encountered after regalloc.");
215 addVRegUseDeps(&ExitSU, i);
219 // For others, e.g. fallthrough, conditional branch, assume the exit
220 // uses all the registers that are livein to the successor blocks.
221 assert(Uses.empty() && "Uses in set before adding deps?");
222 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
223 SE = BB->succ_end(); SI != SE; ++SI)
224 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
225 E = (*SI)->livein_end(); I != E; ++I) {
227 if (!Uses.contains(Reg))
228 Uses[Reg].push_back(&ExitSU);
233 /// MO is an operand of SU's instruction that defines a physical register. Add
234 /// data dependencies from SU to any uses of the physical register.
235 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU,
236 const MachineOperand &MO) {
237 assert(MO.isDef() && "expect physreg def");
239 // Ask the target if address-backscheduling is desirable, and if so how much.
240 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
241 unsigned SpecialAddressLatency = ST.getSpecialAddressLatency();
242 unsigned DataLatency = SU->Latency;
244 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
245 Alias.isValid(); ++Alias) {
246 if (!Uses.contains(*Alias))
248 std::vector<SUnit*> &UseList = Uses[*Alias];
249 for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
250 SUnit *UseSU = UseList[i];
253 unsigned LDataLatency = DataLatency;
254 // Optionally add in a special extra latency for nodes that
256 // TODO: Perhaps we should get rid of
257 // SpecialAddressLatency and just move this into
258 // adjustSchedDependency for the targets that care about it.
259 if (SpecialAddressLatency != 0 && !UnitLatencies &&
261 MachineInstr *UseMI = UseSU->getInstr();
262 const MCInstrDesc &UseMCID = UseMI->getDesc();
263 int RegUseIndex = UseMI->findRegisterUseOperandIdx(*Alias);
264 assert(RegUseIndex >= 0 && "UseMI doesn't use register!");
265 if (RegUseIndex >= 0 &&
266 (UseMI->mayLoad() || UseMI->mayStore()) &&
267 (unsigned)RegUseIndex < UseMCID.getNumOperands() &&
268 UseMCID.OpInfo[RegUseIndex].isLookupPtrRegClass())
269 LDataLatency += SpecialAddressLatency;
271 // Adjust the dependence latency using operand def/use
272 // information (if any), and then allow the target to
273 // perform its own adjustments.
274 const SDep& dep = SDep(SU, SDep::Data, LDataLatency, *Alias);
275 if (!UnitLatencies) {
276 computeOperandLatency(SU, UseSU, const_cast<SDep &>(dep));
277 ST.adjustSchedDependency(SU, UseSU, const_cast<SDep &>(dep));
284 /// addPhysRegDeps - Add register dependencies (data, anti, and output) from
285 /// this SUnit to following instructions in the same scheduling region that
286 /// depend the physical register referenced at OperIdx.
287 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
288 const MachineInstr *MI = SU->getInstr();
289 const MachineOperand &MO = MI->getOperand(OperIdx);
291 // Optionally add output and anti dependencies. For anti
292 // dependencies we use a latency of 0 because for a multi-issue
293 // target we want to allow the defining instruction to issue
294 // in the same cycle as the using instruction.
295 // TODO: Using a latency of 1 here for output dependencies assumes
296 // there's no cost for reusing registers.
297 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
298 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
299 Alias.isValid(); ++Alias) {
300 if (!Defs.contains(*Alias))
302 std::vector<SUnit *> &DefList = Defs[*Alias];
303 for (unsigned i = 0, e = DefList.size(); i != e; ++i) {
304 SUnit *DefSU = DefList[i];
305 if (DefSU == &ExitSU)
308 (Kind != SDep::Output || !MO.isDead() ||
309 !DefSU->getInstr()->registerDefIsDead(*Alias))) {
310 if (Kind == SDep::Anti)
311 DefSU->addPred(SDep(SU, Kind, 0, /*Reg=*/*Alias));
313 unsigned AOLat = TII->getOutputLatency(InstrItins, MI, OperIdx,
315 DefSU->addPred(SDep(SU, Kind, AOLat, /*Reg=*/*Alias));
322 // Either insert a new Reg2SUnits entry with an empty SUnits list, or
323 // retrieve the existing SUnits list for this register's uses.
324 // Push this SUnit on the use list.
325 Uses[MO.getReg()].push_back(SU);
328 addPhysRegDataDeps(SU, MO);
330 // Either insert a new Reg2SUnits entry with an empty SUnits list, or
331 // retrieve the existing SUnits list for this register's defs.
332 std::vector<SUnit *> &DefList = Defs[MO.getReg()];
334 // If a def is going to wrap back around to the top of the loop,
336 if (!UnitLatencies && DefList.empty()) {
337 LoopDependencies::LoopDeps::iterator I = LoopRegs.Deps.find(MO.getReg());
338 if (I != LoopRegs.Deps.end()) {
339 const MachineOperand *UseMO = I->second.first;
340 unsigned Count = I->second.second;
341 const MachineInstr *UseMI = UseMO->getParent();
342 unsigned UseMOIdx = UseMO - &UseMI->getOperand(0);
343 const MCInstrDesc &UseMCID = UseMI->getDesc();
344 const TargetSubtargetInfo &ST =
345 TM.getSubtarget<TargetSubtargetInfo>();
346 unsigned SpecialAddressLatency = ST.getSpecialAddressLatency();
347 // TODO: If we knew the total depth of the region here, we could
348 // handle the case where the whole loop is inside the region but
349 // is large enough that the isScheduleHigh trick isn't needed.
350 if (UseMOIdx < UseMCID.getNumOperands()) {
351 // Currently, we only support scheduling regions consisting of
352 // single basic blocks. Check to see if the instruction is in
353 // the same region by checking to see if it has the same parent.
354 if (UseMI->getParent() != MI->getParent()) {
355 unsigned Latency = SU->Latency;
356 if (UseMCID.OpInfo[UseMOIdx].isLookupPtrRegClass())
357 Latency += SpecialAddressLatency;
358 // This is a wild guess as to the portion of the latency which
359 // will be overlapped by work done outside the current
360 // scheduling region.
361 Latency -= std::min(Latency, Count);
362 // Add the artificial edge.
363 ExitSU.addPred(SDep(SU, SDep::Order, Latency,
364 /*Reg=*/0, /*isNormalMemory=*/false,
365 /*isMustAlias=*/false,
366 /*isArtificial=*/true));
367 } else if (SpecialAddressLatency > 0 &&
368 UseMCID.OpInfo[UseMOIdx].isLookupPtrRegClass()) {
369 // The entire loop body is within the current scheduling region
370 // and the latency of this operation is assumed to be greater
371 // than the latency of the loop.
372 // TODO: Recursively mark data-edge predecessors as
373 // isScheduleHigh too.
374 SU->isScheduleHigh = true;
377 LoopRegs.Deps.erase(I);
381 // clear this register's use list
382 if (Uses.contains(MO.getReg()))
383 Uses[MO.getReg()].clear();
388 // Calls will not be reordered because of chain dependencies (see
389 // below). Since call operands are dead, calls may continue to be added
390 // to the DefList making dependence checking quadratic in the size of
391 // the block. Instead, we leave only one call at the back of the
394 while (!DefList.empty() && DefList.back()->isCall)
397 // Defs are pushed in the order they are visited and never reordered.
398 DefList.push_back(SU);
402 /// addVRegDefDeps - Add register output and data dependencies from this SUnit
403 /// to instructions that occur later in the same scheduling region if they read
404 /// from or write to the virtual register defined at OperIdx.
406 /// TODO: Hoist loop induction variable increments. This has to be
407 /// reevaluated. Generally, IV scheduling should be done before coalescing.
408 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
409 const MachineInstr *MI = SU->getInstr();
410 unsigned Reg = MI->getOperand(OperIdx).getReg();
412 // SSA defs do not have output/anti dependencies.
413 // The current operand is a def, so we have at least one.
414 if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
417 // Add output dependence to the next nearest def of this vreg.
419 // Unless this definition is dead, the output dependence should be
420 // transitively redundant with antidependencies from this definition's
421 // uses. We're conservative for now until we have a way to guarantee the uses
422 // are not eliminated sometime during scheduling. The output dependence edge
423 // is also useful if output latency exceeds def-use latency.
424 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
425 if (DefI == VRegDefs.end())
426 VRegDefs.insert(VReg2SUnit(Reg, SU));
428 SUnit *DefSU = DefI->SU;
429 if (DefSU != SU && DefSU != &ExitSU) {
430 unsigned OutLatency = TII->getOutputLatency(InstrItins, MI, OperIdx,
432 DefSU->addPred(SDep(SU, SDep::Output, OutLatency, Reg));
438 /// addVRegUseDeps - Add a register data dependency if the instruction that
439 /// defines the virtual register used at OperIdx is mapped to an SUnit. Add a
440 /// register antidependency from this SUnit to instructions that occur later in
441 /// the same scheduling region if they write the virtual register.
443 /// TODO: Handle ExitSU "uses" properly.
444 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
445 MachineInstr *MI = SU->getInstr();
446 unsigned Reg = MI->getOperand(OperIdx).getReg();
448 // Lookup this operand's reaching definition.
449 assert(LIS && "vreg dependencies requires LiveIntervals");
450 LiveRangeQuery LRQ(LIS->getInterval(Reg), LIS->getInstructionIndex(MI));
451 VNInfo *VNI = LRQ.valueIn();
453 // VNI will be valid because MachineOperand::readsReg() is checked by caller.
454 assert(VNI && "No value to read by operand");
455 MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def);
456 // Phis and other noninstructions (after coalescing) have a NULL Def.
458 SUnit *DefSU = getSUnit(Def);
460 // The reaching Def lives within this scheduling region.
461 // Create a data dependence.
463 // TODO: Handle "special" address latencies cleanly.
464 const SDep &dep = SDep(DefSU, SDep::Data, DefSU->Latency, Reg);
465 if (!UnitLatencies) {
466 // Adjust the dependence latency using operand def/use information, then
467 // allow the target to perform its own adjustments.
468 computeOperandLatency(DefSU, SU, const_cast<SDep &>(dep));
469 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
470 ST.adjustSchedDependency(DefSU, SU, const_cast<SDep &>(dep));
476 // Add antidependence to the following def of the vreg it uses.
477 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
478 if (DefI != VRegDefs.end() && DefI->SU != SU)
479 DefI->SU->addPred(SDep(SU, SDep::Anti, 0, Reg));
482 /// Return true if MI is an instruction we are unable to reason about
483 /// (like a call or something with unmodeled side effects).
484 static inline bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) {
485 if (MI->isCall() || MI->hasUnmodeledSideEffects() ||
486 (MI->hasVolatileMemoryRef() &&
487 (!MI->mayLoad() || !MI->isInvariantLoad(AA))))
492 // This MI might have either incomplete info, or known to be unsafe
493 // to deal with (i.e. volatile object).
494 static inline bool isUnsafeMemoryObject(MachineInstr *MI,
495 const MachineFrameInfo *MFI) {
496 if (!MI || MI->memoperands_empty())
498 // We purposefully do no check for hasOneMemOperand() here
499 // in hope to trigger an assert downstream in order to
500 // finish implementation.
501 if ((*MI->memoperands_begin())->isVolatile() ||
502 MI->hasUnmodeledSideEffects())
505 const Value *V = (*MI->memoperands_begin())->getValue();
509 V = getUnderlyingObject(V);
510 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
511 // Similarly to getUnderlyingObjectForInstr:
512 // For now, ignore PseudoSourceValues which may alias LLVM IR values
513 // because the code that uses this function has no way to cope with
515 if (PSV->isAliased(MFI))
518 // Does this pointer refer to a distinct and identifiable object?
519 if (!isIdentifiedObject(V))
525 /// This returns true if the two MIs need a chain edge betwee them.
526 /// If these are not even memory operations, we still may need
527 /// chain deps between them. The question really is - could
528 /// these two MIs be reordered during scheduling from memory dependency
530 static bool MIsNeedChainEdge(AliasAnalysis *AA, const MachineFrameInfo *MFI,
533 // Cover a trivial case - no edge is need to itself.
537 if (isUnsafeMemoryObject(MIa, MFI) || isUnsafeMemoryObject(MIb, MFI))
540 // If we are dealing with two "normal" loads, we do not need an edge
541 // between them - they could be reordered.
542 if (!MIa->mayStore() && !MIb->mayStore())
545 // To this point analysis is generic. From here on we do need AA.
549 MachineMemOperand *MMOa = *MIa->memoperands_begin();
550 MachineMemOperand *MMOb = *MIb->memoperands_begin();
552 // FIXME: Need to handle multiple memory operands to support all targets.
553 if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand())
554 llvm_unreachable("Multiple memory operands.");
556 // The following interface to AA is fashioned after DAGCombiner::isAlias
557 // and operates with MachineMemOperand offset with some important
559 // - LLVM fundamentally assumes flat address spaces.
560 // - MachineOperand offset can *only* result from legalization and
561 // cannot affect queries other than the trivial case of overlap
563 // - These offsets never wrap and never step outside
564 // of allocated objects.
565 // - There should never be any negative offsets here.
567 // FIXME: Modify API to hide this math from "user"
568 // FIXME: Even before we go to AA we can reason locally about some
569 // memory objects. It can save compile time, and possibly catch some
570 // corner cases not currently covered.
572 assert ((MMOa->getOffset() >= 0) && "Negative MachineMemOperand offset");
573 assert ((MMOb->getOffset() >= 0) && "Negative MachineMemOperand offset");
575 int64_t MinOffset = std::min(MMOa->getOffset(), MMOb->getOffset());
576 int64_t Overlapa = MMOa->getSize() + MMOa->getOffset() - MinOffset;
577 int64_t Overlapb = MMOb->getSize() + MMOb->getOffset() - MinOffset;
579 AliasAnalysis::AliasResult AAResult = AA->alias(
580 AliasAnalysis::Location(MMOa->getValue(), Overlapa,
581 MMOa->getTBAAInfo()),
582 AliasAnalysis::Location(MMOb->getValue(), Overlapb,
583 MMOb->getTBAAInfo()));
585 return (AAResult != AliasAnalysis::NoAlias);
588 /// This recursive function iterates over chain deps of SUb looking for
589 /// "latest" node that needs a chain edge to SUa.
591 iterateChainSucc(AliasAnalysis *AA, const MachineFrameInfo *MFI,
592 SUnit *SUa, SUnit *SUb, SUnit *ExitSU, unsigned *Depth,
593 SmallPtrSet<const SUnit*, 16> &Visited) {
594 if (!SUa || !SUb || SUb == ExitSU)
597 // Remember visited nodes.
598 if (!Visited.insert(SUb))
600 // If there is _some_ dependency already in place, do not
601 // descend any further.
602 // TODO: Need to make sure that if that dependency got eliminated or ignored
603 // for any reason in the future, we would not violate DAG topology.
604 // Currently it does not happen, but makes an implicit assumption about
605 // future implementation.
607 // Independently, if we encounter node that is some sort of global
608 // object (like a call) we already have full set of dependencies to it
609 // and we can stop descending.
610 if (SUa->isSucc(SUb) ||
611 isGlobalMemoryObject(AA, SUb->getInstr()))
614 // If we do need an edge, or we have exceeded depth budget,
615 // add that edge to the predecessors chain of SUb,
616 // and stop descending.
618 MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) {
619 SUb->addPred(SDep(SUa, SDep::Order, /*Latency=*/0, /*Reg=*/0,
620 /*isNormalMemory=*/true));
623 // Track current depth.
625 // Iterate over chain dependencies only.
626 for (SUnit::const_succ_iterator I = SUb->Succs.begin(), E = SUb->Succs.end();
629 iterateChainSucc (AA, MFI, SUa, I->getSUnit(), ExitSU, Depth, Visited);
633 /// This function assumes that "downward" from SU there exist
634 /// tail/leaf of already constructed DAG. It iterates downward and
635 /// checks whether SU can be aliasing any node dominated
637 static void adjustChainDeps(AliasAnalysis *AA, const MachineFrameInfo *MFI,
638 SUnit *SU, SUnit *ExitSU, std::set<SUnit *> &CheckList) {
642 SmallPtrSet<const SUnit*, 16> Visited;
645 for (std::set<SUnit *>::iterator I = CheckList.begin(), IE = CheckList.end();
649 if (MIsNeedChainEdge(AA, MFI, SU->getInstr(), (*I)->getInstr()))
650 (*I)->addPred(SDep(SU, SDep::Order, /*Latency=*/0, /*Reg=*/0,
651 /*isNormalMemory=*/true));
652 // Now go through all the chain successors and iterate from them.
653 // Keep track of visited nodes.
654 for (SUnit::const_succ_iterator J = (*I)->Succs.begin(),
655 JE = (*I)->Succs.end(); J != JE; ++J)
657 iterateChainSucc (AA, MFI, SU, J->getSUnit(),
658 ExitSU, &Depth, Visited);
662 /// Check whether two objects need a chain edge, if so, add it
663 /// otherwise remember the rejected SU.
665 void addChainDependency (AliasAnalysis *AA, const MachineFrameInfo *MFI,
666 SUnit *SUa, SUnit *SUb,
667 std::set<SUnit *> &RejectList,
668 unsigned TrueMemOrderLatency = 0,
669 bool isNormalMemory = false) {
670 // If this is a false dependency,
671 // do not add the edge, but rememeber the rejected node.
672 if (!EnableAASchedMI ||
673 MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr()))
674 SUb->addPred(SDep(SUa, SDep::Order, TrueMemOrderLatency, /*Reg=*/0,
677 // Duplicate entries should be ignored.
678 RejectList.insert(SUb);
679 DEBUG(dbgs() << "\tReject chain dep between SU("
680 << SUa->NodeNum << ") and SU("
681 << SUb->NodeNum << ")\n");
685 /// Create an SUnit for each real instruction, numbered in top-down toplological
686 /// order. The instruction order A < B, implies that no edge exists from B to A.
688 /// Map each real instruction to its SUnit.
690 /// After initSUnits, the SUnits vector cannot be resized and the scheduler may
691 /// hang onto SUnit pointers. We may relax this in the future by using SUnit IDs
692 /// instead of pointers.
694 /// MachineScheduler relies on initSUnits numbering the nodes by their order in
695 /// the original instruction list.
696 void ScheduleDAGInstrs::initSUnits() {
697 // We'll be allocating one SUnit for each real instruction in the region,
698 // which is contained within a basic block.
699 SUnits.reserve(BB->size());
701 for (MachineBasicBlock::iterator I = RegionBegin; I != RegionEnd; ++I) {
702 MachineInstr *MI = I;
703 if (MI->isDebugValue())
706 SUnit *SU = newSUnit(MI);
709 SU->isCall = MI->isCall();
710 SU->isCommutable = MI->isCommutable();
712 // Assign the Latency field of SU using target-provided information.
720 /// If RegPressure is non null, compute register pressure as a side effect. The
721 /// DAG builder is an efficient place to do it because it already visits
723 void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
724 RegPressureTracker *RPTracker) {
725 // Create an SUnit for each real instruction.
728 // We build scheduling units by walking a block's instruction list from bottom
731 // Remember where a generic side-effecting instruction is as we procede.
732 SUnit *BarrierChain = 0, *AliasChain = 0;
734 // Memory references to specific known memory locations are tracked
735 // so that they can be given more precise dependencies. We track
736 // separately the known memory locations that may alias and those
737 // that are known not to alias
738 std::map<const Value *, SUnit *> AliasMemDefs, NonAliasMemDefs;
739 std::map<const Value *, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses;
740 std::set<SUnit*> RejectMemNodes;
742 // Remove any stale debug info; sometimes BuildSchedGraph is called again
743 // without emitting the info from the previous call.
745 FirstDbgValue = NULL;
747 assert(Defs.empty() && Uses.empty() &&
748 "Only BuildGraph should update Defs/Uses");
749 Defs.setRegLimit(TRI->getNumRegs());
750 Uses.setRegLimit(TRI->getNumRegs());
752 assert(VRegDefs.empty() && "Only BuildSchedGraph may access VRegDefs");
753 // FIXME: Allow SparseSet to reserve space for the creation of virtual
754 // registers during scheduling. Don't artificially inflate the Universe
755 // because we want to assert that vregs are not created during DAG building.
756 VRegDefs.setUniverse(MRI.getNumVirtRegs());
758 // Model data dependencies between instructions being scheduled and the
760 addSchedBarrierDeps();
762 // Walk the list of instructions, from bottom moving up.
763 MachineInstr *PrevMI = NULL;
764 for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
766 MachineInstr *MI = prior(MII);
768 DbgValues.push_back(std::make_pair(PrevMI, MI));
772 if (MI->isDebugValue()) {
778 assert(RPTracker->getPos() == prior(MII) && "RPTracker can't find MI");
781 assert((!MI->isTerminator() || CanHandleTerminators) && !MI->isLabel() &&
782 "Cannot schedule terminators or labels!");
784 SUnit *SU = MISUnitMap[MI];
785 assert(SU && "No SUnit mapped to this MI");
787 // Add register-based dependencies (data, anti, and output).
788 for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
789 const MachineOperand &MO = MI->getOperand(j);
790 if (!MO.isReg()) continue;
791 unsigned Reg = MO.getReg();
792 if (Reg == 0) continue;
794 if (TRI->isPhysicalRegister(Reg))
795 addPhysRegDeps(SU, j);
797 assert(!IsPostRA && "Virtual register encountered!");
799 addVRegDefDeps(SU, j);
800 else if (MO.readsReg()) // ignore undef operands
801 addVRegUseDeps(SU, j);
805 // Add chain dependencies.
806 // Chain dependencies used to enforce memory order should have
807 // latency of 0 (except for true dependency of Store followed by
808 // aliased Load... we estimate that with a single cycle of latency
809 // assuming the hardware will bypass)
810 // Note that isStoreToStackSlot and isLoadFromStackSLot are not usable
811 // after stack slots are lowered to actual addresses.
812 // TODO: Use an AliasAnalysis and do real alias-analysis queries, and
813 // produce more precise dependence information.
814 #define STORE_LOAD_LATENCY 1
815 unsigned TrueMemOrderLatency = 0;
816 if (isGlobalMemoryObject(AA, MI)) {
817 // Be conservative with these and add dependencies on all memory
818 // references, even those that are known to not alias.
819 for (std::map<const Value *, SUnit *>::iterator I =
820 NonAliasMemDefs.begin(), E = NonAliasMemDefs.end(); I != E; ++I) {
821 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
823 for (std::map<const Value *, std::vector<SUnit *> >::iterator I =
824 NonAliasMemUses.begin(), E = NonAliasMemUses.end(); I != E; ++I) {
825 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
826 I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
828 // Add SU to the barrier chain.
830 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
832 // This is a barrier event that acts as a pivotal node in the DAG,
833 // so it is safe to clear list of exposed nodes.
834 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes);
835 RejectMemNodes.clear();
836 NonAliasMemDefs.clear();
837 NonAliasMemUses.clear();
841 // Chain all possibly aliasing memory references though SU.
843 addChainDependency(AA, MFI, SU, AliasChain, RejectMemNodes);
845 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
846 addChainDependency(AA, MFI, SU, PendingLoads[k], RejectMemNodes,
847 TrueMemOrderLatency);
848 for (std::map<const Value *, SUnit *>::iterator I = AliasMemDefs.begin(),
849 E = AliasMemDefs.end(); I != E; ++I)
850 addChainDependency(AA, MFI, SU, I->second, RejectMemNodes);
851 for (std::map<const Value *, std::vector<SUnit *> >::iterator I =
852 AliasMemUses.begin(), E = AliasMemUses.end(); I != E; ++I) {
853 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
854 addChainDependency(AA, MFI, SU, I->second[i], RejectMemNodes,
855 TrueMemOrderLatency);
857 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes);
858 PendingLoads.clear();
859 AliasMemDefs.clear();
860 AliasMemUses.clear();
861 } else if (MI->mayStore()) {
862 bool MayAlias = true;
863 TrueMemOrderLatency = STORE_LOAD_LATENCY;
864 if (const Value *V = getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
865 // A store to a specific PseudoSourceValue. Add precise dependencies.
866 // Record the def in MemDefs, first adding a dep if there is
868 std::map<const Value *, SUnit *>::iterator I =
869 ((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
870 std::map<const Value *, SUnit *>::iterator IE =
871 ((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
873 addChainDependency(AA, MFI, SU, I->second, RejectMemNodes,
878 AliasMemDefs[V] = SU;
880 NonAliasMemDefs[V] = SU;
882 // Handle the uses in MemUses, if there are any.
883 std::map<const Value *, std::vector<SUnit *> >::iterator J =
884 ((MayAlias) ? AliasMemUses.find(V) : NonAliasMemUses.find(V));
885 std::map<const Value *, std::vector<SUnit *> >::iterator JE =
886 ((MayAlias) ? AliasMemUses.end() : NonAliasMemUses.end());
888 for (unsigned i = 0, e = J->second.size(); i != e; ++i)
889 addChainDependency(AA, MFI, SU, J->second[i], RejectMemNodes,
890 TrueMemOrderLatency, true);
894 // Add dependencies from all the PendingLoads, i.e. loads
895 // with no underlying object.
896 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
897 addChainDependency(AA, MFI, SU, PendingLoads[k], RejectMemNodes,
898 TrueMemOrderLatency);
899 // Add dependence on alias chain, if needed.
901 addChainDependency(AA, MFI, SU, AliasChain, RejectMemNodes);
902 // But we also should check dependent instructions for the
904 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes);
906 // Add dependence on barrier chain, if needed.
907 // There is no point to check aliasing on barrier event. Even if
908 // SU and barrier _could_ be reordered, they should not. In addition,
909 // we have lost all RejectMemNodes below barrier.
911 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
913 // Treat all other stores conservatively.
914 goto new_alias_chain;
917 if (!ExitSU.isPred(SU))
918 // Push store's up a bit to avoid them getting in between cmp
920 ExitSU.addPred(SDep(SU, SDep::Order, 0,
921 /*Reg=*/0, /*isNormalMemory=*/false,
922 /*isMustAlias=*/false,
923 /*isArtificial=*/true));
924 } else if (MI->mayLoad()) {
925 bool MayAlias = true;
926 TrueMemOrderLatency = 0;
927 if (MI->isInvariantLoad(AA)) {
928 // Invariant load, no chain dependencies needed!
931 getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
932 // A load from a specific PseudoSourceValue. Add precise dependencies.
933 std::map<const Value *, SUnit *>::iterator I =
934 ((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
935 std::map<const Value *, SUnit *>::iterator IE =
936 ((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
938 addChainDependency(AA, MFI, SU, I->second, RejectMemNodes, 0, true);
940 AliasMemUses[V].push_back(SU);
942 NonAliasMemUses[V].push_back(SU);
944 // A load with no underlying object. Depend on all
945 // potentially aliasing stores.
946 for (std::map<const Value *, SUnit *>::iterator I =
947 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I)
948 addChainDependency(AA, MFI, SU, I->second, RejectMemNodes);
950 PendingLoads.push_back(SU);
954 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes);
955 // Add dependencies on alias and barrier chains, if needed.
956 if (MayAlias && AliasChain)
957 addChainDependency(AA, MFI, SU, AliasChain, RejectMemNodes);
959 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
964 FirstDbgValue = PrevMI;
969 PendingLoads.clear();
972 void ScheduleDAGInstrs::computeLatency(SUnit *SU) {
973 // Compute the latency for the node.
974 if (!InstrItins || InstrItins->isEmpty()) {
977 // Simplistic target-independent heuristic: assume that loads take
979 if (SU->getInstr()->mayLoad())
982 SU->Latency = TII->getInstrLatency(InstrItins, SU->getInstr());
986 void ScheduleDAGInstrs::computeOperandLatency(SUnit *Def, SUnit *Use,
988 if (!InstrItins || InstrItins->isEmpty())
991 // For a data dependency with a known register...
992 if ((dep.getKind() != SDep::Data) || (dep.getReg() == 0))
995 const unsigned Reg = dep.getReg();
997 // ... find the definition of the register in the defining
999 MachineInstr *DefMI = Def->getInstr();
1000 int DefIdx = DefMI->findRegisterDefOperandIdx(Reg);
1002 const MachineOperand &MO = DefMI->getOperand(DefIdx);
1003 if (MO.isReg() && MO.isImplicit() &&
1004 DefIdx >= (int)DefMI->getDesc().getNumOperands()) {
1005 // This is an implicit def, getOperandLatency() won't return the correct
1007 // %D6<def>, %D7<def> = VLD1q16 %R2<kill>, 0, ..., %Q3<imp-def>
1008 // %Q1<def> = VMULv8i16 %Q1<kill>, %Q3<kill>, ...
1009 // What we want is to compute latency between def of %D6/%D7 and use of
1011 unsigned Op2 = DefMI->findRegisterDefOperandIdx(Reg, false, true, TRI);
1012 if (DefMI->getOperand(Op2).isReg())
1015 MachineInstr *UseMI = Use->getInstr();
1016 // For all uses of the register, calculate the maxmimum latency
1019 for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) {
1020 const MachineOperand &MO = UseMI->getOperand(i);
1021 if (!MO.isReg() || !MO.isUse())
1023 unsigned MOReg = MO.getReg();
1027 int UseCycle = TII->getOperandLatency(InstrItins, DefMI, DefIdx,
1029 Latency = std::max(Latency, UseCycle);
1032 // UseMI is null, then it must be a scheduling barrier.
1033 if (!InstrItins || InstrItins->isEmpty())
1035 unsigned DefClass = DefMI->getDesc().getSchedClass();
1036 Latency = InstrItins->getOperandCycle(DefClass, DefIdx);
1039 // If we found a latency, then replace the existing dependence latency.
1041 dep.setLatency(Latency);
1045 void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
1046 SU->getInstr()->dump();
1049 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
1051 raw_string_ostream oss(s);
1054 else if (SU == &ExitSU)
1057 SU->getInstr()->print(oss);
1061 /// Return the basic block label. It is not necessarilly unique because a block
1062 /// contains multiple scheduling regions. But it is fine for visualization.
1063 std::string ScheduleDAGInstrs::getDAGName() const {
1064 return "dag." + BB->getFullName();