1 //===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the ScheduleDAGInstrs class, which implements re-scheduling
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
16 #include "llvm/ADT/MapVector.h"
17 #include "llvm/ADT/SmallPtrSet.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/ValueTracking.h"
21 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/CodeGen/RegisterPressure.h"
28 #include "llvm/CodeGen/ScheduleDFS.h"
29 #include "llvm/IR/Operator.h"
30 #include "llvm/MC/MCInstrItineraries.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/Format.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetRegisterInfo.h"
38 #include "llvm/Target/TargetSubtargetInfo.h"
43 #define DEBUG_TYPE "misched"
45 static cl::opt<bool> EnableAASchedMI("enable-aa-sched-mi", cl::Hidden,
46 cl::ZeroOrMore, cl::init(false),
47 cl::desc("Enable use of AA during MI DAG construction"));
49 static cl::opt<bool> UseTBAA("use-tbaa-in-sched-mi", cl::Hidden,
50 cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"));
52 ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
53 const MachineLoopInfo *mli,
54 bool IsPostRAFlag, bool RemoveKillFlags,
56 : ScheduleDAG(mf), MLI(mli), MFI(mf.getFrameInfo()), LIS(lis),
57 IsPostRA(IsPostRAFlag), RemoveKillFlags(RemoveKillFlags),
58 CanHandleTerminators(false), FirstDbgValue(nullptr) {
59 assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
61 assert(!(IsPostRA && MRI.getNumVirtRegs()) &&
62 "Virtual registers must be removed prior to PostRA scheduling");
64 const TargetSubtargetInfo &ST = mf.getSubtarget();
65 SchedModel.init(ST.getSchedModel(), &ST, TII);
68 /// getUnderlyingObjectFromInt - This is the function that does the work of
69 /// looking through basic ptrtoint+arithmetic+inttoptr sequences.
70 static const Value *getUnderlyingObjectFromInt(const Value *V) {
72 if (const Operator *U = dyn_cast<Operator>(V)) {
73 // If we find a ptrtoint, we can transfer control back to the
74 // regular getUnderlyingObjectFromInt.
75 if (U->getOpcode() == Instruction::PtrToInt)
76 return U->getOperand(0);
77 // If we find an add of a constant, a multiplied value, or a phi, it's
78 // likely that the other operand will lead us to the base
79 // object. We don't have to worry about the case where the
80 // object address is somehow being computed by the multiply,
81 // because our callers only care when the result is an
82 // identifiable object.
83 if (U->getOpcode() != Instruction::Add ||
84 (!isa<ConstantInt>(U->getOperand(1)) &&
85 Operator::getOpcode(U->getOperand(1)) != Instruction::Mul &&
86 !isa<PHINode>(U->getOperand(1))))
92 assert(V->getType()->isIntegerTy() && "Unexpected operand type!");
96 /// getUnderlyingObjects - This is a wrapper around GetUnderlyingObjects
97 /// and adds support for basic ptrtoint+arithmetic+inttoptr sequences.
98 static void getUnderlyingObjects(const Value *V,
99 SmallVectorImpl<Value *> &Objects) {
100 SmallPtrSet<const Value *, 16> Visited;
101 SmallVector<const Value *, 4> Working(1, V);
103 V = Working.pop_back_val();
105 SmallVector<Value *, 4> Objs;
106 GetUnderlyingObjects(const_cast<Value *>(V), Objs);
108 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(), IE = Objs.end();
111 if (!Visited.insert(V).second)
113 if (Operator::getOpcode(V) == Instruction::IntToPtr) {
115 getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0));
116 if (O->getType()->isPointerTy()) {
117 Working.push_back(O);
121 Objects.push_back(const_cast<Value *>(V));
123 } while (!Working.empty());
126 typedef PointerUnion<const Value *, const PseudoSourceValue *> ValueType;
127 typedef SmallVector<PointerIntPair<ValueType, 1, bool>, 4>
128 UnderlyingObjectsVector;
130 /// getUnderlyingObjectsForInstr - If this machine instr has memory reference
131 /// information and it can be tracked to a normal reference to a known
132 /// object, return the Value for that object.
133 static void getUnderlyingObjectsForInstr(const MachineInstr *MI,
134 const MachineFrameInfo *MFI,
135 UnderlyingObjectsVector &Objects) {
136 if (!MI->hasOneMemOperand() ||
137 (!(*MI->memoperands_begin())->getValue() &&
138 !(*MI->memoperands_begin())->getPseudoValue()) ||
139 (*MI->memoperands_begin())->isVolatile())
142 if (const PseudoSourceValue *PSV =
143 (*MI->memoperands_begin())->getPseudoValue()) {
144 // For now, ignore PseudoSourceValues which may alias LLVM IR values
145 // because the code that uses this function has no way to cope with
147 if (!PSV->isAliased(MFI)) {
148 bool MayAlias = PSV->mayAlias(MFI);
149 Objects.push_back(UnderlyingObjectsVector::value_type(PSV, MayAlias));
154 const Value *V = (*MI->memoperands_begin())->getValue();
158 SmallVector<Value *, 4> Objs;
159 getUnderlyingObjects(V, Objs);
161 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(), IE = Objs.end();
165 if (!isIdentifiedObject(V)) {
170 Objects.push_back(UnderlyingObjectsVector::value_type(V, true));
174 void ScheduleDAGInstrs::startBlock(MachineBasicBlock *bb) {
178 void ScheduleDAGInstrs::finishBlock() {
179 // Subclasses should no longer refer to the old block.
183 /// Initialize the DAG and common scheduler state for the current scheduling
184 /// region. This does not actually create the DAG, only clears it. The
185 /// scheduling driver may call BuildSchedGraph multiple times per scheduling
187 void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb,
188 MachineBasicBlock::iterator begin,
189 MachineBasicBlock::iterator end,
190 unsigned regioninstrs) {
191 assert(bb == BB && "startBlock should set BB");
194 NumRegionInstrs = regioninstrs;
197 /// Close the current scheduling region. Don't clear any state in case the
198 /// driver wants to refer to the previous scheduling region.
199 void ScheduleDAGInstrs::exitRegion() {
203 /// addSchedBarrierDeps - Add dependencies from instructions in the current
204 /// list of instructions being scheduled to scheduling barrier by adding
205 /// the exit SU to the register defs and use list. This is because we want to
206 /// make sure instructions which define registers that are either used by
207 /// the terminator or are live-out are properly scheduled. This is
208 /// especially important when the definition latency of the return value(s)
209 /// are too high to be hidden by the branch or when the liveout registers
210 /// used by instructions in the fallthrough block.
211 void ScheduleDAGInstrs::addSchedBarrierDeps() {
212 MachineInstr *ExitMI = RegionEnd != BB->end() ? &*RegionEnd : nullptr;
213 ExitSU.setInstr(ExitMI);
214 bool AllDepKnown = ExitMI &&
215 (ExitMI->isCall() || ExitMI->isBarrier());
216 if (ExitMI && AllDepKnown) {
217 // If it's a call or a barrier, add dependencies on the defs and uses of
219 for (unsigned i = 0, e = ExitMI->getNumOperands(); i != e; ++i) {
220 const MachineOperand &MO = ExitMI->getOperand(i);
221 if (!MO.isReg() || MO.isDef()) continue;
222 unsigned Reg = MO.getReg();
223 if (Reg == 0) continue;
225 if (TRI->isPhysicalRegister(Reg))
226 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
228 assert(!IsPostRA && "Virtual register encountered after regalloc.");
229 if (MO.readsReg()) // ignore undef operands
230 addVRegUseDeps(&ExitSU, i);
234 // For others, e.g. fallthrough, conditional branch, assume the exit
235 // uses all the registers that are livein to the successor blocks.
236 assert(Uses.empty() && "Uses in set before adding deps?");
237 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
238 SE = BB->succ_end(); SI != SE; ++SI)
239 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
240 E = (*SI)->livein_end(); I != E; ++I) {
242 if (!Uses.contains(Reg))
243 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
248 /// MO is an operand of SU's instruction that defines a physical register. Add
249 /// data dependencies from SU to any uses of the physical register.
250 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
251 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
252 assert(MO.isDef() && "expect physreg def");
254 // Ask the target if address-backscheduling is desirable, and if so how much.
255 const TargetSubtargetInfo &ST = MF.getSubtarget();
257 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
258 Alias.isValid(); ++Alias) {
259 if (!Uses.contains(*Alias))
261 for (Reg2SUnitsMap::iterator I = Uses.find(*Alias); I != Uses.end(); ++I) {
262 SUnit *UseSU = I->SU;
266 // Adjust the dependence latency using operand def/use information,
267 // then allow the target to perform its own adjustments.
268 int UseOp = I->OpIdx;
269 MachineInstr *RegUse = nullptr;
272 Dep = SDep(SU, SDep::Artificial);
274 // Set the hasPhysRegDefs only for physreg defs that have a use within
275 // the scheduling region.
276 SU->hasPhysRegDefs = true;
277 Dep = SDep(SU, SDep::Data, *Alias);
278 RegUse = UseSU->getInstr();
281 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse,
284 ST.adjustSchedDependency(SU, UseSU, Dep);
290 /// addPhysRegDeps - Add register dependencies (data, anti, and output) from
291 /// this SUnit to following instructions in the same scheduling region that
292 /// depend the physical register referenced at OperIdx.
293 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
294 MachineInstr *MI = SU->getInstr();
295 MachineOperand &MO = MI->getOperand(OperIdx);
297 // Optionally add output and anti dependencies. For anti
298 // dependencies we use a latency of 0 because for a multi-issue
299 // target we want to allow the defining instruction to issue
300 // in the same cycle as the using instruction.
301 // TODO: Using a latency of 1 here for output dependencies assumes
302 // there's no cost for reusing registers.
303 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
304 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
305 Alias.isValid(); ++Alias) {
306 if (!Defs.contains(*Alias))
308 for (Reg2SUnitsMap::iterator I = Defs.find(*Alias); I != Defs.end(); ++I) {
309 SUnit *DefSU = I->SU;
310 if (DefSU == &ExitSU)
313 (Kind != SDep::Output || !MO.isDead() ||
314 !DefSU->getInstr()->registerDefIsDead(*Alias))) {
315 if (Kind == SDep::Anti)
316 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias));
318 SDep Dep(SU, Kind, /*Reg=*/*Alias);
320 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
328 SU->hasPhysRegUses = true;
329 // Either insert a new Reg2SUnits entry with an empty SUnits list, or
330 // retrieve the existing SUnits list for this register's uses.
331 // Push this SUnit on the use list.
332 Uses.insert(PhysRegSUOper(SU, OperIdx, MO.getReg()));
337 addPhysRegDataDeps(SU, OperIdx);
338 unsigned Reg = MO.getReg();
340 // clear this register's use list
341 if (Uses.contains(Reg))
346 } else if (SU->isCall) {
347 // Calls will not be reordered because of chain dependencies (see
348 // below). Since call operands are dead, calls may continue to be added
349 // to the DefList making dependence checking quadratic in the size of
350 // the block. Instead, we leave only one call at the back of the
352 Reg2SUnitsMap::RangePair P = Defs.equal_range(Reg);
353 Reg2SUnitsMap::iterator B = P.first;
354 Reg2SUnitsMap::iterator I = P.second;
355 for (bool isBegin = I == B; !isBegin; /* empty */) {
356 isBegin = (--I) == B;
363 // Defs are pushed in the order they are visited and never reordered.
364 Defs.insert(PhysRegSUOper(SU, OperIdx, Reg));
368 /// addVRegDefDeps - Add register output and data dependencies from this SUnit
369 /// to instructions that occur later in the same scheduling region if they read
370 /// from or write to the virtual register defined at OperIdx.
372 /// TODO: Hoist loop induction variable increments. This has to be
373 /// reevaluated. Generally, IV scheduling should be done before coalescing.
374 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
375 const MachineInstr *MI = SU->getInstr();
376 unsigned Reg = MI->getOperand(OperIdx).getReg();
378 // Singly defined vregs do not have output/anti dependencies.
379 // The current operand is a def, so we have at least one.
380 // Check here if there are any others...
381 if (MRI.hasOneDef(Reg))
384 // Add output dependence to the next nearest def of this vreg.
386 // Unless this definition is dead, the output dependence should be
387 // transitively redundant with antidependencies from this definition's
388 // uses. We're conservative for now until we have a way to guarantee the uses
389 // are not eliminated sometime during scheduling. The output dependence edge
390 // is also useful if output latency exceeds def-use latency.
391 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
392 if (DefI == VRegDefs.end())
393 VRegDefs.insert(VReg2SUnit(Reg, SU));
395 SUnit *DefSU = DefI->SU;
396 if (DefSU != SU && DefSU != &ExitSU) {
397 SDep Dep(SU, SDep::Output, Reg);
399 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
406 /// addVRegUseDeps - Add a register data dependency if the instruction that
407 /// defines the virtual register used at OperIdx is mapped to an SUnit. Add a
408 /// register antidependency from this SUnit to instructions that occur later in
409 /// the same scheduling region if they write the virtual register.
411 /// TODO: Handle ExitSU "uses" properly.
412 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
413 MachineInstr *MI = SU->getInstr();
414 unsigned Reg = MI->getOperand(OperIdx).getReg();
416 // Record this local VReg use.
417 VReg2UseMap::iterator UI = VRegUses.find(Reg);
418 for (; UI != VRegUses.end(); ++UI) {
422 if (UI == VRegUses.end())
423 VRegUses.insert(VReg2SUnit(Reg, SU));
425 // Lookup this operand's reaching definition.
426 assert(LIS && "vreg dependencies requires LiveIntervals");
428 = LIS->getInterval(Reg).Query(LIS->getInstructionIndex(MI));
429 VNInfo *VNI = LRQ.valueIn();
431 // VNI will be valid because MachineOperand::readsReg() is checked by caller.
432 assert(VNI && "No value to read by operand");
433 MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def);
434 // Phis and other noninstructions (after coalescing) have a NULL Def.
436 SUnit *DefSU = getSUnit(Def);
438 // The reaching Def lives within this scheduling region.
439 // Create a data dependence.
440 SDep dep(DefSU, SDep::Data, Reg);
441 // Adjust the dependence latency using operand def/use information, then
442 // allow the target to perform its own adjustments.
443 int DefOp = Def->findRegisterDefOperandIdx(Reg);
444 dep.setLatency(SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx));
446 const TargetSubtargetInfo &ST = MF.getSubtarget();
447 ST.adjustSchedDependency(DefSU, SU, const_cast<SDep &>(dep));
452 // Add antidependence to the following def of the vreg it uses.
453 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
454 if (DefI != VRegDefs.end() && DefI->SU != SU)
455 DefI->SU->addPred(SDep(SU, SDep::Anti, Reg));
458 /// Return true if MI is an instruction we are unable to reason about
459 /// (like a call or something with unmodeled side effects).
460 static inline bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) {
461 if (MI->isCall() || MI->hasUnmodeledSideEffects() ||
462 (MI->hasOrderedMemoryRef() &&
463 (!MI->mayLoad() || !MI->isInvariantLoad(AA))))
468 // This MI might have either incomplete info, or known to be unsafe
469 // to deal with (i.e. volatile object).
470 static inline bool isUnsafeMemoryObject(MachineInstr *MI,
471 const MachineFrameInfo *MFI) {
472 if (!MI || MI->memoperands_empty())
474 // We purposefully do no check for hasOneMemOperand() here
475 // in hope to trigger an assert downstream in order to
476 // finish implementation.
477 if ((*MI->memoperands_begin())->isVolatile() ||
478 MI->hasUnmodeledSideEffects())
481 if ((*MI->memoperands_begin())->getPseudoValue()) {
482 // Similarly to getUnderlyingObjectForInstr:
483 // For now, ignore PseudoSourceValues which may alias LLVM IR values
484 // because the code that uses this function has no way to cope with
489 const Value *V = (*MI->memoperands_begin())->getValue();
493 SmallVector<Value *, 4> Objs;
494 getUnderlyingObjects(V, Objs);
495 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(),
496 IE = Objs.end(); I != IE; ++I) {
497 // Does this pointer refer to a distinct and identifiable object?
498 if (!isIdentifiedObject(*I))
505 /// This returns true if the two MIs need a chain edge betwee them.
506 /// If these are not even memory operations, we still may need
507 /// chain deps between them. The question really is - could
508 /// these two MIs be reordered during scheduling from memory dependency
510 static bool MIsNeedChainEdge(AliasAnalysis *AA, const MachineFrameInfo *MFI,
513 const MachineFunction *MF = MIa->getParent()->getParent();
514 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
516 // Cover a trivial case - no edge is need to itself.
520 // Let the target decide if memory accesses cannot possibly overlap.
521 if ((MIa->mayLoad() || MIa->mayStore()) &&
522 (MIb->mayLoad() || MIb->mayStore()))
523 if (TII->areMemAccessesTriviallyDisjoint(MIa, MIb, AA))
526 // FIXME: Need to handle multiple memory operands to support all targets.
527 if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand())
530 if (isUnsafeMemoryObject(MIa, MFI) || isUnsafeMemoryObject(MIb, MFI))
533 // If we are dealing with two "normal" loads, we do not need an edge
534 // between them - they could be reordered.
535 if (!MIa->mayStore() && !MIb->mayStore())
538 // To this point analysis is generic. From here on we do need AA.
542 MachineMemOperand *MMOa = *MIa->memoperands_begin();
543 MachineMemOperand *MMOb = *MIb->memoperands_begin();
545 if (!MMOa->getValue() || !MMOb->getValue())
548 // The following interface to AA is fashioned after DAGCombiner::isAlias
549 // and operates with MachineMemOperand offset with some important
551 // - LLVM fundamentally assumes flat address spaces.
552 // - MachineOperand offset can *only* result from legalization and
553 // cannot affect queries other than the trivial case of overlap
555 // - These offsets never wrap and never step outside
556 // of allocated objects.
557 // - There should never be any negative offsets here.
559 // FIXME: Modify API to hide this math from "user"
560 // FIXME: Even before we go to AA we can reason locally about some
561 // memory objects. It can save compile time, and possibly catch some
562 // corner cases not currently covered.
564 assert ((MMOa->getOffset() >= 0) && "Negative MachineMemOperand offset");
565 assert ((MMOb->getOffset() >= 0) && "Negative MachineMemOperand offset");
567 int64_t MinOffset = std::min(MMOa->getOffset(), MMOb->getOffset());
568 int64_t Overlapa = MMOa->getSize() + MMOa->getOffset() - MinOffset;
569 int64_t Overlapb = MMOb->getSize() + MMOb->getOffset() - MinOffset;
571 AliasAnalysis::AliasResult AAResult = AA->alias(
572 AliasAnalysis::Location(MMOa->getValue(), Overlapa,
573 UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
574 AliasAnalysis::Location(MMOb->getValue(), Overlapb,
575 UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
577 return (AAResult != AliasAnalysis::NoAlias);
580 /// This recursive function iterates over chain deps of SUb looking for
581 /// "latest" node that needs a chain edge to SUa.
583 iterateChainSucc(AliasAnalysis *AA, const MachineFrameInfo *MFI,
584 SUnit *SUa, SUnit *SUb, SUnit *ExitSU, unsigned *Depth,
585 SmallPtrSetImpl<const SUnit*> &Visited) {
586 if (!SUa || !SUb || SUb == ExitSU)
589 // Remember visited nodes.
590 if (!Visited.insert(SUb).second)
592 // If there is _some_ dependency already in place, do not
593 // descend any further.
594 // TODO: Need to make sure that if that dependency got eliminated or ignored
595 // for any reason in the future, we would not violate DAG topology.
596 // Currently it does not happen, but makes an implicit assumption about
597 // future implementation.
599 // Independently, if we encounter node that is some sort of global
600 // object (like a call) we already have full set of dependencies to it
601 // and we can stop descending.
602 if (SUa->isSucc(SUb) ||
603 isGlobalMemoryObject(AA, SUb->getInstr()))
606 // If we do need an edge, or we have exceeded depth budget,
607 // add that edge to the predecessors chain of SUb,
608 // and stop descending.
610 MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) {
611 SUb->addPred(SDep(SUa, SDep::MayAliasMem));
614 // Track current depth.
616 // Iterate over memory dependencies only.
617 for (SUnit::const_succ_iterator I = SUb->Succs.begin(), E = SUb->Succs.end();
619 if (I->isNormalMemoryOrBarrier())
620 iterateChainSucc (AA, MFI, SUa, I->getSUnit(), ExitSU, Depth, Visited);
624 /// This function assumes that "downward" from SU there exist
625 /// tail/leaf of already constructed DAG. It iterates downward and
626 /// checks whether SU can be aliasing any node dominated
628 static void adjustChainDeps(AliasAnalysis *AA, const MachineFrameInfo *MFI,
629 SUnit *SU, SUnit *ExitSU, std::set<SUnit *> &CheckList,
630 unsigned LatencyToLoad) {
634 SmallPtrSet<const SUnit*, 16> Visited;
637 for (std::set<SUnit *>::iterator I = CheckList.begin(), IE = CheckList.end();
641 if (MIsNeedChainEdge(AA, MFI, SU->getInstr(), (*I)->getInstr())) {
642 SDep Dep(SU, SDep::MayAliasMem);
643 Dep.setLatency(((*I)->getInstr()->mayLoad()) ? LatencyToLoad : 0);
647 // Iterate recursively over all previously added memory chain
648 // successors. Keep track of visited nodes.
649 for (SUnit::const_succ_iterator J = (*I)->Succs.begin(),
650 JE = (*I)->Succs.end(); J != JE; ++J)
651 if (J->isNormalMemoryOrBarrier())
652 iterateChainSucc (AA, MFI, SU, J->getSUnit(),
653 ExitSU, &Depth, Visited);
657 /// Check whether two objects need a chain edge, if so, add it
658 /// otherwise remember the rejected SU.
660 void addChainDependency (AliasAnalysis *AA, const MachineFrameInfo *MFI,
661 SUnit *SUa, SUnit *SUb,
662 std::set<SUnit *> &RejectList,
663 unsigned TrueMemOrderLatency = 0,
664 bool isNormalMemory = false) {
665 // If this is a false dependency,
666 // do not add the edge, but rememeber the rejected node.
667 if (MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) {
668 SDep Dep(SUa, isNormalMemory ? SDep::MayAliasMem : SDep::Barrier);
669 Dep.setLatency(TrueMemOrderLatency);
673 // Duplicate entries should be ignored.
674 RejectList.insert(SUb);
675 DEBUG(dbgs() << "\tReject chain dep between SU("
676 << SUa->NodeNum << ") and SU("
677 << SUb->NodeNum << ")\n");
681 /// Create an SUnit for each real instruction, numbered in top-down toplological
682 /// order. The instruction order A < B, implies that no edge exists from B to A.
684 /// Map each real instruction to its SUnit.
686 /// After initSUnits, the SUnits vector cannot be resized and the scheduler may
687 /// hang onto SUnit pointers. We may relax this in the future by using SUnit IDs
688 /// instead of pointers.
690 /// MachineScheduler relies on initSUnits numbering the nodes by their order in
691 /// the original instruction list.
692 void ScheduleDAGInstrs::initSUnits() {
693 // We'll be allocating one SUnit for each real instruction in the region,
694 // which is contained within a basic block.
695 SUnits.reserve(NumRegionInstrs);
697 for (MachineBasicBlock::iterator I = RegionBegin; I != RegionEnd; ++I) {
698 MachineInstr *MI = I;
699 if (MI->isDebugValue())
702 SUnit *SU = newSUnit(MI);
705 SU->isCall = MI->isCall();
706 SU->isCommutable = MI->isCommutable();
708 // Assign the Latency field of SU using target-provided information.
709 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
711 // If this SUnit uses a reserved or unbuffered resource, mark it as such.
713 // Reserved resources block an instruction from issuing and stall the
714 // entire pipeline. These are identified by BufferSize=0.
716 // Unbuffered resources prevent execution of subsequent instructions that
717 // require the same resources. This is used for in-order execution pipelines
718 // within an out-of-order core. These are identified by BufferSize=1.
719 if (SchedModel.hasInstrSchedModel()) {
720 const MCSchedClassDesc *SC = getSchedClass(SU);
721 for (TargetSchedModel::ProcResIter
722 PI = SchedModel.getWriteProcResBegin(SC),
723 PE = SchedModel.getWriteProcResEnd(SC); PI != PE; ++PI) {
724 switch (SchedModel.getProcResource(PI->ProcResourceIdx)->BufferSize) {
726 SU->hasReservedResource = true;
729 SU->isUnbuffered = true;
739 /// If RegPressure is non-null, compute register pressure as a side effect. The
740 /// DAG builder is an efficient place to do it because it already visits
742 void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
743 RegPressureTracker *RPTracker,
744 PressureDiffs *PDiffs) {
745 const TargetSubtargetInfo &ST = MF.getSubtarget();
746 bool UseAA = EnableAASchedMI.getNumOccurrences() > 0 ? EnableAASchedMI
748 AliasAnalysis *AAForDep = UseAA ? AA : nullptr;
751 ScheduleDAG::clearDAG();
753 // Create an SUnit for each real instruction.
757 PDiffs->init(SUnits.size());
759 // We build scheduling units by walking a block's instruction list from bottom
762 // Remember where a generic side-effecting instruction is as we procede.
763 SUnit *BarrierChain = nullptr, *AliasChain = nullptr;
765 // Memory references to specific known memory locations are tracked
766 // so that they can be given more precise dependencies. We track
767 // separately the known memory locations that may alias and those
768 // that are known not to alias
769 MapVector<ValueType, std::vector<SUnit *> > AliasMemDefs, NonAliasMemDefs;
770 MapVector<ValueType, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses;
771 std::set<SUnit*> RejectMemNodes;
773 // Remove any stale debug info; sometimes BuildSchedGraph is called again
774 // without emitting the info from the previous call.
776 FirstDbgValue = nullptr;
778 assert(Defs.empty() && Uses.empty() &&
779 "Only BuildGraph should update Defs/Uses");
780 Defs.setUniverse(TRI->getNumRegs());
781 Uses.setUniverse(TRI->getNumRegs());
783 assert(VRegDefs.empty() && "Only BuildSchedGraph may access VRegDefs");
785 VRegDefs.setUniverse(MRI.getNumVirtRegs());
786 VRegUses.setUniverse(MRI.getNumVirtRegs());
788 // Model data dependencies between instructions being scheduled and the
790 addSchedBarrierDeps();
792 // Walk the list of instructions, from bottom moving up.
793 MachineInstr *DbgMI = nullptr;
794 for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
796 MachineInstr *MI = std::prev(MII);
798 DbgValues.push_back(std::make_pair(DbgMI, MI));
802 if (MI->isDebugValue()) {
806 SUnit *SU = MISUnitMap[MI];
807 assert(SU && "No SUnit mapped to this MI");
810 PressureDiff *PDiff = PDiffs ? &(*PDiffs)[SU->NodeNum] : nullptr;
811 RPTracker->recede(/*LiveUses=*/nullptr, PDiff);
812 assert(RPTracker->getPos() == std::prev(MII) &&
813 "RPTracker can't find MI");
817 (CanHandleTerminators || (!MI->isTerminator() && !MI->isPosition())) &&
818 "Cannot schedule terminators or labels!");
820 // Add register-based dependencies (data, anti, and output).
821 bool HasVRegDef = false;
822 for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
823 const MachineOperand &MO = MI->getOperand(j);
824 if (!MO.isReg()) continue;
825 unsigned Reg = MO.getReg();
826 if (Reg == 0) continue;
828 if (TRI->isPhysicalRegister(Reg))
829 addPhysRegDeps(SU, j);
831 assert(!IsPostRA && "Virtual register encountered!");
834 addVRegDefDeps(SU, j);
836 else if (MO.readsReg()) // ignore undef operands
837 addVRegUseDeps(SU, j);
840 // If we haven't seen any uses in this scheduling region, create a
841 // dependence edge to ExitSU to model the live-out latency. This is required
842 // for vreg defs with no in-region use, and prefetches with no vreg def.
844 // FIXME: NumDataSuccs would be more precise than NumSuccs here. This
845 // check currently relies on being called before adding chain deps.
846 if (SU->NumSuccs == 0 && SU->Latency > 1
847 && (HasVRegDef || MI->mayLoad())) {
848 SDep Dep(SU, SDep::Artificial);
849 Dep.setLatency(SU->Latency - 1);
853 // Add chain dependencies.
854 // Chain dependencies used to enforce memory order should have
855 // latency of 0 (except for true dependency of Store followed by
856 // aliased Load... we estimate that with a single cycle of latency
857 // assuming the hardware will bypass)
858 // Note that isStoreToStackSlot and isLoadFromStackSLot are not usable
859 // after stack slots are lowered to actual addresses.
860 // TODO: Use an AliasAnalysis and do real alias-analysis queries, and
861 // produce more precise dependence information.
862 unsigned TrueMemOrderLatency = MI->mayStore() ? 1 : 0;
863 if (isGlobalMemoryObject(AA, MI)) {
864 // Be conservative with these and add dependencies on all memory
865 // references, even those that are known to not alias.
866 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
867 NonAliasMemDefs.begin(), E = NonAliasMemDefs.end(); I != E; ++I) {
868 for (unsigned i = 0, e = I->second.size(); i != e; ++i) {
869 I->second[i]->addPred(SDep(SU, SDep::Barrier));
872 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
873 NonAliasMemUses.begin(), E = NonAliasMemUses.end(); I != E; ++I) {
874 for (unsigned i = 0, e = I->second.size(); i != e; ++i) {
875 SDep Dep(SU, SDep::Barrier);
876 Dep.setLatency(TrueMemOrderLatency);
877 I->second[i]->addPred(Dep);
880 // Add SU to the barrier chain.
882 BarrierChain->addPred(SDep(SU, SDep::Barrier));
884 // This is a barrier event that acts as a pivotal node in the DAG,
885 // so it is safe to clear list of exposed nodes.
886 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
887 TrueMemOrderLatency);
888 RejectMemNodes.clear();
889 NonAliasMemDefs.clear();
890 NonAliasMemUses.clear();
894 // Chain all possibly aliasing memory references through SU.
896 unsigned ChainLatency = 0;
897 if (AliasChain->getInstr()->mayLoad())
898 ChainLatency = TrueMemOrderLatency;
899 addChainDependency(AAForDep, MFI, SU, AliasChain, RejectMemNodes,
903 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
904 addChainDependency(AAForDep, MFI, SU, PendingLoads[k], RejectMemNodes,
905 TrueMemOrderLatency);
906 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
907 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I) {
908 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
909 addChainDependency(AAForDep, MFI, SU, I->second[i], RejectMemNodes);
911 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
912 AliasMemUses.begin(), E = AliasMemUses.end(); I != E; ++I) {
913 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
914 addChainDependency(AAForDep, MFI, SU, I->second[i], RejectMemNodes,
915 TrueMemOrderLatency);
917 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
918 TrueMemOrderLatency);
919 PendingLoads.clear();
920 AliasMemDefs.clear();
921 AliasMemUses.clear();
922 } else if (MI->mayStore()) {
923 // Add dependence on barrier chain, if needed.
924 // There is no point to check aliasing on barrier event. Even if
925 // SU and barrier _could_ be reordered, they should not. In addition,
926 // we have lost all RejectMemNodes below barrier.
928 BarrierChain->addPred(SDep(SU, SDep::Barrier));
930 UnderlyingObjectsVector Objs;
931 getUnderlyingObjectsForInstr(MI, MFI, Objs);
934 // Treat all other stores conservatively.
935 goto new_alias_chain;
938 bool MayAlias = false;
939 for (UnderlyingObjectsVector::iterator K = Objs.begin(), KE = Objs.end();
941 ValueType V = K->getPointer();
942 bool ThisMayAlias = K->getInt();
946 // A store to a specific PseudoSourceValue. Add precise dependencies.
947 // Record the def in MemDefs, first adding a dep if there is
949 MapVector<ValueType, std::vector<SUnit *> >::iterator I =
950 ((ThisMayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
951 MapVector<ValueType, std::vector<SUnit *> >::iterator IE =
952 ((ThisMayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
954 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
955 addChainDependency(AAForDep, MFI, SU, I->second[i], RejectMemNodes,
958 // If we're not using AA, then we only need one store per object.
961 I->second.push_back(SU);
965 AliasMemDefs[V].clear();
966 AliasMemDefs[V].push_back(SU);
969 NonAliasMemDefs[V].clear();
970 NonAliasMemDefs[V].push_back(SU);
973 // Handle the uses in MemUses, if there are any.
974 MapVector<ValueType, std::vector<SUnit *> >::iterator J =
975 ((ThisMayAlias) ? AliasMemUses.find(V) : NonAliasMemUses.find(V));
976 MapVector<ValueType, std::vector<SUnit *> >::iterator JE =
977 ((ThisMayAlias) ? AliasMemUses.end() : NonAliasMemUses.end());
979 for (unsigned i = 0, e = J->second.size(); i != e; ++i)
980 addChainDependency(AAForDep, MFI, SU, J->second[i], RejectMemNodes,
981 TrueMemOrderLatency, true);
986 // Add dependencies from all the PendingLoads, i.e. loads
987 // with no underlying object.
988 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
989 addChainDependency(AAForDep, MFI, SU, PendingLoads[k], RejectMemNodes,
990 TrueMemOrderLatency);
991 // Add dependence on alias chain, if needed.
993 addChainDependency(AAForDep, MFI, SU, AliasChain, RejectMemNodes);
995 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
996 TrueMemOrderLatency);
997 } else if (MI->mayLoad()) {
998 bool MayAlias = true;
999 if (MI->isInvariantLoad(AA)) {
1000 // Invariant load, no chain dependencies needed!
1002 UnderlyingObjectsVector Objs;
1003 getUnderlyingObjectsForInstr(MI, MFI, Objs);
1006 // A load with no underlying object. Depend on all
1007 // potentially aliasing stores.
1008 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
1009 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I)
1010 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
1011 addChainDependency(AAForDep, MFI, SU, I->second[i],
1014 PendingLoads.push_back(SU);
1020 for (UnderlyingObjectsVector::iterator
1021 J = Objs.begin(), JE = Objs.end(); J != JE; ++J) {
1022 ValueType V = J->getPointer();
1023 bool ThisMayAlias = J->getInt();
1028 // A load from a specific PseudoSourceValue. Add precise dependencies.
1029 MapVector<ValueType, std::vector<SUnit *> >::iterator I =
1030 ((ThisMayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
1031 MapVector<ValueType, std::vector<SUnit *> >::iterator IE =
1032 ((ThisMayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
1034 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
1035 addChainDependency(AAForDep, MFI, SU, I->second[i],
1036 RejectMemNodes, 0, true);
1038 AliasMemUses[V].push_back(SU);
1040 NonAliasMemUses[V].push_back(SU);
1043 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes, /*Latency=*/0);
1044 // Add dependencies on alias and barrier chains, if needed.
1045 if (MayAlias && AliasChain)
1046 addChainDependency(AAForDep, MFI, SU, AliasChain, RejectMemNodes);
1048 BarrierChain->addPred(SDep(SU, SDep::Barrier));
1053 FirstDbgValue = DbgMI;
1058 PendingLoads.clear();
1061 /// \brief Initialize register live-range state for updating kills.
1062 void ScheduleDAGInstrs::startBlockForKills(MachineBasicBlock *BB) {
1063 // Start with no live registers.
1066 // Examine the live-in regs of all successors.
1067 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
1068 SE = BB->succ_end(); SI != SE; ++SI) {
1069 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
1070 E = (*SI)->livein_end(); I != E; ++I) {
1072 // Repeat, for reg and all subregs.
1073 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1074 SubRegs.isValid(); ++SubRegs)
1075 LiveRegs.set(*SubRegs);
1080 bool ScheduleDAGInstrs::toggleKillFlag(MachineInstr *MI, MachineOperand &MO) {
1081 // Setting kill flag...
1087 // If MO itself is live, clear the kill flag...
1088 if (LiveRegs.test(MO.getReg())) {
1089 MO.setIsKill(false);
1093 // If any subreg of MO is live, then create an imp-def for that
1094 // subreg and keep MO marked as killed.
1095 MO.setIsKill(false);
1096 bool AllDead = true;
1097 const unsigned SuperReg = MO.getReg();
1098 MachineInstrBuilder MIB(MF, MI);
1099 for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) {
1100 if (LiveRegs.test(*SubRegs)) {
1101 MIB.addReg(*SubRegs, RegState::ImplicitDefine);
1111 // FIXME: Reuse the LivePhysRegs utility for this.
1112 void ScheduleDAGInstrs::fixupKills(MachineBasicBlock *MBB) {
1113 DEBUG(dbgs() << "Fixup kills for BB#" << MBB->getNumber() << '\n');
1115 LiveRegs.resize(TRI->getNumRegs());
1116 BitVector killedRegs(TRI->getNumRegs());
1118 startBlockForKills(MBB);
1120 // Examine block from end to start...
1121 unsigned Count = MBB->size();
1122 for (MachineBasicBlock::iterator I = MBB->end(), E = MBB->begin();
1124 MachineInstr *MI = --I;
1125 if (MI->isDebugValue())
1128 // Update liveness. Registers that are defed but not used in this
1129 // instruction are now dead. Mark register and all subregs as they
1130 // are completely defined.
1131 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1132 MachineOperand &MO = MI->getOperand(i);
1134 LiveRegs.clearBitsNotInMask(MO.getRegMask());
1135 if (!MO.isReg()) continue;
1136 unsigned Reg = MO.getReg();
1137 if (Reg == 0) continue;
1138 if (!MO.isDef()) continue;
1139 // Ignore two-addr defs.
1140 if (MI->isRegTiedToUseOperand(i)) continue;
1142 // Repeat for reg and all subregs.
1143 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1144 SubRegs.isValid(); ++SubRegs)
1145 LiveRegs.reset(*SubRegs);
1148 // Examine all used registers and set/clear kill flag. When a
1149 // register is used multiple times we only set the kill flag on
1150 // the first use. Don't set kill flags on undef operands.
1152 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1153 MachineOperand &MO = MI->getOperand(i);
1154 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
1155 unsigned Reg = MO.getReg();
1156 if ((Reg == 0) || MRI.isReserved(Reg)) continue;
1159 if (!killedRegs.test(Reg)) {
1161 // A register is not killed if any subregs are live...
1162 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
1163 if (LiveRegs.test(*SubRegs)) {
1169 // If subreg is not live, then register is killed if it became
1170 // live in this instruction
1172 kill = !LiveRegs.test(Reg);
1175 if (MO.isKill() != kill) {
1176 DEBUG(dbgs() << "Fixing " << MO << " in ");
1177 // Warning: toggleKillFlag may invalidate MO.
1178 toggleKillFlag(MI, MO);
1182 killedRegs.set(Reg);
1185 // Mark any used register (that is not using undef) and subregs as
1187 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1188 MachineOperand &MO = MI->getOperand(i);
1189 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
1190 unsigned Reg = MO.getReg();
1191 if ((Reg == 0) || MRI.isReserved(Reg)) continue;
1193 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1194 SubRegs.isValid(); ++SubRegs)
1195 LiveRegs.set(*SubRegs);
1200 void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
1201 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1202 SU->getInstr()->dump();
1206 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
1208 raw_string_ostream oss(s);
1211 else if (SU == &ExitSU)
1214 SU->getInstr()->print(oss, &TM, /*SkipOpers=*/true);
1218 /// Return the basic block label. It is not necessarilly unique because a block
1219 /// contains multiple scheduling regions. But it is fine for visualization.
1220 std::string ScheduleDAGInstrs::getDAGName() const {
1221 return "dag." + BB->getFullName();
1224 //===----------------------------------------------------------------------===//
1225 // SchedDFSResult Implementation
1226 //===----------------------------------------------------------------------===//
1229 /// \brief Internal state used to compute SchedDFSResult.
1230 class SchedDFSImpl {
1233 /// Join DAG nodes into equivalence classes by their subtree.
1234 IntEqClasses SubtreeClasses;
1235 /// List PredSU, SuccSU pairs that represent data edges between subtrees.
1236 std::vector<std::pair<const SUnit*, const SUnit*> > ConnectionPairs;
1240 unsigned ParentNodeID; // Parent node (member of the parent subtree).
1241 unsigned SubInstrCount; // Instr count in this tree only, not children.
1243 RootData(unsigned id): NodeID(id),
1244 ParentNodeID(SchedDFSResult::InvalidSubtreeID),
1247 unsigned getSparseSetIndex() const { return NodeID; }
1250 SparseSet<RootData> RootSet;
1253 SchedDFSImpl(SchedDFSResult &r): R(r), SubtreeClasses(R.DFSNodeData.size()) {
1254 RootSet.setUniverse(R.DFSNodeData.size());
1257 /// Return true if this node been visited by the DFS traversal.
1259 /// During visitPostorderNode the Node's SubtreeID is assigned to the Node
1260 /// ID. Later, SubtreeID is updated but remains valid.
1261 bool isVisited(const SUnit *SU) const {
1262 return R.DFSNodeData[SU->NodeNum].SubtreeID
1263 != SchedDFSResult::InvalidSubtreeID;
1266 /// Initialize this node's instruction count. We don't need to flag the node
1267 /// visited until visitPostorder because the DAG cannot have cycles.
1268 void visitPreorder(const SUnit *SU) {
1269 R.DFSNodeData[SU->NodeNum].InstrCount =
1270 SU->getInstr()->isTransient() ? 0 : 1;
1273 /// Called once for each node after all predecessors are visited. Revisit this
1274 /// node's predecessors and potentially join them now that we know the ILP of
1275 /// the other predecessors.
1276 void visitPostorderNode(const SUnit *SU) {
1277 // Mark this node as the root of a subtree. It may be joined with its
1278 // successors later.
1279 R.DFSNodeData[SU->NodeNum].SubtreeID = SU->NodeNum;
1280 RootData RData(SU->NodeNum);
1281 RData.SubInstrCount = SU->getInstr()->isTransient() ? 0 : 1;
1283 // If any predecessors are still in their own subtree, they either cannot be
1284 // joined or are large enough to remain separate. If this parent node's
1285 // total instruction count is not greater than a child subtree by at least
1286 // the subtree limit, then try to join it now since splitting subtrees is
1287 // only useful if multiple high-pressure paths are possible.
1288 unsigned InstrCount = R.DFSNodeData[SU->NodeNum].InstrCount;
1289 for (SUnit::const_pred_iterator
1290 PI = SU->Preds.begin(), PE = SU->Preds.end(); PI != PE; ++PI) {
1291 if (PI->getKind() != SDep::Data)
1293 unsigned PredNum = PI->getSUnit()->NodeNum;
1294 if ((InstrCount - R.DFSNodeData[PredNum].InstrCount) < R.SubtreeLimit)
1295 joinPredSubtree(*PI, SU, /*CheckLimit=*/false);
1297 // Either link or merge the TreeData entry from the child to the parent.
1298 if (R.DFSNodeData[PredNum].SubtreeID == PredNum) {
1299 // If the predecessor's parent is invalid, this is a tree edge and the
1300 // current node is the parent.
1301 if (RootSet[PredNum].ParentNodeID == SchedDFSResult::InvalidSubtreeID)
1302 RootSet[PredNum].ParentNodeID = SU->NodeNum;
1304 else if (RootSet.count(PredNum)) {
1305 // The predecessor is not a root, but is still in the root set. This
1306 // must be the new parent that it was just joined to. Note that
1307 // RootSet[PredNum].ParentNodeID may either be invalid or may still be
1308 // set to the original parent.
1309 RData.SubInstrCount += RootSet[PredNum].SubInstrCount;
1310 RootSet.erase(PredNum);
1313 RootSet[SU->NodeNum] = RData;
1316 /// Called once for each tree edge after calling visitPostOrderNode on the
1317 /// predecessor. Increment the parent node's instruction count and
1318 /// preemptively join this subtree to its parent's if it is small enough.
1319 void visitPostorderEdge(const SDep &PredDep, const SUnit *Succ) {
1320 R.DFSNodeData[Succ->NodeNum].InstrCount
1321 += R.DFSNodeData[PredDep.getSUnit()->NodeNum].InstrCount;
1322 joinPredSubtree(PredDep, Succ);
1325 /// Add a connection for cross edges.
1326 void visitCrossEdge(const SDep &PredDep, const SUnit *Succ) {
1327 ConnectionPairs.push_back(std::make_pair(PredDep.getSUnit(), Succ));
1330 /// Set each node's subtree ID to the representative ID and record connections
1333 SubtreeClasses.compress();
1334 R.DFSTreeData.resize(SubtreeClasses.getNumClasses());
1335 assert(SubtreeClasses.getNumClasses() == RootSet.size()
1336 && "number of roots should match trees");
1337 for (SparseSet<RootData>::const_iterator
1338 RI = RootSet.begin(), RE = RootSet.end(); RI != RE; ++RI) {
1339 unsigned TreeID = SubtreeClasses[RI->NodeID];
1340 if (RI->ParentNodeID != SchedDFSResult::InvalidSubtreeID)
1341 R.DFSTreeData[TreeID].ParentTreeID = SubtreeClasses[RI->ParentNodeID];
1342 R.DFSTreeData[TreeID].SubInstrCount = RI->SubInstrCount;
1343 // Note that SubInstrCount may be greater than InstrCount if we joined
1344 // subtrees across a cross edge. InstrCount will be attributed to the
1345 // original parent, while SubInstrCount will be attributed to the joined
1348 R.SubtreeConnections.resize(SubtreeClasses.getNumClasses());
1349 R.SubtreeConnectLevels.resize(SubtreeClasses.getNumClasses());
1350 DEBUG(dbgs() << R.getNumSubtrees() << " subtrees:\n");
1351 for (unsigned Idx = 0, End = R.DFSNodeData.size(); Idx != End; ++Idx) {
1352 R.DFSNodeData[Idx].SubtreeID = SubtreeClasses[Idx];
1353 DEBUG(dbgs() << " SU(" << Idx << ") in tree "
1354 << R.DFSNodeData[Idx].SubtreeID << '\n');
1356 for (std::vector<std::pair<const SUnit*, const SUnit*> >::const_iterator
1357 I = ConnectionPairs.begin(), E = ConnectionPairs.end();
1359 unsigned PredTree = SubtreeClasses[I->first->NodeNum];
1360 unsigned SuccTree = SubtreeClasses[I->second->NodeNum];
1361 if (PredTree == SuccTree)
1363 unsigned Depth = I->first->getDepth();
1364 addConnection(PredTree, SuccTree, Depth);
1365 addConnection(SuccTree, PredTree, Depth);
1370 /// Join the predecessor subtree with the successor that is its DFS
1371 /// parent. Apply some heuristics before joining.
1372 bool joinPredSubtree(const SDep &PredDep, const SUnit *Succ,
1373 bool CheckLimit = true) {
1374 assert(PredDep.getKind() == SDep::Data && "Subtrees are for data edges");
1376 // Check if the predecessor is already joined.
1377 const SUnit *PredSU = PredDep.getSUnit();
1378 unsigned PredNum = PredSU->NodeNum;
1379 if (R.DFSNodeData[PredNum].SubtreeID != PredNum)
1382 // Four is the magic number of successors before a node is considered a
1384 unsigned NumDataSucs = 0;
1385 for (SUnit::const_succ_iterator SI = PredSU->Succs.begin(),
1386 SE = PredSU->Succs.end(); SI != SE; ++SI) {
1387 if (SI->getKind() == SDep::Data) {
1388 if (++NumDataSucs >= 4)
1392 if (CheckLimit && R.DFSNodeData[PredNum].InstrCount > R.SubtreeLimit)
1394 R.DFSNodeData[PredNum].SubtreeID = Succ->NodeNum;
1395 SubtreeClasses.join(Succ->NodeNum, PredNum);
1399 /// Called by finalize() to record a connection between trees.
1400 void addConnection(unsigned FromTree, unsigned ToTree, unsigned Depth) {
1405 SmallVectorImpl<SchedDFSResult::Connection> &Connections =
1406 R.SubtreeConnections[FromTree];
1407 for (SmallVectorImpl<SchedDFSResult::Connection>::iterator
1408 I = Connections.begin(), E = Connections.end(); I != E; ++I) {
1409 if (I->TreeID == ToTree) {
1410 I->Level = std::max(I->Level, Depth);
1414 Connections.push_back(SchedDFSResult::Connection(ToTree, Depth));
1415 FromTree = R.DFSTreeData[FromTree].ParentTreeID;
1416 } while (FromTree != SchedDFSResult::InvalidSubtreeID);
1422 /// \brief Manage the stack used by a reverse depth-first search over the DAG.
1423 class SchedDAGReverseDFS {
1424 std::vector<std::pair<const SUnit*, SUnit::const_pred_iterator> > DFSStack;
1426 bool isComplete() const { return DFSStack.empty(); }
1428 void follow(const SUnit *SU) {
1429 DFSStack.push_back(std::make_pair(SU, SU->Preds.begin()));
1431 void advance() { ++DFSStack.back().second; }
1433 const SDep *backtrack() {
1434 DFSStack.pop_back();
1435 return DFSStack.empty() ? nullptr : std::prev(DFSStack.back().second);
1438 const SUnit *getCurr() const { return DFSStack.back().first; }
1440 SUnit::const_pred_iterator getPred() const { return DFSStack.back().second; }
1442 SUnit::const_pred_iterator getPredEnd() const {
1443 return getCurr()->Preds.end();
1448 static bool hasDataSucc(const SUnit *SU) {
1449 for (SUnit::const_succ_iterator
1450 SI = SU->Succs.begin(), SE = SU->Succs.end(); SI != SE; ++SI) {
1451 if (SI->getKind() == SDep::Data && !SI->getSUnit()->isBoundaryNode())
1457 /// Compute an ILP metric for all nodes in the subDAG reachable via depth-first
1458 /// search from this root.
1459 void SchedDFSResult::compute(ArrayRef<SUnit> SUnits) {
1461 llvm_unreachable("Top-down ILP metric is unimplemnted");
1463 SchedDFSImpl Impl(*this);
1464 for (ArrayRef<SUnit>::const_iterator
1465 SI = SUnits.begin(), SE = SUnits.end(); SI != SE; ++SI) {
1466 const SUnit *SU = &*SI;
1467 if (Impl.isVisited(SU) || hasDataSucc(SU))
1470 SchedDAGReverseDFS DFS;
1471 Impl.visitPreorder(SU);
1474 // Traverse the leftmost path as far as possible.
1475 while (DFS.getPred() != DFS.getPredEnd()) {
1476 const SDep &PredDep = *DFS.getPred();
1478 // Ignore non-data edges.
1479 if (PredDep.getKind() != SDep::Data
1480 || PredDep.getSUnit()->isBoundaryNode()) {
1483 // An already visited edge is a cross edge, assuming an acyclic DAG.
1484 if (Impl.isVisited(PredDep.getSUnit())) {
1485 Impl.visitCrossEdge(PredDep, DFS.getCurr());
1488 Impl.visitPreorder(PredDep.getSUnit());
1489 DFS.follow(PredDep.getSUnit());
1491 // Visit the top of the stack in postorder and backtrack.
1492 const SUnit *Child = DFS.getCurr();
1493 const SDep *PredDep = DFS.backtrack();
1494 Impl.visitPostorderNode(Child);
1496 Impl.visitPostorderEdge(*PredDep, DFS.getCurr());
1497 if (DFS.isComplete())
1504 /// The root of the given SubtreeID was just scheduled. For all subtrees
1505 /// connected to this tree, record the depth of the connection so that the
1506 /// nearest connected subtrees can be prioritized.
1507 void SchedDFSResult::scheduleTree(unsigned SubtreeID) {
1508 for (SmallVectorImpl<Connection>::const_iterator
1509 I = SubtreeConnections[SubtreeID].begin(),
1510 E = SubtreeConnections[SubtreeID].end(); I != E; ++I) {
1511 SubtreeConnectLevels[I->TreeID] =
1512 std::max(SubtreeConnectLevels[I->TreeID], I->Level);
1513 DEBUG(dbgs() << " Tree: " << I->TreeID
1514 << " @" << SubtreeConnectLevels[I->TreeID] << '\n');
1519 void ILPValue::print(raw_ostream &OS) const {
1520 OS << InstrCount << " / " << Length << " = ";
1524 OS << format("%g", ((double)InstrCount / Length));
1528 void ILPValue::dump() const {
1529 dbgs() << *this << '\n';
1535 raw_ostream &operator<<(raw_ostream &OS, const ILPValue &Val) {