1 //===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the ScheduleDAGInstrs class, which implements re-scheduling
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "sched-instrs"
16 #include "llvm/Operator.h"
17 #include "llvm/Analysis/AliasAnalysis.h"
18 #include "llvm/Analysis/ValueTracking.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineMemOperand.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/CodeGen/RegisterPressure.h"
25 #include "llvm/CodeGen/ScheduleDAGILP.h"
26 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
27 #include "llvm/MC/MCInstrItineraries.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetRegisterInfo.h"
31 #include "llvm/Target/TargetSubtargetInfo.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/Format.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/ADT/SmallSet.h"
37 #include "llvm/ADT/SmallPtrSet.h"
40 static cl::opt<bool> EnableAASchedMI("enable-aa-sched-mi", cl::Hidden,
41 cl::ZeroOrMore, cl::init(false),
42 cl::desc("Enable use of AA during MI GAD construction"));
44 ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
45 const MachineLoopInfo &mli,
46 const MachineDominatorTree &mdt,
49 : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()), LIS(lis),
50 IsPostRA(IsPostRAFlag), CanHandleTerminators(false), FirstDbgValue(0) {
51 assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
53 assert(!(IsPostRA && MRI.getNumVirtRegs()) &&
54 "Virtual registers must be removed prior to PostRA scheduling");
56 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
57 SchedModel.init(*ST.getSchedModel(), &ST, TII);
60 /// getUnderlyingObjectFromInt - This is the function that does the work of
61 /// looking through basic ptrtoint+arithmetic+inttoptr sequences.
62 static const Value *getUnderlyingObjectFromInt(const Value *V) {
64 if (const Operator *U = dyn_cast<Operator>(V)) {
65 // If we find a ptrtoint, we can transfer control back to the
66 // regular getUnderlyingObjectFromInt.
67 if (U->getOpcode() == Instruction::PtrToInt)
68 return U->getOperand(0);
69 // If we find an add of a constant or a multiplied value, it's
70 // likely that the other operand will lead us to the base
71 // object. We don't have to worry about the case where the
72 // object address is somehow being computed by the multiply,
73 // because our callers only care when the result is an
74 // identifibale object.
75 if (U->getOpcode() != Instruction::Add ||
76 (!isa<ConstantInt>(U->getOperand(1)) &&
77 Operator::getOpcode(U->getOperand(1)) != Instruction::Mul))
83 assert(V->getType()->isIntegerTy() && "Unexpected operand type!");
87 /// getUnderlyingObject - This is a wrapper around GetUnderlyingObject
88 /// and adds support for basic ptrtoint+arithmetic+inttoptr sequences.
89 static const Value *getUnderlyingObject(const Value *V) {
90 // First just call Value::getUnderlyingObject to let it do what it does.
92 V = GetUnderlyingObject(V);
93 // If it found an inttoptr, use special code to continue climing.
94 if (Operator::getOpcode(V) != Instruction::IntToPtr)
96 const Value *O = getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0));
97 // If that succeeded in finding a pointer, continue the search.
98 if (!O->getType()->isPointerTy())
105 /// getUnderlyingObjectForInstr - If this machine instr has memory reference
106 /// information and it can be tracked to a normal reference to a known
107 /// object, return the Value for that object. Otherwise return null.
108 static const Value *getUnderlyingObjectForInstr(const MachineInstr *MI,
109 const MachineFrameInfo *MFI,
112 if (!MI->hasOneMemOperand() ||
113 !(*MI->memoperands_begin())->getValue() ||
114 (*MI->memoperands_begin())->isVolatile())
117 const Value *V = (*MI->memoperands_begin())->getValue();
121 V = getUnderlyingObject(V);
122 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
123 // For now, ignore PseudoSourceValues which may alias LLVM IR values
124 // because the code that uses this function has no way to cope with
126 if (PSV->isAliased(MFI))
129 MayAlias = PSV->mayAlias(MFI);
133 if (isIdentifiedObject(V))
139 void ScheduleDAGInstrs::startBlock(MachineBasicBlock *bb) {
143 void ScheduleDAGInstrs::finishBlock() {
144 // Subclasses should no longer refer to the old block.
148 /// Initialize the map with the number of registers.
149 void Reg2SUnitsMap::setRegLimit(unsigned Limit) {
150 PhysRegSet.setUniverse(Limit);
151 SUnits.resize(Limit);
154 /// Clear the map without deallocating storage.
155 void Reg2SUnitsMap::clear() {
156 for (const_iterator I = reg_begin(), E = reg_end(); I != E; ++I) {
162 /// Initialize the DAG and common scheduler state for the current scheduling
163 /// region. This does not actually create the DAG, only clears it. The
164 /// scheduling driver may call BuildSchedGraph multiple times per scheduling
166 void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb,
167 MachineBasicBlock::iterator begin,
168 MachineBasicBlock::iterator end,
170 assert(bb == BB && "startBlock should set BB");
176 ScheduleDAG::clearDAG();
179 /// Close the current scheduling region. Don't clear any state in case the
180 /// driver wants to refer to the previous scheduling region.
181 void ScheduleDAGInstrs::exitRegion() {
185 /// addSchedBarrierDeps - Add dependencies from instructions in the current
186 /// list of instructions being scheduled to scheduling barrier by adding
187 /// the exit SU to the register defs and use list. This is because we want to
188 /// make sure instructions which define registers that are either used by
189 /// the terminator or are live-out are properly scheduled. This is
190 /// especially important when the definition latency of the return value(s)
191 /// are too high to be hidden by the branch or when the liveout registers
192 /// used by instructions in the fallthrough block.
193 void ScheduleDAGInstrs::addSchedBarrierDeps() {
194 MachineInstr *ExitMI = RegionEnd != BB->end() ? &*RegionEnd : 0;
195 ExitSU.setInstr(ExitMI);
196 bool AllDepKnown = ExitMI &&
197 (ExitMI->isCall() || ExitMI->isBarrier());
198 if (ExitMI && AllDepKnown) {
199 // If it's a call or a barrier, add dependencies on the defs and uses of
201 for (unsigned i = 0, e = ExitMI->getNumOperands(); i != e; ++i) {
202 const MachineOperand &MO = ExitMI->getOperand(i);
203 if (!MO.isReg() || MO.isDef()) continue;
204 unsigned Reg = MO.getReg();
205 if (Reg == 0) continue;
207 if (TRI->isPhysicalRegister(Reg))
208 Uses[Reg].push_back(PhysRegSUOper(&ExitSU, -1));
210 assert(!IsPostRA && "Virtual register encountered after regalloc.");
211 addVRegUseDeps(&ExitSU, i);
215 // For others, e.g. fallthrough, conditional branch, assume the exit
216 // uses all the registers that are livein to the successor blocks.
217 assert(Uses.empty() && "Uses in set before adding deps?");
218 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
219 SE = BB->succ_end(); SI != SE; ++SI)
220 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
221 E = (*SI)->livein_end(); I != E; ++I) {
223 if (!Uses.contains(Reg))
224 Uses[Reg].push_back(PhysRegSUOper(&ExitSU, -1));
229 /// MO is an operand of SU's instruction that defines a physical register. Add
230 /// data dependencies from SU to any uses of the physical register.
231 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
232 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
233 assert(MO.isDef() && "expect physreg def");
235 // Ask the target if address-backscheduling is desirable, and if so how much.
236 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
238 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
239 Alias.isValid(); ++Alias) {
240 if (!Uses.contains(*Alias))
242 std::vector<PhysRegSUOper> &UseList = Uses[*Alias];
243 for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
244 SUnit *UseSU = UseList[i].SU;
248 SDep dep(SU, SDep::Data, 1, *Alias);
250 // Adjust the dependence latency using operand def/use information,
251 // then allow the target to perform its own adjustments.
252 int UseOp = UseList[i].OpIdx;
253 MachineInstr *RegUse = UseOp < 0 ? 0 : UseSU->getInstr();
255 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
256 RegUse, UseOp, /*FindMin=*/false));
258 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
259 RegUse, UseOp, /*FindMin=*/true));
261 ST.adjustSchedDependency(SU, UseSU, dep);
267 /// addPhysRegDeps - Add register dependencies (data, anti, and output) from
268 /// this SUnit to following instructions in the same scheduling region that
269 /// depend the physical register referenced at OperIdx.
270 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
271 const MachineInstr *MI = SU->getInstr();
272 const MachineOperand &MO = MI->getOperand(OperIdx);
274 // Optionally add output and anti dependencies. For anti
275 // dependencies we use a latency of 0 because for a multi-issue
276 // target we want to allow the defining instruction to issue
277 // in the same cycle as the using instruction.
278 // TODO: Using a latency of 1 here for output dependencies assumes
279 // there's no cost for reusing registers.
280 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
281 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
282 Alias.isValid(); ++Alias) {
283 if (!Defs.contains(*Alias))
285 std::vector<PhysRegSUOper> &DefList = Defs[*Alias];
286 for (unsigned i = 0, e = DefList.size(); i != e; ++i) {
287 SUnit *DefSU = DefList[i].SU;
288 if (DefSU == &ExitSU)
291 (Kind != SDep::Output || !MO.isDead() ||
292 !DefSU->getInstr()->registerDefIsDead(*Alias))) {
293 if (Kind == SDep::Anti)
294 DefSU->addPred(SDep(SU, Kind, 0, /*Reg=*/*Alias));
297 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr());
298 DefSU->addPred(SDep(SU, Kind, AOLat, /*Reg=*/*Alias));
305 // Either insert a new Reg2SUnits entry with an empty SUnits list, or
306 // retrieve the existing SUnits list for this register's uses.
307 // Push this SUnit on the use list.
308 Uses[MO.getReg()].push_back(PhysRegSUOper(SU, OperIdx));
311 addPhysRegDataDeps(SU, OperIdx);
313 // Either insert a new Reg2SUnits entry with an empty SUnits list, or
314 // retrieve the existing SUnits list for this register's defs.
315 std::vector<PhysRegSUOper> &DefList = Defs[MO.getReg()];
317 // clear this register's use list
318 if (Uses.contains(MO.getReg()))
319 Uses[MO.getReg()].clear();
324 // Calls will not be reordered because of chain dependencies (see
325 // below). Since call operands are dead, calls may continue to be added
326 // to the DefList making dependence checking quadratic in the size of
327 // the block. Instead, we leave only one call at the back of the
330 while (!DefList.empty() && DefList.back().SU->isCall)
333 // Defs are pushed in the order they are visited and never reordered.
334 DefList.push_back(PhysRegSUOper(SU, OperIdx));
338 /// addVRegDefDeps - Add register output and data dependencies from this SUnit
339 /// to instructions that occur later in the same scheduling region if they read
340 /// from or write to the virtual register defined at OperIdx.
342 /// TODO: Hoist loop induction variable increments. This has to be
343 /// reevaluated. Generally, IV scheduling should be done before coalescing.
344 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
345 const MachineInstr *MI = SU->getInstr();
346 unsigned Reg = MI->getOperand(OperIdx).getReg();
348 // Singly defined vregs do not have output/anti dependencies.
349 // The current operand is a def, so we have at least one.
350 // Check here if there are any others...
351 if (MRI.hasOneDef(Reg))
354 // Add output dependence to the next nearest def of this vreg.
356 // Unless this definition is dead, the output dependence should be
357 // transitively redundant with antidependencies from this definition's
358 // uses. We're conservative for now until we have a way to guarantee the uses
359 // are not eliminated sometime during scheduling. The output dependence edge
360 // is also useful if output latency exceeds def-use latency.
361 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
362 if (DefI == VRegDefs.end())
363 VRegDefs.insert(VReg2SUnit(Reg, SU));
365 SUnit *DefSU = DefI->SU;
366 if (DefSU != SU && DefSU != &ExitSU) {
367 unsigned OutLatency =
368 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr());
369 DefSU->addPred(SDep(SU, SDep::Output, OutLatency, Reg));
375 /// addVRegUseDeps - Add a register data dependency if the instruction that
376 /// defines the virtual register used at OperIdx is mapped to an SUnit. Add a
377 /// register antidependency from this SUnit to instructions that occur later in
378 /// the same scheduling region if they write the virtual register.
380 /// TODO: Handle ExitSU "uses" properly.
381 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
382 MachineInstr *MI = SU->getInstr();
383 unsigned Reg = MI->getOperand(OperIdx).getReg();
385 // Lookup this operand's reaching definition.
386 assert(LIS && "vreg dependencies requires LiveIntervals");
387 LiveRangeQuery LRQ(LIS->getInterval(Reg), LIS->getInstructionIndex(MI));
388 VNInfo *VNI = LRQ.valueIn();
390 // VNI will be valid because MachineOperand::readsReg() is checked by caller.
391 assert(VNI && "No value to read by operand");
392 MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def);
393 // Phis and other noninstructions (after coalescing) have a NULL Def.
395 SUnit *DefSU = getSUnit(Def);
397 // The reaching Def lives within this scheduling region.
398 // Create a data dependence.
399 SDep dep(DefSU, SDep::Data, 1, Reg);
400 // Adjust the dependence latency using operand def/use information, then
401 // allow the target to perform its own adjustments.
402 int DefOp = Def->findRegisterDefOperandIdx(Reg);
404 SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx, false));
406 SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx, true));
408 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
409 ST.adjustSchedDependency(DefSU, SU, const_cast<SDep &>(dep));
414 // Add antidependence to the following def of the vreg it uses.
415 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
416 if (DefI != VRegDefs.end() && DefI->SU != SU)
417 DefI->SU->addPred(SDep(SU, SDep::Anti, 0, Reg));
420 /// Return true if MI is an instruction we are unable to reason about
421 /// (like a call or something with unmodeled side effects).
422 static inline bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) {
423 if (MI->isCall() || MI->hasUnmodeledSideEffects() ||
424 (MI->hasOrderedMemoryRef() &&
425 (!MI->mayLoad() || !MI->isInvariantLoad(AA))))
430 // This MI might have either incomplete info, or known to be unsafe
431 // to deal with (i.e. volatile object).
432 static inline bool isUnsafeMemoryObject(MachineInstr *MI,
433 const MachineFrameInfo *MFI) {
434 if (!MI || MI->memoperands_empty())
436 // We purposefully do no check for hasOneMemOperand() here
437 // in hope to trigger an assert downstream in order to
438 // finish implementation.
439 if ((*MI->memoperands_begin())->isVolatile() ||
440 MI->hasUnmodeledSideEffects())
443 const Value *V = (*MI->memoperands_begin())->getValue();
447 V = getUnderlyingObject(V);
448 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
449 // Similarly to getUnderlyingObjectForInstr:
450 // For now, ignore PseudoSourceValues which may alias LLVM IR values
451 // because the code that uses this function has no way to cope with
453 if (PSV->isAliased(MFI))
456 // Does this pointer refer to a distinct and identifiable object?
457 if (!isIdentifiedObject(V))
463 /// This returns true if the two MIs need a chain edge betwee them.
464 /// If these are not even memory operations, we still may need
465 /// chain deps between them. The question really is - could
466 /// these two MIs be reordered during scheduling from memory dependency
468 static bool MIsNeedChainEdge(AliasAnalysis *AA, const MachineFrameInfo *MFI,
471 // Cover a trivial case - no edge is need to itself.
475 if (isUnsafeMemoryObject(MIa, MFI) || isUnsafeMemoryObject(MIb, MFI))
478 // If we are dealing with two "normal" loads, we do not need an edge
479 // between them - they could be reordered.
480 if (!MIa->mayStore() && !MIb->mayStore())
483 // To this point analysis is generic. From here on we do need AA.
487 MachineMemOperand *MMOa = *MIa->memoperands_begin();
488 MachineMemOperand *MMOb = *MIb->memoperands_begin();
490 // FIXME: Need to handle multiple memory operands to support all targets.
491 if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand())
492 llvm_unreachable("Multiple memory operands.");
494 // The following interface to AA is fashioned after DAGCombiner::isAlias
495 // and operates with MachineMemOperand offset with some important
497 // - LLVM fundamentally assumes flat address spaces.
498 // - MachineOperand offset can *only* result from legalization and
499 // cannot affect queries other than the trivial case of overlap
501 // - These offsets never wrap and never step outside
502 // of allocated objects.
503 // - There should never be any negative offsets here.
505 // FIXME: Modify API to hide this math from "user"
506 // FIXME: Even before we go to AA we can reason locally about some
507 // memory objects. It can save compile time, and possibly catch some
508 // corner cases not currently covered.
510 assert ((MMOa->getOffset() >= 0) && "Negative MachineMemOperand offset");
511 assert ((MMOb->getOffset() >= 0) && "Negative MachineMemOperand offset");
513 int64_t MinOffset = std::min(MMOa->getOffset(), MMOb->getOffset());
514 int64_t Overlapa = MMOa->getSize() + MMOa->getOffset() - MinOffset;
515 int64_t Overlapb = MMOb->getSize() + MMOb->getOffset() - MinOffset;
517 AliasAnalysis::AliasResult AAResult = AA->alias(
518 AliasAnalysis::Location(MMOa->getValue(), Overlapa,
519 MMOa->getTBAAInfo()),
520 AliasAnalysis::Location(MMOb->getValue(), Overlapb,
521 MMOb->getTBAAInfo()));
523 return (AAResult != AliasAnalysis::NoAlias);
526 /// This recursive function iterates over chain deps of SUb looking for
527 /// "latest" node that needs a chain edge to SUa.
529 iterateChainSucc(AliasAnalysis *AA, const MachineFrameInfo *MFI,
530 SUnit *SUa, SUnit *SUb, SUnit *ExitSU, unsigned *Depth,
531 SmallPtrSet<const SUnit*, 16> &Visited) {
532 if (!SUa || !SUb || SUb == ExitSU)
535 // Remember visited nodes.
536 if (!Visited.insert(SUb))
538 // If there is _some_ dependency already in place, do not
539 // descend any further.
540 // TODO: Need to make sure that if that dependency got eliminated or ignored
541 // for any reason in the future, we would not violate DAG topology.
542 // Currently it does not happen, but makes an implicit assumption about
543 // future implementation.
545 // Independently, if we encounter node that is some sort of global
546 // object (like a call) we already have full set of dependencies to it
547 // and we can stop descending.
548 if (SUa->isSucc(SUb) ||
549 isGlobalMemoryObject(AA, SUb->getInstr()))
552 // If we do need an edge, or we have exceeded depth budget,
553 // add that edge to the predecessors chain of SUb,
554 // and stop descending.
556 MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) {
557 SUb->addPred(SDep(SUa, SDep::Order, /*Latency=*/0, /*Reg=*/0,
558 /*isNormalMemory=*/true));
561 // Track current depth.
563 // Iterate over chain dependencies only.
564 for (SUnit::const_succ_iterator I = SUb->Succs.begin(), E = SUb->Succs.end();
567 iterateChainSucc (AA, MFI, SUa, I->getSUnit(), ExitSU, Depth, Visited);
571 /// This function assumes that "downward" from SU there exist
572 /// tail/leaf of already constructed DAG. It iterates downward and
573 /// checks whether SU can be aliasing any node dominated
575 static void adjustChainDeps(AliasAnalysis *AA, const MachineFrameInfo *MFI,
576 SUnit *SU, SUnit *ExitSU, std::set<SUnit *> &CheckList,
577 unsigned LatencyToLoad) {
581 SmallPtrSet<const SUnit*, 16> Visited;
584 for (std::set<SUnit *>::iterator I = CheckList.begin(), IE = CheckList.end();
588 if (MIsNeedChainEdge(AA, MFI, SU->getInstr(), (*I)->getInstr())) {
589 unsigned Latency = ((*I)->getInstr()->mayLoad()) ? LatencyToLoad : 0;
590 (*I)->addPred(SDep(SU, SDep::Order, Latency, /*Reg=*/0,
591 /*isNormalMemory=*/true));
593 // Now go through all the chain successors and iterate from them.
594 // Keep track of visited nodes.
595 for (SUnit::const_succ_iterator J = (*I)->Succs.begin(),
596 JE = (*I)->Succs.end(); J != JE; ++J)
598 iterateChainSucc (AA, MFI, SU, J->getSUnit(),
599 ExitSU, &Depth, Visited);
603 /// Check whether two objects need a chain edge, if so, add it
604 /// otherwise remember the rejected SU.
606 void addChainDependency (AliasAnalysis *AA, const MachineFrameInfo *MFI,
607 SUnit *SUa, SUnit *SUb,
608 std::set<SUnit *> &RejectList,
609 unsigned TrueMemOrderLatency = 0,
610 bool isNormalMemory = false) {
611 // If this is a false dependency,
612 // do not add the edge, but rememeber the rejected node.
613 if (!EnableAASchedMI ||
614 MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr()))
615 SUb->addPred(SDep(SUa, SDep::Order, TrueMemOrderLatency, /*Reg=*/0,
618 // Duplicate entries should be ignored.
619 RejectList.insert(SUb);
620 DEBUG(dbgs() << "\tReject chain dep between SU("
621 << SUa->NodeNum << ") and SU("
622 << SUb->NodeNum << ")\n");
626 /// Create an SUnit for each real instruction, numbered in top-down toplological
627 /// order. The instruction order A < B, implies that no edge exists from B to A.
629 /// Map each real instruction to its SUnit.
631 /// After initSUnits, the SUnits vector cannot be resized and the scheduler may
632 /// hang onto SUnit pointers. We may relax this in the future by using SUnit IDs
633 /// instead of pointers.
635 /// MachineScheduler relies on initSUnits numbering the nodes by their order in
636 /// the original instruction list.
637 void ScheduleDAGInstrs::initSUnits() {
638 // We'll be allocating one SUnit for each real instruction in the region,
639 // which is contained within a basic block.
640 SUnits.reserve(BB->size());
642 for (MachineBasicBlock::iterator I = RegionBegin; I != RegionEnd; ++I) {
643 MachineInstr *MI = I;
644 if (MI->isDebugValue())
647 SUnit *SU = newSUnit(MI);
650 SU->isCall = MI->isCall();
651 SU->isCommutable = MI->isCommutable();
653 // Assign the Latency field of SU using target-provided information.
654 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
658 /// If RegPressure is non null, compute register pressure as a side effect. The
659 /// DAG builder is an efficient place to do it because it already visits
661 void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
662 RegPressureTracker *RPTracker) {
663 // Create an SUnit for each real instruction.
666 // We build scheduling units by walking a block's instruction list from bottom
669 // Remember where a generic side-effecting instruction is as we procede.
670 SUnit *BarrierChain = 0, *AliasChain = 0;
672 // Memory references to specific known memory locations are tracked
673 // so that they can be given more precise dependencies. We track
674 // separately the known memory locations that may alias and those
675 // that are known not to alias
676 std::map<const Value *, SUnit *> AliasMemDefs, NonAliasMemDefs;
677 std::map<const Value *, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses;
678 std::set<SUnit*> RejectMemNodes;
680 // Remove any stale debug info; sometimes BuildSchedGraph is called again
681 // without emitting the info from the previous call.
683 FirstDbgValue = NULL;
685 assert(Defs.empty() && Uses.empty() &&
686 "Only BuildGraph should update Defs/Uses");
687 Defs.setRegLimit(TRI->getNumRegs());
688 Uses.setRegLimit(TRI->getNumRegs());
690 assert(VRegDefs.empty() && "Only BuildSchedGraph may access VRegDefs");
691 // FIXME: Allow SparseSet to reserve space for the creation of virtual
692 // registers during scheduling. Don't artificially inflate the Universe
693 // because we want to assert that vregs are not created during DAG building.
694 VRegDefs.setUniverse(MRI.getNumVirtRegs());
696 // Model data dependencies between instructions being scheduled and the
698 addSchedBarrierDeps();
700 // Walk the list of instructions, from bottom moving up.
701 MachineInstr *PrevMI = NULL;
702 for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
704 MachineInstr *MI = prior(MII);
706 DbgValues.push_back(std::make_pair(PrevMI, MI));
710 if (MI->isDebugValue()) {
716 assert(RPTracker->getPos() == prior(MII) && "RPTracker can't find MI");
719 assert((!MI->isTerminator() || CanHandleTerminators) && !MI->isLabel() &&
720 "Cannot schedule terminators or labels!");
722 SUnit *SU = MISUnitMap[MI];
723 assert(SU && "No SUnit mapped to this MI");
725 // Add register-based dependencies (data, anti, and output).
726 for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
727 const MachineOperand &MO = MI->getOperand(j);
728 if (!MO.isReg()) continue;
729 unsigned Reg = MO.getReg();
730 if (Reg == 0) continue;
732 if (TRI->isPhysicalRegister(Reg))
733 addPhysRegDeps(SU, j);
735 assert(!IsPostRA && "Virtual register encountered!");
737 addVRegDefDeps(SU, j);
738 else if (MO.readsReg()) // ignore undef operands
739 addVRegUseDeps(SU, j);
743 // Add chain dependencies.
744 // Chain dependencies used to enforce memory order should have
745 // latency of 0 (except for true dependency of Store followed by
746 // aliased Load... we estimate that with a single cycle of latency
747 // assuming the hardware will bypass)
748 // Note that isStoreToStackSlot and isLoadFromStackSLot are not usable
749 // after stack slots are lowered to actual addresses.
750 // TODO: Use an AliasAnalysis and do real alias-analysis queries, and
751 // produce more precise dependence information.
752 unsigned TrueMemOrderLatency = MI->mayStore() ? 1 : 0;
753 if (isGlobalMemoryObject(AA, MI)) {
754 // Be conservative with these and add dependencies on all memory
755 // references, even those that are known to not alias.
756 for (std::map<const Value *, SUnit *>::iterator I =
757 NonAliasMemDefs.begin(), E = NonAliasMemDefs.end(); I != E; ++I) {
758 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
760 for (std::map<const Value *, std::vector<SUnit *> >::iterator I =
761 NonAliasMemUses.begin(), E = NonAliasMemUses.end(); I != E; ++I) {
762 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
763 I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
765 // Add SU to the barrier chain.
767 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
769 // This is a barrier event that acts as a pivotal node in the DAG,
770 // so it is safe to clear list of exposed nodes.
771 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
772 TrueMemOrderLatency);
773 RejectMemNodes.clear();
774 NonAliasMemDefs.clear();
775 NonAliasMemUses.clear();
779 // Chain all possibly aliasing memory references though SU.
781 unsigned ChainLatency = 0;
782 if (AliasChain->getInstr()->mayLoad())
783 ChainLatency = TrueMemOrderLatency;
784 addChainDependency(AA, MFI, SU, AliasChain, RejectMemNodes,
788 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
789 addChainDependency(AA, MFI, SU, PendingLoads[k], RejectMemNodes,
790 TrueMemOrderLatency);
791 for (std::map<const Value *, SUnit *>::iterator I = AliasMemDefs.begin(),
792 E = AliasMemDefs.end(); I != E; ++I)
793 addChainDependency(AA, MFI, SU, I->second, RejectMemNodes);
794 for (std::map<const Value *, std::vector<SUnit *> >::iterator I =
795 AliasMemUses.begin(), E = AliasMemUses.end(); I != E; ++I) {
796 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
797 addChainDependency(AA, MFI, SU, I->second[i], RejectMemNodes,
798 TrueMemOrderLatency);
800 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
801 TrueMemOrderLatency);
802 PendingLoads.clear();
803 AliasMemDefs.clear();
804 AliasMemUses.clear();
805 } else if (MI->mayStore()) {
806 bool MayAlias = true;
807 if (const Value *V = getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
808 // A store to a specific PseudoSourceValue. Add precise dependencies.
809 // Record the def in MemDefs, first adding a dep if there is
811 std::map<const Value *, SUnit *>::iterator I =
812 ((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
813 std::map<const Value *, SUnit *>::iterator IE =
814 ((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
816 addChainDependency(AA, MFI, SU, I->second, RejectMemNodes,
821 AliasMemDefs[V] = SU;
823 NonAliasMemDefs[V] = SU;
825 // Handle the uses in MemUses, if there are any.
826 std::map<const Value *, std::vector<SUnit *> >::iterator J =
827 ((MayAlias) ? AliasMemUses.find(V) : NonAliasMemUses.find(V));
828 std::map<const Value *, std::vector<SUnit *> >::iterator JE =
829 ((MayAlias) ? AliasMemUses.end() : NonAliasMemUses.end());
831 for (unsigned i = 0, e = J->second.size(); i != e; ++i)
832 addChainDependency(AA, MFI, SU, J->second[i], RejectMemNodes,
833 TrueMemOrderLatency, true);
837 // Add dependencies from all the PendingLoads, i.e. loads
838 // with no underlying object.
839 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
840 addChainDependency(AA, MFI, SU, PendingLoads[k], RejectMemNodes,
841 TrueMemOrderLatency);
842 // Add dependence on alias chain, if needed.
844 addChainDependency(AA, MFI, SU, AliasChain, RejectMemNodes);
845 // But we also should check dependent instructions for the
847 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
848 TrueMemOrderLatency);
850 // Add dependence on barrier chain, if needed.
851 // There is no point to check aliasing on barrier event. Even if
852 // SU and barrier _could_ be reordered, they should not. In addition,
853 // we have lost all RejectMemNodes below barrier.
855 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
857 // Treat all other stores conservatively.
858 goto new_alias_chain;
861 if (!ExitSU.isPred(SU))
862 // Push store's up a bit to avoid them getting in between cmp
864 ExitSU.addPred(SDep(SU, SDep::Order, 0,
865 /*Reg=*/0, /*isNormalMemory=*/false,
866 /*isMustAlias=*/false,
867 /*isArtificial=*/true));
868 } else if (MI->mayLoad()) {
869 bool MayAlias = true;
870 if (MI->isInvariantLoad(AA)) {
871 // Invariant load, no chain dependencies needed!
874 getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
875 // A load from a specific PseudoSourceValue. Add precise dependencies.
876 std::map<const Value *, SUnit *>::iterator I =
877 ((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
878 std::map<const Value *, SUnit *>::iterator IE =
879 ((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
881 addChainDependency(AA, MFI, SU, I->second, RejectMemNodes, 0, true);
883 AliasMemUses[V].push_back(SU);
885 NonAliasMemUses[V].push_back(SU);
887 // A load with no underlying object. Depend on all
888 // potentially aliasing stores.
889 for (std::map<const Value *, SUnit *>::iterator I =
890 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I)
891 addChainDependency(AA, MFI, SU, I->second, RejectMemNodes);
893 PendingLoads.push_back(SU);
897 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes, /*Latency=*/0);
898 // Add dependencies on alias and barrier chains, if needed.
899 if (MayAlias && AliasChain)
900 addChainDependency(AA, MFI, SU, AliasChain, RejectMemNodes);
902 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
907 FirstDbgValue = PrevMI;
912 PendingLoads.clear();
915 void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
916 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
917 SU->getInstr()->dump();
921 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
923 raw_string_ostream oss(s);
926 else if (SU == &ExitSU)
929 SU->getInstr()->print(oss);
933 /// Return the basic block label. It is not necessarilly unique because a block
934 /// contains multiple scheduling regions. But it is fine for visualization.
935 std::string ScheduleDAGInstrs::getDAGName() const {
936 return "dag." + BB->getFullName();
940 /// \brief Manage the stack used by a reverse depth-first search over the DAG.
941 class SchedDAGReverseDFS {
942 std::vector<std::pair<const SUnit*, SUnit::const_pred_iterator> > DFSStack;
944 bool isComplete() const { return DFSStack.empty(); }
946 void follow(const SUnit *SU) {
947 DFSStack.push_back(std::make_pair(SU, SU->Preds.begin()));
949 void advance() { ++DFSStack.back().second; }
951 void backtrack() { DFSStack.pop_back(); }
953 const SUnit *getCurr() const { return DFSStack.back().first; }
955 SUnit::const_pred_iterator getPred() const { return DFSStack.back().second; }
957 SUnit::const_pred_iterator getPredEnd() const {
958 return getCurr()->Preds.end();
963 void ScheduleDAGILP::resize(unsigned NumSUnits) {
964 ILPValues.resize(NumSUnits);
967 ILPValue ScheduleDAGILP::getILP(const SUnit *SU) {
968 return ILPValues[SU->NodeNum];
971 // A leaf node has an ILP of 1/1.
972 static ILPValue initILP(const SUnit *SU) {
973 unsigned Cnt = SU->getInstr()->isTransient() ? 0 : 1;
974 return ILPValue(Cnt, 1 + SU->getDepth());
977 /// Compute an ILP metric for all nodes in the subDAG reachable via depth-first
978 /// search from this root.
979 void ScheduleDAGILP::computeILP(const SUnit *Root) {
981 llvm_unreachable("Top-down ILP metric is unimplemnted");
983 SchedDAGReverseDFS DFS;
984 // Mark a node visited by validating it.
985 ILPValues[Root->NodeNum] = initILP(Root);
988 // Traverse the leftmost path as far as possible.
989 while (DFS.getPred() != DFS.getPredEnd()) {
990 const SUnit *PredSU = DFS.getPred()->getSUnit();
992 // If the pred is already valid, skip it.
993 if (ILPValues[PredSU->NodeNum].isValid())
995 ILPValues[PredSU->NodeNum] = initILP(PredSU);
998 // Visit the top of the stack in postorder and backtrack.
999 unsigned PredCount = ILPValues[DFS.getCurr()->NodeNum].InstrCount;
1001 if (DFS.isComplete())
1003 // Add the recently finished predecessor's bottom-up descendent count.
1004 ILPValues[DFS.getCurr()->NodeNum].InstrCount += PredCount;
1008 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1009 void ILPValue::print(raw_ostream &OS) const {
1012 OS << InstrCount << " / " << Cycles << " = "
1013 << format("%g", ((double)InstrCount / Cycles));
1016 void ILPValue::dump() const {
1017 dbgs() << *this << '\n';
1022 raw_ostream &operator<<(raw_ostream &OS, const ILPValue &Val) {
1028 #endif // !NDEBUG || LLVM_ENABLE_DUMP