1 //===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the ScheduleDAGInstrs class, which implements re-scheduling
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "sched-instrs"
16 #include "ScheduleDAGInstrs.h"
17 #include "llvm/Operator.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Analysis/ValueTracking.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineMemOperand.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/MC/MCInstrItineraries.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Target/TargetSubtargetInfo.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/ADT/SmallSet.h"
35 ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
36 const MachineLoopInfo &mli,
37 const MachineDominatorTree &mdt,
40 : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()),
41 InstrItins(mf.getTarget().getInstrItineraryData()), IsPostRA(IsPostRAFlag),
42 LIS(lis), UnitLatencies(false), LoopRegs(MLI, MDT), FirstDbgValue(0) {
43 assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
45 assert(!(IsPostRA && MRI.getNumVirtRegs()) &&
46 "Virtual registers must be removed prior to PostRA scheduling");
49 /// getUnderlyingObjectFromInt - This is the function that does the work of
50 /// looking through basic ptrtoint+arithmetic+inttoptr sequences.
51 static const Value *getUnderlyingObjectFromInt(const Value *V) {
53 if (const Operator *U = dyn_cast<Operator>(V)) {
54 // If we find a ptrtoint, we can transfer control back to the
55 // regular getUnderlyingObjectFromInt.
56 if (U->getOpcode() == Instruction::PtrToInt)
57 return U->getOperand(0);
58 // If we find an add of a constant or a multiplied value, it's
59 // likely that the other operand will lead us to the base
60 // object. We don't have to worry about the case where the
61 // object address is somehow being computed by the multiply,
62 // because our callers only care when the result is an
63 // identifibale object.
64 if (U->getOpcode() != Instruction::Add ||
65 (!isa<ConstantInt>(U->getOperand(1)) &&
66 Operator::getOpcode(U->getOperand(1)) != Instruction::Mul))
72 assert(V->getType()->isIntegerTy() && "Unexpected operand type!");
76 /// getUnderlyingObject - This is a wrapper around GetUnderlyingObject
77 /// and adds support for basic ptrtoint+arithmetic+inttoptr sequences.
78 static const Value *getUnderlyingObject(const Value *V) {
79 // First just call Value::getUnderlyingObject to let it do what it does.
81 V = GetUnderlyingObject(V);
82 // If it found an inttoptr, use special code to continue climing.
83 if (Operator::getOpcode(V) != Instruction::IntToPtr)
85 const Value *O = getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0));
86 // If that succeeded in finding a pointer, continue the search.
87 if (!O->getType()->isPointerTy())
94 /// getUnderlyingObjectForInstr - If this machine instr has memory reference
95 /// information and it can be tracked to a normal reference to a known
96 /// object, return the Value for that object. Otherwise return null.
97 static const Value *getUnderlyingObjectForInstr(const MachineInstr *MI,
98 const MachineFrameInfo *MFI,
101 if (!MI->hasOneMemOperand() ||
102 !(*MI->memoperands_begin())->getValue() ||
103 (*MI->memoperands_begin())->isVolatile())
106 const Value *V = (*MI->memoperands_begin())->getValue();
110 V = getUnderlyingObject(V);
111 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
112 // For now, ignore PseudoSourceValues which may alias LLVM IR values
113 // because the code that uses this function has no way to cope with
115 if (PSV->isAliased(MFI))
118 MayAlias = PSV->mayAlias(MFI);
122 if (isIdentifiedObject(V))
128 void ScheduleDAGInstrs::StartBlock(MachineBasicBlock *BB) {
129 LoopRegs.Deps.clear();
130 if (MachineLoop *ML = MLI.getLoopFor(BB))
131 if (BB == ML->getLoopLatch())
132 LoopRegs.VisitLoop(ML);
135 void ScheduleDAGInstrs::FinishBlock() {
139 /// Initialize the map with the number of registers.
140 void ScheduleDAGInstrs::Reg2SUnitsMap::setRegLimit(unsigned Limit) {
141 PhysRegSet.setUniverse(Limit);
142 SUnits.resize(Limit);
145 /// Clear the map without deallocating storage.
146 void ScheduleDAGInstrs::Reg2SUnitsMap::clear() {
147 for (const_iterator I = reg_begin(), E = reg_end(); I != E; ++I) {
153 /// Initialize the DAG and common scheduler state for the current scheduling
154 /// region. This does not actually create the DAG, only clears it. The
155 /// scheduling driver may call BuildSchedGraph multiple times per scheduling
157 void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb,
158 MachineBasicBlock::iterator begin,
159 MachineBasicBlock::iterator end,
164 InsertPosIndex = endcount;
166 // Check to see if the scheduler cares about latencies.
167 UnitLatencies = ForceUnitLatencies();
169 ScheduleDAG::clearDAG();
172 /// Close the current scheduling region. Don't clear any state in case the
173 /// driver wants to refer to the previous scheduling region.
174 void ScheduleDAGInstrs::exitRegion() {
178 /// AddSchedBarrierDeps - Add dependencies from instructions in the current
179 /// list of instructions being scheduled to scheduling barrier by adding
180 /// the exit SU to the register defs and use list. This is because we want to
181 /// make sure instructions which define registers that are either used by
182 /// the terminator or are live-out are properly scheduled. This is
183 /// especially important when the definition latency of the return value(s)
184 /// are too high to be hidden by the branch or when the liveout registers
185 /// used by instructions in the fallthrough block.
186 void ScheduleDAGInstrs::AddSchedBarrierDeps() {
187 MachineInstr *ExitMI = InsertPos != BB->end() ? &*InsertPos : 0;
188 ExitSU.setInstr(ExitMI);
189 bool AllDepKnown = ExitMI &&
190 (ExitMI->isCall() || ExitMI->isBarrier());
191 if (ExitMI && AllDepKnown) {
192 // If it's a call or a barrier, add dependencies on the defs and uses of
194 for (unsigned i = 0, e = ExitMI->getNumOperands(); i != e; ++i) {
195 const MachineOperand &MO = ExitMI->getOperand(i);
196 if (!MO.isReg() || MO.isDef()) continue;
197 unsigned Reg = MO.getReg();
198 if (Reg == 0) continue;
200 if (TRI->isPhysicalRegister(Reg))
201 Uses[Reg].push_back(&ExitSU);
203 assert(!IsPostRA && "Virtual register encountered after regalloc.");
206 // For others, e.g. fallthrough, conditional branch, assume the exit
207 // uses all the registers that are livein to the successor blocks.
208 SmallSet<unsigned, 8> Seen;
209 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
210 SE = BB->succ_end(); SI != SE; ++SI)
211 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
212 E = (*SI)->livein_end(); I != E; ++I) {
214 if (Seen.insert(Reg))
215 Uses[Reg].push_back(&ExitSU);
220 /// MO is an operand of SU's instruction that defines a physical register. Add
221 /// data dependencies from SU to any uses of the physical register.
222 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU,
223 const MachineOperand &MO) {
224 assert(MO.isDef() && "expect physreg def");
226 // Ask the target if address-backscheduling is desirable, and if so how much.
227 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
228 unsigned SpecialAddressLatency = ST.getSpecialAddressLatency();
229 unsigned DataLatency = SU->Latency;
231 for (const uint16_t *Alias = TRI->getOverlaps(MO.getReg()); *Alias; ++Alias) {
232 if (!Uses.contains(*Alias))
234 std::vector<SUnit*> &UseList = Uses[*Alias];
235 for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
236 SUnit *UseSU = UseList[i];
239 unsigned LDataLatency = DataLatency;
240 // Optionally add in a special extra latency for nodes that
242 // TODO: Perhaps we should get rid of
243 // SpecialAddressLatency and just move this into
244 // adjustSchedDependency for the targets that care about it.
245 if (SpecialAddressLatency != 0 && !UnitLatencies &&
247 MachineInstr *UseMI = UseSU->getInstr();
248 const MCInstrDesc &UseMCID = UseMI->getDesc();
249 int RegUseIndex = UseMI->findRegisterUseOperandIdx(*Alias);
250 assert(RegUseIndex >= 0 && "UseMI doesn't use register!");
251 if (RegUseIndex >= 0 &&
252 (UseMI->mayLoad() || UseMI->mayStore()) &&
253 (unsigned)RegUseIndex < UseMCID.getNumOperands() &&
254 UseMCID.OpInfo[RegUseIndex].isLookupPtrRegClass())
255 LDataLatency += SpecialAddressLatency;
257 // Adjust the dependence latency using operand def/use
258 // information (if any), and then allow the target to
259 // perform its own adjustments.
260 const SDep& dep = SDep(SU, SDep::Data, LDataLatency, *Alias);
261 if (!UnitLatencies) {
262 ComputeOperandLatency(SU, UseSU, const_cast<SDep &>(dep));
263 ST.adjustSchedDependency(SU, UseSU, const_cast<SDep &>(dep));
270 /// addPhysRegDeps - Add register dependencies (data, anti, and output) from
271 /// this SUnit to following instructions in the same scheduling region that
272 /// depend the physical register referenced at OperIdx.
273 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
274 const MachineInstr *MI = SU->getInstr();
275 const MachineOperand &MO = MI->getOperand(OperIdx);
277 // Optionally add output and anti dependencies. For anti
278 // dependencies we use a latency of 0 because for a multi-issue
279 // target we want to allow the defining instruction to issue
280 // in the same cycle as the using instruction.
281 // TODO: Using a latency of 1 here for output dependencies assumes
282 // there's no cost for reusing registers.
283 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
284 for (const uint16_t *Alias = TRI->getOverlaps(MO.getReg()); *Alias; ++Alias) {
285 if (!Defs.contains(*Alias))
287 std::vector<SUnit *> &DefList = Defs[*Alias];
288 for (unsigned i = 0, e = DefList.size(); i != e; ++i) {
289 SUnit *DefSU = DefList[i];
290 if (DefSU == &ExitSU)
293 (Kind != SDep::Output || !MO.isDead() ||
294 !DefSU->getInstr()->registerDefIsDead(*Alias))) {
295 if (Kind == SDep::Anti)
296 DefSU->addPred(SDep(SU, Kind, 0, /*Reg=*/*Alias));
298 unsigned AOLat = TII->getOutputLatency(InstrItins, MI, OperIdx,
300 DefSU->addPred(SDep(SU, Kind, AOLat, /*Reg=*/*Alias));
307 // Either insert a new Reg2SUnits entry with an empty SUnits list, or
308 // retrieve the existing SUnits list for this register's uses.
309 // Push this SUnit on the use list.
310 Uses[MO.getReg()].push_back(SU);
313 addPhysRegDataDeps(SU, MO);
315 // Either insert a new Reg2SUnits entry with an empty SUnits list, or
316 // retrieve the existing SUnits list for this register's defs.
317 std::vector<SUnit *> &DefList = Defs[MO.getReg()];
319 // If a def is going to wrap back around to the top of the loop,
321 if (!UnitLatencies && DefList.empty()) {
322 LoopDependencies::LoopDeps::iterator I = LoopRegs.Deps.find(MO.getReg());
323 if (I != LoopRegs.Deps.end()) {
324 const MachineOperand *UseMO = I->second.first;
325 unsigned Count = I->second.second;
326 const MachineInstr *UseMI = UseMO->getParent();
327 unsigned UseMOIdx = UseMO - &UseMI->getOperand(0);
328 const MCInstrDesc &UseMCID = UseMI->getDesc();
329 const TargetSubtargetInfo &ST =
330 TM.getSubtarget<TargetSubtargetInfo>();
331 unsigned SpecialAddressLatency = ST.getSpecialAddressLatency();
332 // TODO: If we knew the total depth of the region here, we could
333 // handle the case where the whole loop is inside the region but
334 // is large enough that the isScheduleHigh trick isn't needed.
335 if (UseMOIdx < UseMCID.getNumOperands()) {
336 // Currently, we only support scheduling regions consisting of
337 // single basic blocks. Check to see if the instruction is in
338 // the same region by checking to see if it has the same parent.
339 if (UseMI->getParent() != MI->getParent()) {
340 unsigned Latency = SU->Latency;
341 if (UseMCID.OpInfo[UseMOIdx].isLookupPtrRegClass())
342 Latency += SpecialAddressLatency;
343 // This is a wild guess as to the portion of the latency which
344 // will be overlapped by work done outside the current
345 // scheduling region.
346 Latency -= std::min(Latency, Count);
347 // Add the artificial edge.
348 ExitSU.addPred(SDep(SU, SDep::Order, Latency,
349 /*Reg=*/0, /*isNormalMemory=*/false,
350 /*isMustAlias=*/false,
351 /*isArtificial=*/true));
352 } else if (SpecialAddressLatency > 0 &&
353 UseMCID.OpInfo[UseMOIdx].isLookupPtrRegClass()) {
354 // The entire loop body is within the current scheduling region
355 // and the latency of this operation is assumed to be greater
356 // than the latency of the loop.
357 // TODO: Recursively mark data-edge predecessors as
358 // isScheduleHigh too.
359 SU->isScheduleHigh = true;
362 LoopRegs.Deps.erase(I);
366 // clear this register's use list
367 if (Uses.contains(MO.getReg()))
368 Uses[MO.getReg()].clear();
373 // Calls will not be reordered because of chain dependencies (see
374 // below). Since call operands are dead, calls may continue to be added
375 // to the DefList making dependence checking quadratic in the size of
376 // the block. Instead, we leave only one call at the back of the
379 while (!DefList.empty() && DefList.back()->isCall)
382 // Defs are pushed in the order they are visited and never reordered.
383 DefList.push_back(SU);
387 /// addVRegDefDeps - Add register output and data dependencies from this SUnit
388 /// to instructions that occur later in the same scheduling region if they read
389 /// from or write to the virtual register defined at OperIdx.
391 /// TODO: Hoist loop induction variable increments. This has to be
392 /// reevaluated. Generally, IV scheduling should be done before coalescing.
393 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
394 const MachineInstr *MI = SU->getInstr();
395 unsigned Reg = MI->getOperand(OperIdx).getReg();
397 // SSA defs do not have output/anti dependencies.
398 // The current operand is a def, so we have at least one.
399 if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
402 // Add output dependence to the next nearest def of this vreg.
404 // Unless this definition is dead, the output dependence should be
405 // transitively redundant with antidependencies from this definition's
406 // uses. We're conservative for now until we have a way to guarantee the uses
407 // are not eliminated sometime during scheduling. The output dependence edge
408 // is also useful if output latency exceeds def-use latency.
409 VReg2SUnitMap::iterator DefI = findVRegDef(Reg);
410 if (DefI == VRegDefs.end())
411 VRegDefs.insert(VReg2SUnit(Reg, SU));
413 SUnit *DefSU = DefI->SU;
414 if (DefSU != SU && DefSU != &ExitSU) {
415 unsigned OutLatency = TII->getOutputLatency(InstrItins, MI, OperIdx,
417 DefSU->addPred(SDep(SU, SDep::Output, OutLatency, Reg));
423 /// addVRegUseDeps - Add a register data dependency if the instruction that
424 /// defines the virtual register used at OperIdx is mapped to an SUnit. Add a
425 /// register antidependency from this SUnit to instructions that occur later in
426 /// the same scheduling region if they write the virtual register.
428 /// TODO: Handle ExitSU "uses" properly.
429 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
430 MachineInstr *MI = SU->getInstr();
431 unsigned Reg = MI->getOperand(OperIdx).getReg();
433 // Lookup this operand's reaching definition.
434 assert(LIS && "vreg dependencies requires LiveIntervals");
435 SlotIndex UseIdx = LIS->getInstructionIndex(MI).getRegSlot();
436 LiveInterval *LI = &LIS->getInterval(Reg);
437 VNInfo *VNI = LI->getVNInfoBefore(UseIdx);
438 // VNI will be valid because MachineOperand::readsReg() is checked by caller.
439 MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def);
440 // Phis and other noninstructions (after coalescing) have a NULL Def.
442 SUnit *DefSU = getSUnit(Def);
444 // The reaching Def lives within this scheduling region.
445 // Create a data dependence.
447 // TODO: Handle "special" address latencies cleanly.
448 const SDep &dep = SDep(DefSU, SDep::Data, DefSU->Latency, Reg);
449 if (!UnitLatencies) {
450 // Adjust the dependence latency using operand def/use information, then
451 // allow the target to perform its own adjustments.
452 ComputeOperandLatency(DefSU, SU, const_cast<SDep &>(dep));
453 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
454 ST.adjustSchedDependency(DefSU, SU, const_cast<SDep &>(dep));
460 // Add antidependence to the following def of the vreg it uses.
461 VReg2SUnitMap::iterator DefI = findVRegDef(Reg);
462 if (DefI != VRegDefs.end() && DefI->SU != SU)
463 DefI->SU->addPred(SDep(SU, SDep::Anti, 0, Reg));
466 /// Create an SUnit for each real instruction, numbered in top-down toplological
467 /// order. The instruction order A < B, implies that no edge exists from B to A.
469 /// Map each real instruction to its SUnit.
471 /// After initSUnits, the SUnits vector is cannot be resized and the scheduler
472 /// may hang onto SUnit pointers. We may relax this in the future by using SUnit
473 /// IDs instead of pointers.
474 void ScheduleDAGInstrs::initSUnits() {
475 // We'll be allocating one SUnit for each real instruction in the region,
476 // which is contained within a basic block.
477 SUnits.reserve(BB->size());
479 for (MachineBasicBlock::iterator I = Begin; I != InsertPos; ++I) {
480 MachineInstr *MI = I;
481 if (MI->isDebugValue())
484 SUnit *SU = NewSUnit(MI);
487 SU->isCall = MI->isCall();
488 SU->isCommutable = MI->isCommutable();
490 // Assign the Latency field of SU using target-provided information.
498 void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
499 // Create an SUnit for each real instruction.
502 // We build scheduling units by walking a block's instruction list from bottom
505 // Remember where a generic side-effecting instruction is as we procede.
506 SUnit *BarrierChain = 0, *AliasChain = 0;
508 // Memory references to specific known memory locations are tracked
509 // so that they can be given more precise dependencies. We track
510 // separately the known memory locations that may alias and those
511 // that are known not to alias
512 std::map<const Value *, SUnit *> AliasMemDefs, NonAliasMemDefs;
513 std::map<const Value *, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses;
515 // Remove any stale debug info; sometimes BuildSchedGraph is called again
516 // without emitting the info from the previous call.
518 FirstDbgValue = NULL;
520 assert(Defs.empty() && Uses.empty() &&
521 "Only BuildGraph should update Defs/Uses");
522 Defs.setRegLimit(TRI->getNumRegs());
523 Uses.setRegLimit(TRI->getNumRegs());
525 assert(VRegDefs.empty() && "Only BuildSchedGraph may access VRegDefs");
526 // FIXME: Allow SparseSet to reserve space for the creation of virtual
527 // registers during scheduling. Don't artificially inflate the Universe
528 // because we want to assert that vregs are not created during DAG building.
529 VRegDefs.setUniverse(MRI.getNumVirtRegs());
531 // Model data dependencies between instructions being scheduled and the
533 AddSchedBarrierDeps();
535 // Walk the list of instructions, from bottom moving up.
536 MachineInstr *PrevMI = NULL;
537 for (MachineBasicBlock::iterator MII = InsertPos, MIE = Begin;
539 MachineInstr *MI = prior(MII);
541 DbgValues.push_back(std::make_pair(PrevMI, MI));
545 if (MI->isDebugValue()) {
550 assert(!MI->isTerminator() && !MI->isLabel() &&
551 "Cannot schedule terminators or labels!");
553 SUnit *SU = MISUnitMap[MI];
554 assert(SU && "No SUnit mapped to this MI");
556 // Add register-based dependencies (data, anti, and output).
557 for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
558 const MachineOperand &MO = MI->getOperand(j);
559 if (!MO.isReg()) continue;
560 unsigned Reg = MO.getReg();
561 if (Reg == 0) continue;
563 if (TRI->isPhysicalRegister(Reg))
564 addPhysRegDeps(SU, j);
566 assert(!IsPostRA && "Virtual register encountered!");
568 addVRegDefDeps(SU, j);
569 else if (MO.readsReg()) // ignore undef operands
570 addVRegUseDeps(SU, j);
574 // Add chain dependencies.
575 // Chain dependencies used to enforce memory order should have
576 // latency of 0 (except for true dependency of Store followed by
577 // aliased Load... we estimate that with a single cycle of latency
578 // assuming the hardware will bypass)
579 // Note that isStoreToStackSlot and isLoadFromStackSLot are not usable
580 // after stack slots are lowered to actual addresses.
581 // TODO: Use an AliasAnalysis and do real alias-analysis queries, and
582 // produce more precise dependence information.
583 #define STORE_LOAD_LATENCY 1
584 unsigned TrueMemOrderLatency = 0;
585 if (MI->isCall() || MI->hasUnmodeledSideEffects() ||
586 (MI->hasVolatileMemoryRef() &&
587 (!MI->mayLoad() || !MI->isInvariantLoad(AA)))) {
588 // Be conservative with these and add dependencies on all memory
589 // references, even those that are known to not alias.
590 for (std::map<const Value *, SUnit *>::iterator I =
591 NonAliasMemDefs.begin(), E = NonAliasMemDefs.end(); I != E; ++I) {
592 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
594 for (std::map<const Value *, std::vector<SUnit *> >::iterator I =
595 NonAliasMemUses.begin(), E = NonAliasMemUses.end(); I != E; ++I) {
596 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
597 I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
599 NonAliasMemDefs.clear();
600 NonAliasMemUses.clear();
601 // Add SU to the barrier chain.
603 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
608 // Chain all possibly aliasing memory references though SU.
610 AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
612 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
613 PendingLoads[k]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
614 for (std::map<const Value *, SUnit *>::iterator I = AliasMemDefs.begin(),
615 E = AliasMemDefs.end(); I != E; ++I) {
616 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
618 for (std::map<const Value *, std::vector<SUnit *> >::iterator I =
619 AliasMemUses.begin(), E = AliasMemUses.end(); I != E; ++I) {
620 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
621 I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
623 PendingLoads.clear();
624 AliasMemDefs.clear();
625 AliasMemUses.clear();
626 } else if (MI->mayStore()) {
627 bool MayAlias = true;
628 TrueMemOrderLatency = STORE_LOAD_LATENCY;
629 if (const Value *V = getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
630 // A store to a specific PseudoSourceValue. Add precise dependencies.
631 // Record the def in MemDefs, first adding a dep if there is
633 std::map<const Value *, SUnit *>::iterator I =
634 ((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
635 std::map<const Value *, SUnit *>::iterator IE =
636 ((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
638 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0, /*Reg=*/0,
639 /*isNormalMemory=*/true));
643 AliasMemDefs[V] = SU;
645 NonAliasMemDefs[V] = SU;
647 // Handle the uses in MemUses, if there are any.
648 std::map<const Value *, std::vector<SUnit *> >::iterator J =
649 ((MayAlias) ? AliasMemUses.find(V) : NonAliasMemUses.find(V));
650 std::map<const Value *, std::vector<SUnit *> >::iterator JE =
651 ((MayAlias) ? AliasMemUses.end() : NonAliasMemUses.end());
653 for (unsigned i = 0, e = J->second.size(); i != e; ++i)
654 J->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency,
655 /*Reg=*/0, /*isNormalMemory=*/true));
659 // Add dependencies from all the PendingLoads, i.e. loads
660 // with no underlying object.
661 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
662 PendingLoads[k]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
663 // Add dependence on alias chain, if needed.
665 AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
667 // Add dependence on barrier chain, if needed.
669 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
671 // Treat all other stores conservatively.
672 goto new_alias_chain;
675 if (!ExitSU.isPred(SU))
676 // Push store's up a bit to avoid them getting in between cmp
678 ExitSU.addPred(SDep(SU, SDep::Order, 0,
679 /*Reg=*/0, /*isNormalMemory=*/false,
680 /*isMustAlias=*/false,
681 /*isArtificial=*/true));
682 } else if (MI->mayLoad()) {
683 bool MayAlias = true;
684 TrueMemOrderLatency = 0;
685 if (MI->isInvariantLoad(AA)) {
686 // Invariant load, no chain dependencies needed!
689 getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
690 // A load from a specific PseudoSourceValue. Add precise dependencies.
691 std::map<const Value *, SUnit *>::iterator I =
692 ((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
693 std::map<const Value *, SUnit *>::iterator IE =
694 ((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
696 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0, /*Reg=*/0,
697 /*isNormalMemory=*/true));
699 AliasMemUses[V].push_back(SU);
701 NonAliasMemUses[V].push_back(SU);
703 // A load with no underlying object. Depend on all
704 // potentially aliasing stores.
705 for (std::map<const Value *, SUnit *>::iterator I =
706 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I)
707 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
709 PendingLoads.push_back(SU);
713 // Add dependencies on alias and barrier chains, if needed.
714 if (MayAlias && AliasChain)
715 AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
717 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
722 FirstDbgValue = PrevMI;
727 PendingLoads.clear();
731 void ScheduleDAGInstrs::ComputeLatency(SUnit *SU) {
732 // Compute the latency for the node.
733 if (!InstrItins || InstrItins->isEmpty()) {
736 // Simplistic target-independent heuristic: assume that loads take
738 if (SU->getInstr()->mayLoad())
741 SU->Latency = TII->getInstrLatency(InstrItins, SU->getInstr());
745 void ScheduleDAGInstrs::ComputeOperandLatency(SUnit *Def, SUnit *Use,
747 if (!InstrItins || InstrItins->isEmpty())
750 // For a data dependency with a known register...
751 if ((dep.getKind() != SDep::Data) || (dep.getReg() == 0))
754 const unsigned Reg = dep.getReg();
756 // ... find the definition of the register in the defining
758 MachineInstr *DefMI = Def->getInstr();
759 int DefIdx = DefMI->findRegisterDefOperandIdx(Reg);
761 const MachineOperand &MO = DefMI->getOperand(DefIdx);
762 if (MO.isReg() && MO.isImplicit() &&
763 DefIdx >= (int)DefMI->getDesc().getNumOperands()) {
764 // This is an implicit def, getOperandLatency() won't return the correct
766 // %D6<def>, %D7<def> = VLD1q16 %R2<kill>, 0, ..., %Q3<imp-def>
767 // %Q1<def> = VMULv8i16 %Q1<kill>, %Q3<kill>, ...
768 // What we want is to compute latency between def of %D6/%D7 and use of
770 unsigned Op2 = DefMI->findRegisterDefOperandIdx(Reg, false, true, TRI);
771 if (DefMI->getOperand(Op2).isReg())
774 MachineInstr *UseMI = Use->getInstr();
775 // For all uses of the register, calculate the maxmimum latency
778 for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) {
779 const MachineOperand &MO = UseMI->getOperand(i);
780 if (!MO.isReg() || !MO.isUse())
782 unsigned MOReg = MO.getReg();
786 int UseCycle = TII->getOperandLatency(InstrItins, DefMI, DefIdx,
788 Latency = std::max(Latency, UseCycle);
791 // UseMI is null, then it must be a scheduling barrier.
792 if (!InstrItins || InstrItins->isEmpty())
794 unsigned DefClass = DefMI->getDesc().getSchedClass();
795 Latency = InstrItins->getOperandCycle(DefClass, DefIdx);
798 // If we found a latency, then replace the existing dependence latency.
800 dep.setLatency(Latency);
804 void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
805 SU->getInstr()->dump();
808 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
810 raw_string_ostream oss(s);
813 else if (SU == &ExitSU)
816 SU->getInstr()->print(oss);
820 /// Return the basic block label. It is not necessarilly unique because a block
821 /// contains multiple scheduling regions. But it is fine for visualization.
822 std::string ScheduleDAGInstrs::getDAGName() const {
823 return "dag." + BB->getFullName();