1 //===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the ScheduleDAGInstrs class, which implements re-scheduling
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
16 #include "llvm/ADT/MapVector.h"
17 #include "llvm/ADT/SmallPtrSet.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/ValueTracking.h"
21 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineMemOperand.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/CodeGen/RegisterPressure.h"
29 #include "llvm/CodeGen/ScheduleDFS.h"
30 #include "llvm/IR/Operator.h"
31 #include "llvm/MC/MCInstrItineraries.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/Format.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
44 #define DEBUG_TYPE "misched"
46 static cl::opt<bool> EnableAASchedMI("enable-aa-sched-mi", cl::Hidden,
47 cl::ZeroOrMore, cl::init(false),
48 cl::desc("Enable use of AA during MI DAG construction"));
50 static cl::opt<bool> UseTBAA("use-tbaa-in-sched-mi", cl::Hidden,
51 cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"));
53 ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
54 const MachineLoopInfo *mli,
55 bool IsPostRAFlag, bool RemoveKillFlags,
57 : ScheduleDAG(mf), MLI(mli), MFI(mf.getFrameInfo()), LIS(lis),
58 IsPostRA(IsPostRAFlag), RemoveKillFlags(RemoveKillFlags),
59 CanHandleTerminators(false), FirstDbgValue(nullptr) {
60 assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
62 assert(!(IsPostRA && MRI.getNumVirtRegs()) &&
63 "Virtual registers must be removed prior to PostRA scheduling");
65 const TargetSubtargetInfo &ST = mf.getSubtarget();
66 SchedModel.init(ST.getSchedModel(), &ST, TII);
69 /// getUnderlyingObjectFromInt - This is the function that does the work of
70 /// looking through basic ptrtoint+arithmetic+inttoptr sequences.
71 static const Value *getUnderlyingObjectFromInt(const Value *V) {
73 if (const Operator *U = dyn_cast<Operator>(V)) {
74 // If we find a ptrtoint, we can transfer control back to the
75 // regular getUnderlyingObjectFromInt.
76 if (U->getOpcode() == Instruction::PtrToInt)
77 return U->getOperand(0);
78 // If we find an add of a constant, a multiplied value, or a phi, it's
79 // likely that the other operand will lead us to the base
80 // object. We don't have to worry about the case where the
81 // object address is somehow being computed by the multiply,
82 // because our callers only care when the result is an
83 // identifiable object.
84 if (U->getOpcode() != Instruction::Add ||
85 (!isa<ConstantInt>(U->getOperand(1)) &&
86 Operator::getOpcode(U->getOperand(1)) != Instruction::Mul &&
87 !isa<PHINode>(U->getOperand(1))))
93 assert(V->getType()->isIntegerTy() && "Unexpected operand type!");
97 /// getUnderlyingObjects - This is a wrapper around GetUnderlyingObjects
98 /// and adds support for basic ptrtoint+arithmetic+inttoptr sequences.
99 static void getUnderlyingObjects(const Value *V,
100 SmallVectorImpl<Value *> &Objects,
101 const DataLayout &DL) {
102 SmallPtrSet<const Value *, 16> Visited;
103 SmallVector<const Value *, 4> Working(1, V);
105 V = Working.pop_back_val();
107 SmallVector<Value *, 4> Objs;
108 GetUnderlyingObjects(const_cast<Value *>(V), Objs, DL);
110 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(), IE = Objs.end();
113 if (!Visited.insert(V).second)
115 if (Operator::getOpcode(V) == Instruction::IntToPtr) {
117 getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0));
118 if (O->getType()->isPointerTy()) {
119 Working.push_back(O);
123 Objects.push_back(const_cast<Value *>(V));
125 } while (!Working.empty());
128 typedef PointerUnion<const Value *, const PseudoSourceValue *> ValueType;
129 typedef SmallVector<PointerIntPair<ValueType, 1, bool>, 4>
130 UnderlyingObjectsVector;
132 /// getUnderlyingObjectsForInstr - If this machine instr has memory reference
133 /// information and it can be tracked to a normal reference to a known
134 /// object, return the Value for that object.
135 static void getUnderlyingObjectsForInstr(const MachineInstr *MI,
136 const MachineFrameInfo *MFI,
137 UnderlyingObjectsVector &Objects,
138 const DataLayout &DL) {
139 if (!MI->hasOneMemOperand() ||
140 (!(*MI->memoperands_begin())->getValue() &&
141 !(*MI->memoperands_begin())->getPseudoValue()) ||
142 (*MI->memoperands_begin())->isVolatile())
145 if (const PseudoSourceValue *PSV =
146 (*MI->memoperands_begin())->getPseudoValue()) {
147 // Function that contain tail calls don't have unique PseudoSourceValue
148 // objects. Two PseudoSourceValues might refer to the same or overlapping
149 // locations. The client code calling this function assumes this is not the
150 // case. So return a conservative answer of no known object.
151 if (MFI->hasTailCall())
154 // For now, ignore PseudoSourceValues which may alias LLVM IR values
155 // because the code that uses this function has no way to cope with
157 if (!PSV->isAliased(MFI)) {
158 bool MayAlias = PSV->mayAlias(MFI);
159 Objects.push_back(UnderlyingObjectsVector::value_type(PSV, MayAlias));
164 const Value *V = (*MI->memoperands_begin())->getValue();
168 SmallVector<Value *, 4> Objs;
169 getUnderlyingObjects(V, Objs, DL);
171 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(), IE = Objs.end();
175 if (!isIdentifiedObject(V)) {
180 Objects.push_back(UnderlyingObjectsVector::value_type(V, true));
184 void ScheduleDAGInstrs::startBlock(MachineBasicBlock *bb) {
188 void ScheduleDAGInstrs::finishBlock() {
189 // Subclasses should no longer refer to the old block.
193 /// Initialize the DAG and common scheduler state for the current scheduling
194 /// region. This does not actually create the DAG, only clears it. The
195 /// scheduling driver may call BuildSchedGraph multiple times per scheduling
197 void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb,
198 MachineBasicBlock::iterator begin,
199 MachineBasicBlock::iterator end,
200 unsigned regioninstrs) {
201 assert(bb == BB && "startBlock should set BB");
204 NumRegionInstrs = regioninstrs;
207 /// Close the current scheduling region. Don't clear any state in case the
208 /// driver wants to refer to the previous scheduling region.
209 void ScheduleDAGInstrs::exitRegion() {
213 /// addSchedBarrierDeps - Add dependencies from instructions in the current
214 /// list of instructions being scheduled to scheduling barrier by adding
215 /// the exit SU to the register defs and use list. This is because we want to
216 /// make sure instructions which define registers that are either used by
217 /// the terminator or are live-out are properly scheduled. This is
218 /// especially important when the definition latency of the return value(s)
219 /// are too high to be hidden by the branch or when the liveout registers
220 /// used by instructions in the fallthrough block.
221 void ScheduleDAGInstrs::addSchedBarrierDeps() {
222 MachineInstr *ExitMI = RegionEnd != BB->end() ? &*RegionEnd : nullptr;
223 ExitSU.setInstr(ExitMI);
224 bool AllDepKnown = ExitMI &&
225 (ExitMI->isCall() || ExitMI->isBarrier());
226 if (ExitMI && AllDepKnown) {
227 // If it's a call or a barrier, add dependencies on the defs and uses of
229 for (unsigned i = 0, e = ExitMI->getNumOperands(); i != e; ++i) {
230 const MachineOperand &MO = ExitMI->getOperand(i);
231 if (!MO.isReg() || MO.isDef()) continue;
232 unsigned Reg = MO.getReg();
233 if (Reg == 0) continue;
235 if (TRI->isPhysicalRegister(Reg))
236 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
238 assert(!IsPostRA && "Virtual register encountered after regalloc.");
239 if (MO.readsReg()) // ignore undef operands
240 addVRegUseDeps(&ExitSU, i);
244 // For others, e.g. fallthrough, conditional branch, assume the exit
245 // uses all the registers that are livein to the successor blocks.
246 assert(Uses.empty() && "Uses in set before adding deps?");
247 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
248 SE = BB->succ_end(); SI != SE; ++SI)
249 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
250 E = (*SI)->livein_end(); I != E; ++I) {
252 if (!Uses.contains(Reg))
253 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
258 /// MO is an operand of SU's instruction that defines a physical register. Add
259 /// data dependencies from SU to any uses of the physical register.
260 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
261 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
262 assert(MO.isDef() && "expect physreg def");
264 // Ask the target if address-backscheduling is desirable, and if so how much.
265 const TargetSubtargetInfo &ST = MF.getSubtarget();
267 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
268 Alias.isValid(); ++Alias) {
269 if (!Uses.contains(*Alias))
271 for (Reg2SUnitsMap::iterator I = Uses.find(*Alias); I != Uses.end(); ++I) {
272 SUnit *UseSU = I->SU;
276 // Adjust the dependence latency using operand def/use information,
277 // then allow the target to perform its own adjustments.
278 int UseOp = I->OpIdx;
279 MachineInstr *RegUse = nullptr;
282 Dep = SDep(SU, SDep::Artificial);
284 // Set the hasPhysRegDefs only for physreg defs that have a use within
285 // the scheduling region.
286 SU->hasPhysRegDefs = true;
287 Dep = SDep(SU, SDep::Data, *Alias);
288 RegUse = UseSU->getInstr();
291 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse,
294 ST.adjustSchedDependency(SU, UseSU, Dep);
300 /// addPhysRegDeps - Add register dependencies (data, anti, and output) from
301 /// this SUnit to following instructions in the same scheduling region that
302 /// depend the physical register referenced at OperIdx.
303 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
304 MachineInstr *MI = SU->getInstr();
305 MachineOperand &MO = MI->getOperand(OperIdx);
307 // Optionally add output and anti dependencies. For anti
308 // dependencies we use a latency of 0 because for a multi-issue
309 // target we want to allow the defining instruction to issue
310 // in the same cycle as the using instruction.
311 // TODO: Using a latency of 1 here for output dependencies assumes
312 // there's no cost for reusing registers.
313 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
314 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
315 Alias.isValid(); ++Alias) {
316 if (!Defs.contains(*Alias))
318 for (Reg2SUnitsMap::iterator I = Defs.find(*Alias); I != Defs.end(); ++I) {
319 SUnit *DefSU = I->SU;
320 if (DefSU == &ExitSU)
323 (Kind != SDep::Output || !MO.isDead() ||
324 !DefSU->getInstr()->registerDefIsDead(*Alias))) {
325 if (Kind == SDep::Anti)
326 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias));
328 SDep Dep(SU, Kind, /*Reg=*/*Alias);
330 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
338 SU->hasPhysRegUses = true;
339 // Either insert a new Reg2SUnits entry with an empty SUnits list, or
340 // retrieve the existing SUnits list for this register's uses.
341 // Push this SUnit on the use list.
342 Uses.insert(PhysRegSUOper(SU, OperIdx, MO.getReg()));
347 addPhysRegDataDeps(SU, OperIdx);
348 unsigned Reg = MO.getReg();
350 // clear this register's use list
351 if (Uses.contains(Reg))
356 } else if (SU->isCall) {
357 // Calls will not be reordered because of chain dependencies (see
358 // below). Since call operands are dead, calls may continue to be added
359 // to the DefList making dependence checking quadratic in the size of
360 // the block. Instead, we leave only one call at the back of the
362 Reg2SUnitsMap::RangePair P = Defs.equal_range(Reg);
363 Reg2SUnitsMap::iterator B = P.first;
364 Reg2SUnitsMap::iterator I = P.second;
365 for (bool isBegin = I == B; !isBegin; /* empty */) {
366 isBegin = (--I) == B;
373 // Defs are pushed in the order they are visited and never reordered.
374 Defs.insert(PhysRegSUOper(SU, OperIdx, Reg));
378 /// addVRegDefDeps - Add register output and data dependencies from this SUnit
379 /// to instructions that occur later in the same scheduling region if they read
380 /// from or write to the virtual register defined at OperIdx.
382 /// TODO: Hoist loop induction variable increments. This has to be
383 /// reevaluated. Generally, IV scheduling should be done before coalescing.
384 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
385 const MachineInstr *MI = SU->getInstr();
386 unsigned Reg = MI->getOperand(OperIdx).getReg();
388 // Singly defined vregs do not have output/anti dependencies.
389 // The current operand is a def, so we have at least one.
390 // Check here if there are any others...
391 if (MRI.hasOneDef(Reg))
394 // Add output dependence to the next nearest def of this vreg.
396 // Unless this definition is dead, the output dependence should be
397 // transitively redundant with antidependencies from this definition's
398 // uses. We're conservative for now until we have a way to guarantee the uses
399 // are not eliminated sometime during scheduling. The output dependence edge
400 // is also useful if output latency exceeds def-use latency.
401 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
402 if (DefI == VRegDefs.end())
403 VRegDefs.insert(VReg2SUnit(Reg, SU));
405 SUnit *DefSU = DefI->SU;
406 if (DefSU != SU && DefSU != &ExitSU) {
407 SDep Dep(SU, SDep::Output, Reg);
409 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
416 /// addVRegUseDeps - Add a register data dependency if the instruction that
417 /// defines the virtual register used at OperIdx is mapped to an SUnit. Add a
418 /// register antidependency from this SUnit to instructions that occur later in
419 /// the same scheduling region if they write the virtual register.
421 /// TODO: Handle ExitSU "uses" properly.
422 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
423 MachineInstr *MI = SU->getInstr();
424 unsigned Reg = MI->getOperand(OperIdx).getReg();
426 // Record this local VReg use.
427 VReg2UseMap::iterator UI = VRegUses.find(Reg);
428 for (; UI != VRegUses.end(); ++UI) {
432 if (UI == VRegUses.end())
433 VRegUses.insert(VReg2SUnit(Reg, SU));
435 // Lookup this operand's reaching definition.
436 assert(LIS && "vreg dependencies requires LiveIntervals");
438 = LIS->getInterval(Reg).Query(LIS->getInstructionIndex(MI));
439 VNInfo *VNI = LRQ.valueIn();
441 // VNI will be valid because MachineOperand::readsReg() is checked by caller.
442 assert(VNI && "No value to read by operand");
443 MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def);
444 // Phis and other noninstructions (after coalescing) have a NULL Def.
446 SUnit *DefSU = getSUnit(Def);
448 // The reaching Def lives within this scheduling region.
449 // Create a data dependence.
450 SDep dep(DefSU, SDep::Data, Reg);
451 // Adjust the dependence latency using operand def/use information, then
452 // allow the target to perform its own adjustments.
453 int DefOp = Def->findRegisterDefOperandIdx(Reg);
454 dep.setLatency(SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx));
456 const TargetSubtargetInfo &ST = MF.getSubtarget();
457 ST.adjustSchedDependency(DefSU, SU, const_cast<SDep &>(dep));
462 // Add antidependence to the following def of the vreg it uses.
463 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
464 if (DefI != VRegDefs.end() && DefI->SU != SU)
465 DefI->SU->addPred(SDep(SU, SDep::Anti, Reg));
468 /// Return true if MI is an instruction we are unable to reason about
469 /// (like a call or something with unmodeled side effects).
470 static inline bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) {
471 if (MI->isCall() || MI->hasUnmodeledSideEffects() ||
472 (MI->hasOrderedMemoryRef() &&
473 (!MI->mayLoad() || !MI->isInvariantLoad(AA))))
478 // This MI might have either incomplete info, or known to be unsafe
479 // to deal with (i.e. volatile object).
480 static inline bool isUnsafeMemoryObject(MachineInstr *MI,
481 const MachineFrameInfo *MFI,
482 const DataLayout &DL) {
483 if (!MI || MI->memoperands_empty())
485 // We purposefully do no check for hasOneMemOperand() here
486 // in hope to trigger an assert downstream in order to
487 // finish implementation.
488 if ((*MI->memoperands_begin())->isVolatile() ||
489 MI->hasUnmodeledSideEffects())
492 if ((*MI->memoperands_begin())->getPseudoValue()) {
493 // Similarly to getUnderlyingObjectForInstr:
494 // For now, ignore PseudoSourceValues which may alias LLVM IR values
495 // because the code that uses this function has no way to cope with
500 const Value *V = (*MI->memoperands_begin())->getValue();
504 SmallVector<Value *, 4> Objs;
505 getUnderlyingObjects(V, Objs, DL);
506 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(),
507 IE = Objs.end(); I != IE; ++I) {
508 // Does this pointer refer to a distinct and identifiable object?
509 if (!isIdentifiedObject(*I))
516 /// This returns true if the two MIs need a chain edge betwee them.
517 /// If these are not even memory operations, we still may need
518 /// chain deps between them. The question really is - could
519 /// these two MIs be reordered during scheduling from memory dependency
521 static bool MIsNeedChainEdge(AliasAnalysis *AA, const MachineFrameInfo *MFI,
522 const DataLayout &DL, MachineInstr *MIa,
524 const MachineFunction *MF = MIa->getParent()->getParent();
525 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
527 // Cover a trivial case - no edge is need to itself.
531 // Let the target decide if memory accesses cannot possibly overlap.
532 if ((MIa->mayLoad() || MIa->mayStore()) &&
533 (MIb->mayLoad() || MIb->mayStore()))
534 if (TII->areMemAccessesTriviallyDisjoint(MIa, MIb, AA))
537 // FIXME: Need to handle multiple memory operands to support all targets.
538 if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand())
541 if (isUnsafeMemoryObject(MIa, MFI, DL) || isUnsafeMemoryObject(MIb, MFI, DL))
544 // If we are dealing with two "normal" loads, we do not need an edge
545 // between them - they could be reordered.
546 if (!MIa->mayStore() && !MIb->mayStore())
549 // To this point analysis is generic. From here on we do need AA.
553 MachineMemOperand *MMOa = *MIa->memoperands_begin();
554 MachineMemOperand *MMOb = *MIb->memoperands_begin();
556 if (!MMOa->getValue() || !MMOb->getValue())
559 // The following interface to AA is fashioned after DAGCombiner::isAlias
560 // and operates with MachineMemOperand offset with some important
562 // - LLVM fundamentally assumes flat address spaces.
563 // - MachineOperand offset can *only* result from legalization and
564 // cannot affect queries other than the trivial case of overlap
566 // - These offsets never wrap and never step outside
567 // of allocated objects.
568 // - There should never be any negative offsets here.
570 // FIXME: Modify API to hide this math from "user"
571 // FIXME: Even before we go to AA we can reason locally about some
572 // memory objects. It can save compile time, and possibly catch some
573 // corner cases not currently covered.
575 assert ((MMOa->getOffset() >= 0) && "Negative MachineMemOperand offset");
576 assert ((MMOb->getOffset() >= 0) && "Negative MachineMemOperand offset");
578 int64_t MinOffset = std::min(MMOa->getOffset(), MMOb->getOffset());
579 int64_t Overlapa = MMOa->getSize() + MMOa->getOffset() - MinOffset;
580 int64_t Overlapb = MMOb->getSize() + MMOb->getOffset() - MinOffset;
582 AliasAnalysis::AliasResult AAResult = AA->alias(
583 AliasAnalysis::Location(MMOa->getValue(), Overlapa,
584 UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
585 AliasAnalysis::Location(MMOb->getValue(), Overlapb,
586 UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
588 return (AAResult != AliasAnalysis::NoAlias);
591 /// This recursive function iterates over chain deps of SUb looking for
592 /// "latest" node that needs a chain edge to SUa.
593 static unsigned iterateChainSucc(AliasAnalysis *AA, const MachineFrameInfo *MFI,
594 const DataLayout &DL, SUnit *SUa, SUnit *SUb,
595 SUnit *ExitSU, unsigned *Depth,
596 SmallPtrSetImpl<const SUnit *> &Visited) {
597 if (!SUa || !SUb || SUb == ExitSU)
600 // Remember visited nodes.
601 if (!Visited.insert(SUb).second)
603 // If there is _some_ dependency already in place, do not
604 // descend any further.
605 // TODO: Need to make sure that if that dependency got eliminated or ignored
606 // for any reason in the future, we would not violate DAG topology.
607 // Currently it does not happen, but makes an implicit assumption about
608 // future implementation.
610 // Independently, if we encounter node that is some sort of global
611 // object (like a call) we already have full set of dependencies to it
612 // and we can stop descending.
613 if (SUa->isSucc(SUb) ||
614 isGlobalMemoryObject(AA, SUb->getInstr()))
617 // If we do need an edge, or we have exceeded depth budget,
618 // add that edge to the predecessors chain of SUb,
619 // and stop descending.
621 MIsNeedChainEdge(AA, MFI, DL, SUa->getInstr(), SUb->getInstr())) {
622 SUb->addPred(SDep(SUa, SDep::MayAliasMem));
625 // Track current depth.
627 // Iterate over memory dependencies only.
628 for (SUnit::const_succ_iterator I = SUb->Succs.begin(), E = SUb->Succs.end();
630 if (I->isNormalMemoryOrBarrier())
631 iterateChainSucc(AA, MFI, DL, SUa, I->getSUnit(), ExitSU, Depth, Visited);
635 /// This function assumes that "downward" from SU there exist
636 /// tail/leaf of already constructed DAG. It iterates downward and
637 /// checks whether SU can be aliasing any node dominated
639 static void adjustChainDeps(AliasAnalysis *AA, const MachineFrameInfo *MFI,
640 const DataLayout &DL, SUnit *SU, SUnit *ExitSU,
641 std::set<SUnit *> &CheckList,
642 unsigned LatencyToLoad) {
646 SmallPtrSet<const SUnit*, 16> Visited;
649 for (std::set<SUnit *>::iterator I = CheckList.begin(), IE = CheckList.end();
653 if (MIsNeedChainEdge(AA, MFI, DL, SU->getInstr(), (*I)->getInstr())) {
654 SDep Dep(SU, SDep::MayAliasMem);
655 Dep.setLatency(((*I)->getInstr()->mayLoad()) ? LatencyToLoad : 0);
659 // Iterate recursively over all previously added memory chain
660 // successors. Keep track of visited nodes.
661 for (SUnit::const_succ_iterator J = (*I)->Succs.begin(),
662 JE = (*I)->Succs.end(); J != JE; ++J)
663 if (J->isNormalMemoryOrBarrier())
664 iterateChainSucc(AA, MFI, DL, SU, J->getSUnit(), ExitSU, &Depth,
669 /// Check whether two objects need a chain edge, if so, add it
670 /// otherwise remember the rejected SU.
671 static inline void addChainDependency(AliasAnalysis *AA,
672 const MachineFrameInfo *MFI,
673 const DataLayout &DL, SUnit *SUa,
674 SUnit *SUb, std::set<SUnit *> &RejectList,
675 unsigned TrueMemOrderLatency = 0,
676 bool isNormalMemory = false) {
677 // If this is a false dependency,
678 // do not add the edge, but rememeber the rejected node.
679 if (MIsNeedChainEdge(AA, MFI, DL, SUa->getInstr(), SUb->getInstr())) {
680 SDep Dep(SUa, isNormalMemory ? SDep::MayAliasMem : SDep::Barrier);
681 Dep.setLatency(TrueMemOrderLatency);
685 // Duplicate entries should be ignored.
686 RejectList.insert(SUb);
687 DEBUG(dbgs() << "\tReject chain dep between SU("
688 << SUa->NodeNum << ") and SU("
689 << SUb->NodeNum << ")\n");
693 /// Create an SUnit for each real instruction, numbered in top-down toplological
694 /// order. The instruction order A < B, implies that no edge exists from B to A.
696 /// Map each real instruction to its SUnit.
698 /// After initSUnits, the SUnits vector cannot be resized and the scheduler may
699 /// hang onto SUnit pointers. We may relax this in the future by using SUnit IDs
700 /// instead of pointers.
702 /// MachineScheduler relies on initSUnits numbering the nodes by their order in
703 /// the original instruction list.
704 void ScheduleDAGInstrs::initSUnits() {
705 // We'll be allocating one SUnit for each real instruction in the region,
706 // which is contained within a basic block.
707 SUnits.reserve(NumRegionInstrs);
709 for (MachineBasicBlock::iterator I = RegionBegin; I != RegionEnd; ++I) {
710 MachineInstr *MI = I;
711 if (MI->isDebugValue())
714 SUnit *SU = newSUnit(MI);
717 SU->isCall = MI->isCall();
718 SU->isCommutable = MI->isCommutable();
720 // Assign the Latency field of SU using target-provided information.
721 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
723 // If this SUnit uses a reserved or unbuffered resource, mark it as such.
725 // Reserved resources block an instruction from issuing and stall the
726 // entire pipeline. These are identified by BufferSize=0.
728 // Unbuffered resources prevent execution of subsequent instructions that
729 // require the same resources. This is used for in-order execution pipelines
730 // within an out-of-order core. These are identified by BufferSize=1.
731 if (SchedModel.hasInstrSchedModel()) {
732 const MCSchedClassDesc *SC = getSchedClass(SU);
733 for (TargetSchedModel::ProcResIter
734 PI = SchedModel.getWriteProcResBegin(SC),
735 PE = SchedModel.getWriteProcResEnd(SC); PI != PE; ++PI) {
736 switch (SchedModel.getProcResource(PI->ProcResourceIdx)->BufferSize) {
738 SU->hasReservedResource = true;
741 SU->isUnbuffered = true;
751 /// If RegPressure is non-null, compute register pressure as a side effect. The
752 /// DAG builder is an efficient place to do it because it already visits
754 void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
755 RegPressureTracker *RPTracker,
756 PressureDiffs *PDiffs) {
757 const TargetSubtargetInfo &ST = MF.getSubtarget();
758 bool UseAA = EnableAASchedMI.getNumOccurrences() > 0 ? EnableAASchedMI
760 AliasAnalysis *AAForDep = UseAA ? AA : nullptr;
763 ScheduleDAG::clearDAG();
765 // Create an SUnit for each real instruction.
769 PDiffs->init(SUnits.size());
771 // We build scheduling units by walking a block's instruction list from bottom
774 // Remember where a generic side-effecting instruction is as we procede.
775 SUnit *BarrierChain = nullptr, *AliasChain = nullptr;
777 // Memory references to specific known memory locations are tracked
778 // so that they can be given more precise dependencies. We track
779 // separately the known memory locations that may alias and those
780 // that are known not to alias
781 MapVector<ValueType, std::vector<SUnit *> > AliasMemDefs, NonAliasMemDefs;
782 MapVector<ValueType, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses;
783 std::set<SUnit*> RejectMemNodes;
785 // Remove any stale debug info; sometimes BuildSchedGraph is called again
786 // without emitting the info from the previous call.
788 FirstDbgValue = nullptr;
790 assert(Defs.empty() && Uses.empty() &&
791 "Only BuildGraph should update Defs/Uses");
792 Defs.setUniverse(TRI->getNumRegs());
793 Uses.setUniverse(TRI->getNumRegs());
795 assert(VRegDefs.empty() && "Only BuildSchedGraph may access VRegDefs");
797 VRegDefs.setUniverse(MRI.getNumVirtRegs());
798 VRegUses.setUniverse(MRI.getNumVirtRegs());
800 // Model data dependencies between instructions being scheduled and the
802 addSchedBarrierDeps();
804 // Walk the list of instructions, from bottom moving up.
805 MachineInstr *DbgMI = nullptr;
806 for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
808 MachineInstr *MI = std::prev(MII);
810 DbgValues.push_back(std::make_pair(DbgMI, MI));
814 if (MI->isDebugValue()) {
818 SUnit *SU = MISUnitMap[MI];
819 assert(SU && "No SUnit mapped to this MI");
822 PressureDiff *PDiff = PDiffs ? &(*PDiffs)[SU->NodeNum] : nullptr;
823 RPTracker->recede(/*LiveUses=*/nullptr, PDiff);
824 assert(RPTracker->getPos() == std::prev(MII) &&
825 "RPTracker can't find MI");
829 (CanHandleTerminators || (!MI->isTerminator() && !MI->isPosition())) &&
830 "Cannot schedule terminators or labels!");
832 // Add register-based dependencies (data, anti, and output).
833 bool HasVRegDef = false;
834 for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
835 const MachineOperand &MO = MI->getOperand(j);
836 if (!MO.isReg()) continue;
837 unsigned Reg = MO.getReg();
838 if (Reg == 0) continue;
840 if (TRI->isPhysicalRegister(Reg))
841 addPhysRegDeps(SU, j);
843 assert(!IsPostRA && "Virtual register encountered!");
846 addVRegDefDeps(SU, j);
848 else if (MO.readsReg()) // ignore undef operands
849 addVRegUseDeps(SU, j);
852 // If we haven't seen any uses in this scheduling region, create a
853 // dependence edge to ExitSU to model the live-out latency. This is required
854 // for vreg defs with no in-region use, and prefetches with no vreg def.
856 // FIXME: NumDataSuccs would be more precise than NumSuccs here. This
857 // check currently relies on being called before adding chain deps.
858 if (SU->NumSuccs == 0 && SU->Latency > 1
859 && (HasVRegDef || MI->mayLoad())) {
860 SDep Dep(SU, SDep::Artificial);
861 Dep.setLatency(SU->Latency - 1);
865 // Add chain dependencies.
866 // Chain dependencies used to enforce memory order should have
867 // latency of 0 (except for true dependency of Store followed by
868 // aliased Load... we estimate that with a single cycle of latency
869 // assuming the hardware will bypass)
870 // Note that isStoreToStackSlot and isLoadFromStackSLot are not usable
871 // after stack slots are lowered to actual addresses.
872 // TODO: Use an AliasAnalysis and do real alias-analysis queries, and
873 // produce more precise dependence information.
874 unsigned TrueMemOrderLatency = MI->mayStore() ? 1 : 0;
875 if (isGlobalMemoryObject(AA, MI)) {
876 // Be conservative with these and add dependencies on all memory
877 // references, even those that are known to not alias.
878 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
879 NonAliasMemDefs.begin(), E = NonAliasMemDefs.end(); I != E; ++I) {
880 for (unsigned i = 0, e = I->second.size(); i != e; ++i) {
881 I->second[i]->addPred(SDep(SU, SDep::Barrier));
884 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
885 NonAliasMemUses.begin(), E = NonAliasMemUses.end(); I != E; ++I) {
886 for (unsigned i = 0, e = I->second.size(); i != e; ++i) {
887 SDep Dep(SU, SDep::Barrier);
888 Dep.setLatency(TrueMemOrderLatency);
889 I->second[i]->addPred(Dep);
892 // Add SU to the barrier chain.
894 BarrierChain->addPred(SDep(SU, SDep::Barrier));
896 // This is a barrier event that acts as a pivotal node in the DAG,
897 // so it is safe to clear list of exposed nodes.
898 adjustChainDeps(AA, MFI, *TM.getDataLayout(), SU, &ExitSU, RejectMemNodes,
899 TrueMemOrderLatency);
900 RejectMemNodes.clear();
901 NonAliasMemDefs.clear();
902 NonAliasMemUses.clear();
906 // Chain all possibly aliasing memory references through SU.
908 unsigned ChainLatency = 0;
909 if (AliasChain->getInstr()->mayLoad())
910 ChainLatency = TrueMemOrderLatency;
911 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU, AliasChain,
912 RejectMemNodes, ChainLatency);
915 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
916 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU,
917 PendingLoads[k], RejectMemNodes,
918 TrueMemOrderLatency);
919 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
920 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I) {
921 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
922 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU,
923 I->second[i], RejectMemNodes);
925 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
926 AliasMemUses.begin(), E = AliasMemUses.end(); I != E; ++I) {
927 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
928 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU,
929 I->second[i], RejectMemNodes, TrueMemOrderLatency);
931 adjustChainDeps(AA, MFI, *TM.getDataLayout(), SU, &ExitSU, RejectMemNodes,
932 TrueMemOrderLatency);
933 PendingLoads.clear();
934 AliasMemDefs.clear();
935 AliasMemUses.clear();
936 } else if (MI->mayStore()) {
937 // Add dependence on barrier chain, if needed.
938 // There is no point to check aliasing on barrier event. Even if
939 // SU and barrier _could_ be reordered, they should not. In addition,
940 // we have lost all RejectMemNodes below barrier.
942 BarrierChain->addPred(SDep(SU, SDep::Barrier));
944 UnderlyingObjectsVector Objs;
945 getUnderlyingObjectsForInstr(MI, MFI, Objs, *TM.getDataLayout());
948 // Treat all other stores conservatively.
949 goto new_alias_chain;
952 bool MayAlias = false;
953 for (UnderlyingObjectsVector::iterator K = Objs.begin(), KE = Objs.end();
955 ValueType V = K->getPointer();
956 bool ThisMayAlias = K->getInt();
960 // A store to a specific PseudoSourceValue. Add precise dependencies.
961 // Record the def in MemDefs, first adding a dep if there is
963 MapVector<ValueType, std::vector<SUnit *> >::iterator I =
964 ((ThisMayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
965 MapVector<ValueType, std::vector<SUnit *> >::iterator IE =
966 ((ThisMayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
968 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
969 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU,
970 I->second[i], RejectMemNodes, 0, true);
972 // If we're not using AA, then we only need one store per object.
975 I->second.push_back(SU);
979 AliasMemDefs[V].clear();
980 AliasMemDefs[V].push_back(SU);
983 NonAliasMemDefs[V].clear();
984 NonAliasMemDefs[V].push_back(SU);
987 // Handle the uses in MemUses, if there are any.
988 MapVector<ValueType, std::vector<SUnit *> >::iterator J =
989 ((ThisMayAlias) ? AliasMemUses.find(V) : NonAliasMemUses.find(V));
990 MapVector<ValueType, std::vector<SUnit *> >::iterator JE =
991 ((ThisMayAlias) ? AliasMemUses.end() : NonAliasMemUses.end());
993 for (unsigned i = 0, e = J->second.size(); i != e; ++i)
994 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU,
995 J->second[i], RejectMemNodes,
996 TrueMemOrderLatency, true);
1001 // Add dependencies from all the PendingLoads, i.e. loads
1002 // with no underlying object.
1003 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
1004 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU,
1005 PendingLoads[k], RejectMemNodes,
1006 TrueMemOrderLatency);
1007 // Add dependence on alias chain, if needed.
1009 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU, AliasChain,
1012 adjustChainDeps(AA, MFI, *TM.getDataLayout(), SU, &ExitSU, RejectMemNodes,
1013 TrueMemOrderLatency);
1014 } else if (MI->mayLoad()) {
1015 bool MayAlias = true;
1016 if (MI->isInvariantLoad(AA)) {
1017 // Invariant load, no chain dependencies needed!
1019 UnderlyingObjectsVector Objs;
1020 getUnderlyingObjectsForInstr(MI, MFI, Objs, *TM.getDataLayout());
1023 // A load with no underlying object. Depend on all
1024 // potentially aliasing stores.
1025 for (MapVector<ValueType, std::vector<SUnit *> >::iterator I =
1026 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I)
1027 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
1028 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU,
1029 I->second[i], RejectMemNodes);
1031 PendingLoads.push_back(SU);
1037 for (UnderlyingObjectsVector::iterator
1038 J = Objs.begin(), JE = Objs.end(); J != JE; ++J) {
1039 ValueType V = J->getPointer();
1040 bool ThisMayAlias = J->getInt();
1045 // A load from a specific PseudoSourceValue. Add precise dependencies.
1046 MapVector<ValueType, std::vector<SUnit *> >::iterator I =
1047 ((ThisMayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
1048 MapVector<ValueType, std::vector<SUnit *> >::iterator IE =
1049 ((ThisMayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
1051 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
1052 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU,
1053 I->second[i], RejectMemNodes, 0, true);
1055 AliasMemUses[V].push_back(SU);
1057 NonAliasMemUses[V].push_back(SU);
1060 adjustChainDeps(AA, MFI, *TM.getDataLayout(), SU, &ExitSU,
1061 RejectMemNodes, /*Latency=*/0);
1062 // Add dependencies on alias and barrier chains, if needed.
1063 if (MayAlias && AliasChain)
1064 addChainDependency(AAForDep, MFI, *TM.getDataLayout(), SU, AliasChain,
1067 BarrierChain->addPred(SDep(SU, SDep::Barrier));
1072 FirstDbgValue = DbgMI;
1077 PendingLoads.clear();
1080 /// \brief Initialize register live-range state for updating kills.
1081 void ScheduleDAGInstrs::startBlockForKills(MachineBasicBlock *BB) {
1082 // Start with no live registers.
1085 // Examine the live-in regs of all successors.
1086 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
1087 SE = BB->succ_end(); SI != SE; ++SI) {
1088 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
1089 E = (*SI)->livein_end(); I != E; ++I) {
1091 // Repeat, for reg and all subregs.
1092 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1093 SubRegs.isValid(); ++SubRegs)
1094 LiveRegs.set(*SubRegs);
1099 /// \brief If we change a kill flag on the bundle instruction implicit register
1100 /// operands, then we also need to propagate that to any instructions inside
1101 /// the bundle which had the same kill state.
1102 static void toggleBundleKillFlag(MachineInstr *MI, unsigned Reg,
1103 bool NewKillState) {
1104 if (MI->getOpcode() != TargetOpcode::BUNDLE)
1107 // Walk backwards from the last instruction in the bundle to the first.
1108 // Once we set a kill flag on an instruction, we bail out, as otherwise we
1109 // might set it on too many operands. We will clear as many flags as we
1111 MachineBasicBlock::instr_iterator Begin = MI;
1112 MachineBasicBlock::instr_iterator End = getBundleEnd(MI);
1113 while (Begin != End) {
1114 for (MIOperands MO(--End); MO.isValid(); ++MO) {
1115 if (!MO->isReg() || MO->isDef() || Reg != MO->getReg())
1118 // DEBUG_VALUE nodes do not contribute to code generation and should
1119 // always be ignored. Failure to do so may result in trying to modify
1120 // KILL flags on DEBUG_VALUE nodes, which is distressing.
1124 // If the register has the internal flag then it could be killing an
1125 // internal def of the register. In this case, just skip. We only want
1126 // to toggle the flag on operands visible outside the bundle.
1127 if (MO->isInternalRead())
1130 if (MO->isKill() == NewKillState)
1132 MO->setIsKill(NewKillState);
1139 bool ScheduleDAGInstrs::toggleKillFlag(MachineInstr *MI, MachineOperand &MO) {
1140 // Setting kill flag...
1143 toggleBundleKillFlag(MI, MO.getReg(), true);
1147 // If MO itself is live, clear the kill flag...
1148 if (LiveRegs.test(MO.getReg())) {
1149 MO.setIsKill(false);
1150 toggleBundleKillFlag(MI, MO.getReg(), false);
1154 // If any subreg of MO is live, then create an imp-def for that
1155 // subreg and keep MO marked as killed.
1156 MO.setIsKill(false);
1157 toggleBundleKillFlag(MI, MO.getReg(), false);
1158 bool AllDead = true;
1159 const unsigned SuperReg = MO.getReg();
1160 MachineInstrBuilder MIB(MF, MI);
1161 for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) {
1162 if (LiveRegs.test(*SubRegs)) {
1163 MIB.addReg(*SubRegs, RegState::ImplicitDefine);
1170 toggleBundleKillFlag(MI, MO.getReg(), true);
1175 // FIXME: Reuse the LivePhysRegs utility for this.
1176 void ScheduleDAGInstrs::fixupKills(MachineBasicBlock *MBB) {
1177 DEBUG(dbgs() << "Fixup kills for BB#" << MBB->getNumber() << '\n');
1179 LiveRegs.resize(TRI->getNumRegs());
1180 BitVector killedRegs(TRI->getNumRegs());
1182 startBlockForKills(MBB);
1184 // Examine block from end to start...
1185 unsigned Count = MBB->size();
1186 for (MachineBasicBlock::iterator I = MBB->end(), E = MBB->begin();
1188 MachineInstr *MI = --I;
1189 if (MI->isDebugValue())
1192 // Update liveness. Registers that are defed but not used in this
1193 // instruction are now dead. Mark register and all subregs as they
1194 // are completely defined.
1195 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1196 MachineOperand &MO = MI->getOperand(i);
1198 LiveRegs.clearBitsNotInMask(MO.getRegMask());
1199 if (!MO.isReg()) continue;
1200 unsigned Reg = MO.getReg();
1201 if (Reg == 0) continue;
1202 if (!MO.isDef()) continue;
1203 // Ignore two-addr defs.
1204 if (MI->isRegTiedToUseOperand(i)) continue;
1206 // Repeat for reg and all subregs.
1207 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1208 SubRegs.isValid(); ++SubRegs)
1209 LiveRegs.reset(*SubRegs);
1212 // Examine all used registers and set/clear kill flag. When a
1213 // register is used multiple times we only set the kill flag on
1214 // the first use. Don't set kill flags on undef operands.
1216 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1217 MachineOperand &MO = MI->getOperand(i);
1218 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
1219 unsigned Reg = MO.getReg();
1220 if ((Reg == 0) || MRI.isReserved(Reg)) continue;
1223 if (!killedRegs.test(Reg)) {
1225 // A register is not killed if any subregs are live...
1226 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
1227 if (LiveRegs.test(*SubRegs)) {
1233 // If subreg is not live, then register is killed if it became
1234 // live in this instruction
1236 kill = !LiveRegs.test(Reg);
1239 if (MO.isKill() != kill) {
1240 DEBUG(dbgs() << "Fixing " << MO << " in ");
1241 // Warning: toggleKillFlag may invalidate MO.
1242 toggleKillFlag(MI, MO);
1244 DEBUG(if (MI->getOpcode() == TargetOpcode::BUNDLE) {
1245 MachineBasicBlock::instr_iterator Begin = MI;
1246 MachineBasicBlock::instr_iterator End = getBundleEnd(MI);
1247 while (++Begin != End)
1248 DEBUG(Begin->dump());
1252 killedRegs.set(Reg);
1255 // Mark any used register (that is not using undef) and subregs as
1257 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1258 MachineOperand &MO = MI->getOperand(i);
1259 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
1260 unsigned Reg = MO.getReg();
1261 if ((Reg == 0) || MRI.isReserved(Reg)) continue;
1263 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1264 SubRegs.isValid(); ++SubRegs)
1265 LiveRegs.set(*SubRegs);
1270 void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
1271 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1272 SU->getInstr()->dump();
1276 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
1278 raw_string_ostream oss(s);
1281 else if (SU == &ExitSU)
1284 SU->getInstr()->print(oss, /*SkipOpers=*/true);
1288 /// Return the basic block label. It is not necessarilly unique because a block
1289 /// contains multiple scheduling regions. But it is fine for visualization.
1290 std::string ScheduleDAGInstrs::getDAGName() const {
1291 return "dag." + BB->getFullName();
1294 //===----------------------------------------------------------------------===//
1295 // SchedDFSResult Implementation
1296 //===----------------------------------------------------------------------===//
1299 /// \brief Internal state used to compute SchedDFSResult.
1300 class SchedDFSImpl {
1303 /// Join DAG nodes into equivalence classes by their subtree.
1304 IntEqClasses SubtreeClasses;
1305 /// List PredSU, SuccSU pairs that represent data edges between subtrees.
1306 std::vector<std::pair<const SUnit*, const SUnit*> > ConnectionPairs;
1310 unsigned ParentNodeID; // Parent node (member of the parent subtree).
1311 unsigned SubInstrCount; // Instr count in this tree only, not children.
1313 RootData(unsigned id): NodeID(id),
1314 ParentNodeID(SchedDFSResult::InvalidSubtreeID),
1317 unsigned getSparseSetIndex() const { return NodeID; }
1320 SparseSet<RootData> RootSet;
1323 SchedDFSImpl(SchedDFSResult &r): R(r), SubtreeClasses(R.DFSNodeData.size()) {
1324 RootSet.setUniverse(R.DFSNodeData.size());
1327 /// Return true if this node been visited by the DFS traversal.
1329 /// During visitPostorderNode the Node's SubtreeID is assigned to the Node
1330 /// ID. Later, SubtreeID is updated but remains valid.
1331 bool isVisited(const SUnit *SU) const {
1332 return R.DFSNodeData[SU->NodeNum].SubtreeID
1333 != SchedDFSResult::InvalidSubtreeID;
1336 /// Initialize this node's instruction count. We don't need to flag the node
1337 /// visited until visitPostorder because the DAG cannot have cycles.
1338 void visitPreorder(const SUnit *SU) {
1339 R.DFSNodeData[SU->NodeNum].InstrCount =
1340 SU->getInstr()->isTransient() ? 0 : 1;
1343 /// Called once for each node after all predecessors are visited. Revisit this
1344 /// node's predecessors and potentially join them now that we know the ILP of
1345 /// the other predecessors.
1346 void visitPostorderNode(const SUnit *SU) {
1347 // Mark this node as the root of a subtree. It may be joined with its
1348 // successors later.
1349 R.DFSNodeData[SU->NodeNum].SubtreeID = SU->NodeNum;
1350 RootData RData(SU->NodeNum);
1351 RData.SubInstrCount = SU->getInstr()->isTransient() ? 0 : 1;
1353 // If any predecessors are still in their own subtree, they either cannot be
1354 // joined or are large enough to remain separate. If this parent node's
1355 // total instruction count is not greater than a child subtree by at least
1356 // the subtree limit, then try to join it now since splitting subtrees is
1357 // only useful if multiple high-pressure paths are possible.
1358 unsigned InstrCount = R.DFSNodeData[SU->NodeNum].InstrCount;
1359 for (SUnit::const_pred_iterator
1360 PI = SU->Preds.begin(), PE = SU->Preds.end(); PI != PE; ++PI) {
1361 if (PI->getKind() != SDep::Data)
1363 unsigned PredNum = PI->getSUnit()->NodeNum;
1364 if ((InstrCount - R.DFSNodeData[PredNum].InstrCount) < R.SubtreeLimit)
1365 joinPredSubtree(*PI, SU, /*CheckLimit=*/false);
1367 // Either link or merge the TreeData entry from the child to the parent.
1368 if (R.DFSNodeData[PredNum].SubtreeID == PredNum) {
1369 // If the predecessor's parent is invalid, this is a tree edge and the
1370 // current node is the parent.
1371 if (RootSet[PredNum].ParentNodeID == SchedDFSResult::InvalidSubtreeID)
1372 RootSet[PredNum].ParentNodeID = SU->NodeNum;
1374 else if (RootSet.count(PredNum)) {
1375 // The predecessor is not a root, but is still in the root set. This
1376 // must be the new parent that it was just joined to. Note that
1377 // RootSet[PredNum].ParentNodeID may either be invalid or may still be
1378 // set to the original parent.
1379 RData.SubInstrCount += RootSet[PredNum].SubInstrCount;
1380 RootSet.erase(PredNum);
1383 RootSet[SU->NodeNum] = RData;
1386 /// Called once for each tree edge after calling visitPostOrderNode on the
1387 /// predecessor. Increment the parent node's instruction count and
1388 /// preemptively join this subtree to its parent's if it is small enough.
1389 void visitPostorderEdge(const SDep &PredDep, const SUnit *Succ) {
1390 R.DFSNodeData[Succ->NodeNum].InstrCount
1391 += R.DFSNodeData[PredDep.getSUnit()->NodeNum].InstrCount;
1392 joinPredSubtree(PredDep, Succ);
1395 /// Add a connection for cross edges.
1396 void visitCrossEdge(const SDep &PredDep, const SUnit *Succ) {
1397 ConnectionPairs.push_back(std::make_pair(PredDep.getSUnit(), Succ));
1400 /// Set each node's subtree ID to the representative ID and record connections
1403 SubtreeClasses.compress();
1404 R.DFSTreeData.resize(SubtreeClasses.getNumClasses());
1405 assert(SubtreeClasses.getNumClasses() == RootSet.size()
1406 && "number of roots should match trees");
1407 for (SparseSet<RootData>::const_iterator
1408 RI = RootSet.begin(), RE = RootSet.end(); RI != RE; ++RI) {
1409 unsigned TreeID = SubtreeClasses[RI->NodeID];
1410 if (RI->ParentNodeID != SchedDFSResult::InvalidSubtreeID)
1411 R.DFSTreeData[TreeID].ParentTreeID = SubtreeClasses[RI->ParentNodeID];
1412 R.DFSTreeData[TreeID].SubInstrCount = RI->SubInstrCount;
1413 // Note that SubInstrCount may be greater than InstrCount if we joined
1414 // subtrees across a cross edge. InstrCount will be attributed to the
1415 // original parent, while SubInstrCount will be attributed to the joined
1418 R.SubtreeConnections.resize(SubtreeClasses.getNumClasses());
1419 R.SubtreeConnectLevels.resize(SubtreeClasses.getNumClasses());
1420 DEBUG(dbgs() << R.getNumSubtrees() << " subtrees:\n");
1421 for (unsigned Idx = 0, End = R.DFSNodeData.size(); Idx != End; ++Idx) {
1422 R.DFSNodeData[Idx].SubtreeID = SubtreeClasses[Idx];
1423 DEBUG(dbgs() << " SU(" << Idx << ") in tree "
1424 << R.DFSNodeData[Idx].SubtreeID << '\n');
1426 for (std::vector<std::pair<const SUnit*, const SUnit*> >::const_iterator
1427 I = ConnectionPairs.begin(), E = ConnectionPairs.end();
1429 unsigned PredTree = SubtreeClasses[I->first->NodeNum];
1430 unsigned SuccTree = SubtreeClasses[I->second->NodeNum];
1431 if (PredTree == SuccTree)
1433 unsigned Depth = I->first->getDepth();
1434 addConnection(PredTree, SuccTree, Depth);
1435 addConnection(SuccTree, PredTree, Depth);
1440 /// Join the predecessor subtree with the successor that is its DFS
1441 /// parent. Apply some heuristics before joining.
1442 bool joinPredSubtree(const SDep &PredDep, const SUnit *Succ,
1443 bool CheckLimit = true) {
1444 assert(PredDep.getKind() == SDep::Data && "Subtrees are for data edges");
1446 // Check if the predecessor is already joined.
1447 const SUnit *PredSU = PredDep.getSUnit();
1448 unsigned PredNum = PredSU->NodeNum;
1449 if (R.DFSNodeData[PredNum].SubtreeID != PredNum)
1452 // Four is the magic number of successors before a node is considered a
1454 unsigned NumDataSucs = 0;
1455 for (SUnit::const_succ_iterator SI = PredSU->Succs.begin(),
1456 SE = PredSU->Succs.end(); SI != SE; ++SI) {
1457 if (SI->getKind() == SDep::Data) {
1458 if (++NumDataSucs >= 4)
1462 if (CheckLimit && R.DFSNodeData[PredNum].InstrCount > R.SubtreeLimit)
1464 R.DFSNodeData[PredNum].SubtreeID = Succ->NodeNum;
1465 SubtreeClasses.join(Succ->NodeNum, PredNum);
1469 /// Called by finalize() to record a connection between trees.
1470 void addConnection(unsigned FromTree, unsigned ToTree, unsigned Depth) {
1475 SmallVectorImpl<SchedDFSResult::Connection> &Connections =
1476 R.SubtreeConnections[FromTree];
1477 for (SmallVectorImpl<SchedDFSResult::Connection>::iterator
1478 I = Connections.begin(), E = Connections.end(); I != E; ++I) {
1479 if (I->TreeID == ToTree) {
1480 I->Level = std::max(I->Level, Depth);
1484 Connections.push_back(SchedDFSResult::Connection(ToTree, Depth));
1485 FromTree = R.DFSTreeData[FromTree].ParentTreeID;
1486 } while (FromTree != SchedDFSResult::InvalidSubtreeID);
1492 /// \brief Manage the stack used by a reverse depth-first search over the DAG.
1493 class SchedDAGReverseDFS {
1494 std::vector<std::pair<const SUnit*, SUnit::const_pred_iterator> > DFSStack;
1496 bool isComplete() const { return DFSStack.empty(); }
1498 void follow(const SUnit *SU) {
1499 DFSStack.push_back(std::make_pair(SU, SU->Preds.begin()));
1501 void advance() { ++DFSStack.back().second; }
1503 const SDep *backtrack() {
1504 DFSStack.pop_back();
1505 return DFSStack.empty() ? nullptr : std::prev(DFSStack.back().second);
1508 const SUnit *getCurr() const { return DFSStack.back().first; }
1510 SUnit::const_pred_iterator getPred() const { return DFSStack.back().second; }
1512 SUnit::const_pred_iterator getPredEnd() const {
1513 return getCurr()->Preds.end();
1518 static bool hasDataSucc(const SUnit *SU) {
1519 for (SUnit::const_succ_iterator
1520 SI = SU->Succs.begin(), SE = SU->Succs.end(); SI != SE; ++SI) {
1521 if (SI->getKind() == SDep::Data && !SI->getSUnit()->isBoundaryNode())
1527 /// Compute an ILP metric for all nodes in the subDAG reachable via depth-first
1528 /// search from this root.
1529 void SchedDFSResult::compute(ArrayRef<SUnit> SUnits) {
1531 llvm_unreachable("Top-down ILP metric is unimplemnted");
1533 SchedDFSImpl Impl(*this);
1534 for (ArrayRef<SUnit>::const_iterator
1535 SI = SUnits.begin(), SE = SUnits.end(); SI != SE; ++SI) {
1536 const SUnit *SU = &*SI;
1537 if (Impl.isVisited(SU) || hasDataSucc(SU))
1540 SchedDAGReverseDFS DFS;
1541 Impl.visitPreorder(SU);
1544 // Traverse the leftmost path as far as possible.
1545 while (DFS.getPred() != DFS.getPredEnd()) {
1546 const SDep &PredDep = *DFS.getPred();
1548 // Ignore non-data edges.
1549 if (PredDep.getKind() != SDep::Data
1550 || PredDep.getSUnit()->isBoundaryNode()) {
1553 // An already visited edge is a cross edge, assuming an acyclic DAG.
1554 if (Impl.isVisited(PredDep.getSUnit())) {
1555 Impl.visitCrossEdge(PredDep, DFS.getCurr());
1558 Impl.visitPreorder(PredDep.getSUnit());
1559 DFS.follow(PredDep.getSUnit());
1561 // Visit the top of the stack in postorder and backtrack.
1562 const SUnit *Child = DFS.getCurr();
1563 const SDep *PredDep = DFS.backtrack();
1564 Impl.visitPostorderNode(Child);
1566 Impl.visitPostorderEdge(*PredDep, DFS.getCurr());
1567 if (DFS.isComplete())
1574 /// The root of the given SubtreeID was just scheduled. For all subtrees
1575 /// connected to this tree, record the depth of the connection so that the
1576 /// nearest connected subtrees can be prioritized.
1577 void SchedDFSResult::scheduleTree(unsigned SubtreeID) {
1578 for (SmallVectorImpl<Connection>::const_iterator
1579 I = SubtreeConnections[SubtreeID].begin(),
1580 E = SubtreeConnections[SubtreeID].end(); I != E; ++I) {
1581 SubtreeConnectLevels[I->TreeID] =
1582 std::max(SubtreeConnectLevels[I->TreeID], I->Level);
1583 DEBUG(dbgs() << " Tree: " << I->TreeID
1584 << " @" << SubtreeConnectLevels[I->TreeID] << '\n');
1589 void ILPValue::print(raw_ostream &OS) const {
1590 OS << InstrCount << " / " << Length << " = ";
1594 OS << format("%g", ((double)InstrCount / Length));
1598 void ILPValue::dump() const {
1599 dbgs() << *this << '\n';
1605 raw_ostream &operator<<(raw_ostream &OS, const ILPValue &Val) {