1 //===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the ScheduleDAGInstrs class, which implements re-scheduling
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "sched-instrs"
16 #include "ScheduleDAGInstrs.h"
17 #include "llvm/Operator.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Analysis/ValueTracking.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineMemOperand.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/MC/MCInstrItineraries.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Target/TargetSubtargetInfo.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/ADT/SmallSet.h"
35 ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
36 const MachineLoopInfo &mli,
37 const MachineDominatorTree &mdt,
40 : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()),
41 InstrItins(mf.getTarget().getInstrItineraryData()), IsPostRA(IsPostRAFlag),
42 LIS(lis), UnitLatencies(false),
43 Defs(TRI->getNumRegs()), Uses(TRI->getNumRegs()),
44 LoopRegs(MLI, MDT), FirstDbgValue(0) {
45 assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
47 assert(!(IsPostRA && MRI.getNumVirtRegs()) &&
48 "Virtual registers must be removed prior to PostRA scheduling");
51 /// Run - perform scheduling.
53 void ScheduleDAGInstrs::Run(MachineBasicBlock *bb,
54 MachineBasicBlock::iterator begin,
55 MachineBasicBlock::iterator end,
59 InsertPosIndex = endcount;
61 // Check to see if the scheduler cares about latencies.
62 UnitLatencies = ForceUnitLatencies();
64 ScheduleDAG::Run(bb, end);
67 /// getUnderlyingObjectFromInt - This is the function that does the work of
68 /// looking through basic ptrtoint+arithmetic+inttoptr sequences.
69 static const Value *getUnderlyingObjectFromInt(const Value *V) {
71 if (const Operator *U = dyn_cast<Operator>(V)) {
72 // If we find a ptrtoint, we can transfer control back to the
73 // regular getUnderlyingObjectFromInt.
74 if (U->getOpcode() == Instruction::PtrToInt)
75 return U->getOperand(0);
76 // If we find an add of a constant or a multiplied value, it's
77 // likely that the other operand will lead us to the base
78 // object. We don't have to worry about the case where the
79 // object address is somehow being computed by the multiply,
80 // because our callers only care when the result is an
81 // identifibale object.
82 if (U->getOpcode() != Instruction::Add ||
83 (!isa<ConstantInt>(U->getOperand(1)) &&
84 Operator::getOpcode(U->getOperand(1)) != Instruction::Mul))
90 assert(V->getType()->isIntegerTy() && "Unexpected operand type!");
94 /// getUnderlyingObject - This is a wrapper around GetUnderlyingObject
95 /// and adds support for basic ptrtoint+arithmetic+inttoptr sequences.
96 static const Value *getUnderlyingObject(const Value *V) {
97 // First just call Value::getUnderlyingObject to let it do what it does.
99 V = GetUnderlyingObject(V);
100 // If it found an inttoptr, use special code to continue climing.
101 if (Operator::getOpcode(V) != Instruction::IntToPtr)
103 const Value *O = getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0));
104 // If that succeeded in finding a pointer, continue the search.
105 if (!O->getType()->isPointerTy())
112 /// getUnderlyingObjectForInstr - If this machine instr has memory reference
113 /// information and it can be tracked to a normal reference to a known
114 /// object, return the Value for that object. Otherwise return null.
115 static const Value *getUnderlyingObjectForInstr(const MachineInstr *MI,
116 const MachineFrameInfo *MFI,
119 if (!MI->hasOneMemOperand() ||
120 !(*MI->memoperands_begin())->getValue() ||
121 (*MI->memoperands_begin())->isVolatile())
124 const Value *V = (*MI->memoperands_begin())->getValue();
128 V = getUnderlyingObject(V);
129 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
130 // For now, ignore PseudoSourceValues which may alias LLVM IR values
131 // because the code that uses this function has no way to cope with
133 if (PSV->isAliased(MFI))
136 MayAlias = PSV->mayAlias(MFI);
140 if (isIdentifiedObject(V))
146 void ScheduleDAGInstrs::StartBlock(MachineBasicBlock *BB) {
147 LoopRegs.Deps.clear();
148 if (MachineLoop *ML = MLI.getLoopFor(BB))
149 if (BB == ML->getLoopLatch())
150 LoopRegs.VisitLoop(ML);
153 /// AddSchedBarrierDeps - Add dependencies from instructions in the current
154 /// list of instructions being scheduled to scheduling barrier by adding
155 /// the exit SU to the register defs and use list. This is because we want to
156 /// make sure instructions which define registers that are either used by
157 /// the terminator or are live-out are properly scheduled. This is
158 /// especially important when the definition latency of the return value(s)
159 /// are too high to be hidden by the branch or when the liveout registers
160 /// used by instructions in the fallthrough block.
161 void ScheduleDAGInstrs::AddSchedBarrierDeps() {
162 MachineInstr *ExitMI = InsertPos != BB->end() ? &*InsertPos : 0;
163 ExitSU.setInstr(ExitMI);
164 bool AllDepKnown = ExitMI &&
165 (ExitMI->isCall() || ExitMI->isBarrier());
166 if (ExitMI && AllDepKnown) {
167 // If it's a call or a barrier, add dependencies on the defs and uses of
169 for (unsigned i = 0, e = ExitMI->getNumOperands(); i != e; ++i) {
170 const MachineOperand &MO = ExitMI->getOperand(i);
171 if (!MO.isReg() || MO.isDef()) continue;
172 unsigned Reg = MO.getReg();
173 if (Reg == 0) continue;
175 if (TRI->isPhysicalRegister(Reg))
176 Uses[Reg].push_back(&ExitSU);
178 assert(!IsPostRA && "Virtual register encountered after regalloc.");
181 // For others, e.g. fallthrough, conditional branch, assume the exit
182 // uses all the registers that are livein to the successor blocks.
183 SmallSet<unsigned, 8> Seen;
184 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
185 SE = BB->succ_end(); SI != SE; ++SI)
186 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
187 E = (*SI)->livein_end(); I != E; ++I) {
189 if (Seen.insert(Reg))
190 Uses[Reg].push_back(&ExitSU);
195 /// addPhysRegDeps - Add register dependencies (data, anti, and output) from
196 /// this SUnit to following instructions in the same scheduling region that
197 /// depend the physical register referenced at OperIdx.
198 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
199 const MachineInstr *MI = SU->getInstr();
200 const MachineOperand &MO = MI->getOperand(OperIdx);
201 unsigned Reg = MO.getReg();
203 // Ask the target if address-backscheduling is desirable, and if so how much.
204 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
205 unsigned SpecialAddressLatency = ST.getSpecialAddressLatency();
207 // Optionally add output and anti dependencies. For anti
208 // dependencies we use a latency of 0 because for a multi-issue
209 // target we want to allow the defining instruction to issue
210 // in the same cycle as the using instruction.
211 // TODO: Using a latency of 1 here for output dependencies assumes
212 // there's no cost for reusing registers.
213 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
214 for (const unsigned *Alias = TRI->getOverlaps(Reg); *Alias; ++Alias) {
215 std::vector<SUnit *> &DefList = Defs[*Alias];
216 for (unsigned i = 0, e = DefList.size(); i != e; ++i) {
217 SUnit *DefSU = DefList[i];
218 if (DefSU == &ExitSU)
221 (Kind != SDep::Output || !MO.isDead() ||
222 !DefSU->getInstr()->registerDefIsDead(*Alias))) {
223 if (Kind == SDep::Anti)
224 DefSU->addPred(SDep(SU, Kind, 0, /*Reg=*/*Alias));
226 unsigned AOLat = TII->getOutputLatency(InstrItins, MI, OperIdx,
228 DefSU->addPred(SDep(SU, Kind, AOLat, /*Reg=*/*Alias));
234 // Retrieve the UseList to add data dependencies and update uses.
235 std::vector<SUnit *> &UseList = Uses[Reg];
237 // Update DefList. Defs are pushed in the order they are visited and
239 std::vector<SUnit *> &DefList = Defs[Reg];
241 // Add any data dependencies.
242 unsigned DataLatency = SU->Latency;
243 for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
244 SUnit *UseSU = UseList[i];
247 unsigned LDataLatency = DataLatency;
248 // Optionally add in a special extra latency for nodes that
250 // TODO: Do this for register aliases too.
251 // TODO: Perhaps we should get rid of
252 // SpecialAddressLatency and just move this into
253 // adjustSchedDependency for the targets that care about it.
254 if (SpecialAddressLatency != 0 && !UnitLatencies &&
256 MachineInstr *UseMI = UseSU->getInstr();
257 const MCInstrDesc &UseMCID = UseMI->getDesc();
258 int RegUseIndex = UseMI->findRegisterUseOperandIdx(Reg);
259 assert(RegUseIndex >= 0 && "UseMI doesn's use register!");
260 if (RegUseIndex >= 0 &&
261 (UseMI->mayLoad() || UseMI->mayStore()) &&
262 (unsigned)RegUseIndex < UseMCID.getNumOperands() &&
263 UseMCID.OpInfo[RegUseIndex].isLookupPtrRegClass())
264 LDataLatency += SpecialAddressLatency;
266 // Adjust the dependence latency using operand def/use
267 // information (if any), and then allow the target to
268 // perform its own adjustments.
269 const SDep& dep = SDep(SU, SDep::Data, LDataLatency, Reg);
270 if (!UnitLatencies) {
271 ComputeOperandLatency(SU, UseSU, const_cast<SDep &>(dep));
272 ST.adjustSchedDependency(SU, UseSU, const_cast<SDep &>(dep));
276 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
277 std::vector<SUnit *> &UseList = Uses[*Alias];
278 for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
279 SUnit *UseSU = UseList[i];
282 const SDep& dep = SDep(SU, SDep::Data, DataLatency, *Alias);
283 if (!UnitLatencies) {
284 ComputeOperandLatency(SU, UseSU, const_cast<SDep &>(dep));
285 ST.adjustSchedDependency(SU, UseSU, const_cast<SDep &>(dep));
291 // If a def is going to wrap back around to the top of the loop,
293 if (!UnitLatencies && DefList.empty()) {
294 LoopDependencies::LoopDeps::iterator I = LoopRegs.Deps.find(Reg);
295 if (I != LoopRegs.Deps.end()) {
296 const MachineOperand *UseMO = I->second.first;
297 unsigned Count = I->second.second;
298 const MachineInstr *UseMI = UseMO->getParent();
299 unsigned UseMOIdx = UseMO - &UseMI->getOperand(0);
300 const MCInstrDesc &UseMCID = UseMI->getDesc();
301 // TODO: If we knew the total depth of the region here, we could
302 // handle the case where the whole loop is inside the region but
303 // is large enough that the isScheduleHigh trick isn't needed.
304 if (UseMOIdx < UseMCID.getNumOperands()) {
305 // Currently, we only support scheduling regions consisting of
306 // single basic blocks. Check to see if the instruction is in
307 // the same region by checking to see if it has the same parent.
308 if (UseMI->getParent() != MI->getParent()) {
309 unsigned Latency = SU->Latency;
310 if (UseMCID.OpInfo[UseMOIdx].isLookupPtrRegClass())
311 Latency += SpecialAddressLatency;
312 // This is a wild guess as to the portion of the latency which
313 // will be overlapped by work done outside the current
314 // scheduling region.
315 Latency -= std::min(Latency, Count);
316 // Add the artificial edge.
317 ExitSU.addPred(SDep(SU, SDep::Order, Latency,
318 /*Reg=*/0, /*isNormalMemory=*/false,
319 /*isMustAlias=*/false,
320 /*isArtificial=*/true));
321 } else if (SpecialAddressLatency > 0 &&
322 UseMCID.OpInfo[UseMOIdx].isLookupPtrRegClass()) {
323 // The entire loop body is within the current scheduling region
324 // and the latency of this operation is assumed to be greater
325 // than the latency of the loop.
326 // TODO: Recursively mark data-edge predecessors as
327 // isScheduleHigh too.
328 SU->isScheduleHigh = true;
331 LoopRegs.Deps.erase(I);
339 // Calls will not be reordered because of chain dependencies (see
340 // below). Since call operands are dead, calls may continue to be added
341 // to the DefList making dependence checking quadratic in the size of
342 // the block. Instead, we leave only one call at the back of the
345 while (!DefList.empty() && DefList.back()->isCall)
348 DefList.push_back(SU);
350 UseList.push_back(SU);
354 /// addVRegDefDeps - Add register output and data dependencies from this SUnit
355 /// to instructions that occur later in the same scheduling region if they read
356 /// from or write to the virtual register defined at OperIdx.
358 /// TODO: Hoist loop induction variable increments. This has to be
359 /// reevaluated. Generally, IV scheduling should be done before coalescing.
360 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
361 const MachineInstr *MI = SU->getInstr();
362 unsigned Reg = MI->getOperand(OperIdx).getReg();
364 // SSA defs do not have output/anti dependencies.
365 // The current operand is a def, so we have at least one.
366 if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
369 // Add output dependence to the next nearest def of this vreg.
371 // Unless this definition is dead, the output dependence should be
372 // transitively redundant with antidependencies from this definition's
373 // uses. We're conservative for now until we have a way to guarantee the uses
374 // are not eliminated sometime during scheduling. The output dependence edge
375 // is also useful if output latency exceeds def-use latency.
376 SUnit *&DefSU = VRegDefs[Reg];
377 if (DefSU && DefSU != SU && DefSU != &ExitSU) {
378 unsigned OutLatency = TII->getOutputLatency(InstrItins, MI, OperIdx,
380 DefSU->addPred(SDep(SU, SDep::Output, OutLatency, Reg));
385 /// addVRegUseDeps - Add a register data dependency if the instruction that
386 /// defines the virtual register used at OperIdx is mapped to an SUnit. Add a
387 /// register antidependency from this SUnit to instructions that occur later in
388 /// the same scheduling region if they write the virtual register.
390 /// TODO: Handle ExitSU "uses" properly.
391 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
392 MachineInstr *MI = SU->getInstr();
393 unsigned Reg = MI->getOperand(OperIdx).getReg();
395 // Lookup this operand's reaching definition.
396 assert(LIS && "vreg dependencies requires LiveIntervals");
397 SlotIndex UseIdx = LIS->getSlotIndexes()->getInstructionIndex(MI);
398 LiveInterval *LI = &LIS->getInterval(Reg);
399 VNInfo *VNI = LI->getVNInfoAt(UseIdx);
400 MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def);
402 SUnit *DefSU = getSUnit(Def);
404 // The reaching Def lives within this scheduling region.
405 // Create a data dependence.
407 // TODO: Handle "special" address latencies cleanly.
408 const SDep &dep = SDep(DefSU, SDep::Data, DefSU->Latency, Reg);
409 if (!UnitLatencies) {
410 // Adjust the dependence latency using operand def/use information, then
411 // allow the target to perform its own adjustments.
412 ComputeOperandLatency(DefSU, SU, const_cast<SDep &>(dep));
413 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
414 ST.adjustSchedDependency(DefSU, SU, const_cast<SDep &>(dep));
420 // Add antidependence to the following def of the vreg it uses.
421 DenseMap<unsigned, SUnit*>::const_iterator I = VRegDefs.find(Reg);
422 if (I != VRegDefs.end()) {
423 SUnit *DefSU = I->second;
425 DefSU->addPred(SDep(SU, SDep::Anti, 0, Reg));
429 /// Create an SUnit for each real instruction, numbered in top-down toplological
430 /// order. The instruction order A < B, implies that no edge exists from B to A.
432 /// Map each real instruction to its SUnit.
434 /// After initSUnits, the SUnits vector is cannot be resized and the scheduler
435 /// may hang onto SUnit pointers. We may relax this in the future by using SUnit
436 /// IDs instead of pointers.
437 void ScheduleDAGInstrs::initSUnits() {
438 // We'll be allocating one SUnit for each real instruction in the region,
439 // which is contained within a basic block.
440 SUnits.reserve(BB->size());
442 for (MachineBasicBlock::iterator I = Begin; I != InsertPos; ++I) {
443 MachineInstr *MI = I;
444 if (MI->isDebugValue())
447 SUnit *SU = NewSUnit(MI);
450 SU->isCall = MI->isCall();
451 SU->isCommutable = MI->isCommutable();
453 // Assign the Latency field of SU using target-provided information.
461 void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
462 // Create an SUnit for each real instruction.
465 // We build scheduling units by walking a block's instruction list from bottom
468 // Remember where a generic side-effecting instruction is as we procede.
469 SUnit *BarrierChain = 0, *AliasChain = 0;
471 // Memory references to specific known memory locations are tracked
472 // so that they can be given more precise dependencies. We track
473 // separately the known memory locations that may alias and those
474 // that are known not to alias
475 std::map<const Value *, SUnit *> AliasMemDefs, NonAliasMemDefs;
476 std::map<const Value *, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses;
478 // Remove any stale debug info; sometimes BuildSchedGraph is called again
479 // without emitting the info from the previous call.
481 FirstDbgValue = NULL;
483 // Model data dependencies between instructions being scheduled and the
485 AddSchedBarrierDeps();
487 for (int i = 0, e = TRI->getNumRegs(); i != e; ++i) {
488 assert(Defs[i].empty() && "Only BuildGraph should push/pop Defs");
491 assert(VRegDefs.size() == 0 && "Only BuildSchedGraph may access VRegDefs");
493 // Walk the list of instructions, from bottom moving up.
494 MachineInstr *PrevMI = NULL;
495 for (MachineBasicBlock::iterator MII = InsertPos, MIE = Begin;
497 MachineInstr *MI = prior(MII);
499 DbgValues.push_back(std::make_pair(PrevMI, MI));
503 if (MI->isDebugValue()) {
508 assert(!MI->isTerminator() && !MI->isLabel() &&
509 "Cannot schedule terminators or labels!");
511 SUnit *SU = MISUnitMap[MI];
512 assert(SU && "No SUnit mapped to this MI");
514 // Add register-based dependencies (data, anti, and output).
515 for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
516 const MachineOperand &MO = MI->getOperand(j);
517 if (!MO.isReg()) continue;
518 unsigned Reg = MO.getReg();
519 if (Reg == 0) continue;
521 if (TRI->isPhysicalRegister(Reg))
522 addPhysRegDeps(SU, j);
524 assert(!IsPostRA && "Virtual register encountered!");
526 addVRegDefDeps(SU, j);
528 addVRegUseDeps(SU, j);
532 // Add chain dependencies.
533 // Chain dependencies used to enforce memory order should have
534 // latency of 0 (except for true dependency of Store followed by
535 // aliased Load... we estimate that with a single cycle of latency
536 // assuming the hardware will bypass)
537 // Note that isStoreToStackSlot and isLoadFromStackSLot are not usable
538 // after stack slots are lowered to actual addresses.
539 // TODO: Use an AliasAnalysis and do real alias-analysis queries, and
540 // produce more precise dependence information.
541 #define STORE_LOAD_LATENCY 1
542 unsigned TrueMemOrderLatency = 0;
543 if (MI->isCall() || MI->hasUnmodeledSideEffects() ||
544 (MI->hasVolatileMemoryRef() &&
545 (!MI->mayLoad() || !MI->isInvariantLoad(AA)))) {
546 // Be conservative with these and add dependencies on all memory
547 // references, even those that are known to not alias.
548 for (std::map<const Value *, SUnit *>::iterator I =
549 NonAliasMemDefs.begin(), E = NonAliasMemDefs.end(); I != E; ++I) {
550 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
552 for (std::map<const Value *, std::vector<SUnit *> >::iterator I =
553 NonAliasMemUses.begin(), E = NonAliasMemUses.end(); I != E; ++I) {
554 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
555 I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
557 NonAliasMemDefs.clear();
558 NonAliasMemUses.clear();
559 // Add SU to the barrier chain.
561 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
566 // Chain all possibly aliasing memory references though SU.
568 AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
570 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
571 PendingLoads[k]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
572 for (std::map<const Value *, SUnit *>::iterator I = AliasMemDefs.begin(),
573 E = AliasMemDefs.end(); I != E; ++I) {
574 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
576 for (std::map<const Value *, std::vector<SUnit *> >::iterator I =
577 AliasMemUses.begin(), E = AliasMemUses.end(); I != E; ++I) {
578 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
579 I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
581 PendingLoads.clear();
582 AliasMemDefs.clear();
583 AliasMemUses.clear();
584 } else if (MI->mayStore()) {
585 bool MayAlias = true;
586 TrueMemOrderLatency = STORE_LOAD_LATENCY;
587 if (const Value *V = getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
588 // A store to a specific PseudoSourceValue. Add precise dependencies.
589 // Record the def in MemDefs, first adding a dep if there is
591 std::map<const Value *, SUnit *>::iterator I =
592 ((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
593 std::map<const Value *, SUnit *>::iterator IE =
594 ((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
596 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0, /*Reg=*/0,
597 /*isNormalMemory=*/true));
601 AliasMemDefs[V] = SU;
603 NonAliasMemDefs[V] = SU;
605 // Handle the uses in MemUses, if there are any.
606 std::map<const Value *, std::vector<SUnit *> >::iterator J =
607 ((MayAlias) ? AliasMemUses.find(V) : NonAliasMemUses.find(V));
608 std::map<const Value *, std::vector<SUnit *> >::iterator JE =
609 ((MayAlias) ? AliasMemUses.end() : NonAliasMemUses.end());
611 for (unsigned i = 0, e = J->second.size(); i != e; ++i)
612 J->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency,
613 /*Reg=*/0, /*isNormalMemory=*/true));
617 // Add dependencies from all the PendingLoads, i.e. loads
618 // with no underlying object.
619 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
620 PendingLoads[k]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
621 // Add dependence on alias chain, if needed.
623 AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
625 // Add dependence on barrier chain, if needed.
627 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
629 // Treat all other stores conservatively.
630 goto new_alias_chain;
633 if (!ExitSU.isPred(SU))
634 // Push store's up a bit to avoid them getting in between cmp
636 ExitSU.addPred(SDep(SU, SDep::Order, 0,
637 /*Reg=*/0, /*isNormalMemory=*/false,
638 /*isMustAlias=*/false,
639 /*isArtificial=*/true));
640 } else if (MI->mayLoad()) {
641 bool MayAlias = true;
642 TrueMemOrderLatency = 0;
643 if (MI->isInvariantLoad(AA)) {
644 // Invariant load, no chain dependencies needed!
647 getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
648 // A load from a specific PseudoSourceValue. Add precise dependencies.
649 std::map<const Value *, SUnit *>::iterator I =
650 ((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
651 std::map<const Value *, SUnit *>::iterator IE =
652 ((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
654 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0, /*Reg=*/0,
655 /*isNormalMemory=*/true));
657 AliasMemUses[V].push_back(SU);
659 NonAliasMemUses[V].push_back(SU);
661 // A load with no underlying object. Depend on all
662 // potentially aliasing stores.
663 for (std::map<const Value *, SUnit *>::iterator I =
664 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I)
665 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
667 PendingLoads.push_back(SU);
671 // Add dependencies on alias and barrier chains, if needed.
672 if (MayAlias && AliasChain)
673 AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
675 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
680 FirstDbgValue = PrevMI;
682 for (int i = 0, e = TRI->getNumRegs(); i != e; ++i) {
687 PendingLoads.clear();
691 void ScheduleDAGInstrs::FinishBlock() {
695 void ScheduleDAGInstrs::ComputeLatency(SUnit *SU) {
696 // Compute the latency for the node.
697 if (!InstrItins || InstrItins->isEmpty()) {
700 // Simplistic target-independent heuristic: assume that loads take
702 if (SU->getInstr()->mayLoad())
705 SU->Latency = TII->getInstrLatency(InstrItins, SU->getInstr());
709 void ScheduleDAGInstrs::ComputeOperandLatency(SUnit *Def, SUnit *Use,
711 if (!InstrItins || InstrItins->isEmpty())
714 // For a data dependency with a known register...
715 if ((dep.getKind() != SDep::Data) || (dep.getReg() == 0))
718 const unsigned Reg = dep.getReg();
720 // ... find the definition of the register in the defining
722 MachineInstr *DefMI = Def->getInstr();
723 int DefIdx = DefMI->findRegisterDefOperandIdx(Reg);
725 const MachineOperand &MO = DefMI->getOperand(DefIdx);
726 if (MO.isReg() && MO.isImplicit() &&
727 DefIdx >= (int)DefMI->getDesc().getNumOperands()) {
728 // This is an implicit def, getOperandLatency() won't return the correct
730 // %D6<def>, %D7<def> = VLD1q16 %R2<kill>, 0, ..., %Q3<imp-def>
731 // %Q1<def> = VMULv8i16 %Q1<kill>, %Q3<kill>, ...
732 // What we want is to compute latency between def of %D6/%D7 and use of
734 DefIdx = DefMI->findRegisterDefOperandIdx(Reg, false, true, TRI);
736 MachineInstr *UseMI = Use->getInstr();
737 // For all uses of the register, calculate the maxmimum latency
740 for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) {
741 const MachineOperand &MO = UseMI->getOperand(i);
742 if (!MO.isReg() || !MO.isUse())
744 unsigned MOReg = MO.getReg();
748 int UseCycle = TII->getOperandLatency(InstrItins, DefMI, DefIdx,
750 Latency = std::max(Latency, UseCycle);
753 // UseMI is null, then it must be a scheduling barrier.
754 if (!InstrItins || InstrItins->isEmpty())
756 unsigned DefClass = DefMI->getDesc().getSchedClass();
757 Latency = InstrItins->getOperandCycle(DefClass, DefIdx);
760 // If we found a latency, then replace the existing dependence latency.
762 dep.setLatency(Latency);
766 void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
767 SU->getInstr()->dump();
770 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
772 raw_string_ostream oss(s);
775 else if (SU == &ExitSU)
778 SU->getInstr()->print(oss);
782 // EmitSchedule - Emit the machine code in scheduled order.
783 MachineBasicBlock *ScheduleDAGInstrs::EmitSchedule() {
786 // If first instruction was a DBG_VALUE then put it back.
788 BB->splice(InsertPos, BB, FirstDbgValue);
790 // Then re-insert them according to the given schedule.
791 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
792 if (SUnit *SU = Sequence[i])
793 BB->splice(InsertPos, BB, SU->getInstr());
795 // Null SUnit* is a noop.
798 // Update the Begin iterator, as the first instruction in the block
799 // may have been scheduled later.
801 Begin = prior(InsertPos);
804 // Reinsert any remaining debug_values.
805 for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
806 DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
807 std::pair<MachineInstr *, MachineInstr *> P = *prior(DI);
808 MachineInstr *DbgValue = P.first;
809 MachineBasicBlock::iterator OrigPrivMI = P.second;
810 BB->splice(++OrigPrivMI, BB, DbgValue);
813 FirstDbgValue = NULL;