1 //==- ScheduleDAGInstrs.h - MachineInstr Scheduling --------------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAGInstrs class, which implements
11 // scheduling for a MachineInstr-based dependency graph.
13 //===----------------------------------------------------------------------===//
15 #ifndef SCHEDULEDAGINSTRS_H
16 #define SCHEDULEDAGINSTRS_H
18 #include "llvm/CodeGen/MachineDominators.h"
19 #include "llvm/CodeGen/MachineLoopInfo.h"
20 #include "llvm/CodeGen/ScheduleDAG.h"
21 #include "llvm/Support/Compiler.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/SmallSet.h"
28 class MachineLoopInfo;
29 class MachineDominatorTree;
31 /// LoopDependencies - This class analyzes loop-oriented register
32 /// dependencies, which are used to guide scheduling decisions.
33 /// For example, loop induction variable increments should be
34 /// scheduled as soon as possible after the variable's last use.
36 class VISIBILITY_HIDDEN LoopDependencies {
37 const MachineLoopInfo &MLI;
38 const MachineDominatorTree &MDT;
41 typedef std::map<unsigned, std::pair<const MachineOperand *, unsigned> >
45 LoopDependencies(const MachineLoopInfo &mli,
46 const MachineDominatorTree &mdt) :
49 /// VisitLoop - Clear out any previous state and analyze the given loop.
51 void VisitLoop(const MachineLoop *Loop) {
53 MachineBasicBlock *Header = Loop->getHeader();
54 SmallSet<unsigned, 8> LoopLiveIns;
55 for (MachineBasicBlock::livein_iterator LI = Header->livein_begin(),
56 LE = Header->livein_end(); LI != LE; ++LI)
57 LoopLiveIns.insert(*LI);
59 const MachineDomTreeNode *Node = MDT.getNode(Header);
60 const MachineBasicBlock *MBB = Node->getBlock();
61 assert(Loop->contains(MBB) &&
62 "Loop does not contain header!");
63 VisitRegion(Node, MBB, Loop, LoopLiveIns);
67 void VisitRegion(const MachineDomTreeNode *Node,
68 const MachineBasicBlock *MBB,
69 const MachineLoop *Loop,
70 const SmallSet<unsigned, 8> &LoopLiveIns) {
72 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
73 I != E; ++I, ++Count) {
74 const MachineInstr *MI = I;
75 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
76 const MachineOperand &MO = MI->getOperand(i);
77 if (!MO.isReg() || !MO.isUse())
79 unsigned MOReg = MO.getReg();
80 if (LoopLiveIns.count(MOReg))
81 Deps.insert(std::make_pair(MOReg, std::make_pair(&MO, Count)));
85 const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
86 for (std::vector<MachineDomTreeNode*>::const_iterator I =
87 Children.begin(), E = Children.end(); I != E; ++I) {
88 const MachineDomTreeNode *ChildNode = *I;
89 MachineBasicBlock *ChildBlock = ChildNode->getBlock();
90 if (Loop->contains(ChildBlock))
91 VisitRegion(ChildNode, ChildBlock, Loop, LoopLiveIns);
96 /// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of
98 class VISIBILITY_HIDDEN ScheduleDAGInstrs : public ScheduleDAG {
99 const MachineLoopInfo &MLI;
100 const MachineDominatorTree &MDT;
102 /// Defs, Uses - Remember where defs and uses of each physical register
103 /// are as we iterate upward through the instructions. This is allocated
104 /// here instead of inside BuildSchedGraph to avoid the need for it to be
105 /// initialized and destructed for each block.
106 std::vector<SUnit *> Defs[TargetRegisterInfo::FirstVirtualRegister];
107 std::vector<SUnit *> Uses[TargetRegisterInfo::FirstVirtualRegister];
109 /// PendingLoads - Remember where unknown loads are after the most recent
110 /// unknown store, as we iterate. As with Defs and Uses, this is here
111 /// to minimize construction/destruction.
112 std::vector<SUnit *> PendingLoads;
114 /// LoopRegs - Track which registers are used for loop-carried dependencies.
116 LoopDependencies LoopRegs;
118 /// LoopLiveInRegs - Track which regs are live into a loop, to help guide
119 /// back-edge-aware scheduling.
121 SmallSet<unsigned, 8> LoopLiveInRegs;
124 MachineBasicBlock *BB; // Current basic block
125 MachineBasicBlock::iterator Begin; // The beginning of the range to
126 // be scheduled. The range extends
128 unsigned InsertPosIndex; // The index in BB of InsertPos.
130 explicit ScheduleDAGInstrs(MachineFunction &mf,
131 const MachineLoopInfo &mli,
132 const MachineDominatorTree &mdt);
134 virtual ~ScheduleDAGInstrs() {}
136 /// NewSUnit - Creates a new SUnit and return a ptr to it.
138 SUnit *NewSUnit(MachineInstr *MI) {
140 const SUnit *Addr = SUnits.empty() ? 0 : &SUnits[0];
142 SUnits.push_back(SUnit(MI, (unsigned)SUnits.size()));
143 assert((Addr == 0 || Addr == &SUnits[0]) &&
144 "SUnits std::vector reallocated on the fly!");
145 SUnits.back().OrigNode = &SUnits.back();
146 return &SUnits.back();
149 /// Run - perform scheduling.
151 void Run(MachineBasicBlock *bb,
152 MachineBasicBlock::iterator begin,
153 MachineBasicBlock::iterator end,
156 /// BuildSchedGraph - Build SUnits from the MachineBasicBlock that we are
158 virtual void BuildSchedGraph(AliasAnalysis *AA);
160 /// ComputeLatency - Compute node latency.
162 virtual void ComputeLatency(SUnit *SU);
164 /// ComputeOperandLatency - Override dependence edge latency using
165 /// operand use/def information
167 virtual void ComputeOperandLatency(SUnit *Def, SUnit *Use,
170 virtual MachineBasicBlock*
171 EmitSchedule(DenseMap<MachineBasicBlock*, MachineBasicBlock*>*);
173 /// StartBlock - Prepare to perform scheduling in the given block.
175 virtual void StartBlock(MachineBasicBlock *BB);
177 /// Schedule - Order nodes according to selected style, filling
178 /// in the Sequence member.
180 virtual void Schedule() = 0;
182 /// FinishBlock - Clean up after scheduling in the given block.
184 virtual void FinishBlock();
186 virtual void dumpNode(const SUnit *SU) const;
188 virtual std::string getGraphNodeLabel(const SUnit *SU) const;