1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "dagcombine"
16 #include "llvm/CodeGen/SelectionDAG.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Target/TargetData.h"
21 #include "llvm/Target/TargetFrameInfo.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/SmallPtrSet.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/MathExtras.h"
34 STATISTIC(NodesCombined , "Number of dag nodes combined");
35 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
36 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
41 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
42 cl::desc("Pop up a window to show dags before the first "
45 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
46 cl::desc("Pop up a window to show dags before the second "
49 static const bool ViewDAGCombine1 = false;
50 static const bool ViewDAGCombine2 = false;
54 CombinerAA("combiner-alias-analysis", cl::Hidden,
55 cl::desc("Turn on alias analysis during testing"));
58 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
59 cl::desc("Include global information in alias analysis"));
61 //------------------------------ DAGCombiner ---------------------------------//
63 class VISIBILITY_HIDDEN DAGCombiner {
68 // Worklist of all of the nodes that need to be simplified.
69 std::vector<SDNode*> WorkList;
71 // AA - Used for DAG load/store alias analysis.
74 /// AddUsersToWorkList - When an instruction is simplified, add all users of
75 /// the instruction to the work lists because they might get more simplified
78 void AddUsersToWorkList(SDNode *N) {
79 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
84 /// visit - call the node-specific routine that knows how to fold each
85 /// particular type of node.
86 SDOperand visit(SDNode *N);
89 /// AddToWorkList - Add to the work list making sure it's instance is at the
90 /// the back (next to be processed.)
91 void AddToWorkList(SDNode *N) {
92 removeFromWorkList(N);
93 WorkList.push_back(N);
96 /// removeFromWorkList - remove all instances of N from the worklist.
98 void removeFromWorkList(SDNode *N) {
99 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
103 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
106 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
107 return CombineTo(N, &Res, 1, AddTo);
110 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
112 SDOperand To[] = { Res0, Res1 };
113 return CombineTo(N, To, 2, AddTo);
118 /// SimplifyDemandedBits - Check the specified integer node value to see if
119 /// it can be simplified or if things it uses can be simplified by bit
120 /// propagation. If so, return true.
121 bool SimplifyDemandedBits(SDOperand Op, uint64_t Demanded = ~0ULL);
123 bool CombineToPreIndexedLoadStore(SDNode *N);
124 bool CombineToPostIndexedLoadStore(SDNode *N);
127 /// combine - call the node-specific routine that knows how to fold each
128 /// particular type of node. If that doesn't do anything, try the
129 /// target-specific DAG combines.
130 SDOperand combine(SDNode *N);
132 // Visitation implementation - Implement dag node combining for different
133 // node types. The semantics are as follows:
135 // SDOperand.Val == 0 - No change was made
136 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
137 // otherwise - N should be replaced by the returned Operand.
139 SDOperand visitTokenFactor(SDNode *N);
140 SDOperand visitMERGE_VALUES(SDNode *N);
141 SDOperand visitADD(SDNode *N);
142 SDOperand visitSUB(SDNode *N);
143 SDOperand visitADDC(SDNode *N);
144 SDOperand visitADDE(SDNode *N);
145 SDOperand visitMUL(SDNode *N);
146 SDOperand visitSDIV(SDNode *N);
147 SDOperand visitUDIV(SDNode *N);
148 SDOperand visitSREM(SDNode *N);
149 SDOperand visitUREM(SDNode *N);
150 SDOperand visitMULHU(SDNode *N);
151 SDOperand visitMULHS(SDNode *N);
152 SDOperand visitSMUL_LOHI(SDNode *N);
153 SDOperand visitUMUL_LOHI(SDNode *N);
154 SDOperand visitSDIVREM(SDNode *N);
155 SDOperand visitUDIVREM(SDNode *N);
156 SDOperand visitAND(SDNode *N);
157 SDOperand visitOR(SDNode *N);
158 SDOperand visitXOR(SDNode *N);
159 SDOperand SimplifyVBinOp(SDNode *N);
160 SDOperand visitSHL(SDNode *N);
161 SDOperand visitSRA(SDNode *N);
162 SDOperand visitSRL(SDNode *N);
163 SDOperand visitCTLZ(SDNode *N);
164 SDOperand visitCTTZ(SDNode *N);
165 SDOperand visitCTPOP(SDNode *N);
166 SDOperand visitSELECT(SDNode *N);
167 SDOperand visitSELECT_CC(SDNode *N);
168 SDOperand visitSETCC(SDNode *N);
169 SDOperand visitSIGN_EXTEND(SDNode *N);
170 SDOperand visitZERO_EXTEND(SDNode *N);
171 SDOperand visitANY_EXTEND(SDNode *N);
172 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
173 SDOperand visitTRUNCATE(SDNode *N);
174 SDOperand visitBIT_CONVERT(SDNode *N);
175 SDOperand visitFADD(SDNode *N);
176 SDOperand visitFSUB(SDNode *N);
177 SDOperand visitFMUL(SDNode *N);
178 SDOperand visitFDIV(SDNode *N);
179 SDOperand visitFREM(SDNode *N);
180 SDOperand visitFCOPYSIGN(SDNode *N);
181 SDOperand visitSINT_TO_FP(SDNode *N);
182 SDOperand visitUINT_TO_FP(SDNode *N);
183 SDOperand visitFP_TO_SINT(SDNode *N);
184 SDOperand visitFP_TO_UINT(SDNode *N);
185 SDOperand visitFP_ROUND(SDNode *N);
186 SDOperand visitFP_ROUND_INREG(SDNode *N);
187 SDOperand visitFP_EXTEND(SDNode *N);
188 SDOperand visitFNEG(SDNode *N);
189 SDOperand visitFABS(SDNode *N);
190 SDOperand visitBRCOND(SDNode *N);
191 SDOperand visitBR_CC(SDNode *N);
192 SDOperand visitLOAD(SDNode *N);
193 SDOperand visitSTORE(SDNode *N);
194 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
195 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N);
196 SDOperand visitBUILD_VECTOR(SDNode *N);
197 SDOperand visitCONCAT_VECTORS(SDNode *N);
198 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
200 SDOperand XformToShuffleWithZero(SDNode *N);
201 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
203 SDOperand visitShiftByConstant(SDNode *N, unsigned Amt);
205 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
206 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
207 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
208 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
209 SDOperand N3, ISD::CondCode CC,
210 bool NotExtCompare = false);
211 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
212 ISD::CondCode Cond, bool foldBooleans = true);
213 SDOperand SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
215 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType);
216 SDOperand BuildSDIV(SDNode *N);
217 SDOperand BuildUDIV(SDNode *N);
218 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
219 SDOperand ReduceLoadWidth(SDNode *N);
221 SDOperand GetDemandedBits(SDOperand V, uint64_t Mask);
223 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
224 /// looking for aliasing nodes and adding them to the Aliases vector.
225 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
226 SmallVector<SDOperand, 8> &Aliases);
228 /// isAlias - Return true if there is any possibility that the two addresses
230 bool isAlias(SDOperand Ptr1, int64_t Size1,
231 const Value *SrcValue1, int SrcValueOffset1,
232 SDOperand Ptr2, int64_t Size2,
233 const Value *SrcValue2, int SrcValueOffset2);
235 /// FindAliasInfo - Extracts the relevant alias information from the memory
236 /// node. Returns true if the operand was a load.
237 bool FindAliasInfo(SDNode *N,
238 SDOperand &Ptr, int64_t &Size,
239 const Value *&SrcValue, int &SrcValueOffset);
241 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
242 /// looking for a better chain (aliasing node.)
243 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
246 DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
248 TLI(D.getTargetLoweringInfo()),
249 AfterLegalize(false),
252 /// Run - runs the dag combiner on all nodes in the work list
253 void Run(bool RunningAfterLegalize);
259 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
260 /// nodes from the worklist.
261 class VISIBILITY_HIDDEN WorkListRemover :
262 public SelectionDAG::DAGUpdateListener {
265 WorkListRemover(DAGCombiner &dc) : DC(dc) {}
267 virtual void NodeDeleted(SDNode *N) {
268 DC.removeFromWorkList(N);
271 virtual void NodeUpdated(SDNode *N) {
277 //===----------------------------------------------------------------------===//
278 // TargetLowering::DAGCombinerInfo implementation
279 //===----------------------------------------------------------------------===//
281 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
282 ((DAGCombiner*)DC)->AddToWorkList(N);
285 SDOperand TargetLowering::DAGCombinerInfo::
286 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
287 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
290 SDOperand TargetLowering::DAGCombinerInfo::
291 CombineTo(SDNode *N, SDOperand Res) {
292 return ((DAGCombiner*)DC)->CombineTo(N, Res);
296 SDOperand TargetLowering::DAGCombinerInfo::
297 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
298 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
302 //===----------------------------------------------------------------------===//
304 //===----------------------------------------------------------------------===//
306 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
307 /// specified expression for the same cost as the expression itself, or 2 if we
308 /// can compute the negated form more cheaply than the expression itself.
309 static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) {
310 // No compile time optimizations on this type.
311 if (Op.getValueType() == MVT::ppcf128)
314 // fneg is removable even if it has multiple uses.
315 if (Op.getOpcode() == ISD::FNEG) return 2;
317 // Don't allow anything with multiple uses.
318 if (!Op.hasOneUse()) return 0;
320 // Don't recurse exponentially.
321 if (Depth > 6) return 0;
323 switch (Op.getOpcode()) {
324 default: return false;
325 case ISD::ConstantFP:
328 // FIXME: determine better conditions for this xform.
329 if (!UnsafeFPMath) return 0;
332 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
335 return isNegatibleForFree(Op.getOperand(1), Depth+1);
337 // We can't turn -(A-B) into B-A when we honor signed zeros.
338 if (!UnsafeFPMath) return 0;
345 if (HonorSignDependentRoundingFPMath()) return 0;
347 // -(X*Y) -> (-X * Y) or (X*-Y)
348 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
351 return isNegatibleForFree(Op.getOperand(1), Depth+1);
356 return isNegatibleForFree(Op.getOperand(0), Depth+1);
360 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
361 /// returns the newly negated expression.
362 static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG,
363 unsigned Depth = 0) {
364 // fneg is removable even if it has multiple uses.
365 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
367 // Don't allow anything with multiple uses.
368 assert(Op.hasOneUse() && "Unknown reuse!");
370 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
371 switch (Op.getOpcode()) {
372 default: assert(0 && "Unknown code");
373 case ISD::ConstantFP: {
374 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
376 return DAG.getConstantFP(V, Op.getValueType());
379 // FIXME: determine better conditions for this xform.
380 assert(UnsafeFPMath);
383 if (isNegatibleForFree(Op.getOperand(0), Depth+1))
384 return DAG.getNode(ISD::FSUB, Op.getValueType(),
385 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
388 return DAG.getNode(ISD::FSUB, Op.getValueType(),
389 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1),
392 // We can't turn -(A-B) into B-A when we honor signed zeros.
393 assert(UnsafeFPMath);
396 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
397 if (N0CFP->getValueAPF().isZero())
398 return Op.getOperand(1);
401 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1),
406 assert(!HonorSignDependentRoundingFPMath());
409 if (isNegatibleForFree(Op.getOperand(0), Depth+1))
410 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
411 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
415 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
417 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1));
421 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
422 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1));
424 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(),
425 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
431 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
432 // that selects between the values 1 and 0, making it equivalent to a setcc.
433 // Also, set the incoming LHS, RHS, and CC references to the appropriate
434 // nodes based on the type of node we are checking. This simplifies life a
435 // bit for the callers.
436 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
438 if (N.getOpcode() == ISD::SETCC) {
439 LHS = N.getOperand(0);
440 RHS = N.getOperand(1);
441 CC = N.getOperand(2);
444 if (N.getOpcode() == ISD::SELECT_CC &&
445 N.getOperand(2).getOpcode() == ISD::Constant &&
446 N.getOperand(3).getOpcode() == ISD::Constant &&
447 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
448 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
449 LHS = N.getOperand(0);
450 RHS = N.getOperand(1);
451 CC = N.getOperand(4);
457 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
458 // one use. If this is true, it allows the users to invert the operation for
459 // free when it is profitable to do so.
460 static bool isOneUseSetCC(SDOperand N) {
461 SDOperand N0, N1, N2;
462 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
467 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
468 MVT::ValueType VT = N0.getValueType();
469 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
470 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
471 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
472 if (isa<ConstantSDNode>(N1)) {
473 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
474 AddToWorkList(OpNode.Val);
475 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
476 } else if (N0.hasOneUse()) {
477 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
478 AddToWorkList(OpNode.Val);
479 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
482 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
483 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
484 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
485 if (isa<ConstantSDNode>(N0)) {
486 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
487 AddToWorkList(OpNode.Val);
488 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
489 } else if (N1.hasOneUse()) {
490 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
491 AddToWorkList(OpNode.Val);
492 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
498 SDOperand DAGCombiner::CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
500 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
502 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
503 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
504 DOUT << " and " << NumTo-1 << " other values\n";
505 WorkListRemover DeadNodes(*this);
506 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
509 // Push the new nodes and any users onto the worklist
510 for (unsigned i = 0, e = NumTo; i != e; ++i) {
511 AddToWorkList(To[i].Val);
512 AddUsersToWorkList(To[i].Val);
516 // Nodes can be reintroduced into the worklist. Make sure we do not
517 // process a node that has been replaced.
518 removeFromWorkList(N);
520 // Finally, since the node is now dead, remove it from the graph.
522 return SDOperand(N, 0);
525 /// SimplifyDemandedBits - Check the specified integer node value to see if
526 /// it can be simplified or if things it uses can be simplified by bit
527 /// propagation. If so, return true.
528 bool DAGCombiner::SimplifyDemandedBits(SDOperand Op, uint64_t Demanded) {
529 TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize);
530 uint64_t KnownZero, KnownOne;
531 Demanded &= MVT::getIntVTBitMask(Op.getValueType());
532 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
536 AddToWorkList(Op.Val);
538 // Replace the old value with the new one.
540 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG));
541 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
544 // Replace all uses. If any nodes become isomorphic to other nodes and
545 // are deleted, make sure to remove them from our worklist.
546 WorkListRemover DeadNodes(*this);
547 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
549 // Push the new node and any (possibly new) users onto the worklist.
550 AddToWorkList(TLO.New.Val);
551 AddUsersToWorkList(TLO.New.Val);
553 // Finally, if the node is now dead, remove it from the graph. The node
554 // may not be dead if the replacement process recursively simplified to
555 // something else needing this node.
556 if (TLO.Old.Val->use_empty()) {
557 removeFromWorkList(TLO.Old.Val);
559 // If the operands of this node are only used by the node, they will now
560 // be dead. Make sure to visit them first to delete dead nodes early.
561 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i)
562 if (TLO.Old.Val->getOperand(i).Val->hasOneUse())
563 AddToWorkList(TLO.Old.Val->getOperand(i).Val);
565 DAG.DeleteNode(TLO.Old.Val);
570 //===----------------------------------------------------------------------===//
571 // Main DAG Combiner implementation
572 //===----------------------------------------------------------------------===//
574 void DAGCombiner::Run(bool RunningAfterLegalize) {
575 // set the instance variable, so that the various visit routines may use it.
576 AfterLegalize = RunningAfterLegalize;
578 // Add all the dag nodes to the worklist.
579 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
580 E = DAG.allnodes_end(); I != E; ++I)
581 WorkList.push_back(I);
583 // Create a dummy node (which is not added to allnodes), that adds a reference
584 // to the root node, preventing it from being deleted, and tracking any
585 // changes of the root.
586 HandleSDNode Dummy(DAG.getRoot());
588 // The root of the dag may dangle to deleted nodes until the dag combiner is
589 // done. Set it to null to avoid confusion.
590 DAG.setRoot(SDOperand());
592 // while the worklist isn't empty, inspect the node on the end of it and
593 // try and combine it.
594 while (!WorkList.empty()) {
595 SDNode *N = WorkList.back();
598 // If N has no uses, it is dead. Make sure to revisit all N's operands once
599 // N is deleted from the DAG, since they too may now be dead or may have a
600 // reduced number of uses, allowing other xforms.
601 if (N->use_empty() && N != &Dummy) {
602 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
603 AddToWorkList(N->getOperand(i).Val);
609 SDOperand RV = combine(N);
616 // If we get back the same node we passed in, rather than a new node or
617 // zero, we know that the node must have defined multiple values and
618 // CombineTo was used. Since CombineTo takes care of the worklist
619 // mechanics for us, we have no work to do in this case.
623 assert(N->getOpcode() != ISD::DELETED_NODE &&
624 RV.Val->getOpcode() != ISD::DELETED_NODE &&
625 "Node was deleted but visit returned new node!");
627 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
628 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
630 WorkListRemover DeadNodes(*this);
631 if (N->getNumValues() == RV.Val->getNumValues())
632 DAG.ReplaceAllUsesWith(N, RV.Val, &DeadNodes);
634 assert(N->getValueType(0) == RV.getValueType() &&
635 N->getNumValues() == 1 && "Type mismatch");
637 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
640 // Push the new node and any users onto the worklist
641 AddToWorkList(RV.Val);
642 AddUsersToWorkList(RV.Val);
644 // Add any uses of the old node to the worklist in case this node is the
645 // last one that uses them. They may become dead after this node is
647 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
648 AddToWorkList(N->getOperand(i).Val);
650 // Nodes can be reintroduced into the worklist. Make sure we do not
651 // process a node that has been replaced.
652 removeFromWorkList(N);
654 // Finally, since the node is now dead, remove it from the graph.
658 // If the root changed (e.g. it was a dead load, update the root).
659 DAG.setRoot(Dummy.getValue());
662 SDOperand DAGCombiner::visit(SDNode *N) {
663 switch(N->getOpcode()) {
665 case ISD::TokenFactor: return visitTokenFactor(N);
666 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
667 case ISD::ADD: return visitADD(N);
668 case ISD::SUB: return visitSUB(N);
669 case ISD::ADDC: return visitADDC(N);
670 case ISD::ADDE: return visitADDE(N);
671 case ISD::MUL: return visitMUL(N);
672 case ISD::SDIV: return visitSDIV(N);
673 case ISD::UDIV: return visitUDIV(N);
674 case ISD::SREM: return visitSREM(N);
675 case ISD::UREM: return visitUREM(N);
676 case ISD::MULHU: return visitMULHU(N);
677 case ISD::MULHS: return visitMULHS(N);
678 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
679 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
680 case ISD::SDIVREM: return visitSDIVREM(N);
681 case ISD::UDIVREM: return visitUDIVREM(N);
682 case ISD::AND: return visitAND(N);
683 case ISD::OR: return visitOR(N);
684 case ISD::XOR: return visitXOR(N);
685 case ISD::SHL: return visitSHL(N);
686 case ISD::SRA: return visitSRA(N);
687 case ISD::SRL: return visitSRL(N);
688 case ISD::CTLZ: return visitCTLZ(N);
689 case ISD::CTTZ: return visitCTTZ(N);
690 case ISD::CTPOP: return visitCTPOP(N);
691 case ISD::SELECT: return visitSELECT(N);
692 case ISD::SELECT_CC: return visitSELECT_CC(N);
693 case ISD::SETCC: return visitSETCC(N);
694 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
695 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
696 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
697 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
698 case ISD::TRUNCATE: return visitTRUNCATE(N);
699 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
700 case ISD::FADD: return visitFADD(N);
701 case ISD::FSUB: return visitFSUB(N);
702 case ISD::FMUL: return visitFMUL(N);
703 case ISD::FDIV: return visitFDIV(N);
704 case ISD::FREM: return visitFREM(N);
705 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
706 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
707 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
708 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
709 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
710 case ISD::FP_ROUND: return visitFP_ROUND(N);
711 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
712 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
713 case ISD::FNEG: return visitFNEG(N);
714 case ISD::FABS: return visitFABS(N);
715 case ISD::BRCOND: return visitBRCOND(N);
716 case ISD::BR_CC: return visitBR_CC(N);
717 case ISD::LOAD: return visitLOAD(N);
718 case ISD::STORE: return visitSTORE(N);
719 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
720 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
721 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
722 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
723 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
728 SDOperand DAGCombiner::combine(SDNode *N) {
730 SDOperand RV = visit(N);
732 // If nothing happened, try a target-specific DAG combine.
734 assert(N->getOpcode() != ISD::DELETED_NODE &&
735 "Node was deleted but visit returned NULL!");
737 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
738 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
740 // Expose the DAG combiner to the target combiner impls.
741 TargetLowering::DAGCombinerInfo
742 DagCombineInfo(DAG, !AfterLegalize, false, this);
744 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
751 /// getInputChainForNode - Given a node, return its input chain if it has one,
752 /// otherwise return a null sd operand.
753 static SDOperand getInputChainForNode(SDNode *N) {
754 if (unsigned NumOps = N->getNumOperands()) {
755 if (N->getOperand(0).getValueType() == MVT::Other)
756 return N->getOperand(0);
757 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
758 return N->getOperand(NumOps-1);
759 for (unsigned i = 1; i < NumOps-1; ++i)
760 if (N->getOperand(i).getValueType() == MVT::Other)
761 return N->getOperand(i);
763 return SDOperand(0, 0);
766 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
767 // If N has two operands, where one has an input chain equal to the other,
768 // the 'other' chain is redundant.
769 if (N->getNumOperands() == 2) {
770 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
771 return N->getOperand(0);
772 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
773 return N->getOperand(1);
776 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
777 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
778 SmallPtrSet<SDNode*, 16> SeenOps;
779 bool Changed = false; // If we should replace this token factor.
781 // Start out with this token factor.
784 // Iterate through token factors. The TFs grows when new token factors are
786 for (unsigned i = 0; i < TFs.size(); ++i) {
789 // Check each of the operands.
790 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
791 SDOperand Op = TF->getOperand(i);
793 switch (Op.getOpcode()) {
794 case ISD::EntryToken:
795 // Entry tokens don't need to be added to the list. They are
800 case ISD::TokenFactor:
801 if ((CombinerAA || Op.hasOneUse()) &&
802 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
803 // Queue up for processing.
804 TFs.push_back(Op.Val);
805 // Clean up in case the token factor is removed.
806 AddToWorkList(Op.Val);
813 // Only add if it isn't already in the list.
814 if (SeenOps.insert(Op.Val))
825 // If we've change things around then replace token factor.
828 // The entry token is the only possible outcome.
829 Result = DAG.getEntryNode();
831 // New and improved token factor.
832 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
835 // Don't add users to work list.
836 return CombineTo(N, Result, false);
842 /// MERGE_VALUES can always be eliminated.
843 SDOperand DAGCombiner::visitMERGE_VALUES(SDNode *N) {
844 WorkListRemover DeadNodes(*this);
845 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
846 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, i), N->getOperand(i),
848 removeFromWorkList(N);
850 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
855 SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
856 MVT::ValueType VT = N0.getValueType();
857 SDOperand N00 = N0.getOperand(0);
858 SDOperand N01 = N0.getOperand(1);
859 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
860 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
861 isa<ConstantSDNode>(N00.getOperand(1))) {
862 N0 = DAG.getNode(ISD::ADD, VT,
863 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01),
864 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01));
865 return DAG.getNode(ISD::ADD, VT, N0, N1);
871 SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp,
873 MVT::ValueType VT = N->getValueType(0);
874 unsigned Opc = N->getOpcode();
875 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
876 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
877 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
878 ISD::CondCode CC = ISD::SETCC_INVALID;
880 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
882 SDOperand CCOp = Slct.getOperand(0);
883 if (CCOp.getOpcode() == ISD::SETCC)
884 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
887 bool DoXform = false;
889 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
891 if (LHS.getOpcode() == ISD::Constant &&
892 cast<ConstantSDNode>(LHS)->isNullValue())
894 else if (CC != ISD::SETCC_INVALID &&
895 RHS.getOpcode() == ISD::Constant &&
896 cast<ConstantSDNode>(RHS)->isNullValue()) {
898 SDOperand Op0 = Slct.getOperand(0);
899 bool isInt = MVT::isInteger(isSlctCC ? Op0.getValueType()
900 : Op0.getOperand(0).getValueType());
901 CC = ISD::getSetCCInverse(CC, isInt);
907 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS);
909 return DAG.getSelectCC(OtherOp, Result,
910 Slct.getOperand(0), Slct.getOperand(1), CC);
911 SDOperand CCOp = Slct.getOperand(0);
913 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0),
914 CCOp.getOperand(1), CC);
915 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result);
920 SDOperand DAGCombiner::visitADD(SDNode *N) {
921 SDOperand N0 = N->getOperand(0);
922 SDOperand N1 = N->getOperand(1);
923 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
924 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
925 MVT::ValueType VT = N0.getValueType();
928 if (MVT::isVector(VT)) {
929 SDOperand FoldedVOp = SimplifyVBinOp(N);
930 if (FoldedVOp.Val) return FoldedVOp;
933 // fold (add x, undef) -> undef
934 if (N0.getOpcode() == ISD::UNDEF)
936 if (N1.getOpcode() == ISD::UNDEF)
938 // fold (add c1, c2) -> c1+c2
940 return DAG.getConstant(N0C->getValue() + N1C->getValue(), VT);
941 // canonicalize constant to RHS
943 return DAG.getNode(ISD::ADD, VT, N1, N0);
944 // fold (add x, 0) -> x
945 if (N1C && N1C->isNullValue())
947 // fold ((c1-A)+c2) -> (c1+c2)-A
948 if (N1C && N0.getOpcode() == ISD::SUB)
949 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
950 return DAG.getNode(ISD::SUB, VT,
951 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
954 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
957 // fold ((0-A) + B) -> B-A
958 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
959 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
960 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
961 // fold (A + (0-B)) -> A-B
962 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
963 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
964 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
965 // fold (A+(B-A)) -> B
966 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
967 return N1.getOperand(0);
969 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
970 return SDOperand(N, 0);
972 // fold (a+b) -> (a|b) iff a and b share no bits.
973 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
974 uint64_t LHSZero, LHSOne;
975 uint64_t RHSZero, RHSOne;
976 uint64_t Mask = MVT::getIntVTBitMask(VT);
977 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
979 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
981 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
982 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
983 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
984 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
985 return DAG.getNode(ISD::OR, VT, N0, N1);
989 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
990 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) {
991 SDOperand Result = combineShlAddConstant(N0, N1, DAG);
992 if (Result.Val) return Result;
994 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) {
995 SDOperand Result = combineShlAddConstant(N1, N0, DAG);
996 if (Result.Val) return Result;
999 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
1000 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) {
1001 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG);
1002 if (Result.Val) return Result;
1004 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
1005 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
1006 if (Result.Val) return Result;
1012 SDOperand DAGCombiner::visitADDC(SDNode *N) {
1013 SDOperand N0 = N->getOperand(0);
1014 SDOperand N1 = N->getOperand(1);
1015 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1016 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1017 MVT::ValueType VT = N0.getValueType();
1019 // If the flag result is dead, turn this into an ADD.
1020 if (N->hasNUsesOfValue(0, 1))
1021 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0),
1022 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
1024 // canonicalize constant to RHS.
1026 SDOperand Ops[] = { N1, N0 };
1027 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
1030 // fold (addc x, 0) -> x + no carry out
1031 if (N1C && N1C->isNullValue())
1032 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
1034 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1035 uint64_t LHSZero, LHSOne;
1036 uint64_t RHSZero, RHSOne;
1037 uint64_t Mask = MVT::getIntVTBitMask(VT);
1038 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1040 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1042 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1043 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1044 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1045 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1046 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1),
1047 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
1053 SDOperand DAGCombiner::visitADDE(SDNode *N) {
1054 SDOperand N0 = N->getOperand(0);
1055 SDOperand N1 = N->getOperand(1);
1056 SDOperand CarryIn = N->getOperand(2);
1057 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1058 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1059 //MVT::ValueType VT = N0.getValueType();
1061 // canonicalize constant to RHS
1063 SDOperand Ops[] = { N1, N0, CarryIn };
1064 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3);
1067 // fold (adde x, y, false) -> (addc x, y)
1068 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) {
1069 SDOperand Ops[] = { N1, N0 };
1070 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
1078 SDOperand DAGCombiner::visitSUB(SDNode *N) {
1079 SDOperand N0 = N->getOperand(0);
1080 SDOperand N1 = N->getOperand(1);
1081 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1082 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1083 MVT::ValueType VT = N0.getValueType();
1086 if (MVT::isVector(VT)) {
1087 SDOperand FoldedVOp = SimplifyVBinOp(N);
1088 if (FoldedVOp.Val) return FoldedVOp;
1091 // fold (sub x, x) -> 0
1093 return DAG.getConstant(0, N->getValueType(0));
1094 // fold (sub c1, c2) -> c1-c2
1096 return DAG.getNode(ISD::SUB, VT, N0, N1);
1097 // fold (sub x, c) -> (add x, -c)
1099 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
1100 // fold (A+B)-A -> B
1101 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1102 return N0.getOperand(1);
1103 // fold (A+B)-B -> A
1104 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1105 return N0.getOperand(0);
1106 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1107 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
1108 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
1109 if (Result.Val) return Result;
1111 // If either operand of a sub is undef, the result is undef
1112 if (N0.getOpcode() == ISD::UNDEF)
1114 if (N1.getOpcode() == ISD::UNDEF)
1120 SDOperand DAGCombiner::visitMUL(SDNode *N) {
1121 SDOperand N0 = N->getOperand(0);
1122 SDOperand N1 = N->getOperand(1);
1123 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1124 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1125 MVT::ValueType VT = N0.getValueType();
1128 if (MVT::isVector(VT)) {
1129 SDOperand FoldedVOp = SimplifyVBinOp(N);
1130 if (FoldedVOp.Val) return FoldedVOp;
1133 // fold (mul x, undef) -> 0
1134 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1135 return DAG.getConstant(0, VT);
1136 // fold (mul c1, c2) -> c1*c2
1138 return DAG.getNode(ISD::MUL, VT, N0, N1);
1139 // canonicalize constant to RHS
1141 return DAG.getNode(ISD::MUL, VT, N1, N0);
1142 // fold (mul x, 0) -> 0
1143 if (N1C && N1C->isNullValue())
1145 // fold (mul x, -1) -> 0-x
1146 if (N1C && N1C->isAllOnesValue())
1147 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1148 // fold (mul x, (1 << c)) -> x << c
1149 if (N1C && isPowerOf2_64(N1C->getValue()))
1150 return DAG.getNode(ISD::SHL, VT, N0,
1151 DAG.getConstant(Log2_64(N1C->getValue()),
1152 TLI.getShiftAmountTy()));
1153 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1154 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
1155 // FIXME: If the input is something that is easily negated (e.g. a
1156 // single-use add), we should put the negate there.
1157 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
1158 DAG.getNode(ISD::SHL, VT, N0,
1159 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
1160 TLI.getShiftAmountTy())));
1163 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1164 if (N1C && N0.getOpcode() == ISD::SHL &&
1165 isa<ConstantSDNode>(N0.getOperand(1))) {
1166 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
1167 AddToWorkList(C3.Val);
1168 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
1171 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1174 SDOperand Sh(0,0), Y(0,0);
1175 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1176 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1177 N0.Val->hasOneUse()) {
1179 } else if (N1.getOpcode() == ISD::SHL &&
1180 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
1184 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
1185 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
1188 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1189 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1190 isa<ConstantSDNode>(N0.getOperand(1))) {
1191 return DAG.getNode(ISD::ADD, VT,
1192 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
1193 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
1197 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
1204 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
1205 SDOperand N0 = N->getOperand(0);
1206 SDOperand N1 = N->getOperand(1);
1207 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1208 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1209 MVT::ValueType VT = N->getValueType(0);
1212 if (MVT::isVector(VT)) {
1213 SDOperand FoldedVOp = SimplifyVBinOp(N);
1214 if (FoldedVOp.Val) return FoldedVOp;
1217 // fold (sdiv c1, c2) -> c1/c2
1218 if (N0C && N1C && !N1C->isNullValue())
1219 return DAG.getNode(ISD::SDIV, VT, N0, N1);
1220 // fold (sdiv X, 1) -> X
1221 if (N1C && N1C->getSignExtended() == 1LL)
1223 // fold (sdiv X, -1) -> 0-X
1224 if (N1C && N1C->isAllOnesValue())
1225 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1226 // If we know the sign bits of both operands are zero, strength reduce to a
1227 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1228 if (!MVT::isVector(VT)) {
1229 uint64_t SignBit = MVT::getIntVTSignBit(VT);
1230 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1231 DAG.MaskedValueIsZero(N0, SignBit))
1232 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
1234 // fold (sdiv X, pow2) -> simple ops after legalize
1235 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
1236 (isPowerOf2_64(N1C->getSignExtended()) ||
1237 isPowerOf2_64(-N1C->getSignExtended()))) {
1238 // If dividing by powers of two is cheap, then don't perform the following
1240 if (TLI.isPow2DivCheap())
1242 int64_t pow2 = N1C->getSignExtended();
1243 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1244 unsigned lg2 = Log2_64(abs2);
1245 // Splat the sign bit into the register
1246 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
1247 DAG.getConstant(MVT::getSizeInBits(VT)-1,
1248 TLI.getShiftAmountTy()));
1249 AddToWorkList(SGN.Val);
1250 // Add (N0 < 0) ? abs2 - 1 : 0;
1251 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
1252 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
1253 TLI.getShiftAmountTy()));
1254 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
1255 AddToWorkList(SRL.Val);
1256 AddToWorkList(ADD.Val); // Divide by pow2
1257 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
1258 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
1259 // If we're dividing by a positive value, we're done. Otherwise, we must
1260 // negate the result.
1263 AddToWorkList(SRA.Val);
1264 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
1266 // if integer divide is expensive and we satisfy the requirements, emit an
1267 // alternate sequence.
1268 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
1269 !TLI.isIntDivCheap()) {
1270 SDOperand Op = BuildSDIV(N);
1271 if (Op.Val) return Op;
1275 if (N0.getOpcode() == ISD::UNDEF)
1276 return DAG.getConstant(0, VT);
1277 // X / undef -> undef
1278 if (N1.getOpcode() == ISD::UNDEF)
1284 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
1285 SDOperand N0 = N->getOperand(0);
1286 SDOperand N1 = N->getOperand(1);
1287 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1288 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1289 MVT::ValueType VT = N->getValueType(0);
1292 if (MVT::isVector(VT)) {
1293 SDOperand FoldedVOp = SimplifyVBinOp(N);
1294 if (FoldedVOp.Val) return FoldedVOp;
1297 // fold (udiv c1, c2) -> c1/c2
1298 if (N0C && N1C && !N1C->isNullValue())
1299 return DAG.getNode(ISD::UDIV, VT, N0, N1);
1300 // fold (udiv x, (1 << c)) -> x >>u c
1301 if (N1C && isPowerOf2_64(N1C->getValue()))
1302 return DAG.getNode(ISD::SRL, VT, N0,
1303 DAG.getConstant(Log2_64(N1C->getValue()),
1304 TLI.getShiftAmountTy()));
1305 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1306 if (N1.getOpcode() == ISD::SHL) {
1307 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1308 if (isPowerOf2_64(SHC->getValue())) {
1309 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
1310 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
1311 DAG.getConstant(Log2_64(SHC->getValue()),
1313 AddToWorkList(Add.Val);
1314 return DAG.getNode(ISD::SRL, VT, N0, Add);
1318 // fold (udiv x, c) -> alternate
1319 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
1320 SDOperand Op = BuildUDIV(N);
1321 if (Op.Val) return Op;
1325 if (N0.getOpcode() == ISD::UNDEF)
1326 return DAG.getConstant(0, VT);
1327 // X / undef -> undef
1328 if (N1.getOpcode() == ISD::UNDEF)
1334 SDOperand DAGCombiner::visitSREM(SDNode *N) {
1335 SDOperand N0 = N->getOperand(0);
1336 SDOperand N1 = N->getOperand(1);
1337 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1338 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1339 MVT::ValueType VT = N->getValueType(0);
1341 // fold (srem c1, c2) -> c1%c2
1342 if (N0C && N1C && !N1C->isNullValue())
1343 return DAG.getNode(ISD::SREM, VT, N0, N1);
1344 // If we know the sign bits of both operands are zero, strength reduce to a
1345 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1346 if (!MVT::isVector(VT)) {
1347 uint64_t SignBit = MVT::getIntVTSignBit(VT);
1348 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1349 DAG.MaskedValueIsZero(N0, SignBit))
1350 return DAG.getNode(ISD::UREM, VT, N0, N1);
1353 // If X/C can be simplified by the division-by-constant logic, lower
1354 // X%C to the equivalent of X-X/C*C.
1355 if (N1C && !N1C->isNullValue()) {
1356 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
1357 AddToWorkList(Div.Val);
1358 SDOperand OptimizedDiv = combine(Div.Val);
1359 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) {
1360 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
1361 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1362 AddToWorkList(Mul.Val);
1368 if (N0.getOpcode() == ISD::UNDEF)
1369 return DAG.getConstant(0, VT);
1370 // X % undef -> undef
1371 if (N1.getOpcode() == ISD::UNDEF)
1377 SDOperand DAGCombiner::visitUREM(SDNode *N) {
1378 SDOperand N0 = N->getOperand(0);
1379 SDOperand N1 = N->getOperand(1);
1380 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1381 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1382 MVT::ValueType VT = N->getValueType(0);
1384 // fold (urem c1, c2) -> c1%c2
1385 if (N0C && N1C && !N1C->isNullValue())
1386 return DAG.getNode(ISD::UREM, VT, N0, N1);
1387 // fold (urem x, pow2) -> (and x, pow2-1)
1388 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
1389 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
1390 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1391 if (N1.getOpcode() == ISD::SHL) {
1392 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1393 if (isPowerOf2_64(SHC->getValue())) {
1394 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
1395 AddToWorkList(Add.Val);
1396 return DAG.getNode(ISD::AND, VT, N0, Add);
1401 // If X/C can be simplified by the division-by-constant logic, lower
1402 // X%C to the equivalent of X-X/C*C.
1403 if (N1C && !N1C->isNullValue()) {
1404 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
1405 SDOperand OptimizedDiv = combine(Div.Val);
1406 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) {
1407 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
1408 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1409 AddToWorkList(Mul.Val);
1415 if (N0.getOpcode() == ISD::UNDEF)
1416 return DAG.getConstant(0, VT);
1417 // X % undef -> undef
1418 if (N1.getOpcode() == ISD::UNDEF)
1424 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
1425 SDOperand N0 = N->getOperand(0);
1426 SDOperand N1 = N->getOperand(1);
1427 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1428 MVT::ValueType VT = N->getValueType(0);
1430 // fold (mulhs x, 0) -> 0
1431 if (N1C && N1C->isNullValue())
1433 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1434 if (N1C && N1C->getValue() == 1)
1435 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
1436 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
1437 TLI.getShiftAmountTy()));
1438 // fold (mulhs x, undef) -> 0
1439 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1440 return DAG.getConstant(0, VT);
1445 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
1446 SDOperand N0 = N->getOperand(0);
1447 SDOperand N1 = N->getOperand(1);
1448 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1449 MVT::ValueType VT = N->getValueType(0);
1451 // fold (mulhu x, 0) -> 0
1452 if (N1C && N1C->isNullValue())
1454 // fold (mulhu x, 1) -> 0
1455 if (N1C && N1C->getValue() == 1)
1456 return DAG.getConstant(0, N0.getValueType());
1457 // fold (mulhu x, undef) -> 0
1458 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1459 return DAG.getConstant(0, VT);
1464 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1465 /// compute two values. LoOp and HiOp give the opcodes for the two computations
1466 /// that are being performed. Return true if a simplification was made.
1468 SDOperand DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
1470 // If the high half is not needed, just compute the low half.
1471 bool HiExists = N->hasAnyUseOfValue(1);
1474 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1475 SDOperand Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(),
1476 N->getNumOperands());
1477 return CombineTo(N, Res, Res);
1480 // If the low half is not needed, just compute the high half.
1481 bool LoExists = N->hasAnyUseOfValue(0);
1484 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
1485 SDOperand Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(),
1486 N->getNumOperands());
1487 return CombineTo(N, Res, Res);
1490 // If both halves are used, return as it is.
1491 if (LoExists && HiExists)
1494 // If the two computed results can be simplified separately, separate them.
1496 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0),
1497 N->op_begin(), N->getNumOperands());
1498 AddToWorkList(Lo.Val);
1499 SDOperand LoOpt = combine(Lo.Val);
1500 if (LoOpt.Val && LoOpt.Val != Lo.Val &&
1501 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))
1502 return CombineTo(N, LoOpt, LoOpt);
1506 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1),
1507 N->op_begin(), N->getNumOperands());
1508 AddToWorkList(Hi.Val);
1509 SDOperand HiOpt = combine(Hi.Val);
1510 if (HiOpt.Val && HiOpt != Hi &&
1511 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))
1512 return CombineTo(N, HiOpt, HiOpt);
1517 SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) {
1518 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
1519 if (Res.Val) return Res;
1524 SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) {
1525 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
1526 if (Res.Val) return Res;
1531 SDOperand DAGCombiner::visitSDIVREM(SDNode *N) {
1532 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
1533 if (Res.Val) return Res;
1538 SDOperand DAGCombiner::visitUDIVREM(SDNode *N) {
1539 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
1540 if (Res.Val) return Res;
1545 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1546 /// two operands of the same opcode, try to simplify it.
1547 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1548 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
1549 MVT::ValueType VT = N0.getValueType();
1550 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1552 // For each of OP in AND/OR/XOR:
1553 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1554 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1555 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1556 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1557 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1558 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1559 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1560 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1561 N0.getOperand(0).getValueType(),
1562 N0.getOperand(0), N1.getOperand(0));
1563 AddToWorkList(ORNode.Val);
1564 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1567 // For each of OP in SHL/SRL/SRA/AND...
1568 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1569 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1570 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1571 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1572 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1573 N0.getOperand(1) == N1.getOperand(1)) {
1574 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1575 N0.getOperand(0).getValueType(),
1576 N0.getOperand(0), N1.getOperand(0));
1577 AddToWorkList(ORNode.Val);
1578 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1584 SDOperand DAGCombiner::visitAND(SDNode *N) {
1585 SDOperand N0 = N->getOperand(0);
1586 SDOperand N1 = N->getOperand(1);
1587 SDOperand LL, LR, RL, RR, CC0, CC1;
1588 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1589 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1590 MVT::ValueType VT = N1.getValueType();
1593 if (MVT::isVector(VT)) {
1594 SDOperand FoldedVOp = SimplifyVBinOp(N);
1595 if (FoldedVOp.Val) return FoldedVOp;
1598 // fold (and x, undef) -> 0
1599 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1600 return DAG.getConstant(0, VT);
1601 // fold (and c1, c2) -> c1&c2
1603 return DAG.getNode(ISD::AND, VT, N0, N1);
1604 // canonicalize constant to RHS
1606 return DAG.getNode(ISD::AND, VT, N1, N0);
1607 // fold (and x, -1) -> x
1608 if (N1C && N1C->isAllOnesValue())
1610 // if (and x, c) is known to be zero, return 0
1611 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1612 return DAG.getConstant(0, VT);
1614 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1617 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1618 if (N1C && N0.getOpcode() == ISD::OR)
1619 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1620 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1622 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1623 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1624 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1625 if (DAG.MaskedValueIsZero(N0.getOperand(0),
1626 ~N1C->getValue() & InMask)) {
1627 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1630 // Replace uses of the AND with uses of the Zero extend node.
1633 // We actually want to replace all uses of the any_extend with the
1634 // zero_extend, to avoid duplicating things. This will later cause this
1635 // AND to be folded.
1636 CombineTo(N0.Val, Zext);
1637 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1640 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1641 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1642 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1643 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1645 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1646 MVT::isInteger(LL.getValueType())) {
1647 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1648 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1649 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1650 AddToWorkList(ORNode.Val);
1651 return DAG.getSetCC(VT, ORNode, LR, Op1);
1653 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1654 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1655 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1656 AddToWorkList(ANDNode.Val);
1657 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1659 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1660 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1661 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1662 AddToWorkList(ORNode.Val);
1663 return DAG.getSetCC(VT, ORNode, LR, Op1);
1666 // canonicalize equivalent to ll == rl
1667 if (LL == RR && LR == RL) {
1668 Op1 = ISD::getSetCCSwappedOperands(Op1);
1671 if (LL == RL && LR == RR) {
1672 bool isInteger = MVT::isInteger(LL.getValueType());
1673 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1674 if (Result != ISD::SETCC_INVALID)
1675 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1679 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1680 if (N0.getOpcode() == N1.getOpcode()) {
1681 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1682 if (Tmp.Val) return Tmp;
1685 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1686 // fold (and (sra)) -> (and (srl)) when possible.
1687 if (!MVT::isVector(VT) &&
1688 SimplifyDemandedBits(SDOperand(N, 0)))
1689 return SDOperand(N, 0);
1690 // fold (zext_inreg (extload x)) -> (zextload x)
1691 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
1692 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1693 MVT::ValueType EVT = LN0->getMemoryVT();
1694 // If we zero all the possible extended bits, then we can turn this into
1695 // a zextload if we are running before legalize or the operation is legal.
1696 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1697 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1698 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1699 LN0->getBasePtr(), LN0->getSrcValue(),
1700 LN0->getSrcValueOffset(), EVT,
1702 LN0->getAlignment());
1704 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1705 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1708 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1709 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
1711 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1712 MVT::ValueType EVT = LN0->getMemoryVT();
1713 // If we zero all the possible extended bits, then we can turn this into
1714 // a zextload if we are running before legalize or the operation is legal.
1715 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1716 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1717 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1718 LN0->getBasePtr(), LN0->getSrcValue(),
1719 LN0->getSrcValueOffset(), EVT,
1721 LN0->getAlignment());
1723 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1724 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1728 // fold (and (load x), 255) -> (zextload x, i8)
1729 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1730 if (N1C && N0.getOpcode() == ISD::LOAD) {
1731 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1732 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1733 LN0->isUnindexed() && N0.hasOneUse()) {
1734 MVT::ValueType EVT, LoadedVT;
1735 if (N1C->getValue() == 255)
1737 else if (N1C->getValue() == 65535)
1739 else if (N1C->getValue() == ~0U)
1744 LoadedVT = LN0->getMemoryVT();
1745 if (EVT != MVT::Other && LoadedVT > EVT &&
1746 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1747 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1748 // For big endian targets, we need to add an offset to the pointer to
1749 // load the correct bytes. For little endian systems, we merely need to
1750 // read fewer bytes from the same pointer.
1751 unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8;
1752 unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8;
1753 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
1754 unsigned Alignment = LN0->getAlignment();
1755 SDOperand NewPtr = LN0->getBasePtr();
1756 if (TLI.isBigEndian()) {
1757 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1758 DAG.getConstant(PtrOff, PtrType));
1759 Alignment = MinAlign(Alignment, PtrOff);
1761 AddToWorkList(NewPtr.Val);
1763 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1764 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
1765 LN0->isVolatile(), Alignment);
1767 CombineTo(N0.Val, Load, Load.getValue(1));
1768 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1776 SDOperand DAGCombiner::visitOR(SDNode *N) {
1777 SDOperand N0 = N->getOperand(0);
1778 SDOperand N1 = N->getOperand(1);
1779 SDOperand LL, LR, RL, RR, CC0, CC1;
1780 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1781 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1782 MVT::ValueType VT = N1.getValueType();
1783 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1786 if (MVT::isVector(VT)) {
1787 SDOperand FoldedVOp = SimplifyVBinOp(N);
1788 if (FoldedVOp.Val) return FoldedVOp;
1791 // fold (or x, undef) -> -1
1792 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1793 return DAG.getConstant(~0ULL, VT);
1794 // fold (or c1, c2) -> c1|c2
1796 return DAG.getNode(ISD::OR, VT, N0, N1);
1797 // canonicalize constant to RHS
1799 return DAG.getNode(ISD::OR, VT, N1, N0);
1800 // fold (or x, 0) -> x
1801 if (N1C && N1C->isNullValue())
1803 // fold (or x, -1) -> -1
1804 if (N1C && N1C->isAllOnesValue())
1806 // fold (or x, c) -> c iff (x & ~c) == 0
1808 DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1811 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1814 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1815 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1816 isa<ConstantSDNode>(N0.getOperand(1))) {
1817 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1818 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1820 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1822 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1823 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1824 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1825 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1827 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1828 MVT::isInteger(LL.getValueType())) {
1829 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1830 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1831 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1832 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1833 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1834 AddToWorkList(ORNode.Val);
1835 return DAG.getSetCC(VT, ORNode, LR, Op1);
1837 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1838 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1839 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1840 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1841 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1842 AddToWorkList(ANDNode.Val);
1843 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1846 // canonicalize equivalent to ll == rl
1847 if (LL == RR && LR == RL) {
1848 Op1 = ISD::getSetCCSwappedOperands(Op1);
1851 if (LL == RL && LR == RR) {
1852 bool isInteger = MVT::isInteger(LL.getValueType());
1853 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1854 if (Result != ISD::SETCC_INVALID)
1855 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1859 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1860 if (N0.getOpcode() == N1.getOpcode()) {
1861 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1862 if (Tmp.Val) return Tmp;
1865 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1866 if (N0.getOpcode() == ISD::AND &&
1867 N1.getOpcode() == ISD::AND &&
1868 N0.getOperand(1).getOpcode() == ISD::Constant &&
1869 N1.getOperand(1).getOpcode() == ISD::Constant &&
1870 // Don't increase # computations.
1871 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1872 // We can only do this xform if we know that bits from X that are set in C2
1873 // but not in C1 are already zero. Likewise for Y.
1874 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1875 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1877 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1878 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1879 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1880 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1885 // See if this is some rotate idiom.
1886 if (SDNode *Rot = MatchRotate(N0, N1))
1887 return SDOperand(Rot, 0);
1893 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1894 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1895 if (Op.getOpcode() == ISD::AND) {
1896 if (isa<ConstantSDNode>(Op.getOperand(1))) {
1897 Mask = Op.getOperand(1);
1898 Op = Op.getOperand(0);
1904 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1912 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1913 // idioms for rotate, and if the target supports rotation instructions, generate
1915 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1916 // Must be a legal type. Expanded an promoted things won't work with rotates.
1917 MVT::ValueType VT = LHS.getValueType();
1918 if (!TLI.isTypeLegal(VT)) return 0;
1920 // The target must have at least one rotate flavor.
1921 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1922 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1923 if (!HasROTL && !HasROTR) return 0;
1925 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1926 SDOperand LHSShift; // The shift.
1927 SDOperand LHSMask; // AND value if any.
1928 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1929 return 0; // Not part of a rotate.
1931 SDOperand RHSShift; // The shift.
1932 SDOperand RHSMask; // AND value if any.
1933 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1934 return 0; // Not part of a rotate.
1936 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1937 return 0; // Not shifting the same value.
1939 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1940 return 0; // Shifts must disagree.
1942 // Canonicalize shl to left side in a shl/srl pair.
1943 if (RHSShift.getOpcode() == ISD::SHL) {
1944 std::swap(LHS, RHS);
1945 std::swap(LHSShift, RHSShift);
1946 std::swap(LHSMask , RHSMask );
1949 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1950 SDOperand LHSShiftArg = LHSShift.getOperand(0);
1951 SDOperand LHSShiftAmt = LHSShift.getOperand(1);
1952 SDOperand RHSShiftAmt = RHSShift.getOperand(1);
1954 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1955 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1956 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
1957 RHSShiftAmt.getOpcode() == ISD::Constant) {
1958 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue();
1959 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue();
1960 if ((LShVal + RShVal) != OpSizeInBits)
1965 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt);
1967 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
1969 // If there is an AND of either shifted operand, apply it to the result.
1970 if (LHSMask.Val || RHSMask.Val) {
1971 uint64_t Mask = MVT::getIntVTBitMask(VT);
1974 uint64_t RHSBits = (1ULL << LShVal)-1;
1975 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1978 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1979 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1982 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1988 // If there is a mask here, and we have a variable shift, we can't be sure
1989 // that we're masking out the right stuff.
1990 if (LHSMask.Val || RHSMask.Val)
1993 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1994 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1995 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
1996 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
1997 if (ConstantSDNode *SUBC =
1998 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
1999 if (SUBC->getValue() == OpSizeInBits)
2001 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
2003 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
2007 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2008 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
2009 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
2010 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
2011 if (ConstantSDNode *SUBC =
2012 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
2013 if (SUBC->getValue() == OpSizeInBits)
2015 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
2017 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
2021 // Look for sign/zext/any-extended cases:
2022 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2023 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2024 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) &&
2025 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2026 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2027 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) {
2028 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0);
2029 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0);
2030 if (RExtOp0.getOpcode() == ISD::SUB &&
2031 RExtOp0.getOperand(1) == LExtOp0) {
2032 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2034 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2035 // (rotl x, (sub 32, y))
2036 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
2037 if (SUBC->getValue() == OpSizeInBits) {
2039 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
2041 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
2044 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2045 RExtOp0 == LExtOp0.getOperand(1)) {
2046 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
2048 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
2049 // (rotr x, (sub 32, y))
2050 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2051 if (SUBC->getValue() == OpSizeInBits) {
2053 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val;
2055 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
2065 SDOperand DAGCombiner::visitXOR(SDNode *N) {
2066 SDOperand N0 = N->getOperand(0);
2067 SDOperand N1 = N->getOperand(1);
2068 SDOperand LHS, RHS, CC;
2069 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2070 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2071 MVT::ValueType VT = N0.getValueType();
2074 if (MVT::isVector(VT)) {
2075 SDOperand FoldedVOp = SimplifyVBinOp(N);
2076 if (FoldedVOp.Val) return FoldedVOp;
2079 // fold (xor x, undef) -> undef
2080 if (N0.getOpcode() == ISD::UNDEF)
2082 if (N1.getOpcode() == ISD::UNDEF)
2084 // fold (xor c1, c2) -> c1^c2
2086 return DAG.getNode(ISD::XOR, VT, N0, N1);
2087 // canonicalize constant to RHS
2089 return DAG.getNode(ISD::XOR, VT, N1, N0);
2090 // fold (xor x, 0) -> x
2091 if (N1C && N1C->isNullValue())
2094 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
2097 // fold !(x cc y) -> (x !cc y)
2098 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2099 bool isInt = MVT::isInteger(LHS.getValueType());
2100 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2102 if (N0.getOpcode() == ISD::SETCC)
2103 return DAG.getSetCC(VT, LHS, RHS, NotCC);
2104 if (N0.getOpcode() == ISD::SELECT_CC)
2105 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
2106 assert(0 && "Unhandled SetCC Equivalent!");
2109 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2110 if (N1C && N1C->getValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2111 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2112 SDOperand V = N0.getOperand(0);
2113 V = DAG.getNode(ISD::XOR, V.getValueType(), V,
2114 DAG.getConstant(1, V.getValueType()));
2115 AddToWorkList(V.Val);
2116 return DAG.getNode(ISD::ZERO_EXTEND, VT, V);
2119 // fold !(x or y) -> (!x and !y) iff x or y are setcc
2120 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 &&
2121 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2122 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2123 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2124 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2125 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
2126 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
2127 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
2128 return DAG.getNode(NewOpcode, VT, LHS, RHS);
2131 // fold !(x or y) -> (!x and !y) iff x or y are constants
2132 if (N1C && N1C->isAllOnesValue() &&
2133 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2134 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2135 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2136 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2137 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
2138 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
2139 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
2140 return DAG.getNode(NewOpcode, VT, LHS, RHS);
2143 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
2144 if (N1C && N0.getOpcode() == ISD::XOR) {
2145 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2146 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2148 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
2149 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
2151 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
2152 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
2154 // fold (xor x, x) -> 0
2156 if (!MVT::isVector(VT)) {
2157 return DAG.getConstant(0, VT);
2158 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
2159 // Produce a vector of zeros.
2160 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT));
2161 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
2162 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
2166 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2167 if (N0.getOpcode() == N1.getOpcode()) {
2168 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2169 if (Tmp.Val) return Tmp;
2172 // Simplify the expression using non-local knowledge.
2173 if (!MVT::isVector(VT) &&
2174 SimplifyDemandedBits(SDOperand(N, 0)))
2175 return SDOperand(N, 0);
2180 /// visitShiftByConstant - Handle transforms common to the three shifts, when
2181 /// the shift amount is a constant.
2182 SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
2183 SDNode *LHS = N->getOperand(0).Val;
2184 if (!LHS->hasOneUse()) return SDOperand();
2186 // We want to pull some binops through shifts, so that we have (and (shift))
2187 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
2188 // thing happens with address calculations, so it's important to canonicalize
2190 bool HighBitSet = false; // Can we transform this if the high bit is set?
2192 switch (LHS->getOpcode()) {
2193 default: return SDOperand();
2196 HighBitSet = false; // We can only transform sra if the high bit is clear.
2199 HighBitSet = true; // We can only transform sra if the high bit is set.
2202 if (N->getOpcode() != ISD::SHL)
2203 return SDOperand(); // only shl(add) not sr[al](add).
2204 HighBitSet = false; // We can only transform sra if the high bit is clear.
2208 // We require the RHS of the binop to be a constant as well.
2209 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
2210 if (!BinOpCst) return SDOperand();
2213 // FIXME: disable this for unless the input to the binop is a shift by a
2214 // constant. If it is not a shift, it pessimizes some common cases like:
2216 //void foo(int *X, int i) { X[i & 1235] = 1; }
2217 //int bar(int *X, int i) { return X[i & 255]; }
2218 SDNode *BinOpLHSVal = LHS->getOperand(0).Val;
2219 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
2220 BinOpLHSVal->getOpcode() != ISD::SRA &&
2221 BinOpLHSVal->getOpcode() != ISD::SRL) ||
2222 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
2225 MVT::ValueType VT = N->getValueType(0);
2227 // If this is a signed shift right, and the high bit is modified
2228 // by the logical operation, do not perform the transformation.
2229 // The highBitSet boolean indicates the value of the high bit of
2230 // the constant which would cause it to be modified for this
2232 if (N->getOpcode() == ISD::SRA) {
2233 uint64_t BinOpRHSSign = BinOpCst->getValue() >> MVT::getSizeInBits(VT)-1;
2234 if ((bool)BinOpRHSSign != HighBitSet)
2238 // Fold the constants, shifting the binop RHS by the shift amount.
2239 SDOperand NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0),
2240 LHS->getOperand(1), N->getOperand(1));
2242 // Create the new shift.
2243 SDOperand NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0),
2246 // Create the new binop.
2247 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS);
2251 SDOperand DAGCombiner::visitSHL(SDNode *N) {
2252 SDOperand N0 = N->getOperand(0);
2253 SDOperand N1 = N->getOperand(1);
2254 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2255 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2256 MVT::ValueType VT = N0.getValueType();
2257 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2259 // fold (shl c1, c2) -> c1<<c2
2261 return DAG.getNode(ISD::SHL, VT, N0, N1);
2262 // fold (shl 0, x) -> 0
2263 if (N0C && N0C->isNullValue())
2265 // fold (shl x, c >= size(x)) -> undef
2266 if (N1C && N1C->getValue() >= OpSizeInBits)
2267 return DAG.getNode(ISD::UNDEF, VT);
2268 // fold (shl x, 0) -> x
2269 if (N1C && N1C->isNullValue())
2271 // if (shl x, c) is known to be zero, return 0
2272 if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
2273 return DAG.getConstant(0, VT);
2274 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2275 return SDOperand(N, 0);
2276 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
2277 if (N1C && N0.getOpcode() == ISD::SHL &&
2278 N0.getOperand(1).getOpcode() == ISD::Constant) {
2279 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2280 uint64_t c2 = N1C->getValue();
2281 if (c1 + c2 > OpSizeInBits)
2282 return DAG.getConstant(0, VT);
2283 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
2284 DAG.getConstant(c1 + c2, N1.getValueType()));
2286 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
2287 // (srl (and x, -1 << c1), c1-c2)
2288 if (N1C && N0.getOpcode() == ISD::SRL &&
2289 N0.getOperand(1).getOpcode() == ISD::Constant) {
2290 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2291 uint64_t c2 = N1C->getValue();
2292 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2293 DAG.getConstant(~0ULL << c1, VT));
2295 return DAG.getNode(ISD::SHL, VT, Mask,
2296 DAG.getConstant(c2-c1, N1.getValueType()));
2298 return DAG.getNode(ISD::SRL, VT, Mask,
2299 DAG.getConstant(c1-c2, N1.getValueType()));
2301 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
2302 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
2303 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2304 DAG.getConstant(~0ULL << N1C->getValue(), VT));
2306 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand();
2309 SDOperand DAGCombiner::visitSRA(SDNode *N) {
2310 SDOperand N0 = N->getOperand(0);
2311 SDOperand N1 = N->getOperand(1);
2312 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2313 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2314 MVT::ValueType VT = N0.getValueType();
2316 // fold (sra c1, c2) -> c1>>c2
2318 return DAG.getNode(ISD::SRA, VT, N0, N1);
2319 // fold (sra 0, x) -> 0
2320 if (N0C && N0C->isNullValue())
2322 // fold (sra -1, x) -> -1
2323 if (N0C && N0C->isAllOnesValue())
2325 // fold (sra x, c >= size(x)) -> undef
2326 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
2327 return DAG.getNode(ISD::UNDEF, VT);
2328 // fold (sra x, 0) -> x
2329 if (N1C && N1C->isNullValue())
2331 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2333 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2334 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
2337 default: EVT = MVT::Other; break;
2338 case 1: EVT = MVT::i1; break;
2339 case 8: EVT = MVT::i8; break;
2340 case 16: EVT = MVT::i16; break;
2341 case 32: EVT = MVT::i32; break;
2343 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
2344 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
2345 DAG.getValueType(EVT));
2348 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
2349 if (N1C && N0.getOpcode() == ISD::SRA) {
2350 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2351 unsigned Sum = N1C->getValue() + C1->getValue();
2352 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
2353 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
2354 DAG.getConstant(Sum, N1C->getValueType(0)));
2358 // Simplify, based on bits shifted out of the LHS.
2359 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2360 return SDOperand(N, 0);
2363 // If the sign bit is known to be zero, switch this to a SRL.
2364 if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
2365 return DAG.getNode(ISD::SRL, VT, N0, N1);
2367 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand();
2370 SDOperand DAGCombiner::visitSRL(SDNode *N) {
2371 SDOperand N0 = N->getOperand(0);
2372 SDOperand N1 = N->getOperand(1);
2373 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2374 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2375 MVT::ValueType VT = N0.getValueType();
2376 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2378 // fold (srl c1, c2) -> c1 >>u c2
2380 return DAG.getNode(ISD::SRL, VT, N0, N1);
2381 // fold (srl 0, x) -> 0
2382 if (N0C && N0C->isNullValue())
2384 // fold (srl x, c >= size(x)) -> undef
2385 if (N1C && N1C->getValue() >= OpSizeInBits)
2386 return DAG.getNode(ISD::UNDEF, VT);
2387 // fold (srl x, 0) -> x
2388 if (N1C && N1C->isNullValue())
2390 // if (srl x, c) is known to be zero, return 0
2391 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
2392 return DAG.getConstant(0, VT);
2394 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
2395 if (N1C && N0.getOpcode() == ISD::SRL &&
2396 N0.getOperand(1).getOpcode() == ISD::Constant) {
2397 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2398 uint64_t c2 = N1C->getValue();
2399 if (c1 + c2 > OpSizeInBits)
2400 return DAG.getConstant(0, VT);
2401 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
2402 DAG.getConstant(c1 + c2, N1.getValueType()));
2405 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
2406 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2407 // Shifting in all undef bits?
2408 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
2409 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
2410 return DAG.getNode(ISD::UNDEF, VT);
2412 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
2413 AddToWorkList(SmallShift.Val);
2414 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
2417 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
2418 // bit, which is unmodified by sra.
2419 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
2420 if (N0.getOpcode() == ISD::SRA)
2421 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
2424 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
2425 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2426 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
2427 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
2428 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
2430 // If any of the input bits are KnownOne, then the input couldn't be all
2431 // zeros, thus the result of the srl will always be zero.
2432 if (KnownOne) return DAG.getConstant(0, VT);
2434 // If all of the bits input the to ctlz node are known to be zero, then
2435 // the result of the ctlz is "32" and the result of the shift is one.
2436 uint64_t UnknownBits = ~KnownZero & Mask;
2437 if (UnknownBits == 0) return DAG.getConstant(1, VT);
2439 // Otherwise, check to see if there is exactly one bit input to the ctlz.
2440 if ((UnknownBits & (UnknownBits-1)) == 0) {
2441 // Okay, we know that only that the single bit specified by UnknownBits
2442 // could be set on input to the CTLZ node. If this bit is set, the SRL
2443 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
2444 // to an SRL,XOR pair, which is likely to simplify more.
2445 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
2446 SDOperand Op = N0.getOperand(0);
2448 Op = DAG.getNode(ISD::SRL, VT, Op,
2449 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
2450 AddToWorkList(Op.Val);
2452 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
2456 // fold operands of srl based on knowledge that the low bits are not
2458 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2459 return SDOperand(N, 0);
2461 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand();
2464 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
2465 SDOperand N0 = N->getOperand(0);
2466 MVT::ValueType VT = N->getValueType(0);
2468 // fold (ctlz c1) -> c2
2469 if (isa<ConstantSDNode>(N0))
2470 return DAG.getNode(ISD::CTLZ, VT, N0);
2474 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
2475 SDOperand N0 = N->getOperand(0);
2476 MVT::ValueType VT = N->getValueType(0);
2478 // fold (cttz c1) -> c2
2479 if (isa<ConstantSDNode>(N0))
2480 return DAG.getNode(ISD::CTTZ, VT, N0);
2484 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
2485 SDOperand N0 = N->getOperand(0);
2486 MVT::ValueType VT = N->getValueType(0);
2488 // fold (ctpop c1) -> c2
2489 if (isa<ConstantSDNode>(N0))
2490 return DAG.getNode(ISD::CTPOP, VT, N0);
2494 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
2495 SDOperand N0 = N->getOperand(0);
2496 SDOperand N1 = N->getOperand(1);
2497 SDOperand N2 = N->getOperand(2);
2498 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2499 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2500 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2501 MVT::ValueType VT = N->getValueType(0);
2502 MVT::ValueType VT0 = N0.getValueType();
2504 // fold select C, X, X -> X
2507 // fold select true, X, Y -> X
2508 if (N0C && !N0C->isNullValue())
2510 // fold select false, X, Y -> Y
2511 if (N0C && N0C->isNullValue())
2513 // fold select C, 1, X -> C | X
2514 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
2515 return DAG.getNode(ISD::OR, VT, N0, N2);
2516 // fold select C, 0, 1 -> ~C
2517 if (MVT::isInteger(VT) && MVT::isInteger(VT0) &&
2518 N1C && N2C && N1C->isNullValue() && N2C->getValue() == 1) {
2519 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0));
2522 AddToWorkList(XORNode.Val);
2523 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0))
2524 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
2525 return DAG.getNode(ISD::TRUNCATE, VT, XORNode);
2527 // fold select C, 0, X -> ~C & X
2528 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
2529 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2530 AddToWorkList(XORNode.Val);
2531 return DAG.getNode(ISD::AND, VT, XORNode, N2);
2533 // fold select C, X, 1 -> ~C | X
2534 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getValue() == 1) {
2535 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2536 AddToWorkList(XORNode.Val);
2537 return DAG.getNode(ISD::OR, VT, XORNode, N1);
2539 // fold select C, X, 0 -> C & X
2540 // FIXME: this should check for C type == X type, not i1?
2541 if (MVT::i1 == VT && N2C && N2C->isNullValue())
2542 return DAG.getNode(ISD::AND, VT, N0, N1);
2543 // fold X ? X : Y --> X ? 1 : Y --> X | Y
2544 if (MVT::i1 == VT && N0 == N1)
2545 return DAG.getNode(ISD::OR, VT, N0, N2);
2546 // fold X ? Y : X --> X ? Y : 0 --> X & Y
2547 if (MVT::i1 == VT && N0 == N2)
2548 return DAG.getNode(ISD::AND, VT, N0, N1);
2550 // If we can fold this based on the true/false value, do so.
2551 if (SimplifySelectOps(N, N1, N2))
2552 return SDOperand(N, 0); // Don't revisit N.
2554 // fold selects based on a setcc into other things, such as min/max/abs
2555 if (N0.getOpcode() == ISD::SETCC)
2557 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
2558 // having to say they don't support SELECT_CC on every type the DAG knows
2559 // about, since there is no way to mark an opcode illegal at all value types
2560 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
2561 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
2562 N1, N2, N0.getOperand(2));
2564 return SimplifySelect(N0, N1, N2);
2568 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
2569 SDOperand N0 = N->getOperand(0);
2570 SDOperand N1 = N->getOperand(1);
2571 SDOperand N2 = N->getOperand(2);
2572 SDOperand N3 = N->getOperand(3);
2573 SDOperand N4 = N->getOperand(4);
2574 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
2576 // fold select_cc lhs, rhs, x, x, cc -> x
2580 // Determine if the condition we're dealing with is constant
2581 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
2582 if (SCC.Val) AddToWorkList(SCC.Val);
2584 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
2585 if (SCCC->getValue())
2586 return N2; // cond always true -> true val
2588 return N3; // cond always false -> false val
2591 // Fold to a simpler select_cc
2592 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
2593 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
2594 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
2597 // If we can fold this based on the true/false value, do so.
2598 if (SimplifySelectOps(N, N2, N3))
2599 return SDOperand(N, 0); // Don't revisit N.
2601 // fold select_cc into other things, such as min/max/abs
2602 return SimplifySelectCC(N0, N1, N2, N3, CC);
2605 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
2606 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
2607 cast<CondCodeSDNode>(N->getOperand(2))->get());
2610 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
2611 // "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))"
2612 // transformation. Returns true if extension are possible and the above
2613 // mentioned transformation is profitable.
2614 static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0,
2616 SmallVector<SDNode*, 4> &ExtendNodes,
2617 TargetLowering &TLI) {
2618 bool HasCopyToRegUses = false;
2619 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
2620 for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end();
2625 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
2626 if (User->getOpcode() == ISD::SETCC) {
2627 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
2628 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
2629 // Sign bits will be lost after a zext.
2632 for (unsigned i = 0; i != 2; ++i) {
2633 SDOperand UseOp = User->getOperand(i);
2636 if (!isa<ConstantSDNode>(UseOp))
2641 ExtendNodes.push_back(User);
2643 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2644 SDOperand UseOp = User->getOperand(i);
2646 // If truncate from extended type to original load type is free
2647 // on this target, then it's ok to extend a CopyToReg.
2648 if (isTruncFree && User->getOpcode() == ISD::CopyToReg)
2649 HasCopyToRegUses = true;
2657 if (HasCopyToRegUses) {
2658 bool BothLiveOut = false;
2659 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
2662 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2663 SDOperand UseOp = User->getOperand(i);
2664 if (UseOp.Val == N && UseOp.ResNo == 0) {
2671 // Both unextended and extended values are live out. There had better be
2672 // good a reason for the transformation.
2673 return ExtendNodes.size();
2678 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
2679 SDOperand N0 = N->getOperand(0);
2680 MVT::ValueType VT = N->getValueType(0);
2682 // fold (sext c1) -> c1
2683 if (isa<ConstantSDNode>(N0))
2684 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
2686 // fold (sext (sext x)) -> (sext x)
2687 // fold (sext (aext x)) -> (sext x)
2688 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2689 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
2691 // fold (sext (truncate (load x))) -> (sext (smaller load x))
2692 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
2693 if (N0.getOpcode() == ISD::TRUNCATE) {
2694 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2695 if (NarrowLoad.Val) {
2696 if (NarrowLoad.Val != N0.Val)
2697 CombineTo(N0.Val, NarrowLoad);
2698 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad);
2702 // See if the value being truncated is already sign extended. If so, just
2703 // eliminate the trunc/sext pair.
2704 if (N0.getOpcode() == ISD::TRUNCATE) {
2705 SDOperand Op = N0.getOperand(0);
2706 unsigned OpBits = MVT::getSizeInBits(Op.getValueType());
2707 unsigned MidBits = MVT::getSizeInBits(N0.getValueType());
2708 unsigned DestBits = MVT::getSizeInBits(VT);
2709 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
2711 if (OpBits == DestBits) {
2712 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
2713 // bits, it is already ready.
2714 if (NumSignBits > DestBits-MidBits)
2716 } else if (OpBits < DestBits) {
2717 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
2718 // bits, just sext from i32.
2719 if (NumSignBits > OpBits-MidBits)
2720 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op);
2722 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
2723 // bits, just truncate to i32.
2724 if (NumSignBits > OpBits-MidBits)
2725 return DAG.getNode(ISD::TRUNCATE, VT, Op);
2728 // fold (sext (truncate x)) -> (sextinreg x).
2729 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
2730 N0.getValueType())) {
2731 if (Op.getValueType() < VT)
2732 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2733 else if (Op.getValueType() > VT)
2734 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2735 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
2736 DAG.getValueType(N0.getValueType()));
2740 // fold (sext (load x)) -> (sext (truncate (sextload x)))
2741 if (ISD::isNON_EXTLoad(N0.Val) &&
2742 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
2743 bool DoXform = true;
2744 SmallVector<SDNode*, 4> SetCCs;
2745 if (!N0.hasOneUse())
2746 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
2748 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2749 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2750 LN0->getBasePtr(), LN0->getSrcValue(),
2751 LN0->getSrcValueOffset(),
2754 LN0->getAlignment());
2755 CombineTo(N, ExtLoad);
2756 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
2757 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
2758 // Extend SetCC uses if necessary.
2759 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
2760 SDNode *SetCC = SetCCs[i];
2761 SmallVector<SDOperand, 4> Ops;
2762 for (unsigned j = 0; j != 2; ++j) {
2763 SDOperand SOp = SetCC->getOperand(j);
2765 Ops.push_back(ExtLoad);
2767 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp));
2769 Ops.push_back(SetCC->getOperand(2));
2770 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0),
2771 &Ops[0], Ops.size()));
2773 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2777 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
2778 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
2779 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2780 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2781 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2782 MVT::ValueType EVT = LN0->getMemoryVT();
2783 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
2784 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2785 LN0->getBasePtr(), LN0->getSrcValue(),
2786 LN0->getSrcValueOffset(), EVT,
2788 LN0->getAlignment());
2789 CombineTo(N, ExtLoad);
2790 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2791 ExtLoad.getValue(1));
2792 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2796 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc
2797 if (N0.getOpcode() == ISD::SETCC) {
2799 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2800 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
2801 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2802 if (SCC.Val) return SCC;
2808 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
2809 SDOperand N0 = N->getOperand(0);
2810 MVT::ValueType VT = N->getValueType(0);
2812 // fold (zext c1) -> c1
2813 if (isa<ConstantSDNode>(N0))
2814 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2815 // fold (zext (zext x)) -> (zext x)
2816 // fold (zext (aext x)) -> (zext x)
2817 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2818 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
2820 // fold (zext (truncate (load x))) -> (zext (smaller load x))
2821 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
2822 if (N0.getOpcode() == ISD::TRUNCATE) {
2823 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2824 if (NarrowLoad.Val) {
2825 if (NarrowLoad.Val != N0.Val)
2826 CombineTo(N0.Val, NarrowLoad);
2827 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad);
2831 // fold (zext (truncate x)) -> (and x, mask)
2832 if (N0.getOpcode() == ISD::TRUNCATE &&
2833 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
2834 SDOperand Op = N0.getOperand(0);
2835 if (Op.getValueType() < VT) {
2836 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2837 } else if (Op.getValueType() > VT) {
2838 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2840 return DAG.getZeroExtendInReg(Op, N0.getValueType());
2843 // fold (zext (and (trunc x), cst)) -> (and x, cst).
2844 if (N0.getOpcode() == ISD::AND &&
2845 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2846 N0.getOperand(1).getOpcode() == ISD::Constant) {
2847 SDOperand X = N0.getOperand(0).getOperand(0);
2848 if (X.getValueType() < VT) {
2849 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2850 } else if (X.getValueType() > VT) {
2851 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2853 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2854 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2857 // fold (zext (load x)) -> (zext (truncate (zextload x)))
2858 if (ISD::isNON_EXTLoad(N0.Val) &&
2859 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
2860 bool DoXform = true;
2861 SmallVector<SDNode*, 4> SetCCs;
2862 if (!N0.hasOneUse())
2863 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
2865 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2866 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2867 LN0->getBasePtr(), LN0->getSrcValue(),
2868 LN0->getSrcValueOffset(),
2871 LN0->getAlignment());
2872 CombineTo(N, ExtLoad);
2873 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
2874 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
2875 // Extend SetCC uses if necessary.
2876 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
2877 SDNode *SetCC = SetCCs[i];
2878 SmallVector<SDOperand, 4> Ops;
2879 for (unsigned j = 0; j != 2; ++j) {
2880 SDOperand SOp = SetCC->getOperand(j);
2882 Ops.push_back(ExtLoad);
2884 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp));
2886 Ops.push_back(SetCC->getOperand(2));
2887 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0),
2888 &Ops[0], Ops.size()));
2890 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2894 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
2895 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
2896 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2897 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2898 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2899 MVT::ValueType EVT = LN0->getMemoryVT();
2900 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2901 LN0->getBasePtr(), LN0->getSrcValue(),
2902 LN0->getSrcValueOffset(), EVT,
2904 LN0->getAlignment());
2905 CombineTo(N, ExtLoad);
2906 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2907 ExtLoad.getValue(1));
2908 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2911 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2912 if (N0.getOpcode() == ISD::SETCC) {
2914 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2915 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2916 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2917 if (SCC.Val) return SCC;
2923 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
2924 SDOperand N0 = N->getOperand(0);
2925 MVT::ValueType VT = N->getValueType(0);
2927 // fold (aext c1) -> c1
2928 if (isa<ConstantSDNode>(N0))
2929 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
2930 // fold (aext (aext x)) -> (aext x)
2931 // fold (aext (zext x)) -> (zext x)
2932 // fold (aext (sext x)) -> (sext x)
2933 if (N0.getOpcode() == ISD::ANY_EXTEND ||
2934 N0.getOpcode() == ISD::ZERO_EXTEND ||
2935 N0.getOpcode() == ISD::SIGN_EXTEND)
2936 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2938 // fold (aext (truncate (load x))) -> (aext (smaller load x))
2939 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
2940 if (N0.getOpcode() == ISD::TRUNCATE) {
2941 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2942 if (NarrowLoad.Val) {
2943 if (NarrowLoad.Val != N0.Val)
2944 CombineTo(N0.Val, NarrowLoad);
2945 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad);
2949 // fold (aext (truncate x))
2950 if (N0.getOpcode() == ISD::TRUNCATE) {
2951 SDOperand TruncOp = N0.getOperand(0);
2952 if (TruncOp.getValueType() == VT)
2953 return TruncOp; // x iff x size == zext size.
2954 if (TruncOp.getValueType() > VT)
2955 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
2956 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
2959 // fold (aext (and (trunc x), cst)) -> (and x, cst).
2960 if (N0.getOpcode() == ISD::AND &&
2961 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2962 N0.getOperand(1).getOpcode() == ISD::Constant) {
2963 SDOperand X = N0.getOperand(0).getOperand(0);
2964 if (X.getValueType() < VT) {
2965 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2966 } else if (X.getValueType() > VT) {
2967 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2969 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2970 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2973 // fold (aext (load x)) -> (aext (truncate (extload x)))
2974 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2975 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2976 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2977 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2978 LN0->getBasePtr(), LN0->getSrcValue(),
2979 LN0->getSrcValueOffset(),
2982 LN0->getAlignment());
2983 CombineTo(N, ExtLoad);
2984 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2985 ExtLoad.getValue(1));
2986 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2989 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2990 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2991 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2992 if (N0.getOpcode() == ISD::LOAD &&
2993 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
2995 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2996 MVT::ValueType EVT = LN0->getMemoryVT();
2997 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2998 LN0->getChain(), LN0->getBasePtr(),
3000 LN0->getSrcValueOffset(), EVT,
3002 LN0->getAlignment());
3003 CombineTo(N, ExtLoad);
3004 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
3005 ExtLoad.getValue(1));
3006 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3009 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3010 if (N0.getOpcode() == ISD::SETCC) {
3012 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
3013 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3014 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3022 /// GetDemandedBits - See if the specified operand can be simplified with the
3023 /// knowledge that only the bits specified by Mask are used. If so, return the
3024 /// simpler operand, otherwise return a null SDOperand.
3025 SDOperand DAGCombiner::GetDemandedBits(SDOperand V, uint64_t Mask) {
3026 switch (V.getOpcode()) {
3030 // If the LHS or RHS don't contribute bits to the or, drop them.
3031 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
3032 return V.getOperand(1);
3033 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
3034 return V.getOperand(0);
3037 // Only look at single-use SRLs.
3038 if (!V.Val->hasOneUse())
3040 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
3041 // See if we can recursively simplify the LHS.
3042 unsigned Amt = RHSC->getValue();
3043 Mask = (Mask << Amt) & MVT::getIntVTBitMask(V.getValueType());
3044 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), Mask);
3045 if (SimplifyLHS.Val) {
3046 return DAG.getNode(ISD::SRL, V.getValueType(),
3047 SimplifyLHS, V.getOperand(1));
3054 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
3055 /// bits and then truncated to a narrower type and where N is a multiple
3056 /// of number of bits of the narrower type, transform it to a narrower load
3057 /// from address + N / num of bits of new type. If the result is to be
3058 /// extended, also fold the extension to form a extending load.
3059 SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
3060 unsigned Opc = N->getOpcode();
3061 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
3062 SDOperand N0 = N->getOperand(0);
3063 MVT::ValueType VT = N->getValueType(0);
3064 MVT::ValueType EVT = N->getValueType(0);
3066 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
3068 if (Opc == ISD::SIGN_EXTEND_INREG) {
3069 ExtType = ISD::SEXTLOAD;
3070 EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3071 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))
3075 unsigned EVTBits = MVT::getSizeInBits(EVT);
3077 bool CombineSRL = false;
3078 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
3079 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3080 ShAmt = N01->getValue();
3081 // Is the shift amount a multiple of size of VT?
3082 if ((ShAmt & (EVTBits-1)) == 0) {
3083 N0 = N0.getOperand(0);
3084 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits)
3091 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
3092 // Do not allow folding to i1 here. i1 is implicitly stored in memory in
3093 // zero extended form: by shrinking the load, we lose track of the fact
3094 // that it is already zero extended.
3095 // FIXME: This should be reevaluated.
3097 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits &&
3098 "Cannot truncate to larger type!");
3099 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3100 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
3101 // For big endian targets, we need to adjust the offset to the pointer to
3102 // load the correct bytes.
3103 if (TLI.isBigEndian()) {
3104 unsigned LVTStoreBits = MVT::getStoreSizeInBits(N0.getValueType());
3105 unsigned EVTStoreBits = MVT::getStoreSizeInBits(EVT);
3106 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
3108 uint64_t PtrOff = ShAmt / 8;
3109 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
3110 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
3111 DAG.getConstant(PtrOff, PtrType));
3112 AddToWorkList(NewPtr.Val);
3113 SDOperand Load = (ExtType == ISD::NON_EXTLOAD)
3114 ? DAG.getLoad(VT, LN0->getChain(), NewPtr,
3115 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3116 LN0->isVolatile(), NewAlign)
3117 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr,
3118 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
3119 LN0->isVolatile(), NewAlign);
3122 WorkListRemover DeadNodes(*this);
3123 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
3125 CombineTo(N->getOperand(0).Val, Load);
3127 CombineTo(N0.Val, Load, Load.getValue(1));
3129 if (Opc == ISD::SIGN_EXTEND_INREG)
3130 return DAG.getNode(Opc, VT, Load, N->getOperand(1));
3132 return DAG.getNode(Opc, VT, Load);
3134 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3141 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
3142 SDOperand N0 = N->getOperand(0);
3143 SDOperand N1 = N->getOperand(1);
3144 MVT::ValueType VT = N->getValueType(0);
3145 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
3146 unsigned EVTBits = MVT::getSizeInBits(EVT);
3148 // fold (sext_in_reg c1) -> c1
3149 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
3150 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
3152 // If the input is already sign extended, just drop the extension.
3153 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
3156 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
3157 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3158 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
3159 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
3162 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
3163 if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
3164 return DAG.getZeroExtendInReg(N0, EVT);
3166 // fold operands of sext_in_reg based on knowledge that the top bits are not
3168 if (SimplifyDemandedBits(SDOperand(N, 0)))
3169 return SDOperand(N, 0);
3171 // fold (sext_in_reg (load x)) -> (smaller sextload x)
3172 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
3173 SDOperand NarrowLoad = ReduceLoadWidth(N);
3177 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
3178 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
3179 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
3180 if (N0.getOpcode() == ISD::SRL) {
3181 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
3182 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
3183 // We can turn this into an SRA iff the input to the SRL is already sign
3185 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
3186 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
3187 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
3191 // fold (sext_inreg (extload x)) -> (sextload x)
3192 if (ISD::isEXTLoad(N0.Val) &&
3193 ISD::isUNINDEXEDLoad(N0.Val) &&
3194 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3195 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
3196 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3197 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
3198 LN0->getBasePtr(), LN0->getSrcValue(),
3199 LN0->getSrcValueOffset(), EVT,
3201 LN0->getAlignment());
3202 CombineTo(N, ExtLoad);
3203 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
3204 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3206 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
3207 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
3209 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3210 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
3211 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3212 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
3213 LN0->getBasePtr(), LN0->getSrcValue(),
3214 LN0->getSrcValueOffset(), EVT,
3216 LN0->getAlignment());
3217 CombineTo(N, ExtLoad);
3218 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
3219 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3224 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
3225 SDOperand N0 = N->getOperand(0);
3226 MVT::ValueType VT = N->getValueType(0);
3229 if (N0.getValueType() == N->getValueType(0))
3231 // fold (truncate c1) -> c1
3232 if (isa<ConstantSDNode>(N0))
3233 return DAG.getNode(ISD::TRUNCATE, VT, N0);
3234 // fold (truncate (truncate x)) -> (truncate x)
3235 if (N0.getOpcode() == ISD::TRUNCATE)
3236 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
3237 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
3238 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
3239 N0.getOpcode() == ISD::ANY_EXTEND) {
3240 if (N0.getOperand(0).getValueType() < VT)
3241 // if the source is smaller than the dest, we still need an extend
3242 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
3243 else if (N0.getOperand(0).getValueType() > VT)
3244 // if the source is larger than the dest, than we just need the truncate
3245 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
3247 // if the source and dest are the same type, we can drop both the extend
3249 return N0.getOperand(0);
3252 // See if we can simplify the input to this truncate through knowledge that
3253 // only the low bits are being used. For example "trunc (or (shl x, 8), y)"
3255 SDOperand Shorter = GetDemandedBits(N0, MVT::getIntVTBitMask(VT));
3257 return DAG.getNode(ISD::TRUNCATE, VT, Shorter);
3259 // fold (truncate (load x)) -> (smaller load x)
3260 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
3261 return ReduceLoadWidth(N);
3264 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
3265 SDOperand N0 = N->getOperand(0);
3266 MVT::ValueType VT = N->getValueType(0);
3268 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
3269 // Only do this before legalize, since afterward the target may be depending
3270 // on the bitconvert.
3271 // First check to see if this is all constant.
3272 if (!AfterLegalize &&
3273 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() &&
3274 MVT::isVector(VT)) {
3275 bool isSimple = true;
3276 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
3277 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
3278 N0.getOperand(i).getOpcode() != ISD::Constant &&
3279 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
3284 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0));
3285 assert(!MVT::isVector(DestEltVT) &&
3286 "Element type of vector ValueType must not be vector!");
3288 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT);
3292 // If the input is a constant, let getNode() fold it.
3293 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
3294 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
3295 if (Res.Val != N) return Res;
3298 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
3299 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
3301 // fold (conv (load x)) -> (load (conv*)x)
3302 // If the resultant load doesn't need a higher alignment than the original!
3303 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() &&
3304 TLI.isOperationLegal(ISD::LOAD, VT)) {
3305 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3306 unsigned Align = TLI.getTargetMachine().getTargetData()->
3307 getABITypeAlignment(MVT::getTypeForValueType(VT));
3308 unsigned OrigAlign = LN0->getAlignment();
3309 if (Align <= OrigAlign) {
3310 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
3311 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3312 LN0->isVolatile(), Align);
3314 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
3320 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit)
3321 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit)
3322 // This often reduces constant pool loads.
3323 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
3324 N0.Val->hasOneUse() && MVT::isInteger(VT) && !MVT::isVector(VT)) {
3325 SDOperand NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
3326 AddToWorkList(NewConv.Val);
3328 uint64_t SignBit = MVT::getIntVTSignBit(VT);
3329 if (N0.getOpcode() == ISD::FNEG)
3330 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT));
3331 assert(N0.getOpcode() == ISD::FABS);
3332 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT));
3335 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign'
3336 // Note that we don't handle copysign(x,cst) because this can always be folded
3337 // to an fneg or fabs.
3338 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse() &&
3339 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
3340 MVT::isInteger(VT) && !MVT::isVector(VT)) {
3341 unsigned OrigXWidth = MVT::getSizeInBits(N0.getOperand(1).getValueType());
3342 SDOperand X = DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerType(OrigXWidth),
3344 AddToWorkList(X.Val);
3346 // If X has a different width than the result/lhs, sext it or truncate it.
3347 unsigned VTWidth = MVT::getSizeInBits(VT);
3348 if (OrigXWidth < VTWidth) {
3349 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X);
3350 AddToWorkList(X.Val);
3351 } else if (OrigXWidth > VTWidth) {
3352 // To get the sign bit in the right place, we have to shift it right
3353 // before truncating.
3354 X = DAG.getNode(ISD::SRL, X.getValueType(), X,
3355 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
3356 AddToWorkList(X.Val);
3357 X = DAG.getNode(ISD::TRUNCATE, VT, X);
3358 AddToWorkList(X.Val);
3361 uint64_t SignBit = MVT::getIntVTSignBit(VT);
3362 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT));
3363 AddToWorkList(X.Val);
3365 SDOperand Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
3366 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT));
3367 AddToWorkList(Cst.Val);
3369 return DAG.getNode(ISD::OR, VT, X, Cst);
3375 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
3376 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
3377 /// destination element value type.
3378 SDOperand DAGCombiner::
3379 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
3380 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
3382 // If this is already the right type, we're done.
3383 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
3385 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
3386 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
3388 // If this is a conversion of N elements of one type to N elements of another
3389 // type, convert each element. This handles FP<->INT cases.
3390 if (SrcBitSize == DstBitSize) {
3391 SmallVector<SDOperand, 8> Ops;
3392 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3393 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
3394 AddToWorkList(Ops.back().Val);
3397 MVT::getVectorType(DstEltVT,
3398 MVT::getVectorNumElements(BV->getValueType(0)));
3399 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3402 // Otherwise, we're growing or shrinking the elements. To avoid having to
3403 // handle annoying details of growing/shrinking FP values, we convert them to
3405 if (MVT::isFloatingPoint(SrcEltVT)) {
3406 // Convert the input float vector to a int vector where the elements are the
3408 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
3409 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
3410 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val;
3414 // Now we know the input is an integer vector. If the output is a FP type,
3415 // convert to integer first, then to FP of the right size.
3416 if (MVT::isFloatingPoint(DstEltVT)) {
3417 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
3418 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
3419 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val;
3421 // Next, convert to FP elements of the same size.
3422 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
3425 // Okay, we know the src/dst types are both integers of differing types.
3426 // Handling growing first.
3427 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
3428 if (SrcBitSize < DstBitSize) {
3429 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
3431 SmallVector<SDOperand, 8> Ops;
3432 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
3433 i += NumInputsPerOutput) {
3434 bool isLE = TLI.isLittleEndian();
3435 uint64_t NewBits = 0;
3436 bool EltIsUndef = true;
3437 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
3438 // Shift the previously computed bits over.
3439 NewBits <<= SrcBitSize;
3440 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
3441 if (Op.getOpcode() == ISD::UNDEF) continue;
3444 NewBits |= cast<ConstantSDNode>(Op)->getValue();
3448 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3450 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
3453 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size());
3454 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3457 // Finally, this must be the case where we are shrinking elements: each input
3458 // turns into multiple outputs.
3459 bool isS2V = ISD::isScalarToVector(BV);
3460 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
3461 MVT::ValueType VT = MVT::getVectorType(DstEltVT,
3462 NumOutputsPerInput * BV->getNumOperands());
3463 SmallVector<SDOperand, 8> Ops;
3464 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3465 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
3466 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
3467 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3470 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
3471 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
3472 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
3473 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
3474 if (isS2V && i == 0 && j == 0 && ThisVal == OpVal)
3475 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
3476 return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]);
3477 OpVal >>= DstBitSize;
3480 // For big endian targets, swap the order of the pieces of each element.
3481 if (TLI.isBigEndian())
3482 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
3484 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3489 SDOperand DAGCombiner::visitFADD(SDNode *N) {
3490 SDOperand N0 = N->getOperand(0);
3491 SDOperand N1 = N->getOperand(1);
3492 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3493 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3494 MVT::ValueType VT = N->getValueType(0);
3497 if (MVT::isVector(VT)) {
3498 SDOperand FoldedVOp = SimplifyVBinOp(N);
3499 if (FoldedVOp.Val) return FoldedVOp;
3502 // fold (fadd c1, c2) -> c1+c2
3503 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3504 return DAG.getNode(ISD::FADD, VT, N0, N1);
3505 // canonicalize constant to RHS
3506 if (N0CFP && !N1CFP)
3507 return DAG.getNode(ISD::FADD, VT, N1, N0);
3508 // fold (A + (-B)) -> A-B
3509 if (isNegatibleForFree(N1) == 2)
3510 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG));
3511 // fold ((-A) + B) -> B-A
3512 if (isNegatibleForFree(N0) == 2)
3513 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG));
3515 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
3516 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
3517 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3518 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
3519 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1));
3524 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
3525 SDOperand N0 = N->getOperand(0);
3526 SDOperand N1 = N->getOperand(1);
3527 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3528 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3529 MVT::ValueType VT = N->getValueType(0);
3532 if (MVT::isVector(VT)) {
3533 SDOperand FoldedVOp = SimplifyVBinOp(N);
3534 if (FoldedVOp.Val) return FoldedVOp;
3537 // fold (fsub c1, c2) -> c1-c2
3538 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3539 return DAG.getNode(ISD::FSUB, VT, N0, N1);
3541 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
3542 if (isNegatibleForFree(N1))
3543 return GetNegatedExpression(N1, DAG);
3544 return DAG.getNode(ISD::FNEG, VT, N1);
3546 // fold (A-(-B)) -> A+B
3547 if (isNegatibleForFree(N1))
3548 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG));
3553 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
3554 SDOperand N0 = N->getOperand(0);
3555 SDOperand N1 = N->getOperand(1);
3556 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3557 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3558 MVT::ValueType VT = N->getValueType(0);
3561 if (MVT::isVector(VT)) {
3562 SDOperand FoldedVOp = SimplifyVBinOp(N);
3563 if (FoldedVOp.Val) return FoldedVOp;
3566 // fold (fmul c1, c2) -> c1*c2
3567 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3568 return DAG.getNode(ISD::FMUL, VT, N0, N1);
3569 // canonicalize constant to RHS
3570 if (N0CFP && !N1CFP)
3571 return DAG.getNode(ISD::FMUL, VT, N1, N0);
3572 // fold (fmul X, 2.0) -> (fadd X, X)
3573 if (N1CFP && N1CFP->isExactlyValue(+2.0))
3574 return DAG.getNode(ISD::FADD, VT, N0, N0);
3575 // fold (fmul X, -1.0) -> (fneg X)
3576 if (N1CFP && N1CFP->isExactlyValue(-1.0))
3577 return DAG.getNode(ISD::FNEG, VT, N0);
3580 if (char LHSNeg = isNegatibleForFree(N0)) {
3581 if (char RHSNeg = isNegatibleForFree(N1)) {
3582 // Both can be negated for free, check to see if at least one is cheaper
3584 if (LHSNeg == 2 || RHSNeg == 2)
3585 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG),
3586 GetNegatedExpression(N1, DAG));
3590 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
3591 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
3592 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3593 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
3594 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1));
3599 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
3600 SDOperand N0 = N->getOperand(0);
3601 SDOperand N1 = N->getOperand(1);
3602 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3603 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3604 MVT::ValueType VT = N->getValueType(0);
3607 if (MVT::isVector(VT)) {
3608 SDOperand FoldedVOp = SimplifyVBinOp(N);
3609 if (FoldedVOp.Val) return FoldedVOp;
3612 // fold (fdiv c1, c2) -> c1/c2
3613 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3614 return DAG.getNode(ISD::FDIV, VT, N0, N1);
3618 if (char LHSNeg = isNegatibleForFree(N0)) {
3619 if (char RHSNeg = isNegatibleForFree(N1)) {
3620 // Both can be negated for free, check to see if at least one is cheaper
3622 if (LHSNeg == 2 || RHSNeg == 2)
3623 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG),
3624 GetNegatedExpression(N1, DAG));
3631 SDOperand DAGCombiner::visitFREM(SDNode *N) {
3632 SDOperand N0 = N->getOperand(0);
3633 SDOperand N1 = N->getOperand(1);
3634 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3635 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3636 MVT::ValueType VT = N->getValueType(0);
3638 // fold (frem c1, c2) -> fmod(c1,c2)
3639 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3640 return DAG.getNode(ISD::FREM, VT, N0, N1);
3645 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
3646 SDOperand N0 = N->getOperand(0);
3647 SDOperand N1 = N->getOperand(1);
3648 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3649 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3650 MVT::ValueType VT = N->getValueType(0);
3652 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
3653 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
3656 const APFloat& V = N1CFP->getValueAPF();
3657 // copysign(x, c1) -> fabs(x) iff ispos(c1)
3658 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
3659 if (!V.isNegative())
3660 return DAG.getNode(ISD::FABS, VT, N0);
3662 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
3665 // copysign(fabs(x), y) -> copysign(x, y)
3666 // copysign(fneg(x), y) -> copysign(x, y)
3667 // copysign(copysign(x,z), y) -> copysign(x, y)
3668 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
3669 N0.getOpcode() == ISD::FCOPYSIGN)
3670 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
3672 // copysign(x, abs(y)) -> abs(x)
3673 if (N1.getOpcode() == ISD::FABS)
3674 return DAG.getNode(ISD::FABS, VT, N0);
3676 // copysign(x, copysign(y,z)) -> copysign(x, z)
3677 if (N1.getOpcode() == ISD::FCOPYSIGN)
3678 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
3680 // copysign(x, fp_extend(y)) -> copysign(x, y)
3681 // copysign(x, fp_round(y)) -> copysign(x, y)
3682 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
3683 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
3690 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
3691 SDOperand N0 = N->getOperand(0);
3692 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3693 MVT::ValueType VT = N->getValueType(0);
3695 // fold (sint_to_fp c1) -> c1fp
3696 if (N0C && N0.getValueType() != MVT::ppcf128)
3697 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
3701 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
3702 SDOperand N0 = N->getOperand(0);
3703 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3704 MVT::ValueType VT = N->getValueType(0);
3706 // fold (uint_to_fp c1) -> c1fp
3707 if (N0C && N0.getValueType() != MVT::ppcf128)
3708 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
3712 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
3713 SDOperand N0 = N->getOperand(0);
3714 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3715 MVT::ValueType VT = N->getValueType(0);
3717 // fold (fp_to_sint c1fp) -> c1
3719 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
3723 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
3724 SDOperand N0 = N->getOperand(0);
3725 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3726 MVT::ValueType VT = N->getValueType(0);
3728 // fold (fp_to_uint c1fp) -> c1
3729 if (N0CFP && VT != MVT::ppcf128)
3730 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
3734 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
3735 SDOperand N0 = N->getOperand(0);
3736 SDOperand N1 = N->getOperand(1);
3737 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3738 MVT::ValueType VT = N->getValueType(0);
3740 // fold (fp_round c1fp) -> c1fp
3741 if (N0CFP && N0.getValueType() != MVT::ppcf128)
3742 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1);
3744 // fold (fp_round (fp_extend x)) -> x
3745 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
3746 return N0.getOperand(0);
3748 // fold (fp_round (fp_round x)) -> (fp_round x)
3749 if (N0.getOpcode() == ISD::FP_ROUND) {
3750 // This is a value preserving truncation if both round's are.
3751 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
3752 N0.Val->getConstantOperandVal(1) == 1;
3753 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0),
3754 DAG.getIntPtrConstant(IsTrunc));
3757 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
3758 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
3759 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1);
3760 AddToWorkList(Tmp.Val);
3761 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
3767 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
3768 SDOperand N0 = N->getOperand(0);
3769 MVT::ValueType VT = N->getValueType(0);
3770 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3771 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3773 // fold (fp_round_inreg c1fp) -> c1fp
3775 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT);
3776 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
3781 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
3782 SDOperand N0 = N->getOperand(0);
3783 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3784 MVT::ValueType VT = N->getValueType(0);
3786 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
3787 if (N->hasOneUse() && (*N->use_begin())->getOpcode() == ISD::FP_ROUND)
3790 // fold (fp_extend c1fp) -> c1fp
3791 if (N0CFP && VT != MVT::ppcf128)
3792 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
3794 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
3796 if (N0.getOpcode() == ISD::FP_ROUND && N0.Val->getConstantOperandVal(1) == 1){
3797 SDOperand In = N0.getOperand(0);
3798 if (In.getValueType() == VT) return In;
3799 if (VT < In.getValueType())
3800 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1));
3801 return DAG.getNode(ISD::FP_EXTEND, VT, In);
3804 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
3805 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
3806 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
3807 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3808 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
3809 LN0->getBasePtr(), LN0->getSrcValue(),
3810 LN0->getSrcValueOffset(),
3813 LN0->getAlignment());
3814 CombineTo(N, ExtLoad);
3815 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad,
3816 DAG.getIntPtrConstant(1)),
3817 ExtLoad.getValue(1));
3818 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3825 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
3826 SDOperand N0 = N->getOperand(0);
3828 if (isNegatibleForFree(N0))
3829 return GetNegatedExpression(N0, DAG);
3831 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
3832 // constant pool values.
3833 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() &&
3834 MVT::isInteger(N0.getOperand(0).getValueType()) &&
3835 !MVT::isVector(N0.getOperand(0).getValueType())) {
3836 SDOperand Int = N0.getOperand(0);
3837 MVT::ValueType IntVT = Int.getValueType();
3838 if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) {
3839 Int = DAG.getNode(ISD::XOR, IntVT, Int,
3840 DAG.getConstant(MVT::getIntVTSignBit(IntVT), IntVT));
3841 AddToWorkList(Int.Val);
3842 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int);
3849 SDOperand DAGCombiner::visitFABS(SDNode *N) {
3850 SDOperand N0 = N->getOperand(0);
3851 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3852 MVT::ValueType VT = N->getValueType(0);
3854 // fold (fabs c1) -> fabs(c1)
3855 if (N0CFP && VT != MVT::ppcf128)
3856 return DAG.getNode(ISD::FABS, VT, N0);
3857 // fold (fabs (fabs x)) -> (fabs x)
3858 if (N0.getOpcode() == ISD::FABS)
3859 return N->getOperand(0);
3860 // fold (fabs (fneg x)) -> (fabs x)
3861 // fold (fabs (fcopysign x, y)) -> (fabs x)
3862 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
3863 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
3865 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
3866 // constant pool values.
3867 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() &&
3868 MVT::isInteger(N0.getOperand(0).getValueType()) &&
3869 !MVT::isVector(N0.getOperand(0).getValueType())) {
3870 SDOperand Int = N0.getOperand(0);
3871 MVT::ValueType IntVT = Int.getValueType();
3872 if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) {
3873 Int = DAG.getNode(ISD::AND, IntVT, Int,
3874 DAG.getConstant(~MVT::getIntVTSignBit(IntVT), IntVT));
3875 AddToWorkList(Int.Val);
3876 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int);
3883 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
3884 SDOperand Chain = N->getOperand(0);
3885 SDOperand N1 = N->getOperand(1);
3886 SDOperand N2 = N->getOperand(2);
3887 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3889 // never taken branch, fold to chain
3890 if (N1C && N1C->isNullValue())
3892 // unconditional branch
3893 if (N1C && N1C->getValue() == 1)
3894 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
3895 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
3897 if (N1.getOpcode() == ISD::SETCC &&
3898 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
3899 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
3900 N1.getOperand(0), N1.getOperand(1), N2);
3905 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
3907 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
3908 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
3909 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
3911 // Use SimplifySetCC to simplify SETCC's.
3912 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
3913 if (Simp.Val) AddToWorkList(Simp.Val);
3915 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
3917 // fold br_cc true, dest -> br dest (unconditional branch)
3918 if (SCCC && SCCC->getValue())
3919 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
3921 // fold br_cc false, dest -> unconditional fall through
3922 if (SCCC && SCCC->isNullValue())
3923 return N->getOperand(0);
3925 // fold to a simpler setcc
3926 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
3927 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
3928 Simp.getOperand(2), Simp.getOperand(0),
3929 Simp.getOperand(1), N->getOperand(4));
3934 /// CombineToPreIndexedLoadStore - Try turning a load / store and a
3935 /// pre-indexed load / store when the base pointer is a add or subtract
3936 /// and it has other uses besides the load / store. After the
3937 /// transformation, the new indexed load / store has effectively folded
3938 /// the add / subtract in and all of its other uses are redirected to the
3939 /// new load / store.
3940 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
3947 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3948 if (LD->isIndexed())
3950 VT = LD->getMemoryVT();
3951 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
3952 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
3954 Ptr = LD->getBasePtr();
3955 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3956 if (ST->isIndexed())
3958 VT = ST->getMemoryVT();
3959 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
3960 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
3962 Ptr = ST->getBasePtr();
3967 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
3968 // out. There is no reason to make this a preinc/predec.
3969 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
3970 Ptr.Val->hasOneUse())
3973 // Ask the target to do addressing mode selection.
3976 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3977 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
3979 // Don't create a indexed load / store with zero offset.
3980 if (isa<ConstantSDNode>(Offset) &&
3981 cast<ConstantSDNode>(Offset)->getValue() == 0)
3984 // Try turning it into a pre-indexed load / store except when:
3985 // 1) The new base ptr is a frame index.
3986 // 2) If N is a store and the new base ptr is either the same as or is a
3987 // predecessor of the value being stored.
3988 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
3989 // that would create a cycle.
3990 // 4) All uses are load / store ops that use it as old base ptr.
3992 // Check #1. Preinc'ing a frame index would require copying the stack pointer
3993 // (plus the implicit offset) to a register to preinc anyway.
3994 if (isa<FrameIndexSDNode>(BasePtr))
3999 SDOperand Val = cast<StoreSDNode>(N)->getValue();
4000 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val))
4004 // Now check for #3 and #4.
4005 bool RealUse = false;
4006 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
4007 E = Ptr.Val->use_end(); I != E; ++I) {
4011 if (Use->isPredecessor(N))
4014 if (!((Use->getOpcode() == ISD::LOAD &&
4015 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
4016 (Use->getOpcode() == ISD::STORE) &&
4017 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))
4025 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM);
4027 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
4030 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
4031 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
4033 WorkListRemover DeadNodes(*this);
4035 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
4037 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
4040 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
4044 // Finally, since the node is now dead, remove it from the graph.
4047 // Replace the uses of Ptr with uses of the updated base value.
4048 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
4050 removeFromWorkList(Ptr.Val);
4051 DAG.DeleteNode(Ptr.Val);
4056 /// CombineToPostIndexedLoadStore - Try combine a load / store with a
4057 /// add / sub of the base pointer node into a post-indexed load / store.
4058 /// The transformation folded the add / subtract into the new indexed
4059 /// load / store effectively and all of its uses are redirected to the
4060 /// new load / store.
4061 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
4068 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4069 if (LD->isIndexed())
4071 VT = LD->getMemoryVT();
4072 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
4073 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
4075 Ptr = LD->getBasePtr();
4076 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4077 if (ST->isIndexed())
4079 VT = ST->getMemoryVT();
4080 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
4081 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
4083 Ptr = ST->getBasePtr();
4088 if (Ptr.Val->hasOneUse())
4091 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
4092 E = Ptr.Val->use_end(); I != E; ++I) {
4095 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
4100 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4101 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
4103 std::swap(BasePtr, Offset);
4106 // Don't create a indexed load / store with zero offset.
4107 if (isa<ConstantSDNode>(Offset) &&
4108 cast<ConstantSDNode>(Offset)->getValue() == 0)
4111 // Try turning it into a post-indexed load / store except when
4112 // 1) All uses are load / store ops that use it as base ptr.
4113 // 2) Op must be independent of N, i.e. Op is neither a predecessor
4114 // nor a successor of N. Otherwise, if Op is folded that would
4118 bool TryNext = false;
4119 for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
4120 EE = BasePtr.Val->use_end(); II != EE; ++II) {
4125 // If all the uses are load / store addresses, then don't do the
4127 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
4128 bool RealUse = false;
4129 for (SDNode::use_iterator III = Use->use_begin(),
4130 EEE = Use->use_end(); III != EEE; ++III) {
4131 SDNode *UseUse = *III;
4132 if (!((UseUse->getOpcode() == ISD::LOAD &&
4133 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
4134 (UseUse->getOpcode() == ISD::STORE) &&
4135 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))
4149 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) {
4150 SDOperand Result = isLoad
4151 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
4152 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
4155 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
4156 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
4158 WorkListRemover DeadNodes(*this);
4160 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
4162 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
4165 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
4169 // Finally, since the node is now dead, remove it from the graph.
4172 // Replace the uses of Use with uses of the updated base value.
4173 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0),
4174 Result.getValue(isLoad ? 1 : 0),
4176 removeFromWorkList(Op);
4185 /// InferAlignment - If we can infer some alignment information from this
4186 /// pointer, return it.
4187 static unsigned InferAlignment(SDOperand Ptr, SelectionDAG &DAG) {
4188 // If this is a direct reference to a stack slot, use information about the
4189 // stack slot's alignment.
4190 int FrameIdx = 1 << 31;
4191 int64_t FrameOffset = 0;
4192 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) {
4193 FrameIdx = FI->getIndex();
4194 } else if (Ptr.getOpcode() == ISD::ADD &&
4195 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
4196 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4197 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4198 FrameOffset = Ptr.getConstantOperandVal(1);
4201 if (FrameIdx != (1 << 31)) {
4202 // FIXME: Handle FI+CST.
4203 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo();
4204 if (MFI.isFixedObjectIndex(FrameIdx)) {
4205 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx);
4207 // The alignment of the frame index can be determined from its offset from
4208 // the incoming frame position. If the frame object is at offset 32 and
4209 // the stack is guaranteed to be 16-byte aligned, then we know that the
4210 // object is 16-byte aligned.
4211 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment();
4212 unsigned Align = MinAlign(ObjectOffset, StackAlign);
4214 // Finally, the frame object itself may have a known alignment. Factor
4215 // the alignment + offset into a new alignment. For example, if we know
4216 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a
4217 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte
4218 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc.
4219 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx),
4221 return std::max(Align, FIInfoAlign);
4228 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
4229 LoadSDNode *LD = cast<LoadSDNode>(N);
4230 SDOperand Chain = LD->getChain();
4231 SDOperand Ptr = LD->getBasePtr();
4233 // Try to infer better alignment information than the load already has.
4234 if (LD->isUnindexed()) {
4235 if (unsigned Align = InferAlignment(Ptr, DAG)) {
4236 if (Align > LD->getAlignment())
4237 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0),
4238 Chain, Ptr, LD->getSrcValue(),
4239 LD->getSrcValueOffset(), LD->getMemoryVT(),
4240 LD->isVolatile(), Align);
4245 // If load is not volatile and there are no uses of the loaded value (and
4246 // the updated indexed value in case of indexed loads), change uses of the
4247 // chain value into uses of the chain input (i.e. delete the dead load).
4248 if (!LD->isVolatile()) {
4249 if (N->getValueType(1) == MVT::Other) {
4251 if (N->hasNUsesOfValue(0, 0)) {
4252 // It's not safe to use the two value CombineTo variant here. e.g.
4253 // v1, chain2 = load chain1, loc
4254 // v2, chain3 = load chain2, loc
4256 // Now we replace use of chain2 with chain1. This makes the second load
4257 // isomorphic to the one we are deleting, and thus makes this load live.
4258 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4259 DOUT << "\nWith chain: "; DEBUG(Chain.Val->dump(&DAG));
4261 WorkListRemover DeadNodes(*this);
4262 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Chain, &DeadNodes);
4263 if (N->use_empty()) {
4264 removeFromWorkList(N);
4267 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
4271 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
4272 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
4273 SDOperand Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0));
4274 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4275 DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG));
4276 DOUT << " and 2 other values\n";
4277 WorkListRemover DeadNodes(*this);
4278 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Undef, &DeadNodes);
4279 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1),
4280 DAG.getNode(ISD::UNDEF, N->getValueType(1)),
4282 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 2), Chain, &DeadNodes);
4283 removeFromWorkList(N);
4285 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
4290 // If this load is directly stored, replace the load value with the stored
4292 // TODO: Handle store large -> read small portion.
4293 // TODO: Handle TRUNCSTORE/LOADEXT
4294 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
4295 if (ISD::isNON_TRUNCStore(Chain.Val)) {
4296 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
4297 if (PrevST->getBasePtr() == Ptr &&
4298 PrevST->getValue().getValueType() == N->getValueType(0))
4299 return CombineTo(N, Chain.getOperand(1), Chain);
4304 // Walk up chain skipping non-aliasing memory nodes.
4305 SDOperand BetterChain = FindBetterChain(N, Chain);
4307 // If there is a better chain.
4308 if (Chain != BetterChain) {
4311 // Replace the chain to void dependency.
4312 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
4313 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
4314 LD->getSrcValue(), LD->getSrcValueOffset(),
4315 LD->isVolatile(), LD->getAlignment());
4317 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
4318 LD->getValueType(0),
4319 BetterChain, Ptr, LD->getSrcValue(),
4320 LD->getSrcValueOffset(),
4323 LD->getAlignment());
4326 // Create token factor to keep old chain connected.
4327 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
4328 Chain, ReplLoad.getValue(1));
4330 // Replace uses with load result and token factor. Don't add users
4332 return CombineTo(N, ReplLoad.getValue(0), Token, false);
4336 // Try transforming N to an indexed load.
4337 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4338 return SDOperand(N, 0);
4344 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
4345 StoreSDNode *ST = cast<StoreSDNode>(N);
4346 SDOperand Chain = ST->getChain();
4347 SDOperand Value = ST->getValue();
4348 SDOperand Ptr = ST->getBasePtr();
4350 // Try to infer better alignment information than the store already has.
4351 if (ST->isUnindexed()) {
4352 if (unsigned Align = InferAlignment(Ptr, DAG)) {
4353 if (Align > ST->getAlignment())
4354 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(),
4355 ST->getSrcValueOffset(), ST->getMemoryVT(),
4356 ST->isVolatile(), Align);
4360 // If this is a store of a bit convert, store the input value if the
4361 // resultant store does not need a higher alignment than the original.
4362 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
4363 ST->isUnindexed()) {
4364 unsigned Align = ST->getAlignment();
4365 MVT::ValueType SVT = Value.getOperand(0).getValueType();
4366 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
4367 getABITypeAlignment(MVT::getTypeForValueType(SVT));
4368 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT))
4369 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
4370 ST->getSrcValueOffset(), ST->isVolatile(), Align);
4373 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
4374 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
4375 if (Value.getOpcode() != ISD::TargetConstantFP) {
4377 switch (CFP->getValueType(0)) {
4378 default: assert(0 && "Unknown FP type");
4379 case MVT::f80: // We don't do this for these yet.
4384 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) {
4385 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
4386 convertToAPInt().getZExtValue(), MVT::i32);
4387 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
4388 ST->getSrcValueOffset(), ST->isVolatile(),
4389 ST->getAlignment());
4393 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) {
4394 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
4395 getZExtValue(), MVT::i64);
4396 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
4397 ST->getSrcValueOffset(), ST->isVolatile(),
4398 ST->getAlignment());
4399 } else if (TLI.isTypeLegal(MVT::i32)) {
4400 // Many FP stores are not made apparent until after legalize, e.g. for
4401 // argument passing. Since this is so common, custom legalize the
4402 // 64-bit integer store into two 32-bit stores.
4403 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue();
4404 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
4405 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32);
4406 if (TLI.isBigEndian()) std::swap(Lo, Hi);
4408 int SVOffset = ST->getSrcValueOffset();
4409 unsigned Alignment = ST->getAlignment();
4410 bool isVolatile = ST->isVolatile();
4412 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(),
4413 ST->getSrcValueOffset(),
4414 isVolatile, ST->getAlignment());
4415 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4416 DAG.getConstant(4, Ptr.getValueType()));
4418 Alignment = MinAlign(Alignment, 4U);
4419 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(),
4420 SVOffset, isVolatile, Alignment);
4421 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1);
4429 // Walk up chain skipping non-aliasing memory nodes.
4430 SDOperand BetterChain = FindBetterChain(N, Chain);
4432 // If there is a better chain.
4433 if (Chain != BetterChain) {
4434 // Replace the chain to avoid dependency.
4435 SDOperand ReplStore;
4436 if (ST->isTruncatingStore()) {
4437 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
4438 ST->getSrcValue(),ST->getSrcValueOffset(),
4440 ST->isVolatile(), ST->getAlignment());
4442 ReplStore = DAG.getStore(BetterChain, Value, Ptr,
4443 ST->getSrcValue(), ST->getSrcValueOffset(),
4444 ST->isVolatile(), ST->getAlignment());
4447 // Create token to keep both nodes around.
4449 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
4451 // Don't add users to work list.
4452 return CombineTo(N, Token, false);
4456 // Try transforming N to an indexed store.
4457 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4458 return SDOperand(N, 0);
4460 // FIXME: is there such a thing as a truncating indexed store?
4461 if (ST->isTruncatingStore() && ST->isUnindexed() &&
4462 MVT::isInteger(Value.getValueType())) {
4463 // See if we can simplify the input to this truncstore with knowledge that
4464 // only the low bits are being used. For example:
4465 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
4467 GetDemandedBits(Value, MVT::getIntVTBitMask(ST->getMemoryVT()));
4468 AddToWorkList(Value.Val);
4470 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(),
4471 ST->getSrcValueOffset(), ST->getMemoryVT(),
4472 ST->isVolatile(), ST->getAlignment());
4474 // Otherwise, see if we can simplify the operation with
4475 // SimplifyDemandedBits, which only works if the value has a single use.
4476 if (SimplifyDemandedBits(Value, MVT::getIntVTBitMask(ST->getMemoryVT())))
4477 return SDOperand(N, 0);
4480 // If this is a load followed by a store to the same location, then the store
4482 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
4483 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
4484 ST->isUnindexed() && !ST->isVolatile() &&
4485 // There can't be any side effects between the load and store, such as
4487 Chain.reachesChainWithoutSideEffects(SDOperand(Ld, 1))) {
4488 // The store is dead, remove it.
4493 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
4494 // truncating store. We can do this even if this is already a truncstore.
4495 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
4496 && TLI.isTypeLegal(Value.getOperand(0).getValueType()) &&
4497 Value.Val->hasOneUse() && ST->isUnindexed() &&
4498 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
4499 ST->getMemoryVT())) {
4500 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
4501 ST->getSrcValueOffset(), ST->getMemoryVT(),
4502 ST->isVolatile(), ST->getAlignment());
4508 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
4509 SDOperand InVec = N->getOperand(0);
4510 SDOperand InVal = N->getOperand(1);
4511 SDOperand EltNo = N->getOperand(2);
4513 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
4514 // vector with the inserted element.
4515 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
4516 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
4517 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
4518 if (Elt < Ops.size())
4520 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
4521 &Ops[0], Ops.size());
4527 SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
4528 SDOperand InVec = N->getOperand(0);
4529 SDOperand EltNo = N->getOperand(1);
4531 // (vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr)
4532 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr)
4533 if (isa<ConstantSDNode>(EltNo)) {
4534 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
4535 bool NewLoad = false;
4537 MVT::ValueType VT = InVec.getValueType();
4538 MVT::ValueType EVT = MVT::getVectorElementType(VT);
4539 MVT::ValueType LVT = EVT;
4540 unsigned NumElts = MVT::getVectorNumElements(VT);
4541 if (InVec.getOpcode() == ISD::BIT_CONVERT) {
4542 MVT::ValueType BCVT = InVec.getOperand(0).getValueType();
4543 if (!MVT::isVector(BCVT) ||
4544 NumElts != MVT::getVectorNumElements(BCVT))
4546 InVec = InVec.getOperand(0);
4547 EVT = MVT::getVectorElementType(BCVT);
4550 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4551 InVec.getOperand(0).getValueType() == EVT &&
4552 ISD::isNormalLoad(InVec.getOperand(0).Val) &&
4553 InVec.getOperand(0).hasOneUse()) {
4554 LoadSDNode *LN0 = cast<LoadSDNode>(InVec.getOperand(0));
4555 unsigned Align = LN0->getAlignment();
4557 // Check the resultant load doesn't need a higher alignment than the
4559 unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
4560 getABITypeAlignment(MVT::getTypeForValueType(LVT));
4561 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align)
4566 return DAG.getLoad(LVT, LN0->getChain(), LN0->getBasePtr(),
4567 LN0->getSrcValue(), LN0->getSrcValueOffset(),
4568 LN0->isVolatile(), Align);
4576 SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
4577 unsigned NumInScalars = N->getNumOperands();
4578 MVT::ValueType VT = N->getValueType(0);
4579 unsigned NumElts = MVT::getVectorNumElements(VT);
4580 MVT::ValueType EltType = MVT::getVectorElementType(VT);
4582 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
4583 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
4584 // at most two distinct vectors, turn this into a shuffle node.
4585 SDOperand VecIn1, VecIn2;
4586 for (unsigned i = 0; i != NumInScalars; ++i) {
4587 // Ignore undef inputs.
4588 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4590 // If this input is something other than a EXTRACT_VECTOR_ELT with a
4591 // constant index, bail out.
4592 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4593 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
4594 VecIn1 = VecIn2 = SDOperand(0, 0);
4598 // If the input vector type disagrees with the result of the build_vector,
4599 // we can't make a shuffle.
4600 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
4601 if (ExtractedFromVec.getValueType() != VT) {
4602 VecIn1 = VecIn2 = SDOperand(0, 0);
4606 // Otherwise, remember this. We allow up to two distinct input vectors.
4607 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
4610 if (VecIn1.Val == 0) {
4611 VecIn1 = ExtractedFromVec;
4612 } else if (VecIn2.Val == 0) {
4613 VecIn2 = ExtractedFromVec;
4616 VecIn1 = VecIn2 = SDOperand(0, 0);
4621 // If everything is good, we can make a shuffle operation.
4623 SmallVector<SDOperand, 8> BuildVecIndices;
4624 for (unsigned i = 0; i != NumInScalars; ++i) {
4625 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
4626 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy()));
4630 SDOperand Extract = N->getOperand(i);
4632 // If extracting from the first vector, just use the index directly.
4633 if (Extract.getOperand(0) == VecIn1) {
4634 BuildVecIndices.push_back(Extract.getOperand(1));
4638 // Otherwise, use InIdx + VecSize
4639 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
4640 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars));
4643 // Add count and size info.
4644 MVT::ValueType BuildVecVT = MVT::getVectorType(TLI.getPointerTy(), NumElts);
4646 // Return the new VECTOR_SHUFFLE node.
4652 // Use an undef build_vector as input for the second operand.
4653 std::vector<SDOperand> UnOps(NumInScalars,
4654 DAG.getNode(ISD::UNDEF,
4656 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT,
4657 &UnOps[0], UnOps.size());
4658 AddToWorkList(Ops[1].Val);
4660 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT,
4661 &BuildVecIndices[0], BuildVecIndices.size());
4662 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3);
4668 SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
4669 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
4670 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
4671 // inputs come from at most two distinct vectors, turn this into a shuffle
4674 // If we only have one input vector, we don't need to do any concatenation.
4675 if (N->getNumOperands() == 1) {
4676 return N->getOperand(0);
4682 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
4683 SDOperand ShufMask = N->getOperand(2);
4684 unsigned NumElts = ShufMask.getNumOperands();
4686 // If the shuffle mask is an identity operation on the LHS, return the LHS.
4687 bool isIdentity = true;
4688 for (unsigned i = 0; i != NumElts; ++i) {
4689 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4690 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
4695 if (isIdentity) return N->getOperand(0);
4697 // If the shuffle mask is an identity operation on the RHS, return the RHS.
4699 for (unsigned i = 0; i != NumElts; ++i) {
4700 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4701 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
4706 if (isIdentity) return N->getOperand(1);
4708 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
4710 bool isUnary = true;
4711 bool isSplat = true;
4713 unsigned BaseIdx = 0;
4714 for (unsigned i = 0; i != NumElts; ++i)
4715 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
4716 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
4717 int V = (Idx < NumElts) ? 0 : 1;
4731 SDOperand N0 = N->getOperand(0);
4732 SDOperand N1 = N->getOperand(1);
4733 // Normalize unary shuffle so the RHS is undef.
4734 if (isUnary && VecNum == 1)
4737 // If it is a splat, check if the argument vector is a build_vector with
4738 // all scalar elements the same.
4742 // If this is a bit convert that changes the element type of the vector but
4743 // not the number of vector elements, look through it. Be careful not to
4744 // look though conversions that change things like v4f32 to v2f64.
4745 if (V->getOpcode() == ISD::BIT_CONVERT) {
4746 SDOperand ConvInput = V->getOperand(0);
4747 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts)
4751 if (V->getOpcode() == ISD::BUILD_VECTOR) {
4752 unsigned NumElems = V->getNumOperands();
4753 if (NumElems > BaseIdx) {
4755 bool AllSame = true;
4756 for (unsigned i = 0; i != NumElems; ++i) {
4757 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
4758 Base = V->getOperand(i);
4762 // Splat of <u, u, u, u>, return <u, u, u, u>
4765 for (unsigned i = 0; i != NumElems; ++i) {
4766 if (V->getOperand(i) != Base) {
4771 // Splat of <x, x, x, x>, return <x, x, x, x>
4778 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
4780 if (isUnary || N0 == N1) {
4781 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
4783 SmallVector<SDOperand, 8> MappedOps;
4784 for (unsigned i = 0; i != NumElts; ++i) {
4785 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
4786 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
4787 MappedOps.push_back(ShufMask.getOperand(i));
4790 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
4791 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
4794 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
4795 &MappedOps[0], MappedOps.size());
4796 AddToWorkList(ShufMask.Val);
4797 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
4799 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
4806 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
4807 /// an AND to a vector_shuffle with the destination vector and a zero vector.
4808 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
4809 /// vector_shuffle V, Zero, <0, 4, 2, 4>
4810 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
4811 SDOperand LHS = N->getOperand(0);
4812 SDOperand RHS = N->getOperand(1);
4813 if (N->getOpcode() == ISD::AND) {
4814 if (RHS.getOpcode() == ISD::BIT_CONVERT)
4815 RHS = RHS.getOperand(0);
4816 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
4817 std::vector<SDOperand> IdxOps;
4818 unsigned NumOps = RHS.getNumOperands();
4819 unsigned NumElts = NumOps;
4820 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType());
4821 for (unsigned i = 0; i != NumElts; ++i) {
4822 SDOperand Elt = RHS.getOperand(i);
4823 if (!isa<ConstantSDNode>(Elt))
4825 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
4826 IdxOps.push_back(DAG.getConstant(i, EVT));
4827 else if (cast<ConstantSDNode>(Elt)->isNullValue())
4828 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
4833 // Let's see if the target supports this vector_shuffle.
4834 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
4837 // Return the new VECTOR_SHUFFLE node.
4838 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts);
4839 std::vector<SDOperand> Ops;
4840 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS);
4842 AddToWorkList(LHS.Val);
4843 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
4844 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
4845 &ZeroOps[0], ZeroOps.size()));
4846 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
4847 &IdxOps[0], IdxOps.size()));
4848 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT,
4849 &Ops[0], Ops.size());
4850 if (VT != LHS.getValueType()) {
4851 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result);
4859 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
4860 SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) {
4861 // After legalize, the target may be depending on adds and other
4862 // binary ops to provide legal ways to construct constants or other
4863 // things. Simplifying them may result in a loss of legality.
4864 if (AfterLegalize) return SDOperand();
4866 MVT::ValueType VT = N->getValueType(0);
4867 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!");
4869 MVT::ValueType EltType = MVT::getVectorElementType(VT);
4870 SDOperand LHS = N->getOperand(0);
4871 SDOperand RHS = N->getOperand(1);
4872 SDOperand Shuffle = XformToShuffleWithZero(N);
4873 if (Shuffle.Val) return Shuffle;
4875 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
4877 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
4878 RHS.getOpcode() == ISD::BUILD_VECTOR) {
4879 SmallVector<SDOperand, 8> Ops;
4880 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
4881 SDOperand LHSOp = LHS.getOperand(i);
4882 SDOperand RHSOp = RHS.getOperand(i);
4883 // If these two elements can't be folded, bail out.
4884 if ((LHSOp.getOpcode() != ISD::UNDEF &&
4885 LHSOp.getOpcode() != ISD::Constant &&
4886 LHSOp.getOpcode() != ISD::ConstantFP) ||
4887 (RHSOp.getOpcode() != ISD::UNDEF &&
4888 RHSOp.getOpcode() != ISD::Constant &&
4889 RHSOp.getOpcode() != ISD::ConstantFP))
4891 // Can't fold divide by zero.
4892 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
4893 N->getOpcode() == ISD::FDIV) {
4894 if ((RHSOp.getOpcode() == ISD::Constant &&
4895 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
4896 (RHSOp.getOpcode() == ISD::ConstantFP &&
4897 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero()))
4900 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp));
4901 AddToWorkList(Ops.back().Val);
4902 assert((Ops.back().getOpcode() == ISD::UNDEF ||
4903 Ops.back().getOpcode() == ISD::Constant ||
4904 Ops.back().getOpcode() == ISD::ConstantFP) &&
4905 "Scalar binop didn't fold!");
4908 if (Ops.size() == LHS.getNumOperands()) {
4909 MVT::ValueType VT = LHS.getValueType();
4910 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
4917 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
4918 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
4920 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
4921 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4922 // If we got a simplified select_cc node back from SimplifySelectCC, then
4923 // break it down into a new SETCC node, and a new SELECT node, and then return
4924 // the SELECT node, since we were called with a SELECT node.
4926 // Check to see if we got a select_cc back (to turn into setcc/select).
4927 // Otherwise, just return whatever node we got back, like fabs.
4928 if (SCC.getOpcode() == ISD::SELECT_CC) {
4929 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
4930 SCC.getOperand(0), SCC.getOperand(1),
4932 AddToWorkList(SETCC.Val);
4933 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
4934 SCC.getOperand(3), SETCC);
4941 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
4942 /// are the two values being selected between, see if we can simplify the
4943 /// select. Callers of this should assume that TheSelect is deleted if this
4944 /// returns true. As such, they should return the appropriate thing (e.g. the
4945 /// node) back to the top-level of the DAG combiner loop to avoid it being
4948 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
4951 // If this is a select from two identical things, try to pull the operation
4952 // through the select.
4953 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
4954 // If this is a load and the token chain is identical, replace the select
4955 // of two loads with a load through a select of the address to load from.
4956 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
4957 // constants have been dropped into the constant pool.
4958 if (LHS.getOpcode() == ISD::LOAD &&
4959 // Token chains must be identical.
4960 LHS.getOperand(0) == RHS.getOperand(0)) {
4961 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
4962 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
4964 // If this is an EXTLOAD, the VT's must match.
4965 if (LLD->getMemoryVT() == RLD->getMemoryVT()) {
4966 // FIXME: this conflates two src values, discarding one. This is not
4967 // the right thing to do, but nothing uses srcvalues now. When they do,
4968 // turn SrcValue into a list of locations.
4970 if (TheSelect->getOpcode() == ISD::SELECT) {
4971 // Check that the condition doesn't reach either load. If so, folding
4972 // this will induce a cycle into the DAG.
4973 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4974 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) {
4975 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
4976 TheSelect->getOperand(0), LLD->getBasePtr(),
4980 // Check that the condition doesn't reach either load. If so, folding
4981 // this will induce a cycle into the DAG.
4982 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4983 !RLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4984 !LLD->isPredecessor(TheSelect->getOperand(1).Val) &&
4985 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) {
4986 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
4987 TheSelect->getOperand(0),
4988 TheSelect->getOperand(1),
4989 LLD->getBasePtr(), RLD->getBasePtr(),
4990 TheSelect->getOperand(4));
4996 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
4997 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
4998 Addr,LLD->getSrcValue(),
4999 LLD->getSrcValueOffset(),
5001 LLD->getAlignment());
5003 Load = DAG.getExtLoad(LLD->getExtensionType(),
5004 TheSelect->getValueType(0),
5005 LLD->getChain(), Addr, LLD->getSrcValue(),
5006 LLD->getSrcValueOffset(),
5009 LLD->getAlignment());
5011 // Users of the select now use the result of the load.
5012 CombineTo(TheSelect, Load);
5014 // Users of the old loads now use the new load's chain. We know the
5015 // old-load value is dead now.
5016 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
5017 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
5027 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
5028 SDOperand N2, SDOperand N3,
5029 ISD::CondCode CC, bool NotExtCompare) {
5031 MVT::ValueType VT = N2.getValueType();
5032 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
5033 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
5034 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
5036 // Determine if the condition we're dealing with is constant
5037 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
5038 if (SCC.Val) AddToWorkList(SCC.Val);
5039 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
5041 // fold select_cc true, x, y -> x
5042 if (SCCC && SCCC->getValue())
5044 // fold select_cc false, x, y -> y
5045 if (SCCC && SCCC->getValue() == 0)
5048 // Check to see if we can simplify the select into an fabs node
5049 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
5050 // Allow either -0.0 or 0.0
5051 if (CFP->getValueAPF().isZero()) {
5052 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
5053 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
5054 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
5055 N2 == N3.getOperand(0))
5056 return DAG.getNode(ISD::FABS, VT, N0);
5058 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
5059 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
5060 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
5061 N2.getOperand(0) == N3)
5062 return DAG.getNode(ISD::FABS, VT, N3);
5066 // Check to see if we can perform the "gzip trick", transforming
5067 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
5068 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
5069 MVT::isInteger(N0.getValueType()) &&
5070 MVT::isInteger(N2.getValueType()) &&
5071 (N1C->isNullValue() || // (a < 0) ? b : 0
5072 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
5073 MVT::ValueType XType = N0.getValueType();
5074 MVT::ValueType AType = N2.getValueType();
5075 if (XType >= AType) {
5076 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
5077 // single-bit constant.
5078 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
5079 unsigned ShCtV = Log2_64(N2C->getValue());
5080 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
5081 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
5082 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
5083 AddToWorkList(Shift.Val);
5084 if (XType > AType) {
5085 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
5086 AddToWorkList(Shift.Val);
5088 return DAG.getNode(ISD::AND, AType, Shift, N2);
5090 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
5091 DAG.getConstant(MVT::getSizeInBits(XType)-1,
5092 TLI.getShiftAmountTy()));
5093 AddToWorkList(Shift.Val);
5094 if (XType > AType) {
5095 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
5096 AddToWorkList(Shift.Val);
5098 return DAG.getNode(ISD::AND, AType, Shift, N2);
5102 // fold select C, 16, 0 -> shl C, 4
5103 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
5104 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
5106 // If the caller doesn't want us to simplify this into a zext of a compare,
5108 if (NotExtCompare && N2C->getValue() == 1)
5111 // Get a SetCC of the condition
5112 // FIXME: Should probably make sure that setcc is legal if we ever have a
5113 // target where it isn't.
5114 SDOperand Temp, SCC;
5115 // cast from setcc result type to select result type
5116 if (AfterLegalize) {
5117 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
5118 if (N2.getValueType() < SCC.getValueType())
5119 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
5121 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
5123 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
5124 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
5126 AddToWorkList(SCC.Val);
5127 AddToWorkList(Temp.Val);
5129 if (N2C->getValue() == 1)
5131 // shl setcc result by log2 n2c
5132 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
5133 DAG.getConstant(Log2_64(N2C->getValue()),
5134 TLI.getShiftAmountTy()));
5137 // Check to see if this is the equivalent of setcc
5138 // FIXME: Turn all of these into setcc if setcc if setcc is legal
5139 // otherwise, go ahead with the folds.
5140 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
5141 MVT::ValueType XType = N0.getValueType();
5142 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
5143 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
5144 if (Res.getValueType() != VT)
5145 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
5149 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
5150 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
5151 TLI.isOperationLegal(ISD::CTLZ, XType)) {
5152 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
5153 return DAG.getNode(ISD::SRL, XType, Ctlz,
5154 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
5155 TLI.getShiftAmountTy()));
5157 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
5158 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
5159 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
5161 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
5162 DAG.getConstant(~0ULL, XType));
5163 return DAG.getNode(ISD::SRL, XType,
5164 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
5165 DAG.getConstant(MVT::getSizeInBits(XType)-1,
5166 TLI.getShiftAmountTy()));
5168 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
5169 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
5170 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
5171 DAG.getConstant(MVT::getSizeInBits(XType)-1,
5172 TLI.getShiftAmountTy()));
5173 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
5177 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
5178 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5179 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
5180 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
5181 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) {
5182 MVT::ValueType XType = N0.getValueType();
5183 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
5184 DAG.getConstant(MVT::getSizeInBits(XType)-1,
5185 TLI.getShiftAmountTy()));
5186 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
5187 AddToWorkList(Shift.Val);
5188 AddToWorkList(Add.Val);
5189 return DAG.getNode(ISD::XOR, XType, Add, Shift);
5191 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
5192 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5193 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
5194 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
5195 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
5196 MVT::ValueType XType = N0.getValueType();
5197 if (SubC->isNullValue() && MVT::isInteger(XType)) {
5198 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
5199 DAG.getConstant(MVT::getSizeInBits(XType)-1,
5200 TLI.getShiftAmountTy()));
5201 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
5202 AddToWorkList(Shift.Val);
5203 AddToWorkList(Add.Val);
5204 return DAG.getNode(ISD::XOR, XType, Add, Shift);
5212 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
5213 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
5214 SDOperand N1, ISD::CondCode Cond,
5215 bool foldBooleans) {
5216 TargetLowering::DAGCombinerInfo
5217 DagCombineInfo(DAG, !AfterLegalize, false, this);
5218 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo);
5221 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
5222 /// return a DAG expression to select that will generate the same value by
5223 /// multiplying by a magic number. See:
5224 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
5225 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
5226 std::vector<SDNode*> Built;
5227 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
5229 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
5235 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
5236 /// return a DAG expression to select that will generate the same value by
5237 /// multiplying by a magic number. See:
5238 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
5239 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
5240 std::vector<SDNode*> Built;
5241 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
5243 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
5249 /// FindBaseOffset - Return true if base is known not to alias with anything
5250 /// but itself. Provides base object and offset as results.
5251 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
5252 // Assume it is a primitive operation.
5253 Base = Ptr; Offset = 0;
5255 // If it's an adding a simple constant then integrate the offset.
5256 if (Base.getOpcode() == ISD::ADD) {
5257 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
5258 Base = Base.getOperand(0);
5259 Offset += C->getValue();
5263 // If it's any of the following then it can't alias with anything but itself.
5264 return isa<FrameIndexSDNode>(Base) ||
5265 isa<ConstantPoolSDNode>(Base) ||
5266 isa<GlobalAddressSDNode>(Base);
5269 /// isAlias - Return true if there is any possibility that the two addresses
5271 bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1,
5272 const Value *SrcValue1, int SrcValueOffset1,
5273 SDOperand Ptr2, int64_t Size2,
5274 const Value *SrcValue2, int SrcValueOffset2)
5276 // If they are the same then they must be aliases.
5277 if (Ptr1 == Ptr2) return true;
5279 // Gather base node and offset information.
5280 SDOperand Base1, Base2;
5281 int64_t Offset1, Offset2;
5282 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
5283 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
5285 // If they have a same base address then...
5286 if (Base1 == Base2) {
5287 // Check to see if the addresses overlap.
5288 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
5291 // If we know both bases then they can't alias.
5292 if (KnownBase1 && KnownBase2) return false;
5294 if (CombinerGlobalAA) {
5295 // Use alias analysis information.
5296 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
5297 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
5298 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
5299 AliasAnalysis::AliasResult AAResult =
5300 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
5301 if (AAResult == AliasAnalysis::NoAlias)
5305 // Otherwise we have to assume they alias.
5309 /// FindAliasInfo - Extracts the relevant alias information from the memory
5310 /// node. Returns true if the operand was a load.
5311 bool DAGCombiner::FindAliasInfo(SDNode *N,
5312 SDOperand &Ptr, int64_t &Size,
5313 const Value *&SrcValue, int &SrcValueOffset) {
5314 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5315 Ptr = LD->getBasePtr();
5316 Size = MVT::getSizeInBits(LD->getMemoryVT()) >> 3;
5317 SrcValue = LD->getSrcValue();
5318 SrcValueOffset = LD->getSrcValueOffset();
5320 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5321 Ptr = ST->getBasePtr();
5322 Size = MVT::getSizeInBits(ST->getMemoryVT()) >> 3;
5323 SrcValue = ST->getSrcValue();
5324 SrcValueOffset = ST->getSrcValueOffset();
5326 assert(0 && "FindAliasInfo expected a memory operand");
5332 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
5333 /// looking for aliasing nodes and adding them to the Aliases vector.
5334 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
5335 SmallVector<SDOperand, 8> &Aliases) {
5336 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
5337 std::set<SDNode *> Visited; // Visited node set.
5339 // Get alias information for node.
5342 const Value *SrcValue;
5344 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
5347 Chains.push_back(OriginalChain);
5349 // Look at each chain and determine if it is an alias. If so, add it to the
5350 // aliases list. If not, then continue up the chain looking for the next
5352 while (!Chains.empty()) {
5353 SDOperand Chain = Chains.back();
5356 // Don't bother if we've been before.
5357 if (Visited.find(Chain.Val) != Visited.end()) continue;
5358 Visited.insert(Chain.Val);
5360 switch (Chain.getOpcode()) {
5361 case ISD::EntryToken:
5362 // Entry token is ideal chain operand, but handled in FindBetterChain.
5367 // Get alias information for Chain.
5370 const Value *OpSrcValue;
5371 int OpSrcValueOffset;
5372 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
5373 OpSrcValue, OpSrcValueOffset);
5375 // If chain is alias then stop here.
5376 if (!(IsLoad && IsOpLoad) &&
5377 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
5378 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
5379 Aliases.push_back(Chain);
5381 // Look further up the chain.
5382 Chains.push_back(Chain.getOperand(0));
5383 // Clean up old chain.
5384 AddToWorkList(Chain.Val);
5389 case ISD::TokenFactor:
5390 // We have to check each of the operands of the token factor, so we queue
5391 // then up. Adding the operands to the queue (stack) in reverse order
5392 // maintains the original order and increases the likelihood that getNode
5393 // will find a matching token factor (CSE.)
5394 for (unsigned n = Chain.getNumOperands(); n;)
5395 Chains.push_back(Chain.getOperand(--n));
5396 // Eliminate the token factor if we can.
5397 AddToWorkList(Chain.Val);
5401 // For all other instructions we will just have to take what we can get.
5402 Aliases.push_back(Chain);
5408 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
5409 /// for a better chain (aliasing node.)
5410 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
5411 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
5413 // Accumulate all the aliases to this node.
5414 GatherAllAliases(N, OldChain, Aliases);
5416 if (Aliases.size() == 0) {
5417 // If no operands then chain to entry token.
5418 return DAG.getEntryNode();
5419 } else if (Aliases.size() == 1) {
5420 // If a single operand then chain to it. We don't need to revisit it.
5424 // Construct a custom tailored token factor.
5425 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5426 &Aliases[0], Aliases.size());
5428 // Make sure the old chain gets cleaned up.
5429 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
5434 // SelectionDAG::Combine - This is the entry point for the file.
5436 void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
5437 if (!RunningAfterLegalize && ViewDAGCombine1)
5439 if (RunningAfterLegalize && ViewDAGCombine2)
5441 /// run - This is the main entry point to this class.
5443 DAGCombiner(*this, AA).Run(RunningAfterLegalize);