1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: make truncate see through SIGN_EXTEND and AND
26 // FIXME: divide by zero is currently left unfolded. do we want to turn this
28 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
30 //===----------------------------------------------------------------------===//
32 #define DEBUG_TYPE "dagcombine"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Target/TargetLowering.h"
44 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined");
51 // Worklist of all of the nodes that need to be simplified.
52 std::vector<SDNode*> WorkList;
54 /// AddUsersToWorkList - When an instruction is simplified, add all users of
55 /// the instruction to the work lists because they might get more simplified
58 void AddUsersToWorkList(SDNode *N) {
59 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
61 WorkList.push_back(*UI);
64 /// removeFromWorkList - remove all instances of N from the worklist.
66 void removeFromWorkList(SDNode *N) {
67 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
72 void AddToWorkList(SDNode *N) {
73 WorkList.push_back(N);
76 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
78 DEBUG(std::cerr << "\nReplacing "; N->dump();
79 std::cerr << "\nWith: "; To[0].Val->dump();
80 std::cerr << " and " << To.size()-1 << " other values\n");
81 std::vector<SDNode*> NowDead;
82 DAG.ReplaceAllUsesWith(N, To, &NowDead);
84 // Push the new nodes and any users onto the worklist
85 for (unsigned i = 0, e = To.size(); i != e; ++i) {
86 WorkList.push_back(To[i].Val);
87 AddUsersToWorkList(To[i].Val);
90 // Nodes can end up on the worklist more than once. Make sure we do
91 // not process a node that has been replaced.
92 removeFromWorkList(N);
93 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
94 removeFromWorkList(NowDead[i]);
96 // Finally, since the node is now dead, remove it from the graph.
98 return SDOperand(N, 0);
101 SDOperand CombineTo(SDNode *N, SDOperand Res) {
102 std::vector<SDOperand> To;
104 return CombineTo(N, To);
107 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
108 std::vector<SDOperand> To;
111 return CombineTo(N, To);
115 /// SimplifyDemandedBits - Check the specified integer node value to see if
116 /// it can be simplified or if things it uses can be simplified by bit
117 /// propagation. If so, return true.
118 bool SimplifyDemandedBits(SDOperand Op) {
119 TargetLowering::TargetLoweringOpt TLO(DAG);
120 uint64_t KnownZero, KnownOne;
121 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
122 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
126 WorkList.push_back(Op.Val);
128 // Replace the old value with the new one.
130 DEBUG(std::cerr << "\nReplacing "; TLO.Old.Val->dump();
131 std::cerr << "\nWith: "; TLO.New.Val->dump());
133 std::vector<SDNode*> NowDead;
134 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
136 // Push the new node and any (possibly new) users onto the worklist.
137 WorkList.push_back(TLO.New.Val);
138 AddUsersToWorkList(TLO.New.Val);
140 // Nodes can end up on the worklist more than once. Make sure we do
141 // not process a node that has been replaced.
142 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
143 removeFromWorkList(NowDead[i]);
145 // Finally, if the node is now dead, remove it from the graph. The node
146 // may not be dead if the replacement process recursively simplified to
147 // something else needing this node.
148 if (TLO.Old.Val->use_empty()) {
149 removeFromWorkList(TLO.Old.Val);
150 DAG.DeleteNode(TLO.Old.Val);
155 /// visit - call the node-specific routine that knows how to fold each
156 /// particular type of node.
157 SDOperand visit(SDNode *N);
159 // Visitation implementation - Implement dag node combining for different
160 // node types. The semantics are as follows:
162 // SDOperand.Val == 0 - No change was made
163 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
164 // otherwise - N should be replaced by the returned Operand.
166 SDOperand visitTokenFactor(SDNode *N);
167 SDOperand visitADD(SDNode *N);
168 SDOperand visitSUB(SDNode *N);
169 SDOperand visitMUL(SDNode *N);
170 SDOperand visitSDIV(SDNode *N);
171 SDOperand visitUDIV(SDNode *N);
172 SDOperand visitSREM(SDNode *N);
173 SDOperand visitUREM(SDNode *N);
174 SDOperand visitMULHU(SDNode *N);
175 SDOperand visitMULHS(SDNode *N);
176 SDOperand visitAND(SDNode *N);
177 SDOperand visitOR(SDNode *N);
178 SDOperand visitXOR(SDNode *N);
179 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp);
180 SDOperand visitSHL(SDNode *N);
181 SDOperand visitSRA(SDNode *N);
182 SDOperand visitSRL(SDNode *N);
183 SDOperand visitCTLZ(SDNode *N);
184 SDOperand visitCTTZ(SDNode *N);
185 SDOperand visitCTPOP(SDNode *N);
186 SDOperand visitSELECT(SDNode *N);
187 SDOperand visitSELECT_CC(SDNode *N);
188 SDOperand visitSETCC(SDNode *N);
189 SDOperand visitSIGN_EXTEND(SDNode *N);
190 SDOperand visitZERO_EXTEND(SDNode *N);
191 SDOperand visitANY_EXTEND(SDNode *N);
192 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
193 SDOperand visitTRUNCATE(SDNode *N);
194 SDOperand visitBIT_CONVERT(SDNode *N);
195 SDOperand visitVBIT_CONVERT(SDNode *N);
196 SDOperand visitFADD(SDNode *N);
197 SDOperand visitFSUB(SDNode *N);
198 SDOperand visitFMUL(SDNode *N);
199 SDOperand visitFDIV(SDNode *N);
200 SDOperand visitFREM(SDNode *N);
201 SDOperand visitFCOPYSIGN(SDNode *N);
202 SDOperand visitSINT_TO_FP(SDNode *N);
203 SDOperand visitUINT_TO_FP(SDNode *N);
204 SDOperand visitFP_TO_SINT(SDNode *N);
205 SDOperand visitFP_TO_UINT(SDNode *N);
206 SDOperand visitFP_ROUND(SDNode *N);
207 SDOperand visitFP_ROUND_INREG(SDNode *N);
208 SDOperand visitFP_EXTEND(SDNode *N);
209 SDOperand visitFNEG(SDNode *N);
210 SDOperand visitFABS(SDNode *N);
211 SDOperand visitBRCOND(SDNode *N);
212 SDOperand visitBR_CC(SDNode *N);
213 SDOperand visitLOAD(SDNode *N);
214 SDOperand visitXEXTLOAD(SDNode *N);
215 SDOperand visitSTORE(SDNode *N);
216 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
217 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
218 SDOperand visitVBUILD_VECTOR(SDNode *N);
219 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
220 SDOperand visitVVECTOR_SHUFFLE(SDNode *N);
222 SDOperand XformToShuffleWithZero(SDNode *N);
223 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
225 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
226 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
227 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
228 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
229 SDOperand N3, ISD::CondCode CC);
230 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
231 ISD::CondCode Cond, bool foldBooleans = true);
232 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType);
233 SDOperand BuildSDIV(SDNode *N);
234 SDOperand BuildUDIV(SDNode *N);
236 DAGCombiner(SelectionDAG &D)
237 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
239 /// Run - runs the dag combiner on all nodes in the work list
240 void Run(bool RunningAfterLegalize);
244 //===----------------------------------------------------------------------===//
245 // TargetLowering::DAGCombinerInfo implementation
246 //===----------------------------------------------------------------------===//
248 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
249 ((DAGCombiner*)DC)->AddToWorkList(N);
252 SDOperand TargetLowering::DAGCombinerInfo::
253 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
254 return ((DAGCombiner*)DC)->CombineTo(N, To);
257 SDOperand TargetLowering::DAGCombinerInfo::
258 CombineTo(SDNode *N, SDOperand Res) {
259 return ((DAGCombiner*)DC)->CombineTo(N, Res);
263 SDOperand TargetLowering::DAGCombinerInfo::
264 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
265 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
271 //===----------------------------------------------------------------------===//
275 int64_t m; // magic number
276 int64_t s; // shift amount
280 uint64_t m; // magic number
281 int64_t a; // add indicator
282 int64_t s; // shift amount
285 /// magic - calculate the magic numbers required to codegen an integer sdiv as
286 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
288 static ms magic32(int32_t d) {
290 uint32_t ad, anc, delta, q1, r1, q2, r2, t;
291 const uint32_t two31 = 0x80000000U;
295 t = two31 + ((uint32_t)d >> 31);
296 anc = t - 1 - t%ad; // absolute value of nc
297 p = 31; // initialize p
298 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
299 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
300 q2 = two31/ad; // initialize q2 = 2p/abs(d)
301 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
304 q1 = 2*q1; // update q1 = 2p/abs(nc)
305 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
306 if (r1 >= anc) { // must be unsigned comparison
310 q2 = 2*q2; // update q2 = 2p/abs(d)
311 r2 = 2*r2; // update r2 = rem(2p/abs(d))
312 if (r2 >= ad) { // must be unsigned comparison
317 } while (q1 < delta || (q1 == delta && r1 == 0));
319 mag.m = (int32_t)(q2 + 1); // make sure to sign extend
320 if (d < 0) mag.m = -mag.m; // resulting magic number
321 mag.s = p - 32; // resulting shift
325 /// magicu - calculate the magic numbers required to codegen an integer udiv as
326 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
327 static mu magicu32(uint32_t d) {
329 uint32_t nc, delta, q1, r1, q2, r2;
331 magu.a = 0; // initialize "add" indicator
333 p = 31; // initialize p
334 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
335 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
336 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
337 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
340 if (r1 >= nc - r1 ) {
341 q1 = 2*q1 + 1; // update q1
342 r1 = 2*r1 - nc; // update r1
345 q1 = 2*q1; // update q1
346 r1 = 2*r1; // update r1
348 if (r2 + 1 >= d - r2) {
349 if (q2 >= 0x7FFFFFFF) magu.a = 1;
350 q2 = 2*q2 + 1; // update q2
351 r2 = 2*r2 + 1 - d; // update r2
354 if (q2 >= 0x80000000) magu.a = 1;
355 q2 = 2*q2; // update q2
356 r2 = 2*r2 + 1; // update r2
359 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
360 magu.m = q2 + 1; // resulting magic number
361 magu.s = p - 32; // resulting shift
365 /// magic - calculate the magic numbers required to codegen an integer sdiv as
366 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
368 static ms magic64(int64_t d) {
370 uint64_t ad, anc, delta, q1, r1, q2, r2, t;
371 const uint64_t two63 = 9223372036854775808ULL; // 2^63
374 ad = d >= 0 ? d : -d;
375 t = two63 + ((uint64_t)d >> 63);
376 anc = t - 1 - t%ad; // absolute value of nc
377 p = 63; // initialize p
378 q1 = two63/anc; // initialize q1 = 2p/abs(nc)
379 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
380 q2 = two63/ad; // initialize q2 = 2p/abs(d)
381 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
384 q1 = 2*q1; // update q1 = 2p/abs(nc)
385 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
386 if (r1 >= anc) { // must be unsigned comparison
390 q2 = 2*q2; // update q2 = 2p/abs(d)
391 r2 = 2*r2; // update r2 = rem(2p/abs(d))
392 if (r2 >= ad) { // must be unsigned comparison
397 } while (q1 < delta || (q1 == delta && r1 == 0));
400 if (d < 0) mag.m = -mag.m; // resulting magic number
401 mag.s = p - 64; // resulting shift
405 /// magicu - calculate the magic numbers required to codegen an integer udiv as
406 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
407 static mu magicu64(uint64_t d)
410 uint64_t nc, delta, q1, r1, q2, r2;
412 magu.a = 0; // initialize "add" indicator
414 p = 63; // initialize p
415 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
416 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
417 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
418 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
421 if (r1 >= nc - r1 ) {
422 q1 = 2*q1 + 1; // update q1
423 r1 = 2*r1 - nc; // update r1
426 q1 = 2*q1; // update q1
427 r1 = 2*r1; // update r1
429 if (r2 + 1 >= d - r2) {
430 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
431 q2 = 2*q2 + 1; // update q2
432 r2 = 2*r2 + 1 - d; // update r2
435 if (q2 >= 0x8000000000000000ull) magu.a = 1;
436 q2 = 2*q2; // update q2
437 r2 = 2*r2 + 1; // update r2
440 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
441 magu.m = q2 + 1; // resulting magic number
442 magu.s = p - 64; // resulting shift
446 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
447 // that selects between the values 1 and 0, making it equivalent to a setcc.
448 // Also, set the incoming LHS, RHS, and CC references to the appropriate
449 // nodes based on the type of node we are checking. This simplifies life a
450 // bit for the callers.
451 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
453 if (N.getOpcode() == ISD::SETCC) {
454 LHS = N.getOperand(0);
455 RHS = N.getOperand(1);
456 CC = N.getOperand(2);
459 if (N.getOpcode() == ISD::SELECT_CC &&
460 N.getOperand(2).getOpcode() == ISD::Constant &&
461 N.getOperand(3).getOpcode() == ISD::Constant &&
462 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
463 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
464 LHS = N.getOperand(0);
465 RHS = N.getOperand(1);
466 CC = N.getOperand(4);
472 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
473 // one use. If this is true, it allows the users to invert the operation for
474 // free when it is profitable to do so.
475 static bool isOneUseSetCC(SDOperand N) {
476 SDOperand N0, N1, N2;
477 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
482 // FIXME: This should probably go in the ISD class rather than being duplicated
484 static bool isCommutativeBinOp(unsigned Opcode) {
490 case ISD::XOR: return true;
491 default: return false; // FIXME: Need commutative info for user ops!
495 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
496 MVT::ValueType VT = N0.getValueType();
497 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
498 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
499 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
500 if (isa<ConstantSDNode>(N1)) {
501 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
502 AddToWorkList(OpNode.Val);
503 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
504 } else if (N0.hasOneUse()) {
505 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
506 AddToWorkList(OpNode.Val);
507 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
510 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
511 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
512 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
513 if (isa<ConstantSDNode>(N0)) {
514 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
515 AddToWorkList(OpNode.Val);
516 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
517 } else if (N1.hasOneUse()) {
518 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
519 AddToWorkList(OpNode.Val);
520 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
526 void DAGCombiner::Run(bool RunningAfterLegalize) {
527 // set the instance variable, so that the various visit routines may use it.
528 AfterLegalize = RunningAfterLegalize;
530 // Add all the dag nodes to the worklist.
531 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
532 E = DAG.allnodes_end(); I != E; ++I)
533 WorkList.push_back(I);
535 // Create a dummy node (which is not added to allnodes), that adds a reference
536 // to the root node, preventing it from being deleted, and tracking any
537 // changes of the root.
538 HandleSDNode Dummy(DAG.getRoot());
541 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
542 TargetLowering::DAGCombinerInfo
543 DagCombineInfo(DAG, !RunningAfterLegalize, this);
545 // while the worklist isn't empty, inspect the node on the end of it and
546 // try and combine it.
547 while (!WorkList.empty()) {
548 SDNode *N = WorkList.back();
551 // If N has no uses, it is dead. Make sure to revisit all N's operands once
552 // N is deleted from the DAG, since they too may now be dead or may have a
553 // reduced number of uses, allowing other xforms.
554 if (N->use_empty() && N != &Dummy) {
555 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
556 WorkList.push_back(N->getOperand(i).Val);
558 removeFromWorkList(N);
563 SDOperand RV = visit(N);
565 // If nothing happened, try a target-specific DAG combine.
567 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
568 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
569 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
574 // If we get back the same node we passed in, rather than a new node or
575 // zero, we know that the node must have defined multiple values and
576 // CombineTo was used. Since CombineTo takes care of the worklist
577 // mechanics for us, we have no work to do in this case.
579 DEBUG(std::cerr << "\nReplacing "; N->dump();
580 std::cerr << "\nWith: "; RV.Val->dump();
582 std::vector<SDNode*> NowDead;
583 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead);
585 // Push the new node and any users onto the worklist
586 WorkList.push_back(RV.Val);
587 AddUsersToWorkList(RV.Val);
589 // Nodes can end up on the worklist more than once. Make sure we do
590 // not process a node that has been replaced.
591 removeFromWorkList(N);
592 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
593 removeFromWorkList(NowDead[i]);
595 // Finally, since the node is now dead, remove it from the graph.
601 // If the root changed (e.g. it was a dead load, update the root).
602 DAG.setRoot(Dummy.getValue());
605 SDOperand DAGCombiner::visit(SDNode *N) {
606 switch(N->getOpcode()) {
608 case ISD::TokenFactor: return visitTokenFactor(N);
609 case ISD::ADD: return visitADD(N);
610 case ISD::SUB: return visitSUB(N);
611 case ISD::MUL: return visitMUL(N);
612 case ISD::SDIV: return visitSDIV(N);
613 case ISD::UDIV: return visitUDIV(N);
614 case ISD::SREM: return visitSREM(N);
615 case ISD::UREM: return visitUREM(N);
616 case ISD::MULHU: return visitMULHU(N);
617 case ISD::MULHS: return visitMULHS(N);
618 case ISD::AND: return visitAND(N);
619 case ISD::OR: return visitOR(N);
620 case ISD::XOR: return visitXOR(N);
621 case ISD::SHL: return visitSHL(N);
622 case ISD::SRA: return visitSRA(N);
623 case ISD::SRL: return visitSRL(N);
624 case ISD::CTLZ: return visitCTLZ(N);
625 case ISD::CTTZ: return visitCTTZ(N);
626 case ISD::CTPOP: return visitCTPOP(N);
627 case ISD::SELECT: return visitSELECT(N);
628 case ISD::SELECT_CC: return visitSELECT_CC(N);
629 case ISD::SETCC: return visitSETCC(N);
630 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
631 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
632 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
633 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
634 case ISD::TRUNCATE: return visitTRUNCATE(N);
635 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
636 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N);
637 case ISD::FADD: return visitFADD(N);
638 case ISD::FSUB: return visitFSUB(N);
639 case ISD::FMUL: return visitFMUL(N);
640 case ISD::FDIV: return visitFDIV(N);
641 case ISD::FREM: return visitFREM(N);
642 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
643 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
644 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
645 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
646 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
647 case ISD::FP_ROUND: return visitFP_ROUND(N);
648 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
649 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
650 case ISD::FNEG: return visitFNEG(N);
651 case ISD::FABS: return visitFABS(N);
652 case ISD::BRCOND: return visitBRCOND(N);
653 case ISD::BR_CC: return visitBR_CC(N);
654 case ISD::LOAD: return visitLOAD(N);
657 case ISD::ZEXTLOAD: return visitXEXTLOAD(N);
658 case ISD::STORE: return visitSTORE(N);
659 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
660 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
661 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N);
662 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
663 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N);
664 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD);
665 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB);
666 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL);
667 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV);
668 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV);
669 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND);
670 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR);
671 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR);
676 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
677 std::vector<SDOperand> Ops;
678 bool Changed = false;
680 // If the token factor has two operands and one is the entry token, replace
681 // the token factor with the other operand.
682 if (N->getNumOperands() == 2) {
683 if (N->getOperand(0).getOpcode() == ISD::EntryToken)
684 return N->getOperand(1);
685 if (N->getOperand(1).getOpcode() == ISD::EntryToken)
686 return N->getOperand(0);
689 // fold (tokenfactor (tokenfactor)) -> tokenfactor
690 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
691 SDOperand Op = N->getOperand(i);
692 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) {
693 AddToWorkList(Op.Val); // Remove dead node.
695 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j)
696 Ops.push_back(Op.getOperand(j));
702 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
706 SDOperand DAGCombiner::visitADD(SDNode *N) {
707 SDOperand N0 = N->getOperand(0);
708 SDOperand N1 = N->getOperand(1);
709 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
710 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
711 MVT::ValueType VT = N0.getValueType();
713 // fold (add c1, c2) -> c1+c2
715 return DAG.getNode(ISD::ADD, VT, N0, N1);
716 // canonicalize constant to RHS
718 return DAG.getNode(ISD::ADD, VT, N1, N0);
719 // fold (add x, 0) -> x
720 if (N1C && N1C->isNullValue())
722 // fold ((c1-A)+c2) -> (c1+c2)-A
723 if (N1C && N0.getOpcode() == ISD::SUB)
724 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
725 return DAG.getNode(ISD::SUB, VT,
726 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
729 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
732 // fold ((0-A) + B) -> B-A
733 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
734 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
735 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
736 // fold (A + (0-B)) -> A-B
737 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
738 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
739 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
740 // fold (A+(B-A)) -> B
741 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
742 return N1.getOperand(0);
744 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
745 return SDOperand(N, 0);
747 // fold (a+b) -> (a|b) iff a and b share no bits.
748 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
749 uint64_t LHSZero, LHSOne;
750 uint64_t RHSZero, RHSOne;
751 uint64_t Mask = MVT::getIntVTBitMask(VT);
752 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
754 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
756 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
757 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
758 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
759 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
760 return DAG.getNode(ISD::OR, VT, N0, N1);
767 SDOperand DAGCombiner::visitSUB(SDNode *N) {
768 SDOperand N0 = N->getOperand(0);
769 SDOperand N1 = N->getOperand(1);
770 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
771 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
772 MVT::ValueType VT = N0.getValueType();
774 // fold (sub x, x) -> 0
776 return DAG.getConstant(0, N->getValueType(0));
777 // fold (sub c1, c2) -> c1-c2
779 return DAG.getNode(ISD::SUB, VT, N0, N1);
780 // fold (sub x, c) -> (add x, -c)
782 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
784 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
785 return N0.getOperand(1);
787 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
788 return N0.getOperand(0);
792 SDOperand DAGCombiner::visitMUL(SDNode *N) {
793 SDOperand N0 = N->getOperand(0);
794 SDOperand N1 = N->getOperand(1);
795 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
796 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
797 MVT::ValueType VT = N0.getValueType();
799 // fold (mul c1, c2) -> c1*c2
801 return DAG.getNode(ISD::MUL, VT, N0, N1);
802 // canonicalize constant to RHS
804 return DAG.getNode(ISD::MUL, VT, N1, N0);
805 // fold (mul x, 0) -> 0
806 if (N1C && N1C->isNullValue())
808 // fold (mul x, -1) -> 0-x
809 if (N1C && N1C->isAllOnesValue())
810 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
811 // fold (mul x, (1 << c)) -> x << c
812 if (N1C && isPowerOf2_64(N1C->getValue()))
813 return DAG.getNode(ISD::SHL, VT, N0,
814 DAG.getConstant(Log2_64(N1C->getValue()),
815 TLI.getShiftAmountTy()));
816 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
817 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
818 // FIXME: If the input is something that is easily negated (e.g. a
819 // single-use add), we should put the negate there.
820 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
821 DAG.getNode(ISD::SHL, VT, N0,
822 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
823 TLI.getShiftAmountTy())));
826 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
827 if (N1C && N0.getOpcode() == ISD::SHL &&
828 isa<ConstantSDNode>(N0.getOperand(1))) {
829 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
830 AddToWorkList(C3.Val);
831 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
834 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
837 SDOperand Sh(0,0), Y(0,0);
838 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
839 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
840 N0.Val->hasOneUse()) {
842 } else if (N1.getOpcode() == ISD::SHL &&
843 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
847 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
848 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
851 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
852 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
853 isa<ConstantSDNode>(N0.getOperand(1))) {
854 return DAG.getNode(ISD::ADD, VT,
855 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
856 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
860 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
866 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
867 SDOperand N0 = N->getOperand(0);
868 SDOperand N1 = N->getOperand(1);
869 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
870 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
871 MVT::ValueType VT = N->getValueType(0);
873 // fold (sdiv c1, c2) -> c1/c2
874 if (N0C && N1C && !N1C->isNullValue())
875 return DAG.getNode(ISD::SDIV, VT, N0, N1);
876 // fold (sdiv X, 1) -> X
877 if (N1C && N1C->getSignExtended() == 1LL)
879 // fold (sdiv X, -1) -> 0-X
880 if (N1C && N1C->isAllOnesValue())
881 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
882 // If we know the sign bits of both operands are zero, strength reduce to a
883 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
884 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
885 if (TLI.MaskedValueIsZero(N1, SignBit) &&
886 TLI.MaskedValueIsZero(N0, SignBit))
887 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
888 // fold (sdiv X, pow2) -> simple ops after legalize
889 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
890 (isPowerOf2_64(N1C->getSignExtended()) ||
891 isPowerOf2_64(-N1C->getSignExtended()))) {
892 // If dividing by powers of two is cheap, then don't perform the following
894 if (TLI.isPow2DivCheap())
896 int64_t pow2 = N1C->getSignExtended();
897 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
898 unsigned lg2 = Log2_64(abs2);
899 // Splat the sign bit into the register
900 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
901 DAG.getConstant(MVT::getSizeInBits(VT)-1,
902 TLI.getShiftAmountTy()));
903 AddToWorkList(SGN.Val);
904 // Add (N0 < 0) ? abs2 - 1 : 0;
905 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
906 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
907 TLI.getShiftAmountTy()));
908 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
909 AddToWorkList(SRL.Val);
910 AddToWorkList(ADD.Val); // Divide by pow2
911 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
912 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
913 // If we're dividing by a positive value, we're done. Otherwise, we must
914 // negate the result.
917 AddToWorkList(SRA.Val);
918 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
920 // if integer divide is expensive and we satisfy the requirements, emit an
921 // alternate sequence.
922 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
923 !TLI.isIntDivCheap()) {
924 SDOperand Op = BuildSDIV(N);
925 if (Op.Val) return Op;
930 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
931 SDOperand N0 = N->getOperand(0);
932 SDOperand N1 = N->getOperand(1);
933 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
934 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
935 MVT::ValueType VT = N->getValueType(0);
937 // fold (udiv c1, c2) -> c1/c2
938 if (N0C && N1C && !N1C->isNullValue())
939 return DAG.getNode(ISD::UDIV, VT, N0, N1);
940 // fold (udiv x, (1 << c)) -> x >>u c
941 if (N1C && isPowerOf2_64(N1C->getValue()))
942 return DAG.getNode(ISD::SRL, VT, N0,
943 DAG.getConstant(Log2_64(N1C->getValue()),
944 TLI.getShiftAmountTy()));
945 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
946 if (N1.getOpcode() == ISD::SHL) {
947 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
948 if (isPowerOf2_64(SHC->getValue())) {
949 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
950 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
951 DAG.getConstant(Log2_64(SHC->getValue()),
953 AddToWorkList(Add.Val);
954 return DAG.getNode(ISD::SRL, VT, N0, Add);
958 // fold (udiv x, c) -> alternate
959 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
960 SDOperand Op = BuildUDIV(N);
961 if (Op.Val) return Op;
966 SDOperand DAGCombiner::visitSREM(SDNode *N) {
967 SDOperand N0 = N->getOperand(0);
968 SDOperand N1 = N->getOperand(1);
969 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
970 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
971 MVT::ValueType VT = N->getValueType(0);
973 // fold (srem c1, c2) -> c1%c2
974 if (N0C && N1C && !N1C->isNullValue())
975 return DAG.getNode(ISD::SREM, VT, N0, N1);
976 // If we know the sign bits of both operands are zero, strength reduce to a
977 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
978 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
979 if (TLI.MaskedValueIsZero(N1, SignBit) &&
980 TLI.MaskedValueIsZero(N0, SignBit))
981 return DAG.getNode(ISD::UREM, VT, N0, N1);
985 SDOperand DAGCombiner::visitUREM(SDNode *N) {
986 SDOperand N0 = N->getOperand(0);
987 SDOperand N1 = N->getOperand(1);
988 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
989 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
990 MVT::ValueType VT = N->getValueType(0);
992 // fold (urem c1, c2) -> c1%c2
993 if (N0C && N1C && !N1C->isNullValue())
994 return DAG.getNode(ISD::UREM, VT, N0, N1);
995 // fold (urem x, pow2) -> (and x, pow2-1)
996 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
997 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
998 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
999 if (N1.getOpcode() == ISD::SHL) {
1000 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1001 if (isPowerOf2_64(SHC->getValue())) {
1002 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
1003 AddToWorkList(Add.Val);
1004 return DAG.getNode(ISD::AND, VT, N0, Add);
1011 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
1012 SDOperand N0 = N->getOperand(0);
1013 SDOperand N1 = N->getOperand(1);
1014 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1016 // fold (mulhs x, 0) -> 0
1017 if (N1C && N1C->isNullValue())
1019 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1020 if (N1C && N1C->getValue() == 1)
1021 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
1022 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
1023 TLI.getShiftAmountTy()));
1027 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
1028 SDOperand N0 = N->getOperand(0);
1029 SDOperand N1 = N->getOperand(1);
1030 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1032 // fold (mulhu x, 0) -> 0
1033 if (N1C && N1C->isNullValue())
1035 // fold (mulhu x, 1) -> 0
1036 if (N1C && N1C->getValue() == 1)
1037 return DAG.getConstant(0, N0.getValueType());
1041 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1042 /// two operands of the same opcode, try to simplify it.
1043 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1044 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
1045 MVT::ValueType VT = N0.getValueType();
1046 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1048 // For each of OP in AND/OR/XOR:
1049 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1050 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1051 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1052 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1053 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1054 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1055 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1056 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1057 N0.getOperand(0).getValueType(),
1058 N0.getOperand(0), N1.getOperand(0));
1059 AddToWorkList(ORNode.Val);
1060 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1063 // For each of OP in SHL/SRL/SRA/AND...
1064 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1065 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1066 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1067 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1068 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1069 N0.getOperand(1) == N1.getOperand(1)) {
1070 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1071 N0.getOperand(0).getValueType(),
1072 N0.getOperand(0), N1.getOperand(0));
1073 AddToWorkList(ORNode.Val);
1074 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1080 SDOperand DAGCombiner::visitAND(SDNode *N) {
1081 SDOperand N0 = N->getOperand(0);
1082 SDOperand N1 = N->getOperand(1);
1083 SDOperand LL, LR, RL, RR, CC0, CC1;
1084 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1085 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1086 MVT::ValueType VT = N1.getValueType();
1087 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1089 // fold (and c1, c2) -> c1&c2
1091 return DAG.getNode(ISD::AND, VT, N0, N1);
1092 // canonicalize constant to RHS
1094 return DAG.getNode(ISD::AND, VT, N1, N0);
1095 // fold (and x, -1) -> x
1096 if (N1C && N1C->isAllOnesValue())
1098 // if (and x, c) is known to be zero, return 0
1099 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1100 return DAG.getConstant(0, VT);
1102 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1105 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1106 if (N1C && N0.getOpcode() == ISD::OR)
1107 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1108 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1110 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1111 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1112 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1113 if (TLI.MaskedValueIsZero(N0.getOperand(0),
1114 ~N1C->getValue() & InMask)) {
1115 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1118 // Replace uses of the AND with uses of the Zero extend node.
1121 // We actually want to replace all uses of the any_extend with the
1122 // zero_extend, to avoid duplicating things. This will later cause this
1123 // AND to be folded.
1124 CombineTo(N0.Val, Zext);
1125 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1128 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1129 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1130 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1131 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1133 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1134 MVT::isInteger(LL.getValueType())) {
1135 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1136 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1137 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1138 AddToWorkList(ORNode.Val);
1139 return DAG.getSetCC(VT, ORNode, LR, Op1);
1141 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1142 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1143 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1144 AddToWorkList(ANDNode.Val);
1145 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1147 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1148 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1149 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1150 AddToWorkList(ORNode.Val);
1151 return DAG.getSetCC(VT, ORNode, LR, Op1);
1154 // canonicalize equivalent to ll == rl
1155 if (LL == RR && LR == RL) {
1156 Op1 = ISD::getSetCCSwappedOperands(Op1);
1159 if (LL == RL && LR == RR) {
1160 bool isInteger = MVT::isInteger(LL.getValueType());
1161 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1162 if (Result != ISD::SETCC_INVALID)
1163 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1167 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1168 if (N0.getOpcode() == N1.getOpcode()) {
1169 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1170 if (Tmp.Val) return Tmp;
1173 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1174 // fold (and (sra)) -> (and (srl)) when possible.
1175 if (!MVT::isVector(VT) &&
1176 SimplifyDemandedBits(SDOperand(N, 0)))
1177 return SDOperand(N, 0);
1178 // fold (zext_inreg (extload x)) -> (zextload x)
1179 if (N0.getOpcode() == ISD::EXTLOAD) {
1180 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1181 // If we zero all the possible extended bits, then we can turn this into
1182 // a zextload if we are running before legalize or the operation is legal.
1183 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1184 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1185 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1186 N0.getOperand(1), N0.getOperand(2),
1189 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1190 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1193 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1194 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) {
1195 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1196 // If we zero all the possible extended bits, then we can turn this into
1197 // a zextload if we are running before legalize or the operation is legal.
1198 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1199 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1200 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1201 N0.getOperand(1), N0.getOperand(2),
1204 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1205 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1209 // fold (and (load x), 255) -> (zextload x, i8)
1210 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1212 (N0.getOpcode() == ISD::LOAD || N0.getOpcode() == ISD::EXTLOAD ||
1213 N0.getOpcode() == ISD::ZEXTLOAD) &&
1215 MVT::ValueType EVT, LoadedVT;
1216 if (N1C->getValue() == 255)
1218 else if (N1C->getValue() == 65535)
1220 else if (N1C->getValue() == ~0U)
1225 LoadedVT = N0.getOpcode() == ISD::LOAD ? VT :
1226 cast<VTSDNode>(N0.getOperand(3))->getVT();
1227 if (EVT != MVT::Other && LoadedVT > EVT &&
1228 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1229 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1230 // For big endian targets, we need to add an offset to the pointer to load
1231 // the correct bytes. For little endian systems, we merely need to read
1232 // fewer bytes from the same pointer.
1234 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1235 SDOperand NewPtr = N0.getOperand(1);
1236 if (!TLI.isLittleEndian())
1237 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1238 DAG.getConstant(PtrOff, PtrType));
1239 AddToWorkList(NewPtr.Val);
1241 DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), NewPtr,
1242 N0.getOperand(2), EVT);
1244 CombineTo(N0.Val, Load, Load.getValue(1));
1245 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1252 SDOperand DAGCombiner::visitOR(SDNode *N) {
1253 SDOperand N0 = N->getOperand(0);
1254 SDOperand N1 = N->getOperand(1);
1255 SDOperand LL, LR, RL, RR, CC0, CC1;
1256 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1257 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1258 MVT::ValueType VT = N1.getValueType();
1259 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1261 // fold (or c1, c2) -> c1|c2
1263 return DAG.getNode(ISD::OR, VT, N0, N1);
1264 // canonicalize constant to RHS
1266 return DAG.getNode(ISD::OR, VT, N1, N0);
1267 // fold (or x, 0) -> x
1268 if (N1C && N1C->isNullValue())
1270 // fold (or x, -1) -> -1
1271 if (N1C && N1C->isAllOnesValue())
1273 // fold (or x, c) -> c iff (x & ~c) == 0
1275 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1278 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1281 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1282 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1283 isa<ConstantSDNode>(N0.getOperand(1))) {
1284 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1285 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1287 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1289 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1290 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1291 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1292 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1294 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1295 MVT::isInteger(LL.getValueType())) {
1296 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1297 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1298 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1299 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1300 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1301 AddToWorkList(ORNode.Val);
1302 return DAG.getSetCC(VT, ORNode, LR, Op1);
1304 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1305 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1306 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1307 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1308 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1309 AddToWorkList(ANDNode.Val);
1310 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1313 // canonicalize equivalent to ll == rl
1314 if (LL == RR && LR == RL) {
1315 Op1 = ISD::getSetCCSwappedOperands(Op1);
1318 if (LL == RL && LR == RR) {
1319 bool isInteger = MVT::isInteger(LL.getValueType());
1320 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1321 if (Result != ISD::SETCC_INVALID)
1322 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1326 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1327 if (N0.getOpcode() == N1.getOpcode()) {
1328 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1329 if (Tmp.Val) return Tmp;
1332 // canonicalize shl to left side in a shl/srl pair, to match rotate
1333 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
1335 // check for rotl, rotr
1336 if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL &&
1337 N0.getOperand(0) == N1.getOperand(0) &&
1338 TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) {
1339 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1340 if (N0.getOperand(1).getOpcode() == ISD::Constant &&
1341 N1.getOperand(1).getOpcode() == ISD::Constant) {
1342 uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1343 uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1344 if ((c1val + c2val) == OpSizeInBits)
1345 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
1347 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1348 if (N1.getOperand(1).getOpcode() == ISD::SUB &&
1349 N0.getOperand(1) == N1.getOperand(1).getOperand(1))
1350 if (ConstantSDNode *SUBC =
1351 dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0)))
1352 if (SUBC->getValue() == OpSizeInBits)
1353 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
1354 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1355 if (N0.getOperand(1).getOpcode() == ISD::SUB &&
1356 N1.getOperand(1) == N0.getOperand(1).getOperand(1))
1357 if (ConstantSDNode *SUBC =
1358 dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0)))
1359 if (SUBC->getValue() == OpSizeInBits) {
1360 if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT))
1361 return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0),
1364 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0),
1371 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1372 SDOperand N0 = N->getOperand(0);
1373 SDOperand N1 = N->getOperand(1);
1374 SDOperand LHS, RHS, CC;
1375 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1376 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1377 MVT::ValueType VT = N0.getValueType();
1379 // fold (xor c1, c2) -> c1^c2
1381 return DAG.getNode(ISD::XOR, VT, N0, N1);
1382 // canonicalize constant to RHS
1384 return DAG.getNode(ISD::XOR, VT, N1, N0);
1385 // fold (xor x, 0) -> x
1386 if (N1C && N1C->isNullValue())
1389 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1392 // fold !(x cc y) -> (x !cc y)
1393 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1394 bool isInt = MVT::isInteger(LHS.getValueType());
1395 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1397 if (N0.getOpcode() == ISD::SETCC)
1398 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1399 if (N0.getOpcode() == ISD::SELECT_CC)
1400 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1401 assert(0 && "Unhandled SetCC Equivalent!");
1404 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1405 if (N1C && N1C->getValue() == 1 &&
1406 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1407 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1408 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1409 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1410 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1411 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1412 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1413 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1416 // fold !(x or y) -> (!x and !y) iff x or y are constants
1417 if (N1C && N1C->isAllOnesValue() &&
1418 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1419 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1420 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1421 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1422 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1423 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1424 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1425 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1428 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1429 if (N1C && N0.getOpcode() == ISD::XOR) {
1430 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1431 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1433 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1434 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1436 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1437 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1439 // fold (xor x, x) -> 0
1441 if (!MVT::isVector(VT)) {
1442 return DAG.getConstant(0, VT);
1443 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1444 // Produce a vector of zeros.
1445 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
1446 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
1447 return DAG.getNode(ISD::BUILD_VECTOR, VT, Ops);
1451 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
1452 if (N0.getOpcode() == N1.getOpcode()) {
1453 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1454 if (Tmp.Val) return Tmp;
1457 // Simplify the expression using non-local knowledge.
1458 if (!MVT::isVector(VT) &&
1459 SimplifyDemandedBits(SDOperand(N, 0)))
1460 return SDOperand(N, 0);
1465 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1466 SDOperand N0 = N->getOperand(0);
1467 SDOperand N1 = N->getOperand(1);
1468 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1469 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1470 MVT::ValueType VT = N0.getValueType();
1471 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1473 // fold (shl c1, c2) -> c1<<c2
1475 return DAG.getNode(ISD::SHL, VT, N0, N1);
1476 // fold (shl 0, x) -> 0
1477 if (N0C && N0C->isNullValue())
1479 // fold (shl x, c >= size(x)) -> undef
1480 if (N1C && N1C->getValue() >= OpSizeInBits)
1481 return DAG.getNode(ISD::UNDEF, VT);
1482 // fold (shl x, 0) -> x
1483 if (N1C && N1C->isNullValue())
1485 // if (shl x, c) is known to be zero, return 0
1486 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1487 return DAG.getConstant(0, VT);
1488 if (SimplifyDemandedBits(SDOperand(N, 0)))
1489 return SDOperand(N, 0);
1490 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1491 if (N1C && N0.getOpcode() == ISD::SHL &&
1492 N0.getOperand(1).getOpcode() == ISD::Constant) {
1493 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1494 uint64_t c2 = N1C->getValue();
1495 if (c1 + c2 > OpSizeInBits)
1496 return DAG.getConstant(0, VT);
1497 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1498 DAG.getConstant(c1 + c2, N1.getValueType()));
1500 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1501 // (srl (and x, -1 << c1), c1-c2)
1502 if (N1C && N0.getOpcode() == ISD::SRL &&
1503 N0.getOperand(1).getOpcode() == ISD::Constant) {
1504 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1505 uint64_t c2 = N1C->getValue();
1506 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1507 DAG.getConstant(~0ULL << c1, VT));
1509 return DAG.getNode(ISD::SHL, VT, Mask,
1510 DAG.getConstant(c2-c1, N1.getValueType()));
1512 return DAG.getNode(ISD::SRL, VT, Mask,
1513 DAG.getConstant(c1-c2, N1.getValueType()));
1515 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1516 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1517 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1518 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1519 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
1520 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1521 isa<ConstantSDNode>(N0.getOperand(1))) {
1522 return DAG.getNode(ISD::ADD, VT,
1523 DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1),
1524 DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1));
1529 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1530 SDOperand N0 = N->getOperand(0);
1531 SDOperand N1 = N->getOperand(1);
1532 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1533 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1534 MVT::ValueType VT = N0.getValueType();
1536 // fold (sra c1, c2) -> c1>>c2
1538 return DAG.getNode(ISD::SRA, VT, N0, N1);
1539 // fold (sra 0, x) -> 0
1540 if (N0C && N0C->isNullValue())
1542 // fold (sra -1, x) -> -1
1543 if (N0C && N0C->isAllOnesValue())
1545 // fold (sra x, c >= size(x)) -> undef
1546 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
1547 return DAG.getNode(ISD::UNDEF, VT);
1548 // fold (sra x, 0) -> x
1549 if (N1C && N1C->isNullValue())
1551 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
1553 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
1554 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
1557 default: EVT = MVT::Other; break;
1558 case 1: EVT = MVT::i1; break;
1559 case 8: EVT = MVT::i8; break;
1560 case 16: EVT = MVT::i16; break;
1561 case 32: EVT = MVT::i32; break;
1563 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
1564 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1565 DAG.getValueType(EVT));
1568 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
1569 if (N1C && N0.getOpcode() == ISD::SRA) {
1570 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1571 unsigned Sum = N1C->getValue() + C1->getValue();
1572 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
1573 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
1574 DAG.getConstant(Sum, N1C->getValueType(0)));
1578 // If the sign bit is known to be zero, switch this to a SRL.
1579 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
1580 return DAG.getNode(ISD::SRL, VT, N0, N1);
1584 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1585 SDOperand N0 = N->getOperand(0);
1586 SDOperand N1 = N->getOperand(1);
1587 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1588 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1589 MVT::ValueType VT = N0.getValueType();
1590 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1592 // fold (srl c1, c2) -> c1 >>u c2
1594 return DAG.getNode(ISD::SRL, VT, N0, N1);
1595 // fold (srl 0, x) -> 0
1596 if (N0C && N0C->isNullValue())
1598 // fold (srl x, c >= size(x)) -> undef
1599 if (N1C && N1C->getValue() >= OpSizeInBits)
1600 return DAG.getNode(ISD::UNDEF, VT);
1601 // fold (srl x, 0) -> x
1602 if (N1C && N1C->isNullValue())
1604 // if (srl x, c) is known to be zero, return 0
1605 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1606 return DAG.getConstant(0, VT);
1607 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1608 if (N1C && N0.getOpcode() == ISD::SRL &&
1609 N0.getOperand(1).getOpcode() == ISD::Constant) {
1610 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1611 uint64_t c2 = N1C->getValue();
1612 if (c1 + c2 > OpSizeInBits)
1613 return DAG.getConstant(0, VT);
1614 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1615 DAG.getConstant(c1 + c2, N1.getValueType()));
1618 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
1619 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1620 // Shifting in all undef bits?
1621 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
1622 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
1623 return DAG.getNode(ISD::UNDEF, VT);
1625 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
1626 AddToWorkList(SmallShift.Val);
1627 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
1630 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
1631 if (N1C && N0.getOpcode() == ISD::CTLZ &&
1632 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
1633 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
1634 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
1636 // If any of the input bits are KnownOne, then the input couldn't be all
1637 // zeros, thus the result of the srl will always be zero.
1638 if (KnownOne) return DAG.getConstant(0, VT);
1640 // If all of the bits input the to ctlz node are known to be zero, then
1641 // the result of the ctlz is "32" and the result of the shift is one.
1642 uint64_t UnknownBits = ~KnownZero & Mask;
1643 if (UnknownBits == 0) return DAG.getConstant(1, VT);
1645 // Otherwise, check to see if there is exactly one bit input to the ctlz.
1646 if ((UnknownBits & (UnknownBits-1)) == 0) {
1647 // Okay, we know that only that the single bit specified by UnknownBits
1648 // could be set on input to the CTLZ node. If this bit is set, the SRL
1649 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
1650 // to an SRL,XOR pair, which is likely to simplify more.
1651 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
1652 SDOperand Op = N0.getOperand(0);
1654 Op = DAG.getNode(ISD::SRL, VT, Op,
1655 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
1656 AddToWorkList(Op.Val);
1658 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
1665 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1666 SDOperand N0 = N->getOperand(0);
1667 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1668 MVT::ValueType VT = N->getValueType(0);
1670 // fold (ctlz c1) -> c2
1672 return DAG.getNode(ISD::CTLZ, VT, N0);
1676 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1677 SDOperand N0 = N->getOperand(0);
1678 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1679 MVT::ValueType VT = N->getValueType(0);
1681 // fold (cttz c1) -> c2
1683 return DAG.getNode(ISD::CTTZ, VT, N0);
1687 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1688 SDOperand N0 = N->getOperand(0);
1689 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1690 MVT::ValueType VT = N->getValueType(0);
1692 // fold (ctpop c1) -> c2
1694 return DAG.getNode(ISD::CTPOP, VT, N0);
1698 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1699 SDOperand N0 = N->getOperand(0);
1700 SDOperand N1 = N->getOperand(1);
1701 SDOperand N2 = N->getOperand(2);
1702 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1703 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1704 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1705 MVT::ValueType VT = N->getValueType(0);
1707 // fold select C, X, X -> X
1710 // fold select true, X, Y -> X
1711 if (N0C && !N0C->isNullValue())
1713 // fold select false, X, Y -> Y
1714 if (N0C && N0C->isNullValue())
1716 // fold select C, 1, X -> C | X
1717 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1718 return DAG.getNode(ISD::OR, VT, N0, N2);
1719 // fold select C, 0, X -> ~C & X
1720 // FIXME: this should check for C type == X type, not i1?
1721 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1722 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1723 AddToWorkList(XORNode.Val);
1724 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1726 // fold select C, X, 1 -> ~C | X
1727 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1728 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1729 AddToWorkList(XORNode.Val);
1730 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1732 // fold select C, X, 0 -> C & X
1733 // FIXME: this should check for C type == X type, not i1?
1734 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1735 return DAG.getNode(ISD::AND, VT, N0, N1);
1736 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1737 if (MVT::i1 == VT && N0 == N1)
1738 return DAG.getNode(ISD::OR, VT, N0, N2);
1739 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1740 if (MVT::i1 == VT && N0 == N2)
1741 return DAG.getNode(ISD::AND, VT, N0, N1);
1742 // If we can fold this based on the true/false value, do so.
1743 if (SimplifySelectOps(N, N1, N2))
1745 // fold selects based on a setcc into other things, such as min/max/abs
1746 if (N0.getOpcode() == ISD::SETCC)
1748 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1749 // having to say they don't support SELECT_CC on every type the DAG knows
1750 // about, since there is no way to mark an opcode illegal at all value types
1751 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1752 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1753 N1, N2, N0.getOperand(2));
1755 return SimplifySelect(N0, N1, N2);
1759 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1760 SDOperand N0 = N->getOperand(0);
1761 SDOperand N1 = N->getOperand(1);
1762 SDOperand N2 = N->getOperand(2);
1763 SDOperand N3 = N->getOperand(3);
1764 SDOperand N4 = N->getOperand(4);
1765 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1766 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1767 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1768 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1770 // Determine if the condition we're dealing with is constant
1771 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1772 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1774 // fold select_cc lhs, rhs, x, x, cc -> x
1778 // If we can fold this based on the true/false value, do so.
1779 if (SimplifySelectOps(N, N2, N3))
1782 // fold select_cc into other things, such as min/max/abs
1783 return SimplifySelectCC(N0, N1, N2, N3, CC);
1786 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1787 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1788 cast<CondCodeSDNode>(N->getOperand(2))->get());
1791 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1792 SDOperand N0 = N->getOperand(0);
1793 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1794 MVT::ValueType VT = N->getValueType(0);
1796 // fold (sext c1) -> c1
1798 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
1799 // fold (sext (sext x)) -> (sext x)
1800 if (N0.getOpcode() == ISD::SIGN_EXTEND)
1801 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1802 // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size.
1803 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
1805 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType())))
1806 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1807 DAG.getValueType(N0.getValueType()));
1808 // fold (sext (load x)) -> (sext (truncate (sextload x)))
1809 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1810 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){
1811 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1812 N0.getOperand(1), N0.getOperand(2),
1814 CombineTo(N, ExtLoad);
1815 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1816 ExtLoad.getValue(1));
1817 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1820 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
1821 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
1822 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
1824 SDOperand ExtLoad = DAG.getNode(ISD::SEXTLOAD, VT, N0.getOperand(0),
1825 N0.getOperand(1), N0.getOperand(2),
1827 CombineTo(N, ExtLoad);
1828 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1829 ExtLoad.getValue(1));
1830 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1836 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1837 SDOperand N0 = N->getOperand(0);
1838 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1839 MVT::ValueType VT = N->getValueType(0);
1841 // fold (zext c1) -> c1
1843 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1844 // fold (zext (zext x)) -> (zext x)
1845 if (N0.getOpcode() == ISD::ZERO_EXTEND)
1846 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1847 // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size.
1848 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
1849 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType())))
1850 return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType());
1851 // fold (zext (load x)) -> (zext (truncate (zextload x)))
1852 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1853 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){
1854 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1855 N0.getOperand(1), N0.getOperand(2),
1857 CombineTo(N, ExtLoad);
1858 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1859 ExtLoad.getValue(1));
1860 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1863 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
1864 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
1865 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
1867 SDOperand ExtLoad = DAG.getNode(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1868 N0.getOperand(1), N0.getOperand(2),
1870 CombineTo(N, ExtLoad);
1871 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1872 ExtLoad.getValue(1));
1873 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1878 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
1879 SDOperand N0 = N->getOperand(0);
1880 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1881 MVT::ValueType VT = N->getValueType(0);
1883 // fold (aext c1) -> c1
1885 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
1886 // fold (aext (aext x)) -> (aext x)
1887 // fold (aext (zext x)) -> (zext x)
1888 // fold (aext (sext x)) -> (sext x)
1889 if (N0.getOpcode() == ISD::ANY_EXTEND ||
1890 N0.getOpcode() == ISD::ZERO_EXTEND ||
1891 N0.getOpcode() == ISD::SIGN_EXTEND)
1892 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
1894 // fold (aext (truncate x)) -> x iff x size == zext size.
1895 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT)
1896 return N0.getOperand(0);
1897 // fold (aext (load x)) -> (aext (truncate (extload x)))
1898 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1899 (!AfterLegalize||TLI.isOperationLegal(ISD::EXTLOAD, N0.getValueType()))) {
1900 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0),
1901 N0.getOperand(1), N0.getOperand(2),
1903 CombineTo(N, ExtLoad);
1904 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1905 ExtLoad.getValue(1));
1906 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1909 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
1910 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
1911 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
1912 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD ||
1913 N0.getOpcode() == ISD::SEXTLOAD) &&
1915 SDOperand ExtLoad = DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0),
1916 N0.getOperand(1), N0.getOperand(2),
1918 CombineTo(N, ExtLoad);
1919 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1920 ExtLoad.getValue(1));
1921 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1927 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1928 SDOperand N0 = N->getOperand(0);
1929 SDOperand N1 = N->getOperand(1);
1930 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1931 MVT::ValueType VT = N->getValueType(0);
1932 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
1933 unsigned EVTBits = MVT::getSizeInBits(EVT);
1935 // fold (sext_in_reg c1) -> c1
1937 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT);
1938 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate);
1940 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1
1941 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1942 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1945 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
1946 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1947 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
1948 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
1950 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x)
1951 if (N0.getOpcode() == ISD::AssertSext &&
1952 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1955 // fold (sext_in_reg (sextload x)) -> (sextload x)
1956 if (N0.getOpcode() == ISD::SEXTLOAD &&
1957 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) {
1960 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1
1961 if (N0.getOpcode() == ISD::SETCC &&
1962 TLI.getSetCCResultContents() ==
1963 TargetLowering::ZeroOrNegativeOneSetCCResult)
1965 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
1966 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
1967 return DAG.getZeroExtendInReg(N0, EVT);
1968 // fold (sext_inreg (extload x)) -> (sextload x)
1969 if (N0.getOpcode() == ISD::EXTLOAD &&
1970 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1971 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1972 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1973 N0.getOperand(1), N0.getOperand(2),
1975 CombineTo(N, ExtLoad);
1976 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1977 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1979 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
1980 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() &&
1981 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1982 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1983 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1984 N0.getOperand(1), N0.getOperand(2),
1986 CombineTo(N, ExtLoad);
1987 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1988 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1993 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
1994 SDOperand N0 = N->getOperand(0);
1995 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1996 MVT::ValueType VT = N->getValueType(0);
1999 if (N0.getValueType() == N->getValueType(0))
2001 // fold (truncate c1) -> c1
2003 return DAG.getNode(ISD::TRUNCATE, VT, N0);
2004 // fold (truncate (truncate x)) -> (truncate x)
2005 if (N0.getOpcode() == ISD::TRUNCATE)
2006 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2007 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
2008 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){
2009 if (N0.getValueType() < VT)
2010 // if the source is smaller than the dest, we still need an extend
2011 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2012 else if (N0.getValueType() > VT)
2013 // if the source is larger than the dest, than we just need the truncate
2014 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2016 // if the source and dest are the same type, we can drop both the extend
2018 return N0.getOperand(0);
2020 // fold (truncate (load x)) -> (smaller load x)
2021 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
2022 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
2023 "Cannot truncate to larger type!");
2024 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2025 // For big endian targets, we need to add an offset to the pointer to load
2026 // the correct bytes. For little endian systems, we merely need to read
2027 // fewer bytes from the same pointer.
2029 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
2030 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) :
2031 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1),
2032 DAG.getConstant(PtrOff, PtrType));
2033 AddToWorkList(NewPtr.Val);
2034 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2));
2036 CombineTo(N0.Val, Load, Load.getValue(1));
2037 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2042 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
2043 SDOperand N0 = N->getOperand(0);
2044 MVT::ValueType VT = N->getValueType(0);
2046 // If the input is a constant, let getNode() fold it.
2047 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
2048 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2049 if (Res.Val != N) return Res;
2052 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
2053 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
2055 // fold (conv (load x)) -> (load (conv*)x)
2056 // FIXME: These xforms need to know that the resultant load doesn't need a
2057 // higher alignment than the original!
2058 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
2059 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1),
2062 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
2070 SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) {
2071 SDOperand N0 = N->getOperand(0);
2072 MVT::ValueType VT = N->getValueType(0);
2074 // If the input is a VBUILD_VECTOR with all constant elements, fold this now.
2075 // First check to see if this is all constant.
2076 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() &&
2077 VT == MVT::Vector) {
2078 bool isSimple = true;
2079 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i)
2080 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
2081 N0.getOperand(i).getOpcode() != ISD::Constant &&
2082 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
2087 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT();
2088 if (isSimple && !MVT::isVector(DestEltVT)) {
2089 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT);
2096 /// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector
2097 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
2098 /// destination element value type.
2099 SDOperand DAGCombiner::
2100 ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
2101 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
2103 // If this is already the right type, we're done.
2104 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
2106 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
2107 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
2109 // If this is a conversion of N elements of one type to N elements of another
2110 // type, convert each element. This handles FP<->INT cases.
2111 if (SrcBitSize == DstBitSize) {
2112 std::vector<SDOperand> Ops;
2113 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2114 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
2115 AddToWorkList(Ops.back().Val);
2117 Ops.push_back(*(BV->op_end()-2)); // Add num elements.
2118 Ops.push_back(DAG.getValueType(DstEltVT));
2119 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
2122 // Otherwise, we're growing or shrinking the elements. To avoid having to
2123 // handle annoying details of growing/shrinking FP values, we convert them to
2125 if (MVT::isFloatingPoint(SrcEltVT)) {
2126 // Convert the input float vector to a int vector where the elements are the
2128 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
2129 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2130 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val;
2134 // Now we know the input is an integer vector. If the output is a FP type,
2135 // convert to integer first, then to FP of the right size.
2136 if (MVT::isFloatingPoint(DstEltVT)) {
2137 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
2138 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2139 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val;
2141 // Next, convert to FP elements of the same size.
2142 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT);
2145 // Okay, we know the src/dst types are both integers of differing types.
2146 // Handling growing first.
2147 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
2148 if (SrcBitSize < DstBitSize) {
2149 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
2151 std::vector<SDOperand> Ops;
2152 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e;
2153 i += NumInputsPerOutput) {
2154 bool isLE = TLI.isLittleEndian();
2155 uint64_t NewBits = 0;
2156 bool EltIsUndef = true;
2157 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
2158 // Shift the previously computed bits over.
2159 NewBits <<= SrcBitSize;
2160 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
2161 if (Op.getOpcode() == ISD::UNDEF) continue;
2164 NewBits |= cast<ConstantSDNode>(Op)->getValue();
2168 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2170 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
2173 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2174 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2175 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
2178 // Finally, this must be the case where we are shrinking elements: each input
2179 // turns into multiple outputs.
2180 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
2181 std::vector<SDOperand> Ops;
2182 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2183 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
2184 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
2185 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2188 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
2190 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
2191 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
2192 OpVal >>= DstBitSize;
2193 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
2196 // For big endian targets, swap the order of the pieces of each element.
2197 if (!TLI.isLittleEndian())
2198 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
2200 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2201 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2202 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
2207 SDOperand DAGCombiner::visitFADD(SDNode *N) {
2208 SDOperand N0 = N->getOperand(0);
2209 SDOperand N1 = N->getOperand(1);
2210 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2211 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2212 MVT::ValueType VT = N->getValueType(0);
2214 // fold (fadd c1, c2) -> c1+c2
2216 return DAG.getNode(ISD::FADD, VT, N0, N1);
2217 // canonicalize constant to RHS
2218 if (N0CFP && !N1CFP)
2219 return DAG.getNode(ISD::FADD, VT, N1, N0);
2220 // fold (A + (-B)) -> A-B
2221 if (N1.getOpcode() == ISD::FNEG)
2222 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
2223 // fold ((-A) + B) -> B-A
2224 if (N0.getOpcode() == ISD::FNEG)
2225 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
2229 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
2230 SDOperand N0 = N->getOperand(0);
2231 SDOperand N1 = N->getOperand(1);
2232 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2233 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2234 MVT::ValueType VT = N->getValueType(0);
2236 // fold (fsub c1, c2) -> c1-c2
2238 return DAG.getNode(ISD::FSUB, VT, N0, N1);
2239 // fold (A-(-B)) -> A+B
2240 if (N1.getOpcode() == ISD::FNEG)
2241 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
2245 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
2246 SDOperand N0 = N->getOperand(0);
2247 SDOperand N1 = N->getOperand(1);
2248 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2249 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2250 MVT::ValueType VT = N->getValueType(0);
2252 // fold (fmul c1, c2) -> c1*c2
2254 return DAG.getNode(ISD::FMUL, VT, N0, N1);
2255 // canonicalize constant to RHS
2256 if (N0CFP && !N1CFP)
2257 return DAG.getNode(ISD::FMUL, VT, N1, N0);
2258 // fold (fmul X, 2.0) -> (fadd X, X)
2259 if (N1CFP && N1CFP->isExactlyValue(+2.0))
2260 return DAG.getNode(ISD::FADD, VT, N0, N0);
2264 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
2265 SDOperand N0 = N->getOperand(0);
2266 SDOperand N1 = N->getOperand(1);
2267 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2268 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2269 MVT::ValueType VT = N->getValueType(0);
2271 // fold (fdiv c1, c2) -> c1/c2
2273 return DAG.getNode(ISD::FDIV, VT, N0, N1);
2277 SDOperand DAGCombiner::visitFREM(SDNode *N) {
2278 SDOperand N0 = N->getOperand(0);
2279 SDOperand N1 = N->getOperand(1);
2280 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2281 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2282 MVT::ValueType VT = N->getValueType(0);
2284 // fold (frem c1, c2) -> fmod(c1,c2)
2286 return DAG.getNode(ISD::FREM, VT, N0, N1);
2290 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
2291 SDOperand N0 = N->getOperand(0);
2292 SDOperand N1 = N->getOperand(1);
2293 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2294 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2295 MVT::ValueType VT = N->getValueType(0);
2297 if (N0CFP && N1CFP) // Constant fold
2298 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
2301 // copysign(x, c1) -> fabs(x) iff ispos(c1)
2302 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
2307 u.d = N1CFP->getValue();
2309 return DAG.getNode(ISD::FABS, VT, N0);
2311 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
2314 // copysign(fabs(x), y) -> copysign(x, y)
2315 // copysign(fneg(x), y) -> copysign(x, y)
2316 // copysign(copysign(x,z), y) -> copysign(x, y)
2317 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
2318 N0.getOpcode() == ISD::FCOPYSIGN)
2319 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
2321 // copysign(x, abs(y)) -> abs(x)
2322 if (N1.getOpcode() == ISD::FABS)
2323 return DAG.getNode(ISD::FABS, VT, N0);
2325 // copysign(x, copysign(y,z)) -> copysign(x, z)
2326 if (N1.getOpcode() == ISD::FCOPYSIGN)
2327 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
2329 // copysign(x, fp_extend(y)) -> copysign(x, y)
2330 // copysign(x, fp_round(y)) -> copysign(x, y)
2331 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
2332 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
2339 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
2340 SDOperand N0 = N->getOperand(0);
2341 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2342 MVT::ValueType VT = N->getValueType(0);
2344 // fold (sint_to_fp c1) -> c1fp
2346 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
2350 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
2351 SDOperand N0 = N->getOperand(0);
2352 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2353 MVT::ValueType VT = N->getValueType(0);
2355 // fold (uint_to_fp c1) -> c1fp
2357 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
2361 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
2362 SDOperand N0 = N->getOperand(0);
2363 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2364 MVT::ValueType VT = N->getValueType(0);
2366 // fold (fp_to_sint c1fp) -> c1
2368 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
2372 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
2373 SDOperand N0 = N->getOperand(0);
2374 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2375 MVT::ValueType VT = N->getValueType(0);
2377 // fold (fp_to_uint c1fp) -> c1
2379 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
2383 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
2384 SDOperand N0 = N->getOperand(0);
2385 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2386 MVT::ValueType VT = N->getValueType(0);
2388 // fold (fp_round c1fp) -> c1fp
2390 return DAG.getNode(ISD::FP_ROUND, VT, N0);
2392 // fold (fp_round (fp_extend x)) -> x
2393 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
2394 return N0.getOperand(0);
2396 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
2397 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
2398 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
2399 AddToWorkList(Tmp.Val);
2400 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
2406 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
2407 SDOperand N0 = N->getOperand(0);
2408 MVT::ValueType VT = N->getValueType(0);
2409 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2410 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2412 // fold (fp_round_inreg c1fp) -> c1fp
2414 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
2415 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
2420 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
2421 SDOperand N0 = N->getOperand(0);
2422 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2423 MVT::ValueType VT = N->getValueType(0);
2425 // fold (fp_extend c1fp) -> c1fp
2427 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
2429 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
2430 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
2431 (!AfterLegalize||TLI.isOperationLegal(ISD::EXTLOAD, N0.getValueType()))) {
2432 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0),
2433 N0.getOperand(1), N0.getOperand(2),
2435 CombineTo(N, ExtLoad);
2436 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
2437 ExtLoad.getValue(1));
2438 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2445 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
2446 SDOperand N0 = N->getOperand(0);
2447 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2448 MVT::ValueType VT = N->getValueType(0);
2450 // fold (fneg c1) -> -c1
2452 return DAG.getNode(ISD::FNEG, VT, N0);
2453 // fold (fneg (sub x, y)) -> (sub y, x)
2454 if (N0.getOpcode() == ISD::SUB)
2455 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0));
2456 // fold (fneg (fneg x)) -> x
2457 if (N0.getOpcode() == ISD::FNEG)
2458 return N0.getOperand(0);
2462 SDOperand DAGCombiner::visitFABS(SDNode *N) {
2463 SDOperand N0 = N->getOperand(0);
2464 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2465 MVT::ValueType VT = N->getValueType(0);
2467 // fold (fabs c1) -> fabs(c1)
2469 return DAG.getNode(ISD::FABS, VT, N0);
2470 // fold (fabs (fabs x)) -> (fabs x)
2471 if (N0.getOpcode() == ISD::FABS)
2472 return N->getOperand(0);
2473 // fold (fabs (fneg x)) -> (fabs x)
2474 // fold (fabs (fcopysign x, y)) -> (fabs x)
2475 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
2476 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
2481 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
2482 SDOperand Chain = N->getOperand(0);
2483 SDOperand N1 = N->getOperand(1);
2484 SDOperand N2 = N->getOperand(2);
2485 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2487 // never taken branch, fold to chain
2488 if (N1C && N1C->isNullValue())
2490 // unconditional branch
2491 if (N1C && N1C->getValue() == 1)
2492 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2493 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
2495 if (N1.getOpcode() == ISD::SETCC &&
2496 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
2497 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
2498 N1.getOperand(0), N1.getOperand(1), N2);
2503 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
2505 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
2506 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2507 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2509 // Use SimplifySetCC to simplify SETCC's.
2510 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2511 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2513 // fold br_cc true, dest -> br dest (unconditional branch)
2514 if (SCCC && SCCC->getValue())
2515 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2517 // fold br_cc false, dest -> unconditional fall through
2518 if (SCCC && SCCC->isNullValue())
2519 return N->getOperand(0);
2520 // fold to a simpler setcc
2521 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2522 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2523 Simp.getOperand(2), Simp.getOperand(0),
2524 Simp.getOperand(1), N->getOperand(4));
2528 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
2529 SDOperand Chain = N->getOperand(0);
2530 SDOperand Ptr = N->getOperand(1);
2531 SDOperand SrcValue = N->getOperand(2);
2533 // If there are no uses of the loaded value, change uses of the chain value
2534 // into uses of the chain input (i.e. delete the dead load).
2535 if (N->hasNUsesOfValue(0, 0))
2536 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
2538 // If this load is directly stored, replace the load value with the stored
2540 // TODO: Handle store large -> read small portion.
2541 // TODO: Handle TRUNCSTORE/EXTLOAD
2542 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2543 Chain.getOperand(1).getValueType() == N->getValueType(0))
2544 return CombineTo(N, Chain.getOperand(1), Chain);
2549 /// visitXEXTLOAD - Handle EXTLOAD/ZEXTLOAD/SEXTLOAD.
2550 SDOperand DAGCombiner::visitXEXTLOAD(SDNode *N) {
2551 SDOperand Chain = N->getOperand(0);
2552 SDOperand Ptr = N->getOperand(1);
2553 SDOperand SrcValue = N->getOperand(2);
2554 SDOperand EVT = N->getOperand(3);
2556 // If there are no uses of the loaded value, change uses of the chain value
2557 // into uses of the chain input (i.e. delete the dead load).
2558 if (N->hasNUsesOfValue(0, 0))
2559 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
2564 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
2565 SDOperand Chain = N->getOperand(0);
2566 SDOperand Value = N->getOperand(1);
2567 SDOperand Ptr = N->getOperand(2);
2568 SDOperand SrcValue = N->getOperand(3);
2570 // If this is a store that kills a previous store, remove the previous store.
2571 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2572 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ &&
2573 // Make sure that these stores are the same value type:
2574 // FIXME: we really care that the second store is >= size of the first.
2575 Value.getValueType() == Chain.getOperand(1).getValueType()) {
2576 // Create a new store of Value that replaces both stores.
2577 SDNode *PrevStore = Chain.Val;
2578 if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
2580 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other,
2581 PrevStore->getOperand(0), Value, Ptr,
2583 CombineTo(N, NewStore); // Nuke this store.
2584 CombineTo(PrevStore, NewStore); // Nuke the previous store.
2585 return SDOperand(N, 0);
2588 // If this is a store of a bit convert, store the input value.
2589 // FIXME: This needs to know that the resultant store does not need a
2590 // higher alignment than the original.
2591 if (0 && Value.getOpcode() == ISD::BIT_CONVERT)
2592 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0),
2598 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
2599 SDOperand InVec = N->getOperand(0);
2600 SDOperand InVal = N->getOperand(1);
2601 SDOperand EltNo = N->getOperand(2);
2603 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
2604 // vector with the inserted element.
2605 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2606 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2607 std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2608 if (Elt < Ops.size())
2610 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), Ops);
2616 SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
2617 SDOperand InVec = N->getOperand(0);
2618 SDOperand InVal = N->getOperand(1);
2619 SDOperand EltNo = N->getOperand(2);
2620 SDOperand NumElts = N->getOperand(3);
2621 SDOperand EltType = N->getOperand(4);
2623 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new
2624 // vector with the inserted element.
2625 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2626 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2627 std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2628 if (Elt < Ops.size()-2)
2630 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), Ops);
2636 SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
2637 unsigned NumInScalars = N->getNumOperands()-2;
2638 SDOperand NumElts = N->getOperand(NumInScalars);
2639 SDOperand EltType = N->getOperand(NumInScalars+1);
2641 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT
2642 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most
2643 // two distinct vectors, turn this into a shuffle node.
2644 SDOperand VecIn1, VecIn2;
2645 for (unsigned i = 0; i != NumInScalars; ++i) {
2646 // Ignore undef inputs.
2647 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
2649 // If this input is something other than a VEXTRACT_VECTOR_ELT with a
2650 // constant index, bail out.
2651 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT ||
2652 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
2653 VecIn1 = VecIn2 = SDOperand(0, 0);
2657 // If the input vector type disagrees with the result of the vbuild_vector,
2658 // we can't make a shuffle.
2659 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
2660 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts ||
2661 *(ExtractedFromVec.Val->op_end()-1) != EltType) {
2662 VecIn1 = VecIn2 = SDOperand(0, 0);
2666 // Otherwise, remember this. We allow up to two distinct input vectors.
2667 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
2670 if (VecIn1.Val == 0) {
2671 VecIn1 = ExtractedFromVec;
2672 } else if (VecIn2.Val == 0) {
2673 VecIn2 = ExtractedFromVec;
2676 VecIn1 = VecIn2 = SDOperand(0, 0);
2681 // If everything is good, we can make a shuffle operation.
2683 std::vector<SDOperand> BuildVecIndices;
2684 for (unsigned i = 0; i != NumInScalars; ++i) {
2685 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
2686 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
2690 SDOperand Extract = N->getOperand(i);
2692 // If extracting from the first vector, just use the index directly.
2693 if (Extract.getOperand(0) == VecIn1) {
2694 BuildVecIndices.push_back(Extract.getOperand(1));
2698 // Otherwise, use InIdx + VecSize
2699 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
2700 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32));
2703 // Add count and size info.
2704 BuildVecIndices.push_back(NumElts);
2705 BuildVecIndices.push_back(DAG.getValueType(MVT::i32));
2707 // Return the new VVECTOR_SHUFFLE node.
2708 std::vector<SDOperand> Ops;
2709 Ops.push_back(VecIn1);
2711 Ops.push_back(VecIn2);
2713 // Use an undef vbuild_vector as input for the second operand.
2714 std::vector<SDOperand> UnOps(NumInScalars,
2715 DAG.getNode(ISD::UNDEF,
2716 cast<VTSDNode>(EltType)->getVT()));
2717 UnOps.push_back(NumElts);
2718 UnOps.push_back(EltType);
2719 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, UnOps));
2720 AddToWorkList(Ops.back().Val);
2722 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector, BuildVecIndices));
2723 Ops.push_back(NumElts);
2724 Ops.push_back(EltType);
2725 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops);
2731 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
2732 SDOperand ShufMask = N->getOperand(2);
2733 unsigned NumElts = ShufMask.getNumOperands();
2735 // If the shuffle mask is an identity operation on the LHS, return the LHS.
2736 bool isIdentity = true;
2737 for (unsigned i = 0; i != NumElts; ++i) {
2738 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2739 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
2744 if (isIdentity) return N->getOperand(0);
2746 // If the shuffle mask is an identity operation on the RHS, return the RHS.
2748 for (unsigned i = 0; i != NumElts; ++i) {
2749 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2750 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
2755 if (isIdentity) return N->getOperand(1);
2757 // If the LHS and the RHS are the same node, turn the RHS into an undef.
2758 if (N->getOperand(0) == N->getOperand(1)) {
2759 if (N->getOperand(0).getOpcode() == ISD::UNDEF)
2760 return DAG.getNode(ISD::UNDEF, N->getValueType(0));
2761 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
2763 std::vector<SDOperand> MappedOps;
2764 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
2765 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
2766 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
2767 MappedOps.push_back(ShufMask.getOperand(i));
2770 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
2771 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
2774 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
2776 AddToWorkList(ShufMask.Val);
2777 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
2779 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
2786 SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
2787 SDOperand ShufMask = N->getOperand(2);
2788 unsigned NumElts = ShufMask.getNumOperands()-2;
2790 // If the shuffle mask is an identity operation on the LHS, return the LHS.
2791 bool isIdentity = true;
2792 for (unsigned i = 0; i != NumElts; ++i) {
2793 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2794 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
2799 if (isIdentity) return N->getOperand(0);
2801 // If the shuffle mask is an identity operation on the RHS, return the RHS.
2803 for (unsigned i = 0; i != NumElts; ++i) {
2804 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2805 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
2810 if (isIdentity) return N->getOperand(1);
2812 // If the LHS and the RHS are the same node, turn the RHS into an undef.
2813 if (N->getOperand(0) == N->getOperand(1)) {
2814 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
2816 std::vector<SDOperand> MappedOps;
2817 for (unsigned i = 0; i != NumElts; ++i) {
2818 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
2819 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
2820 MappedOps.push_back(ShufMask.getOperand(i));
2823 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
2824 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
2827 // Add the type/#elts values.
2828 MappedOps.push_back(ShufMask.getOperand(NumElts));
2829 MappedOps.push_back(ShufMask.getOperand(NumElts+1));
2831 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(),
2833 AddToWorkList(ShufMask.Val);
2835 // Build the undef vector.
2836 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType());
2837 for (unsigned i = 0; i != NumElts; ++i)
2838 MappedOps[i] = UDVal;
2839 MappedOps[NumElts ] = *(N->getOperand(0).Val->op_end()-2);
2840 MappedOps[NumElts+1] = *(N->getOperand(0).Val->op_end()-1);
2841 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, MappedOps);
2843 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
2844 N->getOperand(0), UDVal, ShufMask,
2845 MappedOps[NumElts], MappedOps[NumElts+1]);
2851 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
2852 /// a VAND to a vector_shuffle with the destination vector and a zero vector.
2853 /// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
2854 /// vector_shuffle V, Zero, <0, 4, 2, 4>
2855 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
2856 SDOperand LHS = N->getOperand(0);
2857 SDOperand RHS = N->getOperand(1);
2858 if (N->getOpcode() == ISD::VAND) {
2859 SDOperand DstVecSize = *(LHS.Val->op_end()-2);
2860 SDOperand DstVecEVT = *(LHS.Val->op_end()-1);
2861 if (RHS.getOpcode() == ISD::VBIT_CONVERT)
2862 RHS = RHS.getOperand(0);
2863 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) {
2864 std::vector<SDOperand> IdxOps;
2865 unsigned NumOps = RHS.getNumOperands();
2866 unsigned NumElts = NumOps-2;
2867 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT();
2868 for (unsigned i = 0; i != NumElts; ++i) {
2869 SDOperand Elt = RHS.getOperand(i);
2870 if (!isa<ConstantSDNode>(Elt))
2872 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
2873 IdxOps.push_back(DAG.getConstant(i, EVT));
2874 else if (cast<ConstantSDNode>(Elt)->isNullValue())
2875 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
2880 // Let's see if the target supports this vector_shuffle.
2881 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
2884 // Return the new VVECTOR_SHUFFLE node.
2885 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32);
2886 SDOperand EVTNode = DAG.getValueType(EVT);
2887 std::vector<SDOperand> Ops;
2888 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode, EVTNode);
2890 AddToWorkList(LHS.Val);
2891 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
2892 ZeroOps.push_back(NumEltsNode);
2893 ZeroOps.push_back(EVTNode);
2894 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, ZeroOps));
2895 IdxOps.push_back(NumEltsNode);
2896 IdxOps.push_back(EVTNode);
2897 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, IdxOps));
2898 Ops.push_back(NumEltsNode);
2899 Ops.push_back(EVTNode);
2900 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops);
2901 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) {
2902 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
2903 DstVecSize, DstVecEVT);
2911 /// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates
2912 /// the scalar operation of the vop if it is operating on an integer vector
2913 /// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD).
2914 SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
2915 ISD::NodeType FPOp) {
2916 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT();
2917 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp;
2918 SDOperand LHS = N->getOperand(0);
2919 SDOperand RHS = N->getOperand(1);
2920 SDOperand Shuffle = XformToShuffleWithZero(N);
2921 if (Shuffle.Val) return Shuffle;
2923 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold
2925 if (LHS.getOpcode() == ISD::VBUILD_VECTOR &&
2926 RHS.getOpcode() == ISD::VBUILD_VECTOR) {
2927 std::vector<SDOperand> Ops;
2928 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
2929 SDOperand LHSOp = LHS.getOperand(i);
2930 SDOperand RHSOp = RHS.getOperand(i);
2931 // If these two elements can't be folded, bail out.
2932 if ((LHSOp.getOpcode() != ISD::UNDEF &&
2933 LHSOp.getOpcode() != ISD::Constant &&
2934 LHSOp.getOpcode() != ISD::ConstantFP) ||
2935 (RHSOp.getOpcode() != ISD::UNDEF &&
2936 RHSOp.getOpcode() != ISD::Constant &&
2937 RHSOp.getOpcode() != ISD::ConstantFP))
2939 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
2940 AddToWorkList(Ops.back().Val);
2941 assert((Ops.back().getOpcode() == ISD::UNDEF ||
2942 Ops.back().getOpcode() == ISD::Constant ||
2943 Ops.back().getOpcode() == ISD::ConstantFP) &&
2944 "Scalar binop didn't fold!");
2947 if (Ops.size() == LHS.getNumOperands()-2) {
2948 Ops.push_back(*(LHS.Val->op_end()-2));
2949 Ops.push_back(*(LHS.Val->op_end()-1));
2950 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
2957 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
2958 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
2960 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
2961 cast<CondCodeSDNode>(N0.getOperand(2))->get());
2962 // If we got a simplified select_cc node back from SimplifySelectCC, then
2963 // break it down into a new SETCC node, and a new SELECT node, and then return
2964 // the SELECT node, since we were called with a SELECT node.
2966 // Check to see if we got a select_cc back (to turn into setcc/select).
2967 // Otherwise, just return whatever node we got back, like fabs.
2968 if (SCC.getOpcode() == ISD::SELECT_CC) {
2969 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
2970 SCC.getOperand(0), SCC.getOperand(1),
2972 AddToWorkList(SETCC.Val);
2973 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
2974 SCC.getOperand(3), SETCC);
2981 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
2982 /// are the two values being selected between, see if we can simplify the
2985 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
2988 // If this is a select from two identical things, try to pull the operation
2989 // through the select.
2990 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
2992 std::cerr << "SELECT: ["; LHS.Val->dump();
2993 std::cerr << "] ["; RHS.Val->dump();
2997 // If this is a load and the token chain is identical, replace the select
2998 // of two loads with a load through a select of the address to load from.
2999 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
3000 // constants have been dropped into the constant pool.
3001 if ((LHS.getOpcode() == ISD::LOAD ||
3002 LHS.getOpcode() == ISD::EXTLOAD ||
3003 LHS.getOpcode() == ISD::ZEXTLOAD ||
3004 LHS.getOpcode() == ISD::SEXTLOAD) &&
3005 // Token chains must be identical.
3006 LHS.getOperand(0) == RHS.getOperand(0) &&
3007 // If this is an EXTLOAD, the VT's must match.
3008 (LHS.getOpcode() == ISD::LOAD ||
3009 LHS.getOperand(3) == RHS.getOperand(3))) {
3010 // FIXME: this conflates two src values, discarding one. This is not
3011 // the right thing to do, but nothing uses srcvalues now. When they do,
3012 // turn SrcValue into a list of locations.
3014 if (TheSelect->getOpcode() == ISD::SELECT)
3015 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(),
3016 TheSelect->getOperand(0), LHS.getOperand(1),
3019 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(),
3020 TheSelect->getOperand(0),
3021 TheSelect->getOperand(1),
3022 LHS.getOperand(1), RHS.getOperand(1),
3023 TheSelect->getOperand(4));
3026 if (LHS.getOpcode() == ISD::LOAD)
3027 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0),
3028 Addr, LHS.getOperand(2));
3030 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0),
3031 LHS.getOperand(0), Addr, LHS.getOperand(2),
3032 cast<VTSDNode>(LHS.getOperand(3))->getVT());
3033 // Users of the select now use the result of the load.
3034 CombineTo(TheSelect, Load);
3036 // Users of the old loads now use the new load's chain. We know the
3037 // old-load value is dead now.
3038 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
3039 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
3047 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
3048 SDOperand N2, SDOperand N3,
3051 MVT::ValueType VT = N2.getValueType();
3052 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
3053 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
3054 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
3055 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
3057 // Determine if the condition we're dealing with is constant
3058 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
3059 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
3061 // fold select_cc true, x, y -> x
3062 if (SCCC && SCCC->getValue())
3064 // fold select_cc false, x, y -> y
3065 if (SCCC && SCCC->getValue() == 0)
3068 // Check to see if we can simplify the select into an fabs node
3069 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
3070 // Allow either -0.0 or 0.0
3071 if (CFP->getValue() == 0.0) {
3072 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
3073 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
3074 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
3075 N2 == N3.getOperand(0))
3076 return DAG.getNode(ISD::FABS, VT, N0);
3078 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
3079 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
3080 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
3081 N2.getOperand(0) == N3)
3082 return DAG.getNode(ISD::FABS, VT, N3);
3086 // Check to see if we can perform the "gzip trick", transforming
3087 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
3088 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() &&
3089 MVT::isInteger(N0.getValueType()) &&
3090 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) {
3091 MVT::ValueType XType = N0.getValueType();
3092 MVT::ValueType AType = N2.getValueType();
3093 if (XType >= AType) {
3094 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
3095 // single-bit constant.
3096 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
3097 unsigned ShCtV = Log2_64(N2C->getValue());
3098 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
3099 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
3100 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
3101 AddToWorkList(Shift.Val);
3102 if (XType > AType) {
3103 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3104 AddToWorkList(Shift.Val);
3106 return DAG.getNode(ISD::AND, AType, Shift, N2);
3108 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3109 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3110 TLI.getShiftAmountTy()));
3111 AddToWorkList(Shift.Val);
3112 if (XType > AType) {
3113 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3114 AddToWorkList(Shift.Val);
3116 return DAG.getNode(ISD::AND, AType, Shift, N2);
3120 // fold select C, 16, 0 -> shl C, 4
3121 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
3122 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
3123 // Get a SetCC of the condition
3124 // FIXME: Should probably make sure that setcc is legal if we ever have a
3125 // target where it isn't.
3126 SDOperand Temp, SCC;
3127 // cast from setcc result type to select result type
3128 if (AfterLegalize) {
3129 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3130 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
3132 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
3133 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
3135 AddToWorkList(SCC.Val);
3136 AddToWorkList(Temp.Val);
3137 // shl setcc result by log2 n2c
3138 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
3139 DAG.getConstant(Log2_64(N2C->getValue()),
3140 TLI.getShiftAmountTy()));
3143 // Check to see if this is the equivalent of setcc
3144 // FIXME: Turn all of these into setcc if setcc if setcc is legal
3145 // otherwise, go ahead with the folds.
3146 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
3147 MVT::ValueType XType = N0.getValueType();
3148 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
3149 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3150 if (Res.getValueType() != VT)
3151 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
3155 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
3156 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
3157 TLI.isOperationLegal(ISD::CTLZ, XType)) {
3158 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
3159 return DAG.getNode(ISD::SRL, XType, Ctlz,
3160 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
3161 TLI.getShiftAmountTy()));
3163 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
3164 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
3165 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
3167 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
3168 DAG.getConstant(~0ULL, XType));
3169 return DAG.getNode(ISD::SRL, XType,
3170 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
3171 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3172 TLI.getShiftAmountTy()));
3174 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
3175 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
3176 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
3177 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3178 TLI.getShiftAmountTy()));
3179 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
3183 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
3184 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
3185 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
3186 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
3187 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
3188 MVT::ValueType XType = N0.getValueType();
3189 if (SubC->isNullValue() && MVT::isInteger(XType)) {
3190 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3191 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3192 TLI.getShiftAmountTy()));
3193 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
3194 AddToWorkList(Shift.Val);
3195 AddToWorkList(Add.Val);
3196 return DAG.getNode(ISD::XOR, XType, Add, Shift);
3204 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
3205 SDOperand N1, ISD::CondCode Cond,
3206 bool foldBooleans) {
3207 // These setcc operations always fold.
3211 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
3213 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
3216 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
3217 uint64_t C1 = N1C->getValue();
3218 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
3219 uint64_t C0 = N0C->getValue();
3221 // Sign extend the operands if required
3222 if (ISD::isSignedIntSetCC(Cond)) {
3223 C0 = N0C->getSignExtended();
3224 C1 = N1C->getSignExtended();
3228 default: assert(0 && "Unknown integer setcc!");
3229 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
3230 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
3231 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
3232 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
3233 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
3234 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
3235 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
3236 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
3237 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
3238 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
3241 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
3242 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
3243 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
3245 // If the comparison constant has bits in the upper part, the
3246 // zero-extended value could never match.
3247 if (C1 & (~0ULL << InSize)) {
3248 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
3252 case ISD::SETEQ: return DAG.getConstant(0, VT);
3255 case ISD::SETNE: return DAG.getConstant(1, VT);
3258 // True if the sign bit of C1 is set.
3259 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
3262 // True if the sign bit of C1 isn't set.
3263 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
3269 // Otherwise, we can perform the comparison with the low bits.
3277 return DAG.getSetCC(VT, N0.getOperand(0),
3278 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
3281 break; // todo, be more careful with signed comparisons
3283 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3284 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3285 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
3286 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
3287 MVT::ValueType ExtDstTy = N0.getValueType();
3288 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
3290 // If the extended part has any inconsistent bits, it cannot ever
3291 // compare equal. In other words, they have to be all ones or all
3294 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
3295 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
3296 return DAG.getConstant(Cond == ISD::SETNE, VT);
3299 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
3300 if (Op0Ty == ExtSrcTy) {
3301 ZextOp = N0.getOperand(0);
3303 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
3304 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
3305 DAG.getConstant(Imm, Op0Ty));
3307 AddToWorkList(ZextOp.Val);
3308 // Otherwise, make this a use of a zext.
3309 return DAG.getSetCC(VT, ZextOp,
3310 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
3313 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
3314 (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3315 (N0.getOpcode() == ISD::XOR ||
3316 (N0.getOpcode() == ISD::AND &&
3317 N0.getOperand(0).getOpcode() == ISD::XOR &&
3318 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
3319 isa<ConstantSDNode>(N0.getOperand(1)) &&
3320 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
3321 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can
3322 // only do this if the top bits are known zero.
3323 if (TLI.MaskedValueIsZero(N1,
3324 MVT::getIntVTBitMask(N0.getValueType())-1)) {
3325 // Okay, get the un-inverted input value.
3327 if (N0.getOpcode() == ISD::XOR)
3328 Val = N0.getOperand(0);
3330 assert(N0.getOpcode() == ISD::AND &&
3331 N0.getOperand(0).getOpcode() == ISD::XOR);
3332 // ((X^1)&1)^1 -> X & 1
3333 Val = DAG.getNode(ISD::AND, N0.getValueType(),
3334 N0.getOperand(0).getOperand(0), N0.getOperand(1));
3336 return DAG.getSetCC(VT, Val, N1,
3337 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3341 uint64_t MinVal, MaxVal;
3342 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
3343 if (ISD::isSignedIntSetCC(Cond)) {
3344 MinVal = 1ULL << (OperandBitSize-1);
3345 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
3346 MaxVal = ~0ULL >> (65-OperandBitSize);
3351 MaxVal = ~0ULL >> (64-OperandBitSize);
3354 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
3355 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
3356 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
3357 --C1; // X >= C0 --> X > (C0-1)
3358 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3359 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
3362 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
3363 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
3364 ++C1; // X <= C0 --> X < (C0+1)
3365 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3366 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
3369 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
3370 return DAG.getConstant(0, VT); // X < MIN --> false
3372 // Canonicalize setgt X, Min --> setne X, Min
3373 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
3374 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3375 // Canonicalize setlt X, Max --> setne X, Max
3376 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
3377 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3379 // If we have setult X, 1, turn it into seteq X, 0
3380 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
3381 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
3383 // If we have setugt X, Max-1, turn it into seteq X, Max
3384 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
3385 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
3388 // If we have "setcc X, C0", check to see if we can shrink the immediate
3391 // SETUGT X, SINTMAX -> SETLT X, 0
3392 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
3393 C1 == (~0ULL >> (65-OperandBitSize)))
3394 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
3397 // FIXME: Implement the rest of these.
3399 // Fold bit comparisons when we can.
3400 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3401 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
3402 if (ConstantSDNode *AndRHS =
3403 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3404 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
3405 // Perform the xform if the AND RHS is a single bit.
3406 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
3407 return DAG.getNode(ISD::SRL, VT, N0,
3408 DAG.getConstant(Log2_64(AndRHS->getValue()),
3409 TLI.getShiftAmountTy()));
3411 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
3412 // (X & 8) == 8 --> (X & 8) >> 3
3413 // Perform the xform if C1 is a single bit.
3414 if ((C1 & (C1-1)) == 0) {
3415 return DAG.getNode(ISD::SRL, VT, N0,
3416 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
3421 } else if (isa<ConstantSDNode>(N0.Val)) {
3422 // Ensure that the constant occurs on the RHS.
3423 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
3426 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
3427 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
3428 double C0 = N0C->getValue(), C1 = N1C->getValue();
3431 default: break; // FIXME: Implement the rest of these!
3432 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
3433 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
3434 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
3435 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
3436 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
3437 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
3440 // Ensure that the constant occurs on the RHS.
3441 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
3445 // We can always fold X == Y for integer setcc's.
3446 if (MVT::isInteger(N0.getValueType()))
3447 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3448 unsigned UOF = ISD::getUnorderedFlavor(Cond);
3449 if (UOF == 2) // FP operators that are undefined on NaNs.
3450 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3451 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
3452 return DAG.getConstant(UOF, VT);
3453 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
3454 // if it is not already.
3455 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
3456 if (NewCond != Cond)
3457 return DAG.getSetCC(VT, N0, N1, NewCond);
3460 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3461 MVT::isInteger(N0.getValueType())) {
3462 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
3463 N0.getOpcode() == ISD::XOR) {
3464 // Simplify (X+Y) == (X+Z) --> Y == Z
3465 if (N0.getOpcode() == N1.getOpcode()) {
3466 if (N0.getOperand(0) == N1.getOperand(0))
3467 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
3468 if (N0.getOperand(1) == N1.getOperand(1))
3469 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
3470 if (isCommutativeBinOp(N0.getOpcode())) {
3471 // If X op Y == Y op X, try other combinations.
3472 if (N0.getOperand(0) == N1.getOperand(1))
3473 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
3474 if (N0.getOperand(1) == N1.getOperand(0))
3475 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
3479 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
3480 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3481 // Turn (X+C1) == C2 --> X == C2-C1
3482 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
3483 return DAG.getSetCC(VT, N0.getOperand(0),
3484 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
3485 N0.getValueType()), Cond);
3488 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
3489 if (N0.getOpcode() == ISD::XOR)
3490 // If we know that all of the inverted bits are zero, don't bother
3491 // performing the inversion.
3492 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
3493 return DAG.getSetCC(VT, N0.getOperand(0),
3494 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
3495 N0.getValueType()), Cond);
3498 // Turn (C1-X) == C2 --> X == C1-C2
3499 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
3500 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
3501 return DAG.getSetCC(VT, N0.getOperand(1),
3502 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
3503 N0.getValueType()), Cond);
3508 // Simplify (X+Z) == X --> Z == 0
3509 if (N0.getOperand(0) == N1)
3510 return DAG.getSetCC(VT, N0.getOperand(1),
3511 DAG.getConstant(0, N0.getValueType()), Cond);
3512 if (N0.getOperand(1) == N1) {
3513 if (isCommutativeBinOp(N0.getOpcode()))
3514 return DAG.getSetCC(VT, N0.getOperand(0),
3515 DAG.getConstant(0, N0.getValueType()), Cond);
3517 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
3518 // (Z-X) == X --> Z == X<<1
3519 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
3521 DAG.getConstant(1,TLI.getShiftAmountTy()));
3522 AddToWorkList(SH.Val);
3523 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
3528 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
3529 N1.getOpcode() == ISD::XOR) {
3530 // Simplify X == (X+Z) --> Z == 0
3531 if (N1.getOperand(0) == N0) {
3532 return DAG.getSetCC(VT, N1.getOperand(1),
3533 DAG.getConstant(0, N1.getValueType()), Cond);
3534 } else if (N1.getOperand(1) == N0) {
3535 if (isCommutativeBinOp(N1.getOpcode())) {
3536 return DAG.getSetCC(VT, N1.getOperand(0),
3537 DAG.getConstant(0, N1.getValueType()), Cond);
3539 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
3540 // X == (Z-X) --> X<<1 == Z
3541 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
3542 DAG.getConstant(1,TLI.getShiftAmountTy()));
3543 AddToWorkList(SH.Val);
3544 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
3550 // Fold away ALL boolean setcc's.
3552 if (N0.getValueType() == MVT::i1 && foldBooleans) {
3554 default: assert(0 && "Unknown integer setcc!");
3555 case ISD::SETEQ: // X == Y -> (X^Y)^1
3556 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
3557 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
3558 AddToWorkList(Temp.Val);
3560 case ISD::SETNE: // X != Y --> (X^Y)
3561 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
3563 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
3564 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
3565 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
3566 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
3567 AddToWorkList(Temp.Val);
3569 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
3570 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
3571 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
3572 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
3573 AddToWorkList(Temp.Val);
3575 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
3576 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
3577 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
3578 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
3579 AddToWorkList(Temp.Val);
3581 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
3582 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
3583 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
3584 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
3587 if (VT != MVT::i1) {
3588 AddToWorkList(N0.Val);
3589 // FIXME: If running after legalize, we probably can't do this.
3590 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
3595 // Could not fold it.
3599 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3600 /// return a DAG expression to select that will generate the same value by
3601 /// multiplying by a magic number. See:
3602 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3603 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
3604 MVT::ValueType VT = N->getValueType(0);
3606 // Check to see if we can do this.
3607 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
3608 return SDOperand(); // BuildSDIV only operates on i32 or i64
3609 if (!TLI.isOperationLegal(ISD::MULHS, VT))
3610 return SDOperand(); // Make sure the target supports MULHS.
3612 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
3613 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
3615 // Multiply the numerator (operand 0) by the magic value
3616 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
3617 DAG.getConstant(magics.m, VT));
3618 // If d > 0 and m < 0, add the numerator
3619 if (d > 0 && magics.m < 0) {
3620 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
3621 AddToWorkList(Q.Val);
3623 // If d < 0 and m > 0, subtract the numerator.
3624 if (d < 0 && magics.m > 0) {
3625 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
3626 AddToWorkList(Q.Val);
3628 // Shift right algebraic if shift value is nonzero
3630 Q = DAG.getNode(ISD::SRA, VT, Q,
3631 DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
3632 AddToWorkList(Q.Val);
3634 // Extract the sign bit and add it to the quotient
3636 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1,
3637 TLI.getShiftAmountTy()));
3638 AddToWorkList(T.Val);
3639 return DAG.getNode(ISD::ADD, VT, Q, T);
3642 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3643 /// return a DAG expression to select that will generate the same value by
3644 /// multiplying by a magic number. See:
3645 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3646 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
3647 MVT::ValueType VT = N->getValueType(0);
3649 // Check to see if we can do this.
3650 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
3651 return SDOperand(); // BuildUDIV only operates on i32 or i64
3652 if (!TLI.isOperationLegal(ISD::MULHU, VT))
3653 return SDOperand(); // Make sure the target supports MULHU.
3655 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
3656 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
3658 // Multiply the numerator (operand 0) by the magic value
3659 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
3660 DAG.getConstant(magics.m, VT));
3661 AddToWorkList(Q.Val);
3663 if (magics.a == 0) {
3664 return DAG.getNode(ISD::SRL, VT, Q,
3665 DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
3667 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
3668 AddToWorkList(NPQ.Val);
3669 NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
3670 DAG.getConstant(1, TLI.getShiftAmountTy()));
3671 AddToWorkList(NPQ.Val);
3672 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
3673 AddToWorkList(NPQ.Val);
3674 return DAG.getNode(ISD::SRL, VT, NPQ,
3675 DAG.getConstant(magics.s-1, TLI.getShiftAmountTy()));
3679 // SelectionDAG::Combine - This is the entry point for the file.
3681 void SelectionDAG::Combine(bool RunningAfterLegalize) {
3682 /// run - This is the main entry point to this class.
3684 DAGCombiner(*this).Run(RunningAfterLegalize);