1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "dagcombine"
16 #include "llvm/CodeGen/SelectionDAG.h"
17 #include "llvm/Analysis/AliasAnalysis.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/ADT/SmallPtrSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/Support/Compiler.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
31 STATISTIC(NodesCombined , "Number of dag nodes combined");
32 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
33 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
38 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
39 cl::desc("Pop up a window to show dags before the first "
42 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
43 cl::desc("Pop up a window to show dags before the second "
46 static const bool ViewDAGCombine1 = false;
47 static const bool ViewDAGCombine2 = false;
51 CombinerAA("combiner-alias-analysis", cl::Hidden,
52 cl::desc("Turn on alias analysis during testing"));
55 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
56 cl::desc("Include global information in alias analysis"));
58 //------------------------------ DAGCombiner ---------------------------------//
60 class VISIBILITY_HIDDEN DAGCombiner {
65 // Worklist of all of the nodes that need to be simplified.
66 std::vector<SDNode*> WorkList;
68 // AA - Used for DAG load/store alias analysis.
71 /// AddUsersToWorkList - When an instruction is simplified, add all users of
72 /// the instruction to the work lists because they might get more simplified
75 void AddUsersToWorkList(SDNode *N) {
76 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
81 /// removeFromWorkList - remove all instances of N from the worklist.
83 void removeFromWorkList(SDNode *N) {
84 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
88 /// visit - call the node-specific routine that knows how to fold each
89 /// particular type of node.
90 SDOperand visit(SDNode *N);
93 /// AddToWorkList - Add to the work list making sure it's instance is at the
94 /// the back (next to be processed.)
95 void AddToWorkList(SDNode *N) {
96 removeFromWorkList(N);
97 WorkList.push_back(N);
100 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
102 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
104 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
105 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
106 DOUT << " and " << NumTo-1 << " other values\n";
107 std::vector<SDNode*> NowDead;
108 DAG.ReplaceAllUsesWith(N, To, &NowDead);
111 // Push the new nodes and any users onto the worklist
112 for (unsigned i = 0, e = NumTo; i != e; ++i) {
113 AddToWorkList(To[i].Val);
114 AddUsersToWorkList(To[i].Val);
118 // Nodes can be reintroduced into the worklist. Make sure we do not
119 // process a node that has been replaced.
120 removeFromWorkList(N);
121 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
122 removeFromWorkList(NowDead[i]);
124 // Finally, since the node is now dead, remove it from the graph.
126 return SDOperand(N, 0);
129 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
130 return CombineTo(N, &Res, 1, AddTo);
133 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
135 SDOperand To[] = { Res0, Res1 };
136 return CombineTo(N, To, 2, AddTo);
140 /// SimplifyDemandedBits - Check the specified integer node value to see if
141 /// it can be simplified or if things it uses can be simplified by bit
142 /// propagation. If so, return true.
143 bool SimplifyDemandedBits(SDOperand Op, uint64_t Demanded = ~0ULL) {
144 TargetLowering::TargetLoweringOpt TLO(DAG);
145 uint64_t KnownZero, KnownOne;
146 Demanded &= MVT::getIntVTBitMask(Op.getValueType());
147 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
151 AddToWorkList(Op.Val);
153 // Replace the old value with the new one.
155 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG));
156 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
159 std::vector<SDNode*> NowDead;
160 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &NowDead);
162 // Push the new node and any (possibly new) users onto the worklist.
163 AddToWorkList(TLO.New.Val);
164 AddUsersToWorkList(TLO.New.Val);
166 // Nodes can end up on the worklist more than once. Make sure we do
167 // not process a node that has been replaced.
168 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
169 removeFromWorkList(NowDead[i]);
171 // Finally, if the node is now dead, remove it from the graph. The node
172 // may not be dead if the replacement process recursively simplified to
173 // something else needing this node.
174 if (TLO.Old.Val->use_empty()) {
175 removeFromWorkList(TLO.Old.Val);
177 // If the operands of this node are only used by the node, they will now
178 // be dead. Make sure to visit them first to delete dead nodes early.
179 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i)
180 if (TLO.Old.Val->getOperand(i).Val->hasOneUse())
181 AddToWorkList(TLO.Old.Val->getOperand(i).Val);
183 DAG.DeleteNode(TLO.Old.Val);
188 bool CombineToPreIndexedLoadStore(SDNode *N);
189 bool CombineToPostIndexedLoadStore(SDNode *N);
192 /// combine - call the node-specific routine that knows how to fold each
193 /// particular type of node. If that doesn't do anything, try the
194 /// target-specific DAG combines.
195 SDOperand combine(SDNode *N);
197 // Visitation implementation - Implement dag node combining for different
198 // node types. The semantics are as follows:
200 // SDOperand.Val == 0 - No change was made
201 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
202 // otherwise - N should be replaced by the returned Operand.
204 SDOperand visitTokenFactor(SDNode *N);
205 SDOperand visitADD(SDNode *N);
206 SDOperand visitSUB(SDNode *N);
207 SDOperand visitADDC(SDNode *N);
208 SDOperand visitADDE(SDNode *N);
209 SDOperand visitMUL(SDNode *N);
210 SDOperand visitSDIV(SDNode *N);
211 SDOperand visitUDIV(SDNode *N);
212 SDOperand visitSREM(SDNode *N);
213 SDOperand visitUREM(SDNode *N);
214 SDOperand visitMULHU(SDNode *N);
215 SDOperand visitMULHS(SDNode *N);
216 SDOperand visitSMUL_LOHI(SDNode *N);
217 SDOperand visitUMUL_LOHI(SDNode *N);
218 SDOperand visitSDIVREM(SDNode *N);
219 SDOperand visitUDIVREM(SDNode *N);
220 SDOperand visitAND(SDNode *N);
221 SDOperand visitOR(SDNode *N);
222 SDOperand visitXOR(SDNode *N);
223 SDOperand SimplifyVBinOp(SDNode *N);
224 SDOperand visitSHL(SDNode *N);
225 SDOperand visitSRA(SDNode *N);
226 SDOperand visitSRL(SDNode *N);
227 SDOperand visitCTLZ(SDNode *N);
228 SDOperand visitCTTZ(SDNode *N);
229 SDOperand visitCTPOP(SDNode *N);
230 SDOperand visitSELECT(SDNode *N);
231 SDOperand visitSELECT_CC(SDNode *N);
232 SDOperand visitSETCC(SDNode *N);
233 SDOperand visitSIGN_EXTEND(SDNode *N);
234 SDOperand visitZERO_EXTEND(SDNode *N);
235 SDOperand visitANY_EXTEND(SDNode *N);
236 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
237 SDOperand visitTRUNCATE(SDNode *N);
238 SDOperand visitBIT_CONVERT(SDNode *N);
239 SDOperand visitFADD(SDNode *N);
240 SDOperand visitFSUB(SDNode *N);
241 SDOperand visitFMUL(SDNode *N);
242 SDOperand visitFDIV(SDNode *N);
243 SDOperand visitFREM(SDNode *N);
244 SDOperand visitFCOPYSIGN(SDNode *N);
245 SDOperand visitSINT_TO_FP(SDNode *N);
246 SDOperand visitUINT_TO_FP(SDNode *N);
247 SDOperand visitFP_TO_SINT(SDNode *N);
248 SDOperand visitFP_TO_UINT(SDNode *N);
249 SDOperand visitFP_ROUND(SDNode *N);
250 SDOperand visitFP_ROUND_INREG(SDNode *N);
251 SDOperand visitFP_EXTEND(SDNode *N);
252 SDOperand visitFNEG(SDNode *N);
253 SDOperand visitFABS(SDNode *N);
254 SDOperand visitBRCOND(SDNode *N);
255 SDOperand visitBR_CC(SDNode *N);
256 SDOperand visitLOAD(SDNode *N);
257 SDOperand visitSTORE(SDNode *N);
258 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
259 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N);
260 SDOperand visitBUILD_VECTOR(SDNode *N);
261 SDOperand visitCONCAT_VECTORS(SDNode *N);
262 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
264 SDOperand XformToShuffleWithZero(SDNode *N);
265 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
267 SDOperand visitShiftByConstant(SDNode *N, unsigned Amt);
269 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
270 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
271 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
272 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
273 SDOperand N3, ISD::CondCode CC,
274 bool NotExtCompare = false);
275 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
276 ISD::CondCode Cond, bool foldBooleans = true);
277 bool SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, unsigned HiOp);
278 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType);
279 SDOperand BuildSDIV(SDNode *N);
280 SDOperand BuildUDIV(SDNode *N);
281 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
282 SDOperand ReduceLoadWidth(SDNode *N);
284 SDOperand GetDemandedBits(SDOperand V, uint64_t Mask);
286 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
287 /// looking for aliasing nodes and adding them to the Aliases vector.
288 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
289 SmallVector<SDOperand, 8> &Aliases);
291 /// isAlias - Return true if there is any possibility that the two addresses
293 bool isAlias(SDOperand Ptr1, int64_t Size1,
294 const Value *SrcValue1, int SrcValueOffset1,
295 SDOperand Ptr2, int64_t Size2,
296 const Value *SrcValue2, int SrcValueOffset2);
298 /// FindAliasInfo - Extracts the relevant alias information from the memory
299 /// node. Returns true if the operand was a load.
300 bool FindAliasInfo(SDNode *N,
301 SDOperand &Ptr, int64_t &Size,
302 const Value *&SrcValue, int &SrcValueOffset);
304 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
305 /// looking for a better chain (aliasing node.)
306 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
309 DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
311 TLI(D.getTargetLoweringInfo()),
312 AfterLegalize(false),
315 /// Run - runs the dag combiner on all nodes in the work list
316 void Run(bool RunningAfterLegalize);
320 //===----------------------------------------------------------------------===//
321 // TargetLowering::DAGCombinerInfo implementation
322 //===----------------------------------------------------------------------===//
324 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
325 ((DAGCombiner*)DC)->AddToWorkList(N);
328 SDOperand TargetLowering::DAGCombinerInfo::
329 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
330 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
333 SDOperand TargetLowering::DAGCombinerInfo::
334 CombineTo(SDNode *N, SDOperand Res) {
335 return ((DAGCombiner*)DC)->CombineTo(N, Res);
339 SDOperand TargetLowering::DAGCombinerInfo::
340 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
341 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
345 //===----------------------------------------------------------------------===//
347 //===----------------------------------------------------------------------===//
349 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
350 /// specified expression for the same cost as the expression itself, or 2 if we
351 /// can compute the negated form more cheaply than the expression itself.
352 static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) {
353 // No compile time optimizations on this type.
354 if (Op.getValueType() == MVT::ppcf128)
357 // fneg is removable even if it has multiple uses.
358 if (Op.getOpcode() == ISD::FNEG) return 2;
360 // Don't allow anything with multiple uses.
361 if (!Op.hasOneUse()) return 0;
363 // Don't recurse exponentially.
364 if (Depth > 6) return 0;
366 switch (Op.getOpcode()) {
367 default: return false;
368 case ISD::ConstantFP:
371 // FIXME: determine better conditions for this xform.
372 if (!UnsafeFPMath) return 0;
375 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
378 return isNegatibleForFree(Op.getOperand(1), Depth+1);
380 // We can't turn -(A-B) into B-A when we honor signed zeros.
381 if (!UnsafeFPMath) return 0;
388 if (HonorSignDependentRoundingFPMath()) return 0;
390 // -(X*Y) -> (-X * Y) or (X*-Y)
391 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
394 return isNegatibleForFree(Op.getOperand(1), Depth+1);
399 return isNegatibleForFree(Op.getOperand(0), Depth+1);
403 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
404 /// returns the newly negated expression.
405 static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG,
406 unsigned Depth = 0) {
407 // fneg is removable even if it has multiple uses.
408 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
410 // Don't allow anything with multiple uses.
411 assert(Op.hasOneUse() && "Unknown reuse!");
413 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
414 switch (Op.getOpcode()) {
415 default: assert(0 && "Unknown code");
416 case ISD::ConstantFP: {
417 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
419 return DAG.getConstantFP(V, Op.getValueType());
422 // FIXME: determine better conditions for this xform.
423 assert(UnsafeFPMath);
426 if (isNegatibleForFree(Op.getOperand(0), Depth+1))
427 return DAG.getNode(ISD::FSUB, Op.getValueType(),
428 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
431 return DAG.getNode(ISD::FSUB, Op.getValueType(),
432 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1),
435 // We can't turn -(A-B) into B-A when we honor signed zeros.
436 assert(UnsafeFPMath);
439 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
440 if (N0CFP->getValueAPF().isZero())
441 return Op.getOperand(1);
444 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1),
449 assert(!HonorSignDependentRoundingFPMath());
452 if (isNegatibleForFree(Op.getOperand(0), Depth+1))
453 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
454 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
458 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
460 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1));
465 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
466 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1));
471 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
472 // that selects between the values 1 and 0, making it equivalent to a setcc.
473 // Also, set the incoming LHS, RHS, and CC references to the appropriate
474 // nodes based on the type of node we are checking. This simplifies life a
475 // bit for the callers.
476 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
478 if (N.getOpcode() == ISD::SETCC) {
479 LHS = N.getOperand(0);
480 RHS = N.getOperand(1);
481 CC = N.getOperand(2);
484 if (N.getOpcode() == ISD::SELECT_CC &&
485 N.getOperand(2).getOpcode() == ISD::Constant &&
486 N.getOperand(3).getOpcode() == ISD::Constant &&
487 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
488 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
489 LHS = N.getOperand(0);
490 RHS = N.getOperand(1);
491 CC = N.getOperand(4);
497 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
498 // one use. If this is true, it allows the users to invert the operation for
499 // free when it is profitable to do so.
500 static bool isOneUseSetCC(SDOperand N) {
501 SDOperand N0, N1, N2;
502 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
507 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
508 MVT::ValueType VT = N0.getValueType();
509 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
510 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
511 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
512 if (isa<ConstantSDNode>(N1)) {
513 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
514 AddToWorkList(OpNode.Val);
515 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
516 } else if (N0.hasOneUse()) {
517 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
518 AddToWorkList(OpNode.Val);
519 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
522 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
523 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
524 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
525 if (isa<ConstantSDNode>(N0)) {
526 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
527 AddToWorkList(OpNode.Val);
528 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
529 } else if (N1.hasOneUse()) {
530 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
531 AddToWorkList(OpNode.Val);
532 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
538 //===----------------------------------------------------------------------===//
539 // Main DAG Combiner implementation
540 //===----------------------------------------------------------------------===//
542 void DAGCombiner::Run(bool RunningAfterLegalize) {
543 // set the instance variable, so that the various visit routines may use it.
544 AfterLegalize = RunningAfterLegalize;
546 // Add all the dag nodes to the worklist.
547 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
548 E = DAG.allnodes_end(); I != E; ++I)
549 WorkList.push_back(I);
551 // Create a dummy node (which is not added to allnodes), that adds a reference
552 // to the root node, preventing it from being deleted, and tracking any
553 // changes of the root.
554 HandleSDNode Dummy(DAG.getRoot());
556 // The root of the dag may dangle to deleted nodes until the dag combiner is
557 // done. Set it to null to avoid confusion.
558 DAG.setRoot(SDOperand());
560 // while the worklist isn't empty, inspect the node on the end of it and
561 // try and combine it.
562 while (!WorkList.empty()) {
563 SDNode *N = WorkList.back();
566 // If N has no uses, it is dead. Make sure to revisit all N's operands once
567 // N is deleted from the DAG, since they too may now be dead or may have a
568 // reduced number of uses, allowing other xforms.
569 if (N->use_empty() && N != &Dummy) {
570 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
571 AddToWorkList(N->getOperand(i).Val);
577 SDOperand RV = combine(N);
581 // If we get back the same node we passed in, rather than a new node or
582 // zero, we know that the node must have defined multiple values and
583 // CombineTo was used. Since CombineTo takes care of the worklist
584 // mechanics for us, we have no work to do in this case.
586 assert(N->getOpcode() != ISD::DELETED_NODE &&
587 RV.Val->getOpcode() != ISD::DELETED_NODE &&
588 "Node was deleted but visit returned new node!");
590 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
591 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
593 std::vector<SDNode*> NowDead;
594 if (N->getNumValues() == RV.Val->getNumValues())
595 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
597 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
599 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
602 // Push the new node and any users onto the worklist
603 AddToWorkList(RV.Val);
604 AddUsersToWorkList(RV.Val);
606 // Nodes can be reintroduced into the worklist. Make sure we do not
607 // process a node that has been replaced.
608 removeFromWorkList(N);
609 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
610 removeFromWorkList(NowDead[i]);
612 // Finally, since the node is now dead, remove it from the graph.
618 // If the root changed (e.g. it was a dead load, update the root).
619 DAG.setRoot(Dummy.getValue());
622 SDOperand DAGCombiner::visit(SDNode *N) {
623 switch(N->getOpcode()) {
625 case ISD::TokenFactor: return visitTokenFactor(N);
626 case ISD::ADD: return visitADD(N);
627 case ISD::SUB: return visitSUB(N);
628 case ISD::ADDC: return visitADDC(N);
629 case ISD::ADDE: return visitADDE(N);
630 case ISD::MUL: return visitMUL(N);
631 case ISD::SDIV: return visitSDIV(N);
632 case ISD::UDIV: return visitUDIV(N);
633 case ISD::SREM: return visitSREM(N);
634 case ISD::UREM: return visitUREM(N);
635 case ISD::MULHU: return visitMULHU(N);
636 case ISD::MULHS: return visitMULHS(N);
637 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
638 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
639 case ISD::SDIVREM: return visitSDIVREM(N);
640 case ISD::UDIVREM: return visitUDIVREM(N);
641 case ISD::AND: return visitAND(N);
642 case ISD::OR: return visitOR(N);
643 case ISD::XOR: return visitXOR(N);
644 case ISD::SHL: return visitSHL(N);
645 case ISD::SRA: return visitSRA(N);
646 case ISD::SRL: return visitSRL(N);
647 case ISD::CTLZ: return visitCTLZ(N);
648 case ISD::CTTZ: return visitCTTZ(N);
649 case ISD::CTPOP: return visitCTPOP(N);
650 case ISD::SELECT: return visitSELECT(N);
651 case ISD::SELECT_CC: return visitSELECT_CC(N);
652 case ISD::SETCC: return visitSETCC(N);
653 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
654 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
655 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
656 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
657 case ISD::TRUNCATE: return visitTRUNCATE(N);
658 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
659 case ISD::FADD: return visitFADD(N);
660 case ISD::FSUB: return visitFSUB(N);
661 case ISD::FMUL: return visitFMUL(N);
662 case ISD::FDIV: return visitFDIV(N);
663 case ISD::FREM: return visitFREM(N);
664 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
665 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
666 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
667 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
668 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
669 case ISD::FP_ROUND: return visitFP_ROUND(N);
670 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
671 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
672 case ISD::FNEG: return visitFNEG(N);
673 case ISD::FABS: return visitFABS(N);
674 case ISD::BRCOND: return visitBRCOND(N);
675 case ISD::BR_CC: return visitBR_CC(N);
676 case ISD::LOAD: return visitLOAD(N);
677 case ISD::STORE: return visitSTORE(N);
678 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
679 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
680 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
681 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
682 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
687 SDOperand DAGCombiner::combine(SDNode *N) {
689 SDOperand RV = visit(N);
691 // If nothing happened, try a target-specific DAG combine.
693 assert(N->getOpcode() != ISD::DELETED_NODE &&
694 "Node was deleted but visit returned NULL!");
696 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
697 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
699 // Expose the DAG combiner to the target combiner impls.
700 TargetLowering::DAGCombinerInfo
701 DagCombineInfo(DAG, !AfterLegalize, false, this);
703 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
710 /// getInputChainForNode - Given a node, return its input chain if it has one,
711 /// otherwise return a null sd operand.
712 static SDOperand getInputChainForNode(SDNode *N) {
713 if (unsigned NumOps = N->getNumOperands()) {
714 if (N->getOperand(0).getValueType() == MVT::Other)
715 return N->getOperand(0);
716 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
717 return N->getOperand(NumOps-1);
718 for (unsigned i = 1; i < NumOps-1; ++i)
719 if (N->getOperand(i).getValueType() == MVT::Other)
720 return N->getOperand(i);
722 return SDOperand(0, 0);
725 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
726 // If N has two operands, where one has an input chain equal to the other,
727 // the 'other' chain is redundant.
728 if (N->getNumOperands() == 2) {
729 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
730 return N->getOperand(0);
731 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
732 return N->getOperand(1);
735 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
736 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
737 SmallPtrSet<SDNode*, 16> SeenOps;
738 bool Changed = false; // If we should replace this token factor.
740 // Start out with this token factor.
743 // Iterate through token factors. The TFs grows when new token factors are
745 for (unsigned i = 0; i < TFs.size(); ++i) {
748 // Check each of the operands.
749 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
750 SDOperand Op = TF->getOperand(i);
752 switch (Op.getOpcode()) {
753 case ISD::EntryToken:
754 // Entry tokens don't need to be added to the list. They are
759 case ISD::TokenFactor:
760 if ((CombinerAA || Op.hasOneUse()) &&
761 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
762 // Queue up for processing.
763 TFs.push_back(Op.Val);
764 // Clean up in case the token factor is removed.
765 AddToWorkList(Op.Val);
772 // Only add if it isn't already in the list.
773 if (SeenOps.insert(Op.Val))
784 // If we've change things around then replace token factor.
786 if (Ops.size() == 0) {
787 // The entry token is the only possible outcome.
788 Result = DAG.getEntryNode();
790 // New and improved token factor.
791 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
794 // Don't add users to work list.
795 return CombineTo(N, Result, false);
802 SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
803 MVT::ValueType VT = N0.getValueType();
804 SDOperand N00 = N0.getOperand(0);
805 SDOperand N01 = N0.getOperand(1);
806 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
807 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
808 isa<ConstantSDNode>(N00.getOperand(1))) {
809 N0 = DAG.getNode(ISD::ADD, VT,
810 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01),
811 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01));
812 return DAG.getNode(ISD::ADD, VT, N0, N1);
818 SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp,
820 MVT::ValueType VT = N->getValueType(0);
821 unsigned Opc = N->getOpcode();
822 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
823 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
824 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
825 ISD::CondCode CC = ISD::SETCC_INVALID;
827 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
829 SDOperand CCOp = Slct.getOperand(0);
830 if (CCOp.getOpcode() == ISD::SETCC)
831 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
834 bool DoXform = false;
836 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
838 if (LHS.getOpcode() == ISD::Constant &&
839 cast<ConstantSDNode>(LHS)->isNullValue())
841 else if (CC != ISD::SETCC_INVALID &&
842 RHS.getOpcode() == ISD::Constant &&
843 cast<ConstantSDNode>(RHS)->isNullValue()) {
845 bool isInt = MVT::isInteger(isSlctCC ? Slct.getOperand(0).getValueType()
846 : Slct.getOperand(0).getOperand(0).getValueType());
847 CC = ISD::getSetCCInverse(CC, isInt);
853 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS);
855 return DAG.getSelectCC(OtherOp, Result,
856 Slct.getOperand(0), Slct.getOperand(1), CC);
857 SDOperand CCOp = Slct.getOperand(0);
859 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0),
860 CCOp.getOperand(1), CC);
861 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result);
866 SDOperand DAGCombiner::visitADD(SDNode *N) {
867 SDOperand N0 = N->getOperand(0);
868 SDOperand N1 = N->getOperand(1);
869 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
870 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
871 MVT::ValueType VT = N0.getValueType();
874 if (MVT::isVector(VT)) {
875 SDOperand FoldedVOp = SimplifyVBinOp(N);
876 if (FoldedVOp.Val) return FoldedVOp;
879 // fold (add x, undef) -> undef
880 if (N0.getOpcode() == ISD::UNDEF)
882 if (N1.getOpcode() == ISD::UNDEF)
884 // fold (add c1, c2) -> c1+c2
886 return DAG.getNode(ISD::ADD, VT, N0, N1);
887 // canonicalize constant to RHS
889 return DAG.getNode(ISD::ADD, VT, N1, N0);
890 // fold (add x, 0) -> x
891 if (N1C && N1C->isNullValue())
893 // fold ((c1-A)+c2) -> (c1+c2)-A
894 if (N1C && N0.getOpcode() == ISD::SUB)
895 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
896 return DAG.getNode(ISD::SUB, VT,
897 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
900 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
903 // fold ((0-A) + B) -> B-A
904 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
905 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
906 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
907 // fold (A + (0-B)) -> A-B
908 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
909 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
910 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
911 // fold (A+(B-A)) -> B
912 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
913 return N1.getOperand(0);
915 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
916 return SDOperand(N, 0);
918 // fold (a+b) -> (a|b) iff a and b share no bits.
919 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
920 uint64_t LHSZero, LHSOne;
921 uint64_t RHSZero, RHSOne;
922 uint64_t Mask = MVT::getIntVTBitMask(VT);
923 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
925 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
927 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
928 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
929 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
930 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
931 return DAG.getNode(ISD::OR, VT, N0, N1);
935 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
936 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) {
937 SDOperand Result = combineShlAddConstant(N0, N1, DAG);
938 if (Result.Val) return Result;
940 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) {
941 SDOperand Result = combineShlAddConstant(N1, N0, DAG);
942 if (Result.Val) return Result;
945 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
946 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) {
947 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG);
948 if (Result.Val) return Result;
950 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
951 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
952 if (Result.Val) return Result;
958 SDOperand DAGCombiner::visitADDC(SDNode *N) {
959 SDOperand N0 = N->getOperand(0);
960 SDOperand N1 = N->getOperand(1);
961 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
962 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
963 MVT::ValueType VT = N0.getValueType();
965 // If the flag result is dead, turn this into an ADD.
966 if (N->hasNUsesOfValue(0, 1))
967 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0),
968 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
970 // canonicalize constant to RHS.
972 SDOperand Ops[] = { N1, N0 };
973 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
976 // fold (addc x, 0) -> x + no carry out
977 if (N1C && N1C->isNullValue())
978 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
980 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
981 uint64_t LHSZero, LHSOne;
982 uint64_t RHSZero, RHSOne;
983 uint64_t Mask = MVT::getIntVTBitMask(VT);
984 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
986 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
988 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
989 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
990 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
991 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
992 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1),
993 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
999 SDOperand DAGCombiner::visitADDE(SDNode *N) {
1000 SDOperand N0 = N->getOperand(0);
1001 SDOperand N1 = N->getOperand(1);
1002 SDOperand CarryIn = N->getOperand(2);
1003 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1004 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1005 //MVT::ValueType VT = N0.getValueType();
1007 // canonicalize constant to RHS
1009 SDOperand Ops[] = { N1, N0, CarryIn };
1010 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3);
1013 // fold (adde x, y, false) -> (addc x, y)
1014 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) {
1015 SDOperand Ops[] = { N1, N0 };
1016 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
1024 SDOperand DAGCombiner::visitSUB(SDNode *N) {
1025 SDOperand N0 = N->getOperand(0);
1026 SDOperand N1 = N->getOperand(1);
1027 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1028 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1029 MVT::ValueType VT = N0.getValueType();
1032 if (MVT::isVector(VT)) {
1033 SDOperand FoldedVOp = SimplifyVBinOp(N);
1034 if (FoldedVOp.Val) return FoldedVOp;
1037 // fold (sub x, x) -> 0
1039 return DAG.getConstant(0, N->getValueType(0));
1040 // fold (sub c1, c2) -> c1-c2
1042 return DAG.getNode(ISD::SUB, VT, N0, N1);
1043 // fold (sub x, c) -> (add x, -c)
1045 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
1046 // fold (A+B)-A -> B
1047 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1048 return N0.getOperand(1);
1049 // fold (A+B)-B -> A
1050 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1051 return N0.getOperand(0);
1052 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1053 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
1054 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
1055 if (Result.Val) return Result;
1057 // If either operand of a sub is undef, the result is undef
1058 if (N0.getOpcode() == ISD::UNDEF)
1060 if (N1.getOpcode() == ISD::UNDEF)
1066 SDOperand DAGCombiner::visitMUL(SDNode *N) {
1067 SDOperand N0 = N->getOperand(0);
1068 SDOperand N1 = N->getOperand(1);
1069 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1070 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1071 MVT::ValueType VT = N0.getValueType();
1074 if (MVT::isVector(VT)) {
1075 SDOperand FoldedVOp = SimplifyVBinOp(N);
1076 if (FoldedVOp.Val) return FoldedVOp;
1079 // fold (mul x, undef) -> 0
1080 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1081 return DAG.getConstant(0, VT);
1082 // fold (mul c1, c2) -> c1*c2
1084 return DAG.getNode(ISD::MUL, VT, N0, N1);
1085 // canonicalize constant to RHS
1087 return DAG.getNode(ISD::MUL, VT, N1, N0);
1088 // fold (mul x, 0) -> 0
1089 if (N1C && N1C->isNullValue())
1091 // fold (mul x, -1) -> 0-x
1092 if (N1C && N1C->isAllOnesValue())
1093 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1094 // fold (mul x, (1 << c)) -> x << c
1095 if (N1C && isPowerOf2_64(N1C->getValue()))
1096 return DAG.getNode(ISD::SHL, VT, N0,
1097 DAG.getConstant(Log2_64(N1C->getValue()),
1098 TLI.getShiftAmountTy()));
1099 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1100 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
1101 // FIXME: If the input is something that is easily negated (e.g. a
1102 // single-use add), we should put the negate there.
1103 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
1104 DAG.getNode(ISD::SHL, VT, N0,
1105 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
1106 TLI.getShiftAmountTy())));
1109 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1110 if (N1C && N0.getOpcode() == ISD::SHL &&
1111 isa<ConstantSDNode>(N0.getOperand(1))) {
1112 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
1113 AddToWorkList(C3.Val);
1114 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
1117 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1120 SDOperand Sh(0,0), Y(0,0);
1121 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1122 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1123 N0.Val->hasOneUse()) {
1125 } else if (N1.getOpcode() == ISD::SHL &&
1126 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
1130 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
1131 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
1134 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1135 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1136 isa<ConstantSDNode>(N0.getOperand(1))) {
1137 return DAG.getNode(ISD::ADD, VT,
1138 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
1139 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
1143 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
1150 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
1151 SDOperand N0 = N->getOperand(0);
1152 SDOperand N1 = N->getOperand(1);
1153 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1154 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1155 MVT::ValueType VT = N->getValueType(0);
1158 if (MVT::isVector(VT)) {
1159 SDOperand FoldedVOp = SimplifyVBinOp(N);
1160 if (FoldedVOp.Val) return FoldedVOp;
1163 // fold (sdiv c1, c2) -> c1/c2
1164 if (N0C && N1C && !N1C->isNullValue())
1165 return DAG.getNode(ISD::SDIV, VT, N0, N1);
1166 // fold (sdiv X, 1) -> X
1167 if (N1C && N1C->getSignExtended() == 1LL)
1169 // fold (sdiv X, -1) -> 0-X
1170 if (N1C && N1C->isAllOnesValue())
1171 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1172 // If we know the sign bits of both operands are zero, strength reduce to a
1173 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1174 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1175 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1176 DAG.MaskedValueIsZero(N0, SignBit))
1177 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
1178 // fold (sdiv X, pow2) -> simple ops after legalize
1179 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
1180 (isPowerOf2_64(N1C->getSignExtended()) ||
1181 isPowerOf2_64(-N1C->getSignExtended()))) {
1182 // If dividing by powers of two is cheap, then don't perform the following
1184 if (TLI.isPow2DivCheap())
1186 int64_t pow2 = N1C->getSignExtended();
1187 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1188 unsigned lg2 = Log2_64(abs2);
1189 // Splat the sign bit into the register
1190 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
1191 DAG.getConstant(MVT::getSizeInBits(VT)-1,
1192 TLI.getShiftAmountTy()));
1193 AddToWorkList(SGN.Val);
1194 // Add (N0 < 0) ? abs2 - 1 : 0;
1195 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
1196 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
1197 TLI.getShiftAmountTy()));
1198 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
1199 AddToWorkList(SRL.Val);
1200 AddToWorkList(ADD.Val); // Divide by pow2
1201 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
1202 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
1203 // If we're dividing by a positive value, we're done. Otherwise, we must
1204 // negate the result.
1207 AddToWorkList(SRA.Val);
1208 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
1210 // if integer divide is expensive and we satisfy the requirements, emit an
1211 // alternate sequence.
1212 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
1213 !TLI.isIntDivCheap()) {
1214 SDOperand Op = BuildSDIV(N);
1215 if (Op.Val) return Op;
1219 if (N0.getOpcode() == ISD::UNDEF)
1220 return DAG.getConstant(0, VT);
1221 // X / undef -> undef
1222 if (N1.getOpcode() == ISD::UNDEF)
1228 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
1229 SDOperand N0 = N->getOperand(0);
1230 SDOperand N1 = N->getOperand(1);
1231 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1232 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1233 MVT::ValueType VT = N->getValueType(0);
1236 if (MVT::isVector(VT)) {
1237 SDOperand FoldedVOp = SimplifyVBinOp(N);
1238 if (FoldedVOp.Val) return FoldedVOp;
1241 // fold (udiv c1, c2) -> c1/c2
1242 if (N0C && N1C && !N1C->isNullValue())
1243 return DAG.getNode(ISD::UDIV, VT, N0, N1);
1244 // fold (udiv x, (1 << c)) -> x >>u c
1245 if (N1C && isPowerOf2_64(N1C->getValue()))
1246 return DAG.getNode(ISD::SRL, VT, N0,
1247 DAG.getConstant(Log2_64(N1C->getValue()),
1248 TLI.getShiftAmountTy()));
1249 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1250 if (N1.getOpcode() == ISD::SHL) {
1251 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1252 if (isPowerOf2_64(SHC->getValue())) {
1253 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
1254 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
1255 DAG.getConstant(Log2_64(SHC->getValue()),
1257 AddToWorkList(Add.Val);
1258 return DAG.getNode(ISD::SRL, VT, N0, Add);
1262 // fold (udiv x, c) -> alternate
1263 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
1264 SDOperand Op = BuildUDIV(N);
1265 if (Op.Val) return Op;
1269 if (N0.getOpcode() == ISD::UNDEF)
1270 return DAG.getConstant(0, VT);
1271 // X / undef -> undef
1272 if (N1.getOpcode() == ISD::UNDEF)
1278 SDOperand DAGCombiner::visitSREM(SDNode *N) {
1279 SDOperand N0 = N->getOperand(0);
1280 SDOperand N1 = N->getOperand(1);
1281 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1282 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1283 MVT::ValueType VT = N->getValueType(0);
1285 // fold (srem c1, c2) -> c1%c2
1286 if (N0C && N1C && !N1C->isNullValue())
1287 return DAG.getNode(ISD::SREM, VT, N0, N1);
1288 // If we know the sign bits of both operands are zero, strength reduce to a
1289 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1290 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1291 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1292 DAG.MaskedValueIsZero(N0, SignBit))
1293 return DAG.getNode(ISD::UREM, VT, N0, N1);
1295 // If X/C can be simplified by the division-by-constant logic, lower
1296 // X%C to the equivalent of X-X/C*C.
1297 if (N1C && !N1C->isNullValue()) {
1298 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
1299 SDOperand OptimizedDiv = combine(Div.Val);
1300 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) {
1301 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
1302 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1303 AddToWorkList(Mul.Val);
1309 if (N0.getOpcode() == ISD::UNDEF)
1310 return DAG.getConstant(0, VT);
1311 // X % undef -> undef
1312 if (N1.getOpcode() == ISD::UNDEF)
1318 SDOperand DAGCombiner::visitUREM(SDNode *N) {
1319 SDOperand N0 = N->getOperand(0);
1320 SDOperand N1 = N->getOperand(1);
1321 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1322 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1323 MVT::ValueType VT = N->getValueType(0);
1325 // fold (urem c1, c2) -> c1%c2
1326 if (N0C && N1C && !N1C->isNullValue())
1327 return DAG.getNode(ISD::UREM, VT, N0, N1);
1328 // fold (urem x, pow2) -> (and x, pow2-1)
1329 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
1330 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
1331 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1332 if (N1.getOpcode() == ISD::SHL) {
1333 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1334 if (isPowerOf2_64(SHC->getValue())) {
1335 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
1336 AddToWorkList(Add.Val);
1337 return DAG.getNode(ISD::AND, VT, N0, Add);
1342 // If X/C can be simplified by the division-by-constant logic, lower
1343 // X%C to the equivalent of X-X/C*C.
1344 if (N1C && !N1C->isNullValue()) {
1345 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
1346 SDOperand OptimizedDiv = combine(Div.Val);
1347 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) {
1348 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
1349 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1350 AddToWorkList(Mul.Val);
1356 if (N0.getOpcode() == ISD::UNDEF)
1357 return DAG.getConstant(0, VT);
1358 // X % undef -> undef
1359 if (N1.getOpcode() == ISD::UNDEF)
1365 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
1366 SDOperand N0 = N->getOperand(0);
1367 SDOperand N1 = N->getOperand(1);
1368 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1369 MVT::ValueType VT = N->getValueType(0);
1371 // fold (mulhs x, 0) -> 0
1372 if (N1C && N1C->isNullValue())
1374 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1375 if (N1C && N1C->getValue() == 1)
1376 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
1377 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
1378 TLI.getShiftAmountTy()));
1379 // fold (mulhs x, undef) -> 0
1380 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1381 return DAG.getConstant(0, VT);
1386 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
1387 SDOperand N0 = N->getOperand(0);
1388 SDOperand N1 = N->getOperand(1);
1389 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1390 MVT::ValueType VT = N->getValueType(0);
1392 // fold (mulhu x, 0) -> 0
1393 if (N1C && N1C->isNullValue())
1395 // fold (mulhu x, 1) -> 0
1396 if (N1C && N1C->getValue() == 1)
1397 return DAG.getConstant(0, N0.getValueType());
1398 // fold (mulhu x, undef) -> 0
1399 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1400 return DAG.getConstant(0, VT);
1405 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1406 /// compute two values. LoOp and HiOp give the opcodes for the two computations
1407 /// that are being performed. Return true if a simplification was made.
1409 bool DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N,
1410 unsigned LoOp, unsigned HiOp) {
1411 // If the high half is not needed, just compute the low half.
1412 bool HiExists = N->hasAnyUseOfValue(1);
1415 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1416 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0),
1417 DAG.getNode(LoOp, N->getValueType(0),
1419 N->getNumOperands()));
1423 // If the low half is not needed, just compute the high half.
1424 bool LoExists = N->hasAnyUseOfValue(0);
1427 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
1428 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1),
1429 DAG.getNode(HiOp, N->getValueType(1),
1431 N->getNumOperands()));
1435 // If both halves are used, return as it is.
1436 if (LoExists && HiExists)
1439 // If the two computed results can be simplified separately, separate them.
1440 bool RetVal = false;
1442 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0),
1443 N->op_begin(), N->getNumOperands());
1444 SDOperand LoOpt = combine(Lo.Val);
1445 if (LoOpt.Val && LoOpt != Lo &&
1446 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())) {
1448 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), LoOpt);
1453 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1),
1454 N->op_begin(), N->getNumOperands());
1455 SDOperand HiOpt = combine(Hi.Val);
1456 if (HiOpt.Val && HiOpt != Hi &&
1457 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())) {
1459 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), HiOpt);
1466 SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) {
1468 if (SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS))
1474 SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) {
1476 if (SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU))
1482 SDOperand DAGCombiner::visitSDIVREM(SDNode *N) {
1484 if (SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM))
1490 SDOperand DAGCombiner::visitUDIVREM(SDNode *N) {
1492 if (SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM))
1498 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1499 /// two operands of the same opcode, try to simplify it.
1500 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1501 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
1502 MVT::ValueType VT = N0.getValueType();
1503 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1505 // For each of OP in AND/OR/XOR:
1506 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1507 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1508 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1509 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1510 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1511 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1512 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1513 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1514 N0.getOperand(0).getValueType(),
1515 N0.getOperand(0), N1.getOperand(0));
1516 AddToWorkList(ORNode.Val);
1517 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1520 // For each of OP in SHL/SRL/SRA/AND...
1521 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1522 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1523 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1524 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1525 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1526 N0.getOperand(1) == N1.getOperand(1)) {
1527 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1528 N0.getOperand(0).getValueType(),
1529 N0.getOperand(0), N1.getOperand(0));
1530 AddToWorkList(ORNode.Val);
1531 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1537 SDOperand DAGCombiner::visitAND(SDNode *N) {
1538 SDOperand N0 = N->getOperand(0);
1539 SDOperand N1 = N->getOperand(1);
1540 SDOperand LL, LR, RL, RR, CC0, CC1;
1541 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1542 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1543 MVT::ValueType VT = N1.getValueType();
1546 if (MVT::isVector(VT)) {
1547 SDOperand FoldedVOp = SimplifyVBinOp(N);
1548 if (FoldedVOp.Val) return FoldedVOp;
1551 // fold (and x, undef) -> 0
1552 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1553 return DAG.getConstant(0, VT);
1554 // fold (and c1, c2) -> c1&c2
1556 return DAG.getNode(ISD::AND, VT, N0, N1);
1557 // canonicalize constant to RHS
1559 return DAG.getNode(ISD::AND, VT, N1, N0);
1560 // fold (and x, -1) -> x
1561 if (N1C && N1C->isAllOnesValue())
1563 // if (and x, c) is known to be zero, return 0
1564 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1565 return DAG.getConstant(0, VT);
1567 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1570 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1571 if (N1C && N0.getOpcode() == ISD::OR)
1572 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1573 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1575 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1576 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1577 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1578 if (DAG.MaskedValueIsZero(N0.getOperand(0),
1579 ~N1C->getValue() & InMask)) {
1580 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1583 // Replace uses of the AND with uses of the Zero extend node.
1586 // We actually want to replace all uses of the any_extend with the
1587 // zero_extend, to avoid duplicating things. This will later cause this
1588 // AND to be folded.
1589 CombineTo(N0.Val, Zext);
1590 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1593 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1594 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1595 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1596 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1598 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1599 MVT::isInteger(LL.getValueType())) {
1600 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1601 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1602 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1603 AddToWorkList(ORNode.Val);
1604 return DAG.getSetCC(VT, ORNode, LR, Op1);
1606 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1607 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1608 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1609 AddToWorkList(ANDNode.Val);
1610 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1612 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1613 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1614 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1615 AddToWorkList(ORNode.Val);
1616 return DAG.getSetCC(VT, ORNode, LR, Op1);
1619 // canonicalize equivalent to ll == rl
1620 if (LL == RR && LR == RL) {
1621 Op1 = ISD::getSetCCSwappedOperands(Op1);
1624 if (LL == RL && LR == RR) {
1625 bool isInteger = MVT::isInteger(LL.getValueType());
1626 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1627 if (Result != ISD::SETCC_INVALID)
1628 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1632 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1633 if (N0.getOpcode() == N1.getOpcode()) {
1634 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1635 if (Tmp.Val) return Tmp;
1638 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1639 // fold (and (sra)) -> (and (srl)) when possible.
1640 if (!MVT::isVector(VT) &&
1641 SimplifyDemandedBits(SDOperand(N, 0)))
1642 return SDOperand(N, 0);
1643 // fold (zext_inreg (extload x)) -> (zextload x)
1644 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
1645 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1646 MVT::ValueType EVT = LN0->getLoadedVT();
1647 // If we zero all the possible extended bits, then we can turn this into
1648 // a zextload if we are running before legalize or the operation is legal.
1649 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1650 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1651 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1652 LN0->getBasePtr(), LN0->getSrcValue(),
1653 LN0->getSrcValueOffset(), EVT,
1655 LN0->getAlignment());
1657 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1658 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1661 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1662 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
1664 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1665 MVT::ValueType EVT = LN0->getLoadedVT();
1666 // If we zero all the possible extended bits, then we can turn this into
1667 // a zextload if we are running before legalize or the operation is legal.
1668 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1669 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1670 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1671 LN0->getBasePtr(), LN0->getSrcValue(),
1672 LN0->getSrcValueOffset(), EVT,
1674 LN0->getAlignment());
1676 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1677 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1681 // fold (and (load x), 255) -> (zextload x, i8)
1682 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1683 if (N1C && N0.getOpcode() == ISD::LOAD) {
1684 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1685 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1686 LN0->getAddressingMode() == ISD::UNINDEXED &&
1688 MVT::ValueType EVT, LoadedVT;
1689 if (N1C->getValue() == 255)
1691 else if (N1C->getValue() == 65535)
1693 else if (N1C->getValue() == ~0U)
1698 LoadedVT = LN0->getLoadedVT();
1699 if (EVT != MVT::Other && LoadedVT > EVT &&
1700 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1701 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1702 // For big endian targets, we need to add an offset to the pointer to
1703 // load the correct bytes. For little endian systems, we merely need to
1704 // read fewer bytes from the same pointer.
1705 unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8;
1706 unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8;
1707 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
1708 unsigned Alignment = LN0->getAlignment();
1709 SDOperand NewPtr = LN0->getBasePtr();
1710 if (!TLI.isLittleEndian()) {
1711 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1712 DAG.getConstant(PtrOff, PtrType));
1713 Alignment = MinAlign(Alignment, PtrOff);
1715 AddToWorkList(NewPtr.Val);
1717 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1718 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
1719 LN0->isVolatile(), Alignment);
1721 CombineTo(N0.Val, Load, Load.getValue(1));
1722 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1730 SDOperand DAGCombiner::visitOR(SDNode *N) {
1731 SDOperand N0 = N->getOperand(0);
1732 SDOperand N1 = N->getOperand(1);
1733 SDOperand LL, LR, RL, RR, CC0, CC1;
1734 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1735 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1736 MVT::ValueType VT = N1.getValueType();
1737 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1740 if (MVT::isVector(VT)) {
1741 SDOperand FoldedVOp = SimplifyVBinOp(N);
1742 if (FoldedVOp.Val) return FoldedVOp;
1745 // fold (or x, undef) -> -1
1746 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1747 return DAG.getConstant(~0ULL, VT);
1748 // fold (or c1, c2) -> c1|c2
1750 return DAG.getNode(ISD::OR, VT, N0, N1);
1751 // canonicalize constant to RHS
1753 return DAG.getNode(ISD::OR, VT, N1, N0);
1754 // fold (or x, 0) -> x
1755 if (N1C && N1C->isNullValue())
1757 // fold (or x, -1) -> -1
1758 if (N1C && N1C->isAllOnesValue())
1760 // fold (or x, c) -> c iff (x & ~c) == 0
1762 DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1765 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1768 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1769 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1770 isa<ConstantSDNode>(N0.getOperand(1))) {
1771 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1772 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1774 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1776 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1777 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1778 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1779 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1781 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1782 MVT::isInteger(LL.getValueType())) {
1783 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1784 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1785 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1786 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1787 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1788 AddToWorkList(ORNode.Val);
1789 return DAG.getSetCC(VT, ORNode, LR, Op1);
1791 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1792 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1793 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1794 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1795 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1796 AddToWorkList(ANDNode.Val);
1797 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1800 // canonicalize equivalent to ll == rl
1801 if (LL == RR && LR == RL) {
1802 Op1 = ISD::getSetCCSwappedOperands(Op1);
1805 if (LL == RL && LR == RR) {
1806 bool isInteger = MVT::isInteger(LL.getValueType());
1807 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1808 if (Result != ISD::SETCC_INVALID)
1809 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1813 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1814 if (N0.getOpcode() == N1.getOpcode()) {
1815 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1816 if (Tmp.Val) return Tmp;
1819 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1820 if (N0.getOpcode() == ISD::AND &&
1821 N1.getOpcode() == ISD::AND &&
1822 N0.getOperand(1).getOpcode() == ISD::Constant &&
1823 N1.getOperand(1).getOpcode() == ISD::Constant &&
1824 // Don't increase # computations.
1825 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1826 // We can only do this xform if we know that bits from X that are set in C2
1827 // but not in C1 are already zero. Likewise for Y.
1828 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1829 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1831 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1832 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1833 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1834 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1839 // See if this is some rotate idiom.
1840 if (SDNode *Rot = MatchRotate(N0, N1))
1841 return SDOperand(Rot, 0);
1847 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1848 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1849 if (Op.getOpcode() == ISD::AND) {
1850 if (isa<ConstantSDNode>(Op.getOperand(1))) {
1851 Mask = Op.getOperand(1);
1852 Op = Op.getOperand(0);
1858 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1866 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1867 // idioms for rotate, and if the target supports rotation instructions, generate
1869 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1870 // Must be a legal type. Expanded an promoted things won't work with rotates.
1871 MVT::ValueType VT = LHS.getValueType();
1872 if (!TLI.isTypeLegal(VT)) return 0;
1874 // The target must have at least one rotate flavor.
1875 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1876 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1877 if (!HasROTL && !HasROTR) return 0;
1879 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1880 SDOperand LHSShift; // The shift.
1881 SDOperand LHSMask; // AND value if any.
1882 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1883 return 0; // Not part of a rotate.
1885 SDOperand RHSShift; // The shift.
1886 SDOperand RHSMask; // AND value if any.
1887 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1888 return 0; // Not part of a rotate.
1890 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1891 return 0; // Not shifting the same value.
1893 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1894 return 0; // Shifts must disagree.
1896 // Canonicalize shl to left side in a shl/srl pair.
1897 if (RHSShift.getOpcode() == ISD::SHL) {
1898 std::swap(LHS, RHS);
1899 std::swap(LHSShift, RHSShift);
1900 std::swap(LHSMask , RHSMask );
1903 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1904 SDOperand LHSShiftArg = LHSShift.getOperand(0);
1905 SDOperand LHSShiftAmt = LHSShift.getOperand(1);
1906 SDOperand RHSShiftAmt = RHSShift.getOperand(1);
1908 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1909 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1910 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
1911 RHSShiftAmt.getOpcode() == ISD::Constant) {
1912 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue();
1913 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue();
1914 if ((LShVal + RShVal) != OpSizeInBits)
1919 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt);
1921 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
1923 // If there is an AND of either shifted operand, apply it to the result.
1924 if (LHSMask.Val || RHSMask.Val) {
1925 uint64_t Mask = MVT::getIntVTBitMask(VT);
1928 uint64_t RHSBits = (1ULL << LShVal)-1;
1929 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1932 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1933 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1936 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1942 // If there is a mask here, and we have a variable shift, we can't be sure
1943 // that we're masking out the right stuff.
1944 if (LHSMask.Val || RHSMask.Val)
1947 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1948 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1949 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
1950 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
1951 if (ConstantSDNode *SUBC =
1952 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
1953 if (SUBC->getValue() == OpSizeInBits)
1955 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1957 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1961 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1962 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1963 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
1964 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
1965 if (ConstantSDNode *SUBC =
1966 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
1967 if (SUBC->getValue() == OpSizeInBits)
1969 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1971 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1975 // Look for sign/zext/any-extended cases:
1976 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1977 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1978 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) &&
1979 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1980 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1981 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) {
1982 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0);
1983 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0);
1984 if (RExtOp0.getOpcode() == ISD::SUB &&
1985 RExtOp0.getOperand(1) == LExtOp0) {
1986 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1988 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1989 // (rotl x, (sub 32, y))
1990 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
1991 if (SUBC->getValue() == OpSizeInBits) {
1993 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1995 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1998 } else if (LExtOp0.getOpcode() == ISD::SUB &&
1999 RExtOp0 == LExtOp0.getOperand(1)) {
2000 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
2002 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
2003 // (rotr x, (sub 32, y))
2004 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2005 if (SUBC->getValue() == OpSizeInBits) {
2007 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val;
2009 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
2019 SDOperand DAGCombiner::visitXOR(SDNode *N) {
2020 SDOperand N0 = N->getOperand(0);
2021 SDOperand N1 = N->getOperand(1);
2022 SDOperand LHS, RHS, CC;
2023 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2024 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2025 MVT::ValueType VT = N0.getValueType();
2028 if (MVT::isVector(VT)) {
2029 SDOperand FoldedVOp = SimplifyVBinOp(N);
2030 if (FoldedVOp.Val) return FoldedVOp;
2033 // fold (xor x, undef) -> undef
2034 if (N0.getOpcode() == ISD::UNDEF)
2036 if (N1.getOpcode() == ISD::UNDEF)
2038 // fold (xor c1, c2) -> c1^c2
2040 return DAG.getNode(ISD::XOR, VT, N0, N1);
2041 // canonicalize constant to RHS
2043 return DAG.getNode(ISD::XOR, VT, N1, N0);
2044 // fold (xor x, 0) -> x
2045 if (N1C && N1C->isNullValue())
2048 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
2051 // fold !(x cc y) -> (x !cc y)
2052 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2053 bool isInt = MVT::isInteger(LHS.getValueType());
2054 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2056 if (N0.getOpcode() == ISD::SETCC)
2057 return DAG.getSetCC(VT, LHS, RHS, NotCC);
2058 if (N0.getOpcode() == ISD::SELECT_CC)
2059 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
2060 assert(0 && "Unhandled SetCC Equivalent!");
2063 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2064 if (N1C && N1C->getValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2065 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2066 SDOperand V = N0.getOperand(0);
2067 V = DAG.getNode(ISD::XOR, V.getValueType(), V,
2068 DAG.getConstant(1, V.getValueType()));
2069 AddToWorkList(V.Val);
2070 return DAG.getNode(ISD::ZERO_EXTEND, VT, V);
2073 // fold !(x or y) -> (!x and !y) iff x or y are setcc
2074 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 &&
2075 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2076 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2077 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2078 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2079 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
2080 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
2081 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
2082 return DAG.getNode(NewOpcode, VT, LHS, RHS);
2085 // fold !(x or y) -> (!x and !y) iff x or y are constants
2086 if (N1C && N1C->isAllOnesValue() &&
2087 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2088 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2089 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2090 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2091 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
2092 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
2093 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
2094 return DAG.getNode(NewOpcode, VT, LHS, RHS);
2097 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
2098 if (N1C && N0.getOpcode() == ISD::XOR) {
2099 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2100 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2102 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
2103 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
2105 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
2106 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
2108 // fold (xor x, x) -> 0
2110 if (!MVT::isVector(VT)) {
2111 return DAG.getConstant(0, VT);
2112 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
2113 // Produce a vector of zeros.
2114 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT));
2115 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
2116 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
2120 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2121 if (N0.getOpcode() == N1.getOpcode()) {
2122 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2123 if (Tmp.Val) return Tmp;
2126 // Simplify the expression using non-local knowledge.
2127 if (!MVT::isVector(VT) &&
2128 SimplifyDemandedBits(SDOperand(N, 0)))
2129 return SDOperand(N, 0);
2134 /// visitShiftByConstant - Handle transforms common to the three shifts, when
2135 /// the shift amount is a constant.
2136 SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
2137 SDNode *LHS = N->getOperand(0).Val;
2138 if (!LHS->hasOneUse()) return SDOperand();
2140 // We want to pull some binops through shifts, so that we have (and (shift))
2141 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
2142 // thing happens with address calculations, so it's important to canonicalize
2144 bool HighBitSet = false; // Can we transform this if the high bit is set?
2146 switch (LHS->getOpcode()) {
2147 default: return SDOperand();
2150 HighBitSet = false; // We can only transform sra if the high bit is clear.
2153 HighBitSet = true; // We can only transform sra if the high bit is set.
2156 if (N->getOpcode() != ISD::SHL)
2157 return SDOperand(); // only shl(add) not sr[al](add).
2158 HighBitSet = false; // We can only transform sra if the high bit is clear.
2162 // We require the RHS of the binop to be a constant as well.
2163 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
2164 if (!BinOpCst) return SDOperand();
2167 // FIXME: disable this for unless the input to the binop is a shift by a
2168 // constant. If it is not a shift, it pessimizes some common cases like:
2170 //void foo(int *X, int i) { X[i & 1235] = 1; }
2171 //int bar(int *X, int i) { return X[i & 255]; }
2172 SDNode *BinOpLHSVal = LHS->getOperand(0).Val;
2173 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
2174 BinOpLHSVal->getOpcode() != ISD::SRA &&
2175 BinOpLHSVal->getOpcode() != ISD::SRL) ||
2176 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
2179 MVT::ValueType VT = N->getValueType(0);
2181 // If this is a signed shift right, and the high bit is modified
2182 // by the logical operation, do not perform the transformation.
2183 // The highBitSet boolean indicates the value of the high bit of
2184 // the constant which would cause it to be modified for this
2186 if (N->getOpcode() == ISD::SRA) {
2187 uint64_t BinOpRHSSign = BinOpCst->getValue() >> MVT::getSizeInBits(VT)-1;
2188 if ((bool)BinOpRHSSign != HighBitSet)
2192 // Fold the constants, shifting the binop RHS by the shift amount.
2193 SDOperand NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0),
2194 LHS->getOperand(1), N->getOperand(1));
2196 // Create the new shift.
2197 SDOperand NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0),
2200 // Create the new binop.
2201 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS);
2205 SDOperand DAGCombiner::visitSHL(SDNode *N) {
2206 SDOperand N0 = N->getOperand(0);
2207 SDOperand N1 = N->getOperand(1);
2208 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2209 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2210 MVT::ValueType VT = N0.getValueType();
2211 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2213 // fold (shl c1, c2) -> c1<<c2
2215 return DAG.getNode(ISD::SHL, VT, N0, N1);
2216 // fold (shl 0, x) -> 0
2217 if (N0C && N0C->isNullValue())
2219 // fold (shl x, c >= size(x)) -> undef
2220 if (N1C && N1C->getValue() >= OpSizeInBits)
2221 return DAG.getNode(ISD::UNDEF, VT);
2222 // fold (shl x, 0) -> x
2223 if (N1C && N1C->isNullValue())
2225 // if (shl x, c) is known to be zero, return 0
2226 if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
2227 return DAG.getConstant(0, VT);
2228 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2229 return SDOperand(N, 0);
2230 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
2231 if (N1C && N0.getOpcode() == ISD::SHL &&
2232 N0.getOperand(1).getOpcode() == ISD::Constant) {
2233 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2234 uint64_t c2 = N1C->getValue();
2235 if (c1 + c2 > OpSizeInBits)
2236 return DAG.getConstant(0, VT);
2237 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
2238 DAG.getConstant(c1 + c2, N1.getValueType()));
2240 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
2241 // (srl (and x, -1 << c1), c1-c2)
2242 if (N1C && N0.getOpcode() == ISD::SRL &&
2243 N0.getOperand(1).getOpcode() == ISD::Constant) {
2244 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2245 uint64_t c2 = N1C->getValue();
2246 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2247 DAG.getConstant(~0ULL << c1, VT));
2249 return DAG.getNode(ISD::SHL, VT, Mask,
2250 DAG.getConstant(c2-c1, N1.getValueType()));
2252 return DAG.getNode(ISD::SRL, VT, Mask,
2253 DAG.getConstant(c1-c2, N1.getValueType()));
2255 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
2256 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
2257 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2258 DAG.getConstant(~0ULL << N1C->getValue(), VT));
2260 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand();
2263 SDOperand DAGCombiner::visitSRA(SDNode *N) {
2264 SDOperand N0 = N->getOperand(0);
2265 SDOperand N1 = N->getOperand(1);
2266 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2267 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2268 MVT::ValueType VT = N0.getValueType();
2270 // fold (sra c1, c2) -> c1>>c2
2272 return DAG.getNode(ISD::SRA, VT, N0, N1);
2273 // fold (sra 0, x) -> 0
2274 if (N0C && N0C->isNullValue())
2276 // fold (sra -1, x) -> -1
2277 if (N0C && N0C->isAllOnesValue())
2279 // fold (sra x, c >= size(x)) -> undef
2280 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
2281 return DAG.getNode(ISD::UNDEF, VT);
2282 // fold (sra x, 0) -> x
2283 if (N1C && N1C->isNullValue())
2285 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2287 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2288 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
2291 default: EVT = MVT::Other; break;
2292 case 1: EVT = MVT::i1; break;
2293 case 8: EVT = MVT::i8; break;
2294 case 16: EVT = MVT::i16; break;
2295 case 32: EVT = MVT::i32; break;
2297 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
2298 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
2299 DAG.getValueType(EVT));
2302 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
2303 if (N1C && N0.getOpcode() == ISD::SRA) {
2304 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2305 unsigned Sum = N1C->getValue() + C1->getValue();
2306 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
2307 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
2308 DAG.getConstant(Sum, N1C->getValueType(0)));
2312 // Simplify, based on bits shifted out of the LHS.
2313 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2314 return SDOperand(N, 0);
2317 // If the sign bit is known to be zero, switch this to a SRL.
2318 if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
2319 return DAG.getNode(ISD::SRL, VT, N0, N1);
2321 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand();
2324 SDOperand DAGCombiner::visitSRL(SDNode *N) {
2325 SDOperand N0 = N->getOperand(0);
2326 SDOperand N1 = N->getOperand(1);
2327 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2328 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2329 MVT::ValueType VT = N0.getValueType();
2330 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2332 // fold (srl c1, c2) -> c1 >>u c2
2334 return DAG.getNode(ISD::SRL, VT, N0, N1);
2335 // fold (srl 0, x) -> 0
2336 if (N0C && N0C->isNullValue())
2338 // fold (srl x, c >= size(x)) -> undef
2339 if (N1C && N1C->getValue() >= OpSizeInBits)
2340 return DAG.getNode(ISD::UNDEF, VT);
2341 // fold (srl x, 0) -> x
2342 if (N1C && N1C->isNullValue())
2344 // if (srl x, c) is known to be zero, return 0
2345 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
2346 return DAG.getConstant(0, VT);
2348 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
2349 if (N1C && N0.getOpcode() == ISD::SRL &&
2350 N0.getOperand(1).getOpcode() == ISD::Constant) {
2351 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2352 uint64_t c2 = N1C->getValue();
2353 if (c1 + c2 > OpSizeInBits)
2354 return DAG.getConstant(0, VT);
2355 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
2356 DAG.getConstant(c1 + c2, N1.getValueType()));
2359 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
2360 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2361 // Shifting in all undef bits?
2362 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
2363 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
2364 return DAG.getNode(ISD::UNDEF, VT);
2366 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
2367 AddToWorkList(SmallShift.Val);
2368 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
2371 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
2372 // bit, which is unmodified by sra.
2373 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
2374 if (N0.getOpcode() == ISD::SRA)
2375 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
2378 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
2379 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2380 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
2381 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
2382 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
2384 // If any of the input bits are KnownOne, then the input couldn't be all
2385 // zeros, thus the result of the srl will always be zero.
2386 if (KnownOne) return DAG.getConstant(0, VT);
2388 // If all of the bits input the to ctlz node are known to be zero, then
2389 // the result of the ctlz is "32" and the result of the shift is one.
2390 uint64_t UnknownBits = ~KnownZero & Mask;
2391 if (UnknownBits == 0) return DAG.getConstant(1, VT);
2393 // Otherwise, check to see if there is exactly one bit input to the ctlz.
2394 if ((UnknownBits & (UnknownBits-1)) == 0) {
2395 // Okay, we know that only that the single bit specified by UnknownBits
2396 // could be set on input to the CTLZ node. If this bit is set, the SRL
2397 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
2398 // to an SRL,XOR pair, which is likely to simplify more.
2399 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
2400 SDOperand Op = N0.getOperand(0);
2402 Op = DAG.getNode(ISD::SRL, VT, Op,
2403 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
2404 AddToWorkList(Op.Val);
2406 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
2410 // fold operands of srl based on knowledge that the low bits are not
2412 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2413 return SDOperand(N, 0);
2415 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand();
2418 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
2419 SDOperand N0 = N->getOperand(0);
2420 MVT::ValueType VT = N->getValueType(0);
2422 // fold (ctlz c1) -> c2
2423 if (isa<ConstantSDNode>(N0))
2424 return DAG.getNode(ISD::CTLZ, VT, N0);
2428 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
2429 SDOperand N0 = N->getOperand(0);
2430 MVT::ValueType VT = N->getValueType(0);
2432 // fold (cttz c1) -> c2
2433 if (isa<ConstantSDNode>(N0))
2434 return DAG.getNode(ISD::CTTZ, VT, N0);
2438 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
2439 SDOperand N0 = N->getOperand(0);
2440 MVT::ValueType VT = N->getValueType(0);
2442 // fold (ctpop c1) -> c2
2443 if (isa<ConstantSDNode>(N0))
2444 return DAG.getNode(ISD::CTPOP, VT, N0);
2448 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
2449 SDOperand N0 = N->getOperand(0);
2450 SDOperand N1 = N->getOperand(1);
2451 SDOperand N2 = N->getOperand(2);
2452 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2453 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2454 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2455 MVT::ValueType VT = N->getValueType(0);
2456 MVT::ValueType VT0 = N0.getValueType();
2458 // fold select C, X, X -> X
2461 // fold select true, X, Y -> X
2462 if (N0C && !N0C->isNullValue())
2464 // fold select false, X, Y -> Y
2465 if (N0C && N0C->isNullValue())
2467 // fold select C, 1, X -> C | X
2468 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
2469 return DAG.getNode(ISD::OR, VT, N0, N2);
2470 // fold select C, 0, 1 -> ~C
2471 if (MVT::isInteger(VT) && MVT::isInteger(VT0) &&
2472 N1C && N2C && N1C->isNullValue() && N2C->getValue() == 1) {
2473 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0));
2476 AddToWorkList(XORNode.Val);
2477 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0))
2478 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
2479 return DAG.getNode(ISD::TRUNCATE, VT, XORNode);
2481 // fold select C, 0, X -> ~C & X
2482 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
2483 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2484 AddToWorkList(XORNode.Val);
2485 return DAG.getNode(ISD::AND, VT, XORNode, N2);
2487 // fold select C, X, 1 -> ~C | X
2488 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getValue() == 1) {
2489 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2490 AddToWorkList(XORNode.Val);
2491 return DAG.getNode(ISD::OR, VT, XORNode, N1);
2493 // fold select C, X, 0 -> C & X
2494 // FIXME: this should check for C type == X type, not i1?
2495 if (MVT::i1 == VT && N2C && N2C->isNullValue())
2496 return DAG.getNode(ISD::AND, VT, N0, N1);
2497 // fold X ? X : Y --> X ? 1 : Y --> X | Y
2498 if (MVT::i1 == VT && N0 == N1)
2499 return DAG.getNode(ISD::OR, VT, N0, N2);
2500 // fold X ? Y : X --> X ? Y : 0 --> X & Y
2501 if (MVT::i1 == VT && N0 == N2)
2502 return DAG.getNode(ISD::AND, VT, N0, N1);
2504 // If we can fold this based on the true/false value, do so.
2505 if (SimplifySelectOps(N, N1, N2))
2506 return SDOperand(N, 0); // Don't revisit N.
2508 // fold selects based on a setcc into other things, such as min/max/abs
2509 if (N0.getOpcode() == ISD::SETCC)
2511 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
2512 // having to say they don't support SELECT_CC on every type the DAG knows
2513 // about, since there is no way to mark an opcode illegal at all value types
2514 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
2515 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
2516 N1, N2, N0.getOperand(2));
2518 return SimplifySelect(N0, N1, N2);
2522 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
2523 SDOperand N0 = N->getOperand(0);
2524 SDOperand N1 = N->getOperand(1);
2525 SDOperand N2 = N->getOperand(2);
2526 SDOperand N3 = N->getOperand(3);
2527 SDOperand N4 = N->getOperand(4);
2528 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
2530 // fold select_cc lhs, rhs, x, x, cc -> x
2534 // Determine if the condition we're dealing with is constant
2535 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
2536 if (SCC.Val) AddToWorkList(SCC.Val);
2538 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
2539 if (SCCC->getValue())
2540 return N2; // cond always true -> true val
2542 return N3; // cond always false -> false val
2545 // Fold to a simpler select_cc
2546 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
2547 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
2548 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
2551 // If we can fold this based on the true/false value, do so.
2552 if (SimplifySelectOps(N, N2, N3))
2553 return SDOperand(N, 0); // Don't revisit N.
2555 // fold select_cc into other things, such as min/max/abs
2556 return SimplifySelectCC(N0, N1, N2, N3, CC);
2559 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
2560 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
2561 cast<CondCodeSDNode>(N->getOperand(2))->get());
2564 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
2565 // "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))"
2566 // transformation. Returns true if extension are possible and the above
2567 // mentioned transformation is profitable.
2568 static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0,
2570 SmallVector<SDNode*, 4> &ExtendNodes,
2571 TargetLowering &TLI) {
2572 bool HasCopyToRegUses = false;
2573 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
2574 for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end();
2579 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
2580 if (User->getOpcode() == ISD::SETCC) {
2581 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
2582 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
2583 // Sign bits will be lost after a zext.
2586 for (unsigned i = 0; i != 2; ++i) {
2587 SDOperand UseOp = User->getOperand(i);
2590 if (!isa<ConstantSDNode>(UseOp))
2595 ExtendNodes.push_back(User);
2597 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2598 SDOperand UseOp = User->getOperand(i);
2600 // If truncate from extended type to original load type is free
2601 // on this target, then it's ok to extend a CopyToReg.
2602 if (isTruncFree && User->getOpcode() == ISD::CopyToReg)
2603 HasCopyToRegUses = true;
2611 if (HasCopyToRegUses) {
2612 bool BothLiveOut = false;
2613 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
2616 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2617 SDOperand UseOp = User->getOperand(i);
2618 if (UseOp.Val == N && UseOp.ResNo == 0) {
2625 // Both unextended and extended values are live out. There had better be
2626 // good a reason for the transformation.
2627 return ExtendNodes.size();
2632 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
2633 SDOperand N0 = N->getOperand(0);
2634 MVT::ValueType VT = N->getValueType(0);
2636 // fold (sext c1) -> c1
2637 if (isa<ConstantSDNode>(N0))
2638 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
2640 // fold (sext (sext x)) -> (sext x)
2641 // fold (sext (aext x)) -> (sext x)
2642 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2643 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
2645 // fold (sext (truncate (load x))) -> (sext (smaller load x))
2646 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
2647 if (N0.getOpcode() == ISD::TRUNCATE) {
2648 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2649 if (NarrowLoad.Val) {
2650 if (NarrowLoad.Val != N0.Val)
2651 CombineTo(N0.Val, NarrowLoad);
2652 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad);
2656 // See if the value being truncated is already sign extended. If so, just
2657 // eliminate the trunc/sext pair.
2658 if (N0.getOpcode() == ISD::TRUNCATE) {
2659 SDOperand Op = N0.getOperand(0);
2660 unsigned OpBits = MVT::getSizeInBits(Op.getValueType());
2661 unsigned MidBits = MVT::getSizeInBits(N0.getValueType());
2662 unsigned DestBits = MVT::getSizeInBits(VT);
2663 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
2665 if (OpBits == DestBits) {
2666 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
2667 // bits, it is already ready.
2668 if (NumSignBits > DestBits-MidBits)
2670 } else if (OpBits < DestBits) {
2671 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
2672 // bits, just sext from i32.
2673 if (NumSignBits > OpBits-MidBits)
2674 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op);
2676 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
2677 // bits, just truncate to i32.
2678 if (NumSignBits > OpBits-MidBits)
2679 return DAG.getNode(ISD::TRUNCATE, VT, Op);
2682 // fold (sext (truncate x)) -> (sextinreg x).
2683 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
2684 N0.getValueType())) {
2685 if (Op.getValueType() < VT)
2686 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2687 else if (Op.getValueType() > VT)
2688 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2689 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
2690 DAG.getValueType(N0.getValueType()));
2694 // fold (sext (load x)) -> (sext (truncate (sextload x)))
2695 if (ISD::isNON_EXTLoad(N0.Val) &&
2696 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
2697 bool DoXform = true;
2698 SmallVector<SDNode*, 4> SetCCs;
2699 if (!N0.hasOneUse())
2700 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
2702 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2703 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2704 LN0->getBasePtr(), LN0->getSrcValue(),
2705 LN0->getSrcValueOffset(),
2708 LN0->getAlignment());
2709 CombineTo(N, ExtLoad);
2710 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
2711 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
2712 // Extend SetCC uses if necessary.
2713 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
2714 SDNode *SetCC = SetCCs[i];
2715 SmallVector<SDOperand, 4> Ops;
2716 for (unsigned j = 0; j != 2; ++j) {
2717 SDOperand SOp = SetCC->getOperand(j);
2719 Ops.push_back(ExtLoad);
2721 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp));
2723 Ops.push_back(SetCC->getOperand(2));
2724 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0),
2725 &Ops[0], Ops.size()));
2727 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2731 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
2732 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
2733 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2734 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2735 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2736 MVT::ValueType EVT = LN0->getLoadedVT();
2737 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
2738 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2739 LN0->getBasePtr(), LN0->getSrcValue(),
2740 LN0->getSrcValueOffset(), EVT,
2742 LN0->getAlignment());
2743 CombineTo(N, ExtLoad);
2744 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2745 ExtLoad.getValue(1));
2746 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2750 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc
2751 if (N0.getOpcode() == ISD::SETCC) {
2753 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2754 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
2755 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2756 if (SCC.Val) return SCC;
2762 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
2763 SDOperand N0 = N->getOperand(0);
2764 MVT::ValueType VT = N->getValueType(0);
2766 // fold (zext c1) -> c1
2767 if (isa<ConstantSDNode>(N0))
2768 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2769 // fold (zext (zext x)) -> (zext x)
2770 // fold (zext (aext x)) -> (zext x)
2771 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2772 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
2774 // fold (zext (truncate (load x))) -> (zext (smaller load x))
2775 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
2776 if (N0.getOpcode() == ISD::TRUNCATE) {
2777 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2778 if (NarrowLoad.Val) {
2779 if (NarrowLoad.Val != N0.Val)
2780 CombineTo(N0.Val, NarrowLoad);
2781 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad);
2785 // fold (zext (truncate x)) -> (and x, mask)
2786 if (N0.getOpcode() == ISD::TRUNCATE &&
2787 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
2788 SDOperand Op = N0.getOperand(0);
2789 if (Op.getValueType() < VT) {
2790 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2791 } else if (Op.getValueType() > VT) {
2792 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2794 return DAG.getZeroExtendInReg(Op, N0.getValueType());
2797 // fold (zext (and (trunc x), cst)) -> (and x, cst).
2798 if (N0.getOpcode() == ISD::AND &&
2799 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2800 N0.getOperand(1).getOpcode() == ISD::Constant) {
2801 SDOperand X = N0.getOperand(0).getOperand(0);
2802 if (X.getValueType() < VT) {
2803 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2804 } else if (X.getValueType() > VT) {
2805 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2807 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2808 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2811 // fold (zext (load x)) -> (zext (truncate (zextload x)))
2812 if (ISD::isNON_EXTLoad(N0.Val) &&
2813 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
2814 bool DoXform = true;
2815 SmallVector<SDNode*, 4> SetCCs;
2816 if (!N0.hasOneUse())
2817 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
2819 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2820 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2821 LN0->getBasePtr(), LN0->getSrcValue(),
2822 LN0->getSrcValueOffset(),
2825 LN0->getAlignment());
2826 CombineTo(N, ExtLoad);
2827 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
2828 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
2829 // Extend SetCC uses if necessary.
2830 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
2831 SDNode *SetCC = SetCCs[i];
2832 SmallVector<SDOperand, 4> Ops;
2833 for (unsigned j = 0; j != 2; ++j) {
2834 SDOperand SOp = SetCC->getOperand(j);
2836 Ops.push_back(ExtLoad);
2838 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp));
2840 Ops.push_back(SetCC->getOperand(2));
2841 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0),
2842 &Ops[0], Ops.size()));
2844 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2848 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
2849 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
2850 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2851 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2852 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2853 MVT::ValueType EVT = LN0->getLoadedVT();
2854 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2855 LN0->getBasePtr(), LN0->getSrcValue(),
2856 LN0->getSrcValueOffset(), EVT,
2858 LN0->getAlignment());
2859 CombineTo(N, ExtLoad);
2860 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2861 ExtLoad.getValue(1));
2862 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2865 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2866 if (N0.getOpcode() == ISD::SETCC) {
2868 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2869 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2870 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2871 if (SCC.Val) return SCC;
2877 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
2878 SDOperand N0 = N->getOperand(0);
2879 MVT::ValueType VT = N->getValueType(0);
2881 // fold (aext c1) -> c1
2882 if (isa<ConstantSDNode>(N0))
2883 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
2884 // fold (aext (aext x)) -> (aext x)
2885 // fold (aext (zext x)) -> (zext x)
2886 // fold (aext (sext x)) -> (sext x)
2887 if (N0.getOpcode() == ISD::ANY_EXTEND ||
2888 N0.getOpcode() == ISD::ZERO_EXTEND ||
2889 N0.getOpcode() == ISD::SIGN_EXTEND)
2890 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2892 // fold (aext (truncate (load x))) -> (aext (smaller load x))
2893 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
2894 if (N0.getOpcode() == ISD::TRUNCATE) {
2895 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2896 if (NarrowLoad.Val) {
2897 if (NarrowLoad.Val != N0.Val)
2898 CombineTo(N0.Val, NarrowLoad);
2899 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad);
2903 // fold (aext (truncate x))
2904 if (N0.getOpcode() == ISD::TRUNCATE) {
2905 SDOperand TruncOp = N0.getOperand(0);
2906 if (TruncOp.getValueType() == VT)
2907 return TruncOp; // x iff x size == zext size.
2908 if (TruncOp.getValueType() > VT)
2909 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
2910 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
2913 // fold (aext (and (trunc x), cst)) -> (and x, cst).
2914 if (N0.getOpcode() == ISD::AND &&
2915 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2916 N0.getOperand(1).getOpcode() == ISD::Constant) {
2917 SDOperand X = N0.getOperand(0).getOperand(0);
2918 if (X.getValueType() < VT) {
2919 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2920 } else if (X.getValueType() > VT) {
2921 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2923 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2924 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2927 // fold (aext (load x)) -> (aext (truncate (extload x)))
2928 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2929 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2930 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2931 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2932 LN0->getBasePtr(), LN0->getSrcValue(),
2933 LN0->getSrcValueOffset(),
2936 LN0->getAlignment());
2937 CombineTo(N, ExtLoad);
2938 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2939 ExtLoad.getValue(1));
2940 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2943 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2944 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2945 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2946 if (N0.getOpcode() == ISD::LOAD &&
2947 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
2949 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2950 MVT::ValueType EVT = LN0->getLoadedVT();
2951 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2952 LN0->getChain(), LN0->getBasePtr(),
2954 LN0->getSrcValueOffset(), EVT,
2956 LN0->getAlignment());
2957 CombineTo(N, ExtLoad);
2958 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2959 ExtLoad.getValue(1));
2960 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2963 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2964 if (N0.getOpcode() == ISD::SETCC) {
2966 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2967 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2968 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2976 /// GetDemandedBits - See if the specified operand can be simplified with the
2977 /// knowledge that only the bits specified by Mask are used. If so, return the
2978 /// simpler operand, otherwise return a null SDOperand.
2979 SDOperand DAGCombiner::GetDemandedBits(SDOperand V, uint64_t Mask) {
2980 switch (V.getOpcode()) {
2984 // If the LHS or RHS don't contribute bits to the or, drop them.
2985 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
2986 return V.getOperand(1);
2987 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
2988 return V.getOperand(0);
2991 // Only look at single-use SRLs.
2992 if (!V.Val->hasOneUse())
2994 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
2995 // See if we can recursively simplify the LHS.
2996 unsigned Amt = RHSC->getValue();
2997 Mask = (Mask << Amt) & MVT::getIntVTBitMask(V.getValueType());
2998 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), Mask);
2999 if (SimplifyLHS.Val) {
3000 return DAG.getNode(ISD::SRL, V.getValueType(),
3001 SimplifyLHS, V.getOperand(1));
3008 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
3009 /// bits and then truncated to a narrower type and where N is a multiple
3010 /// of number of bits of the narrower type, transform it to a narrower load
3011 /// from address + N / num of bits of new type. If the result is to be
3012 /// extended, also fold the extension to form a extending load.
3013 SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
3014 unsigned Opc = N->getOpcode();
3015 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
3016 SDOperand N0 = N->getOperand(0);
3017 MVT::ValueType VT = N->getValueType(0);
3018 MVT::ValueType EVT = N->getValueType(0);
3020 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
3022 if (Opc == ISD::SIGN_EXTEND_INREG) {
3023 ExtType = ISD::SEXTLOAD;
3024 EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3025 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))
3029 unsigned EVTBits = MVT::getSizeInBits(EVT);
3031 bool CombineSRL = false;
3032 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
3033 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3034 ShAmt = N01->getValue();
3035 // Is the shift amount a multiple of size of VT?
3036 if ((ShAmt & (EVTBits-1)) == 0) {
3037 N0 = N0.getOperand(0);
3038 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits)
3045 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
3046 // Do not allow folding to i1 here. i1 is implicitly stored in memory in
3047 // zero extended form: by shrinking the load, we lose track of the fact
3048 // that it is already zero extended.
3049 // FIXME: This should be reevaluated.
3051 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits &&
3052 "Cannot truncate to larger type!");
3053 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3054 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
3055 // For big endian targets, we need to adjust the offset to the pointer to
3056 // load the correct bytes.
3057 if (!TLI.isLittleEndian()) {
3058 unsigned LVTStoreBits = MVT::getStoreSizeInBits(N0.getValueType());
3059 unsigned EVTStoreBits = MVT::getStoreSizeInBits(EVT);
3060 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
3062 uint64_t PtrOff = ShAmt / 8;
3063 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
3064 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
3065 DAG.getConstant(PtrOff, PtrType));
3066 AddToWorkList(NewPtr.Val);
3067 SDOperand Load = (ExtType == ISD::NON_EXTLOAD)
3068 ? DAG.getLoad(VT, LN0->getChain(), NewPtr,
3069 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3070 LN0->isVolatile(), NewAlign)
3071 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr,
3072 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
3073 LN0->isVolatile(), NewAlign);
3076 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
3077 CombineTo(N->getOperand(0).Val, Load);
3079 CombineTo(N0.Val, Load, Load.getValue(1));
3081 if (Opc == ISD::SIGN_EXTEND_INREG)
3082 return DAG.getNode(Opc, VT, Load, N->getOperand(1));
3084 return DAG.getNode(Opc, VT, Load);
3086 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3093 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
3094 SDOperand N0 = N->getOperand(0);
3095 SDOperand N1 = N->getOperand(1);
3096 MVT::ValueType VT = N->getValueType(0);
3097 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
3098 unsigned EVTBits = MVT::getSizeInBits(EVT);
3100 // fold (sext_in_reg c1) -> c1
3101 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
3102 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
3104 // If the input is already sign extended, just drop the extension.
3105 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
3108 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
3109 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3110 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
3111 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
3114 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
3115 if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
3116 return DAG.getZeroExtendInReg(N0, EVT);
3118 // fold operands of sext_in_reg based on knowledge that the top bits are not
3120 if (SimplifyDemandedBits(SDOperand(N, 0)))
3121 return SDOperand(N, 0);
3123 // fold (sext_in_reg (load x)) -> (smaller sextload x)
3124 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
3125 SDOperand NarrowLoad = ReduceLoadWidth(N);
3129 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
3130 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
3131 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
3132 if (N0.getOpcode() == ISD::SRL) {
3133 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
3134 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
3135 // We can turn this into an SRA iff the input to the SRL is already sign
3137 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
3138 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
3139 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
3143 // fold (sext_inreg (extload x)) -> (sextload x)
3144 if (ISD::isEXTLoad(N0.Val) &&
3145 ISD::isUNINDEXEDLoad(N0.Val) &&
3146 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
3147 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
3148 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3149 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
3150 LN0->getBasePtr(), LN0->getSrcValue(),
3151 LN0->getSrcValueOffset(), EVT,
3153 LN0->getAlignment());
3154 CombineTo(N, ExtLoad);
3155 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
3156 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3158 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
3159 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
3161 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
3162 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
3163 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3164 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
3165 LN0->getBasePtr(), LN0->getSrcValue(),
3166 LN0->getSrcValueOffset(), EVT,
3168 LN0->getAlignment());
3169 CombineTo(N, ExtLoad);
3170 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
3171 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3176 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
3177 SDOperand N0 = N->getOperand(0);
3178 MVT::ValueType VT = N->getValueType(0);
3181 if (N0.getValueType() == N->getValueType(0))
3183 // fold (truncate c1) -> c1
3184 if (isa<ConstantSDNode>(N0))
3185 return DAG.getNode(ISD::TRUNCATE, VT, N0);
3186 // fold (truncate (truncate x)) -> (truncate x)
3187 if (N0.getOpcode() == ISD::TRUNCATE)
3188 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
3189 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
3190 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
3191 N0.getOpcode() == ISD::ANY_EXTEND) {
3192 if (N0.getOperand(0).getValueType() < VT)
3193 // if the source is smaller than the dest, we still need an extend
3194 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
3195 else if (N0.getOperand(0).getValueType() > VT)
3196 // if the source is larger than the dest, than we just need the truncate
3197 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
3199 // if the source and dest are the same type, we can drop both the extend
3201 return N0.getOperand(0);
3204 // See if we can simplify the input to this truncate through knowledge that
3205 // only the low bits are being used. For example "trunc (or (shl x, 8), y)"
3207 SDOperand Shorter = GetDemandedBits(N0, MVT::getIntVTBitMask(VT));
3209 return DAG.getNode(ISD::TRUNCATE, VT, Shorter);
3211 // fold (truncate (load x)) -> (smaller load x)
3212 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
3213 return ReduceLoadWidth(N);
3216 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
3217 SDOperand N0 = N->getOperand(0);
3218 MVT::ValueType VT = N->getValueType(0);
3220 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
3221 // Only do this before legalize, since afterward the target may be depending
3222 // on the bitconvert.
3223 // First check to see if this is all constant.
3224 if (!AfterLegalize &&
3225 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() &&
3226 MVT::isVector(VT)) {
3227 bool isSimple = true;
3228 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
3229 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
3230 N0.getOperand(i).getOpcode() != ISD::Constant &&
3231 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
3236 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0));
3237 assert(!MVT::isVector(DestEltVT) &&
3238 "Element type of vector ValueType must not be vector!");
3240 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT);
3244 // If the input is a constant, let getNode() fold it.
3245 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
3246 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
3247 if (Res.Val != N) return Res;
3250 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
3251 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
3253 // fold (conv (load x)) -> (load (conv*)x)
3254 // If the resultant load doesn't need a higher alignment than the original!
3255 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() &&
3256 TLI.isOperationLegal(ISD::LOAD, VT)) {
3257 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3258 unsigned Align = TLI.getTargetMachine().getTargetData()->
3259 getABITypeAlignment(MVT::getTypeForValueType(VT));
3260 unsigned OrigAlign = LN0->getAlignment();
3261 if (Align <= OrigAlign) {
3262 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
3263 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3264 LN0->isVolatile(), Align);
3266 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
3275 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
3276 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
3277 /// destination element value type.
3278 SDOperand DAGCombiner::
3279 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
3280 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
3282 // If this is already the right type, we're done.
3283 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
3285 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
3286 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
3288 // If this is a conversion of N elements of one type to N elements of another
3289 // type, convert each element. This handles FP<->INT cases.
3290 if (SrcBitSize == DstBitSize) {
3291 SmallVector<SDOperand, 8> Ops;
3292 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3293 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
3294 AddToWorkList(Ops.back().Val);
3297 MVT::getVectorType(DstEltVT,
3298 MVT::getVectorNumElements(BV->getValueType(0)));
3299 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3302 // Otherwise, we're growing or shrinking the elements. To avoid having to
3303 // handle annoying details of growing/shrinking FP values, we convert them to
3305 if (MVT::isFloatingPoint(SrcEltVT)) {
3306 // Convert the input float vector to a int vector where the elements are the
3308 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
3309 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
3310 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val;
3314 // Now we know the input is an integer vector. If the output is a FP type,
3315 // convert to integer first, then to FP of the right size.
3316 if (MVT::isFloatingPoint(DstEltVT)) {
3317 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
3318 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
3319 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val;
3321 // Next, convert to FP elements of the same size.
3322 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
3325 // Okay, we know the src/dst types are both integers of differing types.
3326 // Handling growing first.
3327 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
3328 if (SrcBitSize < DstBitSize) {
3329 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
3331 SmallVector<SDOperand, 8> Ops;
3332 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
3333 i += NumInputsPerOutput) {
3334 bool isLE = TLI.isLittleEndian();
3335 uint64_t NewBits = 0;
3336 bool EltIsUndef = true;
3337 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
3338 // Shift the previously computed bits over.
3339 NewBits <<= SrcBitSize;
3340 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
3341 if (Op.getOpcode() == ISD::UNDEF) continue;
3344 NewBits |= cast<ConstantSDNode>(Op)->getValue();
3348 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3350 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
3353 MVT::ValueType VT = MVT::getVectorType(DstEltVT,
3355 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3358 // Finally, this must be the case where we are shrinking elements: each input
3359 // turns into multiple outputs.
3360 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
3361 SmallVector<SDOperand, 8> Ops;
3362 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3363 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
3364 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
3365 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3368 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
3370 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
3371 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
3372 OpVal >>= DstBitSize;
3373 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
3376 // For big endian targets, swap the order of the pieces of each element.
3377 if (!TLI.isLittleEndian())
3378 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
3380 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size());
3381 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3386 SDOperand DAGCombiner::visitFADD(SDNode *N) {
3387 SDOperand N0 = N->getOperand(0);
3388 SDOperand N1 = N->getOperand(1);
3389 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3390 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3391 MVT::ValueType VT = N->getValueType(0);
3394 if (MVT::isVector(VT)) {
3395 SDOperand FoldedVOp = SimplifyVBinOp(N);
3396 if (FoldedVOp.Val) return FoldedVOp;
3399 // fold (fadd c1, c2) -> c1+c2
3400 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3401 return DAG.getNode(ISD::FADD, VT, N0, N1);
3402 // canonicalize constant to RHS
3403 if (N0CFP && !N1CFP)
3404 return DAG.getNode(ISD::FADD, VT, N1, N0);
3405 // fold (A + (-B)) -> A-B
3406 if (isNegatibleForFree(N1) == 2)
3407 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG));
3408 // fold ((-A) + B) -> B-A
3409 if (isNegatibleForFree(N0) == 2)
3410 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG));
3412 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
3413 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
3414 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3415 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
3416 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1));
3421 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
3422 SDOperand N0 = N->getOperand(0);
3423 SDOperand N1 = N->getOperand(1);
3424 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3425 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3426 MVT::ValueType VT = N->getValueType(0);
3429 if (MVT::isVector(VT)) {
3430 SDOperand FoldedVOp = SimplifyVBinOp(N);
3431 if (FoldedVOp.Val) return FoldedVOp;
3434 // fold (fsub c1, c2) -> c1-c2
3435 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3436 return DAG.getNode(ISD::FSUB, VT, N0, N1);
3438 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
3439 if (isNegatibleForFree(N1))
3440 return GetNegatedExpression(N1, DAG);
3441 return DAG.getNode(ISD::FNEG, VT, N1);
3443 // fold (A-(-B)) -> A+B
3444 if (isNegatibleForFree(N1))
3445 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG));
3450 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
3451 SDOperand N0 = N->getOperand(0);
3452 SDOperand N1 = N->getOperand(1);
3453 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3454 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3455 MVT::ValueType VT = N->getValueType(0);
3458 if (MVT::isVector(VT)) {
3459 SDOperand FoldedVOp = SimplifyVBinOp(N);
3460 if (FoldedVOp.Val) return FoldedVOp;
3463 // fold (fmul c1, c2) -> c1*c2
3464 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3465 return DAG.getNode(ISD::FMUL, VT, N0, N1);
3466 // canonicalize constant to RHS
3467 if (N0CFP && !N1CFP)
3468 return DAG.getNode(ISD::FMUL, VT, N1, N0);
3469 // fold (fmul X, 2.0) -> (fadd X, X)
3470 if (N1CFP && N1CFP->isExactlyValue(+2.0))
3471 return DAG.getNode(ISD::FADD, VT, N0, N0);
3472 // fold (fmul X, -1.0) -> (fneg X)
3473 if (N1CFP && N1CFP->isExactlyValue(-1.0))
3474 return DAG.getNode(ISD::FNEG, VT, N0);
3477 if (char LHSNeg = isNegatibleForFree(N0)) {
3478 if (char RHSNeg = isNegatibleForFree(N1)) {
3479 // Both can be negated for free, check to see if at least one is cheaper
3481 if (LHSNeg == 2 || RHSNeg == 2)
3482 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG),
3483 GetNegatedExpression(N1, DAG));
3487 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
3488 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
3489 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3490 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
3491 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1));
3496 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
3497 SDOperand N0 = N->getOperand(0);
3498 SDOperand N1 = N->getOperand(1);
3499 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3500 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3501 MVT::ValueType VT = N->getValueType(0);
3504 if (MVT::isVector(VT)) {
3505 SDOperand FoldedVOp = SimplifyVBinOp(N);
3506 if (FoldedVOp.Val) return FoldedVOp;
3509 // fold (fdiv c1, c2) -> c1/c2
3510 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3511 return DAG.getNode(ISD::FDIV, VT, N0, N1);
3515 if (char LHSNeg = isNegatibleForFree(N0)) {
3516 if (char RHSNeg = isNegatibleForFree(N1)) {
3517 // Both can be negated for free, check to see if at least one is cheaper
3519 if (LHSNeg == 2 || RHSNeg == 2)
3520 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG),
3521 GetNegatedExpression(N1, DAG));
3528 SDOperand DAGCombiner::visitFREM(SDNode *N) {
3529 SDOperand N0 = N->getOperand(0);
3530 SDOperand N1 = N->getOperand(1);
3531 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3532 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3533 MVT::ValueType VT = N->getValueType(0);
3535 // fold (frem c1, c2) -> fmod(c1,c2)
3536 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3537 return DAG.getNode(ISD::FREM, VT, N0, N1);
3542 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
3543 SDOperand N0 = N->getOperand(0);
3544 SDOperand N1 = N->getOperand(1);
3545 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3546 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3547 MVT::ValueType VT = N->getValueType(0);
3549 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
3550 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
3553 const APFloat& V = N1CFP->getValueAPF();
3554 // copysign(x, c1) -> fabs(x) iff ispos(c1)
3555 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
3556 if (!V.isNegative())
3557 return DAG.getNode(ISD::FABS, VT, N0);
3559 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
3562 // copysign(fabs(x), y) -> copysign(x, y)
3563 // copysign(fneg(x), y) -> copysign(x, y)
3564 // copysign(copysign(x,z), y) -> copysign(x, y)
3565 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
3566 N0.getOpcode() == ISD::FCOPYSIGN)
3567 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
3569 // copysign(x, abs(y)) -> abs(x)
3570 if (N1.getOpcode() == ISD::FABS)
3571 return DAG.getNode(ISD::FABS, VT, N0);
3573 // copysign(x, copysign(y,z)) -> copysign(x, z)
3574 if (N1.getOpcode() == ISD::FCOPYSIGN)
3575 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
3577 // copysign(x, fp_extend(y)) -> copysign(x, y)
3578 // copysign(x, fp_round(y)) -> copysign(x, y)
3579 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
3580 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
3587 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
3588 SDOperand N0 = N->getOperand(0);
3589 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3590 MVT::ValueType VT = N->getValueType(0);
3592 // fold (sint_to_fp c1) -> c1fp
3593 if (N0C && N0.getValueType() != MVT::ppcf128)
3594 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
3598 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
3599 SDOperand N0 = N->getOperand(0);
3600 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3601 MVT::ValueType VT = N->getValueType(0);
3603 // fold (uint_to_fp c1) -> c1fp
3604 if (N0C && N0.getValueType() != MVT::ppcf128)
3605 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
3609 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
3610 SDOperand N0 = N->getOperand(0);
3611 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3612 MVT::ValueType VT = N->getValueType(0);
3614 // fold (fp_to_sint c1fp) -> c1
3616 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
3620 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
3621 SDOperand N0 = N->getOperand(0);
3622 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3623 MVT::ValueType VT = N->getValueType(0);
3625 // fold (fp_to_uint c1fp) -> c1
3626 if (N0CFP && VT != MVT::ppcf128)
3627 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
3631 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
3632 SDOperand N0 = N->getOperand(0);
3633 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3634 MVT::ValueType VT = N->getValueType(0);
3636 // fold (fp_round c1fp) -> c1fp
3637 if (N0CFP && N0.getValueType() != MVT::ppcf128)
3638 return DAG.getNode(ISD::FP_ROUND, VT, N0);
3640 // fold (fp_round (fp_extend x)) -> x
3641 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
3642 return N0.getOperand(0);
3644 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
3645 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
3646 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
3647 AddToWorkList(Tmp.Val);
3648 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
3654 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
3655 SDOperand N0 = N->getOperand(0);
3656 MVT::ValueType VT = N->getValueType(0);
3657 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3658 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3660 // fold (fp_round_inreg c1fp) -> c1fp
3662 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT);
3663 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
3668 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
3669 SDOperand N0 = N->getOperand(0);
3670 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3671 MVT::ValueType VT = N->getValueType(0);
3673 // fold (fp_extend c1fp) -> c1fp
3674 if (N0CFP && VT != MVT::ppcf128)
3675 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
3677 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
3678 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
3679 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
3680 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3681 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
3682 LN0->getBasePtr(), LN0->getSrcValue(),
3683 LN0->getSrcValueOffset(),
3686 LN0->getAlignment());
3687 CombineTo(N, ExtLoad);
3688 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
3689 ExtLoad.getValue(1));
3690 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3697 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
3698 SDOperand N0 = N->getOperand(0);
3700 if (isNegatibleForFree(N0))
3701 return GetNegatedExpression(N0, DAG);
3706 SDOperand DAGCombiner::visitFABS(SDNode *N) {
3707 SDOperand N0 = N->getOperand(0);
3708 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3709 MVT::ValueType VT = N->getValueType(0);
3711 // fold (fabs c1) -> fabs(c1)
3712 if (N0CFP && VT != MVT::ppcf128)
3713 return DAG.getNode(ISD::FABS, VT, N0);
3714 // fold (fabs (fabs x)) -> (fabs x)
3715 if (N0.getOpcode() == ISD::FABS)
3716 return N->getOperand(0);
3717 // fold (fabs (fneg x)) -> (fabs x)
3718 // fold (fabs (fcopysign x, y)) -> (fabs x)
3719 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
3720 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
3725 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
3726 SDOperand Chain = N->getOperand(0);
3727 SDOperand N1 = N->getOperand(1);
3728 SDOperand N2 = N->getOperand(2);
3729 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3731 // never taken branch, fold to chain
3732 if (N1C && N1C->isNullValue())
3734 // unconditional branch
3735 if (N1C && N1C->getValue() == 1)
3736 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
3737 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
3739 if (N1.getOpcode() == ISD::SETCC &&
3740 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
3741 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
3742 N1.getOperand(0), N1.getOperand(1), N2);
3747 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
3749 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
3750 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
3751 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
3753 // Use SimplifySetCC to simplify SETCC's.
3754 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
3755 if (Simp.Val) AddToWorkList(Simp.Val);
3757 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
3759 // fold br_cc true, dest -> br dest (unconditional branch)
3760 if (SCCC && SCCC->getValue())
3761 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
3763 // fold br_cc false, dest -> unconditional fall through
3764 if (SCCC && SCCC->isNullValue())
3765 return N->getOperand(0);
3767 // fold to a simpler setcc
3768 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
3769 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
3770 Simp.getOperand(2), Simp.getOperand(0),
3771 Simp.getOperand(1), N->getOperand(4));
3776 /// CombineToPreIndexedLoadStore - Try turning a load / store and a
3777 /// pre-indexed load / store when the base pointer is a add or subtract
3778 /// and it has other uses besides the load / store. After the
3779 /// transformation, the new indexed load / store has effectively folded
3780 /// the add / subtract in and all of its other uses are redirected to the
3781 /// new load / store.
3782 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
3789 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3790 if (LD->getAddressingMode() != ISD::UNINDEXED)
3792 VT = LD->getLoadedVT();
3793 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
3794 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
3796 Ptr = LD->getBasePtr();
3797 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3798 if (ST->getAddressingMode() != ISD::UNINDEXED)
3800 VT = ST->getStoredVT();
3801 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
3802 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
3804 Ptr = ST->getBasePtr();
3809 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
3810 // out. There is no reason to make this a preinc/predec.
3811 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
3812 Ptr.Val->hasOneUse())
3815 // Ask the target to do addressing mode selection.
3818 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3819 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
3821 // Don't create a indexed load / store with zero offset.
3822 if (isa<ConstantSDNode>(Offset) &&
3823 cast<ConstantSDNode>(Offset)->getValue() == 0)
3826 // Try turning it into a pre-indexed load / store except when:
3827 // 1) The new base ptr is a frame index.
3828 // 2) If N is a store and the new base ptr is either the same as or is a
3829 // predecessor of the value being stored.
3830 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
3831 // that would create a cycle.
3832 // 4) All uses are load / store ops that use it as old base ptr.
3834 // Check #1. Preinc'ing a frame index would require copying the stack pointer
3835 // (plus the implicit offset) to a register to preinc anyway.
3836 if (isa<FrameIndexSDNode>(BasePtr))
3841 SDOperand Val = cast<StoreSDNode>(N)->getValue();
3842 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val))
3846 // Now check for #3 and #4.
3847 bool RealUse = false;
3848 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3849 E = Ptr.Val->use_end(); I != E; ++I) {
3853 if (Use->isPredecessor(N))
3856 if (!((Use->getOpcode() == ISD::LOAD &&
3857 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
3858 (Use->getOpcode() == ISD::STORE) &&
3859 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))
3867 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM);
3869 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
3872 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
3873 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
3875 std::vector<SDNode*> NowDead;
3877 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
3879 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
3882 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
3886 // Nodes can end up on the worklist more than once. Make sure we do
3887 // not process a node that has been replaced.
3888 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3889 removeFromWorkList(NowDead[i]);
3890 // Finally, since the node is now dead, remove it from the graph.
3893 // Replace the uses of Ptr with uses of the updated base value.
3894 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
3896 removeFromWorkList(Ptr.Val);
3897 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3898 removeFromWorkList(NowDead[i]);
3899 DAG.DeleteNode(Ptr.Val);
3904 /// CombineToPostIndexedLoadStore - Try combine a load / store with a
3905 /// add / sub of the base pointer node into a post-indexed load / store.
3906 /// The transformation folded the add / subtract into the new indexed
3907 /// load / store effectively and all of its uses are redirected to the
3908 /// new load / store.
3909 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
3916 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3917 if (LD->getAddressingMode() != ISD::UNINDEXED)
3919 VT = LD->getLoadedVT();
3920 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
3921 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
3923 Ptr = LD->getBasePtr();
3924 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3925 if (ST->getAddressingMode() != ISD::UNINDEXED)
3927 VT = ST->getStoredVT();
3928 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
3929 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
3931 Ptr = ST->getBasePtr();
3936 if (Ptr.Val->hasOneUse())
3939 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3940 E = Ptr.Val->use_end(); I != E; ++I) {
3943 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
3948 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3949 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
3951 std::swap(BasePtr, Offset);
3954 // Don't create a indexed load / store with zero offset.
3955 if (isa<ConstantSDNode>(Offset) &&
3956 cast<ConstantSDNode>(Offset)->getValue() == 0)
3959 // Try turning it into a post-indexed load / store except when
3960 // 1) All uses are load / store ops that use it as base ptr.
3961 // 2) Op must be independent of N, i.e. Op is neither a predecessor
3962 // nor a successor of N. Otherwise, if Op is folded that would
3966 bool TryNext = false;
3967 for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
3968 EE = BasePtr.Val->use_end(); II != EE; ++II) {
3973 // If all the uses are load / store addresses, then don't do the
3975 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
3976 bool RealUse = false;
3977 for (SDNode::use_iterator III = Use->use_begin(),
3978 EEE = Use->use_end(); III != EEE; ++III) {
3979 SDNode *UseUse = *III;
3980 if (!((UseUse->getOpcode() == ISD::LOAD &&
3981 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
3982 (UseUse->getOpcode() == ISD::STORE) &&
3983 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))
3997 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) {
3998 SDOperand Result = isLoad
3999 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
4000 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
4003 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
4004 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
4006 std::vector<SDNode*> NowDead;
4008 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
4010 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
4013 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
4017 // Nodes can end up on the worklist more than once. Make sure we do
4018 // not process a node that has been replaced.
4019 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
4020 removeFromWorkList(NowDead[i]);
4021 // Finally, since the node is now dead, remove it from the graph.
4024 // Replace the uses of Use with uses of the updated base value.
4025 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0),
4026 Result.getValue(isLoad ? 1 : 0),
4028 removeFromWorkList(Op);
4029 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
4030 removeFromWorkList(NowDead[i]);
4041 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
4042 LoadSDNode *LD = cast<LoadSDNode>(N);
4043 SDOperand Chain = LD->getChain();
4044 SDOperand Ptr = LD->getBasePtr();
4046 // If load is not volatile and there are no uses of the loaded value (and
4047 // the updated indexed value in case of indexed loads), change uses of the
4048 // chain value into uses of the chain input (i.e. delete the dead load).
4049 if (!LD->isVolatile()) {
4050 if (N->getValueType(1) == MVT::Other) {
4052 if (N->hasNUsesOfValue(0, 0))
4053 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
4056 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
4057 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
4058 SDOperand Undef0 = DAG.getNode(ISD::UNDEF, N->getValueType(0));
4059 SDOperand Undef1 = DAG.getNode(ISD::UNDEF, N->getValueType(1));
4060 SDOperand To[] = { Undef0, Undef1, Chain };
4061 return CombineTo(N, To, 3);
4066 // If this load is directly stored, replace the load value with the stored
4068 // TODO: Handle store large -> read small portion.
4069 // TODO: Handle TRUNCSTORE/LOADEXT
4070 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
4071 if (ISD::isNON_TRUNCStore(Chain.Val)) {
4072 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
4073 if (PrevST->getBasePtr() == Ptr &&
4074 PrevST->getValue().getValueType() == N->getValueType(0))
4075 return CombineTo(N, Chain.getOperand(1), Chain);
4080 // Walk up chain skipping non-aliasing memory nodes.
4081 SDOperand BetterChain = FindBetterChain(N, Chain);
4083 // If there is a better chain.
4084 if (Chain != BetterChain) {
4087 // Replace the chain to void dependency.
4088 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
4089 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
4090 LD->getSrcValue(), LD->getSrcValueOffset(),
4091 LD->isVolatile(), LD->getAlignment());
4093 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
4094 LD->getValueType(0),
4095 BetterChain, Ptr, LD->getSrcValue(),
4096 LD->getSrcValueOffset(),
4099 LD->getAlignment());
4102 // Create token factor to keep old chain connected.
4103 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
4104 Chain, ReplLoad.getValue(1));
4106 // Replace uses with load result and token factor. Don't add users
4108 return CombineTo(N, ReplLoad.getValue(0), Token, false);
4112 // Try transforming N to an indexed load.
4113 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4114 return SDOperand(N, 0);
4119 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
4120 StoreSDNode *ST = cast<StoreSDNode>(N);
4121 SDOperand Chain = ST->getChain();
4122 SDOperand Value = ST->getValue();
4123 SDOperand Ptr = ST->getBasePtr();
4125 // If this is a store of a bit convert, store the input value if the
4126 // resultant store does not need a higher alignment than the original.
4127 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
4128 ST->getAddressingMode() == ISD::UNINDEXED) {
4129 unsigned Align = ST->getAlignment();
4130 MVT::ValueType SVT = Value.getOperand(0).getValueType();
4131 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
4132 getABITypeAlignment(MVT::getTypeForValueType(SVT));
4133 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT))
4134 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
4135 ST->getSrcValueOffset(), ST->isVolatile(), Align);
4138 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
4139 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
4140 if (Value.getOpcode() != ISD::TargetConstantFP) {
4142 switch (CFP->getValueType(0)) {
4143 default: assert(0 && "Unknown FP type");
4144 case MVT::f80: // We don't do this for these yet.
4149 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) {
4150 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
4151 convertToAPInt().getZExtValue(), MVT::i32);
4152 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
4153 ST->getSrcValueOffset(), ST->isVolatile(),
4154 ST->getAlignment());
4158 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) {
4159 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
4160 getZExtValue(), MVT::i64);
4161 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
4162 ST->getSrcValueOffset(), ST->isVolatile(),
4163 ST->getAlignment());
4164 } else if (TLI.isTypeLegal(MVT::i32)) {
4165 // Many FP stores are not made apparent until after legalize, e.g. for
4166 // argument passing. Since this is so common, custom legalize the
4167 // 64-bit integer store into two 32-bit stores.
4168 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue();
4169 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
4170 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32);
4171 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
4173 int SVOffset = ST->getSrcValueOffset();
4174 unsigned Alignment = ST->getAlignment();
4175 bool isVolatile = ST->isVolatile();
4177 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(),
4178 ST->getSrcValueOffset(),
4179 isVolatile, ST->getAlignment());
4180 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4181 DAG.getConstant(4, Ptr.getValueType()));
4183 Alignment = MinAlign(Alignment, 4U);
4184 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(),
4185 SVOffset, isVolatile, Alignment);
4186 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1);
4194 // Walk up chain skipping non-aliasing memory nodes.
4195 SDOperand BetterChain = FindBetterChain(N, Chain);
4197 // If there is a better chain.
4198 if (Chain != BetterChain) {
4199 // Replace the chain to avoid dependency.
4200 SDOperand ReplStore;
4201 if (ST->isTruncatingStore()) {
4202 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
4203 ST->getSrcValue(), ST->getSrcValueOffset(), ST->getStoredVT(),
4204 ST->isVolatile(), ST->getAlignment());
4206 ReplStore = DAG.getStore(BetterChain, Value, Ptr,
4207 ST->getSrcValue(), ST->getSrcValueOffset(),
4208 ST->isVolatile(), ST->getAlignment());
4211 // Create token to keep both nodes around.
4213 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
4215 // Don't add users to work list.
4216 return CombineTo(N, Token, false);
4220 // Try transforming N to an indexed store.
4221 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4222 return SDOperand(N, 0);
4224 // FIXME: is there such a think as a truncating indexed store?
4225 if (ST->isTruncatingStore() && ST->getAddressingMode() == ISD::UNINDEXED &&
4226 MVT::isInteger(Value.getValueType())) {
4227 // See if we can simplify the input to this truncstore with knowledge that
4228 // only the low bits are being used. For example:
4229 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
4231 GetDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT()));
4232 AddToWorkList(Value.Val);
4234 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(),
4235 ST->getSrcValueOffset(), ST->getStoredVT(),
4236 ST->isVolatile(), ST->getAlignment());
4238 // Otherwise, see if we can simplify the operation with
4239 // SimplifyDemandedBits, which only works if the value has a single use.
4240 if (SimplifyDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT())))
4241 return SDOperand(N, 0);
4247 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
4248 SDOperand InVec = N->getOperand(0);
4249 SDOperand InVal = N->getOperand(1);
4250 SDOperand EltNo = N->getOperand(2);
4252 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
4253 // vector with the inserted element.
4254 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
4255 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
4256 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
4257 if (Elt < Ops.size())
4259 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
4260 &Ops[0], Ops.size());
4266 SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
4267 SDOperand InVec = N->getOperand(0);
4268 SDOperand EltNo = N->getOperand(1);
4270 // (vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr)
4271 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr)
4272 if (isa<ConstantSDNode>(EltNo)) {
4273 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
4274 bool NewLoad = false;
4276 MVT::ValueType VT = InVec.getValueType();
4277 MVT::ValueType EVT = MVT::getVectorElementType(VT);
4278 MVT::ValueType LVT = EVT;
4279 unsigned NumElts = MVT::getVectorNumElements(VT);
4280 if (InVec.getOpcode() == ISD::BIT_CONVERT) {
4281 MVT::ValueType BCVT = InVec.getOperand(0).getValueType();
4282 if (!MVT::isVector(BCVT) ||
4283 NumElts != MVT::getVectorNumElements(BCVT))
4285 InVec = InVec.getOperand(0);
4286 EVT = MVT::getVectorElementType(BCVT);
4289 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4290 InVec.getOperand(0).getValueType() == EVT &&
4291 ISD::isNormalLoad(InVec.getOperand(0).Val) &&
4292 InVec.getOperand(0).hasOneUse()) {
4293 LoadSDNode *LN0 = cast<LoadSDNode>(InVec.getOperand(0));
4294 unsigned Align = LN0->getAlignment();
4296 // Check the resultant load doesn't need a higher alignment than the
4298 unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
4299 getABITypeAlignment(MVT::getTypeForValueType(LVT));
4300 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align)
4305 return DAG.getLoad(LVT, LN0->getChain(), LN0->getBasePtr(),
4306 LN0->getSrcValue(), LN0->getSrcValueOffset(),
4307 LN0->isVolatile(), Align);
4315 SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
4316 unsigned NumInScalars = N->getNumOperands();
4317 MVT::ValueType VT = N->getValueType(0);
4318 unsigned NumElts = MVT::getVectorNumElements(VT);
4319 MVT::ValueType EltType = MVT::getVectorElementType(VT);
4321 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
4322 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
4323 // at most two distinct vectors, turn this into a shuffle node.
4324 SDOperand VecIn1, VecIn2;
4325 for (unsigned i = 0; i != NumInScalars; ++i) {
4326 // Ignore undef inputs.
4327 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4329 // If this input is something other than a EXTRACT_VECTOR_ELT with a
4330 // constant index, bail out.
4331 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4332 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
4333 VecIn1 = VecIn2 = SDOperand(0, 0);
4337 // If the input vector type disagrees with the result of the build_vector,
4338 // we can't make a shuffle.
4339 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
4340 if (ExtractedFromVec.getValueType() != VT) {
4341 VecIn1 = VecIn2 = SDOperand(0, 0);
4345 // Otherwise, remember this. We allow up to two distinct input vectors.
4346 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
4349 if (VecIn1.Val == 0) {
4350 VecIn1 = ExtractedFromVec;
4351 } else if (VecIn2.Val == 0) {
4352 VecIn2 = ExtractedFromVec;
4355 VecIn1 = VecIn2 = SDOperand(0, 0);
4360 // If everything is good, we can make a shuffle operation.
4362 SmallVector<SDOperand, 8> BuildVecIndices;
4363 for (unsigned i = 0; i != NumInScalars; ++i) {
4364 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
4365 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy()));
4369 SDOperand Extract = N->getOperand(i);
4371 // If extracting from the first vector, just use the index directly.
4372 if (Extract.getOperand(0) == VecIn1) {
4373 BuildVecIndices.push_back(Extract.getOperand(1));
4377 // Otherwise, use InIdx + VecSize
4378 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
4379 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars,
4380 TLI.getPointerTy()));
4383 // Add count and size info.
4384 MVT::ValueType BuildVecVT =
4385 MVT::getVectorType(TLI.getPointerTy(), NumElts);
4387 // Return the new VECTOR_SHUFFLE node.
4393 // Use an undef build_vector as input for the second operand.
4394 std::vector<SDOperand> UnOps(NumInScalars,
4395 DAG.getNode(ISD::UNDEF,
4397 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT,
4398 &UnOps[0], UnOps.size());
4399 AddToWorkList(Ops[1].Val);
4401 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT,
4402 &BuildVecIndices[0], BuildVecIndices.size());
4403 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3);
4409 SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
4410 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
4411 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
4412 // inputs come from at most two distinct vectors, turn this into a shuffle
4415 // If we only have one input vector, we don't need to do any concatenation.
4416 if (N->getNumOperands() == 1) {
4417 return N->getOperand(0);
4423 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
4424 SDOperand ShufMask = N->getOperand(2);
4425 unsigned NumElts = ShufMask.getNumOperands();
4427 // If the shuffle mask is an identity operation on the LHS, return the LHS.
4428 bool isIdentity = true;
4429 for (unsigned i = 0; i != NumElts; ++i) {
4430 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4431 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
4436 if (isIdentity) return N->getOperand(0);
4438 // If the shuffle mask is an identity operation on the RHS, return the RHS.
4440 for (unsigned i = 0; i != NumElts; ++i) {
4441 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4442 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
4447 if (isIdentity) return N->getOperand(1);
4449 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
4451 bool isUnary = true;
4452 bool isSplat = true;
4454 unsigned BaseIdx = 0;
4455 for (unsigned i = 0; i != NumElts; ++i)
4456 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
4457 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
4458 int V = (Idx < NumElts) ? 0 : 1;
4472 SDOperand N0 = N->getOperand(0);
4473 SDOperand N1 = N->getOperand(1);
4474 // Normalize unary shuffle so the RHS is undef.
4475 if (isUnary && VecNum == 1)
4478 // If it is a splat, check if the argument vector is a build_vector with
4479 // all scalar elements the same.
4483 // If this is a bit convert that changes the element type of the vector but
4484 // not the number of vector elements, look through it. Be careful not to
4485 // look though conversions that change things like v4f32 to v2f64.
4486 if (V->getOpcode() == ISD::BIT_CONVERT) {
4487 SDOperand ConvInput = V->getOperand(0);
4488 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts)
4492 if (V->getOpcode() == ISD::BUILD_VECTOR) {
4493 unsigned NumElems = V->getNumOperands();
4494 if (NumElems > BaseIdx) {
4496 bool AllSame = true;
4497 for (unsigned i = 0; i != NumElems; ++i) {
4498 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
4499 Base = V->getOperand(i);
4503 // Splat of <u, u, u, u>, return <u, u, u, u>
4506 for (unsigned i = 0; i != NumElems; ++i) {
4507 if (V->getOperand(i) != Base) {
4512 // Splat of <x, x, x, x>, return <x, x, x, x>
4519 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
4521 if (isUnary || N0 == N1) {
4522 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
4524 SmallVector<SDOperand, 8> MappedOps;
4525 for (unsigned i = 0; i != NumElts; ++i) {
4526 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
4527 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
4528 MappedOps.push_back(ShufMask.getOperand(i));
4531 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
4532 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
4535 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
4536 &MappedOps[0], MappedOps.size());
4537 AddToWorkList(ShufMask.Val);
4538 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
4540 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
4547 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
4548 /// an AND to a vector_shuffle with the destination vector and a zero vector.
4549 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
4550 /// vector_shuffle V, Zero, <0, 4, 2, 4>
4551 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
4552 SDOperand LHS = N->getOperand(0);
4553 SDOperand RHS = N->getOperand(1);
4554 if (N->getOpcode() == ISD::AND) {
4555 if (RHS.getOpcode() == ISD::BIT_CONVERT)
4556 RHS = RHS.getOperand(0);
4557 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
4558 std::vector<SDOperand> IdxOps;
4559 unsigned NumOps = RHS.getNumOperands();
4560 unsigned NumElts = NumOps;
4561 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType());
4562 for (unsigned i = 0; i != NumElts; ++i) {
4563 SDOperand Elt = RHS.getOperand(i);
4564 if (!isa<ConstantSDNode>(Elt))
4566 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
4567 IdxOps.push_back(DAG.getConstant(i, EVT));
4568 else if (cast<ConstantSDNode>(Elt)->isNullValue())
4569 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
4574 // Let's see if the target supports this vector_shuffle.
4575 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
4578 // Return the new VECTOR_SHUFFLE node.
4579 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts);
4580 std::vector<SDOperand> Ops;
4581 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS);
4583 AddToWorkList(LHS.Val);
4584 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
4585 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
4586 &ZeroOps[0], ZeroOps.size()));
4587 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
4588 &IdxOps[0], IdxOps.size()));
4589 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT,
4590 &Ops[0], Ops.size());
4591 if (VT != LHS.getValueType()) {
4592 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result);
4600 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
4601 SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) {
4602 // After legalize, the target may be depending on adds and other
4603 // binary ops to provide legal ways to construct constants or other
4604 // things. Simplifying them may result in a loss of legality.
4605 if (AfterLegalize) return SDOperand();
4607 MVT::ValueType VT = N->getValueType(0);
4608 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!");
4610 MVT::ValueType EltType = MVT::getVectorElementType(VT);
4611 SDOperand LHS = N->getOperand(0);
4612 SDOperand RHS = N->getOperand(1);
4613 SDOperand Shuffle = XformToShuffleWithZero(N);
4614 if (Shuffle.Val) return Shuffle;
4616 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
4618 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
4619 RHS.getOpcode() == ISD::BUILD_VECTOR) {
4620 SmallVector<SDOperand, 8> Ops;
4621 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
4622 SDOperand LHSOp = LHS.getOperand(i);
4623 SDOperand RHSOp = RHS.getOperand(i);
4624 // If these two elements can't be folded, bail out.
4625 if ((LHSOp.getOpcode() != ISD::UNDEF &&
4626 LHSOp.getOpcode() != ISD::Constant &&
4627 LHSOp.getOpcode() != ISD::ConstantFP) ||
4628 (RHSOp.getOpcode() != ISD::UNDEF &&
4629 RHSOp.getOpcode() != ISD::Constant &&
4630 RHSOp.getOpcode() != ISD::ConstantFP))
4632 // Can't fold divide by zero.
4633 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
4634 N->getOpcode() == ISD::FDIV) {
4635 if ((RHSOp.getOpcode() == ISD::Constant &&
4636 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
4637 (RHSOp.getOpcode() == ISD::ConstantFP &&
4638 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero()))
4641 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp));
4642 AddToWorkList(Ops.back().Val);
4643 assert((Ops.back().getOpcode() == ISD::UNDEF ||
4644 Ops.back().getOpcode() == ISD::Constant ||
4645 Ops.back().getOpcode() == ISD::ConstantFP) &&
4646 "Scalar binop didn't fold!");
4649 if (Ops.size() == LHS.getNumOperands()) {
4650 MVT::ValueType VT = LHS.getValueType();
4651 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
4658 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
4659 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
4661 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
4662 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4663 // If we got a simplified select_cc node back from SimplifySelectCC, then
4664 // break it down into a new SETCC node, and a new SELECT node, and then return
4665 // the SELECT node, since we were called with a SELECT node.
4667 // Check to see if we got a select_cc back (to turn into setcc/select).
4668 // Otherwise, just return whatever node we got back, like fabs.
4669 if (SCC.getOpcode() == ISD::SELECT_CC) {
4670 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
4671 SCC.getOperand(0), SCC.getOperand(1),
4673 AddToWorkList(SETCC.Val);
4674 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
4675 SCC.getOperand(3), SETCC);
4682 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
4683 /// are the two values being selected between, see if we can simplify the
4684 /// select. Callers of this should assume that TheSelect is deleted if this
4685 /// returns true. As such, they should return the appropriate thing (e.g. the
4686 /// node) back to the top-level of the DAG combiner loop to avoid it being
4689 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
4692 // If this is a select from two identical things, try to pull the operation
4693 // through the select.
4694 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
4695 // If this is a load and the token chain is identical, replace the select
4696 // of two loads with a load through a select of the address to load from.
4697 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
4698 // constants have been dropped into the constant pool.
4699 if (LHS.getOpcode() == ISD::LOAD &&
4700 // Token chains must be identical.
4701 LHS.getOperand(0) == RHS.getOperand(0)) {
4702 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
4703 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
4705 // If this is an EXTLOAD, the VT's must match.
4706 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
4707 // FIXME: this conflates two src values, discarding one. This is not
4708 // the right thing to do, but nothing uses srcvalues now. When they do,
4709 // turn SrcValue into a list of locations.
4711 if (TheSelect->getOpcode() == ISD::SELECT) {
4712 // Check that the condition doesn't reach either load. If so, folding
4713 // this will induce a cycle into the DAG.
4714 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4715 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) {
4716 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
4717 TheSelect->getOperand(0), LLD->getBasePtr(),
4721 // Check that the condition doesn't reach either load. If so, folding
4722 // this will induce a cycle into the DAG.
4723 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4724 !RLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4725 !LLD->isPredecessor(TheSelect->getOperand(1).Val) &&
4726 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) {
4727 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
4728 TheSelect->getOperand(0),
4729 TheSelect->getOperand(1),
4730 LLD->getBasePtr(), RLD->getBasePtr(),
4731 TheSelect->getOperand(4));
4737 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
4738 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
4739 Addr,LLD->getSrcValue(),
4740 LLD->getSrcValueOffset(),
4742 LLD->getAlignment());
4744 Load = DAG.getExtLoad(LLD->getExtensionType(),
4745 TheSelect->getValueType(0),
4746 LLD->getChain(), Addr, LLD->getSrcValue(),
4747 LLD->getSrcValueOffset(),
4750 LLD->getAlignment());
4752 // Users of the select now use the result of the load.
4753 CombineTo(TheSelect, Load);
4755 // Users of the old loads now use the new load's chain. We know the
4756 // old-load value is dead now.
4757 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
4758 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
4768 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
4769 SDOperand N2, SDOperand N3,
4770 ISD::CondCode CC, bool NotExtCompare) {
4772 MVT::ValueType VT = N2.getValueType();
4773 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
4774 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
4775 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
4777 // Determine if the condition we're dealing with is constant
4778 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
4779 if (SCC.Val) AddToWorkList(SCC.Val);
4780 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
4782 // fold select_cc true, x, y -> x
4783 if (SCCC && SCCC->getValue())
4785 // fold select_cc false, x, y -> y
4786 if (SCCC && SCCC->getValue() == 0)
4789 // Check to see if we can simplify the select into an fabs node
4790 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
4791 // Allow either -0.0 or 0.0
4792 if (CFP->getValueAPF().isZero()) {
4793 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
4794 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
4795 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
4796 N2 == N3.getOperand(0))
4797 return DAG.getNode(ISD::FABS, VT, N0);
4799 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
4800 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
4801 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
4802 N2.getOperand(0) == N3)
4803 return DAG.getNode(ISD::FABS, VT, N3);
4807 // Check to see if we can perform the "gzip trick", transforming
4808 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
4809 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
4810 MVT::isInteger(N0.getValueType()) &&
4811 MVT::isInteger(N2.getValueType()) &&
4812 (N1C->isNullValue() || // (a < 0) ? b : 0
4813 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
4814 MVT::ValueType XType = N0.getValueType();
4815 MVT::ValueType AType = N2.getValueType();
4816 if (XType >= AType) {
4817 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
4818 // single-bit constant.
4819 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
4820 unsigned ShCtV = Log2_64(N2C->getValue());
4821 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
4822 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
4823 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
4824 AddToWorkList(Shift.Val);
4825 if (XType > AType) {
4826 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
4827 AddToWorkList(Shift.Val);
4829 return DAG.getNode(ISD::AND, AType, Shift, N2);
4831 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4832 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4833 TLI.getShiftAmountTy()));
4834 AddToWorkList(Shift.Val);
4835 if (XType > AType) {
4836 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
4837 AddToWorkList(Shift.Val);
4839 return DAG.getNode(ISD::AND, AType, Shift, N2);
4843 // fold select C, 16, 0 -> shl C, 4
4844 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
4845 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
4847 // If the caller doesn't want us to simplify this into a zext of a compare,
4849 if (NotExtCompare && N2C->getValue() == 1)
4852 // Get a SetCC of the condition
4853 // FIXME: Should probably make sure that setcc is legal if we ever have a
4854 // target where it isn't.
4855 SDOperand Temp, SCC;
4856 // cast from setcc result type to select result type
4857 if (AfterLegalize) {
4858 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4859 if (N2.getValueType() < SCC.getValueType())
4860 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
4862 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
4864 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
4865 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
4867 AddToWorkList(SCC.Val);
4868 AddToWorkList(Temp.Val);
4870 if (N2C->getValue() == 1)
4872 // shl setcc result by log2 n2c
4873 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
4874 DAG.getConstant(Log2_64(N2C->getValue()),
4875 TLI.getShiftAmountTy()));
4878 // Check to see if this is the equivalent of setcc
4879 // FIXME: Turn all of these into setcc if setcc if setcc is legal
4880 // otherwise, go ahead with the folds.
4881 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
4882 MVT::ValueType XType = N0.getValueType();
4883 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
4884 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4885 if (Res.getValueType() != VT)
4886 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
4890 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
4891 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
4892 TLI.isOperationLegal(ISD::CTLZ, XType)) {
4893 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
4894 return DAG.getNode(ISD::SRL, XType, Ctlz,
4895 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
4896 TLI.getShiftAmountTy()));
4898 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
4899 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
4900 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
4902 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
4903 DAG.getConstant(~0ULL, XType));
4904 return DAG.getNode(ISD::SRL, XType,
4905 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
4906 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4907 TLI.getShiftAmountTy()));
4909 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
4910 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
4911 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
4912 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4913 TLI.getShiftAmountTy()));
4914 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
4918 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
4919 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4920 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
4921 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
4922 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) {
4923 MVT::ValueType XType = N0.getValueType();
4924 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4925 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4926 TLI.getShiftAmountTy()));
4927 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
4928 AddToWorkList(Shift.Val);
4929 AddToWorkList(Add.Val);
4930 return DAG.getNode(ISD::XOR, XType, Add, Shift);
4932 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
4933 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4934 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
4935 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
4936 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
4937 MVT::ValueType XType = N0.getValueType();
4938 if (SubC->isNullValue() && MVT::isInteger(XType)) {
4939 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4940 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4941 TLI.getShiftAmountTy()));
4942 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
4943 AddToWorkList(Shift.Val);
4944 AddToWorkList(Add.Val);
4945 return DAG.getNode(ISD::XOR, XType, Add, Shift);
4953 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
4954 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
4955 SDOperand N1, ISD::CondCode Cond,
4956 bool foldBooleans) {
4957 TargetLowering::DAGCombinerInfo
4958 DagCombineInfo(DAG, !AfterLegalize, false, this);
4959 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo);
4962 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
4963 /// return a DAG expression to select that will generate the same value by
4964 /// multiplying by a magic number. See:
4965 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4966 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
4967 std::vector<SDNode*> Built;
4968 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
4970 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4976 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
4977 /// return a DAG expression to select that will generate the same value by
4978 /// multiplying by a magic number. See:
4979 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4980 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
4981 std::vector<SDNode*> Built;
4982 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
4984 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4990 /// FindBaseOffset - Return true if base is known not to alias with anything
4991 /// but itself. Provides base object and offset as results.
4992 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
4993 // Assume it is a primitive operation.
4994 Base = Ptr; Offset = 0;
4996 // If it's an adding a simple constant then integrate the offset.
4997 if (Base.getOpcode() == ISD::ADD) {
4998 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
4999 Base = Base.getOperand(0);
5000 Offset += C->getValue();
5004 // If it's any of the following then it can't alias with anything but itself.
5005 return isa<FrameIndexSDNode>(Base) ||
5006 isa<ConstantPoolSDNode>(Base) ||
5007 isa<GlobalAddressSDNode>(Base);
5010 /// isAlias - Return true if there is any possibility that the two addresses
5012 bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1,
5013 const Value *SrcValue1, int SrcValueOffset1,
5014 SDOperand Ptr2, int64_t Size2,
5015 const Value *SrcValue2, int SrcValueOffset2)
5017 // If they are the same then they must be aliases.
5018 if (Ptr1 == Ptr2) return true;
5020 // Gather base node and offset information.
5021 SDOperand Base1, Base2;
5022 int64_t Offset1, Offset2;
5023 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
5024 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
5026 // If they have a same base address then...
5027 if (Base1 == Base2) {
5028 // Check to see if the addresses overlap.
5029 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
5032 // If we know both bases then they can't alias.
5033 if (KnownBase1 && KnownBase2) return false;
5035 if (CombinerGlobalAA) {
5036 // Use alias analysis information.
5037 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
5038 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
5039 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
5040 AliasAnalysis::AliasResult AAResult =
5041 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
5042 if (AAResult == AliasAnalysis::NoAlias)
5046 // Otherwise we have to assume they alias.
5050 /// FindAliasInfo - Extracts the relevant alias information from the memory
5051 /// node. Returns true if the operand was a load.
5052 bool DAGCombiner::FindAliasInfo(SDNode *N,
5053 SDOperand &Ptr, int64_t &Size,
5054 const Value *&SrcValue, int &SrcValueOffset) {
5055 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5056 Ptr = LD->getBasePtr();
5057 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3;
5058 SrcValue = LD->getSrcValue();
5059 SrcValueOffset = LD->getSrcValueOffset();
5061 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5062 Ptr = ST->getBasePtr();
5063 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3;
5064 SrcValue = ST->getSrcValue();
5065 SrcValueOffset = ST->getSrcValueOffset();
5067 assert(0 && "FindAliasInfo expected a memory operand");
5073 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
5074 /// looking for aliasing nodes and adding them to the Aliases vector.
5075 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
5076 SmallVector<SDOperand, 8> &Aliases) {
5077 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
5078 std::set<SDNode *> Visited; // Visited node set.
5080 // Get alias information for node.
5083 const Value *SrcValue;
5085 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
5088 Chains.push_back(OriginalChain);
5090 // Look at each chain and determine if it is an alias. If so, add it to the
5091 // aliases list. If not, then continue up the chain looking for the next
5093 while (!Chains.empty()) {
5094 SDOperand Chain = Chains.back();
5097 // Don't bother if we've been before.
5098 if (Visited.find(Chain.Val) != Visited.end()) continue;
5099 Visited.insert(Chain.Val);
5101 switch (Chain.getOpcode()) {
5102 case ISD::EntryToken:
5103 // Entry token is ideal chain operand, but handled in FindBetterChain.
5108 // Get alias information for Chain.
5111 const Value *OpSrcValue;
5112 int OpSrcValueOffset;
5113 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
5114 OpSrcValue, OpSrcValueOffset);
5116 // If chain is alias then stop here.
5117 if (!(IsLoad && IsOpLoad) &&
5118 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
5119 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
5120 Aliases.push_back(Chain);
5122 // Look further up the chain.
5123 Chains.push_back(Chain.getOperand(0));
5124 // Clean up old chain.
5125 AddToWorkList(Chain.Val);
5130 case ISD::TokenFactor:
5131 // We have to check each of the operands of the token factor, so we queue
5132 // then up. Adding the operands to the queue (stack) in reverse order
5133 // maintains the original order and increases the likelihood that getNode
5134 // will find a matching token factor (CSE.)
5135 for (unsigned n = Chain.getNumOperands(); n;)
5136 Chains.push_back(Chain.getOperand(--n));
5137 // Eliminate the token factor if we can.
5138 AddToWorkList(Chain.Val);
5142 // For all other instructions we will just have to take what we can get.
5143 Aliases.push_back(Chain);
5149 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
5150 /// for a better chain (aliasing node.)
5151 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
5152 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
5154 // Accumulate all the aliases to this node.
5155 GatherAllAliases(N, OldChain, Aliases);
5157 if (Aliases.size() == 0) {
5158 // If no operands then chain to entry token.
5159 return DAG.getEntryNode();
5160 } else if (Aliases.size() == 1) {
5161 // If a single operand then chain to it. We don't need to revisit it.
5165 // Construct a custom tailored token factor.
5166 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5167 &Aliases[0], Aliases.size());
5169 // Make sure the old chain gets cleaned up.
5170 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
5175 // SelectionDAG::Combine - This is the entry point for the file.
5177 void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
5178 if (!RunningAfterLegalize && ViewDAGCombine1)
5180 if (RunningAfterLegalize && ViewDAGCombine2)
5182 /// run - This is the main entry point to this class.
5184 DAGCombiner(*this, AA).Run(RunningAfterLegalize);