1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "dagcombine"
16 #include "llvm/CodeGen/SelectionDAG.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Target/TargetData.h"
21 #include "llvm/Target/TargetFrameInfo.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/SmallPtrSet.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/MathExtras.h"
35 STATISTIC(NodesCombined , "Number of dag nodes combined");
36 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
37 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
41 CombinerAA("combiner-alias-analysis", cl::Hidden,
42 cl::desc("Turn on alias analysis during testing"));
45 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
46 cl::desc("Include global information in alias analysis"));
48 //------------------------------ DAGCombiner ---------------------------------//
50 class VISIBILITY_HIDDEN DAGCombiner {
52 const TargetLowering &TLI;
58 // Worklist of all of the nodes that need to be simplified.
59 std::vector<SDNode*> WorkList;
61 // AA - Used for DAG load/store alias analysis.
64 /// AddUsersToWorkList - When an instruction is simplified, add all users of
65 /// the instruction to the work lists because they might get more simplified
68 void AddUsersToWorkList(SDNode *N) {
69 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
74 /// visit - call the node-specific routine that knows how to fold each
75 /// particular type of node.
76 SDValue visit(SDNode *N);
79 /// AddToWorkList - Add to the work list making sure it's instance is at the
80 /// the back (next to be processed.)
81 void AddToWorkList(SDNode *N) {
82 removeFromWorkList(N);
83 WorkList.push_back(N);
86 /// removeFromWorkList - remove all instances of N from the worklist.
88 void removeFromWorkList(SDNode *N) {
89 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
93 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
96 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
97 return CombineTo(N, &Res, 1, AddTo);
100 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
102 SDValue To[] = { Res0, Res1 };
103 return CombineTo(N, To, 2, AddTo);
106 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
110 /// SimplifyDemandedBits - Check the specified integer node value to see if
111 /// it can be simplified or if things it uses can be simplified by bit
112 /// propagation. If so, return true.
113 bool SimplifyDemandedBits(SDValue Op) {
114 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits());
115 return SimplifyDemandedBits(Op, Demanded);
118 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
120 bool CombineToPreIndexedLoadStore(SDNode *N);
121 bool CombineToPostIndexedLoadStore(SDNode *N);
124 /// combine - call the node-specific routine that knows how to fold each
125 /// particular type of node. If that doesn't do anything, try the
126 /// target-specific DAG combines.
127 SDValue combine(SDNode *N);
129 // Visitation implementation - Implement dag node combining for different
130 // node types. The semantics are as follows:
132 // SDValue.getNode() == 0 - No change was made
133 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
134 // otherwise - N should be replaced by the returned Operand.
136 SDValue visitTokenFactor(SDNode *N);
137 SDValue visitMERGE_VALUES(SDNode *N);
138 SDValue visitADD(SDNode *N);
139 SDValue visitSUB(SDNode *N);
140 SDValue visitADDC(SDNode *N);
141 SDValue visitADDE(SDNode *N);
142 SDValue visitMUL(SDNode *N);
143 SDValue visitSDIV(SDNode *N);
144 SDValue visitUDIV(SDNode *N);
145 SDValue visitSREM(SDNode *N);
146 SDValue visitUREM(SDNode *N);
147 SDValue visitMULHU(SDNode *N);
148 SDValue visitMULHS(SDNode *N);
149 SDValue visitSMUL_LOHI(SDNode *N);
150 SDValue visitUMUL_LOHI(SDNode *N);
151 SDValue visitSDIVREM(SDNode *N);
152 SDValue visitUDIVREM(SDNode *N);
153 SDValue visitAND(SDNode *N);
154 SDValue visitOR(SDNode *N);
155 SDValue visitXOR(SDNode *N);
156 SDValue SimplifyVBinOp(SDNode *N);
157 SDValue visitSHL(SDNode *N);
158 SDValue visitSRA(SDNode *N);
159 SDValue visitSRL(SDNode *N);
160 SDValue visitCTLZ(SDNode *N);
161 SDValue visitCTTZ(SDNode *N);
162 SDValue visitCTPOP(SDNode *N);
163 SDValue visitSELECT(SDNode *N);
164 SDValue visitSELECT_CC(SDNode *N);
165 SDValue visitSETCC(SDNode *N);
166 SDValue visitSIGN_EXTEND(SDNode *N);
167 SDValue visitZERO_EXTEND(SDNode *N);
168 SDValue visitANY_EXTEND(SDNode *N);
169 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
170 SDValue visitTRUNCATE(SDNode *N);
171 SDValue visitBIT_CONVERT(SDNode *N);
172 SDValue visitBUILD_PAIR(SDNode *N);
173 SDValue visitFADD(SDNode *N);
174 SDValue visitFSUB(SDNode *N);
175 SDValue visitFMUL(SDNode *N);
176 SDValue visitFDIV(SDNode *N);
177 SDValue visitFREM(SDNode *N);
178 SDValue visitFCOPYSIGN(SDNode *N);
179 SDValue visitSINT_TO_FP(SDNode *N);
180 SDValue visitUINT_TO_FP(SDNode *N);
181 SDValue visitFP_TO_SINT(SDNode *N);
182 SDValue visitFP_TO_UINT(SDNode *N);
183 SDValue visitFP_ROUND(SDNode *N);
184 SDValue visitFP_ROUND_INREG(SDNode *N);
185 SDValue visitFP_EXTEND(SDNode *N);
186 SDValue visitFNEG(SDNode *N);
187 SDValue visitFABS(SDNode *N);
188 SDValue visitBRCOND(SDNode *N);
189 SDValue visitBR_CC(SDNode *N);
190 SDValue visitLOAD(SDNode *N);
191 SDValue visitSTORE(SDNode *N);
192 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
193 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
194 SDValue visitBUILD_VECTOR(SDNode *N);
195 SDValue visitCONCAT_VECTORS(SDNode *N);
196 SDValue visitVECTOR_SHUFFLE(SDNode *N);
198 SDValue XformToShuffleWithZero(SDNode *N);
199 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
201 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
203 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
204 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
205 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
206 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
207 SDValue N3, ISD::CondCode CC,
208 bool NotExtCompare = false);
209 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
210 DebugLoc DL, bool foldBooleans = true);
211 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
213 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT);
214 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT);
215 SDValue BuildSDIV(SDNode *N);
216 SDValue BuildUDIV(SDNode *N);
217 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
218 SDValue ReduceLoadWidth(SDNode *N);
220 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
222 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
223 /// looking for aliasing nodes and adding them to the Aliases vector.
224 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
225 SmallVector<SDValue, 8> &Aliases);
227 /// isAlias - Return true if there is any possibility that the two addresses
229 bool isAlias(SDValue Ptr1, int64_t Size1,
230 const Value *SrcValue1, int SrcValueOffset1,
231 SDValue Ptr2, int64_t Size2,
232 const Value *SrcValue2, int SrcValueOffset2) const;
234 /// FindAliasInfo - Extracts the relevant alias information from the memory
235 /// node. Returns true if the operand was a load.
236 bool FindAliasInfo(SDNode *N,
237 SDValue &Ptr, int64_t &Size,
238 const Value *&SrcValue, int &SrcValueOffset) const;
240 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
241 /// looking for a better chain (aliasing node.)
242 SDValue FindBetterChain(SDNode *N, SDValue Chain);
244 /// getShiftAmountTy - Returns a type large enough to hold any valid
245 /// shift amount - before type legalization these can be huge.
246 MVT getShiftAmountTy() {
247 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy();
251 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast)
253 TLI(D.getTargetLoweringInfo()),
255 LegalOperations(false),
260 /// Run - runs the dag combiner on all nodes in the work list
261 void Run(CombineLevel AtLevel);
267 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
268 /// nodes from the worklist.
269 class VISIBILITY_HIDDEN WorkListRemover :
270 public SelectionDAG::DAGUpdateListener {
273 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
275 virtual void NodeDeleted(SDNode *N, SDNode *E) {
276 DC.removeFromWorkList(N);
279 virtual void NodeUpdated(SDNode *N) {
285 //===----------------------------------------------------------------------===//
286 // TargetLowering::DAGCombinerInfo implementation
287 //===----------------------------------------------------------------------===//
289 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
290 ((DAGCombiner*)DC)->AddToWorkList(N);
293 SDValue TargetLowering::DAGCombinerInfo::
294 CombineTo(SDNode *N, const std::vector<SDValue> &To) {
295 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
298 SDValue TargetLowering::DAGCombinerInfo::
299 CombineTo(SDNode *N, SDValue Res) {
300 return ((DAGCombiner*)DC)->CombineTo(N, Res);
304 SDValue TargetLowering::DAGCombinerInfo::
305 CombineTo(SDNode *N, SDValue Res0, SDValue Res1) {
306 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
309 void TargetLowering::DAGCombinerInfo::
310 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
311 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
314 //===----------------------------------------------------------------------===//
316 //===----------------------------------------------------------------------===//
318 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
319 /// specified expression for the same cost as the expression itself, or 2 if we
320 /// can compute the negated form more cheaply than the expression itself.
321 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
322 unsigned Depth = 0) {
323 // No compile time optimizations on this type.
324 if (Op.getValueType() == MVT::ppcf128)
327 // fneg is removable even if it has multiple uses.
328 if (Op.getOpcode() == ISD::FNEG) return 2;
330 // Don't allow anything with multiple uses.
331 if (!Op.hasOneUse()) return 0;
333 // Don't recurse exponentially.
334 if (Depth > 6) return 0;
336 switch (Op.getOpcode()) {
337 default: return false;
338 case ISD::ConstantFP:
339 // Don't invert constant FP values after legalize. The negated constant
340 // isn't necessarily legal.
341 return LegalOperations ? 0 : 1;
343 // FIXME: determine better conditions for this xform.
344 if (!UnsafeFPMath) return 0;
346 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
347 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
349 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
350 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
352 // We can't turn -(A-B) into B-A when we honor signed zeros.
353 if (!UnsafeFPMath) return 0;
355 // fold (fneg (fsub A, B)) -> (fsub B, A)
360 if (HonorSignDependentRoundingFPMath()) return 0;
362 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
363 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
366 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
371 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1);
375 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
376 /// returns the newly negated expression.
377 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
378 bool LegalOperations, unsigned Depth = 0) {
379 // fneg is removable even if it has multiple uses.
380 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
382 // Don't allow anything with multiple uses.
383 assert(Op.hasOneUse() && "Unknown reuse!");
385 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
386 switch (Op.getOpcode()) {
387 default: assert(0 && "Unknown code");
388 case ISD::ConstantFP: {
389 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
391 return DAG.getConstantFP(V, Op.getValueType());
394 // FIXME: determine better conditions for this xform.
395 assert(UnsafeFPMath);
397 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
398 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
399 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
400 GetNegatedExpression(Op.getOperand(0), DAG,
401 LegalOperations, Depth+1),
403 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
404 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
405 GetNegatedExpression(Op.getOperand(1), DAG,
406 LegalOperations, Depth+1),
409 // We can't turn -(A-B) into B-A when we honor signed zeros.
410 assert(UnsafeFPMath);
412 // fold (fneg (fsub 0, B)) -> B
413 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
414 if (N0CFP->getValueAPF().isZero())
415 return Op.getOperand(1);
417 // fold (fneg (fsub A, B)) -> (fsub B, A)
418 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
419 Op.getOperand(1), Op.getOperand(0));
423 assert(!HonorSignDependentRoundingFPMath());
425 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
426 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
427 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
428 GetNegatedExpression(Op.getOperand(0), DAG,
429 LegalOperations, Depth+1),
432 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
433 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
435 GetNegatedExpression(Op.getOperand(1), DAG,
436 LegalOperations, Depth+1));
440 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
441 GetNegatedExpression(Op.getOperand(0), DAG,
442 LegalOperations, Depth+1));
444 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
445 GetNegatedExpression(Op.getOperand(0), DAG,
446 LegalOperations, Depth+1),
452 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
453 // that selects between the values 1 and 0, making it equivalent to a setcc.
454 // Also, set the incoming LHS, RHS, and CC references to the appropriate
455 // nodes based on the type of node we are checking. This simplifies life a
456 // bit for the callers.
457 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
459 if (N.getOpcode() == ISD::SETCC) {
460 LHS = N.getOperand(0);
461 RHS = N.getOperand(1);
462 CC = N.getOperand(2);
465 if (N.getOpcode() == ISD::SELECT_CC &&
466 N.getOperand(2).getOpcode() == ISD::Constant &&
467 N.getOperand(3).getOpcode() == ISD::Constant &&
468 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
469 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
470 LHS = N.getOperand(0);
471 RHS = N.getOperand(1);
472 CC = N.getOperand(4);
478 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
479 // one use. If this is true, it allows the users to invert the operation for
480 // free when it is profitable to do so.
481 static bool isOneUseSetCC(SDValue N) {
483 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
488 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
489 SDValue N0, SDValue N1) {
490 MVT VT = N0.getValueType();
491 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
492 if (isa<ConstantSDNode>(N1)) {
493 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
495 DAG.FoldConstantArithmetic(Opc, VT,
496 cast<ConstantSDNode>(N0.getOperand(1)),
497 cast<ConstantSDNode>(N1));
498 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
499 } else if (N0.hasOneUse()) {
500 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
501 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
502 N0.getOperand(0), N1);
503 AddToWorkList(OpNode.getNode());
504 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
508 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
509 if (isa<ConstantSDNode>(N0)) {
510 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
512 DAG.FoldConstantArithmetic(Opc, VT,
513 cast<ConstantSDNode>(N1.getOperand(1)),
514 cast<ConstantSDNode>(N0));
515 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
516 } else if (N1.hasOneUse()) {
517 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
518 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
519 N1.getOperand(0), N0);
520 AddToWorkList(OpNode.getNode());
521 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
528 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
530 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
532 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
533 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG));
534 DOUT << " and " << NumTo-1 << " other values\n";
535 DEBUG(for (unsigned i = 0, e = NumTo; i != e; ++i)
536 assert(N->getValueType(i) == To[i].getValueType() &&
537 "Cannot combine value to value of different type!"));
538 WorkListRemover DeadNodes(*this);
539 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
542 // Push the new nodes and any users onto the worklist
543 for (unsigned i = 0, e = NumTo; i != e; ++i) {
544 AddToWorkList(To[i].getNode());
545 AddUsersToWorkList(To[i].getNode());
549 // Finally, if the node is now dead, remove it from the graph. The node
550 // may not be dead if the replacement process recursively simplified to
551 // something else needing this node.
552 if (N->use_empty()) {
553 // Nodes can be reintroduced into the worklist. Make sure we do not
554 // process a node that has been replaced.
555 removeFromWorkList(N);
557 // Finally, since the node is now dead, remove it from the graph.
560 return SDValue(N, 0);
564 DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &
566 // Replace all uses. If any nodes become isomorphic to other nodes and
567 // are deleted, make sure to remove them from our worklist.
568 WorkListRemover DeadNodes(*this);
569 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
571 // Push the new node and any (possibly new) users onto the worklist.
572 AddToWorkList(TLO.New.getNode());
573 AddUsersToWorkList(TLO.New.getNode());
575 // Finally, if the node is now dead, remove it from the graph. The node
576 // may not be dead if the replacement process recursively simplified to
577 // something else needing this node.
578 if (TLO.Old.getNode()->use_empty()) {
579 removeFromWorkList(TLO.Old.getNode());
581 // If the operands of this node are only used by the node, they will now
582 // be dead. Make sure to visit them first to delete dead nodes early.
583 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
584 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
585 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
587 DAG.DeleteNode(TLO.Old.getNode());
591 /// SimplifyDemandedBits - Check the specified integer node value to see if
592 /// it can be simplified or if things it uses can be simplified by bit
593 /// propagation. If so, return true.
594 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
595 TargetLowering::TargetLoweringOpt TLO(DAG);
596 APInt KnownZero, KnownOne;
597 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
601 AddToWorkList(Op.getNode());
603 // Replace the old value with the new one.
605 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG));
606 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG));
609 CommitTargetLoweringOpt(TLO);
613 //===----------------------------------------------------------------------===//
614 // Main DAG Combiner implementation
615 //===----------------------------------------------------------------------===//
617 void DAGCombiner::Run(CombineLevel AtLevel) {
618 // set the instance variables, so that the various visit routines may use it.
620 LegalOperations = Level >= NoIllegalOperations;
621 LegalTypes = Level >= NoIllegalTypes;
623 // Add all the dag nodes to the worklist.
624 WorkList.reserve(DAG.allnodes_size());
625 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
626 E = DAG.allnodes_end(); I != E; ++I)
627 WorkList.push_back(I);
629 // Create a dummy node (which is not added to allnodes), that adds a reference
630 // to the root node, preventing it from being deleted, and tracking any
631 // changes of the root.
632 HandleSDNode Dummy(DAG.getRoot());
634 // The root of the dag may dangle to deleted nodes until the dag combiner is
635 // done. Set it to null to avoid confusion.
636 DAG.setRoot(SDValue());
638 // while the worklist isn't empty, inspect the node on the end of it and
639 // try and combine it.
640 while (!WorkList.empty()) {
641 SDNode *N = WorkList.back();
644 // If N has no uses, it is dead. Make sure to revisit all N's operands once
645 // N is deleted from the DAG, since they too may now be dead or may have a
646 // reduced number of uses, allowing other xforms.
647 if (N->use_empty() && N != &Dummy) {
648 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
649 AddToWorkList(N->getOperand(i).getNode());
655 SDValue RV = combine(N);
657 if (RV.getNode() == 0)
662 // If we get back the same node we passed in, rather than a new node or
663 // zero, we know that the node must have defined multiple values and
664 // CombineTo was used. Since CombineTo takes care of the worklist
665 // mechanics for us, we have no work to do in this case.
666 if (RV.getNode() == N)
669 assert(N->getOpcode() != ISD::DELETED_NODE &&
670 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
671 "Node was deleted but visit returned new node!");
673 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
674 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG));
676 WorkListRemover DeadNodes(*this);
677 if (N->getNumValues() == RV.getNode()->getNumValues())
678 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
680 assert(N->getValueType(0) == RV.getValueType() &&
681 N->getNumValues() == 1 && "Type mismatch");
683 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
686 // Push the new node and any users onto the worklist
687 AddToWorkList(RV.getNode());
688 AddUsersToWorkList(RV.getNode());
690 // Add any uses of the old node to the worklist in case this node is the
691 // last one that uses them. They may become dead after this node is
693 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
694 AddToWorkList(N->getOperand(i).getNode());
696 // Finally, if the node is now dead, remove it from the graph. The node
697 // may not be dead if the replacement process recursively simplified to
698 // something else needing this node.
699 if (N->use_empty()) {
700 // Nodes can be reintroduced into the worklist. Make sure we do not
701 // process a node that has been replaced.
702 removeFromWorkList(N);
704 // Finally, since the node is now dead, remove it from the graph.
709 // If the root changed (e.g. it was a dead load, update the root).
710 DAG.setRoot(Dummy.getValue());
713 SDValue DAGCombiner::visit(SDNode *N) {
714 switch(N->getOpcode()) {
716 case ISD::TokenFactor: return visitTokenFactor(N);
717 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
718 case ISD::ADD: return visitADD(N);
719 case ISD::SUB: return visitSUB(N);
720 case ISD::ADDC: return visitADDC(N);
721 case ISD::ADDE: return visitADDE(N);
722 case ISD::MUL: return visitMUL(N);
723 case ISD::SDIV: return visitSDIV(N);
724 case ISD::UDIV: return visitUDIV(N);
725 case ISD::SREM: return visitSREM(N);
726 case ISD::UREM: return visitUREM(N);
727 case ISD::MULHU: return visitMULHU(N);
728 case ISD::MULHS: return visitMULHS(N);
729 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
730 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
731 case ISD::SDIVREM: return visitSDIVREM(N);
732 case ISD::UDIVREM: return visitUDIVREM(N);
733 case ISD::AND: return visitAND(N);
734 case ISD::OR: return visitOR(N);
735 case ISD::XOR: return visitXOR(N);
736 case ISD::SHL: return visitSHL(N);
737 case ISD::SRA: return visitSRA(N);
738 case ISD::SRL: return visitSRL(N);
739 case ISD::CTLZ: return visitCTLZ(N);
740 case ISD::CTTZ: return visitCTTZ(N);
741 case ISD::CTPOP: return visitCTPOP(N);
742 case ISD::SELECT: return visitSELECT(N);
743 case ISD::SELECT_CC: return visitSELECT_CC(N);
744 case ISD::SETCC: return visitSETCC(N);
745 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
746 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
747 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
748 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
749 case ISD::TRUNCATE: return visitTRUNCATE(N);
750 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
751 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
752 case ISD::FADD: return visitFADD(N);
753 case ISD::FSUB: return visitFSUB(N);
754 case ISD::FMUL: return visitFMUL(N);
755 case ISD::FDIV: return visitFDIV(N);
756 case ISD::FREM: return visitFREM(N);
757 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
758 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
759 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
760 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
761 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
762 case ISD::FP_ROUND: return visitFP_ROUND(N);
763 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
764 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
765 case ISD::FNEG: return visitFNEG(N);
766 case ISD::FABS: return visitFABS(N);
767 case ISD::BRCOND: return visitBRCOND(N);
768 case ISD::BR_CC: return visitBR_CC(N);
769 case ISD::LOAD: return visitLOAD(N);
770 case ISD::STORE: return visitSTORE(N);
771 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
772 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
773 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
774 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
775 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
780 SDValue DAGCombiner::combine(SDNode *N) {
781 SDValue RV = visit(N);
783 // If nothing happened, try a target-specific DAG combine.
784 if (RV.getNode() == 0) {
785 assert(N->getOpcode() != ISD::DELETED_NODE &&
786 "Node was deleted but visit returned NULL!");
788 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
789 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
791 // Expose the DAG combiner to the target combiner impls.
792 TargetLowering::DAGCombinerInfo
793 DagCombineInfo(DAG, Level == Unrestricted, false, this);
795 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
799 // If N is a commutative binary node, try commuting it to enable more
801 if (RV.getNode() == 0 &&
802 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
803 N->getNumValues() == 1) {
804 SDValue N0 = N->getOperand(0);
805 SDValue N1 = N->getOperand(1);
807 // Constant operands are canonicalized to RHS.
808 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
809 SDValue Ops[] = { N1, N0 };
810 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
813 return SDValue(CSENode, 0);
820 /// getInputChainForNode - Given a node, return its input chain if it has one,
821 /// otherwise return a null sd operand.
822 static SDValue getInputChainForNode(SDNode *N) {
823 if (unsigned NumOps = N->getNumOperands()) {
824 if (N->getOperand(0).getValueType() == MVT::Other)
825 return N->getOperand(0);
826 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
827 return N->getOperand(NumOps-1);
828 for (unsigned i = 1; i < NumOps-1; ++i)
829 if (N->getOperand(i).getValueType() == MVT::Other)
830 return N->getOperand(i);
835 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
836 // If N has two operands, where one has an input chain equal to the other,
837 // the 'other' chain is redundant.
838 if (N->getNumOperands() == 2) {
839 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
840 return N->getOperand(0);
841 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
842 return N->getOperand(1);
845 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
846 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
847 SmallPtrSet<SDNode*, 16> SeenOps;
848 bool Changed = false; // If we should replace this token factor.
850 // Start out with this token factor.
853 // Iterate through token factors. The TFs grows when new token factors are
855 for (unsigned i = 0; i < TFs.size(); ++i) {
858 // Check each of the operands.
859 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
860 SDValue Op = TF->getOperand(i);
862 switch (Op.getOpcode()) {
863 case ISD::EntryToken:
864 // Entry tokens don't need to be added to the list. They are
869 case ISD::TokenFactor:
870 if ((CombinerAA || Op.hasOneUse()) &&
871 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
872 // Queue up for processing.
873 TFs.push_back(Op.getNode());
874 // Clean up in case the token factor is removed.
875 AddToWorkList(Op.getNode());
882 // Only add if it isn't already in the list.
883 if (SeenOps.insert(Op.getNode()))
894 // If we've change things around then replace token factor.
897 // The entry token is the only possible outcome.
898 Result = DAG.getEntryNode();
900 // New and improved token factor.
901 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
902 MVT::Other, &Ops[0], Ops.size());
905 // Don't add users to work list.
906 return CombineTo(N, Result, false);
912 /// MERGE_VALUES can always be eliminated.
913 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
914 WorkListRemover DeadNodes(*this);
915 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
916 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
918 removeFromWorkList(N);
920 return SDValue(N, 0); // Return N so it doesn't get rechecked!
924 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
926 MVT VT = N0.getValueType();
927 SDValue N00 = N0.getOperand(0);
928 SDValue N01 = N0.getOperand(1);
929 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
931 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
932 isa<ConstantSDNode>(N00.getOperand(1))) {
933 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
934 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
935 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
936 N00.getOperand(0), N01),
937 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
938 N00.getOperand(1), N01));
939 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
946 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
947 SelectionDAG &DAG, const TargetLowering &TLI,
948 bool LegalOperations) {
949 MVT VT = N->getValueType(0);
950 unsigned Opc = N->getOpcode();
951 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
952 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
953 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
954 ISD::CondCode CC = ISD::SETCC_INVALID;
957 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
959 SDValue CCOp = Slct.getOperand(0);
960 if (CCOp.getOpcode() == ISD::SETCC)
961 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
964 bool DoXform = false;
966 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
969 if (LHS.getOpcode() == ISD::Constant &&
970 cast<ConstantSDNode>(LHS)->isNullValue()) {
972 } else if (CC != ISD::SETCC_INVALID &&
973 RHS.getOpcode() == ISD::Constant &&
974 cast<ConstantSDNode>(RHS)->isNullValue()) {
976 SDValue Op0 = Slct.getOperand(0);
977 MVT OpVT = isSlctCC ? Op0.getValueType() :
978 Op0.getOperand(0).getValueType();
979 bool isInt = OpVT.isInteger();
980 CC = ISD::getSetCCInverse(CC, isInt);
982 if (LegalOperations && !TLI.isCondCodeLegal(CC, OpVT))
983 return SDValue(); // Inverse operator isn't legal.
990 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
992 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
993 Slct.getOperand(0), Slct.getOperand(1), CC);
994 SDValue CCOp = Slct.getOperand(0);
996 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
997 CCOp.getOperand(0), CCOp.getOperand(1), CC);
998 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
999 CCOp, OtherOp, Result);
1004 SDValue DAGCombiner::visitADD(SDNode *N) {
1005 SDValue N0 = N->getOperand(0);
1006 SDValue N1 = N->getOperand(1);
1007 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1008 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1009 MVT VT = N0.getValueType();
1012 if (VT.isVector()) {
1013 SDValue FoldedVOp = SimplifyVBinOp(N);
1014 if (FoldedVOp.getNode()) return FoldedVOp;
1017 // fold (add x, undef) -> undef
1018 if (N0.getOpcode() == ISD::UNDEF)
1020 if (N1.getOpcode() == ISD::UNDEF)
1022 // fold (add c1, c2) -> c1+c2
1024 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1025 // canonicalize constant to RHS
1027 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1028 // fold (add x, 0) -> x
1029 if (N1C && N1C->isNullValue())
1031 // fold (add Sym, c) -> Sym+c
1032 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1033 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1034 GA->getOpcode() == ISD::GlobalAddress)
1035 return DAG.getGlobalAddress(GA->getGlobal(), VT,
1037 (uint64_t)N1C->getSExtValue());
1038 // fold ((c1-A)+c2) -> (c1+c2)-A
1039 if (N1C && N0.getOpcode() == ISD::SUB)
1040 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1041 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1042 DAG.getConstant(N1C->getAPIntValue()+
1043 N0C->getAPIntValue(), VT),
1046 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1047 if (RADD.getNode() != 0)
1049 // fold ((0-A) + B) -> B-A
1050 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1051 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1052 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1053 // fold (A + (0-B)) -> A-B
1054 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1055 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1056 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1057 // fold (A+(B-A)) -> B
1058 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1059 return N1.getOperand(0);
1060 // fold ((B-A)+A) -> B
1061 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1062 return N0.getOperand(0);
1063 // fold (A+(B-(A+C))) to (B-C)
1064 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1065 N0 == N1.getOperand(1).getOperand(0))
1066 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1067 N1.getOperand(1).getOperand(1));
1068 // fold (A+(B-(C+A))) to (B-C)
1069 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1070 N0 == N1.getOperand(1).getOperand(1))
1071 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1072 N1.getOperand(1).getOperand(0));
1073 // fold (A+((B-A)+or-C)) to (B+or-C)
1074 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1075 N1.getOperand(0).getOpcode() == ISD::SUB &&
1076 N0 == N1.getOperand(0).getOperand(1))
1077 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1078 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1080 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1081 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1082 SDValue N00 = N0.getOperand(0);
1083 SDValue N01 = N0.getOperand(1);
1084 SDValue N10 = N1.getOperand(0);
1085 SDValue N11 = N1.getOperand(1);
1087 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1088 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1089 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1090 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1093 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1094 return SDValue(N, 0);
1096 // fold (a+b) -> (a|b) iff a and b share no bits.
1097 if (VT.isInteger() && !VT.isVector()) {
1098 APInt LHSZero, LHSOne;
1099 APInt RHSZero, RHSOne;
1100 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
1101 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1103 if (LHSZero.getBoolValue()) {
1104 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1106 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1107 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1108 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1109 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1110 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1114 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1115 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1116 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1117 if (Result.getNode()) return Result;
1119 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1120 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1121 if (Result.getNode()) return Result;
1124 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
1125 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
1126 SDValue Result = combineSelectAndUse(N, N0, N1, DAG, TLI, LegalOperations);
1127 if (Result.getNode()) return Result;
1129 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
1130 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, LegalOperations);
1131 if (Result.getNode()) return Result;
1137 SDValue DAGCombiner::visitADDC(SDNode *N) {
1138 SDValue N0 = N->getOperand(0);
1139 SDValue N1 = N->getOperand(1);
1140 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1141 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1142 MVT VT = N0.getValueType();
1144 // If the flag result is dead, turn this into an ADD.
1145 if (N->hasNUsesOfValue(0, 1))
1146 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
1147 DAG.getNode(ISD::CARRY_FALSE,
1148 N->getDebugLoc(), MVT::Flag));
1150 // canonicalize constant to RHS.
1152 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1154 // fold (addc x, 0) -> x + no carry out
1155 if (N1C && N1C->isNullValue())
1156 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1157 N->getDebugLoc(), MVT::Flag));
1159 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1160 APInt LHSZero, LHSOne;
1161 APInt RHSZero, RHSOne;
1162 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
1163 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1165 if (LHSZero.getBoolValue()) {
1166 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1168 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1169 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1170 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1171 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1172 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1173 DAG.getNode(ISD::CARRY_FALSE,
1174 N->getDebugLoc(), MVT::Flag));
1180 SDValue DAGCombiner::visitADDE(SDNode *N) {
1181 SDValue N0 = N->getOperand(0);
1182 SDValue N1 = N->getOperand(1);
1183 SDValue CarryIn = N->getOperand(2);
1184 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1185 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1187 // canonicalize constant to RHS
1189 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1192 // fold (adde x, y, false) -> (addc x, y)
1193 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1194 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1199 SDValue DAGCombiner::visitSUB(SDNode *N) {
1200 SDValue N0 = N->getOperand(0);
1201 SDValue N1 = N->getOperand(1);
1202 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1203 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1204 MVT VT = N0.getValueType();
1207 if (VT.isVector()) {
1208 SDValue FoldedVOp = SimplifyVBinOp(N);
1209 if (FoldedVOp.getNode()) return FoldedVOp;
1212 // fold (sub x, x) -> 0
1214 return DAG.getConstant(0, N->getValueType(0));
1215 // fold (sub c1, c2) -> c1-c2
1217 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1218 // fold (sub x, c) -> (add x, -c)
1220 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1221 DAG.getConstant(-N1C->getAPIntValue(), VT));
1222 // fold (A+B)-A -> B
1223 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1224 return N0.getOperand(1);
1225 // fold (A+B)-B -> A
1226 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1227 return N0.getOperand(0);
1228 // fold ((A+(B+or-C))-B) -> A+or-C
1229 if (N0.getOpcode() == ISD::ADD &&
1230 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1231 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1232 N0.getOperand(1).getOperand(0) == N1)
1233 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1234 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1235 // fold ((A+(C+B))-B) -> A+C
1236 if (N0.getOpcode() == ISD::ADD &&
1237 N0.getOperand(1).getOpcode() == ISD::ADD &&
1238 N0.getOperand(1).getOperand(1) == N1)
1239 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1240 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1241 // fold ((A-(B-C))-C) -> A-B
1242 if (N0.getOpcode() == ISD::SUB &&
1243 N0.getOperand(1).getOpcode() == ISD::SUB &&
1244 N0.getOperand(1).getOperand(1) == N1)
1245 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1246 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1247 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1248 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
1249 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, LegalOperations);
1250 if (Result.getNode()) return Result;
1253 // If either operand of a sub is undef, the result is undef
1254 if (N0.getOpcode() == ISD::UNDEF)
1256 if (N1.getOpcode() == ISD::UNDEF)
1259 // If the relocation model supports it, consider symbol offsets.
1260 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1261 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1262 // fold (sub Sym, c) -> Sym-c
1263 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1264 return DAG.getGlobalAddress(GA->getGlobal(), VT,
1266 (uint64_t)N1C->getSExtValue());
1267 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1268 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1269 if (GA->getGlobal() == GB->getGlobal())
1270 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1277 SDValue DAGCombiner::visitMUL(SDNode *N) {
1278 SDValue N0 = N->getOperand(0);
1279 SDValue N1 = N->getOperand(1);
1280 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1281 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1282 MVT VT = N0.getValueType();
1285 if (VT.isVector()) {
1286 SDValue FoldedVOp = SimplifyVBinOp(N);
1287 if (FoldedVOp.getNode()) return FoldedVOp;
1290 // fold (mul x, undef) -> 0
1291 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1292 return DAG.getConstant(0, VT);
1293 // fold (mul c1, c2) -> c1*c2
1295 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1296 // canonicalize constant to RHS
1298 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1299 // fold (mul x, 0) -> 0
1300 if (N1C && N1C->isNullValue())
1302 // fold (mul x, -1) -> 0-x
1303 if (N1C && N1C->isAllOnesValue())
1304 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1305 DAG.getConstant(0, VT), N0);
1306 // fold (mul x, (1 << c)) -> x << c
1307 if (N1C && N1C->getAPIntValue().isPowerOf2())
1308 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1309 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1310 getShiftAmountTy()));
1311 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1312 if (N1C && isPowerOf2_64(-N1C->getSExtValue()))
1313 // FIXME: If the input is something that is easily negated (e.g. a
1314 // single-use add), we should put the negate there.
1315 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1316 DAG.getConstant(0, VT),
1317 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1318 DAG.getConstant(Log2_64(-N1C->getSExtValue()),
1319 getShiftAmountTy())));
1320 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1321 if (N1C && N0.getOpcode() == ISD::SHL &&
1322 isa<ConstantSDNode>(N0.getOperand(1))) {
1323 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1324 N1, N0.getOperand(1));
1325 AddToWorkList(C3.getNode());
1326 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1327 N0.getOperand(0), C3);
1330 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1333 SDValue Sh(0,0), Y(0,0);
1334 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1335 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1336 N0.getNode()->hasOneUse()) {
1338 } else if (N1.getOpcode() == ISD::SHL &&
1339 isa<ConstantSDNode>(N1.getOperand(1)) &&
1340 N1.getNode()->hasOneUse()) {
1345 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1346 Sh.getOperand(0), Y);
1347 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1348 Mul, Sh.getOperand(1));
1352 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1353 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1354 isa<ConstantSDNode>(N0.getOperand(1)))
1355 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1356 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1357 N0.getOperand(0), N1),
1358 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1359 N0.getOperand(1), N1));
1362 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1363 if (RMUL.getNode() != 0)
1369 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1370 SDValue N0 = N->getOperand(0);
1371 SDValue N1 = N->getOperand(1);
1372 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1373 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1374 MVT VT = N->getValueType(0);
1377 if (VT.isVector()) {
1378 SDValue FoldedVOp = SimplifyVBinOp(N);
1379 if (FoldedVOp.getNode()) return FoldedVOp;
1382 // fold (sdiv c1, c2) -> c1/c2
1383 if (N0C && N1C && !N1C->isNullValue())
1384 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1385 // fold (sdiv X, 1) -> X
1386 if (N1C && N1C->getSExtValue() == 1LL)
1388 // fold (sdiv X, -1) -> 0-X
1389 if (N1C && N1C->isAllOnesValue())
1390 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1391 DAG.getConstant(0, VT), N0);
1392 // If we know the sign bits of both operands are zero, strength reduce to a
1393 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1394 if (!VT.isVector()) {
1395 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1396 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1399 // fold (sdiv X, pow2) -> simple ops after legalize
1400 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
1401 (isPowerOf2_64(N1C->getSExtValue()) ||
1402 isPowerOf2_64(-N1C->getSExtValue()))) {
1403 // If dividing by powers of two is cheap, then don't perform the following
1405 if (TLI.isPow2DivCheap())
1408 int64_t pow2 = N1C->getSExtValue();
1409 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1410 unsigned lg2 = Log2_64(abs2);
1412 // Splat the sign bit into the register
1413 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1414 DAG.getConstant(VT.getSizeInBits()-1,
1415 getShiftAmountTy()));
1416 AddToWorkList(SGN.getNode());
1418 // Add (N0 < 0) ? abs2 - 1 : 0;
1419 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1420 DAG.getConstant(VT.getSizeInBits() - lg2,
1421 getShiftAmountTy()));
1422 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1423 AddToWorkList(SRL.getNode());
1424 AddToWorkList(ADD.getNode()); // Divide by pow2
1425 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1426 DAG.getConstant(lg2, getShiftAmountTy()));
1428 // If we're dividing by a positive value, we're done. Otherwise, we must
1429 // negate the result.
1433 AddToWorkList(SRA.getNode());
1434 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1435 DAG.getConstant(0, VT), SRA);
1438 // if integer divide is expensive and we satisfy the requirements, emit an
1439 // alternate sequence.
1440 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
1441 !TLI.isIntDivCheap()) {
1442 SDValue Op = BuildSDIV(N);
1443 if (Op.getNode()) return Op;
1447 if (N0.getOpcode() == ISD::UNDEF)
1448 return DAG.getConstant(0, VT);
1449 // X / undef -> undef
1450 if (N1.getOpcode() == ISD::UNDEF)
1456 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1457 SDValue N0 = N->getOperand(0);
1458 SDValue N1 = N->getOperand(1);
1459 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1460 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1461 MVT VT = N->getValueType(0);
1464 if (VT.isVector()) {
1465 SDValue FoldedVOp = SimplifyVBinOp(N);
1466 if (FoldedVOp.getNode()) return FoldedVOp;
1469 // fold (udiv c1, c2) -> c1/c2
1470 if (N0C && N1C && !N1C->isNullValue())
1471 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1472 // fold (udiv x, (1 << c)) -> x >>u c
1473 if (N1C && N1C->getAPIntValue().isPowerOf2())
1474 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1475 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1476 getShiftAmountTy()));
1477 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1478 if (N1.getOpcode() == ISD::SHL) {
1479 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1480 if (SHC->getAPIntValue().isPowerOf2()) {
1481 MVT ADDVT = N1.getOperand(1).getValueType();
1482 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1484 DAG.getConstant(SHC->getAPIntValue()
1487 AddToWorkList(Add.getNode());
1488 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1492 // fold (udiv x, c) -> alternate
1493 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1494 SDValue Op = BuildUDIV(N);
1495 if (Op.getNode()) return Op;
1499 if (N0.getOpcode() == ISD::UNDEF)
1500 return DAG.getConstant(0, VT);
1501 // X / undef -> undef
1502 if (N1.getOpcode() == ISD::UNDEF)
1508 SDValue DAGCombiner::visitSREM(SDNode *N) {
1509 SDValue N0 = N->getOperand(0);
1510 SDValue N1 = N->getOperand(1);
1511 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1512 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1513 MVT VT = N->getValueType(0);
1515 // fold (srem c1, c2) -> c1%c2
1516 if (N0C && N1C && !N1C->isNullValue())
1517 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1518 // If we know the sign bits of both operands are zero, strength reduce to a
1519 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1520 if (!VT.isVector()) {
1521 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1522 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1525 // If X/C can be simplified by the division-by-constant logic, lower
1526 // X%C to the equivalent of X-X/C*C.
1527 if (N1C && !N1C->isNullValue()) {
1528 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1529 AddToWorkList(Div.getNode());
1530 SDValue OptimizedDiv = combine(Div.getNode());
1531 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1532 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1534 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1535 AddToWorkList(Mul.getNode());
1541 if (N0.getOpcode() == ISD::UNDEF)
1542 return DAG.getConstant(0, VT);
1543 // X % undef -> undef
1544 if (N1.getOpcode() == ISD::UNDEF)
1550 SDValue DAGCombiner::visitUREM(SDNode *N) {
1551 SDValue N0 = N->getOperand(0);
1552 SDValue N1 = N->getOperand(1);
1553 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1554 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1555 MVT VT = N->getValueType(0);
1557 // fold (urem c1, c2) -> c1%c2
1558 if (N0C && N1C && !N1C->isNullValue())
1559 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
1560 // fold (urem x, pow2) -> (and x, pow2-1)
1561 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
1562 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
1563 DAG.getConstant(N1C->getAPIntValue()-1,VT));
1564 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1565 if (N1.getOpcode() == ISD::SHL) {
1566 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1567 if (SHC->getAPIntValue().isPowerOf2()) {
1569 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
1570 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
1572 AddToWorkList(Add.getNode());
1573 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
1578 // If X/C can be simplified by the division-by-constant logic, lower
1579 // X%C to the equivalent of X-X/C*C.
1580 if (N1C && !N1C->isNullValue()) {
1581 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
1582 AddToWorkList(Div.getNode());
1583 SDValue OptimizedDiv = combine(Div.getNode());
1584 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1585 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1587 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1588 AddToWorkList(Mul.getNode());
1594 if (N0.getOpcode() == ISD::UNDEF)
1595 return DAG.getConstant(0, VT);
1596 // X % undef -> undef
1597 if (N1.getOpcode() == ISD::UNDEF)
1603 SDValue DAGCombiner::visitMULHS(SDNode *N) {
1604 SDValue N0 = N->getOperand(0);
1605 SDValue N1 = N->getOperand(1);
1606 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1607 MVT VT = N->getValueType(0);
1609 // fold (mulhs x, 0) -> 0
1610 if (N1C && N1C->isNullValue())
1612 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1613 if (N1C && N1C->getAPIntValue() == 1)
1614 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
1615 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
1616 getShiftAmountTy()));
1617 // fold (mulhs x, undef) -> 0
1618 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1619 return DAG.getConstant(0, VT);
1624 SDValue DAGCombiner::visitMULHU(SDNode *N) {
1625 SDValue N0 = N->getOperand(0);
1626 SDValue N1 = N->getOperand(1);
1627 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1628 MVT VT = N->getValueType(0);
1630 // fold (mulhu x, 0) -> 0
1631 if (N1C && N1C->isNullValue())
1633 // fold (mulhu x, 1) -> 0
1634 if (N1C && N1C->getAPIntValue() == 1)
1635 return DAG.getConstant(0, N0.getValueType());
1636 // fold (mulhu x, undef) -> 0
1637 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1638 return DAG.getConstant(0, VT);
1643 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1644 /// compute two values. LoOp and HiOp give the opcodes for the two computations
1645 /// that are being performed. Return true if a simplification was made.
1647 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
1649 // If the high half is not needed, just compute the low half.
1650 bool HiExists = N->hasAnyUseOfValue(1);
1652 (!LegalOperations ||
1653 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1654 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1655 N->op_begin(), N->getNumOperands());
1656 return CombineTo(N, Res, Res);
1659 // If the low half is not needed, just compute the high half.
1660 bool LoExists = N->hasAnyUseOfValue(0);
1662 (!LegalOperations ||
1663 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
1664 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1665 N->op_begin(), N->getNumOperands());
1666 return CombineTo(N, Res, Res);
1669 // If both halves are used, return as it is.
1670 if (LoExists && HiExists)
1673 // If the two computed results can be simplified separately, separate them.
1675 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1676 N->op_begin(), N->getNumOperands());
1677 AddToWorkList(Lo.getNode());
1678 SDValue LoOpt = combine(Lo.getNode());
1679 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
1680 (!LegalOperations ||
1681 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
1682 return CombineTo(N, LoOpt, LoOpt);
1686 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1687 N->op_begin(), N->getNumOperands());
1688 AddToWorkList(Hi.getNode());
1689 SDValue HiOpt = combine(Hi.getNode());
1690 if (HiOpt.getNode() && HiOpt != Hi &&
1691 (!LegalOperations ||
1692 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
1693 return CombineTo(N, HiOpt, HiOpt);
1699 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
1700 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
1701 if (Res.getNode()) return Res;
1706 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
1707 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
1708 if (Res.getNode()) return Res;
1713 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
1714 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
1715 if (Res.getNode()) return Res;
1720 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
1721 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
1722 if (Res.getNode()) return Res;
1727 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1728 /// two operands of the same opcode, try to simplify it.
1729 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1730 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1731 MVT VT = N0.getValueType();
1732 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1734 // For each of OP in AND/OR/XOR:
1735 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1736 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1737 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1738 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1739 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1740 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1741 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1742 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
1743 N0.getOperand(0).getValueType(),
1744 N0.getOperand(0), N1.getOperand(0));
1745 AddToWorkList(ORNode.getNode());
1746 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
1749 // For each of OP in SHL/SRL/SRA/AND...
1750 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1751 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1752 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1753 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1754 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1755 N0.getOperand(1) == N1.getOperand(1)) {
1756 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
1757 N0.getOperand(0).getValueType(),
1758 N0.getOperand(0), N1.getOperand(0));
1759 AddToWorkList(ORNode.getNode());
1760 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
1761 ORNode, N0.getOperand(1));
1767 SDValue DAGCombiner::visitAND(SDNode *N) {
1768 SDValue N0 = N->getOperand(0);
1769 SDValue N1 = N->getOperand(1);
1770 SDValue LL, LR, RL, RR, CC0, CC1;
1771 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1772 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1773 MVT VT = N1.getValueType();
1774 unsigned BitWidth = VT.getSizeInBits();
1777 if (VT.isVector()) {
1778 SDValue FoldedVOp = SimplifyVBinOp(N);
1779 if (FoldedVOp.getNode()) return FoldedVOp;
1782 // fold (and x, undef) -> 0
1783 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1784 return DAG.getConstant(0, VT);
1785 // fold (and c1, c2) -> c1&c2
1787 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
1788 // canonicalize constant to RHS
1790 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
1791 // fold (and x, -1) -> x
1792 if (N1C && N1C->isAllOnesValue())
1794 // if (and x, c) is known to be zero, return 0
1795 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
1796 APInt::getAllOnesValue(BitWidth)))
1797 return DAG.getConstant(0, VT);
1799 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
1800 if (RAND.getNode() != 0)
1802 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1803 if (N1C && N0.getOpcode() == ISD::OR)
1804 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1805 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
1807 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1808 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1809 SDValue N0Op0 = N0.getOperand(0);
1810 APInt Mask = ~N1C->getAPIntValue();
1811 Mask.trunc(N0Op0.getValueSizeInBits());
1812 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
1813 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
1814 N0.getValueType(), N0Op0);
1816 // Replace uses of the AND with uses of the Zero extend node.
1819 // We actually want to replace all uses of the any_extend with the
1820 // zero_extend, to avoid duplicating things. This will later cause this
1821 // AND to be folded.
1822 CombineTo(N0.getNode(), Zext);
1823 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1826 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1827 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1828 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1829 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1831 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1832 LL.getValueType().isInteger()) {
1833 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
1834 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
1835 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
1836 LR.getValueType(), LL, RL);
1837 AddToWorkList(ORNode.getNode());
1838 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
1840 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
1841 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1842 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
1843 LR.getValueType(), LL, RL);
1844 AddToWorkList(ANDNode.getNode());
1845 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
1847 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
1848 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1849 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
1850 LR.getValueType(), LL, RL);
1851 AddToWorkList(ORNode.getNode());
1852 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
1855 // canonicalize equivalent to ll == rl
1856 if (LL == RR && LR == RL) {
1857 Op1 = ISD::getSetCCSwappedOperands(Op1);
1860 if (LL == RL && LR == RR) {
1861 bool isInteger = LL.getValueType().isInteger();
1862 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1863 if (Result != ISD::SETCC_INVALID &&
1864 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
1865 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
1870 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
1871 if (N0.getOpcode() == N1.getOpcode()) {
1872 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1873 if (Tmp.getNode()) return Tmp;
1876 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1877 // fold (and (sra)) -> (and (srl)) when possible.
1878 if (!VT.isVector() &&
1879 SimplifyDemandedBits(SDValue(N, 0)))
1880 return SDValue(N, 0);
1881 // fold (zext_inreg (extload x)) -> (zextload x)
1882 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
1883 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1884 MVT EVT = LN0->getMemoryVT();
1885 // If we zero all the possible extended bits, then we can turn this into
1886 // a zextload if we are running before legalize or the operation is legal.
1887 unsigned BitWidth = N1.getValueSizeInBits();
1888 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1889 BitWidth - EVT.getSizeInBits())) &&
1890 ((!LegalOperations && !LN0->isVolatile()) ||
1891 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
1892 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
1893 LN0->getChain(), LN0->getBasePtr(),
1895 LN0->getSrcValueOffset(), EVT,
1896 LN0->isVolatile(), LN0->getAlignment());
1898 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
1899 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1902 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1903 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
1905 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1906 MVT EVT = LN0->getMemoryVT();
1907 // If we zero all the possible extended bits, then we can turn this into
1908 // a zextload if we are running before legalize or the operation is legal.
1909 unsigned BitWidth = N1.getValueSizeInBits();
1910 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1911 BitWidth - EVT.getSizeInBits())) &&
1912 ((!LegalOperations && !LN0->isVolatile()) ||
1913 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
1914 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
1916 LN0->getBasePtr(), LN0->getSrcValue(),
1917 LN0->getSrcValueOffset(), EVT,
1918 LN0->isVolatile(), LN0->getAlignment());
1920 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
1921 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1925 // fold (and (load x), 255) -> (zextload x, i8)
1926 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1927 if (N1C && N0.getOpcode() == ISD::LOAD) {
1928 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1929 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1930 LN0->isUnindexed() && N0.hasOneUse() &&
1931 // Do not change the width of a volatile load.
1932 !LN0->isVolatile()) {
1933 MVT EVT = MVT::Other;
1934 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
1935 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue()))
1936 EVT = MVT::getIntegerVT(ActiveBits);
1938 MVT LoadedVT = LN0->getMemoryVT();
1940 // Do not generate loads of non-round integer types since these can
1941 // be expensive (and would be wrong if the type is not byte sized).
1942 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() &&
1943 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
1944 MVT PtrType = N0.getOperand(1).getValueType();
1946 // For big endian targets, we need to add an offset to the pointer to
1947 // load the correct bytes. For little endian systems, we merely need to
1948 // read fewer bytes from the same pointer.
1949 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8;
1950 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8;
1951 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
1952 unsigned Alignment = LN0->getAlignment();
1953 SDValue NewPtr = LN0->getBasePtr();
1955 if (TLI.isBigEndian()) {
1956 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
1957 NewPtr, DAG.getConstant(PtrOff, PtrType));
1958 Alignment = MinAlign(Alignment, PtrOff);
1961 AddToWorkList(NewPtr.getNode());
1963 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(),
1964 NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(),
1965 EVT, LN0->isVolatile(), Alignment);
1967 CombineTo(N0.getNode(), Load, Load.getValue(1));
1968 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1976 SDValue DAGCombiner::visitOR(SDNode *N) {
1977 SDValue N0 = N->getOperand(0);
1978 SDValue N1 = N->getOperand(1);
1979 SDValue LL, LR, RL, RR, CC0, CC1;
1980 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1981 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1982 MVT VT = N1.getValueType();
1985 if (VT.isVector()) {
1986 SDValue FoldedVOp = SimplifyVBinOp(N);
1987 if (FoldedVOp.getNode()) return FoldedVOp;
1990 // fold (or x, undef) -> -1
1991 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1992 return DAG.getConstant(~0ULL, VT);
1993 // fold (or c1, c2) -> c1|c2
1995 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
1996 // canonicalize constant to RHS
1998 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
1999 // fold (or x, 0) -> x
2000 if (N1C && N1C->isNullValue())
2002 // fold (or x, -1) -> -1
2003 if (N1C && N1C->isAllOnesValue())
2005 // fold (or x, c) -> c iff (x & ~c) == 0
2006 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
2009 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
2010 if (ROR.getNode() != 0)
2012 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
2013 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
2014 isa<ConstantSDNode>(N0.getOperand(1))) {
2015 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
2016 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
2017 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2018 N0.getOperand(0), N1),
2019 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
2021 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
2022 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2023 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2024 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2026 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2027 LL.getValueType().isInteger()) {
2028 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
2029 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
2030 if (cast<ConstantSDNode>(LR)->isNullValue() &&
2031 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
2032 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
2033 LR.getValueType(), LL, RL);
2034 AddToWorkList(ORNode.getNode());
2035 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2037 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
2038 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
2039 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2040 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
2041 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
2042 LR.getValueType(), LL, RL);
2043 AddToWorkList(ANDNode.getNode());
2044 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2047 // canonicalize equivalent to ll == rl
2048 if (LL == RR && LR == RL) {
2049 Op1 = ISD::getSetCCSwappedOperands(Op1);
2052 if (LL == RL && LR == RR) {
2053 bool isInteger = LL.getValueType().isInteger();
2054 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
2055 if (Result != ISD::SETCC_INVALID &&
2056 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2057 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2062 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
2063 if (N0.getOpcode() == N1.getOpcode()) {
2064 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2065 if (Tmp.getNode()) return Tmp;
2068 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
2069 if (N0.getOpcode() == ISD::AND &&
2070 N1.getOpcode() == ISD::AND &&
2071 N0.getOperand(1).getOpcode() == ISD::Constant &&
2072 N1.getOperand(1).getOpcode() == ISD::Constant &&
2073 // Don't increase # computations.
2074 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
2075 // We can only do this xform if we know that bits from X that are set in C2
2076 // but not in C1 are already zero. Likewise for Y.
2077 const APInt &LHSMask =
2078 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2079 const APInt &RHSMask =
2080 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
2082 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
2083 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
2084 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2085 N0.getOperand(0), N1.getOperand(0));
2086 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
2087 DAG.getConstant(LHSMask | RHSMask, VT));
2091 // See if this is some rotate idiom.
2092 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
2093 return SDValue(Rot, 0);
2098 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
2099 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
2100 if (Op.getOpcode() == ISD::AND) {
2101 if (isa<ConstantSDNode>(Op.getOperand(1))) {
2102 Mask = Op.getOperand(1);
2103 Op = Op.getOperand(0);
2109 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
2117 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
2118 // idioms for rotate, and if the target supports rotation instructions, generate
2120 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
2121 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
2122 MVT VT = LHS.getValueType();
2123 if (!TLI.isTypeLegal(VT)) return 0;
2125 // The target must have at least one rotate flavor.
2126 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
2127 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
2128 if (!HasROTL && !HasROTR) return 0;
2130 // Match "(X shl/srl V1) & V2" where V2 may not be present.
2131 SDValue LHSShift; // The shift.
2132 SDValue LHSMask; // AND value if any.
2133 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
2134 return 0; // Not part of a rotate.
2136 SDValue RHSShift; // The shift.
2137 SDValue RHSMask; // AND value if any.
2138 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
2139 return 0; // Not part of a rotate.
2141 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
2142 return 0; // Not shifting the same value.
2144 if (LHSShift.getOpcode() == RHSShift.getOpcode())
2145 return 0; // Shifts must disagree.
2147 // Canonicalize shl to left side in a shl/srl pair.
2148 if (RHSShift.getOpcode() == ISD::SHL) {
2149 std::swap(LHS, RHS);
2150 std::swap(LHSShift, RHSShift);
2151 std::swap(LHSMask , RHSMask );
2154 unsigned OpSizeInBits = VT.getSizeInBits();
2155 SDValue LHSShiftArg = LHSShift.getOperand(0);
2156 SDValue LHSShiftAmt = LHSShift.getOperand(1);
2157 SDValue RHSShiftAmt = RHSShift.getOperand(1);
2159 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
2160 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
2161 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
2162 RHSShiftAmt.getOpcode() == ISD::Constant) {
2163 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
2164 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
2165 if ((LShVal + RShVal) != OpSizeInBits)
2170 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
2172 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
2174 // If there is an AND of either shifted operand, apply it to the result.
2175 if (LHSMask.getNode() || RHSMask.getNode()) {
2176 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
2178 if (LHSMask.getNode()) {
2179 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
2180 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
2182 if (RHSMask.getNode()) {
2183 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
2184 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
2187 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
2190 return Rot.getNode();
2193 // If there is a mask here, and we have a variable shift, we can't be sure
2194 // that we're masking out the right stuff.
2195 if (LHSMask.getNode() || RHSMask.getNode())
2198 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
2199 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
2200 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
2201 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
2202 if (ConstantSDNode *SUBC =
2203 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
2204 if (SUBC->getAPIntValue() == OpSizeInBits) {
2206 return DAG.getNode(ISD::ROTL, DL, VT,
2207 LHSShiftArg, LHSShiftAmt).getNode();
2209 return DAG.getNode(ISD::ROTR, DL, VT,
2210 LHSShiftArg, RHSShiftAmt).getNode();
2215 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2216 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
2217 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
2218 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
2219 if (ConstantSDNode *SUBC =
2220 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
2221 if (SUBC->getAPIntValue() == OpSizeInBits) {
2223 return DAG.getNode(ISD::ROTR, DL, VT,
2224 LHSShiftArg, RHSShiftAmt).getNode();
2226 return DAG.getNode(ISD::ROTL, DL, VT,
2227 LHSShiftArg, LHSShiftAmt).getNode();
2232 // Look for sign/zext/any-extended or truncate cases:
2233 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2234 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2235 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2236 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
2237 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2238 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2239 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2240 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
2241 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
2242 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
2243 if (RExtOp0.getOpcode() == ISD::SUB &&
2244 RExtOp0.getOperand(1) == LExtOp0) {
2245 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2247 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2248 // (rotr x, (sub 32, y))
2249 if (ConstantSDNode *SUBC =
2250 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
2251 if (SUBC->getAPIntValue() == OpSizeInBits) {
2252 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
2254 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
2257 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2258 RExtOp0 == LExtOp0.getOperand(1)) {
2259 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2261 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2262 // (rotl x, (sub 32, y))
2263 if (ConstantSDNode *SUBC =
2264 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2265 if (SUBC->getAPIntValue() == OpSizeInBits) {
2266 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
2268 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
2277 SDValue DAGCombiner::visitXOR(SDNode *N) {
2278 SDValue N0 = N->getOperand(0);
2279 SDValue N1 = N->getOperand(1);
2280 SDValue LHS, RHS, CC;
2281 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2282 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2283 MVT VT = N0.getValueType();
2286 if (VT.isVector()) {
2287 SDValue FoldedVOp = SimplifyVBinOp(N);
2288 if (FoldedVOp.getNode()) return FoldedVOp;
2291 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
2292 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
2293 return DAG.getConstant(0, VT);
2294 // fold (xor x, undef) -> undef
2295 if (N0.getOpcode() == ISD::UNDEF)
2297 if (N1.getOpcode() == ISD::UNDEF)
2299 // fold (xor c1, c2) -> c1^c2
2301 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
2302 // canonicalize constant to RHS
2304 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
2305 // fold (xor x, 0) -> x
2306 if (N1C && N1C->isNullValue())
2309 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
2310 if (RXOR.getNode() != 0)
2313 // fold !(x cc y) -> (x !cc y)
2314 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2315 bool isInt = LHS.getValueType().isInteger();
2316 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2319 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
2320 switch (N0.getOpcode()) {
2322 assert(0 && "Unhandled SetCC Equivalent!");
2325 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
2326 case ISD::SELECT_CC:
2327 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
2328 N0.getOperand(3), NotCC);
2333 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2334 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2335 N0.getNode()->hasOneUse() &&
2336 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2337 SDValue V = N0.getOperand(0);
2338 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
2339 DAG.getConstant(1, V.getValueType()));
2340 AddToWorkList(V.getNode());
2341 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
2344 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
2345 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
2346 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2347 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2348 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2349 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2350 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2351 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2352 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2353 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2356 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
2357 if (N1C && N1C->isAllOnesValue() &&
2358 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2359 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2360 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2361 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2362 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2363 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2364 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2365 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2368 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
2369 if (N1C && N0.getOpcode() == ISD::XOR) {
2370 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2371 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2373 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
2374 DAG.getConstant(N1C->getAPIntValue() ^
2375 N00C->getAPIntValue(), VT));
2377 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
2378 DAG.getConstant(N1C->getAPIntValue() ^
2379 N01C->getAPIntValue(), VT));
2381 // fold (xor x, x) -> 0
2383 if (!VT.isVector()) {
2384 return DAG.getConstant(0, VT);
2385 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){
2386 // Produce a vector of zeros.
2387 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
2388 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
2389 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
2390 &Ops[0], Ops.size());
2394 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2395 if (N0.getOpcode() == N1.getOpcode()) {
2396 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2397 if (Tmp.getNode()) return Tmp;
2400 // Simplify the expression using non-local knowledge.
2401 if (!VT.isVector() &&
2402 SimplifyDemandedBits(SDValue(N, 0)))
2403 return SDValue(N, 0);
2408 /// visitShiftByConstant - Handle transforms common to the three shifts, when
2409 /// the shift amount is a constant.
2410 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
2411 SDNode *LHS = N->getOperand(0).getNode();
2412 if (!LHS->hasOneUse()) return SDValue();
2414 // We want to pull some binops through shifts, so that we have (and (shift))
2415 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
2416 // thing happens with address calculations, so it's important to canonicalize
2418 bool HighBitSet = false; // Can we transform this if the high bit is set?
2420 switch (LHS->getOpcode()) {
2421 default: return SDValue();
2424 HighBitSet = false; // We can only transform sra if the high bit is clear.
2427 HighBitSet = true; // We can only transform sra if the high bit is set.
2430 if (N->getOpcode() != ISD::SHL)
2431 return SDValue(); // only shl(add) not sr[al](add).
2432 HighBitSet = false; // We can only transform sra if the high bit is clear.
2436 // We require the RHS of the binop to be a constant as well.
2437 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
2438 if (!BinOpCst) return SDValue();
2440 // FIXME: disable this unless the input to the binop is a shift by a constant.
2441 // If it is not a shift, it pessimizes some common cases like:
2443 // void foo(int *X, int i) { X[i & 1235] = 1; }
2444 // int bar(int *X, int i) { return X[i & 255]; }
2445 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
2446 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
2447 BinOpLHSVal->getOpcode() != ISD::SRA &&
2448 BinOpLHSVal->getOpcode() != ISD::SRL) ||
2449 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
2452 MVT VT = N->getValueType(0);
2454 // If this is a signed shift right, and the high bit is modified by the
2455 // logical operation, do not perform the transformation. The highBitSet
2456 // boolean indicates the value of the high bit of the constant which would
2457 // cause it to be modified for this operation.
2458 if (N->getOpcode() == ISD::SRA) {
2459 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
2460 if (BinOpRHSSignSet != HighBitSet)
2464 // Fold the constants, shifting the binop RHS by the shift amount.
2465 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
2467 LHS->getOperand(1), N->getOperand(1));
2469 // Create the new shift.
2470 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(),
2471 VT, LHS->getOperand(0), N->getOperand(1));
2473 // Create the new binop.
2474 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
2477 SDValue DAGCombiner::visitSHL(SDNode *N) {
2478 SDValue N0 = N->getOperand(0);
2479 SDValue N1 = N->getOperand(1);
2480 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2481 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2482 MVT VT = N0.getValueType();
2483 unsigned OpSizeInBits = VT.getSizeInBits();
2485 // fold (shl c1, c2) -> c1<<c2
2487 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
2488 // fold (shl 0, x) -> 0
2489 if (N0C && N0C->isNullValue())
2491 // fold (shl x, c >= size(x)) -> undef
2492 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2493 return DAG.getUNDEF(VT);
2494 // fold (shl x, 0) -> x
2495 if (N1C && N1C->isNullValue())
2497 // if (shl x, c) is known to be zero, return 0
2498 if (DAG.MaskedValueIsZero(SDValue(N, 0),
2499 APInt::getAllOnesValue(VT.getSizeInBits())))
2500 return DAG.getConstant(0, VT);
2501 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
2502 if (N1.getOpcode() == ISD::TRUNCATE &&
2503 N1.getOperand(0).getOpcode() == ISD::AND &&
2504 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2505 SDValue N101 = N1.getOperand(0).getOperand(1);
2506 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2507 MVT TruncVT = N1.getValueType();
2508 SDValue N100 = N1.getOperand(0).getOperand(0);
2509 APInt TruncC = N101C->getAPIntValue();
2510 TruncC.trunc(TruncVT.getSizeInBits());
2511 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
2512 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
2513 DAG.getNode(ISD::TRUNCATE,
2516 DAG.getConstant(TruncC, TruncVT)));
2520 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2521 return SDValue(N, 0);
2523 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
2524 if (N1C && N0.getOpcode() == ISD::SHL &&
2525 N0.getOperand(1).getOpcode() == ISD::Constant) {
2526 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2527 uint64_t c2 = N1C->getZExtValue();
2528 if (c1 + c2 > OpSizeInBits)
2529 return DAG.getConstant(0, VT);
2530 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
2531 DAG.getConstant(c1 + c2, N1.getValueType()));
2533 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or
2534 // (srl (and x, (shl -1, c1)), (sub c1, c2))
2535 if (N1C && N0.getOpcode() == ISD::SRL &&
2536 N0.getOperand(1).getOpcode() == ISD::Constant) {
2537 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2538 uint64_t c2 = N1C->getZExtValue();
2539 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, N0.getOperand(0),
2540 DAG.getConstant(~0ULL << c1, VT));
2542 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask,
2543 DAG.getConstant(c2-c1, N1.getValueType()));
2545 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask,
2546 DAG.getConstant(c1-c2, N1.getValueType()));
2548 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
2549 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
2550 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
2551 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT));
2553 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2556 SDValue DAGCombiner::visitSRA(SDNode *N) {
2557 SDValue N0 = N->getOperand(0);
2558 SDValue N1 = N->getOperand(1);
2559 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2560 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2561 MVT VT = N0.getValueType();
2563 // fold (sra c1, c2) -> (sra c1, c2)
2565 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
2566 // fold (sra 0, x) -> 0
2567 if (N0C && N0C->isNullValue())
2569 // fold (sra -1, x) -> -1
2570 if (N0C && N0C->isAllOnesValue())
2572 // fold (sra x, (setge c, size(x))) -> undef
2573 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits())
2574 return DAG.getUNDEF(VT);
2575 // fold (sra x, 0) -> x
2576 if (N1C && N1C->isNullValue())
2578 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2580 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2581 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue();
2582 MVT EVT = MVT::getIntegerVT(LowBits);
2583 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)))
2584 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
2585 N0.getOperand(0), DAG.getValueType(EVT));
2588 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
2589 if (N1C && N0.getOpcode() == ISD::SRA) {
2590 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2591 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
2592 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1;
2593 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
2594 DAG.getConstant(Sum, N1C->getValueType(0)));
2598 // fold (sra (shl X, m), (sub result_size, n))
2599 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
2600 // result_size - n != m.
2601 // If truncate is free for the target sext(shl) is likely to result in better
2603 if (N0.getOpcode() == ISD::SHL) {
2604 // Get the two constanst of the shifts, CN0 = m, CN = n.
2605 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2607 // Determine what the truncate's result bitsize and type would be.
2608 unsigned VTValSize = VT.getSizeInBits();
2610 MVT::getIntegerVT(VTValSize - N1C->getZExtValue());
2611 // Determine the residual right-shift amount.
2612 unsigned ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
2614 // If the shift is not a no-op (in which case this should be just a sign
2615 // extend already), the truncated to type is legal, sign_extend is legal
2616 // on that type, and the the truncate to that type is both legal and free,
2617 // perform the transform.
2619 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
2620 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
2621 TLI.isTruncateFree(VT, TruncVT)) {
2623 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy());
2624 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
2625 N0.getOperand(0), Amt);
2626 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
2628 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
2629 N->getValueType(0), Trunc);
2634 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
2635 if (N1.getOpcode() == ISD::TRUNCATE &&
2636 N1.getOperand(0).getOpcode() == ISD::AND &&
2637 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2638 SDValue N101 = N1.getOperand(0).getOperand(1);
2639 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2640 MVT TruncVT = N1.getValueType();
2641 SDValue N100 = N1.getOperand(0).getOperand(0);
2642 APInt TruncC = N101C->getAPIntValue();
2643 TruncC.trunc(TruncVT.getSizeInBits());
2644 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
2645 DAG.getNode(ISD::AND, N->getDebugLoc(),
2647 DAG.getNode(ISD::TRUNCATE,
2650 DAG.getConstant(TruncC, TruncVT)));
2654 // Simplify, based on bits shifted out of the LHS.
2655 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2656 return SDValue(N, 0);
2659 // If the sign bit is known to be zero, switch this to a SRL.
2660 if (DAG.SignBitIsZero(N0))
2661 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
2663 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2666 SDValue DAGCombiner::visitSRL(SDNode *N) {
2667 SDValue N0 = N->getOperand(0);
2668 SDValue N1 = N->getOperand(1);
2669 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2670 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2671 MVT VT = N0.getValueType();
2672 unsigned OpSizeInBits = VT.getSizeInBits();
2674 // fold (srl c1, c2) -> c1 >>u c2
2676 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
2677 // fold (srl 0, x) -> 0
2678 if (N0C && N0C->isNullValue())
2680 // fold (srl x, c >= size(x)) -> undef
2681 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2682 return DAG.getUNDEF(VT);
2683 // fold (srl x, 0) -> x
2684 if (N1C && N1C->isNullValue())
2686 // if (srl x, c) is known to be zero, return 0
2687 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2688 APInt::getAllOnesValue(OpSizeInBits)))
2689 return DAG.getConstant(0, VT);
2691 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
2692 if (N1C && N0.getOpcode() == ISD::SRL &&
2693 N0.getOperand(1).getOpcode() == ISD::Constant) {
2694 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2695 uint64_t c2 = N1C->getZExtValue();
2696 if (c1 + c2 > OpSizeInBits)
2697 return DAG.getConstant(0, VT);
2698 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
2699 DAG.getConstant(c1 + c2, N1.getValueType()));
2702 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
2703 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2704 // Shifting in all undef bits?
2705 MVT SmallVT = N0.getOperand(0).getValueType();
2706 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
2707 return DAG.getUNDEF(VT);
2709 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
2710 N0.getOperand(0), N1);
2711 AddToWorkList(SmallShift.getNode());
2712 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
2715 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
2716 // bit, which is unmodified by sra.
2717 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
2718 if (N0.getOpcode() == ISD::SRA)
2719 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
2722 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
2723 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2724 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
2725 APInt KnownZero, KnownOne;
2726 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
2727 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
2729 // If any of the input bits are KnownOne, then the input couldn't be all
2730 // zeros, thus the result of the srl will always be zero.
2731 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
2733 // If all of the bits input the to ctlz node are known to be zero, then
2734 // the result of the ctlz is "32" and the result of the shift is one.
2735 APInt UnknownBits = ~KnownZero & Mask;
2736 if (UnknownBits == 0) return DAG.getConstant(1, VT);
2738 // Otherwise, check to see if there is exactly one bit input to the ctlz.
2739 if ((UnknownBits & (UnknownBits - 1)) == 0) {
2740 // Okay, we know that only that the single bit specified by UnknownBits
2741 // could be set on input to the CTLZ node. If this bit is set, the SRL
2742 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
2743 // to an SRL/XOR pair, which is likely to simplify more.
2744 unsigned ShAmt = UnknownBits.countTrailingZeros();
2745 SDValue Op = N0.getOperand(0);
2748 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
2749 DAG.getConstant(ShAmt, getShiftAmountTy()));
2750 AddToWorkList(Op.getNode());
2753 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
2754 Op, DAG.getConstant(1, VT));
2758 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
2759 if (N1.getOpcode() == ISD::TRUNCATE &&
2760 N1.getOperand(0).getOpcode() == ISD::AND &&
2761 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2762 SDValue N101 = N1.getOperand(0).getOperand(1);
2763 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2764 MVT TruncVT = N1.getValueType();
2765 SDValue N100 = N1.getOperand(0).getOperand(0);
2766 APInt TruncC = N101C->getAPIntValue();
2767 TruncC.trunc(TruncVT.getSizeInBits());
2768 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
2769 DAG.getNode(ISD::AND, N->getDebugLoc(),
2771 DAG.getNode(ISD::TRUNCATE,
2774 DAG.getConstant(TruncC, TruncVT)));
2778 // fold operands of srl based on knowledge that the low bits are not
2780 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2781 return SDValue(N, 0);
2783 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2786 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
2787 SDValue N0 = N->getOperand(0);
2788 MVT VT = N->getValueType(0);
2790 // fold (ctlz c1) -> c2
2791 if (isa<ConstantSDNode>(N0))
2792 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
2796 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
2797 SDValue N0 = N->getOperand(0);
2798 MVT VT = N->getValueType(0);
2800 // fold (cttz c1) -> c2
2801 if (isa<ConstantSDNode>(N0))
2802 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
2806 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
2807 SDValue N0 = N->getOperand(0);
2808 MVT VT = N->getValueType(0);
2810 // fold (ctpop c1) -> c2
2811 if (isa<ConstantSDNode>(N0))
2812 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
2816 SDValue DAGCombiner::visitSELECT(SDNode *N) {
2817 SDValue N0 = N->getOperand(0);
2818 SDValue N1 = N->getOperand(1);
2819 SDValue N2 = N->getOperand(2);
2820 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2821 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2822 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2823 MVT VT = N->getValueType(0);
2824 MVT VT0 = N0.getValueType();
2826 // fold (select C, X, X) -> X
2829 // fold (select true, X, Y) -> X
2830 if (N0C && !N0C->isNullValue())
2832 // fold (select false, X, Y) -> Y
2833 if (N0C && N0C->isNullValue())
2835 // fold (select C, 1, X) -> (or C, X)
2836 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
2837 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
2838 // fold (select C, 0, 1) -> (xor C, 1)
2839 if (VT.isInteger() &&
2842 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
2843 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
2846 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
2847 N0, DAG.getConstant(1, VT0));
2848 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
2849 N0, DAG.getConstant(1, VT0));
2850 AddToWorkList(XORNode.getNode());
2852 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
2853 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
2855 // fold (select C, 0, X) -> (and (not C), X)
2856 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
2857 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
2858 AddToWorkList(NOTNode.getNode());
2859 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
2861 // fold (select C, X, 1) -> (or (not C), X)
2862 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
2863 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
2864 AddToWorkList(NOTNode.getNode());
2865 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
2867 // fold (select C, X, 0) -> (and C, X)
2868 if (VT == MVT::i1 && N2C && N2C->isNullValue())
2869 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
2870 // fold (select X, X, Y) -> (or X, Y)
2871 // fold (select X, 1, Y) -> (or X, Y)
2872 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
2873 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
2874 // fold (select X, Y, X) -> (and X, Y)
2875 // fold (select X, Y, 0) -> (and X, Y)
2876 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
2877 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
2879 // If we can fold this based on the true/false value, do so.
2880 if (SimplifySelectOps(N, N1, N2))
2881 return SDValue(N, 0); // Don't revisit N.
2883 // fold selects based on a setcc into other things, such as min/max/abs
2884 if (N0.getOpcode() == ISD::SETCC) {
2886 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
2887 // having to say they don't support SELECT_CC on every type the DAG knows
2888 // about, since there is no way to mark an opcode illegal at all value types
2889 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other))
2890 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
2891 N0.getOperand(0), N0.getOperand(1),
2892 N1, N2, N0.getOperand(2));
2894 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
2900 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
2901 SDValue N0 = N->getOperand(0);
2902 SDValue N1 = N->getOperand(1);
2903 SDValue N2 = N->getOperand(2);
2904 SDValue N3 = N->getOperand(3);
2905 SDValue N4 = N->getOperand(4);
2906 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
2908 // fold select_cc lhs, rhs, x, x, cc -> x
2912 // Determine if the condition we're dealing with is constant
2913 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
2914 N0, N1, CC, N->getDebugLoc(), false);
2915 if (SCC.getNode()) AddToWorkList(SCC.getNode());
2917 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
2918 if (!SCCC->isNullValue())
2919 return N2; // cond always true -> true val
2921 return N3; // cond always false -> false val
2924 // Fold to a simpler select_cc
2925 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
2926 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
2927 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
2930 // If we can fold this based on the true/false value, do so.
2931 if (SimplifySelectOps(N, N2, N3))
2932 return SDValue(N, 0); // Don't revisit N.
2934 // fold select_cc into other things, such as min/max/abs
2935 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
2938 SDValue DAGCombiner::visitSETCC(SDNode *N) {
2939 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
2940 cast<CondCodeSDNode>(N->getOperand(2))->get(),
2944 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
2945 // "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))"
2946 // transformation. Returns true if extension are possible and the above
2947 // mentioned transformation is profitable.
2948 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
2950 SmallVector<SDNode*, 4> &ExtendNodes,
2951 const TargetLowering &TLI) {
2952 bool HasCopyToRegUses = false;
2953 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
2954 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
2955 UE = N0.getNode()->use_end();
2960 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
2961 if (User->getOpcode() == ISD::SETCC) {
2962 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
2963 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
2964 // Sign bits will be lost after a zext.
2967 for (unsigned i = 0; i != 2; ++i) {
2968 SDValue UseOp = User->getOperand(i);
2971 if (!isa<ConstantSDNode>(UseOp))
2976 ExtendNodes.push_back(User);
2978 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2979 SDValue UseOp = User->getOperand(i);
2981 // If truncate from extended type to original load type is free
2982 // on this target, then it's ok to extend a CopyToReg.
2983 if (isTruncFree && User->getOpcode() == ISD::CopyToReg)
2984 HasCopyToRegUses = true;
2992 if (HasCopyToRegUses) {
2993 bool BothLiveOut = false;
2994 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
2997 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2998 SDValue UseOp = User->getOperand(i);
2999 if (UseOp.getNode() == N && UseOp.getResNo() == 0) {
3006 // Both unextended and extended values are live out. There had better be
3007 // good a reason for the transformation.
3008 return ExtendNodes.size();
3013 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
3014 SDValue N0 = N->getOperand(0);
3015 MVT VT = N->getValueType(0);
3017 // fold (sext c1) -> c1
3018 if (isa<ConstantSDNode>(N0))
3019 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
3021 // fold (sext (sext x)) -> (sext x)
3022 // fold (sext (aext x)) -> (sext x)
3023 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3024 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
3027 if (N0.getOpcode() == ISD::TRUNCATE) {
3028 // fold (sext (truncate (load x))) -> (sext (smaller load x))
3029 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
3030 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3031 if (NarrowLoad.getNode()) {
3032 if (NarrowLoad.getNode() != N0.getNode())
3033 CombineTo(N0.getNode(), NarrowLoad);
3034 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3037 // See if the value being truncated is already sign extended. If so, just
3038 // eliminate the trunc/sext pair.
3039 SDValue Op = N0.getOperand(0);
3040 unsigned OpBits = Op.getValueType().getSizeInBits();
3041 unsigned MidBits = N0.getValueType().getSizeInBits();
3042 unsigned DestBits = VT.getSizeInBits();
3043 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
3045 if (OpBits == DestBits) {
3046 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
3047 // bits, it is already ready.
3048 if (NumSignBits > DestBits-MidBits)
3050 } else if (OpBits < DestBits) {
3051 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
3052 // bits, just sext from i32.
3053 if (NumSignBits > OpBits-MidBits)
3054 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
3056 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
3057 // bits, just truncate to i32.
3058 if (NumSignBits > OpBits-MidBits)
3059 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3062 // fold (sext (truncate x)) -> (sextinreg x).
3063 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
3064 N0.getValueType())) {
3065 if (Op.getValueType().bitsLT(VT))
3066 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
3067 else if (Op.getValueType().bitsGT(VT))
3068 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
3069 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
3070 DAG.getValueType(N0.getValueType()));
3074 // fold (sext (load x)) -> (sext (truncate (sextload x)))
3075 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3076 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3077 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
3078 bool DoXform = true;
3079 SmallVector<SDNode*, 4> SetCCs;
3080 if (!N0.hasOneUse())
3081 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
3083 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3084 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(),
3085 VT, LN0->getChain(),
3086 LN0->getBasePtr(), LN0->getSrcValue(),
3087 LN0->getSrcValueOffset(),
3089 LN0->isVolatile(), LN0->getAlignment());
3090 CombineTo(N, ExtLoad);
3091 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3092 N0.getValueType(), ExtLoad);
3093 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3095 // Extend SetCC uses if necessary.
3096 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3097 SDNode *SetCC = SetCCs[i];
3098 SmallVector<SDValue, 4> Ops;
3100 for (unsigned j = 0; j != 2; ++j) {
3101 SDValue SOp = SetCC->getOperand(j);
3103 Ops.push_back(ExtLoad);
3105 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
3109 Ops.push_back(SetCC->getOperand(2));
3110 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3111 SetCC->getValueType(0),
3112 &Ops[0], Ops.size()));
3115 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3119 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
3120 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
3121 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3122 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3123 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3124 MVT EVT = LN0->getMemoryVT();
3125 if ((!LegalOperations && !LN0->isVolatile()) ||
3126 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) {
3127 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3129 LN0->getBasePtr(), LN0->getSrcValue(),
3130 LN0->getSrcValueOffset(), EVT,
3131 LN0->isVolatile(), LN0->getAlignment());
3132 CombineTo(N, ExtLoad);
3133 CombineTo(N0.getNode(),
3134 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3135 N0.getValueType(), ExtLoad),
3136 ExtLoad.getValue(1));
3137 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3141 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
3142 if (N0.getOpcode() == ISD::SETCC) {
3144 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3145 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
3146 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3147 if (SCC.getNode()) return SCC;
3150 // fold (sext x) -> (zext x) if the sign bit is known zero.
3151 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
3152 DAG.SignBitIsZero(N0))
3153 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3158 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
3159 SDValue N0 = N->getOperand(0);
3160 MVT VT = N->getValueType(0);
3162 // fold (zext c1) -> c1
3163 if (isa<ConstantSDNode>(N0))
3164 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3165 // fold (zext (zext x)) -> (zext x)
3166 // fold (zext (aext x)) -> (zext x)
3167 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3168 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
3171 // fold (zext (truncate (load x))) -> (zext (smaller load x))
3172 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
3173 if (N0.getOpcode() == ISD::TRUNCATE) {
3174 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3175 if (NarrowLoad.getNode()) {
3176 if (NarrowLoad.getNode() != N0.getNode())
3177 CombineTo(N0.getNode(), NarrowLoad);
3178 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3182 // fold (zext (truncate x)) -> (and x, mask)
3183 if (N0.getOpcode() == ISD::TRUNCATE &&
3184 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
3185 SDValue Op = N0.getOperand(0);
3186 if (Op.getValueType().bitsLT(VT)) {
3187 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
3188 } else if (Op.getValueType().bitsGT(VT)) {
3189 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3191 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType());
3194 // fold (zext (and (trunc x), cst)) -> (and x, cst).
3195 if (N0.getOpcode() == ISD::AND &&
3196 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3197 N0.getOperand(1).getOpcode() == ISD::Constant) {
3198 SDValue X = N0.getOperand(0).getOperand(0);
3199 if (X.getValueType().bitsLT(VT)) {
3200 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
3201 } else if (X.getValueType().bitsGT(VT)) {
3202 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
3204 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3205 Mask.zext(VT.getSizeInBits());
3206 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3207 X, DAG.getConstant(Mask, VT));
3210 // fold (zext (load x)) -> (zext (truncate (zextload x)))
3211 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3212 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3213 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
3214 bool DoXform = true;
3215 SmallVector<SDNode*, 4> SetCCs;
3216 if (!N0.hasOneUse())
3217 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
3219 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3220 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3222 LN0->getBasePtr(), LN0->getSrcValue(),
3223 LN0->getSrcValueOffset(),
3225 LN0->isVolatile(), LN0->getAlignment());
3226 CombineTo(N, ExtLoad);
3227 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3228 N0.getValueType(), ExtLoad);
3229 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3231 // Extend SetCC uses if necessary.
3232 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3233 SDNode *SetCC = SetCCs[i];
3234 SmallVector<SDValue, 4> Ops;
3236 for (unsigned j = 0; j != 2; ++j) {
3237 SDValue SOp = SetCC->getOperand(j);
3239 Ops.push_back(ExtLoad);
3241 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND,
3242 N->getDebugLoc(), VT, SOp));
3245 Ops.push_back(SetCC->getOperand(2));
3246 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3247 SetCC->getValueType(0),
3248 &Ops[0], Ops.size()));
3251 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3255 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
3256 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
3257 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3258 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3259 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3260 MVT EVT = LN0->getMemoryVT();
3261 if ((!LegalOperations && !LN0->isVolatile()) ||
3262 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) {
3263 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3265 LN0->getBasePtr(), LN0->getSrcValue(),
3266 LN0->getSrcValueOffset(), EVT,
3267 LN0->isVolatile(), LN0->getAlignment());
3268 CombineTo(N, ExtLoad);
3269 CombineTo(N0.getNode(),
3270 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
3272 ExtLoad.getValue(1));
3273 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3277 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3278 if (N0.getOpcode() == ISD::SETCC) {
3280 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3281 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3282 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3283 if (SCC.getNode()) return SCC;
3289 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
3290 SDValue N0 = N->getOperand(0);
3291 MVT VT = N->getValueType(0);
3293 // fold (aext c1) -> c1
3294 if (isa<ConstantSDNode>(N0))
3295 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
3296 // fold (aext (aext x)) -> (aext x)
3297 // fold (aext (zext x)) -> (zext x)
3298 // fold (aext (sext x)) -> (sext x)
3299 if (N0.getOpcode() == ISD::ANY_EXTEND ||
3300 N0.getOpcode() == ISD::ZERO_EXTEND ||
3301 N0.getOpcode() == ISD::SIGN_EXTEND)
3302 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
3304 // fold (aext (truncate (load x))) -> (aext (smaller load x))
3305 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
3306 if (N0.getOpcode() == ISD::TRUNCATE) {
3307 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3308 if (NarrowLoad.getNode()) {
3309 if (NarrowLoad.getNode() != N0.getNode())
3310 CombineTo(N0.getNode(), NarrowLoad);
3311 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3315 // fold (aext (truncate x))
3316 if (N0.getOpcode() == ISD::TRUNCATE) {
3317 SDValue TruncOp = N0.getOperand(0);
3318 if (TruncOp.getValueType() == VT)
3319 return TruncOp; // x iff x size == zext size.
3320 if (TruncOp.getValueType().bitsGT(VT))
3321 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
3322 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
3325 // fold (aext (and (trunc x), cst)) -> (and x, cst).
3326 if (N0.getOpcode() == ISD::AND &&
3327 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3328 N0.getOperand(1).getOpcode() == ISD::Constant) {
3329 SDValue X = N0.getOperand(0).getOperand(0);
3330 if (X.getValueType().bitsLT(VT)) {
3331 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
3332 } else if (X.getValueType().bitsGT(VT)) {
3333 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
3335 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3336 Mask.zext(VT.getSizeInBits());
3337 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3338 X, DAG.getConstant(Mask, VT));
3341 // fold (aext (load x)) -> (aext (truncate (extload x)))
3342 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
3343 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3344 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
3345 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3346 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
3348 LN0->getBasePtr(), LN0->getSrcValue(),
3349 LN0->getSrcValueOffset(),
3351 LN0->isVolatile(), LN0->getAlignment());
3352 CombineTo(N, ExtLoad);
3353 // Redirect any chain users to the new load.
3354 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1),
3355 SDValue(ExtLoad.getNode(), 1));
3356 // If any node needs the original loaded value, recompute it.
3357 if (!LN0->use_empty())
3358 CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3359 N0.getValueType(), ExtLoad),
3360 ExtLoad.getValue(1));
3361 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3364 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
3365 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
3366 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
3367 if (N0.getOpcode() == ISD::LOAD &&
3368 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3370 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3371 MVT EVT = LN0->getMemoryVT();
3372 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
3373 VT, LN0->getChain(), LN0->getBasePtr(),
3375 LN0->getSrcValueOffset(), EVT,
3376 LN0->isVolatile(), LN0->getAlignment());
3377 CombineTo(N, ExtLoad);
3378 CombineTo(N0.getNode(),
3379 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3380 N0.getValueType(), ExtLoad),
3381 ExtLoad.getValue(1));
3382 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3385 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3386 if (N0.getOpcode() == ISD::SETCC) {
3388 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3389 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3390 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3398 /// GetDemandedBits - See if the specified operand can be simplified with the
3399 /// knowledge that only the bits specified by Mask are used. If so, return the
3400 /// simpler operand, otherwise return a null SDValue.
3401 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
3402 switch (V.getOpcode()) {
3406 // If the LHS or RHS don't contribute bits to the or, drop them.
3407 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
3408 return V.getOperand(1);
3409 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
3410 return V.getOperand(0);
3413 // Only look at single-use SRLs.
3414 if (!V.getNode()->hasOneUse())
3416 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
3417 // See if we can recursively simplify the LHS.
3418 unsigned Amt = RHSC->getZExtValue();
3420 // Watch out for shift count overflow though.
3421 if (Amt >= Mask.getBitWidth()) break;
3422 APInt NewMask = Mask << Amt;
3423 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
3424 if (SimplifyLHS.getNode())
3425 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
3426 SimplifyLHS, V.getOperand(1));
3432 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
3433 /// bits and then truncated to a narrower type and where N is a multiple
3434 /// of number of bits of the narrower type, transform it to a narrower load
3435 /// from address + N / num of bits of new type. If the result is to be
3436 /// extended, also fold the extension to form a extending load.
3437 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
3438 unsigned Opc = N->getOpcode();
3439 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
3440 SDValue N0 = N->getOperand(0);
3441 MVT VT = N->getValueType(0);
3444 // This transformation isn't valid for vector loads.
3448 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
3450 if (Opc == ISD::SIGN_EXTEND_INREG) {
3451 ExtType = ISD::SEXTLOAD;
3452 EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3453 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))
3457 unsigned EVTBits = EVT.getSizeInBits();
3459 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
3460 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3461 ShAmt = N01->getZExtValue();
3462 // Is the shift amount a multiple of size of VT?
3463 if ((ShAmt & (EVTBits-1)) == 0) {
3464 N0 = N0.getOperand(0);
3465 if (N0.getValueType().getSizeInBits() <= EVTBits)
3471 // Do not generate loads of non-round integer types since these can
3472 // be expensive (and would be wrong if the type is not byte sized).
3473 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() &&
3474 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits &&
3475 // Do not change the width of a volatile load.
3476 !cast<LoadSDNode>(N0)->isVolatile()) {
3477 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3478 MVT PtrType = N0.getOperand(1).getValueType();
3480 // For big endian targets, we need to adjust the offset to the pointer to
3481 // load the correct bytes.
3482 if (TLI.isBigEndian()) {
3483 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
3484 unsigned EVTStoreBits = EVT.getStoreSizeInBits();
3485 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
3488 uint64_t PtrOff = ShAmt / 8;
3489 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
3490 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
3491 PtrType, LN0->getBasePtr(),
3492 DAG.getConstant(PtrOff, PtrType));
3493 AddToWorkList(NewPtr.getNode());
3495 SDValue Load = (ExtType == ISD::NON_EXTLOAD)
3496 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
3497 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
3498 LN0->isVolatile(), NewAlign)
3499 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr,
3500 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
3501 EVT, LN0->isVolatile(), NewAlign);
3503 // Replace the old load's chain with the new load's chain.
3504 WorkListRemover DeadNodes(*this);
3505 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
3508 // Return the new loaded value.
3515 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
3516 SDValue N0 = N->getOperand(0);
3517 SDValue N1 = N->getOperand(1);
3518 MVT VT = N->getValueType(0);
3519 MVT EVT = cast<VTSDNode>(N1)->getVT();
3520 unsigned VTBits = VT.getSizeInBits();
3521 unsigned EVTBits = EVT.getSizeInBits();
3523 // fold (sext_in_reg c1) -> c1
3524 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
3525 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
3527 // If the input is already sign extended, just drop the extension.
3528 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1)
3531 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
3532 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3533 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
3534 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3535 N0.getOperand(0), N1);
3538 // fold (sext_in_reg (sext x)) -> (sext x)
3539 // fold (sext_in_reg (aext x)) -> (sext x)
3540 // if x is small enough.
3541 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
3542 SDValue N00 = N0.getOperand(0);
3543 if (N00.getValueType().getSizeInBits() < EVTBits)
3544 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
3547 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
3548 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
3549 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
3551 // fold operands of sext_in_reg based on knowledge that the top bits are not
3553 if (SimplifyDemandedBits(SDValue(N, 0)))
3554 return SDValue(N, 0);
3556 // fold (sext_in_reg (load x)) -> (smaller sextload x)
3557 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
3558 SDValue NarrowLoad = ReduceLoadWidth(N);
3559 if (NarrowLoad.getNode())
3562 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
3563 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
3564 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
3565 if (N0.getOpcode() == ISD::SRL) {
3566 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
3567 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) {
3568 // We can turn this into an SRA iff the input to the SRL is already sign
3570 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
3571 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
3572 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
3573 N0.getOperand(0), N0.getOperand(1));
3577 // fold (sext_inreg (extload x)) -> (sextload x)
3578 if (ISD::isEXTLoad(N0.getNode()) &&
3579 ISD::isUNINDEXEDLoad(N0.getNode()) &&
3580 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3581 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3582 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
3583 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3584 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3586 LN0->getBasePtr(), LN0->getSrcValue(),
3587 LN0->getSrcValueOffset(), EVT,
3588 LN0->isVolatile(), LN0->getAlignment());
3589 CombineTo(N, ExtLoad);
3590 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3591 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3593 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
3594 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3596 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3597 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3598 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
3599 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3600 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3602 LN0->getBasePtr(), LN0->getSrcValue(),
3603 LN0->getSrcValueOffset(), EVT,
3604 LN0->isVolatile(), LN0->getAlignment());
3605 CombineTo(N, ExtLoad);
3606 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3607 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3612 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
3613 SDValue N0 = N->getOperand(0);
3614 MVT VT = N->getValueType(0);
3617 if (N0.getValueType() == N->getValueType(0))
3619 // fold (truncate c1) -> c1
3620 if (isa<ConstantSDNode>(N0))
3621 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
3622 // fold (truncate (truncate x)) -> (truncate x)
3623 if (N0.getOpcode() == ISD::TRUNCATE)
3624 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
3625 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
3626 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
3627 N0.getOpcode() == ISD::ANY_EXTEND) {
3628 if (N0.getOperand(0).getValueType().bitsLT(VT))
3629 // if the source is smaller than the dest, we still need an extend
3630 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
3632 else if (N0.getOperand(0).getValueType().bitsGT(VT))
3633 // if the source is larger than the dest, than we just need the truncate
3634 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
3636 // if the source and dest are the same type, we can drop both the extend
3638 return N0.getOperand(0);
3641 // See if we can simplify the input to this truncate through knowledge that
3642 // only the low bits are being used. For example "trunc (or (shl x, 8), y)"
3645 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
3646 VT.getSizeInBits()));
3647 if (Shorter.getNode())
3648 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
3650 // fold (truncate (load x)) -> (smaller load x)
3651 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
3652 return ReduceLoadWidth(N);
3655 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
3656 SDValue Elt = N->getOperand(i);
3657 if (Elt.getOpcode() != ISD::MERGE_VALUES)
3658 return Elt.getNode();
3659 return Elt.getOperand(Elt.getResNo()).getNode();
3662 /// CombineConsecutiveLoads - build_pair (load, load) -> load
3663 /// if load locations are consecutive.
3664 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) {
3665 assert(N->getOpcode() == ISD::BUILD_PAIR);
3667 SDNode *LD1 = getBuildPairElt(N, 0);
3668 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse())
3670 MVT LD1VT = LD1->getValueType(0);
3671 SDNode *LD2 = getBuildPairElt(N, 1);
3672 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3674 if (ISD::isNON_EXTLoad(LD2) &&
3676 // If both are volatile this would reduce the number of volatile loads.
3677 // If one is volatile it might be ok, but play conservative and bail out.
3678 !cast<LoadSDNode>(LD1)->isVolatile() &&
3679 !cast<LoadSDNode>(LD2)->isVolatile() &&
3680 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) {
3681 LoadSDNode *LD = cast<LoadSDNode>(LD1);
3682 unsigned Align = LD->getAlignment();
3683 unsigned NewAlign = TLI.getTargetData()->
3684 getABITypeAlignment(VT.getTypeForMVT());
3686 if (NewAlign <= Align &&
3687 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
3688 return DAG.getLoad(VT, N->getDebugLoc(), LD->getChain(), LD->getBasePtr(),
3689 LD->getSrcValue(), LD->getSrcValueOffset(),
3696 SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
3697 SDValue N0 = N->getOperand(0);
3698 MVT VT = N->getValueType(0);
3700 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
3701 // Only do this before legalize, since afterward the target may be depending
3702 // on the bitconvert.
3703 // First check to see if this is all constant.
3705 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
3707 bool isSimple = true;
3708 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
3709 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
3710 N0.getOperand(i).getOpcode() != ISD::Constant &&
3711 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
3716 MVT DestEltVT = N->getValueType(0).getVectorElementType();
3717 assert(!DestEltVT.isVector() &&
3718 "Element type of vector ValueType must not be vector!");
3720 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT);
3723 // If the input is a constant, let getNode fold it.
3724 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
3725 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0);
3726 if (Res.getNode() != N) return Res;
3729 // (conv (conv x, t1), t2) -> (conv x, t2)
3730 if (N0.getOpcode() == ISD::BIT_CONVERT)
3731 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT,
3734 // fold (conv (load x)) -> (load (conv*)x)
3735 // If the resultant load doesn't need a higher alignment than the original!
3736 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
3737 // Do not change the width of a volatile load.
3738 !cast<LoadSDNode>(N0)->isVolatile() &&
3739 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
3740 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3741 unsigned Align = TLI.getTargetData()->
3742 getABITypeAlignment(VT.getTypeForMVT());
3743 unsigned OrigAlign = LN0->getAlignment();
3745 if (Align <= OrigAlign) {
3746 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
3748 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3749 LN0->isVolatile(), OrigAlign);
3751 CombineTo(N0.getNode(),
3752 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
3753 N0.getValueType(), Load),
3759 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
3760 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
3761 // This often reduces constant pool loads.
3762 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
3763 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
3764 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT,
3766 AddToWorkList(NewConv.getNode());
3768 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
3769 if (N0.getOpcode() == ISD::FNEG)
3770 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3771 NewConv, DAG.getConstant(SignBit, VT));
3772 assert(N0.getOpcode() == ISD::FABS);
3773 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3774 NewConv, DAG.getConstant(~SignBit, VT));
3777 // fold (bitconvert (fcopysign cst, x)) ->
3778 // (or (and (bitconvert x), sign), (and cst, (not sign)))
3779 // Note that we don't handle (copysign x, cst) because this can always be
3780 // folded to an fneg or fabs.
3781 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
3782 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
3783 VT.isInteger() && !VT.isVector()) {
3784 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
3785 MVT IntXVT = MVT::getIntegerVT(OrigXWidth);
3786 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) {
3787 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
3788 IntXVT, N0.getOperand(1));
3789 AddToWorkList(X.getNode());
3791 // If X has a different width than the result/lhs, sext it or truncate it.
3792 unsigned VTWidth = VT.getSizeInBits();
3793 if (OrigXWidth < VTWidth) {
3794 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
3795 AddToWorkList(X.getNode());
3796 } else if (OrigXWidth > VTWidth) {
3797 // To get the sign bit in the right place, we have to shift it right
3798 // before truncating.
3799 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
3800 X.getValueType(), X,
3801 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
3802 AddToWorkList(X.getNode());
3803 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
3804 AddToWorkList(X.getNode());
3807 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
3808 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
3809 X, DAG.getConstant(SignBit, VT));
3810 AddToWorkList(X.getNode());
3812 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
3813 VT, N0.getOperand(0));
3814 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
3815 Cst, DAG.getConstant(~SignBit, VT));
3816 AddToWorkList(Cst.getNode());
3818 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
3822 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
3823 if (N0.getOpcode() == ISD::BUILD_PAIR) {
3824 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
3825 if (CombineLD.getNode())
3832 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
3833 MVT VT = N->getValueType(0);
3834 return CombineConsecutiveLoads(N, VT);
3837 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
3838 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
3839 /// destination element value type.
3840 SDValue DAGCombiner::
3841 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) {
3842 MVT SrcEltVT = BV->getOperand(0).getValueType();
3844 // If this is already the right type, we're done.
3845 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
3847 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
3848 unsigned DstBitSize = DstEltVT.getSizeInBits();
3850 // If this is a conversion of N elements of one type to N elements of another
3851 // type, convert each element. This handles FP<->INT cases.
3852 if (SrcBitSize == DstBitSize) {
3853 SmallVector<SDValue, 8> Ops;
3854 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3855 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(),
3856 DstEltVT, BV->getOperand(i)));
3857 AddToWorkList(Ops.back().getNode());
3859 MVT VT = MVT::getVectorVT(DstEltVT,
3860 BV->getValueType(0).getVectorNumElements());
3861 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
3862 &Ops[0], Ops.size());
3865 // Otherwise, we're growing or shrinking the elements. To avoid having to
3866 // handle annoying details of growing/shrinking FP values, we convert them to
3868 if (SrcEltVT.isFloatingPoint()) {
3869 // Convert the input float vector to a int vector where the elements are the
3871 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
3872 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits());
3873 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
3877 // Now we know the input is an integer vector. If the output is a FP type,
3878 // convert to integer first, then to FP of the right size.
3879 if (DstEltVT.isFloatingPoint()) {
3880 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
3881 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits());
3882 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
3884 // Next, convert to FP elements of the same size.
3885 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
3888 // Okay, we know the src/dst types are both integers of differing types.
3889 // Handling growing first.
3890 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
3891 if (SrcBitSize < DstBitSize) {
3892 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
3894 SmallVector<SDValue, 8> Ops;
3895 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
3896 i += NumInputsPerOutput) {
3897 bool isLE = TLI.isLittleEndian();
3898 APInt NewBits = APInt(DstBitSize, 0);
3899 bool EltIsUndef = true;
3900 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
3901 // Shift the previously computed bits over.
3902 NewBits <<= SrcBitSize;
3903 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
3904 if (Op.getOpcode() == ISD::UNDEF) continue;
3908 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize);
3912 Ops.push_back(DAG.getUNDEF(DstEltVT));
3914 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
3917 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size());
3918 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
3919 &Ops[0], Ops.size());
3922 // Finally, this must be the case where we are shrinking elements: each input
3923 // turns into multiple outputs.
3924 bool isS2V = ISD::isScalarToVector(BV);
3925 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
3926 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands());
3927 SmallVector<SDValue, 8> Ops;
3929 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3930 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
3931 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
3932 Ops.push_back(DAG.getUNDEF(DstEltVT));
3936 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue();
3938 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
3939 APInt ThisVal = APInt(OpVal).trunc(DstBitSize);
3940 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
3941 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal)
3942 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
3943 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
3945 OpVal = OpVal.lshr(DstBitSize);
3948 // For big endian targets, swap the order of the pieces of each element.
3949 if (TLI.isBigEndian())
3950 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
3953 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
3954 &Ops[0], Ops.size());
3957 SDValue DAGCombiner::visitFADD(SDNode *N) {
3958 SDValue N0 = N->getOperand(0);
3959 SDValue N1 = N->getOperand(1);
3960 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3961 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3962 MVT VT = N->getValueType(0);
3965 if (VT.isVector()) {
3966 SDValue FoldedVOp = SimplifyVBinOp(N);
3967 if (FoldedVOp.getNode()) return FoldedVOp;
3970 // fold (fadd c1, c2) -> (fadd c1, c2)
3971 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3972 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
3973 // canonicalize constant to RHS
3974 if (N0CFP && !N1CFP)
3975 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
3976 // fold (fadd A, 0) -> A
3977 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
3979 // fold (fadd A, (fneg B)) -> (fsub A, B)
3980 if (isNegatibleForFree(N1, LegalOperations) == 2)
3981 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
3982 GetNegatedExpression(N1, DAG, LegalOperations));
3983 // fold (fadd (fneg A), B) -> (fsub B, A)
3984 if (isNegatibleForFree(N0, LegalOperations) == 2)
3985 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
3986 GetNegatedExpression(N0, DAG, LegalOperations));
3988 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
3989 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
3990 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3991 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
3992 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
3993 N0.getOperand(1), N1));
3998 SDValue DAGCombiner::visitFSUB(SDNode *N) {
3999 SDValue N0 = N->getOperand(0);
4000 SDValue N1 = N->getOperand(1);
4001 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4002 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4003 MVT VT = N->getValueType(0);
4006 if (VT.isVector()) {
4007 SDValue FoldedVOp = SimplifyVBinOp(N);
4008 if (FoldedVOp.getNode()) return FoldedVOp;
4011 // fold (fsub c1, c2) -> c1-c2
4012 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4013 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
4014 // fold (fsub A, 0) -> A
4015 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4017 // fold (fsub 0, B) -> -B
4018 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
4019 if (isNegatibleForFree(N1, LegalOperations))
4020 return GetNegatedExpression(N1, DAG, LegalOperations);
4021 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4022 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
4024 // fold (fsub A, (fneg B)) -> (fadd A, B)
4025 if (isNegatibleForFree(N1, LegalOperations))
4026 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
4027 GetNegatedExpression(N1, DAG, LegalOperations));
4032 SDValue DAGCombiner::visitFMUL(SDNode *N) {
4033 SDValue N0 = N->getOperand(0);
4034 SDValue N1 = N->getOperand(1);
4035 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4036 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4037 MVT VT = N->getValueType(0);
4040 if (VT.isVector()) {
4041 SDValue FoldedVOp = SimplifyVBinOp(N);
4042 if (FoldedVOp.getNode()) return FoldedVOp;
4045 // fold (fmul c1, c2) -> c1*c2
4046 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4047 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
4048 // canonicalize constant to RHS
4049 if (N0CFP && !N1CFP)
4050 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
4051 // fold (fmul A, 0) -> 0
4052 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4054 // fold (fmul X, 2.0) -> (fadd X, X)
4055 if (N1CFP && N1CFP->isExactlyValue(+2.0))
4056 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
4057 // fold (fmul X, (fneg 1.0)) -> (fneg X)
4058 if (N1CFP && N1CFP->isExactlyValue(-1.0))
4059 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4060 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
4062 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
4063 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4064 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4065 // Both can be negated for free, check to see if at least one is cheaper
4067 if (LHSNeg == 2 || RHSNeg == 2)
4068 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4069 GetNegatedExpression(N0, DAG, LegalOperations),
4070 GetNegatedExpression(N1, DAG, LegalOperations));
4074 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
4075 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
4076 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4077 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
4078 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4079 N0.getOperand(1), N1));
4084 SDValue DAGCombiner::visitFDIV(SDNode *N) {
4085 SDValue N0 = N->getOperand(0);
4086 SDValue N1 = N->getOperand(1);
4087 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4088 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4089 MVT VT = N->getValueType(0);
4092 if (VT.isVector()) {
4093 SDValue FoldedVOp = SimplifyVBinOp(N);
4094 if (FoldedVOp.getNode()) return FoldedVOp;
4097 // fold (fdiv c1, c2) -> c1/c2
4098 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4099 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
4102 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
4103 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4104 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4105 // Both can be negated for free, check to see if at least one is cheaper
4107 if (LHSNeg == 2 || RHSNeg == 2)
4108 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
4109 GetNegatedExpression(N0, DAG, LegalOperations),
4110 GetNegatedExpression(N1, DAG, LegalOperations));
4117 SDValue DAGCombiner::visitFREM(SDNode *N) {
4118 SDValue N0 = N->getOperand(0);
4119 SDValue N1 = N->getOperand(1);
4120 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4121 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4122 MVT VT = N->getValueType(0);
4124 // fold (frem c1, c2) -> fmod(c1,c2)
4125 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4126 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
4131 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
4132 SDValue N0 = N->getOperand(0);
4133 SDValue N1 = N->getOperand(1);
4134 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4135 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4136 MVT VT = N->getValueType(0);
4138 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
4139 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
4142 const APFloat& V = N1CFP->getValueAPF();
4143 // copysign(x, c1) -> fabs(x) iff ispos(c1)
4144 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
4145 if (!V.isNegative()) {
4146 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
4147 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4149 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4150 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
4151 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
4155 // copysign(fabs(x), y) -> copysign(x, y)
4156 // copysign(fneg(x), y) -> copysign(x, y)
4157 // copysign(copysign(x,z), y) -> copysign(x, y)
4158 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
4159 N0.getOpcode() == ISD::FCOPYSIGN)
4160 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4161 N0.getOperand(0), N1);
4163 // copysign(x, abs(y)) -> abs(x)
4164 if (N1.getOpcode() == ISD::FABS)
4165 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4167 // copysign(x, copysign(y,z)) -> copysign(x, z)
4168 if (N1.getOpcode() == ISD::FCOPYSIGN)
4169 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4170 N0, N1.getOperand(1));
4172 // copysign(x, fp_extend(y)) -> copysign(x, y)
4173 // copysign(x, fp_round(y)) -> copysign(x, y)
4174 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
4175 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4176 N0, N1.getOperand(0));
4181 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
4182 SDValue N0 = N->getOperand(0);
4183 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4184 MVT VT = N->getValueType(0);
4185 MVT OpVT = N0.getValueType();
4187 // fold (sint_to_fp c1) -> c1fp
4188 if (N0C && OpVT != MVT::ppcf128)
4189 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4191 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
4192 // but UINT_TO_FP is legal on this target, try to convert.
4193 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
4194 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
4195 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
4196 if (DAG.SignBitIsZero(N0))
4197 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4203 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
4204 SDValue N0 = N->getOperand(0);
4205 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4206 MVT VT = N->getValueType(0);
4207 MVT OpVT = N0.getValueType();
4209 // fold (uint_to_fp c1) -> c1fp
4210 if (N0C && OpVT != MVT::ppcf128)
4211 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4213 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
4214 // but SINT_TO_FP is legal on this target, try to convert.
4215 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
4216 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
4217 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
4218 if (DAG.SignBitIsZero(N0))
4219 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4225 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
4226 SDValue N0 = N->getOperand(0);
4227 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4228 MVT VT = N->getValueType(0);
4230 // fold (fp_to_sint c1fp) -> c1
4232 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
4237 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
4238 SDValue N0 = N->getOperand(0);
4239 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4240 MVT VT = N->getValueType(0);
4242 // fold (fp_to_uint c1fp) -> c1
4243 if (N0CFP && VT != MVT::ppcf128)
4244 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
4249 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
4250 SDValue N0 = N->getOperand(0);
4251 SDValue N1 = N->getOperand(1);
4252 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4253 MVT VT = N->getValueType(0);
4255 // fold (fp_round c1fp) -> c1fp
4256 if (N0CFP && N0.getValueType() != MVT::ppcf128)
4257 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
4259 // fold (fp_round (fp_extend x)) -> x
4260 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
4261 return N0.getOperand(0);
4263 // fold (fp_round (fp_round x)) -> (fp_round x)
4264 if (N0.getOpcode() == ISD::FP_ROUND) {
4265 // This is a value preserving truncation if both round's are.
4266 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
4267 N0.getNode()->getConstantOperandVal(1) == 1;
4268 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
4269 DAG.getIntPtrConstant(IsTrunc));
4272 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
4273 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
4274 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
4275 N0.getOperand(0), N1);
4276 AddToWorkList(Tmp.getNode());
4277 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4278 Tmp, N0.getOperand(1));
4284 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
4285 SDValue N0 = N->getOperand(0);
4286 MVT VT = N->getValueType(0);
4287 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4288 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4290 // fold (fp_round_inreg c1fp) -> c1fp
4291 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) {
4292 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
4293 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
4299 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
4300 SDValue N0 = N->getOperand(0);
4301 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4302 MVT VT = N->getValueType(0);
4304 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
4305 if (N->hasOneUse() &&
4306 N->use_begin()->getOpcode() == ISD::FP_ROUND)
4309 // fold (fp_extend c1fp) -> c1fp
4310 if (N0CFP && VT != MVT::ppcf128)
4311 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
4313 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
4315 if (N0.getOpcode() == ISD::FP_ROUND
4316 && N0.getNode()->getConstantOperandVal(1) == 1) {
4317 SDValue In = N0.getOperand(0);
4318 if (In.getValueType() == VT) return In;
4319 if (VT.bitsLT(In.getValueType()))
4320 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
4321 In, N0.getOperand(1));
4322 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
4325 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
4326 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
4327 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4328 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4329 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4330 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4332 LN0->getBasePtr(), LN0->getSrcValue(),
4333 LN0->getSrcValueOffset(),
4335 LN0->isVolatile(), LN0->getAlignment());
4336 CombineTo(N, ExtLoad);
4337 CombineTo(N0.getNode(),
4338 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
4339 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
4340 ExtLoad.getValue(1));
4341 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4347 SDValue DAGCombiner::visitFNEG(SDNode *N) {
4348 SDValue N0 = N->getOperand(0);
4350 if (isNegatibleForFree(N0, LegalOperations))
4351 return GetNegatedExpression(N0, DAG, LegalOperations);
4353 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
4354 // constant pool values.
4355 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
4356 N0.getOperand(0).getValueType().isInteger() &&
4357 !N0.getOperand(0).getValueType().isVector()) {
4358 SDValue Int = N0.getOperand(0);
4359 MVT IntVT = Int.getValueType();
4360 if (IntVT.isInteger() && !IntVT.isVector()) {
4361 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
4362 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
4363 AddToWorkList(Int.getNode());
4364 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4365 N->getValueType(0), Int);
4372 SDValue DAGCombiner::visitFABS(SDNode *N) {
4373 SDValue N0 = N->getOperand(0);
4374 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4375 MVT VT = N->getValueType(0);
4377 // fold (fabs c1) -> fabs(c1)
4378 if (N0CFP && VT != MVT::ppcf128)
4379 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4380 // fold (fabs (fabs x)) -> (fabs x)
4381 if (N0.getOpcode() == ISD::FABS)
4382 return N->getOperand(0);
4383 // fold (fabs (fneg x)) -> (fabs x)
4384 // fold (fabs (fcopysign x, y)) -> (fabs x)
4385 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
4386 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
4388 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
4389 // constant pool values.
4390 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
4391 N0.getOperand(0).getValueType().isInteger() &&
4392 !N0.getOperand(0).getValueType().isVector()) {
4393 SDValue Int = N0.getOperand(0);
4394 MVT IntVT = Int.getValueType();
4395 if (IntVT.isInteger() && !IntVT.isVector()) {
4396 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
4397 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
4398 AddToWorkList(Int.getNode());
4399 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4400 N->getValueType(0), Int);
4407 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
4408 SDValue Chain = N->getOperand(0);
4409 SDValue N1 = N->getOperand(1);
4410 SDValue N2 = N->getOperand(2);
4411 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4413 // never taken branch, fold to chain
4414 if (N1C && N1C->isNullValue())
4416 // unconditional branch
4417 if (N1C && N1C->getAPIntValue() == 1)
4418 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2);
4419 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
4421 if (N1.getOpcode() == ISD::SETCC &&
4422 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
4423 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
4424 Chain, N1.getOperand(2),
4425 N1.getOperand(0), N1.getOperand(1), N2);
4431 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
4433 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
4434 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
4435 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
4437 // Use SimplifySetCC to simplify SETCC's.
4438 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
4439 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
4441 if (Simp.getNode()) AddToWorkList(Simp.getNode());
4443 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode());
4445 // fold br_cc true, dest -> br dest (unconditional branch)
4446 if (SCCC && !SCCC->isNullValue())
4447 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other,
4448 N->getOperand(0), N->getOperand(4));
4449 // fold br_cc false, dest -> unconditional fall through
4450 if (SCCC && SCCC->isNullValue())
4451 return N->getOperand(0);
4453 // fold to a simpler setcc
4454 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
4455 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
4456 N->getOperand(0), Simp.getOperand(2),
4457 Simp.getOperand(0), Simp.getOperand(1),
4463 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
4464 /// pre-indexed load / store when the base pointer is an add or subtract
4465 /// and it has other uses besides the load / store. After the
4466 /// transformation, the new indexed load / store has effectively folded
4467 /// the add / subtract in and all of its other uses are redirected to the
4468 /// new load / store.
4469 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
4470 if (!LegalOperations)
4476 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4477 if (LD->isIndexed())
4479 VT = LD->getMemoryVT();
4480 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
4481 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
4483 Ptr = LD->getBasePtr();
4484 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4485 if (ST->isIndexed())
4487 VT = ST->getMemoryVT();
4488 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
4489 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
4491 Ptr = ST->getBasePtr();
4497 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
4498 // out. There is no reason to make this a preinc/predec.
4499 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
4500 Ptr.getNode()->hasOneUse())
4503 // Ask the target to do addressing mode selection.
4506 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4507 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
4509 // Don't create a indexed load / store with zero offset.
4510 if (isa<ConstantSDNode>(Offset) &&
4511 cast<ConstantSDNode>(Offset)->isNullValue())
4514 // Try turning it into a pre-indexed load / store except when:
4515 // 1) The new base ptr is a frame index.
4516 // 2) If N is a store and the new base ptr is either the same as or is a
4517 // predecessor of the value being stored.
4518 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
4519 // that would create a cycle.
4520 // 4) All uses are load / store ops that use it as old base ptr.
4522 // Check #1. Preinc'ing a frame index would require copying the stack pointer
4523 // (plus the implicit offset) to a register to preinc anyway.
4524 if (isa<FrameIndexSDNode>(BasePtr))
4529 SDValue Val = cast<StoreSDNode>(N)->getValue();
4530 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
4534 // Now check for #3 and #4.
4535 bool RealUse = false;
4536 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
4537 E = Ptr.getNode()->use_end(); I != E; ++I) {
4541 if (Use->isPredecessorOf(N))
4544 if (!((Use->getOpcode() == ISD::LOAD &&
4545 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
4546 (Use->getOpcode() == ISD::STORE &&
4547 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
4556 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
4557 BasePtr, Offset, AM);
4559 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
4560 BasePtr, Offset, AM);
4563 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
4564 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
4566 WorkListRemover DeadNodes(*this);
4568 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
4570 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
4573 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
4577 // Finally, since the node is now dead, remove it from the graph.
4580 // Replace the uses of Ptr with uses of the updated base value.
4581 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
4583 removeFromWorkList(Ptr.getNode());
4584 DAG.DeleteNode(Ptr.getNode());
4589 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
4590 /// add / sub of the base pointer node into a post-indexed load / store.
4591 /// The transformation folded the add / subtract into the new indexed
4592 /// load / store effectively and all of its uses are redirected to the
4593 /// new load / store.
4594 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
4595 if (!LegalOperations)
4601 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4602 if (LD->isIndexed())
4604 VT = LD->getMemoryVT();
4605 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
4606 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
4608 Ptr = LD->getBasePtr();
4609 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4610 if (ST->isIndexed())
4612 VT = ST->getMemoryVT();
4613 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
4614 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
4616 Ptr = ST->getBasePtr();
4622 if (Ptr.getNode()->hasOneUse())
4625 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
4626 E = Ptr.getNode()->use_end(); I != E; ++I) {
4629 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
4634 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4635 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
4637 std::swap(BasePtr, Offset);
4640 // Don't create a indexed load / store with zero offset.
4641 if (isa<ConstantSDNode>(Offset) &&
4642 cast<ConstantSDNode>(Offset)->isNullValue())
4645 // Try turning it into a post-indexed load / store except when
4646 // 1) All uses are load / store ops that use it as base ptr.
4647 // 2) Op must be independent of N, i.e. Op is neither a predecessor
4648 // nor a successor of N. Otherwise, if Op is folded that would
4652 bool TryNext = false;
4653 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
4654 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
4656 if (Use == Ptr.getNode())
4659 // If all the uses are load / store addresses, then don't do the
4661 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
4662 bool RealUse = false;
4663 for (SDNode::use_iterator III = Use->use_begin(),
4664 EEE = Use->use_end(); III != EEE; ++III) {
4665 SDNode *UseUse = *III;
4666 if (!((UseUse->getOpcode() == ISD::LOAD &&
4667 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) ||
4668 (UseUse->getOpcode() == ISD::STORE &&
4669 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use)))
4684 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
4685 SDValue Result = isLoad
4686 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
4687 BasePtr, Offset, AM)
4688 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
4689 BasePtr, Offset, AM);
4692 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
4693 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
4695 WorkListRemover DeadNodes(*this);
4697 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
4699 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
4702 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
4706 // Finally, since the node is now dead, remove it from the graph.
4709 // Replace the uses of Use with uses of the updated base value.
4710 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
4711 Result.getValue(isLoad ? 1 : 0),
4713 removeFromWorkList(Op);
4723 /// InferAlignment - If we can infer some alignment information from this
4724 /// pointer, return it.
4725 static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) {
4726 // If this is a direct reference to a stack slot, use information about the
4727 // stack slot's alignment.
4728 int FrameIdx = 1 << 31;
4729 int64_t FrameOffset = 0;
4730 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) {
4731 FrameIdx = FI->getIndex();
4732 } else if (Ptr.getOpcode() == ISD::ADD &&
4733 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
4734 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4735 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4736 FrameOffset = Ptr.getConstantOperandVal(1);
4739 if (FrameIdx != (1 << 31)) {
4740 // FIXME: Handle FI+CST.
4741 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo();
4742 if (MFI.isFixedObjectIndex(FrameIdx)) {
4743 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset;
4745 // The alignment of the frame index can be determined from its offset from
4746 // the incoming frame position. If the frame object is at offset 32 and
4747 // the stack is guaranteed to be 16-byte aligned, then we know that the
4748 // object is 16-byte aligned.
4749 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment();
4750 unsigned Align = MinAlign(ObjectOffset, StackAlign);
4752 // Finally, the frame object itself may have a known alignment. Factor
4753 // the alignment + offset into a new alignment. For example, if we know
4754 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a
4755 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte
4756 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc.
4757 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx),
4759 return std::max(Align, FIInfoAlign);
4766 SDValue DAGCombiner::visitLOAD(SDNode *N) {
4767 LoadSDNode *LD = cast<LoadSDNode>(N);
4768 SDValue Chain = LD->getChain();
4769 SDValue Ptr = LD->getBasePtr();
4771 // Try to infer better alignment information than the load already has.
4772 if (!Fast && LD->isUnindexed()) {
4773 if (unsigned Align = InferAlignment(Ptr, DAG)) {
4774 if (Align > LD->getAlignment())
4775 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
4776 LD->getValueType(0),
4777 Chain, Ptr, LD->getSrcValue(),
4778 LD->getSrcValueOffset(), LD->getMemoryVT(),
4779 LD->isVolatile(), Align);
4783 // If load is not volatile and there are no uses of the loaded value (and
4784 // the updated indexed value in case of indexed loads), change uses of the
4785 // chain value into uses of the chain input (i.e. delete the dead load).
4786 if (!LD->isVolatile()) {
4787 if (N->getValueType(1) == MVT::Other) {
4789 if (N->hasNUsesOfValue(0, 0)) {
4790 // It's not safe to use the two value CombineTo variant here. e.g.
4791 // v1, chain2 = load chain1, loc
4792 // v2, chain3 = load chain2, loc
4794 // Now we replace use of chain2 with chain1. This makes the second load
4795 // isomorphic to the one we are deleting, and thus makes this load live.
4796 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4797 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG));
4799 WorkListRemover DeadNodes(*this);
4800 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
4802 if (N->use_empty()) {
4803 removeFromWorkList(N);
4807 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4811 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
4812 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
4813 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
4814 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4815 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG));
4816 DOUT << " and 2 other values\n";
4817 WorkListRemover DeadNodes(*this);
4818 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
4819 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
4820 DAG.getUNDEF(N->getValueType(1)),
4822 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
4823 removeFromWorkList(N);
4825 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4830 // If this load is directly stored, replace the load value with the stored
4832 // TODO: Handle store large -> read small portion.
4833 // TODO: Handle TRUNCSTORE/LOADEXT
4834 if (LD->getExtensionType() == ISD::NON_EXTLOAD &&
4835 !LD->isVolatile()) {
4836 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
4837 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
4838 if (PrevST->getBasePtr() == Ptr &&
4839 PrevST->getValue().getValueType() == N->getValueType(0))
4840 return CombineTo(N, Chain.getOperand(1), Chain);
4845 // Walk up chain skipping non-aliasing memory nodes.
4846 SDValue BetterChain = FindBetterChain(N, Chain);
4848 // If there is a better chain.
4849 if (Chain != BetterChain) {
4852 // Replace the chain to void dependency.
4853 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
4854 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
4856 LD->getSrcValue(), LD->getSrcValueOffset(),
4857 LD->isVolatile(), LD->getAlignment());
4859 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
4860 LD->getValueType(0),
4861 BetterChain, Ptr, LD->getSrcValue(),
4862 LD->getSrcValueOffset(),
4865 LD->getAlignment());
4868 // Create token factor to keep old chain connected.
4869 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
4870 MVT::Other, Chain, ReplLoad.getValue(1));
4872 // Replace uses with load result and token factor. Don't add users
4874 return CombineTo(N, ReplLoad.getValue(0), Token, false);
4878 // Try transforming N to an indexed load.
4879 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4880 return SDValue(N, 0);
4885 SDValue DAGCombiner::visitSTORE(SDNode *N) {
4886 StoreSDNode *ST = cast<StoreSDNode>(N);
4887 SDValue Chain = ST->getChain();
4888 SDValue Value = ST->getValue();
4889 SDValue Ptr = ST->getBasePtr();
4891 // Try to infer better alignment information than the store already has.
4892 if (!Fast && ST->isUnindexed()) {
4893 if (unsigned Align = InferAlignment(Ptr, DAG)) {
4894 if (Align > ST->getAlignment())
4895 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
4896 Ptr, ST->getSrcValue(),
4897 ST->getSrcValueOffset(), ST->getMemoryVT(),
4898 ST->isVolatile(), Align);
4902 // If this is a store of a bit convert, store the input value if the
4903 // resultant store does not need a higher alignment than the original.
4904 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
4905 ST->isUnindexed()) {
4906 unsigned Align = ST->getAlignment();
4907 MVT SVT = Value.getOperand(0).getValueType();
4908 unsigned OrigAlign = TLI.getTargetData()->
4909 getABITypeAlignment(SVT.getTypeForMVT());
4910 if (Align <= OrigAlign &&
4911 ((!LegalOperations && !ST->isVolatile()) ||
4912 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
4913 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
4914 Ptr, ST->getSrcValue(),
4915 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign);
4918 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
4919 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
4920 // NOTE: If the original store is volatile, this transform must not increase
4921 // the number of stores. For example, on x86-32 an f64 can be stored in one
4922 // processor operation but an i64 (which is not legal) requires two. So the
4923 // transform should not be done in this case.
4924 if (Value.getOpcode() != ISD::TargetConstantFP) {
4926 switch (CFP->getValueType(0).getSimpleVT()) {
4927 default: assert(0 && "Unknown FP type");
4928 case MVT::f80: // We don't do this for these yet.
4933 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations &&
4934 !ST->isVolatile()) ||
4935 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
4936 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
4937 bitcastToAPInt().getZExtValue(), MVT::i32);
4938 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
4939 Ptr, ST->getSrcValue(),
4940 ST->getSrcValueOffset(), ST->isVolatile(),
4941 ST->getAlignment());
4945 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations &&
4946 !ST->isVolatile()) ||
4947 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
4948 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
4949 getZExtValue(), MVT::i64);
4950 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
4951 Ptr, ST->getSrcValue(),
4952 ST->getSrcValueOffset(), ST->isVolatile(),
4953 ST->getAlignment());
4954 } else if (!ST->isVolatile() &&
4955 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
4956 // Many FP stores are not made apparent until after legalize, e.g. for
4957 // argument passing. Since this is so common, custom legalize the
4958 // 64-bit integer store into two 32-bit stores.
4959 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
4960 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
4961 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
4962 if (TLI.isBigEndian()) std::swap(Lo, Hi);
4964 int SVOffset = ST->getSrcValueOffset();
4965 unsigned Alignment = ST->getAlignment();
4966 bool isVolatile = ST->isVolatile();
4968 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
4969 Ptr, ST->getSrcValue(),
4970 ST->getSrcValueOffset(),
4971 isVolatile, ST->getAlignment());
4972 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
4973 DAG.getConstant(4, Ptr.getValueType()));
4975 Alignment = MinAlign(Alignment, 4U);
4976 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
4977 Ptr, ST->getSrcValue(),
4978 SVOffset, isVolatile, Alignment);
4979 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
4989 // Walk up chain skipping non-aliasing memory nodes.
4990 SDValue BetterChain = FindBetterChain(N, Chain);
4992 // If there is a better chain.
4993 if (Chain != BetterChain) {
4994 // Replace the chain to avoid dependency.
4996 if (ST->isTruncatingStore()) {
4997 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
4998 ST->getSrcValue(),ST->getSrcValueOffset(),
5000 ST->isVolatile(), ST->getAlignment());
5002 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
5003 ST->getSrcValue(), ST->getSrcValueOffset(),
5004 ST->isVolatile(), ST->getAlignment());
5007 // Create token to keep both nodes around.
5008 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
5009 MVT::Other, Chain, ReplStore);
5011 // Don't add users to work list.
5012 return CombineTo(N, Token, false);
5016 // Try transforming N to an indexed store.
5017 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
5018 return SDValue(N, 0);
5020 // FIXME: is there such a thing as a truncating indexed store?
5021 if (ST->isTruncatingStore() && ST->isUnindexed() &&
5022 Value.getValueType().isInteger()) {
5023 // See if we can simplify the input to this truncstore with knowledge that
5024 // only the low bits are being used. For example:
5025 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
5027 GetDemandedBits(Value,
5028 APInt::getLowBitsSet(Value.getValueSizeInBits(),
5029 ST->getMemoryVT().getSizeInBits()));
5030 AddToWorkList(Value.getNode());
5031 if (Shorter.getNode())
5032 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
5033 Ptr, ST->getSrcValue(),
5034 ST->getSrcValueOffset(), ST->getMemoryVT(),
5035 ST->isVolatile(), ST->getAlignment());
5037 // Otherwise, see if we can simplify the operation with
5038 // SimplifyDemandedBits, which only works if the value has a single use.
5039 if (SimplifyDemandedBits(Value,
5040 APInt::getLowBitsSet(
5041 Value.getValueSizeInBits(),
5042 ST->getMemoryVT().getSizeInBits())))
5043 return SDValue(N, 0);
5046 // If this is a load followed by a store to the same location, then the store
5048 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
5049 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
5050 ST->isUnindexed() && !ST->isVolatile() &&
5051 // There can't be any side effects between the load and store, such as
5053 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
5054 // The store is dead, remove it.
5059 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
5060 // truncating store. We can do this even if this is already a truncstore.
5061 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
5062 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
5063 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
5064 ST->getMemoryVT())) {
5065 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
5066 Ptr, ST->getSrcValue(),
5067 ST->getSrcValueOffset(), ST->getMemoryVT(),
5068 ST->isVolatile(), ST->getAlignment());
5074 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
5075 SDValue InVec = N->getOperand(0);
5076 SDValue InVal = N->getOperand(1);
5077 SDValue EltNo = N->getOperand(2);
5079 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
5080 // vector with the inserted element.
5081 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
5082 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5083 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
5084 InVec.getNode()->op_end());
5085 if (Elt < Ops.size())
5087 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5088 InVec.getValueType(), &Ops[0], Ops.size());
5094 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
5095 // (vextract (scalar_to_vector val, 0) -> val
5096 SDValue InVec = N->getOperand(0);
5098 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR)
5099 return InVec.getOperand(0);
5101 // Perform only after legalization to ensure build_vector / vector_shuffle
5102 // optimizations have already been done.
5103 if (!LegalOperations) return SDValue();
5105 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
5106 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
5107 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
5108 SDValue EltNo = N->getOperand(1);
5110 if (isa<ConstantSDNode>(EltNo)) {
5111 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5112 bool NewLoad = false;
5113 bool BCNumEltsChanged = false;
5114 MVT VT = InVec.getValueType();
5115 MVT EVT = VT.getVectorElementType();
5118 if (InVec.getOpcode() == ISD::BIT_CONVERT) {
5119 MVT BCVT = InVec.getOperand(0).getValueType();
5120 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType()))
5122 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
5123 BCNumEltsChanged = true;
5124 InVec = InVec.getOperand(0);
5125 EVT = BCVT.getVectorElementType();
5129 LoadSDNode *LN0 = NULL;
5130 if (ISD::isNormalLoad(InVec.getNode())) {
5131 LN0 = cast<LoadSDNode>(InVec);
5132 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5133 InVec.getOperand(0).getValueType() == EVT &&
5134 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
5135 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
5136 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) {
5137 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
5139 // (load $addr+1*size)
5141 // If the bit convert changed the number of elements, it is unsafe
5142 // to examine the mask.
5143 if (BCNumEltsChanged)
5145 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2).
5146 getOperand(Elt))->getZExtValue();
5147 unsigned NumElems = InVec.getOperand(2).getNumOperands();
5148 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
5149 if (InVec.getOpcode() == ISD::BIT_CONVERT)
5150 InVec = InVec.getOperand(0);
5151 if (ISD::isNormalLoad(InVec.getNode())) {
5152 LN0 = cast<LoadSDNode>(InVec);
5153 Elt = (Idx < NumElems) ? Idx : Idx - NumElems;
5157 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile())
5160 unsigned Align = LN0->getAlignment();
5162 // Check the resultant load doesn't need a higher alignment than the
5165 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForMVT());
5167 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
5173 SDValue NewPtr = LN0->getBasePtr();
5175 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8;
5176 MVT PtrType = NewPtr.getValueType();
5177 if (TLI.isBigEndian())
5178 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
5179 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
5180 DAG.getConstant(PtrOff, PtrType));
5183 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
5184 LN0->getSrcValue(), LN0->getSrcValueOffset(),
5185 LN0->isVolatile(), Align);
5191 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
5192 unsigned NumInScalars = N->getNumOperands();
5193 MVT VT = N->getValueType(0);
5194 unsigned NumElts = VT.getVectorNumElements();
5195 MVT EltType = VT.getVectorElementType();
5197 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
5198 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
5199 // at most two distinct vectors, turn this into a shuffle node.
5200 SDValue VecIn1, VecIn2;
5201 for (unsigned i = 0; i != NumInScalars; ++i) {
5202 // Ignore undef inputs.
5203 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5205 // If this input is something other than a EXTRACT_VECTOR_ELT with a
5206 // constant index, bail out.
5207 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5208 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
5209 VecIn1 = VecIn2 = SDValue(0, 0);
5213 // If the input vector type disagrees with the result of the build_vector,
5214 // we can't make a shuffle.
5215 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
5216 if (ExtractedFromVec.getValueType() != VT) {
5217 VecIn1 = VecIn2 = SDValue(0, 0);
5221 // Otherwise, remember this. We allow up to two distinct input vectors.
5222 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
5225 if (VecIn1.getNode() == 0) {
5226 VecIn1 = ExtractedFromVec;
5227 } else if (VecIn2.getNode() == 0) {
5228 VecIn2 = ExtractedFromVec;
5231 VecIn1 = VecIn2 = SDValue(0, 0);
5236 // If everything is good, we can make a shuffle operation.
5237 if (VecIn1.getNode()) {
5238 SmallVector<SDValue, 8> BuildVecIndices;
5239 for (unsigned i = 0; i != NumInScalars; ++i) {
5240 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
5241 BuildVecIndices.push_back(DAG.getUNDEF(TLI.getPointerTy()));
5245 SDValue Extract = N->getOperand(i);
5247 // If extracting from the first vector, just use the index directly.
5248 if (Extract.getOperand(0) == VecIn1) {
5249 BuildVecIndices.push_back(Extract.getOperand(1));
5253 // Otherwise, use InIdx + VecSize
5255 cast<ConstantSDNode>(Extract.getOperand(1))->getZExtValue();
5256 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars));
5259 // Add count and size info.
5260 MVT BuildVecVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts);
5261 if (!TLI.isTypeLegal(BuildVecVT) && LegalTypes)
5264 // Return the new VECTOR_SHUFFLE node.
5267 if (VecIn2.getNode()) {
5270 // Use an undef build_vector as input for the second operand.
5271 std::vector<SDValue> UnOps(NumInScalars,
5272 DAG.getUNDEF(EltType));
5273 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
5274 &UnOps[0], UnOps.size());
5275 AddToWorkList(Ops[1].getNode());
5278 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), BuildVecVT,
5279 &BuildVecIndices[0], BuildVecIndices.size());
5280 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(), VT, Ops, 3);
5286 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
5287 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
5288 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
5289 // inputs come from at most two distinct vectors, turn this into a shuffle
5292 // If we only have one input vector, we don't need to do any concatenation.
5293 if (N->getNumOperands() == 1)
5294 return N->getOperand(0);
5299 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
5300 SDValue ShufMask = N->getOperand(2);
5301 unsigned NumElts = ShufMask.getNumOperands();
5303 SDValue N0 = N->getOperand(0);
5304 SDValue N1 = N->getOperand(1);
5306 assert(N0.getValueType().getVectorNumElements() == NumElts &&
5307 "Vector shuffle must be normalized in DAG");
5309 // If the shuffle mask is an identity operation on the LHS, return the LHS.
5310 bool isIdentity = true;
5311 for (unsigned i = 0; i != NumElts; ++i) {
5312 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
5313 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != i) {
5318 if (isIdentity) return N->getOperand(0);
5320 // If the shuffle mask is an identity operation on the RHS, return the RHS.
5322 for (unsigned i = 0; i != NumElts; ++i) {
5323 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
5324 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() !=
5330 if (isIdentity) return N->getOperand(1);
5332 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
5334 bool isUnary = true;
5335 bool isSplat = true;
5337 unsigned BaseIdx = 0;
5338 for (unsigned i = 0; i != NumElts; ++i)
5339 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
5340 unsigned Idx=cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue();
5341 int V = (Idx < NumElts) ? 0 : 1;
5355 // Normalize unary shuffle so the RHS is undef.
5356 if (isUnary && VecNum == 1)
5359 // If it is a splat, check if the argument vector is a build_vector with
5360 // all scalar elements the same.
5362 SDNode *V = N0.getNode();
5364 // If this is a bit convert that changes the element type of the vector but
5365 // not the number of vector elements, look through it. Be careful not to
5366 // look though conversions that change things like v4f32 to v2f64.
5367 if (V->getOpcode() == ISD::BIT_CONVERT) {
5368 SDValue ConvInput = V->getOperand(0);
5369 if (ConvInput.getValueType().isVector() &&
5370 ConvInput.getValueType().getVectorNumElements() == NumElts)
5371 V = ConvInput.getNode();
5374 if (V->getOpcode() == ISD::BUILD_VECTOR) {
5375 unsigned NumElems = V->getNumOperands();
5376 if (NumElems > BaseIdx) {
5378 bool AllSame = true;
5379 for (unsigned i = 0; i != NumElems; ++i) {
5380 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
5381 Base = V->getOperand(i);
5385 // Splat of <u, u, u, u>, return <u, u, u, u>
5386 if (!Base.getNode())
5388 for (unsigned i = 0; i != NumElems; ++i) {
5389 if (V->getOperand(i) != Base) {
5394 // Splat of <x, x, x, x>, return <x, x, x, x>
5401 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
5403 if (isUnary || N0 == N1) {
5404 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
5406 SmallVector<SDValue, 8> MappedOps;
5408 for (unsigned i = 0; i != NumElts; ++i) {
5409 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
5410 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() <
5412 MappedOps.push_back(ShufMask.getOperand(i));
5415 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() -
5417 MappedOps.push_back(DAG.getConstant(NewIdx,
5418 ShufMask.getOperand(i).getValueType()));
5422 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5423 ShufMask.getValueType(),
5424 &MappedOps[0], MappedOps.size());
5425 AddToWorkList(ShufMask.getNode());
5426 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(),
5427 N->getValueType(0), N0,
5428 DAG.getUNDEF(N->getValueType(0)),
5435 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
5436 /// an AND to a vector_shuffle with the destination vector and a zero vector.
5437 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
5438 /// vector_shuffle V, Zero, <0, 4, 2, 4>
5439 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
5440 SDValue LHS = N->getOperand(0);
5441 SDValue RHS = N->getOperand(1);
5442 if (N->getOpcode() == ISD::AND) {
5443 if (RHS.getOpcode() == ISD::BIT_CONVERT)
5444 RHS = RHS.getOperand(0);
5445 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
5446 std::vector<SDValue> IdxOps;
5447 unsigned NumOps = RHS.getNumOperands();
5448 unsigned NumElts = NumOps;
5449 for (unsigned i = 0; i != NumElts; ++i) {
5450 SDValue Elt = RHS.getOperand(i);
5451 if (!isa<ConstantSDNode>(Elt))
5453 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
5454 IdxOps.push_back(DAG.getIntPtrConstant(i));
5455 else if (cast<ConstantSDNode>(Elt)->isNullValue())
5456 IdxOps.push_back(DAG.getIntPtrConstant(NumElts));
5461 // Let's see if the target supports this vector_shuffle.
5462 if (!TLI.isVectorClearMaskLegal(IdxOps, TLI.getPointerTy(), DAG))
5465 // Return the new VECTOR_SHUFFLE node.
5466 MVT EVT = RHS.getValueType().getVectorElementType();
5467 MVT VT = MVT::getVectorVT(EVT, NumElts);
5468 MVT MaskVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts);
5469 std::vector<SDValue> Ops;
5470 LHS = DAG.getNode(ISD::BIT_CONVERT, LHS.getDebugLoc(), VT, LHS);
5472 AddToWorkList(LHS.getNode());
5473 std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT));
5474 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5475 VT, &ZeroOps[0], ZeroOps.size()));
5476 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5477 MaskVT, &IdxOps[0], IdxOps.size()));
5478 SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(),
5479 VT, &Ops[0], Ops.size());
5481 if (VT != N->getValueType(0))
5482 Result = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
5483 N->getValueType(0), Result);
5492 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
5493 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
5494 // After legalize, the target may be depending on adds and other
5495 // binary ops to provide legal ways to construct constants or other
5496 // things. Simplifying them may result in a loss of legality.
5497 if (LegalOperations) return SDValue();
5499 MVT VT = N->getValueType(0);
5500 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!");
5502 MVT EltType = VT.getVectorElementType();
5503 SDValue LHS = N->getOperand(0);
5504 SDValue RHS = N->getOperand(1);
5505 SDValue Shuffle = XformToShuffleWithZero(N);
5506 if (Shuffle.getNode()) return Shuffle;
5508 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
5510 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
5511 RHS.getOpcode() == ISD::BUILD_VECTOR) {
5512 SmallVector<SDValue, 8> Ops;
5513 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
5514 SDValue LHSOp = LHS.getOperand(i);
5515 SDValue RHSOp = RHS.getOperand(i);
5516 // If these two elements can't be folded, bail out.
5517 if ((LHSOp.getOpcode() != ISD::UNDEF &&
5518 LHSOp.getOpcode() != ISD::Constant &&
5519 LHSOp.getOpcode() != ISD::ConstantFP) ||
5520 (RHSOp.getOpcode() != ISD::UNDEF &&
5521 RHSOp.getOpcode() != ISD::Constant &&
5522 RHSOp.getOpcode() != ISD::ConstantFP))
5525 // Can't fold divide by zero.
5526 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
5527 N->getOpcode() == ISD::FDIV) {
5528 if ((RHSOp.getOpcode() == ISD::Constant &&
5529 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
5530 (RHSOp.getOpcode() == ISD::ConstantFP &&
5531 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
5535 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(),
5536 EltType, LHSOp, RHSOp));
5537 AddToWorkList(Ops.back().getNode());
5538 assert((Ops.back().getOpcode() == ISD::UNDEF ||
5539 Ops.back().getOpcode() == ISD::Constant ||
5540 Ops.back().getOpcode() == ISD::ConstantFP) &&
5541 "Scalar binop didn't fold!");
5544 if (Ops.size() == LHS.getNumOperands()) {
5545 MVT VT = LHS.getValueType();
5546 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
5547 &Ops[0], Ops.size());
5554 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
5555 SDValue N1, SDValue N2){
5556 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
5558 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
5559 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5561 // If we got a simplified select_cc node back from SimplifySelectCC, then
5562 // break it down into a new SETCC node, and a new SELECT node, and then return
5563 // the SELECT node, since we were called with a SELECT node.
5564 if (SCC.getNode()) {
5565 // Check to see if we got a select_cc back (to turn into setcc/select).
5566 // Otherwise, just return whatever node we got back, like fabs.
5567 if (SCC.getOpcode() == ISD::SELECT_CC) {
5568 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
5570 SCC.getOperand(0), SCC.getOperand(1),
5572 AddToWorkList(SETCC.getNode());
5573 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
5574 SCC.getOperand(2), SCC.getOperand(3), SETCC);
5582 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
5583 /// are the two values being selected between, see if we can simplify the
5584 /// select. Callers of this should assume that TheSelect is deleted if this
5585 /// returns true. As such, they should return the appropriate thing (e.g. the
5586 /// node) back to the top-level of the DAG combiner loop to avoid it being
5588 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
5591 // If this is a select from two identical things, try to pull the operation
5592 // through the select.
5593 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
5594 // If this is a load and the token chain is identical, replace the select
5595 // of two loads with a load through a select of the address to load from.
5596 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
5597 // constants have been dropped into the constant pool.
5598 if (LHS.getOpcode() == ISD::LOAD &&
5599 // Do not let this transformation reduce the number of volatile loads.
5600 !cast<LoadSDNode>(LHS)->isVolatile() &&
5601 !cast<LoadSDNode>(RHS)->isVolatile() &&
5602 // Token chains must be identical.
5603 LHS.getOperand(0) == RHS.getOperand(0)) {
5604 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
5605 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
5607 // If this is an EXTLOAD, the VT's must match.
5608 if (LLD->getMemoryVT() == RLD->getMemoryVT()) {
5609 // FIXME: this conflates two src values, discarding one. This is not
5610 // the right thing to do, but nothing uses srcvalues now. When they do,
5611 // turn SrcValue into a list of locations.
5613 if (TheSelect->getOpcode() == ISD::SELECT) {
5614 // Check that the condition doesn't reach either load. If so, folding
5615 // this will induce a cycle into the DAG.
5616 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5617 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) {
5618 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
5619 LLD->getBasePtr().getValueType(),
5620 TheSelect->getOperand(0), LLD->getBasePtr(),
5624 // Check that the condition doesn't reach either load. If so, folding
5625 // this will induce a cycle into the DAG.
5626 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5627 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5628 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) &&
5629 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) {
5630 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
5631 LLD->getBasePtr().getValueType(),
5632 TheSelect->getOperand(0),
5633 TheSelect->getOperand(1),
5634 LLD->getBasePtr(), RLD->getBasePtr(),
5635 TheSelect->getOperand(4));
5639 if (Addr.getNode()) {
5641 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
5642 Load = DAG.getLoad(TheSelect->getValueType(0),
5643 TheSelect->getDebugLoc(),
5645 Addr,LLD->getSrcValue(),
5646 LLD->getSrcValueOffset(),
5648 LLD->getAlignment());
5650 Load = DAG.getExtLoad(LLD->getExtensionType(),
5651 TheSelect->getDebugLoc(),
5652 TheSelect->getValueType(0),
5653 LLD->getChain(), Addr, LLD->getSrcValue(),
5654 LLD->getSrcValueOffset(),
5657 LLD->getAlignment());
5660 // Users of the select now use the result of the load.
5661 CombineTo(TheSelect, Load);
5663 // Users of the old loads now use the new load's chain. We know the
5664 // old-load value is dead now.
5665 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
5666 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
5676 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
5677 SDValue N2, SDValue N3,
5678 ISD::CondCode CC, bool NotExtCompare) {
5679 MVT VT = N2.getValueType();
5680 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
5681 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
5682 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
5684 // Determine if the condition we're dealing with is constant
5685 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
5686 N0, N1, CC, DL, false);
5687 if (SCC.getNode()) AddToWorkList(SCC.getNode());
5688 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
5690 // fold select_cc true, x, y -> x
5691 if (SCCC && !SCCC->isNullValue())
5693 // fold select_cc false, x, y -> y
5694 if (SCCC && SCCC->isNullValue())
5697 // Check to see if we can simplify the select into an fabs node
5698 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
5699 // Allow either -0.0 or 0.0
5700 if (CFP->getValueAPF().isZero()) {
5701 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
5702 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
5703 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
5704 N2 == N3.getOperand(0))
5705 return DAG.getNode(ISD::FABS, DL, VT, N0);
5707 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
5708 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
5709 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
5710 N2.getOperand(0) == N3)
5711 return DAG.getNode(ISD::FABS, DL, VT, N3);
5715 // Check to see if we can perform the "gzip trick", transforming
5716 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
5717 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
5718 N0.getValueType().isInteger() &&
5719 N2.getValueType().isInteger() &&
5720 (N1C->isNullValue() || // (a < 0) ? b : 0
5721 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
5722 MVT XType = N0.getValueType();
5723 MVT AType = N2.getValueType();
5724 if (XType.bitsGE(AType)) {
5725 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
5726 // single-bit constant.
5727 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
5728 unsigned ShCtV = N2C->getAPIntValue().logBase2();
5729 ShCtV = XType.getSizeInBits()-ShCtV-1;
5730 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy());
5731 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
5733 AddToWorkList(Shift.getNode());
5735 if (XType.bitsGT(AType)) {
5736 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
5737 AddToWorkList(Shift.getNode());
5740 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
5743 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
5745 DAG.getConstant(XType.getSizeInBits()-1,
5746 getShiftAmountTy()));
5747 AddToWorkList(Shift.getNode());
5749 if (XType.bitsGT(AType)) {
5750 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
5751 AddToWorkList(Shift.getNode());
5754 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
5758 // fold select C, 16, 0 -> shl C, 4
5759 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
5760 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {
5762 // If the caller doesn't want us to simplify this into a zext of a compare,
5764 if (NotExtCompare && N2C->getAPIntValue() == 1)
5767 // Get a SetCC of the condition
5768 // FIXME: Should probably make sure that setcc is legal if we ever have a
5769 // target where it isn't.
5771 // cast from setcc result type to select result type
5773 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
5775 if (N2.getValueType().bitsLT(SCC.getValueType()))
5776 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
5778 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
5779 N2.getValueType(), SCC);
5781 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
5782 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
5783 N2.getValueType(), SCC);
5786 AddToWorkList(SCC.getNode());
5787 AddToWorkList(Temp.getNode());
5789 if (N2C->getAPIntValue() == 1)
5792 // shl setcc result by log2 n2c
5793 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
5794 DAG.getConstant(N2C->getAPIntValue().logBase2(),
5795 getShiftAmountTy()));
5798 // Check to see if this is the equivalent of setcc
5799 // FIXME: Turn all of these into setcc if setcc if setcc is legal
5800 // otherwise, go ahead with the folds.
5801 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
5802 MVT XType = N0.getValueType();
5803 if (!LegalOperations ||
5804 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
5805 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
5806 if (Res.getValueType() != VT)
5807 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
5811 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
5812 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
5813 (!LegalOperations ||
5814 TLI.isOperationLegal(ISD::CTLZ, XType))) {
5815 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
5816 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
5817 DAG.getConstant(Log2_32(XType.getSizeInBits()),
5818 getShiftAmountTy()));
5820 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
5821 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
5822 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
5823 XType, DAG.getConstant(0, XType), N0);
5824 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
5825 return DAG.getNode(ISD::SRL, DL, XType,
5826 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
5827 DAG.getConstant(XType.getSizeInBits()-1,
5828 getShiftAmountTy()));
5830 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
5831 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
5832 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
5833 DAG.getConstant(XType.getSizeInBits()-1,
5834 getShiftAmountTy()));
5835 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
5839 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
5840 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5841 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
5842 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
5843 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) {
5844 MVT XType = N0.getValueType();
5845 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0,
5846 DAG.getConstant(XType.getSizeInBits()-1,
5847 getShiftAmountTy()));
5848 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType,
5850 AddToWorkList(Shift.getNode());
5851 AddToWorkList(Add.getNode());
5852 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
5854 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
5855 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5856 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
5857 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
5858 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
5859 MVT XType = N0.getValueType();
5860 if (SubC->isNullValue() && XType.isInteger()) {
5861 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
5863 DAG.getConstant(XType.getSizeInBits()-1,
5864 getShiftAmountTy()));
5865 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
5867 AddToWorkList(Shift.getNode());
5868 AddToWorkList(Add.getNode());
5869 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
5877 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
5878 SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0,
5879 SDValue N1, ISD::CondCode Cond,
5880 DebugLoc DL, bool foldBooleans) {
5881 TargetLowering::DAGCombinerInfo
5882 DagCombineInfo(DAG, Level == Unrestricted, false, this);
5883 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
5886 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
5887 /// return a DAG expression to select that will generate the same value by
5888 /// multiplying by a magic number. See:
5889 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
5890 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
5891 std::vector<SDNode*> Built;
5892 SDValue S = TLI.BuildSDIV(N, DAG, &Built);
5894 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
5900 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
5901 /// return a DAG expression to select that will generate the same value by
5902 /// multiplying by a magic number. See:
5903 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
5904 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
5905 std::vector<SDNode*> Built;
5906 SDValue S = TLI.BuildUDIV(N, DAG, &Built);
5908 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
5914 /// FindBaseOffset - Return true if base is known not to alias with anything
5915 /// but itself. Provides base object and offset as results.
5916 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) {
5917 // Assume it is a primitive operation.
5918 Base = Ptr; Offset = 0;
5920 // If it's an adding a simple constant then integrate the offset.
5921 if (Base.getOpcode() == ISD::ADD) {
5922 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
5923 Base = Base.getOperand(0);
5924 Offset += C->getZExtValue();
5928 // If it's any of the following then it can't alias with anything but itself.
5929 return isa<FrameIndexSDNode>(Base) ||
5930 isa<ConstantPoolSDNode>(Base) ||
5931 isa<GlobalAddressSDNode>(Base);
5934 /// isAlias - Return true if there is any possibility that the two addresses
5936 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
5937 const Value *SrcValue1, int SrcValueOffset1,
5938 SDValue Ptr2, int64_t Size2,
5939 const Value *SrcValue2, int SrcValueOffset2) const {
5940 // If they are the same then they must be aliases.
5941 if (Ptr1 == Ptr2) return true;
5943 // Gather base node and offset information.
5944 SDValue Base1, Base2;
5945 int64_t Offset1, Offset2;
5946 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
5947 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
5949 // If they have a same base address then...
5951 // Check to see if the addresses overlap.
5952 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
5954 // If we know both bases then they can't alias.
5955 if (KnownBase1 && KnownBase2) return false;
5957 if (CombinerGlobalAA) {
5958 // Use alias analysis information.
5959 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
5960 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
5961 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
5962 AliasAnalysis::AliasResult AAResult =
5963 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
5964 if (AAResult == AliasAnalysis::NoAlias)
5968 // Otherwise we have to assume they alias.
5972 /// FindAliasInfo - Extracts the relevant alias information from the memory
5973 /// node. Returns true if the operand was a load.
5974 bool DAGCombiner::FindAliasInfo(SDNode *N,
5975 SDValue &Ptr, int64_t &Size,
5976 const Value *&SrcValue, int &SrcValueOffset) const {
5977 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5978 Ptr = LD->getBasePtr();
5979 Size = LD->getMemoryVT().getSizeInBits() >> 3;
5980 SrcValue = LD->getSrcValue();
5981 SrcValueOffset = LD->getSrcValueOffset();
5983 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5984 Ptr = ST->getBasePtr();
5985 Size = ST->getMemoryVT().getSizeInBits() >> 3;
5986 SrcValue = ST->getSrcValue();
5987 SrcValueOffset = ST->getSrcValueOffset();
5989 assert(0 && "FindAliasInfo expected a memory operand");
5995 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
5996 /// looking for aliasing nodes and adding them to the Aliases vector.
5997 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
5998 SmallVector<SDValue, 8> &Aliases) {
5999 SmallVector<SDValue, 8> Chains; // List of chains to visit.
6000 std::set<SDNode *> Visited; // Visited node set.
6002 // Get alias information for node.
6005 const Value *SrcValue;
6007 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
6010 Chains.push_back(OriginalChain);
6012 // Look at each chain and determine if it is an alias. If so, add it to the
6013 // aliases list. If not, then continue up the chain looking for the next
6015 while (!Chains.empty()) {
6016 SDValue Chain = Chains.back();
6019 // Don't bother if we've been before.
6020 if (Visited.find(Chain.getNode()) != Visited.end()) continue;
6021 Visited.insert(Chain.getNode());
6023 switch (Chain.getOpcode()) {
6024 case ISD::EntryToken:
6025 // Entry token is ideal chain operand, but handled in FindBetterChain.
6030 // Get alias information for Chain.
6033 const Value *OpSrcValue;
6034 int OpSrcValueOffset;
6035 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
6036 OpSrcValue, OpSrcValueOffset);
6038 // If chain is alias then stop here.
6039 if (!(IsLoad && IsOpLoad) &&
6040 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
6041 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
6042 Aliases.push_back(Chain);
6044 // Look further up the chain.
6045 Chains.push_back(Chain.getOperand(0));
6046 // Clean up old chain.
6047 AddToWorkList(Chain.getNode());
6052 case ISD::TokenFactor:
6053 // We have to check each of the operands of the token factor, so we queue
6054 // then up. Adding the operands to the queue (stack) in reverse order
6055 // maintains the original order and increases the likelihood that getNode
6056 // will find a matching token factor (CSE.)
6057 for (unsigned n = Chain.getNumOperands(); n;)
6058 Chains.push_back(Chain.getOperand(--n));
6059 // Eliminate the token factor if we can.
6060 AddToWorkList(Chain.getNode());
6064 // For all other instructions we will just have to take what we can get.
6065 Aliases.push_back(Chain);
6071 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
6072 /// for a better chain (aliasing node.)
6073 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
6074 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
6076 // Accumulate all the aliases to this node.
6077 GatherAllAliases(N, OldChain, Aliases);
6079 if (Aliases.size() == 0) {
6080 // If no operands then chain to entry token.
6081 return DAG.getEntryNode();
6082 } else if (Aliases.size() == 1) {
6083 // If a single operand then chain to it. We don't need to revisit it.
6087 // Construct a custom tailored token factor.
6088 SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
6089 &Aliases[0], Aliases.size());
6091 // Make sure the old chain gets cleaned up.
6092 if (NewChain != OldChain) AddToWorkList(OldChain.getNode());
6097 // SelectionDAG::Combine - This is the entry point for the file.
6099 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast) {
6100 /// run - This is the main entry point to this class.
6102 DAGCombiner(*this, AA, Fast).Run(Level);