1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/ADT/SmallPtrSet.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
43 STATISTIC(NodesCombined , "Number of dag nodes combined");
44 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
45 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
46 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
47 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
48 STATISTIC(SlicedLoads, "Number of load sliced");
52 CombinerAA("combiner-alias-analysis", cl::Hidden,
53 cl::desc("Turn on alias analysis during testing"));
56 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
57 cl::desc("Include global information in alias analysis"));
59 /// Hidden option to stress test load slicing, i.e., when this option
60 /// is enabled, load slicing bypasses most of its profitability guards.
62 StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden,
63 cl::desc("Bypass the profitability model of load "
67 //------------------------------ DAGCombiner ---------------------------------//
71 const TargetLowering &TLI;
73 CodeGenOpt::Level OptLevel;
78 // Worklist of all of the nodes that need to be simplified.
80 // This has the semantics that when adding to the worklist,
81 // the item added must be next to be processed. It should
82 // also only appear once. The naive approach to this takes
85 // To reduce the insert/remove time to logarithmic, we use
86 // a set and a vector to maintain our worklist.
88 // The set contains the items on the worklist, but does not
89 // maintain the order they should be visited.
91 // The vector maintains the order nodes should be visited, but may
92 // contain duplicate or removed nodes. When choosing a node to
93 // visit, we pop off the order stack until we find an item that is
94 // also in the contents set. All operations are O(log N).
95 SmallPtrSet<SDNode*, 64> WorkListContents;
96 SmallVector<SDNode*, 64> WorkListOrder;
98 // AA - Used for DAG load/store alias analysis.
101 /// AddUsersToWorkList - When an instruction is simplified, add all users of
102 /// the instruction to the work lists because they might get more simplified
105 void AddUsersToWorkList(SDNode *N) {
106 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
111 /// visit - call the node-specific routine that knows how to fold each
112 /// particular type of node.
113 SDValue visit(SDNode *N);
116 /// AddToWorkList - Add to the work list making sure its instance is at the
117 /// back (next to be processed.)
118 void AddToWorkList(SDNode *N) {
119 WorkListContents.insert(N);
120 WorkListOrder.push_back(N);
123 /// removeFromWorkList - remove all instances of N from the worklist.
125 void removeFromWorkList(SDNode *N) {
126 WorkListContents.erase(N);
129 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
132 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
133 return CombineTo(N, &Res, 1, AddTo);
136 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
138 SDValue To[] = { Res0, Res1 };
139 return CombineTo(N, To, 2, AddTo);
142 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
146 /// SimplifyDemandedBits - Check the specified integer node value to see if
147 /// it can be simplified or if things it uses can be simplified by bit
148 /// propagation. If so, return true.
149 bool SimplifyDemandedBits(SDValue Op) {
150 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
151 APInt Demanded = APInt::getAllOnesValue(BitWidth);
152 return SimplifyDemandedBits(Op, Demanded);
155 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
157 bool CombineToPreIndexedLoadStore(SDNode *N);
158 bool CombineToPostIndexedLoadStore(SDNode *N);
159 bool SliceUpLoad(SDNode *N);
161 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
162 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
163 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
164 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
165 SDValue PromoteIntBinOp(SDValue Op);
166 SDValue PromoteIntShiftOp(SDValue Op);
167 SDValue PromoteExtend(SDValue Op);
168 bool PromoteLoad(SDValue Op);
170 void ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
171 SDValue Trunc, SDValue ExtLoad, SDLoc DL,
172 ISD::NodeType ExtType);
174 /// combine - call the node-specific routine that knows how to fold each
175 /// particular type of node. If that doesn't do anything, try the
176 /// target-specific DAG combines.
177 SDValue combine(SDNode *N);
179 // Visitation implementation - Implement dag node combining for different
180 // node types. The semantics are as follows:
182 // SDValue.getNode() == 0 - No change was made
183 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
184 // otherwise - N should be replaced by the returned Operand.
186 SDValue visitTokenFactor(SDNode *N);
187 SDValue visitMERGE_VALUES(SDNode *N);
188 SDValue visitADD(SDNode *N);
189 SDValue visitSUB(SDNode *N);
190 SDValue visitADDC(SDNode *N);
191 SDValue visitSUBC(SDNode *N);
192 SDValue visitADDE(SDNode *N);
193 SDValue visitSUBE(SDNode *N);
194 SDValue visitMUL(SDNode *N);
195 SDValue visitSDIV(SDNode *N);
196 SDValue visitUDIV(SDNode *N);
197 SDValue visitSREM(SDNode *N);
198 SDValue visitUREM(SDNode *N);
199 SDValue visitMULHU(SDNode *N);
200 SDValue visitMULHS(SDNode *N);
201 SDValue visitSMUL_LOHI(SDNode *N);
202 SDValue visitUMUL_LOHI(SDNode *N);
203 SDValue visitSMULO(SDNode *N);
204 SDValue visitUMULO(SDNode *N);
205 SDValue visitSDIVREM(SDNode *N);
206 SDValue visitUDIVREM(SDNode *N);
207 SDValue visitAND(SDNode *N);
208 SDValue visitOR(SDNode *N);
209 SDValue visitXOR(SDNode *N);
210 SDValue SimplifyVBinOp(SDNode *N);
211 SDValue SimplifyVUnaryOp(SDNode *N);
212 SDValue visitSHL(SDNode *N);
213 SDValue visitSRA(SDNode *N);
214 SDValue visitSRL(SDNode *N);
215 SDValue visitCTLZ(SDNode *N);
216 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
217 SDValue visitCTTZ(SDNode *N);
218 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
219 SDValue visitCTPOP(SDNode *N);
220 SDValue visitSELECT(SDNode *N);
221 SDValue visitVSELECT(SDNode *N);
222 SDValue visitSELECT_CC(SDNode *N);
223 SDValue visitSETCC(SDNode *N);
224 SDValue visitSIGN_EXTEND(SDNode *N);
225 SDValue visitZERO_EXTEND(SDNode *N);
226 SDValue visitANY_EXTEND(SDNode *N);
227 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
228 SDValue visitTRUNCATE(SDNode *N);
229 SDValue visitBITCAST(SDNode *N);
230 SDValue visitBUILD_PAIR(SDNode *N);
231 SDValue visitFADD(SDNode *N);
232 SDValue visitFSUB(SDNode *N);
233 SDValue visitFMUL(SDNode *N);
234 SDValue visitFMA(SDNode *N);
235 SDValue visitFDIV(SDNode *N);
236 SDValue visitFREM(SDNode *N);
237 SDValue visitFCOPYSIGN(SDNode *N);
238 SDValue visitSINT_TO_FP(SDNode *N);
239 SDValue visitUINT_TO_FP(SDNode *N);
240 SDValue visitFP_TO_SINT(SDNode *N);
241 SDValue visitFP_TO_UINT(SDNode *N);
242 SDValue visitFP_ROUND(SDNode *N);
243 SDValue visitFP_ROUND_INREG(SDNode *N);
244 SDValue visitFP_EXTEND(SDNode *N);
245 SDValue visitFNEG(SDNode *N);
246 SDValue visitFABS(SDNode *N);
247 SDValue visitFCEIL(SDNode *N);
248 SDValue visitFTRUNC(SDNode *N);
249 SDValue visitFFLOOR(SDNode *N);
250 SDValue visitBRCOND(SDNode *N);
251 SDValue visitBR_CC(SDNode *N);
252 SDValue visitLOAD(SDNode *N);
253 SDValue visitSTORE(SDNode *N);
254 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
255 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
256 SDValue visitBUILD_VECTOR(SDNode *N);
257 SDValue visitCONCAT_VECTORS(SDNode *N);
258 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
259 SDValue visitVECTOR_SHUFFLE(SDNode *N);
261 SDValue XformToShuffleWithZero(SDNode *N);
262 SDValue ReassociateOps(unsigned Opc, SDLoc DL, SDValue LHS, SDValue RHS);
264 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
266 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
267 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
268 SDValue SimplifySelect(SDLoc DL, SDValue N0, SDValue N1, SDValue N2);
269 SDValue SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1, SDValue N2,
270 SDValue N3, ISD::CondCode CC,
271 bool NotExtCompare = false);
272 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
273 SDLoc DL, bool foldBooleans = true);
274 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
276 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
277 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
278 SDValue BuildSDIV(SDNode *N);
279 SDValue BuildUDIV(SDNode *N);
280 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
281 bool DemandHighBits = true);
282 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
283 SDNode *MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL);
284 SDValue ReduceLoadWidth(SDNode *N);
285 SDValue ReduceLoadOpStoreWidth(SDNode *N);
286 SDValue TransformFPLoadStorePair(SDNode *N);
287 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N);
288 SDValue reduceBuildVecConvertToConvertBuildVec(SDNode *N);
290 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
292 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
293 /// looking for aliasing nodes and adding them to the Aliases vector.
294 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
295 SmallVectorImpl<SDValue> &Aliases);
297 /// isAlias - Return true if there is any possibility that the two addresses
299 bool isAlias(SDValue Ptr1, int64_t Size1, bool IsVolatile1,
300 const Value *SrcValue1, int SrcValueOffset1,
301 unsigned SrcValueAlign1,
302 const MDNode *TBAAInfo1,
303 SDValue Ptr2, int64_t Size2, bool IsVolatile2,
304 const Value *SrcValue2, int SrcValueOffset2,
305 unsigned SrcValueAlign2,
306 const MDNode *TBAAInfo2) const;
308 /// isAlias - Return true if there is any possibility that the two addresses
310 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1);
312 /// FindAliasInfo - Extracts the relevant alias information from the memory
313 /// node. Returns true if the operand was a load.
314 bool FindAliasInfo(SDNode *N,
315 SDValue &Ptr, int64_t &Size, bool &IsVolatile,
316 const Value *&SrcValue, int &SrcValueOffset,
317 unsigned &SrcValueAlignment,
318 const MDNode *&TBAAInfo) const;
320 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
321 /// looking for a better chain (aliasing node.)
322 SDValue FindBetterChain(SDNode *N, SDValue Chain);
324 /// Merge consecutive store operations into a wide store.
325 /// This optimization uses wide integers or vectors when possible.
326 /// \return True if some memory operations were changed.
327 bool MergeConsecutiveStores(StoreSDNode *N);
330 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
331 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
332 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {
333 AttributeSet FnAttrs =
334 DAG.getMachineFunction().getFunction()->getAttributes();
336 FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
337 Attribute::OptimizeForSize) ||
338 FnAttrs.hasAttribute(AttributeSet::FunctionIndex, Attribute::MinSize);
341 /// Run - runs the dag combiner on all nodes in the work list
342 void Run(CombineLevel AtLevel);
344 SelectionDAG &getDAG() const { return DAG; }
346 /// getShiftAmountTy - Returns a type large enough to hold any valid
347 /// shift amount - before type legalization these can be huge.
348 EVT getShiftAmountTy(EVT LHSTy) {
349 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
350 if (LHSTy.isVector())
352 return LegalTypes ? TLI.getScalarShiftAmountTy(LHSTy)
353 : TLI.getPointerTy();
356 /// isTypeLegal - This method returns true if we are running before type
357 /// legalization or if the specified VT is legal.
358 bool isTypeLegal(const EVT &VT) {
359 if (!LegalTypes) return true;
360 return TLI.isTypeLegal(VT);
363 /// getSetCCResultType - Convenience wrapper around
364 /// TargetLowering::getSetCCResultType
365 EVT getSetCCResultType(EVT VT) const {
366 return TLI.getSetCCResultType(*DAG.getContext(), VT);
373 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
374 /// nodes from the worklist.
375 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
378 explicit WorkListRemover(DAGCombiner &dc)
379 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
381 virtual void NodeDeleted(SDNode *N, SDNode *E) {
382 DC.removeFromWorkList(N);
387 //===----------------------------------------------------------------------===//
388 // TargetLowering::DAGCombinerInfo implementation
389 //===----------------------------------------------------------------------===//
391 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
392 ((DAGCombiner*)DC)->AddToWorkList(N);
395 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
396 ((DAGCombiner*)DC)->removeFromWorkList(N);
399 SDValue TargetLowering::DAGCombinerInfo::
400 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
401 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
404 SDValue TargetLowering::DAGCombinerInfo::
405 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
406 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
410 SDValue TargetLowering::DAGCombinerInfo::
411 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
412 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
415 void TargetLowering::DAGCombinerInfo::
416 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
417 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
420 //===----------------------------------------------------------------------===//
422 //===----------------------------------------------------------------------===//
424 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
425 /// specified expression for the same cost as the expression itself, or 2 if we
426 /// can compute the negated form more cheaply than the expression itself.
427 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
428 const TargetLowering &TLI,
429 const TargetOptions *Options,
430 unsigned Depth = 0) {
431 // fneg is removable even if it has multiple uses.
432 if (Op.getOpcode() == ISD::FNEG) return 2;
434 // Don't allow anything with multiple uses.
435 if (!Op.hasOneUse()) return 0;
437 // Don't recurse exponentially.
438 if (Depth > 6) return 0;
440 switch (Op.getOpcode()) {
441 default: return false;
442 case ISD::ConstantFP:
443 // Don't invert constant FP values after legalize. The negated constant
444 // isn't necessarily legal.
445 return LegalOperations ? 0 : 1;
447 // FIXME: determine better conditions for this xform.
448 if (!Options->UnsafeFPMath) return 0;
450 // After operation legalization, it might not be legal to create new FSUBs.
451 if (LegalOperations &&
452 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
455 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
456 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
459 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
460 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
463 // We can't turn -(A-B) into B-A when we honor signed zeros.
464 if (!Options->UnsafeFPMath) return 0;
466 // fold (fneg (fsub A, B)) -> (fsub B, A)
471 if (Options->HonorSignDependentRoundingFPMath()) return 0;
473 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
474 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
478 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
484 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
489 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
490 /// returns the newly negated expression.
491 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
492 bool LegalOperations, unsigned Depth = 0) {
493 // fneg is removable even if it has multiple uses.
494 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
496 // Don't allow anything with multiple uses.
497 assert(Op.hasOneUse() && "Unknown reuse!");
499 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
500 switch (Op.getOpcode()) {
501 default: llvm_unreachable("Unknown code");
502 case ISD::ConstantFP: {
503 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
505 return DAG.getConstantFP(V, Op.getValueType());
508 // FIXME: determine better conditions for this xform.
509 assert(DAG.getTarget().Options.UnsafeFPMath);
511 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
512 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
513 DAG.getTargetLoweringInfo(),
514 &DAG.getTarget().Options, Depth+1))
515 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
516 GetNegatedExpression(Op.getOperand(0), DAG,
517 LegalOperations, Depth+1),
519 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
520 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
521 GetNegatedExpression(Op.getOperand(1), DAG,
522 LegalOperations, Depth+1),
525 // We can't turn -(A-B) into B-A when we honor signed zeros.
526 assert(DAG.getTarget().Options.UnsafeFPMath);
528 // fold (fneg (fsub 0, B)) -> B
529 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
530 if (N0CFP->getValueAPF().isZero())
531 return Op.getOperand(1);
533 // fold (fneg (fsub A, B)) -> (fsub B, A)
534 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
535 Op.getOperand(1), Op.getOperand(0));
539 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath());
541 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
542 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
543 DAG.getTargetLoweringInfo(),
544 &DAG.getTarget().Options, Depth+1))
545 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
546 GetNegatedExpression(Op.getOperand(0), DAG,
547 LegalOperations, Depth+1),
550 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
551 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
553 GetNegatedExpression(Op.getOperand(1), DAG,
554 LegalOperations, Depth+1));
558 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
559 GetNegatedExpression(Op.getOperand(0), DAG,
560 LegalOperations, Depth+1));
562 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(),
563 GetNegatedExpression(Op.getOperand(0), DAG,
564 LegalOperations, Depth+1),
570 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
571 // that selects between the values 1 and 0, making it equivalent to a setcc.
572 // Also, set the incoming LHS, RHS, and CC references to the appropriate
573 // nodes based on the type of node we are checking. This simplifies life a
574 // bit for the callers.
575 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
577 if (N.getOpcode() == ISD::SETCC) {
578 LHS = N.getOperand(0);
579 RHS = N.getOperand(1);
580 CC = N.getOperand(2);
583 if (N.getOpcode() == ISD::SELECT_CC &&
584 N.getOperand(2).getOpcode() == ISD::Constant &&
585 N.getOperand(3).getOpcode() == ISD::Constant &&
586 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
587 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
588 LHS = N.getOperand(0);
589 RHS = N.getOperand(1);
590 CC = N.getOperand(4);
596 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
597 // one use. If this is true, it allows the users to invert the operation for
598 // free when it is profitable to do so.
599 static bool isOneUseSetCC(SDValue N) {
601 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
606 SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDLoc DL,
607 SDValue N0, SDValue N1) {
608 EVT VT = N0.getValueType();
609 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
610 if (isa<ConstantSDNode>(N1)) {
611 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
613 DAG.FoldConstantArithmetic(Opc, VT,
614 cast<ConstantSDNode>(N0.getOperand(1)),
615 cast<ConstantSDNode>(N1));
616 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
618 if (N0.hasOneUse()) {
619 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
620 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT,
621 N0.getOperand(0), N1);
622 AddToWorkList(OpNode.getNode());
623 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
627 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
628 if (isa<ConstantSDNode>(N0)) {
629 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
631 DAG.FoldConstantArithmetic(Opc, VT,
632 cast<ConstantSDNode>(N1.getOperand(1)),
633 cast<ConstantSDNode>(N0));
634 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
636 if (N1.hasOneUse()) {
637 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
638 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT,
639 N1.getOperand(0), N0);
640 AddToWorkList(OpNode.getNode());
641 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
648 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
650 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
652 DEBUG(dbgs() << "\nReplacing.1 ";
654 dbgs() << "\nWith: ";
655 To[0].getNode()->dump(&DAG);
656 dbgs() << " and " << NumTo-1 << " other values\n";
657 for (unsigned i = 0, e = NumTo; i != e; ++i)
658 assert((!To[i].getNode() ||
659 N->getValueType(i) == To[i].getValueType()) &&
660 "Cannot combine value to value of different type!"));
661 WorkListRemover DeadNodes(*this);
662 DAG.ReplaceAllUsesWith(N, To);
664 // Push the new nodes and any users onto the worklist
665 for (unsigned i = 0, e = NumTo; i != e; ++i) {
666 if (To[i].getNode()) {
667 AddToWorkList(To[i].getNode());
668 AddUsersToWorkList(To[i].getNode());
673 // Finally, if the node is now dead, remove it from the graph. The node
674 // may not be dead if the replacement process recursively simplified to
675 // something else needing this node.
676 if (N->use_empty()) {
677 // Nodes can be reintroduced into the worklist. Make sure we do not
678 // process a node that has been replaced.
679 removeFromWorkList(N);
681 // Finally, since the node is now dead, remove it from the graph.
684 return SDValue(N, 0);
688 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
689 // Replace all uses. If any nodes become isomorphic to other nodes and
690 // are deleted, make sure to remove them from our worklist.
691 WorkListRemover DeadNodes(*this);
692 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
694 // Push the new node and any (possibly new) users onto the worklist.
695 AddToWorkList(TLO.New.getNode());
696 AddUsersToWorkList(TLO.New.getNode());
698 // Finally, if the node is now dead, remove it from the graph. The node
699 // may not be dead if the replacement process recursively simplified to
700 // something else needing this node.
701 if (TLO.Old.getNode()->use_empty()) {
702 removeFromWorkList(TLO.Old.getNode());
704 // If the operands of this node are only used by the node, they will now
705 // be dead. Make sure to visit them first to delete dead nodes early.
706 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
707 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
708 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
710 DAG.DeleteNode(TLO.Old.getNode());
714 /// SimplifyDemandedBits - Check the specified integer node value to see if
715 /// it can be simplified or if things it uses can be simplified by bit
716 /// propagation. If so, return true.
717 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
718 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
719 APInt KnownZero, KnownOne;
720 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
724 AddToWorkList(Op.getNode());
726 // Replace the old value with the new one.
728 DEBUG(dbgs() << "\nReplacing.2 ";
729 TLO.Old.getNode()->dump(&DAG);
730 dbgs() << "\nWith: ";
731 TLO.New.getNode()->dump(&DAG);
734 CommitTargetLoweringOpt(TLO);
738 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
740 EVT VT = Load->getValueType(0);
741 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
743 DEBUG(dbgs() << "\nReplacing.9 ";
745 dbgs() << "\nWith: ";
746 Trunc.getNode()->dump(&DAG);
748 WorkListRemover DeadNodes(*this);
749 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
750 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
751 removeFromWorkList(Load);
752 DAG.DeleteNode(Load);
753 AddToWorkList(Trunc.getNode());
756 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
759 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
760 EVT MemVT = LD->getMemoryVT();
761 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
762 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
764 : LD->getExtensionType();
766 return DAG.getExtLoad(ExtType, dl, PVT,
767 LD->getChain(), LD->getBasePtr(),
768 MemVT, LD->getMemOperand());
771 unsigned Opc = Op.getOpcode();
774 case ISD::AssertSext:
775 return DAG.getNode(ISD::AssertSext, dl, PVT,
776 SExtPromoteOperand(Op.getOperand(0), PVT),
778 case ISD::AssertZext:
779 return DAG.getNode(ISD::AssertZext, dl, PVT,
780 ZExtPromoteOperand(Op.getOperand(0), PVT),
782 case ISD::Constant: {
784 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
785 return DAG.getNode(ExtOpc, dl, PVT, Op);
789 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
791 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
794 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
795 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
797 EVT OldVT = Op.getValueType();
799 bool Replace = false;
800 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
801 if (NewOp.getNode() == 0)
803 AddToWorkList(NewOp.getNode());
806 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
807 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
808 DAG.getValueType(OldVT));
811 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
812 EVT OldVT = Op.getValueType();
814 bool Replace = false;
815 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
816 if (NewOp.getNode() == 0)
818 AddToWorkList(NewOp.getNode());
821 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
822 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
825 /// PromoteIntBinOp - Promote the specified integer binary operation if the
826 /// target indicates it is beneficial. e.g. On x86, it's usually better to
827 /// promote i16 operations to i32 since i16 instructions are longer.
828 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
829 if (!LegalOperations)
832 EVT VT = Op.getValueType();
833 if (VT.isVector() || !VT.isInteger())
836 // If operation type is 'undesirable', e.g. i16 on x86, consider
838 unsigned Opc = Op.getOpcode();
839 if (TLI.isTypeDesirableForOp(Opc, VT))
843 // Consult target whether it is a good idea to promote this operation and
844 // what's the right type to promote it to.
845 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
846 assert(PVT != VT && "Don't know what type to promote to!");
848 bool Replace0 = false;
849 SDValue N0 = Op.getOperand(0);
850 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
851 if (NN0.getNode() == 0)
854 bool Replace1 = false;
855 SDValue N1 = Op.getOperand(1);
860 NN1 = PromoteOperand(N1, PVT, Replace1);
861 if (NN1.getNode() == 0)
865 AddToWorkList(NN0.getNode());
867 AddToWorkList(NN1.getNode());
870 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
872 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
874 DEBUG(dbgs() << "\nPromoting ";
875 Op.getNode()->dump(&DAG));
877 return DAG.getNode(ISD::TRUNCATE, dl, VT,
878 DAG.getNode(Opc, dl, PVT, NN0, NN1));
883 /// PromoteIntShiftOp - Promote the specified integer shift operation if the
884 /// target indicates it is beneficial. e.g. On x86, it's usually better to
885 /// promote i16 operations to i32 since i16 instructions are longer.
886 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
887 if (!LegalOperations)
890 EVT VT = Op.getValueType();
891 if (VT.isVector() || !VT.isInteger())
894 // If operation type is 'undesirable', e.g. i16 on x86, consider
896 unsigned Opc = Op.getOpcode();
897 if (TLI.isTypeDesirableForOp(Opc, VT))
901 // Consult target whether it is a good idea to promote this operation and
902 // what's the right type to promote it to.
903 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
904 assert(PVT != VT && "Don't know what type to promote to!");
906 bool Replace = false;
907 SDValue N0 = Op.getOperand(0);
909 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
910 else if (Opc == ISD::SRL)
911 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
913 N0 = PromoteOperand(N0, PVT, Replace);
914 if (N0.getNode() == 0)
917 AddToWorkList(N0.getNode());
919 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
921 DEBUG(dbgs() << "\nPromoting ";
922 Op.getNode()->dump(&DAG));
924 return DAG.getNode(ISD::TRUNCATE, dl, VT,
925 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
930 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
931 if (!LegalOperations)
934 EVT VT = Op.getValueType();
935 if (VT.isVector() || !VT.isInteger())
938 // If operation type is 'undesirable', e.g. i16 on x86, consider
940 unsigned Opc = Op.getOpcode();
941 if (TLI.isTypeDesirableForOp(Opc, VT))
945 // Consult target whether it is a good idea to promote this operation and
946 // what's the right type to promote it to.
947 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
948 assert(PVT != VT && "Don't know what type to promote to!");
949 // fold (aext (aext x)) -> (aext x)
950 // fold (aext (zext x)) -> (zext x)
951 // fold (aext (sext x)) -> (sext x)
952 DEBUG(dbgs() << "\nPromoting ";
953 Op.getNode()->dump(&DAG));
954 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0));
959 bool DAGCombiner::PromoteLoad(SDValue Op) {
960 if (!LegalOperations)
963 EVT VT = Op.getValueType();
964 if (VT.isVector() || !VT.isInteger())
967 // If operation type is 'undesirable', e.g. i16 on x86, consider
969 unsigned Opc = Op.getOpcode();
970 if (TLI.isTypeDesirableForOp(Opc, VT))
974 // Consult target whether it is a good idea to promote this operation and
975 // what's the right type to promote it to.
976 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
977 assert(PVT != VT && "Don't know what type to promote to!");
980 SDNode *N = Op.getNode();
981 LoadSDNode *LD = cast<LoadSDNode>(N);
982 EVT MemVT = LD->getMemoryVT();
983 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
984 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
986 : LD->getExtensionType();
987 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
988 LD->getChain(), LD->getBasePtr(),
989 MemVT, LD->getMemOperand());
990 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
992 DEBUG(dbgs() << "\nPromoting ";
995 Result.getNode()->dump(&DAG);
997 WorkListRemover DeadNodes(*this);
998 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
999 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
1000 removeFromWorkList(N);
1002 AddToWorkList(Result.getNode());
1009 //===----------------------------------------------------------------------===//
1010 // Main DAG Combiner implementation
1011 //===----------------------------------------------------------------------===//
1013 void DAGCombiner::Run(CombineLevel AtLevel) {
1014 // set the instance variables, so that the various visit routines may use it.
1016 LegalOperations = Level >= AfterLegalizeVectorOps;
1017 LegalTypes = Level >= AfterLegalizeTypes;
1019 // Add all the dag nodes to the worklist.
1020 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
1021 E = DAG.allnodes_end(); I != E; ++I)
1024 // Create a dummy node (which is not added to allnodes), that adds a reference
1025 // to the root node, preventing it from being deleted, and tracking any
1026 // changes of the root.
1027 HandleSDNode Dummy(DAG.getRoot());
1029 // The root of the dag may dangle to deleted nodes until the dag combiner is
1030 // done. Set it to null to avoid confusion.
1031 DAG.setRoot(SDValue());
1033 // while the worklist isn't empty, find a node and
1034 // try and combine it.
1035 while (!WorkListContents.empty()) {
1037 // The WorkListOrder holds the SDNodes in order, but it may contain
1039 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the
1040 // worklist *should* contain, and check the node we want to visit is should
1041 // actually be visited.
1043 N = WorkListOrder.pop_back_val();
1044 } while (!WorkListContents.erase(N));
1046 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1047 // N is deleted from the DAG, since they too may now be dead or may have a
1048 // reduced number of uses, allowing other xforms.
1049 if (N->use_empty() && N != &Dummy) {
1050 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1051 AddToWorkList(N->getOperand(i).getNode());
1057 SDValue RV = combine(N);
1059 if (RV.getNode() == 0)
1064 // If we get back the same node we passed in, rather than a new node or
1065 // zero, we know that the node must have defined multiple values and
1066 // CombineTo was used. Since CombineTo takes care of the worklist
1067 // mechanics for us, we have no work to do in this case.
1068 if (RV.getNode() == N)
1071 assert(N->getOpcode() != ISD::DELETED_NODE &&
1072 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1073 "Node was deleted but visit returned new node!");
1075 DEBUG(dbgs() << "\nReplacing.3 ";
1077 dbgs() << "\nWith: ";
1078 RV.getNode()->dump(&DAG);
1081 // Transfer debug value.
1082 DAG.TransferDbgValues(SDValue(N, 0), RV);
1083 WorkListRemover DeadNodes(*this);
1084 if (N->getNumValues() == RV.getNode()->getNumValues())
1085 DAG.ReplaceAllUsesWith(N, RV.getNode());
1087 assert(N->getValueType(0) == RV.getValueType() &&
1088 N->getNumValues() == 1 && "Type mismatch");
1090 DAG.ReplaceAllUsesWith(N, &OpV);
1093 // Push the new node and any users onto the worklist
1094 AddToWorkList(RV.getNode());
1095 AddUsersToWorkList(RV.getNode());
1097 // Add any uses of the old node to the worklist in case this node is the
1098 // last one that uses them. They may become dead after this node is
1100 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1101 AddToWorkList(N->getOperand(i).getNode());
1103 // Finally, if the node is now dead, remove it from the graph. The node
1104 // may not be dead if the replacement process recursively simplified to
1105 // something else needing this node.
1106 if (N->use_empty()) {
1107 // Nodes can be reintroduced into the worklist. Make sure we do not
1108 // process a node that has been replaced.
1109 removeFromWorkList(N);
1111 // Finally, since the node is now dead, remove it from the graph.
1116 // If the root changed (e.g. it was a dead load, update the root).
1117 DAG.setRoot(Dummy.getValue());
1118 DAG.RemoveDeadNodes();
1121 SDValue DAGCombiner::visit(SDNode *N) {
1122 switch (N->getOpcode()) {
1124 case ISD::TokenFactor: return visitTokenFactor(N);
1125 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1126 case ISD::ADD: return visitADD(N);
1127 case ISD::SUB: return visitSUB(N);
1128 case ISD::ADDC: return visitADDC(N);
1129 case ISD::SUBC: return visitSUBC(N);
1130 case ISD::ADDE: return visitADDE(N);
1131 case ISD::SUBE: return visitSUBE(N);
1132 case ISD::MUL: return visitMUL(N);
1133 case ISD::SDIV: return visitSDIV(N);
1134 case ISD::UDIV: return visitUDIV(N);
1135 case ISD::SREM: return visitSREM(N);
1136 case ISD::UREM: return visitUREM(N);
1137 case ISD::MULHU: return visitMULHU(N);
1138 case ISD::MULHS: return visitMULHS(N);
1139 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1140 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1141 case ISD::SMULO: return visitSMULO(N);
1142 case ISD::UMULO: return visitUMULO(N);
1143 case ISD::SDIVREM: return visitSDIVREM(N);
1144 case ISD::UDIVREM: return visitUDIVREM(N);
1145 case ISD::AND: return visitAND(N);
1146 case ISD::OR: return visitOR(N);
1147 case ISD::XOR: return visitXOR(N);
1148 case ISD::SHL: return visitSHL(N);
1149 case ISD::SRA: return visitSRA(N);
1150 case ISD::SRL: return visitSRL(N);
1151 case ISD::CTLZ: return visitCTLZ(N);
1152 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1153 case ISD::CTTZ: return visitCTTZ(N);
1154 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1155 case ISD::CTPOP: return visitCTPOP(N);
1156 case ISD::SELECT: return visitSELECT(N);
1157 case ISD::VSELECT: return visitVSELECT(N);
1158 case ISD::SELECT_CC: return visitSELECT_CC(N);
1159 case ISD::SETCC: return visitSETCC(N);
1160 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1161 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1162 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1163 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1164 case ISD::TRUNCATE: return visitTRUNCATE(N);
1165 case ISD::BITCAST: return visitBITCAST(N);
1166 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1167 case ISD::FADD: return visitFADD(N);
1168 case ISD::FSUB: return visitFSUB(N);
1169 case ISD::FMUL: return visitFMUL(N);
1170 case ISD::FMA: return visitFMA(N);
1171 case ISD::FDIV: return visitFDIV(N);
1172 case ISD::FREM: return visitFREM(N);
1173 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1174 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1175 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1176 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1177 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1178 case ISD::FP_ROUND: return visitFP_ROUND(N);
1179 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1180 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1181 case ISD::FNEG: return visitFNEG(N);
1182 case ISD::FABS: return visitFABS(N);
1183 case ISD::FFLOOR: return visitFFLOOR(N);
1184 case ISD::FCEIL: return visitFCEIL(N);
1185 case ISD::FTRUNC: return visitFTRUNC(N);
1186 case ISD::BRCOND: return visitBRCOND(N);
1187 case ISD::BR_CC: return visitBR_CC(N);
1188 case ISD::LOAD: return visitLOAD(N);
1189 case ISD::STORE: return visitSTORE(N);
1190 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1191 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1192 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1193 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1194 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1195 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1200 SDValue DAGCombiner::combine(SDNode *N) {
1201 SDValue RV = visit(N);
1203 // If nothing happened, try a target-specific DAG combine.
1204 if (RV.getNode() == 0) {
1205 assert(N->getOpcode() != ISD::DELETED_NODE &&
1206 "Node was deleted but visit returned NULL!");
1208 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1209 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1211 // Expose the DAG combiner to the target combiner impls.
1212 TargetLowering::DAGCombinerInfo
1213 DagCombineInfo(DAG, Level, false, this);
1215 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1219 // If nothing happened still, try promoting the operation.
1220 if (RV.getNode() == 0) {
1221 switch (N->getOpcode()) {
1229 RV = PromoteIntBinOp(SDValue(N, 0));
1234 RV = PromoteIntShiftOp(SDValue(N, 0));
1236 case ISD::SIGN_EXTEND:
1237 case ISD::ZERO_EXTEND:
1238 case ISD::ANY_EXTEND:
1239 RV = PromoteExtend(SDValue(N, 0));
1242 if (PromoteLoad(SDValue(N, 0)))
1248 // If N is a commutative binary node, try commuting it to enable more
1250 if (RV.getNode() == 0 &&
1251 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1252 N->getNumValues() == 1) {
1253 SDValue N0 = N->getOperand(0);
1254 SDValue N1 = N->getOperand(1);
1256 // Constant operands are canonicalized to RHS.
1257 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1258 SDValue Ops[] = { N1, N0 };
1259 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1262 return SDValue(CSENode, 0);
1269 /// getInputChainForNode - Given a node, return its input chain if it has one,
1270 /// otherwise return a null sd operand.
1271 static SDValue getInputChainForNode(SDNode *N) {
1272 if (unsigned NumOps = N->getNumOperands()) {
1273 if (N->getOperand(0).getValueType() == MVT::Other)
1274 return N->getOperand(0);
1275 if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1276 return N->getOperand(NumOps-1);
1277 for (unsigned i = 1; i < NumOps-1; ++i)
1278 if (N->getOperand(i).getValueType() == MVT::Other)
1279 return N->getOperand(i);
1284 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1285 // If N has two operands, where one has an input chain equal to the other,
1286 // the 'other' chain is redundant.
1287 if (N->getNumOperands() == 2) {
1288 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1289 return N->getOperand(0);
1290 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1291 return N->getOperand(1);
1294 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1295 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1296 SmallPtrSet<SDNode*, 16> SeenOps;
1297 bool Changed = false; // If we should replace this token factor.
1299 // Start out with this token factor.
1302 // Iterate through token factors. The TFs grows when new token factors are
1304 for (unsigned i = 0; i < TFs.size(); ++i) {
1305 SDNode *TF = TFs[i];
1307 // Check each of the operands.
1308 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1309 SDValue Op = TF->getOperand(i);
1311 switch (Op.getOpcode()) {
1312 case ISD::EntryToken:
1313 // Entry tokens don't need to be added to the list. They are
1318 case ISD::TokenFactor:
1319 if (Op.hasOneUse() &&
1320 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1321 // Queue up for processing.
1322 TFs.push_back(Op.getNode());
1323 // Clean up in case the token factor is removed.
1324 AddToWorkList(Op.getNode());
1331 // Only add if it isn't already in the list.
1332 if (SeenOps.insert(Op.getNode()))
1343 // If we've change things around then replace token factor.
1346 // The entry token is the only possible outcome.
1347 Result = DAG.getEntryNode();
1349 // New and improved token factor.
1350 Result = DAG.getNode(ISD::TokenFactor, SDLoc(N),
1351 MVT::Other, &Ops[0], Ops.size());
1354 // Don't add users to work list.
1355 return CombineTo(N, Result, false);
1361 /// MERGE_VALUES can always be eliminated.
1362 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1363 WorkListRemover DeadNodes(*this);
1364 // Replacing results may cause a different MERGE_VALUES to suddenly
1365 // be CSE'd with N, and carry its uses with it. Iterate until no
1366 // uses remain, to ensure that the node can be safely deleted.
1367 // First add the users of this node to the work list so that they
1368 // can be tried again once they have new operands.
1369 AddUsersToWorkList(N);
1371 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1372 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i));
1373 } while (!N->use_empty());
1374 removeFromWorkList(N);
1376 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1380 SDValue combineShlAddConstant(SDLoc DL, SDValue N0, SDValue N1,
1381 SelectionDAG &DAG) {
1382 EVT VT = N0.getValueType();
1383 SDValue N00 = N0.getOperand(0);
1384 SDValue N01 = N0.getOperand(1);
1385 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1387 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1388 isa<ConstantSDNode>(N00.getOperand(1))) {
1389 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1390 N0 = DAG.getNode(ISD::ADD, SDLoc(N0), VT,
1391 DAG.getNode(ISD::SHL, SDLoc(N00), VT,
1392 N00.getOperand(0), N01),
1393 DAG.getNode(ISD::SHL, SDLoc(N01), VT,
1394 N00.getOperand(1), N01));
1395 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1401 SDValue DAGCombiner::visitADD(SDNode *N) {
1402 SDValue N0 = N->getOperand(0);
1403 SDValue N1 = N->getOperand(1);
1404 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1405 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1406 EVT VT = N0.getValueType();
1409 if (VT.isVector()) {
1410 SDValue FoldedVOp = SimplifyVBinOp(N);
1411 if (FoldedVOp.getNode()) return FoldedVOp;
1413 // fold (add x, 0) -> x, vector edition
1414 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1416 if (ISD::isBuildVectorAllZeros(N0.getNode()))
1420 // fold (add x, undef) -> undef
1421 if (N0.getOpcode() == ISD::UNDEF)
1423 if (N1.getOpcode() == ISD::UNDEF)
1425 // fold (add c1, c2) -> c1+c2
1427 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1428 // canonicalize constant to RHS
1430 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N1, N0);
1431 // fold (add x, 0) -> x
1432 if (N1C && N1C->isNullValue())
1434 // fold (add Sym, c) -> Sym+c
1435 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1436 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1437 GA->getOpcode() == ISD::GlobalAddress)
1438 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
1440 (uint64_t)N1C->getSExtValue());
1441 // fold ((c1-A)+c2) -> (c1+c2)-A
1442 if (N1C && N0.getOpcode() == ISD::SUB)
1443 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1444 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1445 DAG.getConstant(N1C->getAPIntValue()+
1446 N0C->getAPIntValue(), VT),
1449 SDValue RADD = ReassociateOps(ISD::ADD, SDLoc(N), N0, N1);
1450 if (RADD.getNode() != 0)
1452 // fold ((0-A) + B) -> B-A
1453 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1454 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1455 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1, N0.getOperand(1));
1456 // fold (A + (0-B)) -> A-B
1457 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1458 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1459 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1.getOperand(1));
1460 // fold (A+(B-A)) -> B
1461 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1462 return N1.getOperand(0);
1463 // fold ((B-A)+A) -> B
1464 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1465 return N0.getOperand(0);
1466 // fold (A+(B-(A+C))) to (B-C)
1467 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1468 N0 == N1.getOperand(1).getOperand(0))
1469 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
1470 N1.getOperand(1).getOperand(1));
1471 // fold (A+(B-(C+A))) to (B-C)
1472 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1473 N0 == N1.getOperand(1).getOperand(1))
1474 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
1475 N1.getOperand(1).getOperand(0));
1476 // fold (A+((B-A)+or-C)) to (B+or-C)
1477 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1478 N1.getOperand(0).getOpcode() == ISD::SUB &&
1479 N0 == N1.getOperand(0).getOperand(1))
1480 return DAG.getNode(N1.getOpcode(), SDLoc(N), VT,
1481 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1483 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1484 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1485 SDValue N00 = N0.getOperand(0);
1486 SDValue N01 = N0.getOperand(1);
1487 SDValue N10 = N1.getOperand(0);
1488 SDValue N11 = N1.getOperand(1);
1490 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1491 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1492 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10),
1493 DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11));
1496 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1497 return SDValue(N, 0);
1499 // fold (a+b) -> (a|b) iff a and b share no bits.
1500 if (VT.isInteger() && !VT.isVector()) {
1501 APInt LHSZero, LHSOne;
1502 APInt RHSZero, RHSOne;
1503 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne);
1505 if (LHSZero.getBoolValue()) {
1506 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne);
1508 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1509 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1510 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1511 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1);
1515 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1516 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1517 SDValue Result = combineShlAddConstant(SDLoc(N), N0, N1, DAG);
1518 if (Result.getNode()) return Result;
1520 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1521 SDValue Result = combineShlAddConstant(SDLoc(N), N1, N0, DAG);
1522 if (Result.getNode()) return Result;
1525 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1526 if (N1.getOpcode() == ISD::SHL &&
1527 N1.getOperand(0).getOpcode() == ISD::SUB)
1528 if (ConstantSDNode *C =
1529 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1530 if (C->getAPIntValue() == 0)
1531 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0,
1532 DAG.getNode(ISD::SHL, SDLoc(N), VT,
1533 N1.getOperand(0).getOperand(1),
1535 if (N0.getOpcode() == ISD::SHL &&
1536 N0.getOperand(0).getOpcode() == ISD::SUB)
1537 if (ConstantSDNode *C =
1538 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1539 if (C->getAPIntValue() == 0)
1540 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1,
1541 DAG.getNode(ISD::SHL, SDLoc(N), VT,
1542 N0.getOperand(0).getOperand(1),
1545 if (N1.getOpcode() == ISD::AND) {
1546 SDValue AndOp0 = N1.getOperand(0);
1547 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1548 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1549 unsigned DestBits = VT.getScalarType().getSizeInBits();
1551 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1552 // and similar xforms where the inner op is either ~0 or 0.
1553 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1555 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1559 // add (sext i1), X -> sub X, (zext i1)
1560 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1561 N0.getOperand(0).getValueType() == MVT::i1 &&
1562 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1564 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1565 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1571 SDValue DAGCombiner::visitADDC(SDNode *N) {
1572 SDValue N0 = N->getOperand(0);
1573 SDValue N1 = N->getOperand(1);
1574 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1575 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1576 EVT VT = N0.getValueType();
1578 // If the flag result is dead, turn this into an ADD.
1579 if (!N->hasAnyUseOfValue(1))
1580 return CombineTo(N, DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N1),
1581 DAG.getNode(ISD::CARRY_FALSE,
1582 SDLoc(N), MVT::Glue));
1584 // canonicalize constant to RHS.
1586 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N1, N0);
1588 // fold (addc x, 0) -> x + no carry out
1589 if (N1C && N1C->isNullValue())
1590 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1591 SDLoc(N), MVT::Glue));
1593 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1594 APInt LHSZero, LHSOne;
1595 APInt RHSZero, RHSOne;
1596 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne);
1598 if (LHSZero.getBoolValue()) {
1599 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne);
1601 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1602 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1603 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1604 return CombineTo(N, DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1),
1605 DAG.getNode(ISD::CARRY_FALSE,
1606 SDLoc(N), MVT::Glue));
1612 SDValue DAGCombiner::visitADDE(SDNode *N) {
1613 SDValue N0 = N->getOperand(0);
1614 SDValue N1 = N->getOperand(1);
1615 SDValue CarryIn = N->getOperand(2);
1616 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1617 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1619 // canonicalize constant to RHS
1621 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
1624 // fold (adde x, y, false) -> (addc x, y)
1625 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1626 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
1631 // Since it may not be valid to emit a fold to zero for vector initializers
1632 // check if we can before folding.
1633 static SDValue tryFoldToZero(SDLoc DL, const TargetLowering &TLI, EVT VT,
1635 bool LegalOperations, bool LegalTypes) {
1637 return DAG.getConstant(0, VT);
1638 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
1639 return DAG.getConstant(0, VT);
1643 SDValue DAGCombiner::visitSUB(SDNode *N) {
1644 SDValue N0 = N->getOperand(0);
1645 SDValue N1 = N->getOperand(1);
1646 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1647 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1648 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 :
1649 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1650 EVT VT = N0.getValueType();
1653 if (VT.isVector()) {
1654 SDValue FoldedVOp = SimplifyVBinOp(N);
1655 if (FoldedVOp.getNode()) return FoldedVOp;
1657 // fold (sub x, 0) -> x, vector edition
1658 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1662 // fold (sub x, x) -> 0
1663 // FIXME: Refactor this and xor and other similar operations together.
1665 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations, LegalTypes);
1666 // fold (sub c1, c2) -> c1-c2
1668 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1669 // fold (sub x, c) -> (add x, -c)
1671 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0,
1672 DAG.getConstant(-N1C->getAPIntValue(), VT));
1673 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1674 if (N0C && N0C->isAllOnesValue())
1675 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
1676 // fold A-(A-B) -> B
1677 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1678 return N1.getOperand(1);
1679 // fold (A+B)-A -> B
1680 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1681 return N0.getOperand(1);
1682 // fold (A+B)-B -> A
1683 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1684 return N0.getOperand(0);
1685 // fold C2-(A+C1) -> (C2-C1)-A
1686 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1687 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(),
1689 return DAG.getNode(ISD::SUB, SDLoc(N), VT, NewC,
1692 // fold ((A+(B+or-C))-B) -> A+or-C
1693 if (N0.getOpcode() == ISD::ADD &&
1694 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1695 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1696 N0.getOperand(1).getOperand(0) == N1)
1697 return DAG.getNode(N0.getOperand(1).getOpcode(), SDLoc(N), VT,
1698 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1699 // fold ((A+(C+B))-B) -> A+C
1700 if (N0.getOpcode() == ISD::ADD &&
1701 N0.getOperand(1).getOpcode() == ISD::ADD &&
1702 N0.getOperand(1).getOperand(1) == N1)
1703 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
1704 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1705 // fold ((A-(B-C))-C) -> A-B
1706 if (N0.getOpcode() == ISD::SUB &&
1707 N0.getOperand(1).getOpcode() == ISD::SUB &&
1708 N0.getOperand(1).getOperand(1) == N1)
1709 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1710 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1712 // If either operand of a sub is undef, the result is undef
1713 if (N0.getOpcode() == ISD::UNDEF)
1715 if (N1.getOpcode() == ISD::UNDEF)
1718 // If the relocation model supports it, consider symbol offsets.
1719 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1720 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1721 // fold (sub Sym, c) -> Sym-c
1722 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1723 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
1725 (uint64_t)N1C->getSExtValue());
1726 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1727 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1728 if (GA->getGlobal() == GB->getGlobal())
1729 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1736 SDValue DAGCombiner::visitSUBC(SDNode *N) {
1737 SDValue N0 = N->getOperand(0);
1738 SDValue N1 = N->getOperand(1);
1739 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1740 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1741 EVT VT = N0.getValueType();
1743 // If the flag result is dead, turn this into an SUB.
1744 if (!N->hasAnyUseOfValue(1))
1745 return CombineTo(N, DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1),
1746 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1749 // fold (subc x, x) -> 0 + no borrow
1751 return CombineTo(N, DAG.getConstant(0, VT),
1752 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1755 // fold (subc x, 0) -> x + no borrow
1756 if (N1C && N1C->isNullValue())
1757 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1760 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
1761 if (N0C && N0C->isAllOnesValue())
1762 return CombineTo(N, DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0),
1763 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1769 SDValue DAGCombiner::visitSUBE(SDNode *N) {
1770 SDValue N0 = N->getOperand(0);
1771 SDValue N1 = N->getOperand(1);
1772 SDValue CarryIn = N->getOperand(2);
1774 // fold (sube x, y, false) -> (subc x, y)
1775 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1776 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);
1781 /// isConstantSplatVector - Returns true if N is a BUILD_VECTOR node whose
1782 /// elements are all the same constant or undefined.
1783 static bool isConstantSplatVector(SDNode *N, APInt& SplatValue) {
1784 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(N);
1789 unsigned SplatBitSize;
1791 EVT EltVT = N->getValueType(0).getVectorElementType();
1792 return (C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
1794 EltVT.getSizeInBits() >= SplatBitSize);
1797 SDValue DAGCombiner::visitMUL(SDNode *N) {
1798 SDValue N0 = N->getOperand(0);
1799 SDValue N1 = N->getOperand(1);
1800 EVT VT = N0.getValueType();
1802 // fold (mul x, undef) -> 0
1803 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1804 return DAG.getConstant(0, VT);
1806 bool N0IsConst = false;
1807 bool N1IsConst = false;
1808 APInt ConstValue0, ConstValue1;
1810 if (VT.isVector()) {
1811 SDValue FoldedVOp = SimplifyVBinOp(N);
1812 if (FoldedVOp.getNode()) return FoldedVOp;
1814 N0IsConst = isConstantSplatVector(N0.getNode(), ConstValue0);
1815 N1IsConst = isConstantSplatVector(N1.getNode(), ConstValue1);
1817 N0IsConst = dyn_cast<ConstantSDNode>(N0) != 0;
1818 ConstValue0 = N0IsConst ? (dyn_cast<ConstantSDNode>(N0))->getAPIntValue()
1820 N1IsConst = dyn_cast<ConstantSDNode>(N1) != 0;
1821 ConstValue1 = N1IsConst ? (dyn_cast<ConstantSDNode>(N1))->getAPIntValue()
1825 // fold (mul c1, c2) -> c1*c2
1826 if (N0IsConst && N1IsConst)
1827 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0.getNode(), N1.getNode());
1829 // canonicalize constant to RHS
1830 if (N0IsConst && !N1IsConst)
1831 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
1832 // fold (mul x, 0) -> 0
1833 if (N1IsConst && ConstValue1 == 0)
1835 // We require a splat of the entire scalar bit width for non-contiguous
1838 ConstValue1.getBitWidth() == VT.getScalarType().getSizeInBits();
1839 // fold (mul x, 1) -> x
1840 if (N1IsConst && ConstValue1 == 1 && IsFullSplat)
1842 // fold (mul x, -1) -> 0-x
1843 if (N1IsConst && ConstValue1.isAllOnesValue())
1844 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1845 DAG.getConstant(0, VT), N0);
1846 // fold (mul x, (1 << c)) -> x << c
1847 if (N1IsConst && ConstValue1.isPowerOf2() && IsFullSplat)
1848 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
1849 DAG.getConstant(ConstValue1.logBase2(),
1850 getShiftAmountTy(N0.getValueType())));
1851 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1852 if (N1IsConst && (-ConstValue1).isPowerOf2() && IsFullSplat) {
1853 unsigned Log2Val = (-ConstValue1).logBase2();
1854 // FIXME: If the input is something that is easily negated (e.g. a
1855 // single-use add), we should put the negate there.
1856 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1857 DAG.getConstant(0, VT),
1858 DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
1859 DAG.getConstant(Log2Val,
1860 getShiftAmountTy(N0.getValueType()))));
1864 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1865 if (N1IsConst && N0.getOpcode() == ISD::SHL &&
1866 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
1867 isa<ConstantSDNode>(N0.getOperand(1)))) {
1868 SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT,
1869 N1, N0.getOperand(1));
1870 AddToWorkList(C3.getNode());
1871 return DAG.getNode(ISD::MUL, SDLoc(N), VT,
1872 N0.getOperand(0), C3);
1875 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1878 SDValue Sh(0,0), Y(0,0);
1879 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1880 if (N0.getOpcode() == ISD::SHL &&
1881 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
1882 isa<ConstantSDNode>(N0.getOperand(1))) &&
1883 N0.getNode()->hasOneUse()) {
1885 } else if (N1.getOpcode() == ISD::SHL &&
1886 isa<ConstantSDNode>(N1.getOperand(1)) &&
1887 N1.getNode()->hasOneUse()) {
1892 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
1893 Sh.getOperand(0), Y);
1894 return DAG.getNode(ISD::SHL, SDLoc(N), VT,
1895 Mul, Sh.getOperand(1));
1899 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1900 if (N1IsConst && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1901 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
1902 isa<ConstantSDNode>(N0.getOperand(1))))
1903 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
1904 DAG.getNode(ISD::MUL, SDLoc(N0), VT,
1905 N0.getOperand(0), N1),
1906 DAG.getNode(ISD::MUL, SDLoc(N1), VT,
1907 N0.getOperand(1), N1));
1910 SDValue RMUL = ReassociateOps(ISD::MUL, SDLoc(N), N0, N1);
1911 if (RMUL.getNode() != 0)
1917 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1918 SDValue N0 = N->getOperand(0);
1919 SDValue N1 = N->getOperand(1);
1920 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1921 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1922 EVT VT = N->getValueType(0);
1925 if (VT.isVector()) {
1926 SDValue FoldedVOp = SimplifyVBinOp(N);
1927 if (FoldedVOp.getNode()) return FoldedVOp;
1930 // fold (sdiv c1, c2) -> c1/c2
1931 if (N0C && N1C && !N1C->isNullValue())
1932 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1933 // fold (sdiv X, 1) -> X
1934 if (N1C && N1C->getAPIntValue() == 1LL)
1936 // fold (sdiv X, -1) -> 0-X
1937 if (N1C && N1C->isAllOnesValue())
1938 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1939 DAG.getConstant(0, VT), N0);
1940 // If we know the sign bits of both operands are zero, strength reduce to a
1941 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1942 if (!VT.isVector()) {
1943 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1944 return DAG.getNode(ISD::UDIV, SDLoc(N), N1.getValueType(),
1947 // fold (sdiv X, pow2) -> simple ops after legalize
1948 if (N1C && !N1C->isNullValue() &&
1949 (N1C->getAPIntValue().isPowerOf2() ||
1950 (-N1C->getAPIntValue()).isPowerOf2())) {
1951 // If dividing by powers of two is cheap, then don't perform the following
1953 if (TLI.isPow2DivCheap())
1956 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
1958 // Splat the sign bit into the register
1959 SDValue SGN = DAG.getNode(ISD::SRA, SDLoc(N), VT, N0,
1960 DAG.getConstant(VT.getSizeInBits()-1,
1961 getShiftAmountTy(N0.getValueType())));
1962 AddToWorkList(SGN.getNode());
1964 // Add (N0 < 0) ? abs2 - 1 : 0;
1965 SDValue SRL = DAG.getNode(ISD::SRL, SDLoc(N), VT, SGN,
1966 DAG.getConstant(VT.getSizeInBits() - lg2,
1967 getShiftAmountTy(SGN.getValueType())));
1968 SDValue ADD = DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, SRL);
1969 AddToWorkList(SRL.getNode());
1970 AddToWorkList(ADD.getNode()); // Divide by pow2
1971 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), VT, ADD,
1972 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
1974 // If we're dividing by a positive value, we're done. Otherwise, we must
1975 // negate the result.
1976 if (N1C->getAPIntValue().isNonNegative())
1979 AddToWorkList(SRA.getNode());
1980 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1981 DAG.getConstant(0, VT), SRA);
1984 // if integer divide is expensive and we satisfy the requirements, emit an
1985 // alternate sequence.
1986 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1987 SDValue Op = BuildSDIV(N);
1988 if (Op.getNode()) return Op;
1992 if (N0.getOpcode() == ISD::UNDEF)
1993 return DAG.getConstant(0, VT);
1994 // X / undef -> undef
1995 if (N1.getOpcode() == ISD::UNDEF)
2001 SDValue DAGCombiner::visitUDIV(SDNode *N) {
2002 SDValue N0 = N->getOperand(0);
2003 SDValue N1 = N->getOperand(1);
2004 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
2005 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
2006 EVT VT = N->getValueType(0);
2009 if (VT.isVector()) {
2010 SDValue FoldedVOp = SimplifyVBinOp(N);
2011 if (FoldedVOp.getNode()) return FoldedVOp;
2014 // fold (udiv c1, c2) -> c1/c2
2015 if (N0C && N1C && !N1C->isNullValue())
2016 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
2017 // fold (udiv x, (1 << c)) -> x >>u c
2018 if (N1C && N1C->getAPIntValue().isPowerOf2())
2019 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0,
2020 DAG.getConstant(N1C->getAPIntValue().logBase2(),
2021 getShiftAmountTy(N0.getValueType())));
2022 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
2023 if (N1.getOpcode() == ISD::SHL) {
2024 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2025 if (SHC->getAPIntValue().isPowerOf2()) {
2026 EVT ADDVT = N1.getOperand(1).getValueType();
2027 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N), ADDVT,
2029 DAG.getConstant(SHC->getAPIntValue()
2032 AddToWorkList(Add.getNode());
2033 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, Add);
2037 // fold (udiv x, c) -> alternate
2038 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
2039 SDValue Op = BuildUDIV(N);
2040 if (Op.getNode()) return Op;
2044 if (N0.getOpcode() == ISD::UNDEF)
2045 return DAG.getConstant(0, VT);
2046 // X / undef -> undef
2047 if (N1.getOpcode() == ISD::UNDEF)
2053 SDValue DAGCombiner::visitSREM(SDNode *N) {
2054 SDValue N0 = N->getOperand(0);
2055 SDValue N1 = N->getOperand(1);
2056 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2057 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2058 EVT VT = N->getValueType(0);
2060 // fold (srem c1, c2) -> c1%c2
2061 if (N0C && N1C && !N1C->isNullValue())
2062 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
2063 // If we know the sign bits of both operands are zero, strength reduce to a
2064 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
2065 if (!VT.isVector()) {
2066 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2067 return DAG.getNode(ISD::UREM, SDLoc(N), VT, N0, N1);
2070 // If X/C can be simplified by the division-by-constant logic, lower
2071 // X%C to the equivalent of X-X/C*C.
2072 if (N1C && !N1C->isNullValue()) {
2073 SDValue Div = DAG.getNode(ISD::SDIV, SDLoc(N), VT, N0, N1);
2074 AddToWorkList(Div.getNode());
2075 SDValue OptimizedDiv = combine(Div.getNode());
2076 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2077 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2079 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2080 AddToWorkList(Mul.getNode());
2086 if (N0.getOpcode() == ISD::UNDEF)
2087 return DAG.getConstant(0, VT);
2088 // X % undef -> undef
2089 if (N1.getOpcode() == ISD::UNDEF)
2095 SDValue DAGCombiner::visitUREM(SDNode *N) {
2096 SDValue N0 = N->getOperand(0);
2097 SDValue N1 = N->getOperand(1);
2098 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2099 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2100 EVT VT = N->getValueType(0);
2102 // fold (urem c1, c2) -> c1%c2
2103 if (N0C && N1C && !N1C->isNullValue())
2104 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
2105 // fold (urem x, pow2) -> (and x, pow2-1)
2106 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
2107 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0,
2108 DAG.getConstant(N1C->getAPIntValue()-1,VT));
2109 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
2110 if (N1.getOpcode() == ISD::SHL) {
2111 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2112 if (SHC->getAPIntValue().isPowerOf2()) {
2114 DAG.getNode(ISD::ADD, SDLoc(N), VT, N1,
2115 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
2117 AddToWorkList(Add.getNode());
2118 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, Add);
2123 // If X/C can be simplified by the division-by-constant logic, lower
2124 // X%C to the equivalent of X-X/C*C.
2125 if (N1C && !N1C->isNullValue()) {
2126 SDValue Div = DAG.getNode(ISD::UDIV, SDLoc(N), VT, N0, N1);
2127 AddToWorkList(Div.getNode());
2128 SDValue OptimizedDiv = combine(Div.getNode());
2129 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2130 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2132 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2133 AddToWorkList(Mul.getNode());
2139 if (N0.getOpcode() == ISD::UNDEF)
2140 return DAG.getConstant(0, VT);
2141 // X % undef -> undef
2142 if (N1.getOpcode() == ISD::UNDEF)
2148 SDValue DAGCombiner::visitMULHS(SDNode *N) {
2149 SDValue N0 = N->getOperand(0);
2150 SDValue N1 = N->getOperand(1);
2151 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2152 EVT VT = N->getValueType(0);
2155 // fold (mulhs x, 0) -> 0
2156 if (N1C && N1C->isNullValue())
2158 // fold (mulhs x, 1) -> (sra x, size(x)-1)
2159 if (N1C && N1C->getAPIntValue() == 1)
2160 return DAG.getNode(ISD::SRA, SDLoc(N), N0.getValueType(), N0,
2161 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2162 getShiftAmountTy(N0.getValueType())));
2163 // fold (mulhs x, undef) -> 0
2164 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2165 return DAG.getConstant(0, VT);
2167 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2169 if (VT.isSimple() && !VT.isVector()) {
2170 MVT Simple = VT.getSimpleVT();
2171 unsigned SimpleSize = Simple.getSizeInBits();
2172 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2173 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2174 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2175 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2176 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2177 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2178 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2179 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2186 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2187 SDValue N0 = N->getOperand(0);
2188 SDValue N1 = N->getOperand(1);
2189 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2190 EVT VT = N->getValueType(0);
2193 // fold (mulhu x, 0) -> 0
2194 if (N1C && N1C->isNullValue())
2196 // fold (mulhu x, 1) -> 0
2197 if (N1C && N1C->getAPIntValue() == 1)
2198 return DAG.getConstant(0, N0.getValueType());
2199 // fold (mulhu x, undef) -> 0
2200 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2201 return DAG.getConstant(0, VT);
2203 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2205 if (VT.isSimple() && !VT.isVector()) {
2206 MVT Simple = VT.getSimpleVT();
2207 unsigned SimpleSize = Simple.getSizeInBits();
2208 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2209 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2210 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2211 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2212 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2213 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2214 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2215 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2222 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
2223 /// compute two values. LoOp and HiOp give the opcodes for the two computations
2224 /// that are being performed. Return true if a simplification was made.
2226 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2228 // If the high half is not needed, just compute the low half.
2229 bool HiExists = N->hasAnyUseOfValue(1);
2231 (!LegalOperations ||
2232 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
2233 SDValue Res = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0),
2234 N->op_begin(), N->getNumOperands());
2235 return CombineTo(N, Res, Res);
2238 // If the low half is not needed, just compute the high half.
2239 bool LoExists = N->hasAnyUseOfValue(0);
2241 (!LegalOperations ||
2242 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2243 SDValue Res = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1),
2244 N->op_begin(), N->getNumOperands());
2245 return CombineTo(N, Res, Res);
2248 // If both halves are used, return as it is.
2249 if (LoExists && HiExists)
2252 // If the two computed results can be simplified separately, separate them.
2254 SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0),
2255 N->op_begin(), N->getNumOperands());
2256 AddToWorkList(Lo.getNode());
2257 SDValue LoOpt = combine(Lo.getNode());
2258 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2259 (!LegalOperations ||
2260 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2261 return CombineTo(N, LoOpt, LoOpt);
2265 SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1),
2266 N->op_begin(), N->getNumOperands());
2267 AddToWorkList(Hi.getNode());
2268 SDValue HiOpt = combine(Hi.getNode());
2269 if (HiOpt.getNode() && HiOpt != Hi &&
2270 (!LegalOperations ||
2271 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2272 return CombineTo(N, HiOpt, HiOpt);
2278 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2279 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2280 if (Res.getNode()) return Res;
2282 EVT VT = N->getValueType(0);
2285 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2287 if (VT.isSimple() && !VT.isVector()) {
2288 MVT Simple = VT.getSimpleVT();
2289 unsigned SimpleSize = Simple.getSizeInBits();
2290 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2291 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2292 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2293 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2294 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2295 // Compute the high part as N1.
2296 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2297 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2298 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2299 // Compute the low part as N0.
2300 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2301 return CombineTo(N, Lo, Hi);
2308 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2309 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2310 if (Res.getNode()) return Res;
2312 EVT VT = N->getValueType(0);
2315 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2317 if (VT.isSimple() && !VT.isVector()) {
2318 MVT Simple = VT.getSimpleVT();
2319 unsigned SimpleSize = Simple.getSizeInBits();
2320 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2321 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2322 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2323 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2324 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2325 // Compute the high part as N1.
2326 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2327 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2328 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2329 // Compute the low part as N0.
2330 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2331 return CombineTo(N, Lo, Hi);
2338 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2339 // (smulo x, 2) -> (saddo x, x)
2340 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2341 if (C2->getAPIntValue() == 2)
2342 return DAG.getNode(ISD::SADDO, SDLoc(N), N->getVTList(),
2343 N->getOperand(0), N->getOperand(0));
2348 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2349 // (umulo x, 2) -> (uaddo x, x)
2350 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2351 if (C2->getAPIntValue() == 2)
2352 return DAG.getNode(ISD::UADDO, SDLoc(N), N->getVTList(),
2353 N->getOperand(0), N->getOperand(0));
2358 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2359 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2360 if (Res.getNode()) return Res;
2365 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2366 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2367 if (Res.getNode()) return Res;
2372 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2373 /// two operands of the same opcode, try to simplify it.
2374 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2375 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2376 EVT VT = N0.getValueType();
2377 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2379 // Bail early if none of these transforms apply.
2380 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2382 // For each of OP in AND/OR/XOR:
2383 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2384 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2385 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2386 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2388 // do not sink logical op inside of a vector extend, since it may combine
2390 EVT Op0VT = N0.getOperand(0).getValueType();
2391 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2392 N0.getOpcode() == ISD::SIGN_EXTEND ||
2393 // Avoid infinite looping with PromoteIntBinOp.
2394 (N0.getOpcode() == ISD::ANY_EXTEND &&
2395 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2396 (N0.getOpcode() == ISD::TRUNCATE &&
2397 (!TLI.isZExtFree(VT, Op0VT) ||
2398 !TLI.isTruncateFree(Op0VT, VT)) &&
2399 TLI.isTypeLegal(Op0VT))) &&
2401 Op0VT == N1.getOperand(0).getValueType() &&
2402 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2403 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2404 N0.getOperand(0).getValueType(),
2405 N0.getOperand(0), N1.getOperand(0));
2406 AddToWorkList(ORNode.getNode());
2407 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, ORNode);
2410 // For each of OP in SHL/SRL/SRA/AND...
2411 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2412 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2413 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2414 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2415 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2416 N0.getOperand(1) == N1.getOperand(1)) {
2417 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2418 N0.getOperand(0).getValueType(),
2419 N0.getOperand(0), N1.getOperand(0));
2420 AddToWorkList(ORNode.getNode());
2421 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
2422 ORNode, N0.getOperand(1));
2425 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
2426 // Only perform this optimization after type legalization and before
2427 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
2428 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
2429 // we don't want to undo this promotion.
2430 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
2432 if ((N0.getOpcode() == ISD::BITCAST ||
2433 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) &&
2434 Level == AfterLegalizeTypes) {
2435 SDValue In0 = N0.getOperand(0);
2436 SDValue In1 = N1.getOperand(0);
2437 EVT In0Ty = In0.getValueType();
2438 EVT In1Ty = In1.getValueType();
2440 // If both incoming values are integers, and the original types are the
2442 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) {
2443 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1);
2444 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op);
2445 AddToWorkList(Op.getNode());
2450 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
2451 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
2452 // If both shuffles use the same mask, and both shuffle within a single
2453 // vector, then it is worthwhile to move the swizzle after the operation.
2454 // The type-legalizer generates this pattern when loading illegal
2455 // vector types from memory. In many cases this allows additional shuffle
2457 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
2458 N0.getOperand(1).getOpcode() == ISD::UNDEF &&
2459 N1.getOperand(1).getOpcode() == ISD::UNDEF) {
2460 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
2461 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
2463 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() &&
2464 "Inputs to shuffles are not the same type");
2466 unsigned NumElts = VT.getVectorNumElements();
2468 // Check that both shuffles use the same mask. The masks are known to be of
2469 // the same length because the result vector type is the same.
2470 bool SameMask = true;
2471 for (unsigned i = 0; i != NumElts; ++i) {
2472 int Idx0 = SVN0->getMaskElt(i);
2473 int Idx1 = SVN1->getMaskElt(i);
2481 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
2482 N0.getOperand(0), N1.getOperand(0));
2483 AddToWorkList(Op.getNode());
2484 return DAG.getVectorShuffle(VT, SDLoc(N), Op,
2485 DAG.getUNDEF(VT), &SVN0->getMask()[0]);
2492 SDValue DAGCombiner::visitAND(SDNode *N) {
2493 SDValue N0 = N->getOperand(0);
2494 SDValue N1 = N->getOperand(1);
2495 SDValue LL, LR, RL, RR, CC0, CC1;
2496 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2497 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2498 EVT VT = N1.getValueType();
2499 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2502 if (VT.isVector()) {
2503 SDValue FoldedVOp = SimplifyVBinOp(N);
2504 if (FoldedVOp.getNode()) return FoldedVOp;
2506 // fold (and x, 0) -> 0, vector edition
2507 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2509 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2512 // fold (and x, -1) -> x, vector edition
2513 if (ISD::isBuildVectorAllOnes(N0.getNode()))
2515 if (ISD::isBuildVectorAllOnes(N1.getNode()))
2519 // fold (and x, undef) -> 0
2520 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2521 return DAG.getConstant(0, VT);
2522 // fold (and c1, c2) -> c1&c2
2524 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2525 // canonicalize constant to RHS
2527 return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
2528 // fold (and x, -1) -> x
2529 if (N1C && N1C->isAllOnesValue())
2531 // if (and x, c) is known to be zero, return 0
2532 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2533 APInt::getAllOnesValue(BitWidth)))
2534 return DAG.getConstant(0, VT);
2536 SDValue RAND = ReassociateOps(ISD::AND, SDLoc(N), N0, N1);
2537 if (RAND.getNode() != 0)
2539 // fold (and (or x, C), D) -> D if (C & D) == D
2540 if (N1C && N0.getOpcode() == ISD::OR)
2541 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2542 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2544 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2545 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2546 SDValue N0Op0 = N0.getOperand(0);
2547 APInt Mask = ~N1C->getAPIntValue();
2548 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2549 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2550 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
2551 N0.getValueType(), N0Op0);
2553 // Replace uses of the AND with uses of the Zero extend node.
2556 // We actually want to replace all uses of the any_extend with the
2557 // zero_extend, to avoid duplicating things. This will later cause this
2558 // AND to be folded.
2559 CombineTo(N0.getNode(), Zext);
2560 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2563 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
2564 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
2565 // already be zero by virtue of the width of the base type of the load.
2567 // the 'X' node here can either be nothing or an extract_vector_elt to catch
2569 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
2570 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
2571 N0.getOpcode() == ISD::LOAD) {
2572 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
2573 N0 : N0.getOperand(0) );
2575 // Get the constant (if applicable) the zero'th operand is being ANDed with.
2576 // This can be a pure constant or a vector splat, in which case we treat the
2577 // vector as a scalar and use the splat value.
2578 APInt Constant = APInt::getNullValue(1);
2579 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
2580 Constant = C->getAPIntValue();
2581 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
2582 APInt SplatValue, SplatUndef;
2583 unsigned SplatBitSize;
2585 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
2586 SplatBitSize, HasAnyUndefs);
2588 // Undef bits can contribute to a possible optimisation if set, so
2590 SplatValue |= SplatUndef;
2592 // The splat value may be something like "0x00FFFFFF", which means 0 for
2593 // the first vector value and FF for the rest, repeating. We need a mask
2594 // that will apply equally to all members of the vector, so AND all the
2595 // lanes of the constant together.
2596 EVT VT = Vector->getValueType(0);
2597 unsigned BitWidth = VT.getVectorElementType().getSizeInBits();
2599 // If the splat value has been compressed to a bitlength lower
2600 // than the size of the vector lane, we need to re-expand it to
2602 if (BitWidth > SplatBitSize)
2603 for (SplatValue = SplatValue.zextOrTrunc(BitWidth);
2604 SplatBitSize < BitWidth;
2605 SplatBitSize = SplatBitSize * 2)
2606 SplatValue |= SplatValue.shl(SplatBitSize);
2608 Constant = APInt::getAllOnesValue(BitWidth);
2609 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i)
2610 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
2614 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
2615 // actually legal and isn't going to get expanded, else this is a false
2617 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
2618 Load->getMemoryVT());
2620 // Resize the constant to the same size as the original memory access before
2621 // extension. If it is still the AllOnesValue then this AND is completely
2624 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits());
2627 switch (Load->getExtensionType()) {
2628 default: B = false; break;
2629 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
2631 case ISD::NON_EXTLOAD: B = true; break;
2634 if (B && Constant.isAllOnesValue()) {
2635 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
2636 // preserve semantics once we get rid of the AND.
2637 SDValue NewLoad(Load, 0);
2638 if (Load->getExtensionType() == ISD::EXTLOAD) {
2639 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
2640 Load->getValueType(0), SDLoc(Load),
2641 Load->getChain(), Load->getBasePtr(),
2642 Load->getOffset(), Load->getMemoryVT(),
2643 Load->getMemOperand());
2644 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
2645 if (Load->getNumValues() == 3) {
2646 // PRE/POST_INC loads have 3 values.
2647 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
2648 NewLoad.getValue(2) };
2649 CombineTo(Load, To, 3, true);
2651 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
2655 // Fold the AND away, taking care not to fold to the old load node if we
2657 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
2659 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2662 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2663 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2664 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2665 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2667 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2668 LL.getValueType().isInteger()) {
2669 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2670 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2671 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2672 LR.getValueType(), LL, RL);
2673 AddToWorkList(ORNode.getNode());
2674 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
2676 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2677 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2678 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(N0),
2679 LR.getValueType(), LL, RL);
2680 AddToWorkList(ANDNode.getNode());
2681 return DAG.getSetCC(SDLoc(N), VT, ANDNode, LR, Op1);
2683 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2684 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2685 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2686 LR.getValueType(), LL, RL);
2687 AddToWorkList(ORNode.getNode());
2688 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
2691 // Simplify (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2)
2692 if (LL == RL && isa<ConstantSDNode>(LR) && isa<ConstantSDNode>(RR) &&
2693 Op0 == Op1 && LL.getValueType().isInteger() &&
2694 Op0 == ISD::SETNE && ((cast<ConstantSDNode>(LR)->isNullValue() &&
2695 cast<ConstantSDNode>(RR)->isAllOnesValue()) ||
2696 (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2697 cast<ConstantSDNode>(RR)->isNullValue()))) {
2698 SDValue ADDNode = DAG.getNode(ISD::ADD, SDLoc(N0), LL.getValueType(),
2699 LL, DAG.getConstant(1, LL.getValueType()));
2700 AddToWorkList(ADDNode.getNode());
2701 return DAG.getSetCC(SDLoc(N), VT, ADDNode,
2702 DAG.getConstant(2, LL.getValueType()), ISD::SETUGE);
2704 // canonicalize equivalent to ll == rl
2705 if (LL == RR && LR == RL) {
2706 Op1 = ISD::getSetCCSwappedOperands(Op1);
2709 if (LL == RL && LR == RR) {
2710 bool isInteger = LL.getValueType().isInteger();
2711 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2712 if (Result != ISD::SETCC_INVALID &&
2713 (!LegalOperations ||
2714 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
2715 TLI.isOperationLegal(ISD::SETCC,
2716 getSetCCResultType(N0.getSimpleValueType())))))
2717 return DAG.getSetCC(SDLoc(N), N0.getValueType(),
2722 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2723 if (N0.getOpcode() == N1.getOpcode()) {
2724 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2725 if (Tmp.getNode()) return Tmp;
2728 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2729 // fold (and (sra)) -> (and (srl)) when possible.
2730 if (!VT.isVector() &&
2731 SimplifyDemandedBits(SDValue(N, 0)))
2732 return SDValue(N, 0);
2734 // fold (zext_inreg (extload x)) -> (zextload x)
2735 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2736 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2737 EVT MemVT = LN0->getMemoryVT();
2738 // If we zero all the possible extended bits, then we can turn this into
2739 // a zextload if we are running before legalize or the operation is legal.
2740 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2741 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2742 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2743 ((!LegalOperations && !LN0->isVolatile()) ||
2744 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2745 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
2746 LN0->getChain(), LN0->getBasePtr(),
2747 MemVT, LN0->getMemOperand());
2749 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2750 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2753 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2754 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2756 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2757 EVT MemVT = LN0->getMemoryVT();
2758 // If we zero all the possible extended bits, then we can turn this into
2759 // a zextload if we are running before legalize or the operation is legal.
2760 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2761 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2762 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2763 ((!LegalOperations && !LN0->isVolatile()) ||
2764 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2765 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
2766 LN0->getChain(), LN0->getBasePtr(),
2767 MemVT, LN0->getMemOperand());
2769 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2770 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2774 // fold (and (load x), 255) -> (zextload x, i8)
2775 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2776 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2777 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2778 (N0.getOpcode() == ISD::ANY_EXTEND &&
2779 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2780 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2781 LoadSDNode *LN0 = HasAnyExt
2782 ? cast<LoadSDNode>(N0.getOperand(0))
2783 : cast<LoadSDNode>(N0);
2784 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2785 LN0->isUnindexed() && N0.hasOneUse() && SDValue(LN0, 0).hasOneUse()) {
2786 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2787 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2788 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2789 EVT LoadedVT = LN0->getMemoryVT();
2791 if (ExtVT == LoadedVT &&
2792 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2793 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2796 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
2797 LN0->getChain(), LN0->getBasePtr(), ExtVT,
2798 LN0->getMemOperand());
2800 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2801 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2804 // Do not change the width of a volatile load.
2805 // Do not generate loads of non-round integer types since these can
2806 // be expensive (and would be wrong if the type is not byte sized).
2807 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2808 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2809 EVT PtrType = LN0->getOperand(1).getValueType();
2811 unsigned Alignment = LN0->getAlignment();
2812 SDValue NewPtr = LN0->getBasePtr();
2814 // For big endian targets, we need to add an offset to the pointer
2815 // to load the correct bytes. For little endian systems, we merely
2816 // need to read fewer bytes from the same pointer.
2817 if (TLI.isBigEndian()) {
2818 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2819 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2820 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2821 NewPtr = DAG.getNode(ISD::ADD, SDLoc(LN0), PtrType,
2822 NewPtr, DAG.getConstant(PtrOff, PtrType));
2823 Alignment = MinAlign(Alignment, PtrOff);
2826 AddToWorkList(NewPtr.getNode());
2828 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2830 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
2831 LN0->getChain(), NewPtr,
2832 LN0->getPointerInfo(),
2833 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2834 Alignment, LN0->getTBAAInfo());
2836 CombineTo(LN0, Load, Load.getValue(1));
2837 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2843 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
2844 VT.getSizeInBits() <= 64) {
2845 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2846 APInt ADDC = ADDI->getAPIntValue();
2847 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2848 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
2849 // immediate for an add, but it is legal if its top c2 bits are set,
2850 // transform the ADD so the immediate doesn't need to be materialized
2852 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
2853 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
2854 SRLI->getZExtValue());
2855 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
2857 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2859 DAG.getNode(ISD::ADD, SDLoc(N0), VT,
2860 N0.getOperand(0), DAG.getConstant(ADDC, VT));
2861 CombineTo(N0.getNode(), NewAdd);
2862 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2870 // fold (and (or (srl N, 8), (shl N, 8)), 0xffff) -> (srl (bswap N), const)
2871 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
2872 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
2873 N0.getOperand(1), false);
2874 if (BSwap.getNode())
2881 /// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16
2883 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
2884 bool DemandHighBits) {
2885 if (!LegalOperations)
2888 EVT VT = N->getValueType(0);
2889 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
2891 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2894 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
2895 bool LookPassAnd0 = false;
2896 bool LookPassAnd1 = false;
2897 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2899 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
2901 if (N0.getOpcode() == ISD::AND) {
2902 if (!N0.getNode()->hasOneUse())
2904 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2905 if (!N01C || N01C->getZExtValue() != 0xFF00)
2907 N0 = N0.getOperand(0);
2908 LookPassAnd0 = true;
2911 if (N1.getOpcode() == ISD::AND) {
2912 if (!N1.getNode()->hasOneUse())
2914 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2915 if (!N11C || N11C->getZExtValue() != 0xFF)
2917 N1 = N1.getOperand(0);
2918 LookPassAnd1 = true;
2921 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2923 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2925 if (!N0.getNode()->hasOneUse() ||
2926 !N1.getNode()->hasOneUse())
2929 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2930 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2933 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
2936 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
2937 SDValue N00 = N0->getOperand(0);
2938 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
2939 if (!N00.getNode()->hasOneUse())
2941 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
2942 if (!N001C || N001C->getZExtValue() != 0xFF)
2944 N00 = N00.getOperand(0);
2945 LookPassAnd0 = true;
2948 SDValue N10 = N1->getOperand(0);
2949 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
2950 if (!N10.getNode()->hasOneUse())
2952 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
2953 if (!N101C || N101C->getZExtValue() != 0xFF00)
2955 N10 = N10.getOperand(0);
2956 LookPassAnd1 = true;
2962 // Make sure everything beyond the low halfword gets set to zero since the SRL
2963 // 16 will clear the top bits.
2964 unsigned OpSizeInBits = VT.getSizeInBits();
2965 if (DemandHighBits && OpSizeInBits > 16) {
2966 // If the left-shift isn't masked out then the only way this is a bswap is
2967 // if all bits beyond the low 8 are 0. In that case the entire pattern
2968 // reduces to a left shift anyway: leave it for other parts of the combiner.
2972 // However, if the right shift isn't masked out then it might be because
2973 // it's not needed. See if we can spot that too.
2974 if (!LookPassAnd1 &&
2975 !DAG.MaskedValueIsZero(
2976 N10, APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - 16)))
2980 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00);
2981 if (OpSizeInBits > 16)
2982 Res = DAG.getNode(ISD::SRL, SDLoc(N), VT, Res,
2983 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT)));
2987 /// isBSwapHWordElement - Return true if the specified node is an element
2988 /// that makes up a 32-bit packed halfword byteswap. i.e.
2989 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2990 static bool isBSwapHWordElement(SDValue N, SmallVectorImpl<SDNode *> &Parts) {
2991 if (!N.getNode()->hasOneUse())
2994 unsigned Opc = N.getOpcode();
2995 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
2998 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3003 switch (N1C->getZExtValue()) {
3006 case 0xFF: Num = 0; break;
3007 case 0xFF00: Num = 1; break;
3008 case 0xFF0000: Num = 2; break;
3009 case 0xFF000000: Num = 3; break;
3012 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
3013 SDValue N0 = N.getOperand(0);
3014 if (Opc == ISD::AND) {
3015 if (Num == 0 || Num == 2) {
3017 // (x >> 8) & 0xff0000
3018 if (N0.getOpcode() != ISD::SRL)
3020 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3021 if (!C || C->getZExtValue() != 8)
3024 // (x << 8) & 0xff00
3025 // (x << 8) & 0xff000000
3026 if (N0.getOpcode() != ISD::SHL)
3028 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3029 if (!C || C->getZExtValue() != 8)
3032 } else if (Opc == ISD::SHL) {
3034 // (x & 0xff0000) << 8
3035 if (Num != 0 && Num != 2)
3037 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3038 if (!C || C->getZExtValue() != 8)
3040 } else { // Opc == ISD::SRL
3041 // (x & 0xff00) >> 8
3042 // (x & 0xff000000) >> 8
3043 if (Num != 1 && Num != 3)
3045 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3046 if (!C || C->getZExtValue() != 8)
3053 Parts[Num] = N0.getOperand(0).getNode();
3057 /// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is
3058 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
3059 /// => (rotl (bswap x), 16)
3060 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
3061 if (!LegalOperations)
3064 EVT VT = N->getValueType(0);
3067 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
3070 SmallVector<SDNode*,4> Parts(4, (SDNode*)0);
3072 // (or (or (and), (and)), (or (and), (and)))
3073 // (or (or (or (and), (and)), (and)), (and))
3074 if (N0.getOpcode() != ISD::OR)
3076 SDValue N00 = N0.getOperand(0);
3077 SDValue N01 = N0.getOperand(1);
3079 if (N1.getOpcode() == ISD::OR &&
3080 N00.getNumOperands() == 2 && N01.getNumOperands() == 2) {
3081 // (or (or (and), (and)), (or (and), (and)))
3082 SDValue N000 = N00.getOperand(0);
3083 if (!isBSwapHWordElement(N000, Parts))
3086 SDValue N001 = N00.getOperand(1);
3087 if (!isBSwapHWordElement(N001, Parts))
3089 SDValue N010 = N01.getOperand(0);
3090 if (!isBSwapHWordElement(N010, Parts))
3092 SDValue N011 = N01.getOperand(1);
3093 if (!isBSwapHWordElement(N011, Parts))
3096 // (or (or (or (and), (and)), (and)), (and))
3097 if (!isBSwapHWordElement(N1, Parts))
3099 if (!isBSwapHWordElement(N01, Parts))
3101 if (N00.getOpcode() != ISD::OR)
3103 SDValue N000 = N00.getOperand(0);
3104 if (!isBSwapHWordElement(N000, Parts))
3106 SDValue N001 = N00.getOperand(1);
3107 if (!isBSwapHWordElement(N001, Parts))
3111 // Make sure the parts are all coming from the same node.
3112 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
3115 SDValue BSwap = DAG.getNode(ISD::BSWAP, SDLoc(N), VT,
3116 SDValue(Parts[0],0));
3118 // Result of the bswap should be rotated by 16. If it's not legal, then
3119 // do (x << 16) | (x >> 16).
3120 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT));
3121 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
3122 return DAG.getNode(ISD::ROTL, SDLoc(N), VT, BSwap, ShAmt);
3123 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
3124 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, BSwap, ShAmt);
3125 return DAG.getNode(ISD::OR, SDLoc(N), VT,
3126 DAG.getNode(ISD::SHL, SDLoc(N), VT, BSwap, ShAmt),
3127 DAG.getNode(ISD::SRL, SDLoc(N), VT, BSwap, ShAmt));
3130 SDValue DAGCombiner::visitOR(SDNode *N) {
3131 SDValue N0 = N->getOperand(0);
3132 SDValue N1 = N->getOperand(1);
3133 SDValue LL, LR, RL, RR, CC0, CC1;
3134 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3135 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3136 EVT VT = N1.getValueType();
3139 if (VT.isVector()) {
3140 SDValue FoldedVOp = SimplifyVBinOp(N);
3141 if (FoldedVOp.getNode()) return FoldedVOp;
3143 // fold (or x, 0) -> x, vector edition
3144 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3146 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3149 // fold (or x, -1) -> -1, vector edition
3150 if (ISD::isBuildVectorAllOnes(N0.getNode()))
3152 if (ISD::isBuildVectorAllOnes(N1.getNode()))
3156 // fold (or x, undef) -> -1
3157 if (!LegalOperations &&
3158 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
3159 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
3160 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
3162 // fold (or c1, c2) -> c1|c2
3164 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
3165 // canonicalize constant to RHS
3167 return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0);
3168 // fold (or x, 0) -> x
3169 if (N1C && N1C->isNullValue())
3171 // fold (or x, -1) -> -1
3172 if (N1C && N1C->isAllOnesValue())
3174 // fold (or x, c) -> c iff (x & ~c) == 0
3175 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
3178 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
3179 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
3180 if (BSwap.getNode() != 0)
3182 BSwap = MatchBSwapHWordLow(N, N0, N1);
3183 if (BSwap.getNode() != 0)
3187 SDValue ROR = ReassociateOps(ISD::OR, SDLoc(N), N0, N1);
3188 if (ROR.getNode() != 0)
3190 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
3191 // iff (c1 & c2) == 0.
3192 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3193 isa<ConstantSDNode>(N0.getOperand(1))) {
3194 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
3195 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
3196 return DAG.getNode(ISD::AND, SDLoc(N), VT,
3197 DAG.getNode(ISD::OR, SDLoc(N0), VT,
3198 N0.getOperand(0), N1),
3199 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
3201 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
3202 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
3203 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
3204 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
3206 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
3207 LL.getValueType().isInteger()) {
3208 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
3209 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
3210 if (cast<ConstantSDNode>(LR)->isNullValue() &&
3211 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
3212 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(LR),
3213 LR.getValueType(), LL, RL);
3214 AddToWorkList(ORNode.getNode());
3215 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
3217 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
3218 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
3219 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
3220 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
3221 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(LR),
3222 LR.getValueType(), LL, RL);
3223 AddToWorkList(ANDNode.getNode());
3224 return DAG.getSetCC(SDLoc(N), VT, ANDNode, LR, Op1);
3227 // canonicalize equivalent to ll == rl
3228 if (LL == RR && LR == RL) {
3229 Op1 = ISD::getSetCCSwappedOperands(Op1);
3232 if (LL == RL && LR == RR) {
3233 bool isInteger = LL.getValueType().isInteger();
3234 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
3235 if (Result != ISD::SETCC_INVALID &&
3236 (!LegalOperations ||
3237 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
3238 TLI.isOperationLegal(ISD::SETCC,
3239 getSetCCResultType(N0.getValueType())))))
3240 return DAG.getSetCC(SDLoc(N), N0.getValueType(),
3245 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
3246 if (N0.getOpcode() == N1.getOpcode()) {
3247 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3248 if (Tmp.getNode()) return Tmp;
3251 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
3252 if (N0.getOpcode() == ISD::AND &&
3253 N1.getOpcode() == ISD::AND &&
3254 N0.getOperand(1).getOpcode() == ISD::Constant &&
3255 N1.getOperand(1).getOpcode() == ISD::Constant &&
3256 // Don't increase # computations.
3257 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3258 // We can only do this xform if we know that bits from X that are set in C2
3259 // but not in C1 are already zero. Likewise for Y.
3260 const APInt &LHSMask =
3261 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3262 const APInt &RHSMask =
3263 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
3265 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
3266 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
3267 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
3268 N0.getOperand(0), N1.getOperand(0));
3269 return DAG.getNode(ISD::AND, SDLoc(N), VT, X,
3270 DAG.getConstant(LHSMask | RHSMask, VT));
3274 // See if this is some rotate idiom.
3275 if (SDNode *Rot = MatchRotate(N0, N1, SDLoc(N)))
3276 return SDValue(Rot, 0);
3278 // Simplify the operands using demanded-bits information.
3279 if (!VT.isVector() &&
3280 SimplifyDemandedBits(SDValue(N, 0)))
3281 return SDValue(N, 0);
3286 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
3287 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
3288 if (Op.getOpcode() == ISD::AND) {
3289 if (isa<ConstantSDNode>(Op.getOperand(1))) {
3290 Mask = Op.getOperand(1);
3291 Op = Op.getOperand(0);
3297 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3305 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
3306 // idioms for rotate, and if the target supports rotation instructions, generate
3308 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL) {
3309 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
3310 EVT VT = LHS.getValueType();
3311 if (!TLI.isTypeLegal(VT)) return 0;
3313 // The target must have at least one rotate flavor.
3314 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
3315 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
3316 if (!HasROTL && !HasROTR) return 0;
3318 // Match "(X shl/srl V1) & V2" where V2 may not be present.
3319 SDValue LHSShift; // The shift.
3320 SDValue LHSMask; // AND value if any.
3321 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
3322 return 0; // Not part of a rotate.
3324 SDValue RHSShift; // The shift.
3325 SDValue RHSMask; // AND value if any.
3326 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
3327 return 0; // Not part of a rotate.
3329 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
3330 return 0; // Not shifting the same value.
3332 if (LHSShift.getOpcode() == RHSShift.getOpcode())
3333 return 0; // Shifts must disagree.
3335 // Canonicalize shl to left side in a shl/srl pair.
3336 if (RHSShift.getOpcode() == ISD::SHL) {
3337 std::swap(LHS, RHS);
3338 std::swap(LHSShift, RHSShift);
3339 std::swap(LHSMask , RHSMask );
3342 unsigned OpSizeInBits = VT.getSizeInBits();
3343 SDValue LHSShiftArg = LHSShift.getOperand(0);
3344 SDValue LHSShiftAmt = LHSShift.getOperand(1);
3345 SDValue RHSShiftArg = RHSShift.getOperand(0);
3346 SDValue RHSShiftAmt = RHSShift.getOperand(1);
3348 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
3349 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
3350 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
3351 RHSShiftAmt.getOpcode() == ISD::Constant) {
3352 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
3353 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
3354 if ((LShVal + RShVal) != OpSizeInBits)
3357 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3358 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt);
3360 // If there is an AND of either shifted operand, apply it to the result.
3361 if (LHSMask.getNode() || RHSMask.getNode()) {
3362 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
3364 if (LHSMask.getNode()) {
3365 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
3366 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
3368 if (RHSMask.getNode()) {
3369 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
3370 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
3373 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
3376 return Rot.getNode();
3379 // If there is a mask here, and we have a variable shift, we can't be sure
3380 // that we're masking out the right stuff.
3381 if (LHSMask.getNode() || RHSMask.getNode())
3384 // If the shift amount is sign/zext/any-extended just peel it off.
3385 SDValue LExtOp0 = LHSShiftAmt;
3386 SDValue RExtOp0 = RHSShiftAmt;
3387 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3388 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3389 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3390 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3391 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3392 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3393 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3394 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3395 LExtOp0 = LHSShiftAmt.getOperand(0);
3396 RExtOp0 = RHSShiftAmt.getOperand(0);
3399 if (RExtOp0.getOpcode() == ISD::SUB && RExtOp0.getOperand(1) == LExtOp0) {
3400 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3402 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3403 // (rotr x, (sub 32, y))
3404 if (ConstantSDNode *SUBC =
3405 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
3406 if (SUBC->getAPIntValue() == OpSizeInBits) {
3407 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg,
3408 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
3409 } else if (LHSShiftArg.getOpcode() == ISD::ZERO_EXTEND ||
3410 LHSShiftArg.getOpcode() == ISD::ANY_EXTEND) {
3411 // fold (or (shl (*ext x), (*ext y)),
3412 // (srl (*ext x), (*ext (sub 32, y)))) ->
3413 // (*ext (rotl x, y))
3414 // fold (or (shl (*ext x), (*ext y)),
3415 // (srl (*ext x), (*ext (sub 32, y)))) ->
3416 // (*ext (rotr x, (sub 32, y)))
3417 SDValue LArgExtOp0 = LHSShiftArg.getOperand(0);
3418 EVT LArgVT = LArgExtOp0.getValueType();
3419 bool HasROTRWithLArg = TLI.isOperationLegalOrCustom(ISD::ROTR, LArgVT);
3420 bool HasROTLWithLArg = TLI.isOperationLegalOrCustom(ISD::ROTL, LArgVT);
3421 if (HasROTRWithLArg || HasROTLWithLArg) {
3422 if (LArgVT.getSizeInBits() == SUBC->getAPIntValue()) {
3424 DAG.getNode(HasROTLWithLArg ? ISD::ROTL : ISD::ROTR, DL, LArgVT,
3425 LArgExtOp0, HasROTL ? LHSShiftAmt : RHSShiftAmt);
3426 return DAG.getNode(LHSShiftArg.getOpcode(), DL, VT, V).getNode();
3431 } else if (LExtOp0.getOpcode() == ISD::SUB &&
3432 RExtOp0 == LExtOp0.getOperand(1)) {
3433 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3435 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3436 // (rotl x, (sub 32, y))
3437 if (ConstantSDNode *SUBC =
3438 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
3439 if (SUBC->getAPIntValue() == OpSizeInBits) {
3440 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, LHSShiftArg,
3441 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
3442 } else if (RHSShiftArg.getOpcode() == ISD::ZERO_EXTEND ||
3443 RHSShiftArg.getOpcode() == ISD::ANY_EXTEND) {
3444 // fold (or (shl (*ext x), (*ext (sub 32, y))),
3445 // (srl (*ext x), (*ext y))) ->
3446 // (*ext (rotl x, y))
3447 // fold (or (shl (*ext x), (*ext (sub 32, y))),
3448 // (srl (*ext x), (*ext y))) ->
3449 // (*ext (rotr x, (sub 32, y)))
3450 SDValue RArgExtOp0 = RHSShiftArg.getOperand(0);
3451 EVT RArgVT = RArgExtOp0.getValueType();
3452 bool HasROTRWithRArg = TLI.isOperationLegalOrCustom(ISD::ROTR, RArgVT);
3453 bool HasROTLWithRArg = TLI.isOperationLegalOrCustom(ISD::ROTL, RArgVT);
3454 if (HasROTRWithRArg || HasROTLWithRArg) {
3455 if (RArgVT.getSizeInBits() == SUBC->getAPIntValue()) {
3457 DAG.getNode(HasROTRWithRArg ? ISD::ROTR : ISD::ROTL, DL, RArgVT,
3458 RArgExtOp0, HasROTR ? RHSShiftAmt : LHSShiftAmt);
3459 return DAG.getNode(RHSShiftArg.getOpcode(), DL, VT, V).getNode();
3469 SDValue DAGCombiner::visitXOR(SDNode *N) {
3470 SDValue N0 = N->getOperand(0);
3471 SDValue N1 = N->getOperand(1);
3472 SDValue LHS, RHS, CC;
3473 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3474 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3475 EVT VT = N0.getValueType();
3478 if (VT.isVector()) {
3479 SDValue FoldedVOp = SimplifyVBinOp(N);
3480 if (FoldedVOp.getNode()) return FoldedVOp;
3482 // fold (xor x, 0) -> x, vector edition
3483 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3485 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3489 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3490 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3491 return DAG.getConstant(0, VT);
3492 // fold (xor x, undef) -> undef
3493 if (N0.getOpcode() == ISD::UNDEF)
3495 if (N1.getOpcode() == ISD::UNDEF)
3497 // fold (xor c1, c2) -> c1^c2
3499 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3500 // canonicalize constant to RHS
3502 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
3503 // fold (xor x, 0) -> x
3504 if (N1C && N1C->isNullValue())
3507 SDValue RXOR = ReassociateOps(ISD::XOR, SDLoc(N), N0, N1);
3508 if (RXOR.getNode() != 0)
3511 // fold !(x cc y) -> (x !cc y)
3512 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3513 bool isInt = LHS.getValueType().isInteger();
3514 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3517 if (!LegalOperations ||
3518 TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) {
3519 switch (N0.getOpcode()) {
3521 llvm_unreachable("Unhandled SetCC Equivalent!");
3523 return DAG.getSetCC(SDLoc(N), VT, LHS, RHS, NotCC);
3524 case ISD::SELECT_CC:
3525 return DAG.getSelectCC(SDLoc(N), LHS, RHS, N0.getOperand(2),
3526 N0.getOperand(3), NotCC);
3531 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
3532 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3533 N0.getNode()->hasOneUse() &&
3534 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3535 SDValue V = N0.getOperand(0);
3536 V = DAG.getNode(ISD::XOR, SDLoc(N0), V.getValueType(), V,
3537 DAG.getConstant(1, V.getValueType()));
3538 AddToWorkList(V.getNode());
3539 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, V);
3542 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
3543 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
3544 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3545 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3546 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
3547 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3548 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
3549 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
3550 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3551 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
3554 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
3555 if (N1C && N1C->isAllOnesValue() &&
3556 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3557 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3558 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
3559 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3560 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
3561 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
3562 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3563 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
3566 // fold (xor (and x, y), y) -> (and (not x), y)
3567 if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3568 N0->getOperand(1) == N1) {
3569 SDValue X = N0->getOperand(0);
3570 SDValue NotX = DAG.getNOT(SDLoc(X), X, VT);
3571 AddToWorkList(NotX.getNode());
3572 return DAG.getNode(ISD::AND, SDLoc(N), VT, NotX, N1);
3574 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
3575 if (N1C && N0.getOpcode() == ISD::XOR) {
3576 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3577 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3579 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N0.getOperand(1),
3580 DAG.getConstant(N1C->getAPIntValue() ^
3581 N00C->getAPIntValue(), VT));
3583 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N0.getOperand(0),
3584 DAG.getConstant(N1C->getAPIntValue() ^
3585 N01C->getAPIntValue(), VT));
3587 // fold (xor x, x) -> 0
3589 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations, LegalTypes);
3591 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
3592 if (N0.getOpcode() == N1.getOpcode()) {
3593 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3594 if (Tmp.getNode()) return Tmp;
3597 // Simplify the expression using non-local knowledge.
3598 if (!VT.isVector() &&
3599 SimplifyDemandedBits(SDValue(N, 0)))
3600 return SDValue(N, 0);
3605 /// visitShiftByConstant - Handle transforms common to the three shifts, when
3606 /// the shift amount is a constant.
3607 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
3608 SDNode *LHS = N->getOperand(0).getNode();
3609 if (!LHS->hasOneUse()) return SDValue();
3611 // We want to pull some binops through shifts, so that we have (and (shift))
3612 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
3613 // thing happens with address calculations, so it's important to canonicalize
3615 bool HighBitSet = false; // Can we transform this if the high bit is set?
3617 switch (LHS->getOpcode()) {
3618 default: return SDValue();
3621 HighBitSet = false; // We can only transform sra if the high bit is clear.
3624 HighBitSet = true; // We can only transform sra if the high bit is set.
3627 if (N->getOpcode() != ISD::SHL)
3628 return SDValue(); // only shl(add) not sr[al](add).
3629 HighBitSet = false; // We can only transform sra if the high bit is clear.
3633 // We require the RHS of the binop to be a constant as well.
3634 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
3635 if (!BinOpCst) return SDValue();
3637 // FIXME: disable this unless the input to the binop is a shift by a constant.
3638 // If it is not a shift, it pessimizes some common cases like:
3640 // void foo(int *X, int i) { X[i & 1235] = 1; }
3641 // int bar(int *X, int i) { return X[i & 255]; }
3642 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
3643 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
3644 BinOpLHSVal->getOpcode() != ISD::SRA &&
3645 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3646 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
3649 EVT VT = N->getValueType(0);
3651 // If this is a signed shift right, and the high bit is modified by the
3652 // logical operation, do not perform the transformation. The highBitSet
3653 // boolean indicates the value of the high bit of the constant which would
3654 // cause it to be modified for this operation.
3655 if (N->getOpcode() == ISD::SRA) {
3656 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
3657 if (BinOpRHSSignSet != HighBitSet)
3661 // Fold the constants, shifting the binop RHS by the shift amount.
3662 SDValue NewRHS = DAG.getNode(N->getOpcode(), SDLoc(LHS->getOperand(1)),
3664 LHS->getOperand(1), N->getOperand(1));
3666 // Create the new shift.
3667 SDValue NewShift = DAG.getNode(N->getOpcode(),
3668 SDLoc(LHS->getOperand(0)),
3669 VT, LHS->getOperand(0), N->getOperand(1));
3671 // Create the new binop.
3672 return DAG.getNode(LHS->getOpcode(), SDLoc(N), VT, NewShift, NewRHS);
3675 SDValue DAGCombiner::visitSHL(SDNode *N) {
3676 SDValue N0 = N->getOperand(0);
3677 SDValue N1 = N->getOperand(1);
3678 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3679 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3680 EVT VT = N0.getValueType();
3681 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3684 if (VT.isVector()) {
3685 SDValue FoldedVOp = SimplifyVBinOp(N);
3686 if (FoldedVOp.getNode()) return FoldedVOp;
3689 // fold (shl c1, c2) -> c1<<c2
3691 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
3692 // fold (shl 0, x) -> 0
3693 if (N0C && N0C->isNullValue())
3695 // fold (shl x, c >= size(x)) -> undef
3696 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3697 return DAG.getUNDEF(VT);
3698 // fold (shl x, 0) -> x
3699 if (N1C && N1C->isNullValue())
3701 // fold (shl undef, x) -> 0
3702 if (N0.getOpcode() == ISD::UNDEF)
3703 return DAG.getConstant(0, VT);
3704 // if (shl x, c) is known to be zero, return 0
3705 if (DAG.MaskedValueIsZero(SDValue(N, 0),
3706 APInt::getAllOnesValue(OpSizeInBits)))
3707 return DAG.getConstant(0, VT);
3708 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
3709 if (N1.getOpcode() == ISD::TRUNCATE &&
3710 N1.getOperand(0).getOpcode() == ISD::AND &&
3711 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3712 SDValue N101 = N1.getOperand(0).getOperand(1);
3713 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3714 EVT TruncVT = N1.getValueType();
3715 SDValue N100 = N1.getOperand(0).getOperand(0);
3716 APInt TruncC = N101C->getAPIntValue();
3717 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3718 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
3719 DAG.getNode(ISD::AND, SDLoc(N), TruncVT,
3720 DAG.getNode(ISD::TRUNCATE,
3723 DAG.getConstant(TruncC, TruncVT)));
3727 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3728 return SDValue(N, 0);
3730 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
3731 if (N1C && N0.getOpcode() == ISD::SHL &&
3732 N0.getOperand(1).getOpcode() == ISD::Constant) {
3733 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3734 uint64_t c2 = N1C->getZExtValue();
3735 if (c1 + c2 >= OpSizeInBits)
3736 return DAG.getConstant(0, VT);
3737 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0),
3738 DAG.getConstant(c1 + c2, N1.getValueType()));
3741 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
3742 // For this to be valid, the second form must not preserve any of the bits
3743 // that are shifted out by the inner shift in the first form. This means
3744 // the outer shift size must be >= the number of bits added by the ext.
3745 // As a corollary, we don't care what kind of ext it is.
3746 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
3747 N0.getOpcode() == ISD::ANY_EXTEND ||
3748 N0.getOpcode() == ISD::SIGN_EXTEND) &&
3749 N0.getOperand(0).getOpcode() == ISD::SHL &&
3750 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3752 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3753 uint64_t c2 = N1C->getZExtValue();
3754 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3755 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3756 if (c2 >= OpSizeInBits - InnerShiftSize) {
3757 if (c1 + c2 >= OpSizeInBits)
3758 return DAG.getConstant(0, VT);
3759 return DAG.getNode(ISD::SHL, SDLoc(N0), VT,
3760 DAG.getNode(N0.getOpcode(), SDLoc(N0), VT,
3761 N0.getOperand(0)->getOperand(0)),
3762 DAG.getConstant(c1 + c2, N1.getValueType()));
3766 // fold (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C))
3767 // Only fold this if the inner zext has no other uses to avoid increasing
3768 // the total number of instructions.
3769 if (N1C && N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
3770 N0.getOperand(0).getOpcode() == ISD::SRL &&
3771 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3773 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3774 if (c1 < VT.getSizeInBits()) {
3775 uint64_t c2 = N1C->getZExtValue();
3777 SDValue NewOp0 = N0.getOperand(0);
3778 EVT CountVT = NewOp0.getOperand(1).getValueType();
3779 SDValue NewSHL = DAG.getNode(ISD::SHL, SDLoc(N), NewOp0.getValueType(),
3780 NewOp0, DAG.getConstant(c2, CountVT));
3781 AddToWorkList(NewSHL.getNode());
3782 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL);
3787 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
3788 // (and (srl x, (sub c1, c2), MASK)
3789 // Only fold this if the inner shift has no other uses -- if it does, folding
3790 // this will increase the total number of instructions.
3791 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() &&
3792 N0.getOperand(1).getOpcode() == ISD::Constant) {
3793 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3794 if (c1 < VT.getSizeInBits()) {
3795 uint64_t c2 = N1C->getZExtValue();
3796 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
3797 VT.getSizeInBits() - c1);
3800 Mask = Mask.shl(c2-c1);
3801 Shift = DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0),
3802 DAG.getConstant(c2-c1, N1.getValueType()));
3804 Mask = Mask.lshr(c1-c2);
3805 Shift = DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0),
3806 DAG.getConstant(c1-c2, N1.getValueType()));
3808 return DAG.getNode(ISD::AND, SDLoc(N0), VT, Shift,
3809 DAG.getConstant(Mask, VT));
3812 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
3813 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
3814 SDValue HiBitsMask =
3815 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
3816 VT.getSizeInBits() -
3817 N1C->getZExtValue()),
3819 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0),
3824 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
3825 if (NewSHL.getNode())
3832 SDValue DAGCombiner::visitSRA(SDNode *N) {
3833 SDValue N0 = N->getOperand(0);
3834 SDValue N1 = N->getOperand(1);
3835 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3836 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3837 EVT VT = N0.getValueType();
3838 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3841 if (VT.isVector()) {
3842 SDValue FoldedVOp = SimplifyVBinOp(N);
3843 if (FoldedVOp.getNode()) return FoldedVOp;
3846 // fold (sra c1, c2) -> (sra c1, c2)
3848 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
3849 // fold (sra 0, x) -> 0
3850 if (N0C && N0C->isNullValue())
3852 // fold (sra -1, x) -> -1
3853 if (N0C && N0C->isAllOnesValue())
3855 // fold (sra x, (setge c, size(x))) -> undef
3856 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3857 return DAG.getUNDEF(VT);
3858 // fold (sra x, 0) -> x
3859 if (N1C && N1C->isNullValue())
3861 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
3863 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
3864 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
3865 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
3867 ExtVT = EVT::getVectorVT(*DAG.getContext(),
3868 ExtVT, VT.getVectorNumElements());
3869 if ((!LegalOperations ||
3870 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
3871 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
3872 N0.getOperand(0), DAG.getValueType(ExtVT));
3875 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
3876 if (N1C && N0.getOpcode() == ISD::SRA) {
3877 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3878 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
3879 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
3880 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0.getOperand(0),
3881 DAG.getConstant(Sum, N1C->getValueType(0)));
3885 // fold (sra (shl X, m), (sub result_size, n))
3886 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
3887 // result_size - n != m.
3888 // If truncate is free for the target sext(shl) is likely to result in better
3890 if (N0.getOpcode() == ISD::SHL) {
3891 // Get the two constanst of the shifts, CN0 = m, CN = n.
3892 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3894 // Determine what the truncate's result bitsize and type would be.
3896 EVT::getIntegerVT(*DAG.getContext(),
3897 OpSizeInBits - N1C->getZExtValue());
3898 // Determine the residual right-shift amount.
3899 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
3901 // If the shift is not a no-op (in which case this should be just a sign
3902 // extend already), the truncated to type is legal, sign_extend is legal
3903 // on that type, and the truncate to that type is both legal and free,
3904 // perform the transform.
3905 if ((ShiftAmt > 0) &&
3906 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
3907 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
3908 TLI.isTruncateFree(VT, TruncVT)) {
3910 SDValue Amt = DAG.getConstant(ShiftAmt,
3911 getShiftAmountTy(N0.getOperand(0).getValueType()));
3912 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0), VT,
3913 N0.getOperand(0), Amt);
3914 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), TruncVT,
3916 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N),
3917 N->getValueType(0), Trunc);
3922 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
3923 if (N1.getOpcode() == ISD::TRUNCATE &&
3924 N1.getOperand(0).getOpcode() == ISD::AND &&
3925 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3926 SDValue N101 = N1.getOperand(0).getOperand(1);
3927 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3928 EVT TruncVT = N1.getValueType();
3929 SDValue N100 = N1.getOperand(0).getOperand(0);
3930 APInt TruncC = N101C->getAPIntValue();
3931 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
3932 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0,
3933 DAG.getNode(ISD::AND, SDLoc(N),
3935 DAG.getNode(ISD::TRUNCATE,
3938 DAG.getConstant(TruncC, TruncVT)));
3942 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2))
3943 // if c1 is equal to the number of bits the trunc removes
3944 if (N0.getOpcode() == ISD::TRUNCATE &&
3945 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3946 N0.getOperand(0).getOpcode() == ISD::SRA) &&
3947 N0.getOperand(0).hasOneUse() &&
3948 N0.getOperand(0).getOperand(1).hasOneUse() &&
3949 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) {
3950 EVT LargeVT = N0.getOperand(0).getValueType();
3951 ConstantSDNode *LargeShiftAmt =
3952 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1));
3954 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits ==
3955 LargeShiftAmt->getZExtValue()) {
3957 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(),
3958 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType()));
3959 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), LargeVT,
3960 N0.getOperand(0).getOperand(0), Amt);
3961 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, SRA);
3965 // Simplify, based on bits shifted out of the LHS.
3966 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3967 return SDValue(N, 0);
3970 // If the sign bit is known to be zero, switch this to a SRL.
3971 if (DAG.SignBitIsZero(N0))
3972 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1);
3975 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
3976 if (NewSRA.getNode())
3983 SDValue DAGCombiner::visitSRL(SDNode *N) {
3984 SDValue N0 = N->getOperand(0);
3985 SDValue N1 = N->getOperand(1);
3986 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3987 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3988 EVT VT = N0.getValueType();
3989 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3992 if (VT.isVector()) {
3993 SDValue FoldedVOp = SimplifyVBinOp(N);
3994 if (FoldedVOp.getNode()) return FoldedVOp;
3997 // fold (srl c1, c2) -> c1 >>u c2
3999 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
4000 // fold (srl 0, x) -> 0
4001 if (N0C && N0C->isNullValue())
4003 // fold (srl x, c >= size(x)) -> undef
4004 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
4005 return DAG.getUNDEF(VT);
4006 // fold (srl x, 0) -> x
4007 if (N1C && N1C->isNullValue())
4009 // if (srl x, c) is known to be zero, return 0
4010 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
4011 APInt::getAllOnesValue(OpSizeInBits)))
4012 return DAG.getConstant(0, VT);
4014 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
4015 if (N1C && N0.getOpcode() == ISD::SRL &&
4016 N0.getOperand(1).getOpcode() == ISD::Constant) {
4017 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
4018 uint64_t c2 = N1C->getZExtValue();
4019 if (c1 + c2 >= OpSizeInBits)
4020 return DAG.getConstant(0, VT);
4021 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0),
4022 DAG.getConstant(c1 + c2, N1.getValueType()));
4025 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
4026 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
4027 N0.getOperand(0).getOpcode() == ISD::SRL &&
4028 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
4030 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
4031 uint64_t c2 = N1C->getZExtValue();
4032 EVT InnerShiftVT = N0.getOperand(0).getValueType();
4033 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
4034 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
4035 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
4036 if (c1 + OpSizeInBits == InnerShiftSize) {
4037 if (c1 + c2 >= InnerShiftSize)
4038 return DAG.getConstant(0, VT);
4039 return DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT,
4040 DAG.getNode(ISD::SRL, SDLoc(N0), InnerShiftVT,
4041 N0.getOperand(0)->getOperand(0),
4042 DAG.getConstant(c1 + c2, ShiftCountVT)));
4046 // fold (srl (shl x, c), c) -> (and x, cst2)
4047 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
4048 N0.getValueSizeInBits() <= 64) {
4049 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
4050 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0),
4051 DAG.getConstant(~0ULL >> ShAmt, VT));
4054 // fold (srl (anyextend x), c) -> (and (anyextend (srl x, c)), mask)
4055 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
4056 // Shifting in all undef bits?
4057 EVT SmallVT = N0.getOperand(0).getValueType();
4058 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
4059 return DAG.getUNDEF(VT);
4061 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
4062 uint64_t ShiftAmt = N1C->getZExtValue();
4063 SDValue SmallShift = DAG.getNode(ISD::SRL, SDLoc(N0), SmallVT,
4065 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));
4066 AddToWorkList(SmallShift.getNode());
4067 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()).lshr(ShiftAmt);
4068 return DAG.getNode(ISD::AND, SDLoc(N), VT,
4069 DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, SmallShift),
4070 DAG.getConstant(Mask, VT));
4074 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
4075 // bit, which is unmodified by sra.
4076 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
4077 if (N0.getOpcode() == ISD::SRA)
4078 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1);
4081 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
4082 if (N1C && N0.getOpcode() == ISD::CTLZ &&
4083 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
4084 APInt KnownZero, KnownOne;
4085 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne);
4087 // If any of the input bits are KnownOne, then the input couldn't be all
4088 // zeros, thus the result of the srl will always be zero.
4089 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
4091 // If all of the bits input the to ctlz node are known to be zero, then
4092 // the result of the ctlz is "32" and the result of the shift is one.
4093 APInt UnknownBits = ~KnownZero;
4094 if (UnknownBits == 0) return DAG.getConstant(1, VT);
4096 // Otherwise, check to see if there is exactly one bit input to the ctlz.
4097 if ((UnknownBits & (UnknownBits - 1)) == 0) {
4098 // Okay, we know that only that the single bit specified by UnknownBits
4099 // could be set on input to the CTLZ node. If this bit is set, the SRL
4100 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
4101 // to an SRL/XOR pair, which is likely to simplify more.
4102 unsigned ShAmt = UnknownBits.countTrailingZeros();
4103 SDValue Op = N0.getOperand(0);
4106 Op = DAG.getNode(ISD::SRL, SDLoc(N0), VT, Op,
4107 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType())));
4108 AddToWorkList(Op.getNode());
4111 return DAG.getNode(ISD::XOR, SDLoc(N), VT,
4112 Op, DAG.getConstant(1, VT));
4116 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
4117 if (N1.getOpcode() == ISD::TRUNCATE &&
4118 N1.getOperand(0).getOpcode() == ISD::AND &&
4119 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
4120 SDValue N101 = N1.getOperand(0).getOperand(1);
4121 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
4122 EVT TruncVT = N1.getValueType();
4123 SDValue N100 = N1.getOperand(0).getOperand(0);
4124 APInt TruncC = N101C->getAPIntValue();
4125 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
4126 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0,
4127 DAG.getNode(ISD::AND, SDLoc(N),
4129 DAG.getNode(ISD::TRUNCATE,
4132 DAG.getConstant(TruncC, TruncVT)));
4136 // fold operands of srl based on knowledge that the low bits are not
4138 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4139 return SDValue(N, 0);
4142 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
4143 if (NewSRL.getNode())
4147 // Attempt to convert a srl of a load into a narrower zero-extending load.
4148 SDValue NarrowLoad = ReduceLoadWidth(N);
4149 if (NarrowLoad.getNode())
4152 // Here is a common situation. We want to optimize:
4155 // %b = and i32 %a, 2
4156 // %c = srl i32 %b, 1
4157 // brcond i32 %c ...
4163 // %c = setcc eq %b, 0
4166 // However when after the source operand of SRL is optimized into AND, the SRL
4167 // itself may not be optimized further. Look for it and add the BRCOND into
4169 if (N->hasOneUse()) {
4170 SDNode *Use = *N->use_begin();
4171 if (Use->getOpcode() == ISD::BRCOND)
4173 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
4174 // Also look pass the truncate.
4175 Use = *Use->use_begin();
4176 if (Use->getOpcode() == ISD::BRCOND)
4184 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
4185 SDValue N0 = N->getOperand(0);
4186 EVT VT = N->getValueType(0);
4188 // fold (ctlz c1) -> c2
4189 if (isa<ConstantSDNode>(N0))
4190 return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0);
4194 SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) {
4195 SDValue N0 = N->getOperand(0);
4196 EVT VT = N->getValueType(0);
4198 // fold (ctlz_zero_undef c1) -> c2
4199 if (isa<ConstantSDNode>(N0))
4200 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4204 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
4205 SDValue N0 = N->getOperand(0);
4206 EVT VT = N->getValueType(0);
4208 // fold (cttz c1) -> c2
4209 if (isa<ConstantSDNode>(N0))
4210 return DAG.getNode(ISD::CTTZ, SDLoc(N), VT, N0);
4214 SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) {
4215 SDValue N0 = N->getOperand(0);
4216 EVT VT = N->getValueType(0);
4218 // fold (cttz_zero_undef c1) -> c2
4219 if (isa<ConstantSDNode>(N0))
4220 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4224 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
4225 SDValue N0 = N->getOperand(0);
4226 EVT VT = N->getValueType(0);
4228 // fold (ctpop c1) -> c2
4229 if (isa<ConstantSDNode>(N0))
4230 return DAG.getNode(ISD::CTPOP, SDLoc(N), VT, N0);
4234 SDValue DAGCombiner::visitSELECT(SDNode *N) {
4235 SDValue N0 = N->getOperand(0);
4236 SDValue N1 = N->getOperand(1);
4237 SDValue N2 = N->getOperand(2);
4238 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4239 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4240 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
4241 EVT VT = N->getValueType(0);
4242 EVT VT0 = N0.getValueType();
4244 // fold (select C, X, X) -> X
4247 // fold (select true, X, Y) -> X
4248 if (N0C && !N0C->isNullValue())
4250 // fold (select false, X, Y) -> Y
4251 if (N0C && N0C->isNullValue())
4253 // fold (select C, 1, X) -> (or C, X)
4254 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
4255 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
4256 // fold (select C, 0, 1) -> (xor C, 1)
4257 if (VT.isInteger() &&
4260 TLI.getBooleanContents(false) ==
4261 TargetLowering::ZeroOrOneBooleanContent)) &&
4262 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
4265 return DAG.getNode(ISD::XOR, SDLoc(N), VT0,
4266 N0, DAG.getConstant(1, VT0));
4267 XORNode = DAG.getNode(ISD::XOR, SDLoc(N0), VT0,
4268 N0, DAG.getConstant(1, VT0));
4269 AddToWorkList(XORNode.getNode());
4271 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, XORNode);
4272 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, XORNode);
4274 // fold (select C, 0, X) -> (and (not C), X)
4275 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
4276 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
4277 AddToWorkList(NOTNode.getNode());
4278 return DAG.getNode(ISD::AND, SDLoc(N), VT, NOTNode, N2);
4280 // fold (select C, X, 1) -> (or (not C), X)
4281 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
4282 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
4283 AddToWorkList(NOTNode.getNode());
4284 return DAG.getNode(ISD::OR, SDLoc(N), VT, NOTNode, N1);
4286 // fold (select C, X, 0) -> (and C, X)
4287 if (VT == MVT::i1 && N2C && N2C->isNullValue())
4288 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
4289 // fold (select X, X, Y) -> (or X, Y)
4290 // fold (select X, 1, Y) -> (or X, Y)
4291 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
4292 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
4293 // fold (select X, Y, X) -> (and X, Y)
4294 // fold (select X, Y, 0) -> (and X, Y)
4295 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
4296 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
4298 // If we can fold this based on the true/false value, do so.
4299 if (SimplifySelectOps(N, N1, N2))
4300 return SDValue(N, 0); // Don't revisit N.
4302 // fold selects based on a setcc into other things, such as min/max/abs
4303 if (N0.getOpcode() == ISD::SETCC) {
4305 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
4306 // having to say they don't support SELECT_CC on every type the DAG knows
4307 // about, since there is no way to mark an opcode illegal at all value types
4308 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
4309 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
4310 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT,
4311 N0.getOperand(0), N0.getOperand(1),
4312 N1, N2, N0.getOperand(2));
4313 return SimplifySelect(SDLoc(N), N0, N1, N2);
4320 std::pair<SDValue, SDValue> SplitVSETCC(const SDNode *N, SelectionDAG &DAG) {
4323 llvm::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
4325 // Split the inputs.
4326 SDValue Lo, Hi, LL, LH, RL, RH;
4327 llvm::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
4328 llvm::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
4330 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
4331 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
4333 return std::make_pair(Lo, Hi);
4336 SDValue DAGCombiner::visitVSELECT(SDNode *N) {
4337 SDValue N0 = N->getOperand(0);
4338 SDValue N1 = N->getOperand(1);
4339 SDValue N2 = N->getOperand(2);
4342 // Canonicalize integer abs.
4343 // vselect (setg[te] X, 0), X, -X ->
4344 // vselect (setgt X, -1), X, -X ->
4345 // vselect (setl[te] X, 0), -X, X ->
4346 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4347 if (N0.getOpcode() == ISD::SETCC) {
4348 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
4349 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
4351 bool RHSIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
4353 if (((RHSIsAllZeros && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
4354 (ISD::isBuildVectorAllOnes(RHS.getNode()) && CC == ISD::SETGT)) &&
4355 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1))
4356 isAbs = ISD::isBuildVectorAllZeros(N2.getOperand(0).getNode());
4357 else if ((RHSIsAllZeros && (CC == ISD::SETLT || CC == ISD::SETLE)) &&
4358 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1))
4359 isAbs = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode());
4362 EVT VT = LHS.getValueType();
4363 SDValue Shift = DAG.getNode(
4364 ISD::SRA, DL, VT, LHS,
4365 DAG.getConstant(VT.getScalarType().getSizeInBits() - 1, VT));
4366 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, LHS, Shift);
4367 AddToWorkList(Shift.getNode());
4368 AddToWorkList(Add.getNode());
4369 return DAG.getNode(ISD::XOR, DL, VT, Add, Shift);
4373 // If the VSELECT result requires splitting and the mask is provided by a
4374 // SETCC, then split both nodes and its operands before legalization. This
4375 // prevents the type legalizer from unrolling SETCC into scalar comparisons
4376 // and enables future optimizations (e.g. min/max pattern matching on X86).
4377 if (N0.getOpcode() == ISD::SETCC) {
4378 EVT VT = N->getValueType(0);
4380 // Check if any splitting is required.
4381 if (TLI.getTypeAction(*DAG.getContext(), VT) !=
4382 TargetLowering::TypeSplitVector)
4385 SDValue Lo, Hi, CCLo, CCHi, LL, LH, RL, RH;
4386 llvm::tie(CCLo, CCHi) = SplitVSETCC(N0.getNode(), DAG);
4387 llvm::tie(LL, LH) = DAG.SplitVectorOperand(N, 1);
4388 llvm::tie(RL, RH) = DAG.SplitVectorOperand(N, 2);
4390 Lo = DAG.getNode(N->getOpcode(), DL, LL.getValueType(), CCLo, LL, RL);
4391 Hi = DAG.getNode(N->getOpcode(), DL, LH.getValueType(), CCHi, LH, RH);
4393 // Add the new VSELECT nodes to the work list in case they need to be split
4395 AddToWorkList(Lo.getNode());
4396 AddToWorkList(Hi.getNode());
4398 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
4404 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
4405 SDValue N0 = N->getOperand(0);
4406 SDValue N1 = N->getOperand(1);
4407 SDValue N2 = N->getOperand(2);
4408 SDValue N3 = N->getOperand(3);
4409 SDValue N4 = N->getOperand(4);
4410 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
4412 // fold select_cc lhs, rhs, x, x, cc -> x
4416 // Determine if the condition we're dealing with is constant
4417 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
4418 N0, N1, CC, SDLoc(N), false);
4419 if (SCC.getNode()) {
4420 AddToWorkList(SCC.getNode());
4422 if (ConstantSDNode *SCCC = dyn_cast<ConstantSDNode>(SCC.getNode())) {
4423 if (!SCCC->isNullValue())
4424 return N2; // cond always true -> true val
4426 return N3; // cond always false -> false val
4429 // Fold to a simpler select_cc
4430 if (SCC.getOpcode() == ISD::SETCC)
4431 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N2.getValueType(),
4432 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
4436 // If we can fold this based on the true/false value, do so.
4437 if (SimplifySelectOps(N, N2, N3))
4438 return SDValue(N, 0); // Don't revisit N.
4440 // fold select_cc into other things, such as min/max/abs
4441 return SimplifySelectCC(SDLoc(N), N0, N1, N2, N3, CC);
4444 SDValue DAGCombiner::visitSETCC(SDNode *N) {
4445 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
4446 cast<CondCodeSDNode>(N->getOperand(2))->get(),
4450 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
4451 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
4452 // transformation. Returns true if extension are possible and the above
4453 // mentioned transformation is profitable.
4454 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
4456 SmallVectorImpl<SDNode *> &ExtendNodes,
4457 const TargetLowering &TLI) {
4458 bool HasCopyToRegUses = false;
4459 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
4460 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
4461 UE = N0.getNode()->use_end();
4466 if (UI.getUse().getResNo() != N0.getResNo())
4468 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
4469 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
4470 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
4471 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
4472 // Sign bits will be lost after a zext.
4475 for (unsigned i = 0; i != 2; ++i) {
4476 SDValue UseOp = User->getOperand(i);
4479 if (!isa<ConstantSDNode>(UseOp))
4484 ExtendNodes.push_back(User);
4487 // If truncates aren't free and there are users we can't
4488 // extend, it isn't worthwhile.
4491 // Remember if this value is live-out.
4492 if (User->getOpcode() == ISD::CopyToReg)
4493 HasCopyToRegUses = true;
4496 if (HasCopyToRegUses) {
4497 bool BothLiveOut = false;
4498 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
4500 SDUse &Use = UI.getUse();
4501 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
4507 // Both unextended and extended values are live out. There had better be
4508 // a good reason for the transformation.
4509 return ExtendNodes.size();
4514 void DAGCombiner::ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
4515 SDValue Trunc, SDValue ExtLoad, SDLoc DL,
4516 ISD::NodeType ExtType) {
4517 // Extend SetCC uses if necessary.
4518 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
4519 SDNode *SetCC = SetCCs[i];
4520 SmallVector<SDValue, 4> Ops;
4522 for (unsigned j = 0; j != 2; ++j) {
4523 SDValue SOp = SetCC->getOperand(j);
4525 Ops.push_back(ExtLoad);
4527 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
4530 Ops.push_back(SetCC->getOperand(2));
4531 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0),
4532 &Ops[0], Ops.size()));
4536 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
4537 SDValue N0 = N->getOperand(0);
4538 EVT VT = N->getValueType(0);
4540 // fold (sext c1) -> c1
4541 if (isa<ConstantSDNode>(N0))
4542 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N0);
4544 // fold (sext (sext x)) -> (sext x)
4545 // fold (sext (aext x)) -> (sext x)
4546 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4547 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT,
4550 if (N0.getOpcode() == ISD::TRUNCATE) {
4551 // fold (sext (truncate (load x))) -> (sext (smaller load x))
4552 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
4553 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4554 if (NarrowLoad.getNode()) {
4555 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4556 if (NarrowLoad.getNode() != N0.getNode()) {
4557 CombineTo(N0.getNode(), NarrowLoad);
4558 // CombineTo deleted the truncate, if needed, but not what's under it.
4561 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4564 // See if the value being truncated is already sign extended. If so, just
4565 // eliminate the trunc/sext pair.
4566 SDValue Op = N0.getOperand(0);
4567 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
4568 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
4569 unsigned DestBits = VT.getScalarType().getSizeInBits();
4570 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
4572 if (OpBits == DestBits) {
4573 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
4574 // bits, it is already ready.
4575 if (NumSignBits > DestBits-MidBits)
4577 } else if (OpBits < DestBits) {
4578 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
4579 // bits, just sext from i32.
4580 if (NumSignBits > OpBits-MidBits)
4581 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, Op);
4583 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
4584 // bits, just truncate to i32.
4585 if (NumSignBits > OpBits-MidBits)
4586 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
4589 // fold (sext (truncate x)) -> (sextinreg x).
4590 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
4591 N0.getValueType())) {
4592 if (OpBits < DestBits)
4593 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N0), VT, Op);
4594 else if (OpBits > DestBits)
4595 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT, Op);
4596 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, Op,
4597 DAG.getValueType(N0.getValueType()));
4601 // fold (sext (load x)) -> (sext (truncate (sextload x)))
4602 // None of the supported targets knows how to perform load and sign extend
4603 // on vectors in one instruction. We only perform this transformation on
4605 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4606 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4607 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
4608 bool DoXform = true;
4609 SmallVector<SDNode*, 4> SetCCs;
4610 if (!N0.hasOneUse())
4611 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
4613 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4614 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
4616 LN0->getBasePtr(), N0.getValueType(),
4617 LN0->getMemOperand());
4618 CombineTo(N, ExtLoad);
4619 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
4620 N0.getValueType(), ExtLoad);
4621 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4622 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
4624 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4628 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
4629 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
4630 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4631 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4632 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4633 EVT MemVT = LN0->getMemoryVT();
4634 if ((!LegalOperations && !LN0->isVolatile()) ||
4635 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
4636 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
4638 LN0->getBasePtr(), MemVT,
4639 LN0->getMemOperand());
4640 CombineTo(N, ExtLoad);
4641 CombineTo(N0.getNode(),
4642 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
4643 N0.getValueType(), ExtLoad),
4644 ExtLoad.getValue(1));
4645 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4649 // fold (sext (and/or/xor (load x), cst)) ->
4650 // (and/or/xor (sextload x), (sext cst))
4651 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4652 N0.getOpcode() == ISD::XOR) &&
4653 isa<LoadSDNode>(N0.getOperand(0)) &&
4654 N0.getOperand(1).getOpcode() == ISD::Constant &&
4655 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
4656 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4657 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4658 if (LN0->getExtensionType() != ISD::ZEXTLOAD) {
4659 bool DoXform = true;
4660 SmallVector<SDNode*, 4> SetCCs;
4661 if (!N0.hasOneUse())
4662 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
4665 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(LN0), VT,
4666 LN0->getChain(), LN0->getBasePtr(),
4668 LN0->getMemOperand());
4669 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4670 Mask = Mask.sext(VT.getSizeInBits());
4671 SDValue And = DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
4672 ExtLoad, DAG.getConstant(Mask, VT));
4673 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4674 SDLoc(N0.getOperand(0)),
4675 N0.getOperand(0).getValueType(), ExtLoad);
4677 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4678 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
4680 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4685 if (N0.getOpcode() == ISD::SETCC) {
4686 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
4687 // Only do this before legalize for now.
4688 if (VT.isVector() && !LegalOperations &&
4689 TLI.getBooleanContents(true) ==
4690 TargetLowering::ZeroOrNegativeOneBooleanContent) {
4691 EVT N0VT = N0.getOperand(0).getValueType();
4692 // On some architectures (such as SSE/NEON/etc) the SETCC result type is
4693 // of the same size as the compared operands. Only optimize sext(setcc())
4694 // if this is the case.
4695 EVT SVT = getSetCCResultType(N0VT);
4697 // We know that the # elements of the results is the same as the
4698 // # elements of the compare (and the # elements of the compare result
4699 // for that matter). Check to see that they are the same size. If so,
4700 // we know that the element size of the sext'd result matches the
4701 // element size of the compare operands.
4702 if (VT.getSizeInBits() == SVT.getSizeInBits())
4703 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
4705 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4707 // If the desired elements are smaller or larger than the source
4708 // elements we can use a matching integer vector type and then
4709 // truncate/sign extend
4710 EVT MatchingVectorType = N0VT.changeVectorElementTypeToInteger();
4711 if (SVT == MatchingVectorType) {
4712 SDValue VsetCC = DAG.getSetCC(SDLoc(N), MatchingVectorType,
4713 N0.getOperand(0), N0.getOperand(1),
4714 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4715 return DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT);
4719 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
4720 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
4722 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
4724 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
4725 NegOne, DAG.getConstant(0, VT),
4726 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4727 if (SCC.getNode()) return SCC;
4728 if (!VT.isVector() &&
4729 (!LegalOperations ||
4730 TLI.isOperationLegal(ISD::SETCC, getSetCCResultType(VT)))) {
4731 return DAG.getSelect(SDLoc(N), VT,
4732 DAG.getSetCC(SDLoc(N),
4733 getSetCCResultType(VT),
4734 N0.getOperand(0), N0.getOperand(1),
4735 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4736 NegOne, DAG.getConstant(0, VT));
4740 // fold (sext x) -> (zext x) if the sign bit is known zero.
4741 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
4742 DAG.SignBitIsZero(N0))
4743 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0);
4748 // isTruncateOf - If N is a truncate of some other value, return true, record
4749 // the value being truncated in Op and which of Op's bits are zero in KnownZero.
4750 // This function computes KnownZero to avoid a duplicated call to
4751 // ComputeMaskedBits in the caller.
4752 static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
4755 if (N->getOpcode() == ISD::TRUNCATE) {
4756 Op = N->getOperand(0);
4757 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne);
4761 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 ||
4762 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE)
4765 SDValue Op0 = N->getOperand(0);
4766 SDValue Op1 = N->getOperand(1);
4767 assert(Op0.getValueType() == Op1.getValueType());
4769 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0);
4770 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1);
4771 if (COp0 && COp0->isNullValue())
4773 else if (COp1 && COp1->isNullValue())
4778 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne);
4780 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue())
4786 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
4787 SDValue N0 = N->getOperand(0);
4788 EVT VT = N->getValueType(0);
4790 // fold (zext c1) -> c1
4791 if (isa<ConstantSDNode>(N0))
4792 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0);
4793 // fold (zext (zext x)) -> (zext x)
4794 // fold (zext (aext x)) -> (zext x)
4795 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4796 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT,
4799 // fold (zext (truncate x)) -> (zext x) or
4800 // (zext (truncate x)) -> (truncate x)
4801 // This is valid when the truncated bits of x are already zero.
4802 // FIXME: We should extend this to work for vectors too.
4805 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) {
4806 APInt TruncatedBits =
4807 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ?
4808 APInt(Op.getValueSizeInBits(), 0) :
4809 APInt::getBitsSet(Op.getValueSizeInBits(),
4810 N0.getValueSizeInBits(),
4811 std::min(Op.getValueSizeInBits(),
4812 VT.getSizeInBits()));
4813 if (TruncatedBits == (KnownZero & TruncatedBits)) {
4814 if (VT.bitsGT(Op.getValueType()))
4815 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, Op);
4816 if (VT.bitsLT(Op.getValueType()))
4817 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
4823 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4824 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
4825 if (N0.getOpcode() == ISD::TRUNCATE) {
4826 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4827 if (NarrowLoad.getNode()) {
4828 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4829 if (NarrowLoad.getNode() != N0.getNode()) {
4830 CombineTo(N0.getNode(), NarrowLoad);
4831 // CombineTo deleted the truncate, if needed, but not what's under it.
4834 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4838 // fold (zext (truncate x)) -> (and x, mask)
4839 if (N0.getOpcode() == ISD::TRUNCATE &&
4840 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
4842 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4843 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
4844 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4845 if (NarrowLoad.getNode()) {
4846 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4847 if (NarrowLoad.getNode() != N0.getNode()) {
4848 CombineTo(N0.getNode(), NarrowLoad);
4849 // CombineTo deleted the truncate, if needed, but not what's under it.
4852 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4855 SDValue Op = N0.getOperand(0);
4856 if (Op.getValueType().bitsLT(VT)) {
4857 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, Op);
4858 AddToWorkList(Op.getNode());
4859 } else if (Op.getValueType().bitsGT(VT)) {
4860 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
4861 AddToWorkList(Op.getNode());
4863 return DAG.getZeroExtendInReg(Op, SDLoc(N),
4864 N0.getValueType().getScalarType());
4867 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
4868 // if either of the casts is not free.
4869 if (N0.getOpcode() == ISD::AND &&
4870 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4871 N0.getOperand(1).getOpcode() == ISD::Constant &&
4872 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4873 N0.getValueType()) ||
4874 !TLI.isZExtFree(N0.getValueType(), VT))) {
4875 SDValue X = N0.getOperand(0).getOperand(0);
4876 if (X.getValueType().bitsLT(VT)) {
4877 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(X), VT, X);
4878 } else if (X.getValueType().bitsGT(VT)) {
4879 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);
4881 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4882 Mask = Mask.zext(VT.getSizeInBits());
4883 return DAG.getNode(ISD::AND, SDLoc(N), VT,
4884 X, DAG.getConstant(Mask, VT));
4887 // fold (zext (load x)) -> (zext (truncate (zextload x)))
4888 // None of the supported targets knows how to perform load and vector_zext
4889 // on vectors in one instruction. We only perform this transformation on
4891 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4892 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4893 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
4894 bool DoXform = true;
4895 SmallVector<SDNode*, 4> SetCCs;
4896 if (!N0.hasOneUse())
4897 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
4899 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4900 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
4902 LN0->getBasePtr(), N0.getValueType(),
4903 LN0->getMemOperand());
4904 CombineTo(N, ExtLoad);
4905 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
4906 N0.getValueType(), ExtLoad);
4907 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4909 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
4911 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4915 // fold (zext (and/or/xor (load x), cst)) ->
4916 // (and/or/xor (zextload x), (zext cst))
4917 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4918 N0.getOpcode() == ISD::XOR) &&
4919 isa<LoadSDNode>(N0.getOperand(0)) &&
4920 N0.getOperand(1).getOpcode() == ISD::Constant &&
4921 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
4922 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4923 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4924 if (LN0->getExtensionType() != ISD::SEXTLOAD) {
4925 bool DoXform = true;
4926 SmallVector<SDNode*, 4> SetCCs;
4927 if (!N0.hasOneUse())
4928 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
4931 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), VT,
4932 LN0->getChain(), LN0->getBasePtr(),
4934 LN0->getMemOperand());
4935 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4936 Mask = Mask.zext(VT.getSizeInBits());
4937 SDValue And = DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
4938 ExtLoad, DAG.getConstant(Mask, VT));
4939 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4940 SDLoc(N0.getOperand(0)),
4941 N0.getOperand(0).getValueType(), ExtLoad);
4943 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4944 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
4946 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4951 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
4952 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
4953 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4954 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4955 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4956 EVT MemVT = LN0->getMemoryVT();
4957 if ((!LegalOperations && !LN0->isVolatile()) ||
4958 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
4959 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
4961 LN0->getBasePtr(), MemVT,
4962 LN0->getMemOperand());
4963 CombineTo(N, ExtLoad);
4964 CombineTo(N0.getNode(),
4965 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(),
4967 ExtLoad.getValue(1));
4968 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4972 if (N0.getOpcode() == ISD::SETCC) {
4973 if (!LegalOperations && VT.isVector() &&
4974 N0.getValueType().getVectorElementType() == MVT::i1) {
4975 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
4976 // Only do this before legalize for now.
4977 EVT N0VT = N0.getOperand(0).getValueType();
4978 EVT EltVT = VT.getVectorElementType();
4979 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
4980 DAG.getConstant(1, EltVT));
4981 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4982 // We know that the # elements of the results is the same as the
4983 // # elements of the compare (and the # elements of the compare result
4984 // for that matter). Check to see that they are the same size. If so,
4985 // we know that the element size of the sext'd result matches the
4986 // element size of the compare operands.
4987 return DAG.getNode(ISD::AND, SDLoc(N), VT,
4988 DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
4990 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4991 DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT,
4992 &OneOps[0], OneOps.size()));
4994 // If the desired elements are smaller or larger than the source
4995 // elements we can use a matching integer vector type and then
4996 // truncate/sign extend
4997 EVT MatchingElementType =
4998 EVT::getIntegerVT(*DAG.getContext(),
4999 N0VT.getScalarType().getSizeInBits());
5000 EVT MatchingVectorType =
5001 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
5002 N0VT.getVectorNumElements());
5004 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0),
5006 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5007 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5008 DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT),
5009 DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT,
5010 &OneOps[0], OneOps.size()));
5013 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
5015 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
5016 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
5017 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
5018 if (SCC.getNode()) return SCC;
5021 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
5022 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
5023 isa<ConstantSDNode>(N0.getOperand(1)) &&
5024 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
5026 SDValue ShAmt = N0.getOperand(1);
5027 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
5028 if (N0.getOpcode() == ISD::SHL) {
5029 SDValue InnerZExt = N0.getOperand(0);
5030 // If the original shl may be shifting out bits, do not perform this
5032 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
5033 InnerZExt.getOperand(0).getValueType().getSizeInBits();
5034 if (ShAmtVal > KnownZeroBits)
5040 // Ensure that the shift amount is wide enough for the shifted value.
5041 if (VT.getSizeInBits() >= 256)
5042 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
5044 return DAG.getNode(N0.getOpcode(), DL, VT,
5045 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
5052 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
5053 SDValue N0 = N->getOperand(0);
5054 EVT VT = N->getValueType(0);
5056 // fold (aext c1) -> c1
5057 if (isa<ConstantSDNode>(N0))
5058 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, N0);
5059 // fold (aext (aext x)) -> (aext x)
5060 // fold (aext (zext x)) -> (zext x)
5061 // fold (aext (sext x)) -> (sext x)
5062 if (N0.getOpcode() == ISD::ANY_EXTEND ||
5063 N0.getOpcode() == ISD::ZERO_EXTEND ||
5064 N0.getOpcode() == ISD::SIGN_EXTEND)
5065 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0));
5067 // fold (aext (truncate (load x))) -> (aext (smaller load x))
5068 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
5069 if (N0.getOpcode() == ISD::TRUNCATE) {
5070 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5071 if (NarrowLoad.getNode()) {
5072 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5073 if (NarrowLoad.getNode() != N0.getNode()) {
5074 CombineTo(N0.getNode(), NarrowLoad);
5075 // CombineTo deleted the truncate, if needed, but not what's under it.
5078 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5082 // fold (aext (truncate x))
5083 if (N0.getOpcode() == ISD::TRUNCATE) {
5084 SDValue TruncOp = N0.getOperand(0);
5085 if (TruncOp.getValueType() == VT)
5086 return TruncOp; // x iff x size == zext size.
5087 if (TruncOp.getValueType().bitsGT(VT))
5088 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, TruncOp);
5089 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, TruncOp);
5092 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
5093 // if the trunc is not free.
5094 if (N0.getOpcode() == ISD::AND &&
5095 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
5096 N0.getOperand(1).getOpcode() == ISD::Constant &&
5097 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
5098 N0.getValueType())) {
5099 SDValue X = N0.getOperand(0).getOperand(0);
5100 if (X.getValueType().bitsLT(VT)) {
5101 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, X);
5102 } else if (X.getValueType().bitsGT(VT)) {
5103 X = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, X);
5105 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5106 Mask = Mask.zext(VT.getSizeInBits());
5107 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5108 X, DAG.getConstant(Mask, VT));
5111 // fold (aext (load x)) -> (aext (truncate (extload x)))
5112 // None of the supported targets knows how to perform load and any_ext
5113 // on vectors in one instruction. We only perform this transformation on
5115 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
5116 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5117 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
5118 bool DoXform = true;
5119 SmallVector<SDNode*, 4> SetCCs;
5120 if (!N0.hasOneUse())
5121 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
5123 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5124 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
5126 LN0->getBasePtr(), N0.getValueType(),
5127 LN0->getMemOperand());
5128 CombineTo(N, ExtLoad);
5129 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5130 N0.getValueType(), ExtLoad);
5131 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
5132 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5134 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5138 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
5139 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
5140 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
5141 if (N0.getOpcode() == ISD::LOAD &&
5142 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5144 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5145 EVT MemVT = LN0->getMemoryVT();
5146 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), SDLoc(N),
5147 VT, LN0->getChain(), LN0->getBasePtr(),
5148 MemVT, LN0->getMemOperand());
5149 CombineTo(N, ExtLoad);
5150 CombineTo(N0.getNode(),
5151 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5152 N0.getValueType(), ExtLoad),
5153 ExtLoad.getValue(1));
5154 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5157 if (N0.getOpcode() == ISD::SETCC) {
5158 // aext(setcc) -> sext_in_reg(vsetcc) for vectors.
5159 // Only do this before legalize for now.
5160 if (VT.isVector() && !LegalOperations) {
5161 EVT N0VT = N0.getOperand(0).getValueType();
5162 // We know that the # elements of the results is the same as the
5163 // # elements of the compare (and the # elements of the compare result
5164 // for that matter). Check to see that they are the same size. If so,
5165 // we know that the element size of the sext'd result matches the
5166 // element size of the compare operands.
5167 if (VT.getSizeInBits() == N0VT.getSizeInBits())
5168 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
5170 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5171 // If the desired elements are smaller or larger than the source
5172 // elements we can use a matching integer vector type and then
5173 // truncate/sign extend
5175 EVT MatchingElementType =
5176 EVT::getIntegerVT(*DAG.getContext(),
5177 N0VT.getScalarType().getSizeInBits());
5178 EVT MatchingVectorType =
5179 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
5180 N0VT.getVectorNumElements());
5182 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0),
5184 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5185 return DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT);
5189 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
5191 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
5192 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
5193 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
5201 /// GetDemandedBits - See if the specified operand can be simplified with the
5202 /// knowledge that only the bits specified by Mask are used. If so, return the
5203 /// simpler operand, otherwise return a null SDValue.
5204 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
5205 switch (V.getOpcode()) {
5207 case ISD::Constant: {
5208 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode());
5209 assert(CV != 0 && "Const value should be ConstSDNode.");
5210 const APInt &CVal = CV->getAPIntValue();
5211 APInt NewVal = CVal & Mask;
5213 return DAG.getConstant(NewVal, V.getValueType());
5218 // If the LHS or RHS don't contribute bits to the or, drop them.
5219 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
5220 return V.getOperand(1);
5221 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
5222 return V.getOperand(0);
5225 // Only look at single-use SRLs.
5226 if (!V.getNode()->hasOneUse())
5228 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
5229 // See if we can recursively simplify the LHS.
5230 unsigned Amt = RHSC->getZExtValue();
5232 // Watch out for shift count overflow though.
5233 if (Amt >= Mask.getBitWidth()) break;
5234 APInt NewMask = Mask << Amt;
5235 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
5236 if (SimplifyLHS.getNode())
5237 return DAG.getNode(ISD::SRL, SDLoc(V), V.getValueType(),
5238 SimplifyLHS, V.getOperand(1));
5244 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
5245 /// bits and then truncated to a narrower type and where N is a multiple
5246 /// of number of bits of the narrower type, transform it to a narrower load
5247 /// from address + N / num of bits of new type. If the result is to be
5248 /// extended, also fold the extension to form a extending load.
5249 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
5250 unsigned Opc = N->getOpcode();
5252 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
5253 SDValue N0 = N->getOperand(0);
5254 EVT VT = N->getValueType(0);
5257 // This transformation isn't valid for vector loads.
5261 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
5263 if (Opc == ISD::SIGN_EXTEND_INREG) {
5264 ExtType = ISD::SEXTLOAD;
5265 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
5266 } else if (Opc == ISD::SRL) {
5267 // Another special-case: SRL is basically zero-extending a narrower value.
5268 ExtType = ISD::ZEXTLOAD;
5270 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5271 if (!N01) return SDValue();
5272 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
5273 VT.getSizeInBits() - N01->getZExtValue());
5275 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
5278 unsigned EVTBits = ExtVT.getSizeInBits();
5280 // Do not generate loads of non-round integer types since these can
5281 // be expensive (and would be wrong if the type is not byte sized).
5282 if (!ExtVT.isRound())
5286 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
5287 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5288 ShAmt = N01->getZExtValue();
5289 // Is the shift amount a multiple of size of VT?
5290 if ((ShAmt & (EVTBits-1)) == 0) {
5291 N0 = N0.getOperand(0);
5292 // Is the load width a multiple of size of VT?
5293 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
5297 // At this point, we must have a load or else we can't do the transform.
5298 if (!isa<LoadSDNode>(N0)) return SDValue();
5300 // Because a SRL must be assumed to *need* to zero-extend the high bits
5301 // (as opposed to anyext the high bits), we can't combine the zextload
5302 // lowering of SRL and an sextload.
5303 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD)
5306 // If the shift amount is larger than the input type then we're not
5307 // accessing any of the loaded bytes. If the load was a zextload/extload
5308 // then the result of the shift+trunc is zero/undef (handled elsewhere).
5309 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
5314 // If the load is shifted left (and the result isn't shifted back right),
5315 // we can fold the truncate through the shift.
5316 unsigned ShLeftAmt = 0;
5317 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
5318 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
5319 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5320 ShLeftAmt = N01->getZExtValue();
5321 N0 = N0.getOperand(0);
5325 // If we haven't found a load, we can't narrow it. Don't transform one with
5326 // multiple uses, this would require adding a new load.
5327 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse())
5330 // Don't change the width of a volatile load.
5331 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5332 if (LN0->isVolatile())
5335 // Verify that we are actually reducing a load width here.
5336 if (LN0->getMemoryVT().getSizeInBits() < EVTBits)
5339 // For the transform to be legal, the load must produce only two values
5340 // (the value loaded and the chain). Don't transform a pre-increment
5341 // load, for example, which produces an extra value. Otherwise the
5342 // transformation is not equivalent, and the downstream logic to replace
5343 // uses gets things wrong.
5344 if (LN0->getNumValues() > 2)
5347 // If the load that we're shrinking is an extload and we're not just
5348 // discarding the extension we can't simply shrink the load. Bail.
5349 // TODO: It would be possible to merge the extensions in some cases.
5350 if (LN0->getExtensionType() != ISD::NON_EXTLOAD &&
5351 LN0->getMemoryVT().getSizeInBits() < ExtVT.getSizeInBits() + ShAmt)
5354 EVT PtrType = N0.getOperand(1).getValueType();
5356 if (PtrType == MVT::Untyped || PtrType.isExtended())
5357 // It's not possible to generate a constant of extended or untyped type.
5360 // For big endian targets, we need to adjust the offset to the pointer to
5361 // load the correct bytes.
5362 if (TLI.isBigEndian()) {
5363 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
5364 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
5365 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
5368 uint64_t PtrOff = ShAmt / 8;
5369 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
5370 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LN0),
5371 PtrType, LN0->getBasePtr(),
5372 DAG.getConstant(PtrOff, PtrType));
5373 AddToWorkList(NewPtr.getNode());
5376 if (ExtType == ISD::NON_EXTLOAD)
5377 Load = DAG.getLoad(VT, SDLoc(N0), LN0->getChain(), NewPtr,
5378 LN0->getPointerInfo().getWithOffset(PtrOff),
5379 LN0->isVolatile(), LN0->isNonTemporal(),
5380 LN0->isInvariant(), NewAlign, LN0->getTBAAInfo());
5382 Load = DAG.getExtLoad(ExtType, SDLoc(N0), VT, LN0->getChain(),NewPtr,
5383 LN0->getPointerInfo().getWithOffset(PtrOff),
5384 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
5385 NewAlign, LN0->getTBAAInfo());
5387 // Replace the old load's chain with the new load's chain.
5388 WorkListRemover DeadNodes(*this);
5389 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
5391 // Shift the result left, if we've swallowed a left shift.
5392 SDValue Result = Load;
5393 if (ShLeftAmt != 0) {
5394 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
5395 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
5397 // If the shift amount is as large as the result size (but, presumably,
5398 // no larger than the source) then the useful bits of the result are
5399 // zero; we can't simply return the shortened shift, because the result
5400 // of that operation is undefined.
5401 if (ShLeftAmt >= VT.getSizeInBits())
5402 Result = DAG.getConstant(0, VT);
5404 Result = DAG.getNode(ISD::SHL, SDLoc(N0), VT,
5405 Result, DAG.getConstant(ShLeftAmt, ShImmTy));
5408 // Return the new loaded value.
5412 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
5413 SDValue N0 = N->getOperand(0);
5414 SDValue N1 = N->getOperand(1);
5415 EVT VT = N->getValueType(0);
5416 EVT EVT = cast<VTSDNode>(N1)->getVT();
5417 unsigned VTBits = VT.getScalarType().getSizeInBits();
5418 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
5420 // fold (sext_in_reg c1) -> c1
5421 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
5422 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, N0, N1);
5424 // If the input is already sign extended, just drop the extension.
5425 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
5428 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
5429 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
5430 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT()))
5431 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
5432 N0.getOperand(0), N1);
5434 // fold (sext_in_reg (sext x)) -> (sext x)
5435 // fold (sext_in_reg (aext x)) -> (sext x)
5436 // if x is small enough.
5437 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
5438 SDValue N00 = N0.getOperand(0);
5439 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
5440 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
5441 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00, N1);
5444 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
5445 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
5446 return DAG.getZeroExtendInReg(N0, SDLoc(N), EVT);
5448 // fold operands of sext_in_reg based on knowledge that the top bits are not
5450 if (SimplifyDemandedBits(SDValue(N, 0)))
5451 return SDValue(N, 0);
5453 // fold (sext_in_reg (load x)) -> (smaller sextload x)
5454 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
5455 SDValue NarrowLoad = ReduceLoadWidth(N);
5456 if (NarrowLoad.getNode())
5459 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
5460 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
5461 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
5462 if (N0.getOpcode() == ISD::SRL) {
5463 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
5464 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
5465 // We can turn this into an SRA iff the input to the SRL is already sign
5467 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
5468 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
5469 return DAG.getNode(ISD::SRA, SDLoc(N), VT,
5470 N0.getOperand(0), N0.getOperand(1));
5474 // fold (sext_inreg (extload x)) -> (sextload x)
5475 if (ISD::isEXTLoad(N0.getNode()) &&
5476 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5477 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5478 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5479 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5480 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5481 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5483 LN0->getBasePtr(), EVT,
5484 LN0->getMemOperand());
5485 CombineTo(N, ExtLoad);
5486 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5487 AddToWorkList(ExtLoad.getNode());
5488 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5490 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
5491 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5493 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5494 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5495 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5496 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5497 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5499 LN0->getBasePtr(), EVT,
5500 LN0->getMemOperand());
5501 CombineTo(N, ExtLoad);
5502 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5503 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5506 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
5507 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
5508 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
5509 N0.getOperand(1), false);
5510 if (BSwap.getNode() != 0)
5511 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
5515 // Fold a sext_inreg of a build_vector of ConstantSDNodes or undefs
5516 // into a build_vector.
5517 if (ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
5518 SmallVector<SDValue, 8> Elts;
5519 unsigned NumElts = N0->getNumOperands();
5520 unsigned ShAmt = VTBits - EVTBits;
5522 for (unsigned i = 0; i != NumElts; ++i) {
5523 SDValue Op = N0->getOperand(i);
5524 if (Op->getOpcode() == ISD::UNDEF) {
5529 ConstantSDNode *CurrentND = cast<ConstantSDNode>(Op);
5530 const APInt &C = CurrentND->getAPIntValue();
5531 Elts.push_back(DAG.getConstant(C.shl(ShAmt).ashr(ShAmt),
5532 Op.getValueType()));
5535 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, &Elts[0], NumElts);
5541 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
5542 SDValue N0 = N->getOperand(0);
5543 EVT VT = N->getValueType(0);
5544 bool isLE = TLI.isLittleEndian();
5547 if (N0.getValueType() == N->getValueType(0))
5549 // fold (truncate c1) -> c1
5550 if (isa<ConstantSDNode>(N0))
5551 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0);
5552 // fold (truncate (truncate x)) -> (truncate x)
5553 if (N0.getOpcode() == ISD::TRUNCATE)
5554 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
5555 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
5556 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
5557 N0.getOpcode() == ISD::SIGN_EXTEND ||
5558 N0.getOpcode() == ISD::ANY_EXTEND) {
5559 if (N0.getOperand(0).getValueType().bitsLT(VT))
5560 // if the source is smaller than the dest, we still need an extend
5561 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
5563 if (N0.getOperand(0).getValueType().bitsGT(VT))
5564 // if the source is larger than the dest, than we just need the truncate
5565 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
5566 // if the source and dest are the same type, we can drop both the extend
5567 // and the truncate.
5568 return N0.getOperand(0);
5571 // Fold extract-and-trunc into a narrow extract. For example:
5572 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
5573 // i32 y = TRUNCATE(i64 x)
5575 // v16i8 b = BITCAST (v2i64 val)
5576 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8)
5578 // Note: We only run this optimization after type legalization (which often
5579 // creates this pattern) and before operation legalization after which
5580 // we need to be more careful about the vector instructions that we generate.
5581 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5582 LegalTypes && !LegalOperations && N0->hasOneUse()) {
5584 EVT VecTy = N0.getOperand(0).getValueType();
5585 EVT ExTy = N0.getValueType();
5586 EVT TrTy = N->getValueType(0);
5588 unsigned NumElem = VecTy.getVectorNumElements();
5589 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits();
5591 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem);
5592 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size");
5594 SDValue EltNo = N0->getOperand(1);
5595 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
5596 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5597 EVT IndexTy = TLI.getVectorIdxTy();
5598 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
5600 SDValue V = DAG.getNode(ISD::BITCAST, SDLoc(N),
5601 NVT, N0.getOperand(0));
5603 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
5605 DAG.getConstant(Index, IndexTy));
5609 // Fold a series of buildvector, bitcast, and truncate if possible.
5611 // (2xi32 trunc (bitcast ((4xi32)buildvector x, x, y, y) 2xi64)) to
5612 // (2xi32 (buildvector x, y)).
5613 if (Level == AfterLegalizeVectorOps && VT.isVector() &&
5614 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
5615 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
5616 N0.getOperand(0).hasOneUse()) {
5618 SDValue BuildVect = N0.getOperand(0);
5619 EVT BuildVectEltTy = BuildVect.getValueType().getVectorElementType();
5620 EVT TruncVecEltTy = VT.getVectorElementType();
5622 // Check that the element types match.
5623 if (BuildVectEltTy == TruncVecEltTy) {
5624 // Now we only need to compute the offset of the truncated elements.
5625 unsigned BuildVecNumElts = BuildVect.getNumOperands();
5626 unsigned TruncVecNumElts = VT.getVectorNumElements();
5627 unsigned TruncEltOffset = BuildVecNumElts / TruncVecNumElts;
5629 assert((BuildVecNumElts % TruncVecNumElts) == 0 &&
5630 "Invalid number of elements");
5632 SmallVector<SDValue, 8> Opnds;
5633 for (unsigned i = 0, e = BuildVecNumElts; i != e; i += TruncEltOffset)
5634 Opnds.push_back(BuildVect.getOperand(i));
5636 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, &Opnds[0],
5641 // See if we can simplify the input to this truncate through knowledge that
5642 // only the low bits are being used.
5643 // For example "trunc (or (shl x, 8), y)" // -> trunc y
5644 // Currently we only perform this optimization on scalars because vectors
5645 // may have different active low bits.
5646 if (!VT.isVector()) {
5648 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
5649 VT.getSizeInBits()));
5650 if (Shorter.getNode())
5651 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Shorter);
5653 // fold (truncate (load x)) -> (smaller load x)
5654 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
5655 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
5656 SDValue Reduced = ReduceLoadWidth(N);
5657 if (Reduced.getNode())
5659 // Handle the case where the load remains an extending load even
5660 // after truncation.
5661 if (N0.hasOneUse() && ISD::isUNINDEXEDLoad(N0.getNode())) {
5662 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5663 if (!LN0->isVolatile() &&
5664 LN0->getMemoryVT().getStoreSizeInBits() < VT.getSizeInBits()) {
5665 SDValue NewLoad = DAG.getExtLoad(LN0->getExtensionType(), SDLoc(LN0),
5666 VT, LN0->getChain(), LN0->getBasePtr(),
5668 LN0->getMemOperand());
5669 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLoad.getValue(1));
5674 // fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)),
5675 // where ... are all 'undef'.
5676 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) {
5677 SmallVector<EVT, 8> VTs;
5680 unsigned NumDefs = 0;
5682 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
5683 SDValue X = N0.getOperand(i);
5684 if (X.getOpcode() != ISD::UNDEF) {
5689 // Stop if more than one members are non-undef.
5692 VTs.push_back(EVT::getVectorVT(*DAG.getContext(),
5693 VT.getVectorElementType(),
5694 X.getValueType().getVectorNumElements()));
5698 return DAG.getUNDEF(VT);
5701 assert(V.getNode() && "The single defined operand is empty!");
5702 SmallVector<SDValue, 8> Opnds;
5703 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
5705 Opnds.push_back(DAG.getUNDEF(VTs[i]));
5708 SDValue NV = DAG.getNode(ISD::TRUNCATE, SDLoc(V), VTs[i], V);
5709 AddToWorkList(NV.getNode());
5710 Opnds.push_back(NV);
5712 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
5713 &Opnds[0], Opnds.size());
5717 // Simplify the operands using demanded-bits information.
5718 if (!VT.isVector() &&
5719 SimplifyDemandedBits(SDValue(N, 0)))
5720 return SDValue(N, 0);
5725 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
5726 SDValue Elt = N->getOperand(i);
5727 if (Elt.getOpcode() != ISD::MERGE_VALUES)
5728 return Elt.getNode();
5729 return Elt.getOperand(Elt.getResNo()).getNode();
5732 /// CombineConsecutiveLoads - build_pair (load, load) -> load
5733 /// if load locations are consecutive.
5734 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
5735 assert(N->getOpcode() == ISD::BUILD_PAIR);
5737 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
5738 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
5739 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
5740 LD1->getPointerInfo().getAddrSpace() !=
5741 LD2->getPointerInfo().getAddrSpace())
5743 EVT LD1VT = LD1->getValueType(0);
5745 if (ISD::isNON_EXTLoad(LD2) &&
5747 // If both are volatile this would reduce the number of volatile loads.
5748 // If one is volatile it might be ok, but play conservative and bail out.
5749 !LD1->isVolatile() &&
5750 !LD2->isVolatile() &&
5751 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
5752 unsigned Align = LD1->getAlignment();
5753 unsigned NewAlign = TLI.getDataLayout()->
5754 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5756 if (NewAlign <= Align &&
5757 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
5758 return DAG.getLoad(VT, SDLoc(N), LD1->getChain(),
5759 LD1->getBasePtr(), LD1->getPointerInfo(),
5760 false, false, false, Align);
5766 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
5767 SDValue N0 = N->getOperand(0);
5768 EVT VT = N->getValueType(0);
5770 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
5771 // Only do this before legalize, since afterward the target may be depending
5772 // on the bitconvert.
5773 // First check to see if this is all constant.
5775 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
5777 bool isSimple = true;
5778 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
5779 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
5780 N0.getOperand(i).getOpcode() != ISD::Constant &&
5781 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
5786 EVT DestEltVT = N->getValueType(0).getVectorElementType();
5787 assert(!DestEltVT.isVector() &&
5788 "Element type of vector ValueType must not be vector!");
5790 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
5793 // If the input is a constant, let getNode fold it.
5794 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
5795 SDValue Res = DAG.getNode(ISD::BITCAST, SDLoc(N), VT, N0);
5796 if (Res.getNode() != N) {
5797 if (!LegalOperations ||
5798 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
5801 // Folding it resulted in an illegal node, and it's too late to
5802 // do that. Clean up the old node and forego the transformation.
5803 // Ideally this won't happen very often, because instcombine
5804 // and the earlier dagcombine runs (where illegal nodes are
5805 // permitted) should have folded most of them already.
5806 DAG.DeleteNode(Res.getNode());
5810 // (conv (conv x, t1), t2) -> (conv x, t2)
5811 if (N0.getOpcode() == ISD::BITCAST)
5812 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT,
5815 // fold (conv (load x)) -> (load (conv*)x)
5816 // If the resultant load doesn't need a higher alignment than the original!
5817 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
5818 // Do not change the width of a volatile load.
5819 !cast<LoadSDNode>(N0)->isVolatile() &&
5820 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)) &&
5821 TLI.isLoadBitCastBeneficial(N0.getValueType(), VT)) {
5822 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5823 unsigned Align = TLI.getDataLayout()->
5824 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5825 unsigned OrigAlign = LN0->getAlignment();
5827 if (Align <= OrigAlign) {
5828 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(),
5829 LN0->getBasePtr(), LN0->getPointerInfo(),
5830 LN0->isVolatile(), LN0->isNonTemporal(),
5831 LN0->isInvariant(), OrigAlign,
5832 LN0->getTBAAInfo());
5834 CombineTo(N0.getNode(),
5835 DAG.getNode(ISD::BITCAST, SDLoc(N0),
5836 N0.getValueType(), Load),
5842 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
5843 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
5844 // This often reduces constant pool loads.
5845 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) ||
5846 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) &&
5847 N0.getNode()->hasOneUse() && VT.isInteger() &&
5848 !VT.isVector() && !N0.getValueType().isVector()) {
5849 SDValue NewConv = DAG.getNode(ISD::BITCAST, SDLoc(N0), VT,
5851 AddToWorkList(NewConv.getNode());
5853 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5854 if (N0.getOpcode() == ISD::FNEG)
5855 return DAG.getNode(ISD::XOR, SDLoc(N), VT,
5856 NewConv, DAG.getConstant(SignBit, VT));
5857 assert(N0.getOpcode() == ISD::FABS);
5858 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5859 NewConv, DAG.getConstant(~SignBit, VT));
5862 // fold (bitconvert (fcopysign cst, x)) ->
5863 // (or (and (bitconvert x), sign), (and cst, (not sign)))
5864 // Note that we don't handle (copysign x, cst) because this can always be
5865 // folded to an fneg or fabs.
5866 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
5867 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
5868 VT.isInteger() && !VT.isVector()) {
5869 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
5870 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
5871 if (isTypeLegal(IntXVT)) {
5872 SDValue X = DAG.getNode(ISD::BITCAST, SDLoc(N0),
5873 IntXVT, N0.getOperand(1));
5874 AddToWorkList(X.getNode());
5876 // If X has a different width than the result/lhs, sext it or truncate it.
5877 unsigned VTWidth = VT.getSizeInBits();
5878 if (OrigXWidth < VTWidth) {
5879 X = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, X);
5880 AddToWorkList(X.getNode());
5881 } else if (OrigXWidth > VTWidth) {
5882 // To get the sign bit in the right place, we have to shift it right
5883 // before truncating.
5884 X = DAG.getNode(ISD::SRL, SDLoc(X),
5885 X.getValueType(), X,
5886 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
5887 AddToWorkList(X.getNode());
5888 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);
5889 AddToWorkList(X.getNode());
5892 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5893 X = DAG.getNode(ISD::AND, SDLoc(X), VT,
5894 X, DAG.getConstant(SignBit, VT));
5895 AddToWorkList(X.getNode());
5897 SDValue Cst = DAG.getNode(ISD::BITCAST, SDLoc(N0),
5898 VT, N0.getOperand(0));
5899 Cst = DAG.getNode(ISD::AND, SDLoc(Cst), VT,
5900 Cst, DAG.getConstant(~SignBit, VT));
5901 AddToWorkList(Cst.getNode());
5903 return DAG.getNode(ISD::OR, SDLoc(N), VT, X, Cst);
5907 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
5908 if (N0.getOpcode() == ISD::BUILD_PAIR) {
5909 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
5910 if (CombineLD.getNode())
5917 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
5918 EVT VT = N->getValueType(0);
5919 return CombineConsecutiveLoads(N, VT);
5922 /// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector
5923 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
5924 /// destination element value type.
5925 SDValue DAGCombiner::
5926 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
5927 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
5929 // If this is already the right type, we're done.
5930 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
5932 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
5933 unsigned DstBitSize = DstEltVT.getSizeInBits();
5935 // If this is a conversion of N elements of one type to N elements of another
5936 // type, convert each element. This handles FP<->INT cases.
5937 if (SrcBitSize == DstBitSize) {
5938 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5939 BV->getValueType(0).getVectorNumElements());
5941 // Due to the FP element handling below calling this routine recursively,
5942 // we can end up with a scalar-to-vector node here.
5943 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
5944 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(BV), VT,
5945 DAG.getNode(ISD::BITCAST, SDLoc(BV),
5946 DstEltVT, BV->getOperand(0)));
5948 SmallVector<SDValue, 8> Ops;
5949 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5950 SDValue Op = BV->getOperand(i);
5951 // If the vector element type is not legal, the BUILD_VECTOR operands
5952 // are promoted and implicitly truncated. Make that explicit here.
5953 if (Op.getValueType() != SrcEltVT)
5954 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(BV), SrcEltVT, Op);
5955 Ops.push_back(DAG.getNode(ISD::BITCAST, SDLoc(BV),
5957 AddToWorkList(Ops.back().getNode());
5959 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT,
5960 &Ops[0], Ops.size());
5963 // Otherwise, we're growing or shrinking the elements. To avoid having to
5964 // handle annoying details of growing/shrinking FP values, we convert them to
5966 if (SrcEltVT.isFloatingPoint()) {
5967 // Convert the input float vector to a int vector where the elements are the
5969 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
5970 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
5971 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
5975 // Now we know the input is an integer vector. If the output is a FP type,
5976 // convert to integer first, then to FP of the right size.
5977 if (DstEltVT.isFloatingPoint()) {
5978 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
5979 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
5980 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
5982 // Next, convert to FP elements of the same size.
5983 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
5986 // Okay, we know the src/dst types are both integers of differing types.
5987 // Handling growing first.
5988 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
5989 if (SrcBitSize < DstBitSize) {
5990 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
5992 SmallVector<SDValue, 8> Ops;
5993 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
5994 i += NumInputsPerOutput) {
5995 bool isLE = TLI.isLittleEndian();
5996 APInt NewBits = APInt(DstBitSize, 0);
5997 bool EltIsUndef = true;
5998 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
5999 // Shift the previously computed bits over.
6000 NewBits <<= SrcBitSize;
6001 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
6002 if (Op.getOpcode() == ISD::UNDEF) continue;
6005 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
6006 zextOrTrunc(SrcBitSize).zext(DstBitSize);
6010 Ops.push_back(DAG.getUNDEF(DstEltVT));
6012 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
6015 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
6016 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT,
6017 &Ops[0], Ops.size());
6020 // Finally, this must be the case where we are shrinking elements: each input
6021 // turns into multiple outputs.
6022 bool isS2V = ISD::isScalarToVector(BV);
6023 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
6024 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
6025 NumOutputsPerInput*BV->getNumOperands());
6026 SmallVector<SDValue, 8> Ops;
6028 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
6029 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
6030 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
6031 Ops.push_back(DAG.getUNDEF(DstEltVT));
6035 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
6036 getAPIntValue().zextOrTrunc(SrcBitSize);
6038 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
6039 APInt ThisVal = OpVal.trunc(DstBitSize);
6040 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
6041 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
6042 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
6043 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(BV), VT,
6045 OpVal = OpVal.lshr(DstBitSize);
6048 // For big endian targets, swap the order of the pieces of each element.
6049 if (TLI.isBigEndian())
6050 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
6053 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT,
6054 &Ops[0], Ops.size());
6057 SDValue DAGCombiner::visitFADD(SDNode *N) {
6058 SDValue N0 = N->getOperand(0);
6059 SDValue N1 = N->getOperand(1);
6060 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6061 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6062 EVT VT = N->getValueType(0);
6065 if (VT.isVector()) {
6066 SDValue FoldedVOp = SimplifyVBinOp(N);
6067 if (FoldedVOp.getNode()) return FoldedVOp;
6070 // fold (fadd c1, c2) -> c1 + c2
6072 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N1);
6073 // canonicalize constant to RHS
6074 if (N0CFP && !N1CFP)
6075 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N0);
6076 // fold (fadd A, 0) -> A
6077 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
6078 N1CFP->getValueAPF().isZero())
6080 // fold (fadd A, (fneg B)) -> (fsub A, B)
6081 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
6082 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
6083 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0,
6084 GetNegatedExpression(N1, DAG, LegalOperations));
6085 // fold (fadd (fneg A), B) -> (fsub B, A)
6086 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
6087 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
6088 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N1,
6089 GetNegatedExpression(N0, DAG, LegalOperations));
6091 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
6092 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
6093 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
6094 isa<ConstantFPSDNode>(N0.getOperand(1)))
6095 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0.getOperand(0),
6096 DAG.getNode(ISD::FADD, SDLoc(N), VT,
6097 N0.getOperand(1), N1));
6099 // No FP constant should be created after legalization as Instruction
6100 // Selection pass has hard time in dealing with FP constant.
6102 // We don't need test this condition for transformation like following, as
6103 // the DAG being transformed implies it is legal to take FP constant as
6106 // (fadd (fmul c, x), x) -> (fmul c+1, x)
6108 bool AllowNewFpConst = (Level < AfterLegalizeDAG);
6110 // If allow, fold (fadd (fneg x), x) -> 0.0
6111 if (AllowNewFpConst && DAG.getTarget().Options.UnsafeFPMath &&
6112 N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1)
6113 return DAG.getConstantFP(0.0, VT);
6115 // If allow, fold (fadd x, (fneg x)) -> 0.0
6116 if (AllowNewFpConst && DAG.getTarget().Options.UnsafeFPMath &&
6117 N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0)
6118 return DAG.getConstantFP(0.0, VT);
6120 // In unsafe math mode, we can fold chains of FADD's of the same value
6121 // into multiplications. This transform is not safe in general because
6122 // we are reducing the number of rounding steps.
6123 if (DAG.getTarget().Options.UnsafeFPMath &&
6124 TLI.isOperationLegalOrCustom(ISD::FMUL, VT) &&
6126 if (N0.getOpcode() == ISD::FMUL) {
6127 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
6128 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
6130 // (fadd (fmul c, x), x) -> (fmul x, c+1)
6131 if (CFP00 && !CFP01 && N0.getOperand(1) == N1) {
6132 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6134 DAG.getConstantFP(1.0, VT));
6135 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6139 // (fadd (fmul x, c), x) -> (fmul x, c+1)
6140 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) {
6141 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6143 DAG.getConstantFP(1.0, VT));
6144 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6148 // (fadd (fmul c, x), (fadd x, x)) -> (fmul x, c+2)
6149 if (CFP00 && !CFP01 && N1.getOpcode() == ISD::FADD &&
6150 N1.getOperand(0) == N1.getOperand(1) &&
6151 N0.getOperand(1) == N1.getOperand(0)) {
6152 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6154 DAG.getConstantFP(2.0, VT));
6155 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6156 N0.getOperand(1), NewCFP);
6159 // (fadd (fmul x, c), (fadd x, x)) -> (fmul x, c+2)
6160 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD &&
6161 N1.getOperand(0) == N1.getOperand(1) &&
6162 N0.getOperand(0) == N1.getOperand(0)) {
6163 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6165 DAG.getConstantFP(2.0, VT));
6166 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6167 N0.getOperand(0), NewCFP);
6171 if (N1.getOpcode() == ISD::FMUL) {
6172 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
6173 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1));
6175 // (fadd x, (fmul c, x)) -> (fmul x, c+1)
6176 if (CFP10 && !CFP11 && N1.getOperand(1) == N0) {
6177 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6179 DAG.getConstantFP(1.0, VT));
6180 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6184 // (fadd x, (fmul x, c)) -> (fmul x, c+1)
6185 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) {
6186 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6188 DAG.getConstantFP(1.0, VT));
6189 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6194 // (fadd (fadd x, x), (fmul c, x)) -> (fmul x, c+2)
6195 if (CFP10 && !CFP11 && N0.getOpcode() == ISD::FADD &&
6196 N0.getOperand(0) == N0.getOperand(1) &&
6197 N1.getOperand(1) == N0.getOperand(0)) {
6198 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6200 DAG.getConstantFP(2.0, VT));
6201 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6202 N1.getOperand(1), NewCFP);
6205 // (fadd (fadd x, x), (fmul x, c)) -> (fmul x, c+2)
6206 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD &&
6207 N0.getOperand(0) == N0.getOperand(1) &&
6208 N1.getOperand(0) == N0.getOperand(0)) {
6209 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6211 DAG.getConstantFP(2.0, VT));
6212 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6213 N1.getOperand(0), NewCFP);
6217 if (N0.getOpcode() == ISD::FADD && AllowNewFpConst) {
6218 ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
6219 // (fadd (fadd x, x), x) -> (fmul x, 3.0)
6220 if (!CFP && N0.getOperand(0) == N0.getOperand(1) &&
6221 (N0.getOperand(0) == N1))
6222 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6223 N1, DAG.getConstantFP(3.0, VT));
6226 if (N1.getOpcode() == ISD::FADD && AllowNewFpConst) {
6227 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
6228 // (fadd x, (fadd x, x)) -> (fmul x, 3.0)
6229 if (!CFP10 && N1.getOperand(0) == N1.getOperand(1) &&
6230 N1.getOperand(0) == N0)
6231 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6232 N0, DAG.getConstantFP(3.0, VT));
6235 // (fadd (fadd x, x), (fadd x, x)) -> (fmul x, 4.0)
6236 if (AllowNewFpConst &&
6237 N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
6238 N0.getOperand(0) == N0.getOperand(1) &&
6239 N1.getOperand(0) == N1.getOperand(1) &&
6240 N0.getOperand(0) == N1.getOperand(0))
6241 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6243 DAG.getConstantFP(4.0, VT));
6246 // FADD -> FMA combines:
6247 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast ||
6248 DAG.getTarget().Options.UnsafeFPMath) &&
6249 DAG.getTarget().getTargetLowering()->isFMAFasterThanFMulAndFAdd(VT) &&
6250 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT))) {
6252 // fold (fadd (fmul x, y), z) -> (fma x, y, z)
6253 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse())
6254 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6255 N0.getOperand(0), N0.getOperand(1), N1);
6257 // fold (fadd x, (fmul y, z)) -> (fma y, z, x)
6258 // Note: Commutes FADD operands.
6259 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse())
6260 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6261 N1.getOperand(0), N1.getOperand(1), N0);
6267 SDValue DAGCombiner::visitFSUB(SDNode *N) {
6268 SDValue N0 = N->getOperand(0);
6269 SDValue N1 = N->getOperand(1);
6270 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6271 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6272 EVT VT = N->getValueType(0);
6276 if (VT.isVector()) {
6277 SDValue FoldedVOp = SimplifyVBinOp(N);
6278 if (FoldedVOp.getNode()) return FoldedVOp;
6281 // fold (fsub c1, c2) -> c1-c2
6283 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0, N1);
6284 // fold (fsub A, 0) -> A
6285 if (DAG.getTarget().Options.UnsafeFPMath &&
6286 N1CFP && N1CFP->getValueAPF().isZero())
6288 // fold (fsub 0, B) -> -B
6289 if (DAG.getTarget().Options.UnsafeFPMath &&
6290 N0CFP && N0CFP->getValueAPF().isZero()) {
6291 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options))
6292 return GetNegatedExpression(N1, DAG, LegalOperations);
6293 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6294 return DAG.getNode(ISD::FNEG, dl, VT, N1);
6296 // fold (fsub A, (fneg B)) -> (fadd A, B)
6297 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options))
6298 return DAG.getNode(ISD::FADD, dl, VT, N0,
6299 GetNegatedExpression(N1, DAG, LegalOperations));
6301 // If 'unsafe math' is enabled, fold
6302 // (fsub x, x) -> 0.0 &
6303 // (fsub x, (fadd x, y)) -> (fneg y) &
6304 // (fsub x, (fadd y, x)) -> (fneg y)
6305 if (DAG.getTarget().Options.UnsafeFPMath) {
6307 return DAG.getConstantFP(0.0f, VT);
6309 if (N1.getOpcode() == ISD::FADD) {
6310 SDValue N10 = N1->getOperand(0);
6311 SDValue N11 = N1->getOperand(1);
6313 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI,
6314 &DAG.getTarget().Options))
6315 return GetNegatedExpression(N11, DAG, LegalOperations);
6317 if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI,
6318 &DAG.getTarget().Options))
6319 return GetNegatedExpression(N10, DAG, LegalOperations);
6323 // FSUB -> FMA combines:
6324 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast ||
6325 DAG.getTarget().Options.UnsafeFPMath) &&
6326 DAG.getTarget().getTargetLowering()->isFMAFasterThanFMulAndFAdd(VT) &&
6327 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT))) {
6329 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
6330 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse())
6331 return DAG.getNode(ISD::FMA, dl, VT,
6332 N0.getOperand(0), N0.getOperand(1),
6333 DAG.getNode(ISD::FNEG, dl, VT, N1));
6335 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
6336 // Note: Commutes FSUB operands.
6337 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse())
6338 return DAG.getNode(ISD::FMA, dl, VT,
6339 DAG.getNode(ISD::FNEG, dl, VT,
6341 N1.getOperand(1), N0);
6343 // fold (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
6344 if (N0.getOpcode() == ISD::FNEG &&
6345 N0.getOperand(0).getOpcode() == ISD::FMUL &&
6346 N0->hasOneUse() && N0.getOperand(0).hasOneUse()) {
6347 SDValue N00 = N0.getOperand(0).getOperand(0);
6348 SDValue N01 = N0.getOperand(0).getOperand(1);
6349 return DAG.getNode(ISD::FMA, dl, VT,
6350 DAG.getNode(ISD::FNEG, dl, VT, N00), N01,
6351 DAG.getNode(ISD::FNEG, dl, VT, N1));
6358 SDValue DAGCombiner::visitFMUL(SDNode *N) {
6359 SDValue N0 = N->getOperand(0);
6360 SDValue N1 = N->getOperand(1);
6361 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6362 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6363 EVT VT = N->getValueType(0);
6364 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6367 if (VT.isVector()) {
6368 SDValue FoldedVOp = SimplifyVBinOp(N);
6369 if (FoldedVOp.getNode()) return FoldedVOp;
6372 // fold (fmul c1, c2) -> c1*c2
6374 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0, N1);
6375 // canonicalize constant to RHS
6376 if (N0CFP && !N1CFP)
6377 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N1, N0);
6378 // fold (fmul A, 0) -> 0
6379 if (DAG.getTarget().Options.UnsafeFPMath &&
6380 N1CFP && N1CFP->getValueAPF().isZero())
6382 // fold (fmul A, 0) -> 0, vector edition.
6383 if (DAG.getTarget().Options.UnsafeFPMath &&
6384 ISD::isBuildVectorAllZeros(N1.getNode()))
6386 // fold (fmul A, 1.0) -> A
6387 if (N1CFP && N1CFP->isExactlyValue(1.0))
6389 // fold (fmul X, 2.0) -> (fadd X, X)
6390 if (N1CFP && N1CFP->isExactlyValue(+2.0))
6391 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N0);
6392 // fold (fmul X, -1.0) -> (fneg X)
6393 if (N1CFP && N1CFP->isExactlyValue(-1.0))
6394 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6395 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0);
6397 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
6398 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
6399 &DAG.getTarget().Options)) {
6400 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI,
6401 &DAG.getTarget().Options)) {
6402 // Both can be negated for free, check to see if at least one is cheaper
6404 if (LHSNeg == 2 || RHSNeg == 2)
6405 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6406 GetNegatedExpression(N0, DAG, LegalOperations),
6407 GetNegatedExpression(N1, DAG, LegalOperations));
6411 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
6412 if (DAG.getTarget().Options.UnsafeFPMath &&
6413 N1CFP && N0.getOpcode() == ISD::FMUL &&
6414 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
6415 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0.getOperand(0),
6416 DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6417 N0.getOperand(1), N1));
6422 SDValue DAGCombiner::visitFMA(SDNode *N) {
6423 SDValue N0 = N->getOperand(0);
6424 SDValue N1 = N->getOperand(1);
6425 SDValue N2 = N->getOperand(2);
6426 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6427 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6428 EVT VT = N->getValueType(0);
6431 if (DAG.getTarget().Options.UnsafeFPMath) {
6432 if (N0CFP && N0CFP->isZero())
6434 if (N1CFP && N1CFP->isZero())
6437 if (N0CFP && N0CFP->isExactlyValue(1.0))
6438 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N2);
6439 if (N1CFP && N1CFP->isExactlyValue(1.0))
6440 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N2);
6442 // Canonicalize (fma c, x, y) -> (fma x, c, y)
6443 if (N0CFP && !N1CFP)
6444 return DAG.getNode(ISD::FMA, SDLoc(N), VT, N1, N0, N2);
6446 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2)
6447 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
6448 N2.getOpcode() == ISD::FMUL &&
6449 N0 == N2.getOperand(0) &&
6450 N2.getOperand(1).getOpcode() == ISD::ConstantFP) {
6451 return DAG.getNode(ISD::FMUL, dl, VT, N0,
6452 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1)));
6456 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y)
6457 if (DAG.getTarget().Options.UnsafeFPMath &&
6458 N0.getOpcode() == ISD::FMUL && N1CFP &&
6459 N0.getOperand(1).getOpcode() == ISD::ConstantFP) {
6460 return DAG.getNode(ISD::FMA, dl, VT,
6462 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)),
6466 // (fma x, 1, y) -> (fadd x, y)
6467 // (fma x, -1, y) -> (fadd (fneg x), y)
6469 if (N1CFP->isExactlyValue(1.0))
6470 return DAG.getNode(ISD::FADD, dl, VT, N0, N2);
6472 if (N1CFP->isExactlyValue(-1.0) &&
6473 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) {
6474 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0);
6475 AddToWorkList(RHSNeg.getNode());
6476 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg);
6480 // (fma x, c, x) -> (fmul x, (c+1))
6481 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && N0 == N2)
6482 return DAG.getNode(ISD::FMUL, dl, VT, N0,
6483 DAG.getNode(ISD::FADD, dl, VT,
6484 N1, DAG.getConstantFP(1.0, VT)));
6486 // (fma x, c, (fneg x)) -> (fmul x, (c-1))
6487 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
6488 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0)
6489 return DAG.getNode(ISD::FMUL, dl, VT, N0,
6490 DAG.getNode(ISD::FADD, dl, VT,
6491 N1, DAG.getConstantFP(-1.0, VT)));
6497 SDValue DAGCombiner::visitFDIV(SDNode *N) {
6498 SDValue N0 = N->getOperand(0);
6499 SDValue N1 = N->getOperand(1);
6500 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6501 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6502 EVT VT = N->getValueType(0);
6503 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6506 if (VT.isVector()) {
6507 SDValue FoldedVOp = SimplifyVBinOp(N);
6508 if (FoldedVOp.getNode()) return FoldedVOp;
6511 // fold (fdiv c1, c2) -> c1/c2
6513 return DAG.getNode(ISD::FDIV, SDLoc(N), VT, N0, N1);
6515 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable.
6516 if (N1CFP && DAG.getTarget().Options.UnsafeFPMath) {
6517 // Compute the reciprocal 1.0 / c2.
6518 APFloat N1APF = N1CFP->getValueAPF();
6519 APFloat Recip(N1APF.getSemantics(), 1); // 1.0
6520 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven);
6521 // Only do the transform if the reciprocal is a legal fp immediate that
6522 // isn't too nasty (eg NaN, denormal, ...).
6523 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty
6524 (!LegalOperations ||
6525 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM
6526 // backend)... we should handle this gracefully after Legalize.
6527 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) ||
6528 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) ||
6529 TLI.isFPImmLegal(Recip, VT)))
6530 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0,
6531 DAG.getConstantFP(Recip, VT));
6534 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
6535 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
6536 &DAG.getTarget().Options)) {
6537 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI,
6538 &DAG.getTarget().Options)) {
6539 // Both can be negated for free, check to see if at least one is cheaper
6541 if (LHSNeg == 2 || RHSNeg == 2)
6542 return DAG.getNode(ISD::FDIV, SDLoc(N), VT,
6543 GetNegatedExpression(N0, DAG, LegalOperations),
6544 GetNegatedExpression(N1, DAG, LegalOperations));
6551 SDValue DAGCombiner::visitFREM(SDNode *N) {
6552 SDValue N0 = N->getOperand(0);
6553 SDValue N1 = N->getOperand(1);
6554 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6555 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6556 EVT VT = N->getValueType(0);
6558 // fold (frem c1, c2) -> fmod(c1,c2)
6560 return DAG.getNode(ISD::FREM, SDLoc(N), VT, N0, N1);
6565 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
6566 SDValue N0 = N->getOperand(0);
6567 SDValue N1 = N->getOperand(1);
6568 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6569 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6570 EVT VT = N->getValueType(0);
6572 if (N0CFP && N1CFP) // Constant fold
6573 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1);
6576 const APFloat& V = N1CFP->getValueAPF();
6577 // copysign(x, c1) -> fabs(x) iff ispos(c1)
6578 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
6579 if (!V.isNegative()) {
6580 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
6581 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
6583 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6584 return DAG.getNode(ISD::FNEG, SDLoc(N), VT,
6585 DAG.getNode(ISD::FABS, SDLoc(N0), VT, N0));
6589 // copysign(fabs(x), y) -> copysign(x, y)
6590 // copysign(fneg(x), y) -> copysign(x, y)
6591 // copysign(copysign(x,z), y) -> copysign(x, y)
6592 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
6593 N0.getOpcode() == ISD::FCOPYSIGN)
6594 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
6595 N0.getOperand(0), N1);
6597 // copysign(x, abs(y)) -> abs(x)
6598 if (N1.getOpcode() == ISD::FABS)
6599 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
6601 // copysign(x, copysign(y,z)) -> copysign(x, z)
6602 if (N1.getOpcode() == ISD::FCOPYSIGN)
6603 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
6604 N0, N1.getOperand(1));
6606 // copysign(x, fp_extend(y)) -> copysign(x, y)
6607 // copysign(x, fp_round(y)) -> copysign(x, y)
6608 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
6609 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
6610 N0, N1.getOperand(0));
6615 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
6616 SDValue N0 = N->getOperand(0);
6617 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
6618 EVT VT = N->getValueType(0);
6619 EVT OpVT = N0.getValueType();
6621 // fold (sint_to_fp c1) -> c1fp
6623 // ...but only if the target supports immediate floating-point values
6624 (!LegalOperations ||
6625 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
6626 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
6628 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
6629 // but UINT_TO_FP is legal on this target, try to convert.
6630 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
6631 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
6632 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
6633 if (DAG.SignBitIsZero(N0))
6634 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
6637 // The next optimizations are desireable only if SELECT_CC can be lowered.
6638 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
6639 // having to say they don't support SELECT_CC on every type the DAG knows
6640 // about, since there is no way to mark an opcode illegal at all value types
6641 // (See also visitSELECT)
6642 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) {
6643 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
6644 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
6646 (!LegalOperations ||
6647 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6649 { N0.getOperand(0), N0.getOperand(1),
6650 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT),
6652 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops, 5);
6655 // fold (sint_to_fp (zext (setcc x, y, cc))) ->
6656 // (select_cc x, y, 1.0, 0.0,, cc)
6657 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
6658 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
6659 (!LegalOperations ||
6660 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6662 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1),
6663 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT),
6664 N0.getOperand(0).getOperand(2) };
6665 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops, 5);
6672 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
6673 SDValue N0 = N->getOperand(0);
6674 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
6675 EVT VT = N->getValueType(0);
6676 EVT OpVT = N0.getValueType();
6678 // fold (uint_to_fp c1) -> c1fp
6680 // ...but only if the target supports immediate floating-point values
6681 (!LegalOperations ||
6682 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
6683 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
6685 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
6686 // but SINT_TO_FP is legal on this target, try to convert.
6687 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
6688 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
6689 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
6690 if (DAG.SignBitIsZero(N0))
6691 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
6694 // The next optimizations are desireable only if SELECT_CC can be lowered.
6695 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
6696 // having to say they don't support SELECT_CC on every type the DAG knows
6697 // about, since there is no way to mark an opcode illegal at all value types
6698 // (See also visitSELECT)
6699 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) {
6700 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
6702 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
6703 (!LegalOperations ||
6704 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6706 { N0.getOperand(0), N0.getOperand(1),
6707 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT),
6709 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops, 5);
6716 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
6717 SDValue N0 = N->getOperand(0);
6718 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6719 EVT VT = N->getValueType(0);
6721 // fold (fp_to_sint c1fp) -> c1
6723 return DAG.getNode(ISD::FP_TO_SINT, SDLoc(N), VT, N0);
6728 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
6729 SDValue N0 = N->getOperand(0);
6730 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6731 EVT VT = N->getValueType(0);
6733 // fold (fp_to_uint c1fp) -> c1
6735 return DAG.getNode(ISD::FP_TO_UINT, SDLoc(N), VT, N0);
6740 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
6741 SDValue N0 = N->getOperand(0);
6742 SDValue N1 = N->getOperand(1);
6743 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6744 EVT VT = N->getValueType(0);
6746 // fold (fp_round c1fp) -> c1fp
6748 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0, N1);
6750 // fold (fp_round (fp_extend x)) -> x
6751 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
6752 return N0.getOperand(0);
6754 // fold (fp_round (fp_round x)) -> (fp_round x)
6755 if (N0.getOpcode() == ISD::FP_ROUND) {
6756 // This is a value preserving truncation if both round's are.
6757 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
6758 N0.getNode()->getConstantOperandVal(1) == 1;
6759 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0.getOperand(0),
6760 DAG.getIntPtrConstant(IsTrunc));
6763 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
6764 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
6765 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, SDLoc(N0), VT,
6766 N0.getOperand(0), N1);
6767 AddToWorkList(Tmp.getNode());
6768 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
6769 Tmp, N0.getOperand(1));
6775 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
6776 SDValue N0 = N->getOperand(0);
6777 EVT VT = N->getValueType(0);
6778 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
6779 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6781 // fold (fp_round_inreg c1fp) -> c1fp
6782 if (N0CFP && isTypeLegal(EVT)) {
6783 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
6784 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Round);
6790 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
6791 SDValue N0 = N->getOperand(0);
6792 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6793 EVT VT = N->getValueType(0);
6795 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
6796 if (N->hasOneUse() &&
6797 N->use_begin()->getOpcode() == ISD::FP_ROUND)
6800 // fold (fp_extend c1fp) -> c1fp
6802 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, N0);
6804 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
6806 if (N0.getOpcode() == ISD::FP_ROUND
6807 && N0.getNode()->getConstantOperandVal(1) == 1) {
6808 SDValue In = N0.getOperand(0);
6809 if (In.getValueType() == VT) return In;
6810 if (VT.bitsLT(In.getValueType()))
6811 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT,
6812 In, N0.getOperand(1));
6813 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, In);
6816 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
6817 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6818 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6819 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
6820 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6821 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
6823 LN0->getBasePtr(), N0.getValueType(),
6824 LN0->getMemOperand());
6825 CombineTo(N, ExtLoad);
6826 CombineTo(N0.getNode(),
6827 DAG.getNode(ISD::FP_ROUND, SDLoc(N0),
6828 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
6829 ExtLoad.getValue(1));
6830 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6836 SDValue DAGCombiner::visitFNEG(SDNode *N) {
6837 SDValue N0 = N->getOperand(0);
6838 EVT VT = N->getValueType(0);
6840 if (VT.isVector()) {
6841 SDValue FoldedVOp = SimplifyVUnaryOp(N);
6842 if (FoldedVOp.getNode()) return FoldedVOp;
6845 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(),
6846 &DAG.getTarget().Options))
6847 return GetNegatedExpression(N0, DAG, LegalOperations);
6849 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
6850 // constant pool values.
6851 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST &&
6853 N0.getNode()->hasOneUse() &&
6854 N0.getOperand(0).getValueType().isInteger()) {
6855 SDValue Int = N0.getOperand(0);
6856 EVT IntVT = Int.getValueType();
6857 if (IntVT.isInteger() && !IntVT.isVector()) {
6858 Int = DAG.getNode(ISD::XOR, SDLoc(N0), IntVT, Int,
6859 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
6860 AddToWorkList(Int.getNode());
6861 return DAG.getNode(ISD::BITCAST, SDLoc(N),
6866 // (fneg (fmul c, x)) -> (fmul -c, x)
6867 if (N0.getOpcode() == ISD::FMUL) {
6868 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
6870 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6872 DAG.getNode(ISD::FNEG, SDLoc(N), VT,
6879 SDValue DAGCombiner::visitFCEIL(SDNode *N) {
6880 SDValue N0 = N->getOperand(0);
6881 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6882 EVT VT = N->getValueType(0);
6884 // fold (fceil c1) -> fceil(c1)
6886 return DAG.getNode(ISD::FCEIL, SDLoc(N), VT, N0);
6891 SDValue DAGCombiner::visitFTRUNC(SDNode *N) {
6892 SDValue N0 = N->getOperand(0);
6893 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6894 EVT VT = N->getValueType(0);
6896 // fold (ftrunc c1) -> ftrunc(c1)
6898 return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0);
6903 SDValue DAGCombiner::visitFFLOOR(SDNode *N) {
6904 SDValue N0 = N->getOperand(0);
6905 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6906 EVT VT = N->getValueType(0);
6908 // fold (ffloor c1) -> ffloor(c1)
6910 return DAG.getNode(ISD::FFLOOR, SDLoc(N), VT, N0);
6915 SDValue DAGCombiner::visitFABS(SDNode *N) {
6916 SDValue N0 = N->getOperand(0);
6917 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6918 EVT VT = N->getValueType(0);
6920 if (VT.isVector()) {
6921 SDValue FoldedVOp = SimplifyVUnaryOp(N);
6922 if (FoldedVOp.getNode()) return FoldedVOp;
6925 // fold (fabs c1) -> fabs(c1)
6927 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
6928 // fold (fabs (fabs x)) -> (fabs x)
6929 if (N0.getOpcode() == ISD::FABS)
6930 return N->getOperand(0);
6931 // fold (fabs (fneg x)) -> (fabs x)
6932 // fold (fabs (fcopysign x, y)) -> (fabs x)
6933 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
6934 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0.getOperand(0));
6936 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
6937 // constant pool values.
6938 if (!TLI.isFAbsFree(VT) &&
6939 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
6940 N0.getOperand(0).getValueType().isInteger() &&
6941 !N0.getOperand(0).getValueType().isVector()) {
6942 SDValue Int = N0.getOperand(0);
6943 EVT IntVT = Int.getValueType();
6944 if (IntVT.isInteger() && !IntVT.isVector()) {
6945 Int = DAG.getNode(ISD::AND, SDLoc(N0), IntVT, Int,
6946 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
6947 AddToWorkList(Int.getNode());
6948 return DAG.getNode(ISD::BITCAST, SDLoc(N),
6949 N->getValueType(0), Int);
6956 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
6957 SDValue Chain = N->getOperand(0);
6958 SDValue N1 = N->getOperand(1);
6959 SDValue N2 = N->getOperand(2);
6961 // If N is a constant we could fold this into a fallthrough or unconditional
6962 // branch. However that doesn't happen very often in normal code, because
6963 // Instcombine/SimplifyCFG should have handled the available opportunities.
6964 // If we did this folding here, it would be necessary to update the
6965 // MachineBasicBlock CFG, which is awkward.
6967 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
6969 if (N1.getOpcode() == ISD::SETCC &&
6970 TLI.isOperationLegalOrCustom(ISD::BR_CC,
6971 N1.getOperand(0).getValueType())) {
6972 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
6973 Chain, N1.getOperand(2),
6974 N1.getOperand(0), N1.getOperand(1), N2);
6977 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
6978 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
6979 (N1.getOperand(0).hasOneUse() &&
6980 N1.getOperand(0).getOpcode() == ISD::SRL))) {
6982 if (N1.getOpcode() == ISD::TRUNCATE) {
6983 // Look pass the truncate.
6984 Trunc = N1.getNode();
6985 N1 = N1.getOperand(0);
6988 // Match this pattern so that we can generate simpler code:
6991 // %b = and i32 %a, 2
6992 // %c = srl i32 %b, 1
6993 // brcond i32 %c ...
6998 // %b = and i32 %a, 2
6999 // %c = setcc eq %b, 0
7002 // This applies only when the AND constant value has one bit set and the
7003 // SRL constant is equal to the log2 of the AND constant. The back-end is
7004 // smart enough to convert the result into a TEST/JMP sequence.
7005 SDValue Op0 = N1.getOperand(0);
7006 SDValue Op1 = N1.getOperand(1);
7008 if (Op0.getOpcode() == ISD::AND &&
7009 Op1.getOpcode() == ISD::Constant) {
7010 SDValue AndOp1 = Op0.getOperand(1);
7012 if (AndOp1.getOpcode() == ISD::Constant) {
7013 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
7015 if (AndConst.isPowerOf2() &&
7016 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
7018 DAG.getSetCC(SDLoc(N),
7019 getSetCCResultType(Op0.getValueType()),
7020 Op0, DAG.getConstant(0, Op0.getValueType()),
7023 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, SDLoc(N),
7024 MVT::Other, Chain, SetCC, N2);
7025 // Don't add the new BRCond into the worklist or else SimplifySelectCC
7026 // will convert it back to (X & C1) >> C2.
7027 CombineTo(N, NewBRCond, false);
7028 // Truncate is dead.
7030 removeFromWorkList(Trunc);
7031 DAG.DeleteNode(Trunc);
7033 // Replace the uses of SRL with SETCC
7034 WorkListRemover DeadNodes(*this);
7035 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
7036 removeFromWorkList(N1.getNode());
7037 DAG.DeleteNode(N1.getNode());
7038 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7044 // Restore N1 if the above transformation doesn't match.
7045 N1 = N->getOperand(1);
7048 // Transform br(xor(x, y)) -> br(x != y)
7049 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
7050 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
7051 SDNode *TheXor = N1.getNode();
7052 SDValue Op0 = TheXor->getOperand(0);
7053 SDValue Op1 = TheXor->getOperand(1);
7054 if (Op0.getOpcode() == Op1.getOpcode()) {
7055 // Avoid missing important xor optimizations.
7056 SDValue Tmp = visitXOR(TheXor);
7057 if (Tmp.getNode()) {
7058 if (Tmp.getNode() != TheXor) {
7059 DEBUG(dbgs() << "\nReplacing.8 ";
7061 dbgs() << "\nWith: ";
7062 Tmp.getNode()->dump(&DAG);
7064 WorkListRemover DeadNodes(*this);
7065 DAG.ReplaceAllUsesOfValueWith(N1, Tmp);
7066 removeFromWorkList(TheXor);
7067 DAG.DeleteNode(TheXor);
7068 return DAG.getNode(ISD::BRCOND, SDLoc(N),
7069 MVT::Other, Chain, Tmp, N2);
7072 // visitXOR has changed XOR's operands or replaced the XOR completely,
7074 return SDValue(N, 0);
7078 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
7080 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
7081 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
7082 Op0.getOpcode() == ISD::XOR) {
7083 TheXor = Op0.getNode();
7087 EVT SetCCVT = N1.getValueType();
7089 SetCCVT = getSetCCResultType(SetCCVT);
7090 SDValue SetCC = DAG.getSetCC(SDLoc(TheXor),
7093 Equal ? ISD::SETEQ : ISD::SETNE);
7094 // Replace the uses of XOR with SETCC
7095 WorkListRemover DeadNodes(*this);
7096 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
7097 removeFromWorkList(N1.getNode());
7098 DAG.DeleteNode(N1.getNode());
7099 return DAG.getNode(ISD::BRCOND, SDLoc(N),
7100 MVT::Other, Chain, SetCC, N2);
7107 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
7109 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
7110 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
7111 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
7113 // If N is a constant we could fold this into a fallthrough or unconditional
7114 // branch. However that doesn't happen very often in normal code, because
7115 // Instcombine/SimplifyCFG should have handled the available opportunities.
7116 // If we did this folding here, it would be necessary to update the
7117 // MachineBasicBlock CFG, which is awkward.
7119 // Use SimplifySetCC to simplify SETCC's.
7120 SDValue Simp = SimplifySetCC(getSetCCResultType(CondLHS.getValueType()),
7121 CondLHS, CondRHS, CC->get(), SDLoc(N),
7123 if (Simp.getNode()) AddToWorkList(Simp.getNode());
7125 // fold to a simpler setcc
7126 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
7127 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
7128 N->getOperand(0), Simp.getOperand(2),
7129 Simp.getOperand(0), Simp.getOperand(1),
7135 /// canFoldInAddressingMode - Return true if 'Use' is a load or a store that
7136 /// uses N as its base pointer and that N may be folded in the load / store
7137 /// addressing mode.
7138 static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
7140 const TargetLowering &TLI) {
7142 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) {
7143 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
7145 VT = Use->getValueType(0);
7146 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) {
7147 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
7149 VT = ST->getValue().getValueType();
7153 TargetLowering::AddrMode AM;
7154 if (N->getOpcode() == ISD::ADD) {
7155 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
7158 AM.BaseOffs = Offset->getSExtValue();
7162 } else if (N->getOpcode() == ISD::SUB) {
7163 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
7166 AM.BaseOffs = -Offset->getSExtValue();
7173 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext()));
7176 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
7177 /// pre-indexed load / store when the base pointer is an add or subtract
7178 /// and it has other uses besides the load / store. After the
7179 /// transformation, the new indexed load / store has effectively folded
7180 /// the add / subtract in and all of its other uses are redirected to the
7181 /// new load / store.
7182 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
7183 if (Level < AfterLegalizeDAG)
7189 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7190 if (LD->isIndexed())
7192 VT = LD->getMemoryVT();
7193 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
7194 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
7196 Ptr = LD->getBasePtr();
7197 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7198 if (ST->isIndexed())
7200 VT = ST->getMemoryVT();
7201 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
7202 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
7204 Ptr = ST->getBasePtr();
7210 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
7211 // out. There is no reason to make this a preinc/predec.
7212 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
7213 Ptr.getNode()->hasOneUse())
7216 // Ask the target to do addressing mode selection.
7219 ISD::MemIndexedMode AM = ISD::UNINDEXED;
7220 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
7223 // Backends without true r+i pre-indexed forms may need to pass a
7224 // constant base with a variable offset so that constant coercion
7225 // will work with the patterns in canonical form.
7226 bool Swapped = false;
7227 if (isa<ConstantSDNode>(BasePtr)) {
7228 std::swap(BasePtr, Offset);
7232 // Don't create a indexed load / store with zero offset.
7233 if (isa<ConstantSDNode>(Offset) &&
7234 cast<ConstantSDNode>(Offset)->isNullValue())
7237 // Try turning it into a pre-indexed load / store except when:
7238 // 1) The new base ptr is a frame index.
7239 // 2) If N is a store and the new base ptr is either the same as or is a
7240 // predecessor of the value being stored.
7241 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
7242 // that would create a cycle.
7243 // 4) All uses are load / store ops that use it as old base ptr.
7245 // Check #1. Preinc'ing a frame index would require copying the stack pointer
7246 // (plus the implicit offset) to a register to preinc anyway.
7247 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
7252 SDValue Val = cast<StoreSDNode>(N)->getValue();
7253 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
7257 // If the offset is a constant, there may be other adds of constants that
7258 // can be folded with this one. We should do this to avoid having to keep
7259 // a copy of the original base pointer.
7260 SmallVector<SDNode *, 16> OtherUses;
7261 if (isa<ConstantSDNode>(Offset))
7262 for (SDNode::use_iterator I = BasePtr.getNode()->use_begin(),
7263 E = BasePtr.getNode()->use_end(); I != E; ++I) {
7265 if (Use == Ptr.getNode())
7268 if (Use->isPredecessorOf(N))
7271 if (Use->getOpcode() != ISD::ADD && Use->getOpcode() != ISD::SUB) {
7276 SDValue Op0 = Use->getOperand(0), Op1 = Use->getOperand(1);
7277 if (Op1.getNode() == BasePtr.getNode())
7278 std::swap(Op0, Op1);
7279 assert(Op0.getNode() == BasePtr.getNode() &&
7280 "Use of ADD/SUB but not an operand");
7282 if (!isa<ConstantSDNode>(Op1)) {
7287 // FIXME: In some cases, we can be smarter about this.
7288 if (Op1.getValueType() != Offset.getValueType()) {
7293 OtherUses.push_back(Use);
7297 std::swap(BasePtr, Offset);
7299 // Now check for #3 and #4.
7300 bool RealUse = false;
7302 // Caches for hasPredecessorHelper
7303 SmallPtrSet<const SDNode *, 32> Visited;
7304 SmallVector<const SDNode *, 16> Worklist;
7306 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
7307 E = Ptr.getNode()->use_end(); I != E; ++I) {
7311 if (N->hasPredecessorHelper(Use, Visited, Worklist))
7314 // If Ptr may be folded in addressing mode of other use, then it's
7315 // not profitable to do this transformation.
7316 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI))
7325 Result = DAG.getIndexedLoad(SDValue(N,0), SDLoc(N),
7326 BasePtr, Offset, AM);
7328 Result = DAG.getIndexedStore(SDValue(N,0), SDLoc(N),
7329 BasePtr, Offset, AM);
7332 DEBUG(dbgs() << "\nReplacing.4 ";
7334 dbgs() << "\nWith: ";
7335 Result.getNode()->dump(&DAG);
7337 WorkListRemover DeadNodes(*this);
7339 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
7340 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
7342 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
7345 // Finally, since the node is now dead, remove it from the graph.
7349 std::swap(BasePtr, Offset);
7351 // Replace other uses of BasePtr that can be updated to use Ptr
7352 for (unsigned i = 0, e = OtherUses.size(); i != e; ++i) {
7353 unsigned OffsetIdx = 1;
7354 if (OtherUses[i]->getOperand(OffsetIdx).getNode() == BasePtr.getNode())
7356 assert(OtherUses[i]->getOperand(!OffsetIdx).getNode() ==
7357 BasePtr.getNode() && "Expected BasePtr operand");
7359 // We need to replace ptr0 in the following expression:
7360 // x0 * offset0 + y0 * ptr0 = t0
7362 // x1 * offset1 + y1 * ptr0 = t1 (the indexed load/store)
7364 // where x0, x1, y0 and y1 in {-1, 1} are given by the types of the
7365 // indexed load/store and the expresion that needs to be re-written.
7367 // Therefore, we have:
7368 // t0 = (x0 * offset0 - x1 * y0 * y1 *offset1) + (y0 * y1) * t1
7370 ConstantSDNode *CN =
7371 cast<ConstantSDNode>(OtherUses[i]->getOperand(OffsetIdx));
7373 APInt Offset0 = CN->getAPIntValue();
7374 APInt Offset1 = cast<ConstantSDNode>(Offset)->getAPIntValue();
7376 X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1;
7377 Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1;
7378 X1 = (AM == ISD::PRE_DEC && !Swapped) ? -1 : 1;
7379 Y1 = (AM == ISD::PRE_DEC && Swapped) ? -1 : 1;
7381 unsigned Opcode = (Y0 * Y1 < 0) ? ISD::SUB : ISD::ADD;
7383 APInt CNV = Offset0;
7384 if (X0 < 0) CNV = -CNV;
7385 if (X1 * Y0 * Y1 < 0) CNV = CNV + Offset1;
7386 else CNV = CNV - Offset1;
7388 // We can now generate the new expression.
7389 SDValue NewOp1 = DAG.getConstant(CNV, CN->getValueType(0));
7390 SDValue NewOp2 = Result.getValue(isLoad ? 1 : 0);
7392 SDValue NewUse = DAG.getNode(Opcode,
7393 SDLoc(OtherUses[i]),
7394 OtherUses[i]->getValueType(0), NewOp1, NewOp2);
7395 DAG.ReplaceAllUsesOfValueWith(SDValue(OtherUses[i], 0), NewUse);
7396 removeFromWorkList(OtherUses[i]);
7397 DAG.DeleteNode(OtherUses[i]);
7400 // Replace the uses of Ptr with uses of the updated base value.
7401 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0));
7402 removeFromWorkList(Ptr.getNode());
7403 DAG.DeleteNode(Ptr.getNode());
7408 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
7409 /// add / sub of the base pointer node into a post-indexed load / store.
7410 /// The transformation folded the add / subtract into the new indexed
7411 /// load / store effectively and all of its uses are redirected to the
7412 /// new load / store.
7413 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
7414 if (Level < AfterLegalizeDAG)
7420 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7421 if (LD->isIndexed())
7423 VT = LD->getMemoryVT();
7424 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
7425 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
7427 Ptr = LD->getBasePtr();
7428 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7429 if (ST->isIndexed())
7431 VT = ST->getMemoryVT();
7432 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
7433 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
7435 Ptr = ST->getBasePtr();
7441 if (Ptr.getNode()->hasOneUse())
7444 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
7445 E = Ptr.getNode()->use_end(); I != E; ++I) {
7448 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
7453 ISD::MemIndexedMode AM = ISD::UNINDEXED;
7454 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
7455 // Don't create a indexed load / store with zero offset.
7456 if (isa<ConstantSDNode>(Offset) &&
7457 cast<ConstantSDNode>(Offset)->isNullValue())
7460 // Try turning it into a post-indexed load / store except when
7461 // 1) All uses are load / store ops that use it as base ptr (and
7462 // it may be folded as addressing mmode).
7463 // 2) Op must be independent of N, i.e. Op is neither a predecessor
7464 // nor a successor of N. Otherwise, if Op is folded that would
7467 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
7471 bool TryNext = false;
7472 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
7473 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
7475 if (Use == Ptr.getNode())
7478 // If all the uses are load / store addresses, then don't do the
7480 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
7481 bool RealUse = false;
7482 for (SDNode::use_iterator III = Use->use_begin(),
7483 EEE = Use->use_end(); III != EEE; ++III) {
7484 SDNode *UseUse = *III;
7485 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI))
7500 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
7501 SDValue Result = isLoad
7502 ? DAG.getIndexedLoad(SDValue(N,0), SDLoc(N),
7503 BasePtr, Offset, AM)
7504 : DAG.getIndexedStore(SDValue(N,0), SDLoc(N),
7505 BasePtr, Offset, AM);
7508 DEBUG(dbgs() << "\nReplacing.5 ";
7510 dbgs() << "\nWith: ";
7511 Result.getNode()->dump(&DAG);
7513 WorkListRemover DeadNodes(*this);
7515 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
7516 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
7518 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
7521 // Finally, since the node is now dead, remove it from the graph.
7524 // Replace the uses of Use with uses of the updated base value.
7525 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
7526 Result.getValue(isLoad ? 1 : 0));
7527 removeFromWorkList(Op);
7537 SDValue DAGCombiner::visitLOAD(SDNode *N) {
7538 LoadSDNode *LD = cast<LoadSDNode>(N);
7539 SDValue Chain = LD->getChain();
7540 SDValue Ptr = LD->getBasePtr();
7542 // If load is not volatile and there are no uses of the loaded value (and
7543 // the updated indexed value in case of indexed loads), change uses of the
7544 // chain value into uses of the chain input (i.e. delete the dead load).
7545 if (!LD->isVolatile()) {
7546 if (N->getValueType(1) == MVT::Other) {
7548 if (!N->hasAnyUseOfValue(0)) {
7549 // It's not safe to use the two value CombineTo variant here. e.g.
7550 // v1, chain2 = load chain1, loc
7551 // v2, chain3 = load chain2, loc
7553 // Now we replace use of chain2 with chain1. This makes the second load
7554 // isomorphic to the one we are deleting, and thus makes this load live.
7555 DEBUG(dbgs() << "\nReplacing.6 ";
7557 dbgs() << "\nWith chain: ";
7558 Chain.getNode()->dump(&DAG);
7560 WorkListRemover DeadNodes(*this);
7561 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
7563 if (N->use_empty()) {
7564 removeFromWorkList(N);
7568 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7572 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
7573 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) {
7574 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
7575 DEBUG(dbgs() << "\nReplacing.7 ";
7577 dbgs() << "\nWith: ";
7578 Undef.getNode()->dump(&DAG);
7579 dbgs() << " and 2 other values\n");
7580 WorkListRemover DeadNodes(*this);
7581 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef);
7582 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
7583 DAG.getUNDEF(N->getValueType(1)));
7584 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain);
7585 removeFromWorkList(N);
7587 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7592 // If this load is directly stored, replace the load value with the stored
7594 // TODO: Handle store large -> read small portion.
7595 // TODO: Handle TRUNCSTORE/LOADEXT
7596 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
7597 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
7598 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
7599 if (PrevST->getBasePtr() == Ptr &&
7600 PrevST->getValue().getValueType() == N->getValueType(0))
7601 return CombineTo(N, Chain.getOperand(1), Chain);
7605 // Try to infer better alignment information than the load already has.
7606 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
7607 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
7608 if (Align > LD->getMemOperand()->getBaseAlignment()) {
7610 DAG.getExtLoad(LD->getExtensionType(), SDLoc(N),
7611 LD->getValueType(0),
7612 Chain, Ptr, LD->getPointerInfo(),
7614 LD->isVolatile(), LD->isNonTemporal(), Align,
7616 return CombineTo(N, NewLoad, SDValue(NewLoad.getNode(), 1), true);
7621 bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA :
7622 TLI.getTargetMachine().getSubtarget<TargetSubtargetInfo>().useAA();
7624 // Walk up chain skipping non-aliasing memory nodes.
7625 SDValue BetterChain = FindBetterChain(N, Chain);
7627 // If there is a better chain.
7628 if (Chain != BetterChain) {
7631 // Replace the chain to void dependency.
7632 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
7633 ReplLoad = DAG.getLoad(N->getValueType(0), SDLoc(LD),
7634 BetterChain, Ptr, LD->getMemOperand());
7636 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD),
7637 LD->getValueType(0),
7638 BetterChain, Ptr, LD->getMemoryVT(),
7639 LD->getMemOperand());
7642 // Create token factor to keep old chain connected.
7643 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N),
7644 MVT::Other, Chain, ReplLoad.getValue(1));
7646 // Make sure the new and old chains are cleaned up.
7647 AddToWorkList(Token.getNode());
7649 // Replace uses with load result and token factor. Don't add users
7651 return CombineTo(N, ReplLoad.getValue(0), Token, false);
7655 // Try transforming N to an indexed load.
7656 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
7657 return SDValue(N, 0);
7659 // Try to slice up N to more direct loads if the slices are mapped to
7660 // different register banks or pairing can take place.
7662 return SDValue(N, 0);
7668 /// \brief Helper structure used to slice a load in smaller loads.
7669 /// Basically a slice is obtained from the following sequence:
7670 /// Origin = load Ty1, Base
7671 /// Shift = srl Ty1 Origin, CstTy Amount
7672 /// Inst = trunc Shift to Ty2
7674 /// Then, it will be rewriten into:
7675 /// Slice = load SliceTy, Base + SliceOffset
7676 /// [Inst = zext Slice to Ty2], only if SliceTy <> Ty2
7678 /// SliceTy is deduced from the number of bits that are actually used to
7680 struct LoadedSlice {
7681 /// \brief Helper structure used to compute the cost of a slice.
7683 /// Are we optimizing for code size.
7688 unsigned CrossRegisterBanksCopies;
7692 Cost(bool ForCodeSize = false)
7693 : ForCodeSize(ForCodeSize), Loads(0), Truncates(0),
7694 CrossRegisterBanksCopies(0), ZExts(0), Shift(0) {}
7696 /// \brief Get the cost of one isolated slice.
7697 Cost(const LoadedSlice &LS, bool ForCodeSize = false)
7698 : ForCodeSize(ForCodeSize), Loads(1), Truncates(0),
7699 CrossRegisterBanksCopies(0), ZExts(0), Shift(0) {
7700 EVT TruncType = LS.Inst->getValueType(0);
7701 EVT LoadedType = LS.getLoadedType();
7702 if (TruncType != LoadedType &&
7703 !LS.DAG->getTargetLoweringInfo().isZExtFree(LoadedType, TruncType))
7707 /// \brief Account for slicing gain in the current cost.
7708 /// Slicing provide a few gains like removing a shift or a
7709 /// truncate. This method allows to grow the cost of the original
7710 /// load with the gain from this slice.
7711 void addSliceGain(const LoadedSlice &LS) {
7712 // Each slice saves a truncate.
7713 const TargetLowering &TLI = LS.DAG->getTargetLoweringInfo();
7714 if (!TLI.isTruncateFree(LS.Inst->getValueType(0),
7715 LS.Inst->getOperand(0).getValueType()))
7717 // If there is a shift amount, this slice gets rid of it.
7720 // If this slice can merge a cross register bank copy, account for it.
7721 if (LS.canMergeExpensiveCrossRegisterBankCopy())
7722 ++CrossRegisterBanksCopies;
7725 Cost &operator+=(const Cost &RHS) {
7727 Truncates += RHS.Truncates;
7728 CrossRegisterBanksCopies += RHS.CrossRegisterBanksCopies;
7734 bool operator==(const Cost &RHS) const {
7735 return Loads == RHS.Loads && Truncates == RHS.Truncates &&
7736 CrossRegisterBanksCopies == RHS.CrossRegisterBanksCopies &&
7737 ZExts == RHS.ZExts && Shift == RHS.Shift;
7740 bool operator!=(const Cost &RHS) const { return !(*this == RHS); }
7742 bool operator<(const Cost &RHS) const {
7743 // Assume cross register banks copies are as expensive as loads.
7744 // FIXME: Do we want some more target hooks?
7745 unsigned ExpensiveOpsLHS = Loads + CrossRegisterBanksCopies;
7746 unsigned ExpensiveOpsRHS = RHS.Loads + RHS.CrossRegisterBanksCopies;
7747 // Unless we are optimizing for code size, consider the
7748 // expensive operation first.
7749 if (!ForCodeSize && ExpensiveOpsLHS != ExpensiveOpsRHS)
7750 return ExpensiveOpsLHS < ExpensiveOpsRHS;
7751 return (Truncates + ZExts + Shift + ExpensiveOpsLHS) <
7752 (RHS.Truncates + RHS.ZExts + RHS.Shift + ExpensiveOpsRHS);
7755 bool operator>(const Cost &RHS) const { return RHS < *this; }
7757 bool operator<=(const Cost &RHS) const { return !(RHS < *this); }
7759 bool operator>=(const Cost &RHS) const { return !(*this < RHS); }
7761 // The last instruction that represent the slice. This should be a
7762 // truncate instruction.
7764 // The original load instruction.
7766 // The right shift amount in bits from the original load.
7768 // The DAG from which Origin came from.
7769 // This is used to get some contextual information about legal types, etc.
7772 LoadedSlice(SDNode *Inst = NULL, LoadSDNode *Origin = NULL,
7773 unsigned Shift = 0, SelectionDAG *DAG = NULL)
7774 : Inst(Inst), Origin(Origin), Shift(Shift), DAG(DAG) {}
7776 LoadedSlice(const LoadedSlice &LS)
7777 : Inst(LS.Inst), Origin(LS.Origin), Shift(LS.Shift), DAG(LS.DAG) {}
7779 /// \brief Get the bits used in a chunk of bits \p BitWidth large.
7780 /// \return Result is \p BitWidth and has used bits set to 1 and
7781 /// not used bits set to 0.
7782 APInt getUsedBits() const {
7783 // Reproduce the trunc(lshr) sequence:
7784 // - Start from the truncated value.
7785 // - Zero extend to the desired bit width.
7787 assert(Origin && "No original load to compare against.");
7788 unsigned BitWidth = Origin->getValueSizeInBits(0);
7789 assert(Inst && "This slice is not bound to an instruction");
7790 assert(Inst->getValueSizeInBits(0) <= BitWidth &&
7791 "Extracted slice is bigger than the whole type!");
7792 APInt UsedBits(Inst->getValueSizeInBits(0), 0);
7793 UsedBits.setAllBits();
7794 UsedBits = UsedBits.zext(BitWidth);
7799 /// \brief Get the size of the slice to be loaded in bytes.
7800 unsigned getLoadedSize() const {
7801 unsigned SliceSize = getUsedBits().countPopulation();
7802 assert(!(SliceSize & 0x7) && "Size is not a multiple of a byte.");
7803 return SliceSize / 8;
7806 /// \brief Get the type that will be loaded for this slice.
7807 /// Note: This may not be the final type for the slice.
7808 EVT getLoadedType() const {
7809 assert(DAG && "Missing context");
7810 LLVMContext &Ctxt = *DAG->getContext();
7811 return EVT::getIntegerVT(Ctxt, getLoadedSize() * 8);
7814 /// \brief Get the alignment of the load used for this slice.
7815 unsigned getAlignment() const {
7816 unsigned Alignment = Origin->getAlignment();
7817 unsigned Offset = getOffsetFromBase();
7819 Alignment = MinAlign(Alignment, Alignment + Offset);
7823 /// \brief Check if this slice can be rewritten with legal operations.
7824 bool isLegal() const {
7825 // An invalid slice is not legal.
7826 if (!Origin || !Inst || !DAG)
7829 // Offsets are for indexed load only, we do not handle that.
7830 if (Origin->getOffset().getOpcode() != ISD::UNDEF)
7833 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
7835 // Check that the type is legal.
7836 EVT SliceType = getLoadedType();
7837 if (!TLI.isTypeLegal(SliceType))
7840 // Check that the load is legal for this type.
7841 if (!TLI.isOperationLegal(ISD::LOAD, SliceType))
7844 // Check that the offset can be computed.
7845 // 1. Check its type.
7846 EVT PtrType = Origin->getBasePtr().getValueType();
7847 if (PtrType == MVT::Untyped || PtrType.isExtended())
7850 // 2. Check that it fits in the immediate.
7851 if (!TLI.isLegalAddImmediate(getOffsetFromBase()))
7854 // 3. Check that the computation is legal.
7855 if (!TLI.isOperationLegal(ISD::ADD, PtrType))
7858 // Check that the zext is legal if it needs one.
7859 EVT TruncateType = Inst->getValueType(0);
7860 if (TruncateType != SliceType &&
7861 !TLI.isOperationLegal(ISD::ZERO_EXTEND, TruncateType))
7867 /// \brief Get the offset in bytes of this slice in the original chunk of
7869 /// \pre DAG != NULL.
7870 uint64_t getOffsetFromBase() const {
7871 assert(DAG && "Missing context.");
7873 DAG->getTargetLoweringInfo().getDataLayout()->isBigEndian();
7874 assert(!(Shift & 0x7) && "Shifts not aligned on Bytes are not supported.");
7875 uint64_t Offset = Shift / 8;
7876 unsigned TySizeInBytes = Origin->getValueSizeInBits(0) / 8;
7877 assert(!(Origin->getValueSizeInBits(0) & 0x7) &&
7878 "The size of the original loaded type is not a multiple of a"
7880 // If Offset is bigger than TySizeInBytes, it means we are loading all
7881 // zeros. This should have been optimized before in the process.
7882 assert(TySizeInBytes > Offset &&
7883 "Invalid shift amount for given loaded size");
7885 Offset = TySizeInBytes - Offset - getLoadedSize();
7889 /// \brief Generate the sequence of instructions to load the slice
7890 /// represented by this object and redirect the uses of this slice to
7891 /// this new sequence of instructions.
7892 /// \pre this->Inst && this->Origin are valid Instructions and this
7893 /// object passed the legal check: LoadedSlice::isLegal returned true.
7894 /// \return The last instruction of the sequence used to load the slice.
7895 SDValue loadSlice() const {
7896 assert(Inst && Origin && "Unable to replace a non-existing slice.");
7897 const SDValue &OldBaseAddr = Origin->getBasePtr();
7898 SDValue BaseAddr = OldBaseAddr;
7899 // Get the offset in that chunk of bytes w.r.t. the endianess.
7900 int64_t Offset = static_cast<int64_t>(getOffsetFromBase());
7901 assert(Offset >= 0 && "Offset too big to fit in int64_t!");
7903 // BaseAddr = BaseAddr + Offset.
7904 EVT ArithType = BaseAddr.getValueType();
7905 BaseAddr = DAG->getNode(ISD::ADD, SDLoc(Origin), ArithType, BaseAddr,
7906 DAG->getConstant(Offset, ArithType));
7909 // Create the type of the loaded slice according to its size.
7910 EVT SliceType = getLoadedType();
7912 // Create the load for the slice.
7913 SDValue LastInst = DAG->getLoad(
7914 SliceType, SDLoc(Origin), Origin->getChain(), BaseAddr,
7915 Origin->getPointerInfo().getWithOffset(Offset), Origin->isVolatile(),
7916 Origin->isNonTemporal(), Origin->isInvariant(), getAlignment());
7917 // If the final type is not the same as the loaded type, this means that
7918 // we have to pad with zero. Create a zero extend for that.
7919 EVT FinalType = Inst->getValueType(0);
7920 if (SliceType != FinalType)
7922 DAG->getNode(ISD::ZERO_EXTEND, SDLoc(LastInst), FinalType, LastInst);
7926 /// \brief Check if this slice can be merged with an expensive cross register
7927 /// bank copy. E.g.,
7929 /// f = bitcast i32 i to float
7930 bool canMergeExpensiveCrossRegisterBankCopy() const {
7931 if (!Inst || !Inst->hasOneUse())
7933 SDNode *Use = *Inst->use_begin();
7934 if (Use->getOpcode() != ISD::BITCAST)
7936 assert(DAG && "Missing context");
7937 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
7938 EVT ResVT = Use->getValueType(0);
7939 const TargetRegisterClass *ResRC = TLI.getRegClassFor(ResVT.getSimpleVT());
7940 const TargetRegisterClass *ArgRC =
7941 TLI.getRegClassFor(Use->getOperand(0).getValueType().getSimpleVT());
7942 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT))
7945 // At this point, we know that we perform a cross-register-bank copy.
7946 // Check if it is expensive.
7947 const TargetRegisterInfo *TRI = TLI.getTargetMachine().getRegisterInfo();
7948 // Assume bitcasts are cheap, unless both register classes do not
7949 // explicitly share a common sub class.
7950 if (!TRI || TRI->getCommonSubClass(ArgRC, ResRC))
7953 // Check if it will be merged with the load.
7954 // 1. Check the alignment constraint.
7955 unsigned RequiredAlignment = TLI.getDataLayout()->getABITypeAlignment(
7956 ResVT.getTypeForEVT(*DAG->getContext()));
7958 if (RequiredAlignment > getAlignment())
7961 // 2. Check that the load is a legal operation for that type.
7962 if (!TLI.isOperationLegal(ISD::LOAD, ResVT))
7965 // 3. Check that we do not have a zext in the way.
7966 if (Inst->getValueType(0) != getLoadedType())
7974 /// \brief Sorts LoadedSlice according to their offset.
7975 struct LoadedSliceSorter {
7976 bool operator()(const LoadedSlice &LHS, const LoadedSlice &RHS) {
7977 assert(LHS.Origin == RHS.Origin && "Different bases not implemented.");
7978 return LHS.getOffsetFromBase() < RHS.getOffsetFromBase();
7982 /// \brief Check that all bits set in \p UsedBits form a dense region, i.e.,
7983 /// \p UsedBits looks like 0..0 1..1 0..0.
7984 static bool areUsedBitsDense(const APInt &UsedBits) {
7985 // If all the bits are one, this is dense!
7986 if (UsedBits.isAllOnesValue())
7989 // Get rid of the unused bits on the right.
7990 APInt NarrowedUsedBits = UsedBits.lshr(UsedBits.countTrailingZeros());
7991 // Get rid of the unused bits on the left.
7992 if (NarrowedUsedBits.countLeadingZeros())
7993 NarrowedUsedBits = NarrowedUsedBits.trunc(NarrowedUsedBits.getActiveBits());
7994 // Check that the chunk of bits is completely used.
7995 return NarrowedUsedBits.isAllOnesValue();
7998 /// \brief Check whether or not \p First and \p Second are next to each other
7999 /// in memory. This means that there is no hole between the bits loaded
8000 /// by \p First and the bits loaded by \p Second.
8001 static bool areSlicesNextToEachOther(const LoadedSlice &First,
8002 const LoadedSlice &Second) {
8003 assert(First.Origin == Second.Origin && First.Origin &&
8004 "Unable to match different memory origins.");
8005 APInt UsedBits = First.getUsedBits();
8006 assert((UsedBits & Second.getUsedBits()) == 0 &&
8007 "Slices are not supposed to overlap.");
8008 UsedBits |= Second.getUsedBits();
8009 return areUsedBitsDense(UsedBits);
8012 /// \brief Adjust the \p GlobalLSCost according to the target
8013 /// paring capabilities and the layout of the slices.
8014 /// \pre \p GlobalLSCost should account for at least as many loads as
8015 /// there is in the slices in \p LoadedSlices.
8016 static void adjustCostForPairing(SmallVectorImpl<LoadedSlice> &LoadedSlices,
8017 LoadedSlice::Cost &GlobalLSCost) {
8018 unsigned NumberOfSlices = LoadedSlices.size();
8019 // If there is less than 2 elements, no pairing is possible.
8020 if (NumberOfSlices < 2)
8023 // Sort the slices so that elements that are likely to be next to each
8024 // other in memory are next to each other in the list.
8025 std::sort(LoadedSlices.begin(), LoadedSlices.end(), LoadedSliceSorter());
8026 const TargetLowering &TLI = LoadedSlices[0].DAG->getTargetLoweringInfo();
8027 // First (resp. Second) is the first (resp. Second) potentially candidate
8028 // to be placed in a paired load.
8029 const LoadedSlice *First = NULL;
8030 const LoadedSlice *Second = NULL;
8031 for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice,
8032 // Set the beginning of the pair.
8035 Second = &LoadedSlices[CurrSlice];
8037 // If First is NULL, it means we start a new pair.
8038 // Get to the next slice.
8042 EVT LoadedType = First->getLoadedType();
8044 // If the types of the slices are different, we cannot pair them.
8045 if (LoadedType != Second->getLoadedType())
8048 // Check if the target supplies paired loads for this type.
8049 unsigned RequiredAlignment = 0;
8050 if (!TLI.hasPairedLoad(LoadedType, RequiredAlignment)) {
8051 // move to the next pair, this type is hopeless.
8055 // Check if we meet the alignment requirement.
8056 if (RequiredAlignment > First->getAlignment())
8059 // Check that both loads are next to each other in memory.
8060 if (!areSlicesNextToEachOther(*First, *Second))
8063 assert(GlobalLSCost.Loads > 0 && "We save more loads than we created!");
8064 --GlobalLSCost.Loads;
8065 // Move to the next pair.
8070 /// \brief Check the profitability of all involved LoadedSlice.
8071 /// Currently, it is considered profitable if there is exactly two
8072 /// involved slices (1) which are (2) next to each other in memory, and
8073 /// whose cost (\see LoadedSlice::Cost) is smaller than the original load (3).
8075 /// Note: The order of the elements in \p LoadedSlices may be modified, but not
8076 /// the elements themselves.
8078 /// FIXME: When the cost model will be mature enough, we can relax
8079 /// constraints (1) and (2).
8080 static bool isSlicingProfitable(SmallVectorImpl<LoadedSlice> &LoadedSlices,
8081 const APInt &UsedBits, bool ForCodeSize) {
8082 unsigned NumberOfSlices = LoadedSlices.size();
8083 if (StressLoadSlicing)
8084 return NumberOfSlices > 1;
8087 if (NumberOfSlices != 2)
8091 if (!areUsedBitsDense(UsedBits))
8095 LoadedSlice::Cost OrigCost(ForCodeSize), GlobalSlicingCost(ForCodeSize);
8096 // The original code has one big load.
8098 for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice) {
8099 const LoadedSlice &LS = LoadedSlices[CurrSlice];
8100 // Accumulate the cost of all the slices.
8101 LoadedSlice::Cost SliceCost(LS, ForCodeSize);
8102 GlobalSlicingCost += SliceCost;
8104 // Account as cost in the original configuration the gain obtained
8105 // with the current slices.
8106 OrigCost.addSliceGain(LS);
8109 // If the target supports paired load, adjust the cost accordingly.
8110 adjustCostForPairing(LoadedSlices, GlobalSlicingCost);
8111 return OrigCost > GlobalSlicingCost;
8114 /// \brief If the given load, \p LI, is used only by trunc or trunc(lshr)
8115 /// operations, split it in the various pieces being extracted.
8117 /// This sort of thing is introduced by SROA.
8118 /// This slicing takes care not to insert overlapping loads.
8119 /// \pre LI is a simple load (i.e., not an atomic or volatile load).
8120 bool DAGCombiner::SliceUpLoad(SDNode *N) {
8121 if (Level < AfterLegalizeDAG)
8124 LoadSDNode *LD = cast<LoadSDNode>(N);
8125 if (LD->isVolatile() || !ISD::isNormalLoad(LD) ||
8126 !LD->getValueType(0).isInteger())
8129 // Keep track of already used bits to detect overlapping values.
8130 // In that case, we will just abort the transformation.
8131 APInt UsedBits(LD->getValueSizeInBits(0), 0);
8133 SmallVector<LoadedSlice, 4> LoadedSlices;
8135 // Check if this load is used as several smaller chunks of bits.
8136 // Basically, look for uses in trunc or trunc(lshr) and record a new chain
8137 // of computation for each trunc.
8138 for (SDNode::use_iterator UI = LD->use_begin(), UIEnd = LD->use_end();
8139 UI != UIEnd; ++UI) {
8140 // Skip the uses of the chain.
8141 if (UI.getUse().getResNo() != 0)
8147 // Check if this is a trunc(lshr).
8148 if (User->getOpcode() == ISD::SRL && User->hasOneUse() &&
8149 isa<ConstantSDNode>(User->getOperand(1))) {
8150 Shift = cast<ConstantSDNode>(User->getOperand(1))->getZExtValue();
8151 User = *User->use_begin();
8154 // At this point, User is a Truncate, iff we encountered, trunc or
8156 if (User->getOpcode() != ISD::TRUNCATE)
8159 // The width of the type must be a power of 2 and greater than 8-bits.
8160 // Otherwise the load cannot be represented in LLVM IR.
8161 // Moreover, if we shifted with a non-8-bits multiple, the slice
8162 // will be accross several bytes. We do not support that.
8163 unsigned Width = User->getValueSizeInBits(0);
8164 if (Width < 8 || !isPowerOf2_32(Width) || (Shift & 0x7))
8167 // Build the slice for this chain of computations.
8168 LoadedSlice LS(User, LD, Shift, &DAG);
8169 APInt CurrentUsedBits = LS.getUsedBits();
8171 // Check if this slice overlaps with another.
8172 if ((CurrentUsedBits & UsedBits) != 0)
8174 // Update the bits used globally.
8175 UsedBits |= CurrentUsedBits;
8177 // Check if the new slice would be legal.
8181 // Record the slice.
8182 LoadedSlices.push_back(LS);
8185 // Abort slicing if it does not seem to be profitable.
8186 if (!isSlicingProfitable(LoadedSlices, UsedBits, ForCodeSize))
8191 // Rewrite each chain to use an independent load.
8192 // By construction, each chain can be represented by a unique load.
8194 // Prepare the argument for the new token factor for all the slices.
8195 SmallVector<SDValue, 8> ArgChains;
8196 for (SmallVectorImpl<LoadedSlice>::const_iterator
8197 LSIt = LoadedSlices.begin(),
8198 LSItEnd = LoadedSlices.end();
8199 LSIt != LSItEnd; ++LSIt) {
8200 SDValue SliceInst = LSIt->loadSlice();
8201 CombineTo(LSIt->Inst, SliceInst, true);
8202 if (SliceInst.getNode()->getOpcode() != ISD::LOAD)
8203 SliceInst = SliceInst.getOperand(0);
8204 assert(SliceInst->getOpcode() == ISD::LOAD &&
8205 "It takes more than a zext to get to the loaded slice!!");
8206 ArgChains.push_back(SliceInst.getValue(1));
8209 SDValue Chain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other,
8210 &ArgChains[0], ArgChains.size());
8211 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
8215 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
8216 /// load is having specific bytes cleared out. If so, return the byte size
8217 /// being masked out and the shift amount.
8218 static std::pair<unsigned, unsigned>
8219 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
8220 std::pair<unsigned, unsigned> Result(0, 0);
8222 // Check for the structure we're looking for.
8223 if (V->getOpcode() != ISD::AND ||
8224 !isa<ConstantSDNode>(V->getOperand(1)) ||
8225 !ISD::isNormalLoad(V->getOperand(0).getNode()))
8228 // Check the chain and pointer.
8229 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
8230 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
8232 // The store should be chained directly to the load or be an operand of a
8234 if (LD == Chain.getNode())
8236 else if (Chain->getOpcode() != ISD::TokenFactor)
8237 return Result; // Fail.
8240 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
8241 if (Chain->getOperand(i).getNode() == LD) {
8245 if (!isOk) return Result;
8248 // This only handles simple types.
8249 if (V.getValueType() != MVT::i16 &&
8250 V.getValueType() != MVT::i32 &&
8251 V.getValueType() != MVT::i64)
8254 // Check the constant mask. Invert it so that the bits being masked out are
8255 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
8256 // follow the sign bit for uniformity.
8257 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
8258 unsigned NotMaskLZ = countLeadingZeros(NotMask);
8259 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
8260 unsigned NotMaskTZ = countTrailingZeros(NotMask);
8261 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
8262 if (NotMaskLZ == 64) return Result; // All zero mask.
8264 // See if we have a continuous run of bits. If so, we have 0*1+0*
8265 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
8268 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
8269 if (V.getValueType() != MVT::i64 && NotMaskLZ)
8270 NotMaskLZ -= 64-V.getValueSizeInBits();
8272 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
8273 switch (MaskedBytes) {
8277 default: return Result; // All one mask, or 5-byte mask.
8280 // Verify that the first bit starts at a multiple of mask so that the access
8281 // is aligned the same as the access width.
8282 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
8284 Result.first = MaskedBytes;
8285 Result.second = NotMaskTZ/8;
8290 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
8291 /// provides a value as specified by MaskInfo. If so, replace the specified
8292 /// store with a narrower store of truncated IVal.
8294 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
8295 SDValue IVal, StoreSDNode *St,
8297 unsigned NumBytes = MaskInfo.first;
8298 unsigned ByteShift = MaskInfo.second;
8299 SelectionDAG &DAG = DC->getDAG();
8301 // Check to see if IVal is all zeros in the part being masked in by the 'or'
8302 // that uses this. If not, this is not a replacement.
8303 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
8304 ByteShift*8, (ByteShift+NumBytes)*8);
8305 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
8307 // Check that it is legal on the target to do this. It is legal if the new
8308 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
8310 MVT VT = MVT::getIntegerVT(NumBytes*8);
8311 if (!DC->isTypeLegal(VT))
8314 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
8315 // shifted by ByteShift and truncated down to NumBytes.
8317 IVal = DAG.getNode(ISD::SRL, SDLoc(IVal), IVal.getValueType(), IVal,
8318 DAG.getConstant(ByteShift*8,
8319 DC->getShiftAmountTy(IVal.getValueType())));
8321 // Figure out the offset for the store and the alignment of the access.
8323 unsigned NewAlign = St->getAlignment();
8325 if (DAG.getTargetLoweringInfo().isLittleEndian())
8326 StOffset = ByteShift;
8328 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
8330 SDValue Ptr = St->getBasePtr();
8332 Ptr = DAG.getNode(ISD::ADD, SDLoc(IVal), Ptr.getValueType(),
8333 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
8334 NewAlign = MinAlign(NewAlign, StOffset);
8337 // Truncate down to the new size.
8338 IVal = DAG.getNode(ISD::TRUNCATE, SDLoc(IVal), VT, IVal);
8341 return DAG.getStore(St->getChain(), SDLoc(St), IVal, Ptr,
8342 St->getPointerInfo().getWithOffset(StOffset),
8343 false, false, NewAlign).getNode();
8347 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
8348 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
8349 /// of the loaded bits, try narrowing the load and store if it would end up
8350 /// being a win for performance or code size.
8351 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
8352 StoreSDNode *ST = cast<StoreSDNode>(N);
8353 if (ST->isVolatile())
8356 SDValue Chain = ST->getChain();
8357 SDValue Value = ST->getValue();
8358 SDValue Ptr = ST->getBasePtr();
8359 EVT VT = Value.getValueType();
8361 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
8364 unsigned Opc = Value.getOpcode();
8366 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
8367 // is a byte mask indicating a consecutive number of bytes, check to see if
8368 // Y is known to provide just those bytes. If so, we try to replace the
8369 // load + replace + store sequence with a single (narrower) store, which makes
8371 if (Opc == ISD::OR) {
8372 std::pair<unsigned, unsigned> MaskedLoad;
8373 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
8374 if (MaskedLoad.first)
8375 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
8376 Value.getOperand(1), ST,this))
8377 return SDValue(NewST, 0);
8379 // Or is commutative, so try swapping X and Y.
8380 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
8381 if (MaskedLoad.first)
8382 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
8383 Value.getOperand(0), ST,this))
8384 return SDValue(NewST, 0);
8387 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
8388 Value.getOperand(1).getOpcode() != ISD::Constant)
8391 SDValue N0 = Value.getOperand(0);
8392 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
8393 Chain == SDValue(N0.getNode(), 1)) {
8394 LoadSDNode *LD = cast<LoadSDNode>(N0);
8395 if (LD->getBasePtr() != Ptr ||
8396 LD->getPointerInfo().getAddrSpace() !=
8397 ST->getPointerInfo().getAddrSpace())
8400 // Find the type to narrow it the load / op / store to.
8401 SDValue N1 = Value.getOperand(1);
8402 unsigned BitWidth = N1.getValueSizeInBits();
8403 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
8404 if (Opc == ISD::AND)
8405 Imm ^= APInt::getAllOnesValue(BitWidth);
8406 if (Imm == 0 || Imm.isAllOnesValue())
8408 unsigned ShAmt = Imm.countTrailingZeros();
8409 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
8410 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
8411 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
8412 while (NewBW < BitWidth &&
8413 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
8414 TLI.isNarrowingProfitable(VT, NewVT))) {
8415 NewBW = NextPowerOf2(NewBW);
8416 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
8418 if (NewBW >= BitWidth)
8421 // If the lsb changed does not start at the type bitwidth boundary,
8422 // start at the previous one.
8424 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
8425 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt,
8426 std::min(BitWidth, ShAmt + NewBW));
8427 if ((Imm & Mask) == Imm) {
8428 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
8429 if (Opc == ISD::AND)
8430 NewImm ^= APInt::getAllOnesValue(NewBW);
8431 uint64_t PtrOff = ShAmt / 8;
8432 // For big endian targets, we need to adjust the offset to the pointer to
8433 // load the correct bytes.
8434 if (TLI.isBigEndian())
8435 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
8437 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
8438 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
8439 if (NewAlign < TLI.getDataLayout()->getABITypeAlignment(NewVTTy))
8442 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LD),
8443 Ptr.getValueType(), Ptr,
8444 DAG.getConstant(PtrOff, Ptr.getValueType()));
8445 SDValue NewLD = DAG.getLoad(NewVT, SDLoc(N0),
8446 LD->getChain(), NewPtr,
8447 LD->getPointerInfo().getWithOffset(PtrOff),
8448 LD->isVolatile(), LD->isNonTemporal(),
8449 LD->isInvariant(), NewAlign,
8451 SDValue NewVal = DAG.getNode(Opc, SDLoc(Value), NewVT, NewLD,
8452 DAG.getConstant(NewImm, NewVT));
8453 SDValue NewST = DAG.getStore(Chain, SDLoc(N),
8455 ST->getPointerInfo().getWithOffset(PtrOff),
8456 false, false, NewAlign);
8458 AddToWorkList(NewPtr.getNode());
8459 AddToWorkList(NewLD.getNode());
8460 AddToWorkList(NewVal.getNode());
8461 WorkListRemover DeadNodes(*this);
8462 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1));
8471 /// TransformFPLoadStorePair - For a given floating point load / store pair,
8472 /// if the load value isn't used by any other operations, then consider
8473 /// transforming the pair to integer load / store operations if the target
8474 /// deems the transformation profitable.
8475 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
8476 StoreSDNode *ST = cast<StoreSDNode>(N);
8477 SDValue Chain = ST->getChain();
8478 SDValue Value = ST->getValue();
8479 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
8480 Value.hasOneUse() &&
8481 Chain == SDValue(Value.getNode(), 1)) {
8482 LoadSDNode *LD = cast<LoadSDNode>(Value);
8483 EVT VT = LD->getMemoryVT();
8484 if (!VT.isFloatingPoint() ||
8485 VT != ST->getMemoryVT() ||
8486 LD->isNonTemporal() ||
8487 ST->isNonTemporal() ||
8488 LD->getPointerInfo().getAddrSpace() != 0 ||
8489 ST->getPointerInfo().getAddrSpace() != 0)
8492 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
8493 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
8494 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
8495 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
8496 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
8499 unsigned LDAlign = LD->getAlignment();
8500 unsigned STAlign = ST->getAlignment();
8501 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
8502 unsigned ABIAlign = TLI.getDataLayout()->getABITypeAlignment(IntVTTy);
8503 if (LDAlign < ABIAlign || STAlign < ABIAlign)
8506 SDValue NewLD = DAG.getLoad(IntVT, SDLoc(Value),
8507 LD->getChain(), LD->getBasePtr(),
8508 LD->getPointerInfo(),
8509 false, false, false, LDAlign);
8511 SDValue NewST = DAG.getStore(NewLD.getValue(1), SDLoc(N),
8512 NewLD, ST->getBasePtr(),
8513 ST->getPointerInfo(),
8514 false, false, STAlign);
8516 AddToWorkList(NewLD.getNode());
8517 AddToWorkList(NewST.getNode());
8518 WorkListRemover DeadNodes(*this);
8519 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1));
8527 /// Helper struct to parse and store a memory address as base + index + offset.
8528 /// We ignore sign extensions when it is safe to do so.
8529 /// The following two expressions are not equivalent. To differentiate we need
8530 /// to store whether there was a sign extension involved in the index
8532 /// (load (i64 add (i64 copyfromreg %c)
8533 /// (i64 signextend (add (i8 load %index)
8537 /// (load (i64 add (i64 copyfromreg %c)
8538 /// (i64 signextend (i32 add (i32 signextend (i8 load %index))
8540 struct BaseIndexOffset {
8544 bool IsIndexSignExt;
8546 BaseIndexOffset() : Offset(0), IsIndexSignExt(false) {}
8548 BaseIndexOffset(SDValue Base, SDValue Index, int64_t Offset,
8549 bool IsIndexSignExt) :
8550 Base(Base), Index(Index), Offset(Offset), IsIndexSignExt(IsIndexSignExt) {}
8552 bool equalBaseIndex(const BaseIndexOffset &Other) {
8553 return Other.Base == Base && Other.Index == Index &&
8554 Other.IsIndexSignExt == IsIndexSignExt;
8557 /// Parses tree in Ptr for base, index, offset addresses.
8558 static BaseIndexOffset match(SDValue Ptr) {
8559 bool IsIndexSignExt = false;
8561 // We only can pattern match BASE + INDEX + OFFSET. If Ptr is not an ADD
8562 // instruction, then it could be just the BASE or everything else we don't
8563 // know how to handle. Just use Ptr as BASE and give up.
8564 if (Ptr->getOpcode() != ISD::ADD)
8565 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
8567 // We know that we have at least an ADD instruction. Try to pattern match
8568 // the simple case of BASE + OFFSET.
8569 if (isa<ConstantSDNode>(Ptr->getOperand(1))) {
8570 int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue();
8571 return BaseIndexOffset(Ptr->getOperand(0), SDValue(), Offset,
8575 // Inside a loop the current BASE pointer is calculated using an ADD and a
8576 // MUL instruction. In this case Ptr is the actual BASE pointer.
8577 // (i64 add (i64 %array_ptr)
8578 // (i64 mul (i64 %induction_var)
8579 // (i64 %element_size)))
8580 if (Ptr->getOperand(1)->getOpcode() == ISD::MUL)
8581 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
8583 // Look at Base + Index + Offset cases.
8584 SDValue Base = Ptr->getOperand(0);
8585 SDValue IndexOffset = Ptr->getOperand(1);
8587 // Skip signextends.
8588 if (IndexOffset->getOpcode() == ISD::SIGN_EXTEND) {
8589 IndexOffset = IndexOffset->getOperand(0);
8590 IsIndexSignExt = true;
8593 // Either the case of Base + Index (no offset) or something else.
8594 if (IndexOffset->getOpcode() != ISD::ADD)
8595 return BaseIndexOffset(Base, IndexOffset, 0, IsIndexSignExt);
8597 // Now we have the case of Base + Index + offset.
8598 SDValue Index = IndexOffset->getOperand(0);
8599 SDValue Offset = IndexOffset->getOperand(1);
8601 if (!isa<ConstantSDNode>(Offset))
8602 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
8604 // Ignore signextends.
8605 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
8606 Index = Index->getOperand(0);
8607 IsIndexSignExt = true;
8608 } else IsIndexSignExt = false;
8610 int64_t Off = cast<ConstantSDNode>(Offset)->getSExtValue();
8611 return BaseIndexOffset(Base, Index, Off, IsIndexSignExt);
8615 /// Holds a pointer to an LSBaseSDNode as well as information on where it
8616 /// is located in a sequence of memory operations connected by a chain.
8618 MemOpLink (LSBaseSDNode *N, int64_t Offset, unsigned Seq):
8619 MemNode(N), OffsetFromBase(Offset), SequenceNum(Seq) { }
8620 // Ptr to the mem node.
8621 LSBaseSDNode *MemNode;
8622 // Offset from the base ptr.
8623 int64_t OffsetFromBase;
8624 // What is the sequence number of this mem node.
8625 // Lowest mem operand in the DAG starts at zero.
8626 unsigned SequenceNum;
8629 /// Sorts store nodes in a link according to their offset from a shared
8631 struct ConsecutiveMemoryChainSorter {
8632 bool operator()(MemOpLink LHS, MemOpLink RHS) {
8633 return LHS.OffsetFromBase < RHS.OffsetFromBase;
8637 bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
8638 EVT MemVT = St->getMemoryVT();
8639 int64_t ElementSizeBytes = MemVT.getSizeInBits()/8;
8640 bool NoVectors = DAG.getMachineFunction().getFunction()->getAttributes().
8641 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
8643 // Don't merge vectors into wider inputs.
8644 if (MemVT.isVector() || !MemVT.isSimple())
8647 // Perform an early exit check. Do not bother looking at stored values that
8648 // are not constants or loads.
8649 SDValue StoredVal = St->getValue();
8650 bool IsLoadSrc = isa<LoadSDNode>(StoredVal);
8651 if (!isa<ConstantSDNode>(StoredVal) && !isa<ConstantFPSDNode>(StoredVal) &&
8655 // Only look at ends of store sequences.
8656 SDValue Chain = SDValue(St, 1);
8657 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE)
8660 // This holds the base pointer, index, and the offset in bytes from the base
8662 BaseIndexOffset BasePtr = BaseIndexOffset::match(St->getBasePtr());
8664 // We must have a base and an offset.
8665 if (!BasePtr.Base.getNode())
8668 // Do not handle stores to undef base pointers.
8669 if (BasePtr.Base.getOpcode() == ISD::UNDEF)
8672 // Save the LoadSDNodes that we find in the chain.
8673 // We need to make sure that these nodes do not interfere with
8674 // any of the store nodes.
8675 SmallVector<LSBaseSDNode*, 8> AliasLoadNodes;
8677 // Save the StoreSDNodes that we find in the chain.
8678 SmallVector<MemOpLink, 8> StoreNodes;
8680 // Walk up the chain and look for nodes with offsets from the same
8681 // base pointer. Stop when reaching an instruction with a different kind
8682 // or instruction which has a different base pointer.
8684 StoreSDNode *Index = St;
8686 // If the chain has more than one use, then we can't reorder the mem ops.
8687 if (Index != St && !SDValue(Index, 1)->hasOneUse())
8690 // Find the base pointer and offset for this memory node.
8691 BaseIndexOffset Ptr = BaseIndexOffset::match(Index->getBasePtr());
8693 // Check that the base pointer is the same as the original one.
8694 if (!Ptr.equalBaseIndex(BasePtr))
8697 // Check that the alignment is the same.
8698 if (Index->getAlignment() != St->getAlignment())
8701 // The memory operands must not be volatile.
8702 if (Index->isVolatile() || Index->isIndexed())
8706 if (StoreSDNode *St = dyn_cast<StoreSDNode>(Index))
8707 if (St->isTruncatingStore())
8710 // The stored memory type must be the same.
8711 if (Index->getMemoryVT() != MemVT)
8714 // We do not allow unaligned stores because we want to prevent overriding
8716 if (Index->getAlignment()*8 != MemVT.getSizeInBits())
8719 // We found a potential memory operand to merge.
8720 StoreNodes.push_back(MemOpLink(Index, Ptr.Offset, Seq++));
8722 // Find the next memory operand in the chain. If the next operand in the
8723 // chain is a store then move up and continue the scan with the next
8724 // memory operand. If the next operand is a load save it and use alias
8725 // information to check if it interferes with anything.
8726 SDNode *NextInChain = Index->getChain().getNode();
8728 if (StoreSDNode *STn = dyn_cast<StoreSDNode>(NextInChain)) {
8729 // We found a store node. Use it for the next iteration.
8732 } else if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(NextInChain)) {
8733 if (Ldn->isVolatile()) {
8738 // Save the load node for later. Continue the scan.
8739 AliasLoadNodes.push_back(Ldn);
8740 NextInChain = Ldn->getChain().getNode();
8749 // Check if there is anything to merge.
8750 if (StoreNodes.size() < 2)
8753 // Sort the memory operands according to their distance from the base pointer.
8754 std::sort(StoreNodes.begin(), StoreNodes.end(),
8755 ConsecutiveMemoryChainSorter());
8757 // Scan the memory operations on the chain and find the first non-consecutive
8758 // store memory address.
8759 unsigned LastConsecutiveStore = 0;
8760 int64_t StartAddress = StoreNodes[0].OffsetFromBase;
8761 for (unsigned i = 0, e = StoreNodes.size(); i < e; ++i) {
8763 // Check that the addresses are consecutive starting from the second
8764 // element in the list of stores.
8766 int64_t CurrAddress = StoreNodes[i].OffsetFromBase;
8767 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
8772 // Check if this store interferes with any of the loads that we found.
8773 for (unsigned ld = 0, lde = AliasLoadNodes.size(); ld < lde; ++ld)
8774 if (isAlias(AliasLoadNodes[ld], StoreNodes[i].MemNode)) {
8778 // We found a load that alias with this store. Stop the sequence.
8782 // Mark this node as useful.
8783 LastConsecutiveStore = i;
8786 // The node with the lowest store address.
8787 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;
8789 // Store the constants into memory as one consecutive store.
8791 unsigned LastLegalType = 0;
8792 unsigned LastLegalVectorType = 0;
8793 bool NonZero = false;
8794 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
8795 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
8796 SDValue StoredVal = St->getValue();
8798 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(StoredVal)) {
8799 NonZero |= !C->isNullValue();
8800 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) {
8801 NonZero |= !C->getConstantFPValue()->isNullValue();
8807 // Find a legal type for the constant store.
8808 unsigned StoreBW = (i+1) * ElementSizeBytes * 8;
8809 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
8810 if (TLI.isTypeLegal(StoreTy))
8811 LastLegalType = i+1;
8812 // Or check whether a truncstore is legal.
8813 else if (TLI.getTypeAction(*DAG.getContext(), StoreTy) ==
8814 TargetLowering::TypePromoteInteger) {
8815 EVT LegalizedStoredValueTy =
8816 TLI.getTypeToTransformTo(*DAG.getContext(), StoredVal.getValueType());
8817 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy))
8818 LastLegalType = i+1;
8821 // Find a legal type for the vector store.
8822 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
8823 if (TLI.isTypeLegal(Ty))
8824 LastLegalVectorType = i + 1;
8827 // We only use vectors if the constant is known to be zero and the
8828 // function is not marked with the noimplicitfloat attribute.
8829 if (NonZero || NoVectors)
8830 LastLegalVectorType = 0;
8832 // Check if we found a legal integer type to store.
8833 if (LastLegalType == 0 && LastLegalVectorType == 0)
8836 bool UseVector = (LastLegalVectorType > LastLegalType) && !NoVectors;
8837 unsigned NumElem = UseVector ? LastLegalVectorType : LastLegalType;
8839 // Make sure we have something to merge.
8843 unsigned EarliestNodeUsed = 0;
8844 for (unsigned i=0; i < NumElem; ++i) {
8845 // Find a chain for the new wide-store operand. Notice that some
8846 // of the store nodes that we found may not be selected for inclusion
8847 // in the wide store. The chain we use needs to be the chain of the
8848 // earliest store node which is *used* and replaced by the wide store.
8849 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum)
8850 EarliestNodeUsed = i;
8853 // The earliest Node in the DAG.
8854 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode;
8855 SDLoc DL(StoreNodes[0].MemNode);
8859 // Find a legal type for the vector store.
8860 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
8861 assert(TLI.isTypeLegal(Ty) && "Illegal vector store");
8862 StoredVal = DAG.getConstant(0, Ty);
8864 unsigned StoreBW = NumElem * ElementSizeBytes * 8;
8865 APInt StoreInt(StoreBW, 0);
8867 // Construct a single integer constant which is made of the smaller
8869 bool IsLE = TLI.isLittleEndian();
8870 for (unsigned i = 0; i < NumElem ; ++i) {
8871 unsigned Idx = IsLE ?(NumElem - 1 - i) : i;
8872 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[Idx].MemNode);
8873 SDValue Val = St->getValue();
8874 StoreInt<<=ElementSizeBytes*8;
8875 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val)) {
8876 StoreInt|=C->getAPIntValue().zext(StoreBW);
8877 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) {
8878 StoreInt|= C->getValueAPF().bitcastToAPInt().zext(StoreBW);
8880 assert(false && "Invalid constant element type");
8884 // Create the new Load and Store operations.
8885 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
8886 StoredVal = DAG.getConstant(StoreInt, StoreTy);
8889 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), DL, StoredVal,
8890 FirstInChain->getBasePtr(),
8891 FirstInChain->getPointerInfo(),
8893 FirstInChain->getAlignment());
8895 // Replace the first store with the new store
8896 CombineTo(EarliestOp, NewStore);
8897 // Erase all other stores.
8898 for (unsigned i = 0; i < NumElem ; ++i) {
8899 if (StoreNodes[i].MemNode == EarliestOp)
8901 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
8902 // ReplaceAllUsesWith will replace all uses that existed when it was
8903 // called, but graph optimizations may cause new ones to appear. For
8904 // example, the case in pr14333 looks like
8906 // St's chain -> St -> another store -> X
8908 // And the only difference from St to the other store is the chain.
8909 // When we change it's chain to be St's chain they become identical,
8910 // get CSEed and the net result is that X is now a use of St.
8911 // Since we know that St is redundant, just iterate.
8912 while (!St->use_empty())
8913 DAG.ReplaceAllUsesWith(SDValue(St, 0), St->getChain());
8914 removeFromWorkList(St);
8921 // Below we handle the case of multiple consecutive stores that
8922 // come from multiple consecutive loads. We merge them into a single
8923 // wide load and a single wide store.
8925 // Look for load nodes which are used by the stored values.
8926 SmallVector<MemOpLink, 8> LoadNodes;
8928 // Find acceptable loads. Loads need to have the same chain (token factor),
8929 // must not be zext, volatile, indexed, and they must be consecutive.
8930 BaseIndexOffset LdBasePtr;
8931 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
8932 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
8933 LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue());
8936 // Loads must only have one use.
8937 if (!Ld->hasNUsesOfValue(1, 0))
8940 // Check that the alignment is the same as the stores.
8941 if (Ld->getAlignment() != St->getAlignment())
8944 // The memory operands must not be volatile.
8945 if (Ld->isVolatile() || Ld->isIndexed())
8948 // We do not accept ext loads.
8949 if (Ld->getExtensionType() != ISD::NON_EXTLOAD)
8952 // The stored memory type must be the same.
8953 if (Ld->getMemoryVT() != MemVT)
8956 BaseIndexOffset LdPtr = BaseIndexOffset::match(Ld->getBasePtr());
8957 // If this is not the first ptr that we check.
8958 if (LdBasePtr.Base.getNode()) {
8959 // The base ptr must be the same.
8960 if (!LdPtr.equalBaseIndex(LdBasePtr))
8963 // Check that all other base pointers are the same as this one.
8967 // We found a potential memory operand to merge.
8968 LoadNodes.push_back(MemOpLink(Ld, LdPtr.Offset, 0));
8971 if (LoadNodes.size() < 2)
8974 // Scan the memory operations on the chain and find the first non-consecutive
8975 // load memory address. These variables hold the index in the store node
8977 unsigned LastConsecutiveLoad = 0;
8978 // This variable refers to the size and not index in the array.
8979 unsigned LastLegalVectorType = 0;
8980 unsigned LastLegalIntegerType = 0;
8981 StartAddress = LoadNodes[0].OffsetFromBase;
8982 SDValue FirstChain = LoadNodes[0].MemNode->getChain();
8983 for (unsigned i = 1; i < LoadNodes.size(); ++i) {
8984 // All loads much share the same chain.
8985 if (LoadNodes[i].MemNode->getChain() != FirstChain)
8988 int64_t CurrAddress = LoadNodes[i].OffsetFromBase;
8989 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
8991 LastConsecutiveLoad = i;
8993 // Find a legal type for the vector store.
8994 EVT StoreTy = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
8995 if (TLI.isTypeLegal(StoreTy))
8996 LastLegalVectorType = i + 1;
8998 // Find a legal type for the integer store.
8999 unsigned StoreBW = (i+1) * ElementSizeBytes * 8;
9000 StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
9001 if (TLI.isTypeLegal(StoreTy))
9002 LastLegalIntegerType = i + 1;
9003 // Or check whether a truncstore and extload is legal.
9004 else if (TLI.getTypeAction(*DAG.getContext(), StoreTy) ==
9005 TargetLowering::TypePromoteInteger) {
9006 EVT LegalizedStoredValueTy =
9007 TLI.getTypeToTransformTo(*DAG.getContext(), StoreTy);
9008 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy) &&
9009 TLI.isLoadExtLegal(ISD::ZEXTLOAD, StoreTy) &&
9010 TLI.isLoadExtLegal(ISD::SEXTLOAD, StoreTy) &&
9011 TLI.isLoadExtLegal(ISD::EXTLOAD, StoreTy))
9012 LastLegalIntegerType = i+1;
9016 // Only use vector types if the vector type is larger than the integer type.
9017 // If they are the same, use integers.
9018 bool UseVectorTy = LastLegalVectorType > LastLegalIntegerType && !NoVectors;
9019 unsigned LastLegalType = std::max(LastLegalVectorType, LastLegalIntegerType);
9021 // We add +1 here because the LastXXX variables refer to location while
9022 // the NumElem refers to array/index size.
9023 unsigned NumElem = std::min(LastConsecutiveStore, LastConsecutiveLoad) + 1;
9024 NumElem = std::min(LastLegalType, NumElem);
9029 // The earliest Node in the DAG.
9030 unsigned EarliestNodeUsed = 0;
9031 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode;
9032 for (unsigned i=1; i<NumElem; ++i) {
9033 // Find a chain for the new wide-store operand. Notice that some
9034 // of the store nodes that we found may not be selected for inclusion
9035 // in the wide store. The chain we use needs to be the chain of the
9036 // earliest store node which is *used* and replaced by the wide store.
9037 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum)
9038 EarliestNodeUsed = i;
9041 // Find if it is better to use vectors or integers to load and store
9045 JointMemOpVT = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
9047 unsigned StoreBW = NumElem * ElementSizeBytes * 8;
9048 JointMemOpVT = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
9051 SDLoc LoadDL(LoadNodes[0].MemNode);
9052 SDLoc StoreDL(StoreNodes[0].MemNode);
9054 LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode);
9055 SDValue NewLoad = DAG.getLoad(JointMemOpVT, LoadDL,
9056 FirstLoad->getChain(),
9057 FirstLoad->getBasePtr(),
9058 FirstLoad->getPointerInfo(),
9059 false, false, false,
9060 FirstLoad->getAlignment());
9062 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), StoreDL, NewLoad,
9063 FirstInChain->getBasePtr(),
9064 FirstInChain->getPointerInfo(), false, false,
9065 FirstInChain->getAlignment());
9067 // Replace one of the loads with the new load.
9068 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[0].MemNode);
9069 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1),
9070 SDValue(NewLoad.getNode(), 1));
9072 // Remove the rest of the load chains.
9073 for (unsigned i = 1; i < NumElem ; ++i) {
9074 // Replace all chain users of the old load nodes with the chain of the new
9076 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[i].MemNode);
9077 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Ld->getChain());
9080 // Replace the first store with the new store.
9081 CombineTo(EarliestOp, NewStore);
9082 // Erase all other stores.
9083 for (unsigned i = 0; i < NumElem ; ++i) {
9084 // Remove all Store nodes.
9085 if (StoreNodes[i].MemNode == EarliestOp)
9087 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
9088 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain());
9089 removeFromWorkList(St);
9096 SDValue DAGCombiner::visitSTORE(SDNode *N) {
9097 StoreSDNode *ST = cast<StoreSDNode>(N);
9098 SDValue Chain = ST->getChain();
9099 SDValue Value = ST->getValue();
9100 SDValue Ptr = ST->getBasePtr();
9102 // If this is a store of a bit convert, store the input value if the
9103 // resultant store does not need a higher alignment than the original.
9104 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
9105 ST->isUnindexed()) {
9106 unsigned OrigAlign = ST->getAlignment();
9107 EVT SVT = Value.getOperand(0).getValueType();
9108 unsigned Align = TLI.getDataLayout()->
9109 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
9110 if (Align <= OrigAlign &&
9111 ((!LegalOperations && !ST->isVolatile()) ||
9112 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
9113 return DAG.getStore(Chain, SDLoc(N), Value.getOperand(0),
9114 Ptr, ST->getPointerInfo(), ST->isVolatile(),
9115 ST->isNonTemporal(), OrigAlign,
9119 // Turn 'store undef, Ptr' -> nothing.
9120 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
9123 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
9124 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
9125 // NOTE: If the original store is volatile, this transform must not increase
9126 // the number of stores. For example, on x86-32 an f64 can be stored in one
9127 // processor operation but an i64 (which is not legal) requires two. So the
9128 // transform should not be done in this case.
9129 if (Value.getOpcode() != ISD::TargetConstantFP) {
9131 switch (CFP->getSimpleValueType(0).SimpleTy) {
9132 default: llvm_unreachable("Unknown FP type");
9133 case MVT::f16: // We don't do this for these yet.
9139 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
9140 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
9141 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
9142 bitcastToAPInt().getZExtValue(), MVT::i32);
9143 return DAG.getStore(Chain, SDLoc(N), Tmp,
9144 Ptr, ST->getMemOperand());
9148 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
9149 !ST->isVolatile()) ||
9150 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
9151 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
9152 getZExtValue(), MVT::i64);
9153 return DAG.getStore(Chain, SDLoc(N), Tmp,
9154 Ptr, ST->getMemOperand());
9157 if (!ST->isVolatile() &&
9158 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
9159 // Many FP stores are not made apparent until after legalize, e.g. for
9160 // argument passing. Since this is so common, custom legalize the
9161 // 64-bit integer store into two 32-bit stores.
9162 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
9163 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
9164 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
9165 if (TLI.isBigEndian()) std::swap(Lo, Hi);
9167 unsigned Alignment = ST->getAlignment();
9168 bool isVolatile = ST->isVolatile();
9169 bool isNonTemporal = ST->isNonTemporal();
9170 const MDNode *TBAAInfo = ST->getTBAAInfo();
9172 SDValue St0 = DAG.getStore(Chain, SDLoc(ST), Lo,
9173 Ptr, ST->getPointerInfo(),
9174 isVolatile, isNonTemporal,
9175 ST->getAlignment(), TBAAInfo);
9176 Ptr = DAG.getNode(ISD::ADD, SDLoc(N), Ptr.getValueType(), Ptr,
9177 DAG.getConstant(4, Ptr.getValueType()));
9178 Alignment = MinAlign(Alignment, 4U);
9179 SDValue St1 = DAG.getStore(Chain, SDLoc(ST), Hi,
9180 Ptr, ST->getPointerInfo().getWithOffset(4),
9181 isVolatile, isNonTemporal,
9182 Alignment, TBAAInfo);
9183 return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other,
9192 // Try to infer better alignment information than the store already has.
9193 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
9194 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
9195 if (Align > ST->getAlignment())
9196 return DAG.getTruncStore(Chain, SDLoc(N), Value,
9197 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
9198 ST->isVolatile(), ST->isNonTemporal(), Align,
9203 // Try transforming a pair floating point load / store ops to integer
9204 // load / store ops.
9205 SDValue NewST = TransformFPLoadStorePair(N);
9206 if (NewST.getNode())
9209 bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA :
9210 TLI.getTargetMachine().getSubtarget<TargetSubtargetInfo>().useAA();
9212 // Walk up chain skipping non-aliasing memory nodes.
9213 SDValue BetterChain = FindBetterChain(N, Chain);
9215 // If there is a better chain.
9216 if (Chain != BetterChain) {
9219 // Replace the chain to avoid dependency.
9220 if (ST->isTruncatingStore()) {
9221 ReplStore = DAG.getTruncStore(BetterChain, SDLoc(N), Value, Ptr,
9222 ST->getMemoryVT(), ST->getMemOperand());
9224 ReplStore = DAG.getStore(BetterChain, SDLoc(N), Value, Ptr,
9225 ST->getMemOperand());
9228 // Create token to keep both nodes around.
9229 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N),
9230 MVT::Other, Chain, ReplStore);
9232 // Make sure the new and old chains are cleaned up.
9233 AddToWorkList(Token.getNode());
9235 // Don't add users to work list.
9236 return CombineTo(N, Token, false);
9240 // Try transforming N to an indexed store.
9241 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
9242 return SDValue(N, 0);
9244 // FIXME: is there such a thing as a truncating indexed store?
9245 if (ST->isTruncatingStore() && ST->isUnindexed() &&
9246 Value.getValueType().isInteger()) {
9247 // See if we can simplify the input to this truncstore with knowledge that
9248 // only the low bits are being used. For example:
9249 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
9251 GetDemandedBits(Value,
9252 APInt::getLowBitsSet(
9253 Value.getValueType().getScalarType().getSizeInBits(),
9254 ST->getMemoryVT().getScalarType().getSizeInBits()));
9255 AddToWorkList(Value.getNode());
9256 if (Shorter.getNode())
9257 return DAG.getTruncStore(Chain, SDLoc(N), Shorter,
9258 Ptr, ST->getMemoryVT(), ST->getMemOperand());
9260 // Otherwise, see if we can simplify the operation with
9261 // SimplifyDemandedBits, which only works if the value has a single use.
9262 if (SimplifyDemandedBits(Value,
9263 APInt::getLowBitsSet(
9264 Value.getValueType().getScalarType().getSizeInBits(),
9265 ST->getMemoryVT().getScalarType().getSizeInBits())))
9266 return SDValue(N, 0);
9269 // If this is a load followed by a store to the same location, then the store
9271 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
9272 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
9273 ST->isUnindexed() && !ST->isVolatile() &&
9274 // There can't be any side effects between the load and store, such as
9276 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
9277 // The store is dead, remove it.
9282 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
9283 // truncating store. We can do this even if this is already a truncstore.
9284 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
9285 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
9286 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
9287 ST->getMemoryVT())) {
9288 return DAG.getTruncStore(Chain, SDLoc(N), Value.getOperand(0),
9289 Ptr, ST->getMemoryVT(), ST->getMemOperand());
9292 // Only perform this optimization before the types are legal, because we
9293 // don't want to perform this optimization on every DAGCombine invocation.
9295 bool EverChanged = false;
9298 // There can be multiple store sequences on the same chain.
9299 // Keep trying to merge store sequences until we are unable to do so
9300 // or until we merge the last store on the chain.
9301 bool Changed = MergeConsecutiveStores(ST);
9302 EverChanged |= Changed;
9303 if (!Changed) break;
9304 } while (ST->getOpcode() != ISD::DELETED_NODE);
9307 return SDValue(N, 0);
9310 return ReduceLoadOpStoreWidth(N);
9313 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
9314 SDValue InVec = N->getOperand(0);
9315 SDValue InVal = N->getOperand(1);
9316 SDValue EltNo = N->getOperand(2);
9319 // If the inserted element is an UNDEF, just use the input vector.
9320 if (InVal.getOpcode() == ISD::UNDEF)
9323 EVT VT = InVec.getValueType();
9325 // If we can't generate a legal BUILD_VECTOR, exit
9326 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
9329 // Check that we know which element is being inserted
9330 if (!isa<ConstantSDNode>(EltNo))
9332 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
9334 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
9335 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
9337 SmallVector<SDValue, 8> Ops;
9338 // Do not combine these two vectors if the output vector will not replace
9339 // the input vector.
9340 if (InVec.getOpcode() == ISD::BUILD_VECTOR && InVec.hasOneUse()) {
9341 Ops.append(InVec.getNode()->op_begin(),
9342 InVec.getNode()->op_end());
9343 } else if (InVec.getOpcode() == ISD::UNDEF) {
9344 unsigned NElts = VT.getVectorNumElements();
9345 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
9350 // Insert the element
9351 if (Elt < Ops.size()) {
9352 // All the operands of BUILD_VECTOR must have the same type;
9353 // we enforce that here.
9354 EVT OpVT = Ops[0].getValueType();
9355 if (InVal.getValueType() != OpVT)
9356 InVal = OpVT.bitsGT(InVal.getValueType()) ?
9357 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
9358 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
9362 // Return the new vector
9363 return DAG.getNode(ISD::BUILD_VECTOR, dl,
9364 VT, &Ops[0], Ops.size());
9367 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
9368 // (vextract (scalar_to_vector val, 0) -> val
9369 SDValue InVec = N->getOperand(0);
9370 EVT VT = InVec.getValueType();
9371 EVT NVT = N->getValueType(0);
9373 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
9374 // Check if the result type doesn't match the inserted element type. A
9375 // SCALAR_TO_VECTOR may truncate the inserted element and the
9376 // EXTRACT_VECTOR_ELT may widen the extracted vector.
9377 SDValue InOp = InVec.getOperand(0);
9378 if (InOp.getValueType() != NVT) {
9379 assert(InOp.getValueType().isInteger() && NVT.isInteger());
9380 return DAG.getSExtOrTrunc(InOp, SDLoc(InVec), NVT);
9385 SDValue EltNo = N->getOperand(1);
9386 bool ConstEltNo = isa<ConstantSDNode>(EltNo);
9388 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
9389 // We only perform this optimization before the op legalization phase because
9390 // we may introduce new vector instructions which are not backed by TD
9391 // patterns. For example on AVX, extracting elements from a wide vector
9392 // without using extract_subvector.
9393 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
9394 && ConstEltNo && !LegalOperations) {
9395 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
9396 int NumElem = VT.getVectorNumElements();
9397 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
9398 // Find the new index to extract from.
9399 int OrigElt = SVOp->getMaskElt(Elt);
9401 // Extracting an undef index is undef.
9403 return DAG.getUNDEF(NVT);
9405 // Select the right vector half to extract from.
9406 if (OrigElt < NumElem) {
9407 InVec = InVec->getOperand(0);
9409 InVec = InVec->getOperand(1);
9413 EVT IndexTy = TLI.getVectorIdxTy();
9414 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), NVT,
9415 InVec, DAG.getConstant(OrigElt, IndexTy));
9418 // Perform only after legalization to ensure build_vector / vector_shuffle
9419 // optimizations have already been done.
9420 if (!LegalOperations) return SDValue();
9422 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
9423 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
9424 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
9427 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
9428 bool NewLoad = false;
9429 bool BCNumEltsChanged = false;
9430 EVT ExtVT = VT.getVectorElementType();
9433 // If the result of load has to be truncated, then it's not necessarily
9435 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT))
9438 if (InVec.getOpcode() == ISD::BITCAST) {
9439 // Don't duplicate a load with other uses.
9440 if (!InVec.hasOneUse())
9443 EVT BCVT = InVec.getOperand(0).getValueType();
9444 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
9446 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
9447 BCNumEltsChanged = true;
9448 InVec = InVec.getOperand(0);
9449 ExtVT = BCVT.getVectorElementType();
9453 LoadSDNode *LN0 = NULL;
9454 const ShuffleVectorSDNode *SVN = NULL;
9455 if (ISD::isNormalLoad(InVec.getNode())) {
9456 LN0 = cast<LoadSDNode>(InVec);
9457 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
9458 InVec.getOperand(0).getValueType() == ExtVT &&
9459 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
9460 // Don't duplicate a load with other uses.
9461 if (!InVec.hasOneUse())
9464 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
9465 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
9466 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
9468 // (load $addr+1*size)
9470 // Don't duplicate a load with other uses.
9471 if (!InVec.hasOneUse())
9474 // If the bit convert changed the number of elements, it is unsafe
9475 // to examine the mask.
9476 if (BCNumEltsChanged)
9479 // Select the input vector, guarding against out of range extract vector.
9480 unsigned NumElems = VT.getVectorNumElements();
9481 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
9482 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
9484 if (InVec.getOpcode() == ISD::BITCAST) {
9485 // Don't duplicate a load with other uses.
9486 if (!InVec.hasOneUse())
9489 InVec = InVec.getOperand(0);
9491 if (ISD::isNormalLoad(InVec.getNode())) {
9492 LN0 = cast<LoadSDNode>(InVec);
9493 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
9497 // Make sure we found a non-volatile load and the extractelement is
9499 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
9502 // If Idx was -1 above, Elt is going to be -1, so just return undef.
9504 return DAG.getUNDEF(LVT);
9506 unsigned Align = LN0->getAlignment();
9508 // Check the resultant load doesn't need a higher alignment than the
9512 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
9514 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
9520 SDValue NewPtr = LN0->getBasePtr();
9521 unsigned PtrOff = 0;
9524 PtrOff = LVT.getSizeInBits() * Elt / 8;
9525 EVT PtrType = NewPtr.getValueType();
9526 if (TLI.isBigEndian())
9527 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
9528 NewPtr = DAG.getNode(ISD::ADD, SDLoc(N), PtrType, NewPtr,
9529 DAG.getConstant(PtrOff, PtrType));
9532 // The replacement we need to do here is a little tricky: we need to
9533 // replace an extractelement of a load with a load.
9534 // Use ReplaceAllUsesOfValuesWith to do the replacement.
9535 // Note that this replacement assumes that the extractvalue is the only
9536 // use of the load; that's okay because we don't want to perform this
9537 // transformation in other cases anyway.
9540 if (NVT.bitsGT(LVT)) {
9541 // If the result type of vextract is wider than the load, then issue an
9542 // extending load instead.
9543 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT)
9544 ? ISD::ZEXTLOAD : ISD::EXTLOAD;
9545 Load = DAG.getExtLoad(ExtType, SDLoc(N), NVT, LN0->getChain(),
9546 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff),
9547 LVT, LN0->isVolatile(), LN0->isNonTemporal(),
9548 Align, LN0->getTBAAInfo());
9549 Chain = Load.getValue(1);
9551 Load = DAG.getLoad(LVT, SDLoc(N), LN0->getChain(), NewPtr,
9552 LN0->getPointerInfo().getWithOffset(PtrOff),
9553 LN0->isVolatile(), LN0->isNonTemporal(),
9554 LN0->isInvariant(), Align, LN0->getTBAAInfo());
9555 Chain = Load.getValue(1);
9556 if (NVT.bitsLT(LVT))
9557 Load = DAG.getNode(ISD::TRUNCATE, SDLoc(N), NVT, Load);
9559 Load = DAG.getNode(ISD::BITCAST, SDLoc(N), NVT, Load);
9561 WorkListRemover DeadNodes(*this);
9562 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) };
9563 SDValue To[] = { Load, Chain };
9564 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
9565 // Since we're explcitly calling ReplaceAllUses, add the new node to the
9566 // worklist explicitly as well.
9567 AddToWorkList(Load.getNode());
9568 AddUsersToWorkList(Load.getNode()); // Add users too
9569 // Make sure to revisit this node to clean it up; it will usually be dead.
9571 return SDValue(N, 0);
9577 // Simplify (build_vec (ext )) to (bitcast (build_vec ))
9578 SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) {
9579 // We perform this optimization post type-legalization because
9580 // the type-legalizer often scalarizes integer-promoted vectors.
9581 // Performing this optimization before may create bit-casts which
9582 // will be type-legalized to complex code sequences.
9583 // We perform this optimization only before the operation legalizer because we
9584 // may introduce illegal operations.
9585 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes)
9588 unsigned NumInScalars = N->getNumOperands();
9590 EVT VT = N->getValueType(0);
9592 // Check to see if this is a BUILD_VECTOR of a bunch of values
9593 // which come from any_extend or zero_extend nodes. If so, we can create
9594 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR
9595 // optimizations. We do not handle sign-extend because we can't fill the sign
9597 EVT SourceType = MVT::Other;
9598 bool AllAnyExt = true;
9600 for (unsigned i = 0; i != NumInScalars; ++i) {
9601 SDValue In = N->getOperand(i);
9602 // Ignore undef inputs.
9603 if (In.getOpcode() == ISD::UNDEF) continue;
9605 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
9606 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
9608 // Abort if the element is not an extension.
9609 if (!ZeroExt && !AnyExt) {
9610 SourceType = MVT::Other;
9614 // The input is a ZeroExt or AnyExt. Check the original type.
9615 EVT InTy = In.getOperand(0).getValueType();
9617 // Check that all of the widened source types are the same.
9618 if (SourceType == MVT::Other)
9621 else if (InTy != SourceType) {
9622 // Multiple income types. Abort.
9623 SourceType = MVT::Other;
9627 // Check if all of the extends are ANY_EXTENDs.
9628 AllAnyExt &= AnyExt;
9631 // In order to have valid types, all of the inputs must be extended from the
9632 // same source type and all of the inputs must be any or zero extend.
9633 // Scalar sizes must be a power of two.
9634 EVT OutScalarTy = VT.getScalarType();
9635 bool ValidTypes = SourceType != MVT::Other &&
9636 isPowerOf2_32(OutScalarTy.getSizeInBits()) &&
9637 isPowerOf2_32(SourceType.getSizeInBits());
9639 // Create a new simpler BUILD_VECTOR sequence which other optimizations can
9640 // turn into a single shuffle instruction.
9644 bool isLE = TLI.isLittleEndian();
9645 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits();
9646 assert(ElemRatio > 1 && "Invalid element size ratio");
9647 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType):
9648 DAG.getConstant(0, SourceType);
9650 unsigned NewBVElems = ElemRatio * VT.getVectorNumElements();
9651 SmallVector<SDValue, 8> Ops(NewBVElems, Filler);
9653 // Populate the new build_vector
9654 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
9655 SDValue Cast = N->getOperand(i);
9656 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
9657 Cast.getOpcode() == ISD::ZERO_EXTEND ||
9658 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
9660 if (Cast.getOpcode() == ISD::UNDEF)
9661 In = DAG.getUNDEF(SourceType);
9663 In = Cast->getOperand(0);
9664 unsigned Index = isLE ? (i * ElemRatio) :
9665 (i * ElemRatio + (ElemRatio - 1));
9667 assert(Index < Ops.size() && "Invalid index");
9671 // The type of the new BUILD_VECTOR node.
9672 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems);
9673 assert(VecVT.getSizeInBits() == VT.getSizeInBits() &&
9674 "Invalid vector size");
9675 // Check if the new vector type is legal.
9676 if (!isTypeLegal(VecVT)) return SDValue();
9678 // Make the new BUILD_VECTOR.
9679 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], Ops.size());
9681 // The new BUILD_VECTOR node has the potential to be further optimized.
9682 AddToWorkList(BV.getNode());
9683 // Bitcast to the desired type.
9684 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
9687 SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) {
9688 EVT VT = N->getValueType(0);
9690 unsigned NumInScalars = N->getNumOperands();
9693 EVT SrcVT = MVT::Other;
9694 unsigned Opcode = ISD::DELETED_NODE;
9695 unsigned NumDefs = 0;
9697 for (unsigned i = 0; i != NumInScalars; ++i) {
9698 SDValue In = N->getOperand(i);
9699 unsigned Opc = In.getOpcode();
9701 if (Opc == ISD::UNDEF)
9704 // If all scalar values are floats and converted from integers.
9705 if (Opcode == ISD::DELETED_NODE &&
9706 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) {
9713 EVT InVT = In.getOperand(0).getValueType();
9715 // If all scalar values are typed differently, bail out. It's chosen to
9716 // simplify BUILD_VECTOR of integer types.
9717 if (SrcVT == MVT::Other)
9724 // If the vector has just one element defined, it's not worth to fold it into
9725 // a vectorized one.
9729 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP)
9730 && "Should only handle conversion from integer to float.");
9731 assert(SrcVT != MVT::Other && "Cannot determine source type!");
9733 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars);
9735 if (!TLI.isOperationLegalOrCustom(Opcode, NVT))
9738 SmallVector<SDValue, 8> Opnds;
9739 for (unsigned i = 0; i != NumInScalars; ++i) {
9740 SDValue In = N->getOperand(i);
9742 if (In.getOpcode() == ISD::UNDEF)
9743 Opnds.push_back(DAG.getUNDEF(SrcVT));
9745 Opnds.push_back(In.getOperand(0));
9747 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT,
9748 &Opnds[0], Opnds.size());
9749 AddToWorkList(BV.getNode());
9751 return DAG.getNode(Opcode, dl, VT, BV);
9754 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
9755 unsigned NumInScalars = N->getNumOperands();
9757 EVT VT = N->getValueType(0);
9759 // A vector built entirely of undefs is undef.
9760 if (ISD::allOperandsUndef(N))
9761 return DAG.getUNDEF(VT);
9763 SDValue V = reduceBuildVecExtToExtBuildVec(N);
9767 V = reduceBuildVecConvertToConvertBuildVec(N);
9771 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
9772 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
9773 // at most two distinct vectors, turn this into a shuffle node.
9775 // May only combine to shuffle after legalize if shuffle is legal.
9776 if (LegalOperations &&
9777 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT))
9780 SDValue VecIn1, VecIn2;
9781 for (unsigned i = 0; i != NumInScalars; ++i) {
9782 // Ignore undef inputs.
9783 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
9785 // If this input is something other than a EXTRACT_VECTOR_ELT with a
9786 // constant index, bail out.
9787 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
9788 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
9789 VecIn1 = VecIn2 = SDValue(0, 0);
9793 // We allow up to two distinct input vectors.
9794 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
9795 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
9798 if (VecIn1.getNode() == 0) {
9799 VecIn1 = ExtractedFromVec;
9800 } else if (VecIn2.getNode() == 0) {
9801 VecIn2 = ExtractedFromVec;
9804 VecIn1 = VecIn2 = SDValue(0, 0);
9809 // If everything is good, we can make a shuffle operation.
9810 if (VecIn1.getNode()) {
9811 SmallVector<int, 8> Mask;
9812 for (unsigned i = 0; i != NumInScalars; ++i) {
9813 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
9818 // If extracting from the first vector, just use the index directly.
9819 SDValue Extract = N->getOperand(i);
9820 SDValue ExtVal = Extract.getOperand(1);
9821 if (Extract.getOperand(0) == VecIn1) {
9822 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
9823 if (ExtIndex > VT.getVectorNumElements())
9826 Mask.push_back(ExtIndex);
9830 // Otherwise, use InIdx + VecSize
9831 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
9832 Mask.push_back(Idx+NumInScalars);
9835 // We can't generate a shuffle node with mismatched input and output types.
9836 // Attempt to transform a single input vector to the correct type.
9837 if ((VT != VecIn1.getValueType())) {
9838 // We don't support shuffeling between TWO values of different types.
9839 if (VecIn2.getNode() != 0)
9842 // We only support widening of vectors which are half the size of the
9843 // output registers. For example XMM->YMM widening on X86 with AVX.
9844 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits())
9847 // If the input vector type has a different base type to the output
9848 // vector type, bail out.
9849 if (VecIn1.getValueType().getVectorElementType() !=
9850 VT.getVectorElementType())
9853 // Widen the input vector by adding undef values.
9854 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9855 VecIn1, DAG.getUNDEF(VecIn1.getValueType()));
9858 // If VecIn2 is unused then change it to undef.
9859 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
9861 // Check that we were able to transform all incoming values to the same
9863 if (VecIn2.getValueType() != VecIn1.getValueType() ||
9864 VecIn1.getValueType() != VT)
9867 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes.
9868 if (!isTypeLegal(VT))
9871 // Return the new VECTOR_SHUFFLE node.
9875 return DAG.getVectorShuffle(VT, dl, Ops[0], Ops[1], &Mask[0]);
9881 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
9882 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
9883 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
9884 // inputs come from at most two distinct vectors, turn this into a shuffle
9887 // If we only have one input vector, we don't need to do any concatenation.
9888 if (N->getNumOperands() == 1)
9889 return N->getOperand(0);
9891 // Check if all of the operands are undefs.
9892 EVT VT = N->getValueType(0);
9893 if (ISD::allOperandsUndef(N))
9894 return DAG.getUNDEF(VT);
9896 // Optimize concat_vectors where one of the vectors is undef.
9897 if (N->getNumOperands() == 2 &&
9898 N->getOperand(1)->getOpcode() == ISD::UNDEF) {
9899 SDValue In = N->getOperand(0);
9900 assert(In.getValueType().isVector() && "Must concat vectors");
9902 // Transform: concat_vectors(scalar, undef) -> scalar_to_vector(sclr).
9903 if (In->getOpcode() == ISD::BITCAST &&
9904 !In->getOperand(0)->getValueType(0).isVector()) {
9905 SDValue Scalar = In->getOperand(0);
9906 EVT SclTy = Scalar->getValueType(0);
9908 if (!SclTy.isFloatingPoint() && !SclTy.isInteger())
9911 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SclTy,
9912 VT.getSizeInBits() / SclTy.getSizeInBits());
9913 if (!TLI.isTypeLegal(NVT) || !TLI.isTypeLegal(Scalar.getValueType()))
9916 SDLoc dl = SDLoc(N);
9917 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NVT, Scalar);
9918 return DAG.getNode(ISD::BITCAST, dl, VT, Res);
9922 // Type legalization of vectors and DAG canonicalization of SHUFFLE_VECTOR
9923 // nodes often generate nop CONCAT_VECTOR nodes.
9924 // Scan the CONCAT_VECTOR operands and look for a CONCAT operations that
9925 // place the incoming vectors at the exact same location.
9926 SDValue SingleSource = SDValue();
9927 unsigned PartNumElem = N->getOperand(0).getValueType().getVectorNumElements();
9929 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
9930 SDValue Op = N->getOperand(i);
9932 if (Op.getOpcode() == ISD::UNDEF)
9935 // Check if this is the identity extract:
9936 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR)
9939 // Find the single incoming vector for the extract_subvector.
9940 if (SingleSource.getNode()) {
9941 if (Op.getOperand(0) != SingleSource)
9944 SingleSource = Op.getOperand(0);
9946 // Check the source type is the same as the type of the result.
9947 // If not, this concat may extend the vector, so we can not
9948 // optimize it away.
9949 if (SingleSource.getValueType() != N->getValueType(0))
9953 unsigned IdentityIndex = i * PartNumElem;
9954 ConstantSDNode *CS = dyn_cast<ConstantSDNode>(Op.getOperand(1));
9955 // The extract index must be constant.
9959 // Check that we are reading from the identity index.
9960 if (CS->getZExtValue() != IdentityIndex)
9964 if (SingleSource.getNode())
9965 return SingleSource;
9970 SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
9971 EVT NVT = N->getValueType(0);
9972 SDValue V = N->getOperand(0);
9974 if (V->getOpcode() == ISD::CONCAT_VECTORS) {
9976 // (extract_subvec (concat V1, V2, ...), i)
9979 // Only operand 0 is checked as 'concat' assumes all inputs of the same
9981 if (V->getOperand(0).getValueType() != NVT)
9983 unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
9984 unsigned NumElems = NVT.getVectorNumElements();
9985 assert((Idx % NumElems) == 0 &&
9986 "IDX in concat is not a multiple of the result vector length.");
9987 return V->getOperand(Idx / NumElems);
9991 if (V->getOpcode() == ISD::BITCAST)
9992 V = V.getOperand(0);
9994 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
9996 // Handle only simple case where vector being inserted and vector
9997 // being extracted are of same type, and are half size of larger vectors.
9998 EVT BigVT = V->getOperand(0).getValueType();
9999 EVT SmallVT = V->getOperand(1).getValueType();
10000 if (!NVT.bitsEq(SmallVT) || NVT.getSizeInBits()*2 != BigVT.getSizeInBits())
10003 // Only handle cases where both indexes are constants with the same type.
10004 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
10005 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2));
10007 if (InsIdx && ExtIdx &&
10008 InsIdx->getValueType(0).getSizeInBits() <= 64 &&
10009 ExtIdx->getValueType(0).getSizeInBits() <= 64) {
10011 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx)
10013 // indices are equal or bit offsets are equal => V1
10014 // otherwise => (extract_subvec V1, ExtIdx)
10015 if (InsIdx->getZExtValue() * SmallVT.getScalarType().getSizeInBits() ==
10016 ExtIdx->getZExtValue() * NVT.getScalarType().getSizeInBits())
10017 return DAG.getNode(ISD::BITCAST, dl, NVT, V->getOperand(1));
10018 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT,
10019 DAG.getNode(ISD::BITCAST, dl,
10020 N->getOperand(0).getValueType(),
10021 V->getOperand(0)), N->getOperand(1));
10028 // Tries to turn a shuffle of two CONCAT_VECTORS into a single concat.
10029 static SDValue partitionShuffleOfConcats(SDNode *N, SelectionDAG &DAG) {
10030 EVT VT = N->getValueType(0);
10031 unsigned NumElts = VT.getVectorNumElements();
10033 SDValue N0 = N->getOperand(0);
10034 SDValue N1 = N->getOperand(1);
10035 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
10037 SmallVector<SDValue, 4> Ops;
10038 EVT ConcatVT = N0.getOperand(0).getValueType();
10039 unsigned NumElemsPerConcat = ConcatVT.getVectorNumElements();
10040 unsigned NumConcats = NumElts / NumElemsPerConcat;
10042 // Look at every vector that's inserted. We're looking for exact
10043 // subvector-sized copies from a concatenated vector
10044 for (unsigned I = 0; I != NumConcats; ++I) {
10045 // Make sure we're dealing with a copy.
10046 unsigned Begin = I * NumElemsPerConcat;
10047 bool AllUndef = true, NoUndef = true;
10048 for (unsigned J = Begin; J != Begin + NumElemsPerConcat; ++J) {
10049 if (SVN->getMaskElt(J) >= 0)
10056 if (SVN->getMaskElt(Begin) % NumElemsPerConcat != 0)
10059 for (unsigned J = 1; J != NumElemsPerConcat; ++J)
10060 if (SVN->getMaskElt(Begin + J - 1) + 1 != SVN->getMaskElt(Begin + J))
10063 unsigned FirstElt = SVN->getMaskElt(Begin) / NumElemsPerConcat;
10064 if (FirstElt < N0.getNumOperands())
10065 Ops.push_back(N0.getOperand(FirstElt));
10067 Ops.push_back(N1.getOperand(FirstElt - N0.getNumOperands()));
10069 } else if (AllUndef) {
10070 Ops.push_back(DAG.getUNDEF(N0.getOperand(0).getValueType()));
10071 } else { // Mixed with general masks and undefs, can't do optimization.
10076 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops.data(),
10080 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
10081 EVT VT = N->getValueType(0);
10082 unsigned NumElts = VT.getVectorNumElements();
10084 SDValue N0 = N->getOperand(0);
10085 SDValue N1 = N->getOperand(1);
10087 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG");
10089 // Canonicalize shuffle undef, undef -> undef
10090 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
10091 return DAG.getUNDEF(VT);
10093 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
10095 // Canonicalize shuffle v, v -> v, undef
10097 SmallVector<int, 8> NewMask;
10098 for (unsigned i = 0; i != NumElts; ++i) {
10099 int Idx = SVN->getMaskElt(i);
10100 if (Idx >= (int)NumElts) Idx -= NumElts;
10101 NewMask.push_back(Idx);
10103 return DAG.getVectorShuffle(VT, SDLoc(N), N0, DAG.getUNDEF(VT),
10107 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
10108 if (N0.getOpcode() == ISD::UNDEF) {
10109 SmallVector<int, 8> NewMask;
10110 for (unsigned i = 0; i != NumElts; ++i) {
10111 int Idx = SVN->getMaskElt(i);
10113 if (Idx >= (int)NumElts)
10116 Idx = -1; // remove reference to lhs
10118 NewMask.push_back(Idx);
10120 return DAG.getVectorShuffle(VT, SDLoc(N), N1, DAG.getUNDEF(VT),
10124 // Remove references to rhs if it is undef
10125 if (N1.getOpcode() == ISD::UNDEF) {
10126 bool Changed = false;
10127 SmallVector<int, 8> NewMask;
10128 for (unsigned i = 0; i != NumElts; ++i) {
10129 int Idx = SVN->getMaskElt(i);
10130 if (Idx >= (int)NumElts) {
10134 NewMask.push_back(Idx);
10137 return DAG.getVectorShuffle(VT, SDLoc(N), N0, N1, &NewMask[0]);
10140 // If it is a splat, check if the argument vector is another splat or a
10141 // build_vector with all scalar elements the same.
10142 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
10143 SDNode *V = N0.getNode();
10145 // If this is a bit convert that changes the element type of the vector but
10146 // not the number of vector elements, look through it. Be careful not to
10147 // look though conversions that change things like v4f32 to v2f64.
10148 if (V->getOpcode() == ISD::BITCAST) {
10149 SDValue ConvInput = V->getOperand(0);
10150 if (ConvInput.getValueType().isVector() &&
10151 ConvInput.getValueType().getVectorNumElements() == NumElts)
10152 V = ConvInput.getNode();
10155 if (V->getOpcode() == ISD::BUILD_VECTOR) {
10156 assert(V->getNumOperands() == NumElts &&
10157 "BUILD_VECTOR has wrong number of operands");
10159 bool AllSame = true;
10160 for (unsigned i = 0; i != NumElts; ++i) {
10161 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
10162 Base = V->getOperand(i);
10166 // Splat of <u, u, u, u>, return <u, u, u, u>
10167 if (!Base.getNode())
10169 for (unsigned i = 0; i != NumElts; ++i) {
10170 if (V->getOperand(i) != Base) {
10175 // Splat of <x, x, x, x>, return <x, x, x, x>
10181 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
10182 Level < AfterLegalizeVectorOps &&
10183 (N1.getOpcode() == ISD::UNDEF ||
10184 (N1.getOpcode() == ISD::CONCAT_VECTORS &&
10185 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()))) {
10186 SDValue V = partitionShuffleOfConcats(N, DAG);
10192 // If this shuffle node is simply a swizzle of another shuffle node,
10193 // and it reverses the swizzle of the previous shuffle then we can
10194 // optimize shuffle(shuffle(x, undef), undef) -> x.
10195 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
10196 N1.getOpcode() == ISD::UNDEF) {
10198 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
10200 // Shuffle nodes can only reverse shuffles with a single non-undef value.
10201 if (N0.getOperand(1).getOpcode() != ISD::UNDEF)
10204 // The incoming shuffle must be of the same type as the result of the
10205 // current shuffle.
10206 assert(OtherSV->getOperand(0).getValueType() == VT &&
10207 "Shuffle types don't match");
10209 for (unsigned i = 0; i != NumElts; ++i) {
10210 int Idx = SVN->getMaskElt(i);
10211 assert(Idx < (int)NumElts && "Index references undef operand");
10212 // Next, this index comes from the first value, which is the incoming
10213 // shuffle. Adopt the incoming index.
10215 Idx = OtherSV->getMaskElt(Idx);
10217 // The combined shuffle must map each index to itself.
10218 if (Idx >= 0 && (unsigned)Idx != i)
10222 return OtherSV->getOperand(0);
10228 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
10229 /// an AND to a vector_shuffle with the destination vector and a zero vector.
10230 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
10231 /// vector_shuffle V, Zero, <0, 4, 2, 4>
10232 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
10233 EVT VT = N->getValueType(0);
10235 SDValue LHS = N->getOperand(0);
10236 SDValue RHS = N->getOperand(1);
10237 if (N->getOpcode() == ISD::AND) {
10238 if (RHS.getOpcode() == ISD::BITCAST)
10239 RHS = RHS.getOperand(0);
10240 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
10241 SmallVector<int, 8> Indices;
10242 unsigned NumElts = RHS.getNumOperands();
10243 for (unsigned i = 0; i != NumElts; ++i) {
10244 SDValue Elt = RHS.getOperand(i);
10245 if (!isa<ConstantSDNode>(Elt))
10248 if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
10249 Indices.push_back(i);
10250 else if (cast<ConstantSDNode>(Elt)->isNullValue())
10251 Indices.push_back(NumElts);
10256 // Let's see if the target supports this vector_shuffle.
10257 EVT RVT = RHS.getValueType();
10258 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
10261 // Return the new VECTOR_SHUFFLE node.
10262 EVT EltVT = RVT.getVectorElementType();
10263 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
10264 DAG.getConstant(0, EltVT));
10265 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
10266 RVT, &ZeroOps[0], ZeroOps.size());
10267 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
10268 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
10269 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
10276 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
10277 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
10278 assert(N->getValueType(0).isVector() &&
10279 "SimplifyVBinOp only works on vectors!");
10281 SDValue LHS = N->getOperand(0);
10282 SDValue RHS = N->getOperand(1);
10283 SDValue Shuffle = XformToShuffleWithZero(N);
10284 if (Shuffle.getNode()) return Shuffle;
10286 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
10288 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
10289 RHS.getOpcode() == ISD::BUILD_VECTOR) {
10290 SmallVector<SDValue, 8> Ops;
10291 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
10292 SDValue LHSOp = LHS.getOperand(i);
10293 SDValue RHSOp = RHS.getOperand(i);
10294 // If these two elements can't be folded, bail out.
10295 if ((LHSOp.getOpcode() != ISD::UNDEF &&
10296 LHSOp.getOpcode() != ISD::Constant &&
10297 LHSOp.getOpcode() != ISD::ConstantFP) ||
10298 (RHSOp.getOpcode() != ISD::UNDEF &&
10299 RHSOp.getOpcode() != ISD::Constant &&
10300 RHSOp.getOpcode() != ISD::ConstantFP))
10303 // Can't fold divide by zero.
10304 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
10305 N->getOpcode() == ISD::FDIV) {
10306 if ((RHSOp.getOpcode() == ISD::Constant &&
10307 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
10308 (RHSOp.getOpcode() == ISD::ConstantFP &&
10309 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
10313 EVT VT = LHSOp.getValueType();
10314 EVT RVT = RHSOp.getValueType();
10316 // Integer BUILD_VECTOR operands may have types larger than the element
10317 // size (e.g., when the element type is not legal). Prior to type
10318 // legalization, the types may not match between the two BUILD_VECTORS.
10319 // Truncate one of the operands to make them match.
10320 if (RVT.getSizeInBits() > VT.getSizeInBits()) {
10321 RHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, RHSOp);
10323 LHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), RVT, LHSOp);
10327 SDValue FoldOp = DAG.getNode(N->getOpcode(), SDLoc(LHS), VT,
10329 if (FoldOp.getOpcode() != ISD::UNDEF &&
10330 FoldOp.getOpcode() != ISD::Constant &&
10331 FoldOp.getOpcode() != ISD::ConstantFP)
10333 Ops.push_back(FoldOp);
10334 AddToWorkList(FoldOp.getNode());
10337 if (Ops.size() == LHS.getNumOperands())
10338 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
10339 LHS.getValueType(), &Ops[0], Ops.size());
10345 /// SimplifyVUnaryOp - Visit a binary vector operation, like FABS/FNEG.
10346 SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) {
10347 assert(N->getValueType(0).isVector() &&
10348 "SimplifyVUnaryOp only works on vectors!");
10350 SDValue N0 = N->getOperand(0);
10352 if (N0.getOpcode() != ISD::BUILD_VECTOR)
10355 // Operand is a BUILD_VECTOR node, see if we can constant fold it.
10356 SmallVector<SDValue, 8> Ops;
10357 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
10358 SDValue Op = N0.getOperand(i);
10359 if (Op.getOpcode() != ISD::UNDEF &&
10360 Op.getOpcode() != ISD::ConstantFP)
10362 EVT EltVT = Op.getValueType();
10363 SDValue FoldOp = DAG.getNode(N->getOpcode(), SDLoc(N0), EltVT, Op);
10364 if (FoldOp.getOpcode() != ISD::UNDEF &&
10365 FoldOp.getOpcode() != ISD::ConstantFP)
10367 Ops.push_back(FoldOp);
10368 AddToWorkList(FoldOp.getNode());
10371 if (Ops.size() != N0.getNumOperands())
10374 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
10375 N0.getValueType(), &Ops[0], Ops.size());
10378 SDValue DAGCombiner::SimplifySelect(SDLoc DL, SDValue N0,
10379 SDValue N1, SDValue N2){
10380 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
10382 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
10383 cast<CondCodeSDNode>(N0.getOperand(2))->get());
10385 // If we got a simplified select_cc node back from SimplifySelectCC, then
10386 // break it down into a new SETCC node, and a new SELECT node, and then return
10387 // the SELECT node, since we were called with a SELECT node.
10388 if (SCC.getNode()) {
10389 // Check to see if we got a select_cc back (to turn into setcc/select).
10390 // Otherwise, just return whatever node we got back, like fabs.
10391 if (SCC.getOpcode() == ISD::SELECT_CC) {
10392 SDValue SETCC = DAG.getNode(ISD::SETCC, SDLoc(N0),
10394 SCC.getOperand(0), SCC.getOperand(1),
10395 SCC.getOperand(4));
10396 AddToWorkList(SETCC.getNode());
10397 return DAG.getSelect(SDLoc(SCC), SCC.getValueType(),
10398 SCC.getOperand(2), SCC.getOperand(3), SETCC);
10406 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
10407 /// are the two values being selected between, see if we can simplify the
10408 /// select. Callers of this should assume that TheSelect is deleted if this
10409 /// returns true. As such, they should return the appropriate thing (e.g. the
10410 /// node) back to the top-level of the DAG combiner loop to avoid it being
10412 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
10415 // Cannot simplify select with vector condition
10416 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
10418 // If this is a select from two identical things, try to pull the operation
10419 // through the select.
10420 if (LHS.getOpcode() != RHS.getOpcode() ||
10421 !LHS.hasOneUse() || !RHS.hasOneUse())
10424 // If this is a load and the token chain is identical, replace the select
10425 // of two loads with a load through a select of the address to load from.
10426 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
10427 // constants have been dropped into the constant pool.
10428 if (LHS.getOpcode() == ISD::LOAD) {
10429 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
10430 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
10432 // Token chains must be identical.
10433 if (LHS.getOperand(0) != RHS.getOperand(0) ||
10434 // Do not let this transformation reduce the number of volatile loads.
10435 LLD->isVolatile() || RLD->isVolatile() ||
10436 // If this is an EXTLOAD, the VT's must match.
10437 LLD->getMemoryVT() != RLD->getMemoryVT() ||
10438 // If this is an EXTLOAD, the kind of extension must match.
10439 (LLD->getExtensionType() != RLD->getExtensionType() &&
10440 // The only exception is if one of the extensions is anyext.
10441 LLD->getExtensionType() != ISD::EXTLOAD &&
10442 RLD->getExtensionType() != ISD::EXTLOAD) ||
10443 // FIXME: this discards src value information. This is
10444 // over-conservative. It would be beneficial to be able to remember
10445 // both potential memory locations. Since we are discarding
10446 // src value info, don't do the transformation if the memory
10447 // locations are not in the default address space.
10448 LLD->getPointerInfo().getAddrSpace() != 0 ||
10449 RLD->getPointerInfo().getAddrSpace() != 0 ||
10450 !TLI.isOperationLegalOrCustom(TheSelect->getOpcode(),
10451 LLD->getBasePtr().getValueType()))
10454 // Check that the select condition doesn't reach either load. If so,
10455 // folding this will induce a cycle into the DAG. If not, this is safe to
10456 // xform, so create a select of the addresses.
10458 if (TheSelect->getOpcode() == ISD::SELECT) {
10459 SDNode *CondNode = TheSelect->getOperand(0).getNode();
10460 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
10461 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
10463 // The loads must not depend on one another.
10464 if (LLD->isPredecessorOf(RLD) ||
10465 RLD->isPredecessorOf(LLD))
10467 Addr = DAG.getSelect(SDLoc(TheSelect),
10468 LLD->getBasePtr().getValueType(),
10469 TheSelect->getOperand(0), LLD->getBasePtr(),
10470 RLD->getBasePtr());
10471 } else { // Otherwise SELECT_CC
10472 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
10473 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
10475 if ((LLD->hasAnyUseOfValue(1) &&
10476 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
10477 (RLD->hasAnyUseOfValue(1) &&
10478 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS))))
10481 Addr = DAG.getNode(ISD::SELECT_CC, SDLoc(TheSelect),
10482 LLD->getBasePtr().getValueType(),
10483 TheSelect->getOperand(0),
10484 TheSelect->getOperand(1),
10485 LLD->getBasePtr(), RLD->getBasePtr(),
10486 TheSelect->getOperand(4));
10490 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
10491 Load = DAG.getLoad(TheSelect->getValueType(0),
10493 // FIXME: Discards pointer and TBAA info.
10494 LLD->getChain(), Addr, MachinePointerInfo(),
10495 LLD->isVolatile(), LLD->isNonTemporal(),
10496 LLD->isInvariant(), LLD->getAlignment());
10498 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
10499 RLD->getExtensionType() : LLD->getExtensionType(),
10501 TheSelect->getValueType(0),
10502 // FIXME: Discards pointer and TBAA info.
10503 LLD->getChain(), Addr, MachinePointerInfo(),
10504 LLD->getMemoryVT(), LLD->isVolatile(),
10505 LLD->isNonTemporal(), LLD->getAlignment());
10508 // Users of the select now use the result of the load.
10509 CombineTo(TheSelect, Load);
10511 // Users of the old loads now use the new load's chain. We know the
10512 // old-load value is dead now.
10513 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
10514 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
10521 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
10522 /// where 'cond' is the comparison specified by CC.
10523 SDValue DAGCombiner::SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1,
10524 SDValue N2, SDValue N3,
10525 ISD::CondCode CC, bool NotExtCompare) {
10526 // (x ? y : y) -> y.
10527 if (N2 == N3) return N2;
10529 EVT VT = N2.getValueType();
10530 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
10531 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
10532 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
10534 // Determine if the condition we're dealing with is constant
10535 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
10536 N0, N1, CC, DL, false);
10537 if (SCC.getNode()) AddToWorkList(SCC.getNode());
10538 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
10540 // fold select_cc true, x, y -> x
10541 if (SCCC && !SCCC->isNullValue())
10543 // fold select_cc false, x, y -> y
10544 if (SCCC && SCCC->isNullValue())
10547 // Check to see if we can simplify the select into an fabs node
10548 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
10549 // Allow either -0.0 or 0.0
10550 if (CFP->getValueAPF().isZero()) {
10551 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
10552 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
10553 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
10554 N2 == N3.getOperand(0))
10555 return DAG.getNode(ISD::FABS, DL, VT, N0);
10557 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
10558 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
10559 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
10560 N2.getOperand(0) == N3)
10561 return DAG.getNode(ISD::FABS, DL, VT, N3);
10565 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
10566 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
10567 // in it. This is a win when the constant is not otherwise available because
10568 // it replaces two constant pool loads with one. We only do this if the FP
10569 // type is known to be legal, because if it isn't, then we are before legalize
10570 // types an we want the other legalization to happen first (e.g. to avoid
10571 // messing with soft float) and if the ConstantFP is not legal, because if
10572 // it is legal, we may not need to store the FP constant in a constant pool.
10573 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
10574 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
10575 if (TLI.isTypeLegal(N2.getValueType()) &&
10576 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
10577 TargetLowering::Legal) &&
10578 // If both constants have multiple uses, then we won't need to do an
10579 // extra load, they are likely around in registers for other users.
10580 (TV->hasOneUse() || FV->hasOneUse())) {
10581 Constant *Elts[] = {
10582 const_cast<ConstantFP*>(FV->getConstantFPValue()),
10583 const_cast<ConstantFP*>(TV->getConstantFPValue())
10585 Type *FPTy = Elts[0]->getType();
10586 const DataLayout &TD = *TLI.getDataLayout();
10588 // Create a ConstantArray of the two constants.
10589 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
10590 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
10591 TD.getPrefTypeAlignment(FPTy));
10592 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
10594 // Get the offsets to the 0 and 1 element of the array so that we can
10595 // select between them.
10596 SDValue Zero = DAG.getIntPtrConstant(0);
10597 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
10598 SDValue One = DAG.getIntPtrConstant(EltSize);
10600 SDValue Cond = DAG.getSetCC(DL,
10601 getSetCCResultType(N0.getValueType()),
10603 AddToWorkList(Cond.getNode());
10604 SDValue CstOffset = DAG.getSelect(DL, Zero.getValueType(),
10606 AddToWorkList(CstOffset.getNode());
10607 CPIdx = DAG.getNode(ISD::ADD, DL, CPIdx.getValueType(), CPIdx,
10609 AddToWorkList(CPIdx.getNode());
10610 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
10611 MachinePointerInfo::getConstantPool(), false,
10612 false, false, Alignment);
10617 // Check to see if we can perform the "gzip trick", transforming
10618 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
10619 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
10620 (N1C->isNullValue() || // (a < 0) ? b : 0
10621 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
10622 EVT XType = N0.getValueType();
10623 EVT AType = N2.getValueType();
10624 if (XType.bitsGE(AType)) {
10625 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
10626 // single-bit constant.
10627 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
10628 unsigned ShCtV = N2C->getAPIntValue().logBase2();
10629 ShCtV = XType.getSizeInBits()-ShCtV-1;
10630 SDValue ShCt = DAG.getConstant(ShCtV,
10631 getShiftAmountTy(N0.getValueType()));
10632 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0),
10634 AddToWorkList(Shift.getNode());
10636 if (XType.bitsGT(AType)) {
10637 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
10638 AddToWorkList(Shift.getNode());
10641 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
10644 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0),
10646 DAG.getConstant(XType.getSizeInBits()-1,
10647 getShiftAmountTy(N0.getValueType())));
10648 AddToWorkList(Shift.getNode());
10650 if (XType.bitsGT(AType)) {
10651 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
10652 AddToWorkList(Shift.getNode());
10655 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
10659 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
10660 // where y is has a single bit set.
10661 // A plaintext description would be, we can turn the SELECT_CC into an AND
10662 // when the condition can be materialized as an all-ones register. Any
10663 // single bit-test can be materialized as an all-ones register with
10664 // shift-left and shift-right-arith.
10665 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
10666 N0->getValueType(0) == VT &&
10667 N1C && N1C->isNullValue() &&
10668 N2C && N2C->isNullValue()) {
10669 SDValue AndLHS = N0->getOperand(0);
10670 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
10671 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
10672 // Shift the tested bit over the sign bit.
10673 APInt AndMask = ConstAndRHS->getAPIntValue();
10675 DAG.getConstant(AndMask.countLeadingZeros(),
10676 getShiftAmountTy(AndLHS.getValueType()));
10677 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt);
10679 // Now arithmetic right shift it all the way over, so the result is either
10680 // all-ones, or zero.
10682 DAG.getConstant(AndMask.getBitWidth()-1,
10683 getShiftAmountTy(Shl.getValueType()));
10684 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt);
10686 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
10690 // fold select C, 16, 0 -> shl C, 4
10691 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
10692 TLI.getBooleanContents(N0.getValueType().isVector()) ==
10693 TargetLowering::ZeroOrOneBooleanContent) {
10695 // If the caller doesn't want us to simplify this into a zext of a compare,
10697 if (NotExtCompare && N2C->getAPIntValue() == 1)
10700 // Get a SetCC of the condition
10701 // NOTE: Don't create a SETCC if it's not legal on this target.
10702 if (!LegalOperations ||
10703 TLI.isOperationLegal(ISD::SETCC,
10704 LegalTypes ? getSetCCResultType(N0.getValueType()) : MVT::i1)) {
10706 // cast from setcc result type to select result type
10708 SCC = DAG.getSetCC(DL, getSetCCResultType(N0.getValueType()),
10710 if (N2.getValueType().bitsLT(SCC.getValueType()))
10711 Temp = DAG.getZeroExtendInReg(SCC, SDLoc(N2),
10712 N2.getValueType());
10714 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
10715 N2.getValueType(), SCC);
10717 SCC = DAG.getSetCC(SDLoc(N0), MVT::i1, N0, N1, CC);
10718 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
10719 N2.getValueType(), SCC);
10722 AddToWorkList(SCC.getNode());
10723 AddToWorkList(Temp.getNode());
10725 if (N2C->getAPIntValue() == 1)
10728 // shl setcc result by log2 n2c
10729 return DAG.getNode(
10730 ISD::SHL, DL, N2.getValueType(), Temp,
10731 DAG.getConstant(N2C->getAPIntValue().logBase2(),
10732 getShiftAmountTy(Temp.getValueType())));
10736 // Check to see if this is the equivalent of setcc
10737 // FIXME: Turn all of these into setcc if setcc if setcc is legal
10738 // otherwise, go ahead with the folds.
10739 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
10740 EVT XType = N0.getValueType();
10741 if (!LegalOperations ||
10742 TLI.isOperationLegal(ISD::SETCC, getSetCCResultType(XType))) {
10743 SDValue Res = DAG.getSetCC(DL, getSetCCResultType(XType), N0, N1, CC);
10744 if (Res.getValueType() != VT)
10745 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
10749 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
10750 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
10751 (!LegalOperations ||
10752 TLI.isOperationLegal(ISD::CTLZ, XType))) {
10753 SDValue Ctlz = DAG.getNode(ISD::CTLZ, SDLoc(N0), XType, N0);
10754 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
10755 DAG.getConstant(Log2_32(XType.getSizeInBits()),
10756 getShiftAmountTy(Ctlz.getValueType())));
10758 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
10759 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
10760 SDValue NegN0 = DAG.getNode(ISD::SUB, SDLoc(N0),
10761 XType, DAG.getConstant(0, XType), N0);
10762 SDValue NotN0 = DAG.getNOT(SDLoc(N0), N0, XType);
10763 return DAG.getNode(ISD::SRL, DL, XType,
10764 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
10765 DAG.getConstant(XType.getSizeInBits()-1,
10766 getShiftAmountTy(XType)));
10768 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
10769 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
10770 SDValue Sign = DAG.getNode(ISD::SRL, SDLoc(N0), XType, N0,
10771 DAG.getConstant(XType.getSizeInBits()-1,
10772 getShiftAmountTy(N0.getValueType())));
10773 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
10777 // Check to see if this is an integer abs.
10778 // select_cc setg[te] X, 0, X, -X ->
10779 // select_cc setgt X, -1, X, -X ->
10780 // select_cc setl[te] X, 0, -X, X ->
10781 // select_cc setlt X, 1, -X, X ->
10782 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
10784 ConstantSDNode *SubC = NULL;
10785 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
10786 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
10787 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
10788 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
10789 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
10790 (N1C->isOne() && CC == ISD::SETLT)) &&
10791 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
10792 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
10794 EVT XType = N0.getValueType();
10795 if (SubC && SubC->isNullValue() && XType.isInteger()) {
10796 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0), XType,
10798 DAG.getConstant(XType.getSizeInBits()-1,
10799 getShiftAmountTy(N0.getValueType())));
10800 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0),
10802 AddToWorkList(Shift.getNode());
10803 AddToWorkList(Add.getNode());
10804 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
10811 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
10812 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
10813 SDValue N1, ISD::CondCode Cond,
10814 SDLoc DL, bool foldBooleans) {
10815 TargetLowering::DAGCombinerInfo
10816 DagCombineInfo(DAG, Level, false, this);
10817 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
10820 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
10821 /// return a DAG expression to select that will generate the same value by
10822 /// multiplying by a magic number. See:
10823 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
10824 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
10825 std::vector<SDNode*> Built;
10826 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built);
10828 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
10830 AddToWorkList(*ii);
10834 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
10835 /// return a DAG expression to select that will generate the same value by
10836 /// multiplying by a magic number. See:
10837 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
10838 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
10839 std::vector<SDNode*> Built;
10840 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built);
10842 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
10844 AddToWorkList(*ii);
10848 /// FindBaseOffset - Return true if base is a frame index, which is known not
10849 // to alias with anything but itself. Provides base object and offset as
10851 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
10852 const GlobalValue *&GV, const void *&CV) {
10853 // Assume it is a primitive operation.
10854 Base = Ptr; Offset = 0; GV = 0; CV = 0;
10856 // If it's an adding a simple constant then integrate the offset.
10857 if (Base.getOpcode() == ISD::ADD) {
10858 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
10859 Base = Base.getOperand(0);
10860 Offset += C->getZExtValue();
10864 // Return the underlying GlobalValue, and update the Offset. Return false
10865 // for GlobalAddressSDNode since the same GlobalAddress may be represented
10866 // by multiple nodes with different offsets.
10867 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
10868 GV = G->getGlobal();
10869 Offset += G->getOffset();
10873 // Return the underlying Constant value, and update the Offset. Return false
10874 // for ConstantSDNodes since the same constant pool entry may be represented
10875 // by multiple nodes with different offsets.
10876 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
10877 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal()
10878 : (const void *)C->getConstVal();
10879 Offset += C->getOffset();
10882 // If it's any of the following then it can't alias with anything but itself.
10883 return isa<FrameIndexSDNode>(Base);
10886 /// isAlias - Return true if there is any possibility that the two addresses
10888 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, bool IsVolatile1,
10889 const Value *SrcValue1, int SrcValueOffset1,
10890 unsigned SrcValueAlign1,
10891 const MDNode *TBAAInfo1,
10892 SDValue Ptr2, int64_t Size2, bool IsVolatile2,
10893 const Value *SrcValue2, int SrcValueOffset2,
10894 unsigned SrcValueAlign2,
10895 const MDNode *TBAAInfo2) const {
10896 // If they are the same then they must be aliases.
10897 if (Ptr1 == Ptr2) return true;
10899 // If they are both volatile then they cannot be reordered.
10900 if (IsVolatile1 && IsVolatile2) return true;
10902 // Gather base node and offset information.
10903 SDValue Base1, Base2;
10904 int64_t Offset1, Offset2;
10905 const GlobalValue *GV1, *GV2;
10906 const void *CV1, *CV2;
10907 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
10908 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
10910 // If they have a same base address then check to see if they overlap.
10911 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
10912 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
10914 // It is possible for different frame indices to alias each other, mostly
10915 // when tail call optimization reuses return address slots for arguments.
10916 // To catch this case, look up the actual index of frame indices to compute
10917 // the real alias relationship.
10918 if (isFrameIndex1 && isFrameIndex2) {
10919 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10920 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
10921 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
10922 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
10925 // Otherwise, if we know what the bases are, and they aren't identical, then
10926 // we know they cannot alias.
10927 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
10930 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
10931 // compared to the size and offset of the access, we may be able to prove they
10932 // do not alias. This check is conservative for now to catch cases created by
10933 // splitting vector types.
10934 if ((SrcValueAlign1 == SrcValueAlign2) &&
10935 (SrcValueOffset1 != SrcValueOffset2) &&
10936 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
10937 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
10938 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
10940 // There is no overlap between these relatively aligned accesses of similar
10941 // size, return no alias.
10942 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
10946 bool UseAA = CombinerGlobalAA.getNumOccurrences() > 0 ? CombinerGlobalAA :
10947 TLI.getTargetMachine().getSubtarget<TargetSubtargetInfo>().useAA();
10948 if (UseAA && SrcValue1 && SrcValue2) {
10949 // Use alias analysis information.
10950 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
10951 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
10952 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
10953 AliasAnalysis::AliasResult AAResult =
10954 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1),
10955 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2));
10956 if (AAResult == AliasAnalysis::NoAlias)
10960 // Otherwise we have to assume they alias.
10964 bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) {
10965 SDValue Ptr0, Ptr1;
10966 int64_t Size0, Size1;
10967 bool IsVolatile0, IsVolatile1;
10968 const Value *SrcValue0, *SrcValue1;
10969 int SrcValueOffset0, SrcValueOffset1;
10970 unsigned SrcValueAlign0, SrcValueAlign1;
10971 const MDNode *SrcTBAAInfo0, *SrcTBAAInfo1;
10972 FindAliasInfo(Op0, Ptr0, Size0, IsVolatile0, SrcValue0, SrcValueOffset0,
10973 SrcValueAlign0, SrcTBAAInfo0);
10974 FindAliasInfo(Op1, Ptr1, Size1, IsVolatile1, SrcValue1, SrcValueOffset1,
10975 SrcValueAlign1, SrcTBAAInfo1);
10976 return isAlias(Ptr0, Size0, IsVolatile0, SrcValue0, SrcValueOffset0,
10977 SrcValueAlign0, SrcTBAAInfo0,
10978 Ptr1, Size1, IsVolatile1, SrcValue1, SrcValueOffset1,
10979 SrcValueAlign1, SrcTBAAInfo1);
10982 /// FindAliasInfo - Extracts the relevant alias information from the memory
10983 /// node. Returns true if the operand was a nonvolatile load.
10984 bool DAGCombiner::FindAliasInfo(SDNode *N,
10985 SDValue &Ptr, int64_t &Size, bool &IsVolatile,
10986 const Value *&SrcValue,
10987 int &SrcValueOffset,
10988 unsigned &SrcValueAlign,
10989 const MDNode *&TBAAInfo) const {
10990 LSBaseSDNode *LS = cast<LSBaseSDNode>(N);
10992 Ptr = LS->getBasePtr();
10993 Size = LS->getMemoryVT().getSizeInBits() >> 3;
10994 IsVolatile = LS->isVolatile();
10995 SrcValue = LS->getSrcValue();
10996 SrcValueOffset = LS->getSrcValueOffset();
10997 SrcValueAlign = LS->getOriginalAlignment();
10998 TBAAInfo = LS->getTBAAInfo();
10999 return isa<LoadSDNode>(LS) && !IsVolatile;
11002 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
11003 /// looking for aliasing nodes and adding them to the Aliases vector.
11004 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
11005 SmallVectorImpl<SDValue> &Aliases) {
11006 SmallVector<SDValue, 8> Chains; // List of chains to visit.
11007 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
11009 // Get alias information for node.
11013 const Value *SrcValue;
11014 int SrcValueOffset;
11015 unsigned SrcValueAlign;
11016 const MDNode *SrcTBAAInfo;
11017 bool IsLoad = FindAliasInfo(N, Ptr, Size, IsVolatile, SrcValue,
11018 SrcValueOffset, SrcValueAlign, SrcTBAAInfo);
11021 Chains.push_back(OriginalChain);
11022 unsigned Depth = 0;
11024 // Look at each chain and determine if it is an alias. If so, add it to the
11025 // aliases list. If not, then continue up the chain looking for the next
11027 while (!Chains.empty()) {
11028 SDValue Chain = Chains.back();
11031 // For TokenFactor nodes, look at each operand and only continue up the
11032 // chain until we find two aliases. If we've seen two aliases, assume we'll
11033 // find more and revert to original chain since the xform is unlikely to be
11036 // FIXME: The depth check could be made to return the last non-aliasing
11037 // chain we found before we hit a tokenfactor rather than the original
11039 if (Depth > 6 || Aliases.size() == 2) {
11041 Aliases.push_back(OriginalChain);
11045 // Don't bother if we've been before.
11046 if (!Visited.insert(Chain.getNode()))
11049 switch (Chain.getOpcode()) {
11050 case ISD::EntryToken:
11051 // Entry token is ideal chain operand, but handled in FindBetterChain.
11056 // Get alias information for Chain.
11060 const Value *OpSrcValue;
11061 int OpSrcValueOffset;
11062 unsigned OpSrcValueAlign;
11063 const MDNode *OpSrcTBAAInfo;
11064 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
11065 OpIsVolatile, OpSrcValue, OpSrcValueOffset,
11069 // If chain is alias then stop here.
11070 if (!(IsLoad && IsOpLoad) &&
11071 isAlias(Ptr, Size, IsVolatile, SrcValue, SrcValueOffset,
11072 SrcValueAlign, SrcTBAAInfo,
11073 OpPtr, OpSize, OpIsVolatile, OpSrcValue, OpSrcValueOffset,
11074 OpSrcValueAlign, OpSrcTBAAInfo)) {
11075 Aliases.push_back(Chain);
11077 // Look further up the chain.
11078 Chains.push_back(Chain.getOperand(0));
11084 case ISD::TokenFactor:
11085 // We have to check each of the operands of the token factor for "small"
11086 // token factors, so we queue them up. Adding the operands to the queue
11087 // (stack) in reverse order maintains the original order and increases the
11088 // likelihood that getNode will find a matching token factor (CSE.)
11089 if (Chain.getNumOperands() > 16) {
11090 Aliases.push_back(Chain);
11093 for (unsigned n = Chain.getNumOperands(); n;)
11094 Chains.push_back(Chain.getOperand(--n));
11099 // For all other instructions we will just have to take what we can get.
11100 Aliases.push_back(Chain);
11106 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
11107 /// for a better chain (aliasing node.)
11108 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
11109 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
11111 // Accumulate all the aliases to this node.
11112 GatherAllAliases(N, OldChain, Aliases);
11114 // If no operands then chain to entry token.
11115 if (Aliases.size() == 0)
11116 return DAG.getEntryNode();
11118 // If a single operand then chain to it. We don't need to revisit it.
11119 if (Aliases.size() == 1)
11122 // Construct a custom tailored token factor.
11123 return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other,
11124 &Aliases[0], Aliases.size());
11127 // SelectionDAG::Combine - This is the entry point for the file.
11129 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
11130 CodeGenOpt::Level OptLevel) {
11131 /// run - This is the main entry point to this class.
11133 DAGCombiner(*this, AA, OptLevel).Run(Level);