1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Analysis/AliasAnalysis.h"
27 #include "llvm/Target/TargetData.h"
28 #include "llvm/Target/TargetFrameInfo.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/ADT/SmallPtrSet.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
42 STATISTIC(NodesCombined , "Number of dag nodes combined");
43 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
44 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
45 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
49 CombinerAA("combiner-alias-analysis", cl::Hidden,
50 cl::desc("Turn on alias analysis during testing"));
53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
54 cl::desc("Include global information in alias analysis"));
56 //------------------------------ DAGCombiner ---------------------------------//
60 const TargetLowering &TLI;
62 CodeGenOpt::Level OptLevel;
66 // Worklist of all of the nodes that need to be simplified.
67 std::vector<SDNode*> WorkList;
69 // AA - Used for DAG load/store alias analysis.
72 /// AddUsersToWorkList - When an instruction is simplified, add all users of
73 /// the instruction to the work lists because they might get more simplified
76 void AddUsersToWorkList(SDNode *N) {
77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
82 /// visit - call the node-specific routine that knows how to fold each
83 /// particular type of node.
84 SDValue visit(SDNode *N);
87 /// AddToWorkList - Add to the work list making sure it's instance is at the
88 /// the back (next to be processed.)
89 void AddToWorkList(SDNode *N) {
90 removeFromWorkList(N);
91 WorkList.push_back(N);
94 /// removeFromWorkList - remove all instances of N from the worklist.
96 void removeFromWorkList(SDNode *N) {
97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
105 return CombineTo(N, &Res, 1, AddTo);
108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
110 SDValue To[] = { Res0, Res1 };
111 return CombineTo(N, To, 2, AddTo);
114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
118 /// SimplifyDemandedBits - Check the specified integer node value to see if
119 /// it can be simplified or if things it uses can be simplified by bit
120 /// propagation. If so, return true.
121 bool SimplifyDemandedBits(SDValue Op) {
122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
123 APInt Demanded = APInt::getAllOnesValue(BitWidth);
124 return SimplifyDemandedBits(Op, Demanded);
127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
129 bool CombineToPreIndexedLoadStore(SDNode *N);
130 bool CombineToPostIndexedLoadStore(SDNode *N);
133 /// combine - call the node-specific routine that knows how to fold each
134 /// particular type of node. If that doesn't do anything, try the
135 /// target-specific DAG combines.
136 SDValue combine(SDNode *N);
138 // Visitation implementation - Implement dag node combining for different
139 // node types. The semantics are as follows:
141 // SDValue.getNode() == 0 - No change was made
142 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
143 // otherwise - N should be replaced by the returned Operand.
145 SDValue visitTokenFactor(SDNode *N);
146 SDValue visitMERGE_VALUES(SDNode *N);
147 SDValue visitADD(SDNode *N);
148 SDValue visitSUB(SDNode *N);
149 SDValue visitADDC(SDNode *N);
150 SDValue visitADDE(SDNode *N);
151 SDValue visitMUL(SDNode *N);
152 SDValue visitSDIV(SDNode *N);
153 SDValue visitUDIV(SDNode *N);
154 SDValue visitSREM(SDNode *N);
155 SDValue visitUREM(SDNode *N);
156 SDValue visitMULHU(SDNode *N);
157 SDValue visitMULHS(SDNode *N);
158 SDValue visitSMUL_LOHI(SDNode *N);
159 SDValue visitUMUL_LOHI(SDNode *N);
160 SDValue visitSDIVREM(SDNode *N);
161 SDValue visitUDIVREM(SDNode *N);
162 SDValue visitAND(SDNode *N);
163 SDValue visitOR(SDNode *N);
164 SDValue visitXOR(SDNode *N);
165 SDValue SimplifyVBinOp(SDNode *N);
166 SDValue visitSHL(SDNode *N);
167 SDValue visitSRA(SDNode *N);
168 SDValue visitSRL(SDNode *N);
169 SDValue visitCTLZ(SDNode *N);
170 SDValue visitCTTZ(SDNode *N);
171 SDValue visitCTPOP(SDNode *N);
172 SDValue visitSELECT(SDNode *N);
173 SDValue visitSELECT_CC(SDNode *N);
174 SDValue visitSETCC(SDNode *N);
175 SDValue visitSIGN_EXTEND(SDNode *N);
176 SDValue visitZERO_EXTEND(SDNode *N);
177 SDValue visitANY_EXTEND(SDNode *N);
178 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
179 SDValue visitTRUNCATE(SDNode *N);
180 SDValue visitBIT_CONVERT(SDNode *N);
181 SDValue visitBUILD_PAIR(SDNode *N);
182 SDValue visitFADD(SDNode *N);
183 SDValue visitFSUB(SDNode *N);
184 SDValue visitFMUL(SDNode *N);
185 SDValue visitFDIV(SDNode *N);
186 SDValue visitFREM(SDNode *N);
187 SDValue visitFCOPYSIGN(SDNode *N);
188 SDValue visitSINT_TO_FP(SDNode *N);
189 SDValue visitUINT_TO_FP(SDNode *N);
190 SDValue visitFP_TO_SINT(SDNode *N);
191 SDValue visitFP_TO_UINT(SDNode *N);
192 SDValue visitFP_ROUND(SDNode *N);
193 SDValue visitFP_ROUND_INREG(SDNode *N);
194 SDValue visitFP_EXTEND(SDNode *N);
195 SDValue visitFNEG(SDNode *N);
196 SDValue visitFABS(SDNode *N);
197 SDValue visitBRCOND(SDNode *N);
198 SDValue visitBR_CC(SDNode *N);
199 SDValue visitLOAD(SDNode *N);
200 SDValue visitSTORE(SDNode *N);
201 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
202 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
203 SDValue visitBUILD_VECTOR(SDNode *N);
204 SDValue visitCONCAT_VECTORS(SDNode *N);
205 SDValue visitVECTOR_SHUFFLE(SDNode *N);
207 SDValue XformToShuffleWithZero(SDNode *N);
208 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
210 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
212 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
213 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
214 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
215 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
216 SDValue N3, ISD::CondCode CC,
217 bool NotExtCompare = false);
218 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
219 DebugLoc DL, bool foldBooleans = true);
220 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
222 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
223 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT);
224 SDValue BuildSDIV(SDNode *N);
225 SDValue BuildUDIV(SDNode *N);
226 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
227 SDValue ReduceLoadWidth(SDNode *N);
228 SDValue ReduceLoadOpStoreWidth(SDNode *N);
230 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
232 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
233 /// looking for aliasing nodes and adding them to the Aliases vector.
234 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
235 SmallVector<SDValue, 8> &Aliases);
237 /// isAlias - Return true if there is any possibility that the two addresses
239 bool isAlias(SDValue Ptr1, int64_t Size1,
240 const Value *SrcValue1, int SrcValueOffset1,
241 unsigned SrcValueAlign1,
242 SDValue Ptr2, int64_t Size2,
243 const Value *SrcValue2, int SrcValueOffset2,
244 unsigned SrcValueAlign2) const;
246 /// FindAliasInfo - Extracts the relevant alias information from the memory
247 /// node. Returns true if the operand was a load.
248 bool FindAliasInfo(SDNode *N,
249 SDValue &Ptr, int64_t &Size,
250 const Value *&SrcValue, int &SrcValueOffset,
251 unsigned &SrcValueAlignment) const;
253 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
254 /// looking for a better chain (aliasing node.)
255 SDValue FindBetterChain(SDNode *N, SDValue Chain);
257 /// getShiftAmountTy - Returns a type large enough to hold any valid
258 /// shift amount - before type legalization these can be huge.
259 EVT getShiftAmountTy() {
260 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy();
264 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
266 TLI(D.getTargetLoweringInfo()),
269 LegalOperations(false),
273 /// Run - runs the dag combiner on all nodes in the work list
274 void Run(CombineLevel AtLevel);
280 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
281 /// nodes from the worklist.
282 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
285 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
287 virtual void NodeDeleted(SDNode *N, SDNode *E) {
288 DC.removeFromWorkList(N);
291 virtual void NodeUpdated(SDNode *N) {
297 //===----------------------------------------------------------------------===//
298 // TargetLowering::DAGCombinerInfo implementation
299 //===----------------------------------------------------------------------===//
301 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
302 ((DAGCombiner*)DC)->AddToWorkList(N);
305 SDValue TargetLowering::DAGCombinerInfo::
306 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
307 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
310 SDValue TargetLowering::DAGCombinerInfo::
311 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
312 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
316 SDValue TargetLowering::DAGCombinerInfo::
317 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
318 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
321 void TargetLowering::DAGCombinerInfo::
322 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
323 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
326 //===----------------------------------------------------------------------===//
328 //===----------------------------------------------------------------------===//
330 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
331 /// specified expression for the same cost as the expression itself, or 2 if we
332 /// can compute the negated form more cheaply than the expression itself.
333 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
334 unsigned Depth = 0) {
335 // No compile time optimizations on this type.
336 if (Op.getValueType() == MVT::ppcf128)
339 // fneg is removable even if it has multiple uses.
340 if (Op.getOpcode() == ISD::FNEG) return 2;
342 // Don't allow anything with multiple uses.
343 if (!Op.hasOneUse()) return 0;
345 // Don't recurse exponentially.
346 if (Depth > 6) return 0;
348 switch (Op.getOpcode()) {
349 default: return false;
350 case ISD::ConstantFP:
351 // Don't invert constant FP values after legalize. The negated constant
352 // isn't necessarily legal.
353 return LegalOperations ? 0 : 1;
355 // FIXME: determine better conditions for this xform.
356 if (!UnsafeFPMath) return 0;
358 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
359 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
361 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
362 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
364 // We can't turn -(A-B) into B-A when we honor signed zeros.
365 if (!UnsafeFPMath) return 0;
367 // fold (fneg (fsub A, B)) -> (fsub B, A)
372 if (HonorSignDependentRoundingFPMath()) return 0;
374 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
375 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
378 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
383 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1);
387 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
388 /// returns the newly negated expression.
389 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
390 bool LegalOperations, unsigned Depth = 0) {
391 // fneg is removable even if it has multiple uses.
392 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
394 // Don't allow anything with multiple uses.
395 assert(Op.hasOneUse() && "Unknown reuse!");
397 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
398 switch (Op.getOpcode()) {
399 default: llvm_unreachable("Unknown code");
400 case ISD::ConstantFP: {
401 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
403 return DAG.getConstantFP(V, Op.getValueType());
406 // FIXME: determine better conditions for this xform.
407 assert(UnsafeFPMath);
409 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
410 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
411 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
412 GetNegatedExpression(Op.getOperand(0), DAG,
413 LegalOperations, Depth+1),
415 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
416 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
417 GetNegatedExpression(Op.getOperand(1), DAG,
418 LegalOperations, Depth+1),
421 // We can't turn -(A-B) into B-A when we honor signed zeros.
422 assert(UnsafeFPMath);
424 // fold (fneg (fsub 0, B)) -> B
425 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
426 if (N0CFP->getValueAPF().isZero())
427 return Op.getOperand(1);
429 // fold (fneg (fsub A, B)) -> (fsub B, A)
430 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
431 Op.getOperand(1), Op.getOperand(0));
435 assert(!HonorSignDependentRoundingFPMath());
437 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
438 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
439 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
440 GetNegatedExpression(Op.getOperand(0), DAG,
441 LegalOperations, Depth+1),
444 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
445 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
447 GetNegatedExpression(Op.getOperand(1), DAG,
448 LegalOperations, Depth+1));
452 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
453 GetNegatedExpression(Op.getOperand(0), DAG,
454 LegalOperations, Depth+1));
456 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
457 GetNegatedExpression(Op.getOperand(0), DAG,
458 LegalOperations, Depth+1),
464 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
465 // that selects between the values 1 and 0, making it equivalent to a setcc.
466 // Also, set the incoming LHS, RHS, and CC references to the appropriate
467 // nodes based on the type of node we are checking. This simplifies life a
468 // bit for the callers.
469 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
471 if (N.getOpcode() == ISD::SETCC) {
472 LHS = N.getOperand(0);
473 RHS = N.getOperand(1);
474 CC = N.getOperand(2);
477 if (N.getOpcode() == ISD::SELECT_CC &&
478 N.getOperand(2).getOpcode() == ISD::Constant &&
479 N.getOperand(3).getOpcode() == ISD::Constant &&
480 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
481 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
482 LHS = N.getOperand(0);
483 RHS = N.getOperand(1);
484 CC = N.getOperand(4);
490 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
491 // one use. If this is true, it allows the users to invert the operation for
492 // free when it is profitable to do so.
493 static bool isOneUseSetCC(SDValue N) {
495 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
500 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
501 SDValue N0, SDValue N1) {
502 EVT VT = N0.getValueType();
503 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
504 if (isa<ConstantSDNode>(N1)) {
505 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
507 DAG.FoldConstantArithmetic(Opc, VT,
508 cast<ConstantSDNode>(N0.getOperand(1)),
509 cast<ConstantSDNode>(N1));
510 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
511 } else if (N0.hasOneUse()) {
512 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
513 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
514 N0.getOperand(0), N1);
515 AddToWorkList(OpNode.getNode());
516 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
520 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
521 if (isa<ConstantSDNode>(N0)) {
522 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
524 DAG.FoldConstantArithmetic(Opc, VT,
525 cast<ConstantSDNode>(N1.getOperand(1)),
526 cast<ConstantSDNode>(N0));
527 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
528 } else if (N1.hasOneUse()) {
529 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
530 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
531 N1.getOperand(0), N0);
532 AddToWorkList(OpNode.getNode());
533 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
540 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
542 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
544 DEBUG(dbgs() << "\nReplacing.1 ";
546 dbgs() << "\nWith: ";
547 To[0].getNode()->dump(&DAG);
548 dbgs() << " and " << NumTo-1 << " other values\n";
549 for (unsigned i = 0, e = NumTo; i != e; ++i)
550 assert((!To[i].getNode() ||
551 N->getValueType(i) == To[i].getValueType()) &&
552 "Cannot combine value to value of different type!"));
553 WorkListRemover DeadNodes(*this);
554 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
557 // Push the new nodes and any users onto the worklist
558 for (unsigned i = 0, e = NumTo; i != e; ++i) {
559 if (To[i].getNode()) {
560 AddToWorkList(To[i].getNode());
561 AddUsersToWorkList(To[i].getNode());
566 // Finally, if the node is now dead, remove it from the graph. The node
567 // may not be dead if the replacement process recursively simplified to
568 // something else needing this node.
569 if (N->use_empty()) {
570 // Nodes can be reintroduced into the worklist. Make sure we do not
571 // process a node that has been replaced.
572 removeFromWorkList(N);
574 // Finally, since the node is now dead, remove it from the graph.
577 return SDValue(N, 0);
581 DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &
583 // Replace all uses. If any nodes become isomorphic to other nodes and
584 // are deleted, make sure to remove them from our worklist.
585 WorkListRemover DeadNodes(*this);
586 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
588 // Push the new node and any (possibly new) users onto the worklist.
589 AddToWorkList(TLO.New.getNode());
590 AddUsersToWorkList(TLO.New.getNode());
592 // Finally, if the node is now dead, remove it from the graph. The node
593 // may not be dead if the replacement process recursively simplified to
594 // something else needing this node.
595 if (TLO.Old.getNode()->use_empty()) {
596 removeFromWorkList(TLO.Old.getNode());
598 // If the operands of this node are only used by the node, they will now
599 // be dead. Make sure to visit them first to delete dead nodes early.
600 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
601 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
602 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
604 DAG.DeleteNode(TLO.Old.getNode());
608 /// SimplifyDemandedBits - Check the specified integer node value to see if
609 /// it can be simplified or if things it uses can be simplified by bit
610 /// propagation. If so, return true.
611 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
612 TargetLowering::TargetLoweringOpt TLO(DAG);
613 APInt KnownZero, KnownOne;
614 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
618 AddToWorkList(Op.getNode());
620 // Replace the old value with the new one.
622 DEBUG(dbgs() << "\nReplacing.2 ";
623 TLO.Old.getNode()->dump(&DAG);
624 dbgs() << "\nWith: ";
625 TLO.New.getNode()->dump(&DAG);
628 CommitTargetLoweringOpt(TLO);
632 //===----------------------------------------------------------------------===//
633 // Main DAG Combiner implementation
634 //===----------------------------------------------------------------------===//
636 void DAGCombiner::Run(CombineLevel AtLevel) {
637 // set the instance variables, so that the various visit routines may use it.
639 LegalOperations = Level >= NoIllegalOperations;
640 LegalTypes = Level >= NoIllegalTypes;
642 // Add all the dag nodes to the worklist.
643 WorkList.reserve(DAG.allnodes_size());
644 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
645 E = DAG.allnodes_end(); I != E; ++I)
646 WorkList.push_back(I);
648 // Create a dummy node (which is not added to allnodes), that adds a reference
649 // to the root node, preventing it from being deleted, and tracking any
650 // changes of the root.
651 HandleSDNode Dummy(DAG.getRoot());
653 // The root of the dag may dangle to deleted nodes until the dag combiner is
654 // done. Set it to null to avoid confusion.
655 DAG.setRoot(SDValue());
657 // while the worklist isn't empty, inspect the node on the end of it and
658 // try and combine it.
659 while (!WorkList.empty()) {
660 SDNode *N = WorkList.back();
663 // If N has no uses, it is dead. Make sure to revisit all N's operands once
664 // N is deleted from the DAG, since they too may now be dead or may have a
665 // reduced number of uses, allowing other xforms.
666 if (N->use_empty() && N != &Dummy) {
667 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
668 AddToWorkList(N->getOperand(i).getNode());
674 SDValue RV = combine(N);
676 if (RV.getNode() == 0)
681 // If we get back the same node we passed in, rather than a new node or
682 // zero, we know that the node must have defined multiple values and
683 // CombineTo was used. Since CombineTo takes care of the worklist
684 // mechanics for us, we have no work to do in this case.
685 if (RV.getNode() == N)
688 assert(N->getOpcode() != ISD::DELETED_NODE &&
689 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
690 "Node was deleted but visit returned new node!");
692 DEBUG(dbgs() << "\nReplacing.3 ";
694 dbgs() << "\nWith: ";
695 RV.getNode()->dump(&DAG);
697 WorkListRemover DeadNodes(*this);
698 if (N->getNumValues() == RV.getNode()->getNumValues())
699 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
701 assert(N->getValueType(0) == RV.getValueType() &&
702 N->getNumValues() == 1 && "Type mismatch");
704 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
707 // Push the new node and any users onto the worklist
708 AddToWorkList(RV.getNode());
709 AddUsersToWorkList(RV.getNode());
711 // Add any uses of the old node to the worklist in case this node is the
712 // last one that uses them. They may become dead after this node is
714 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
715 AddToWorkList(N->getOperand(i).getNode());
717 // Finally, if the node is now dead, remove it from the graph. The node
718 // may not be dead if the replacement process recursively simplified to
719 // something else needing this node.
720 if (N->use_empty()) {
721 // Nodes can be reintroduced into the worklist. Make sure we do not
722 // process a node that has been replaced.
723 removeFromWorkList(N);
725 // Finally, since the node is now dead, remove it from the graph.
730 // If the root changed (e.g. it was a dead load, update the root).
731 DAG.setRoot(Dummy.getValue());
734 SDValue DAGCombiner::visit(SDNode *N) {
735 switch(N->getOpcode()) {
737 case ISD::TokenFactor: return visitTokenFactor(N);
738 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
739 case ISD::ADD: return visitADD(N);
740 case ISD::SUB: return visitSUB(N);
741 case ISD::ADDC: return visitADDC(N);
742 case ISD::ADDE: return visitADDE(N);
743 case ISD::MUL: return visitMUL(N);
744 case ISD::SDIV: return visitSDIV(N);
745 case ISD::UDIV: return visitUDIV(N);
746 case ISD::SREM: return visitSREM(N);
747 case ISD::UREM: return visitUREM(N);
748 case ISD::MULHU: return visitMULHU(N);
749 case ISD::MULHS: return visitMULHS(N);
750 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
751 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
752 case ISD::SDIVREM: return visitSDIVREM(N);
753 case ISD::UDIVREM: return visitUDIVREM(N);
754 case ISD::AND: return visitAND(N);
755 case ISD::OR: return visitOR(N);
756 case ISD::XOR: return visitXOR(N);
757 case ISD::SHL: return visitSHL(N);
758 case ISD::SRA: return visitSRA(N);
759 case ISD::SRL: return visitSRL(N);
760 case ISD::CTLZ: return visitCTLZ(N);
761 case ISD::CTTZ: return visitCTTZ(N);
762 case ISD::CTPOP: return visitCTPOP(N);
763 case ISD::SELECT: return visitSELECT(N);
764 case ISD::SELECT_CC: return visitSELECT_CC(N);
765 case ISD::SETCC: return visitSETCC(N);
766 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
767 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
768 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
769 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
770 case ISD::TRUNCATE: return visitTRUNCATE(N);
771 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
772 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
773 case ISD::FADD: return visitFADD(N);
774 case ISD::FSUB: return visitFSUB(N);
775 case ISD::FMUL: return visitFMUL(N);
776 case ISD::FDIV: return visitFDIV(N);
777 case ISD::FREM: return visitFREM(N);
778 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
779 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
780 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
781 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
782 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
783 case ISD::FP_ROUND: return visitFP_ROUND(N);
784 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
785 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
786 case ISD::FNEG: return visitFNEG(N);
787 case ISD::FABS: return visitFABS(N);
788 case ISD::BRCOND: return visitBRCOND(N);
789 case ISD::BR_CC: return visitBR_CC(N);
790 case ISD::LOAD: return visitLOAD(N);
791 case ISD::STORE: return visitSTORE(N);
792 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
793 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
794 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
795 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
796 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
801 SDValue DAGCombiner::combine(SDNode *N) {
802 SDValue RV = visit(N);
804 // If nothing happened, try a target-specific DAG combine.
805 if (RV.getNode() == 0) {
806 assert(N->getOpcode() != ISD::DELETED_NODE &&
807 "Node was deleted but visit returned NULL!");
809 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
810 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
812 // Expose the DAG combiner to the target combiner impls.
813 TargetLowering::DAGCombinerInfo
814 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
816 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
820 // If N is a commutative binary node, try commuting it to enable more
822 if (RV.getNode() == 0 &&
823 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
824 N->getNumValues() == 1) {
825 SDValue N0 = N->getOperand(0);
826 SDValue N1 = N->getOperand(1);
828 // Constant operands are canonicalized to RHS.
829 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
830 SDValue Ops[] = { N1, N0 };
831 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
834 return SDValue(CSENode, 0);
841 /// getInputChainForNode - Given a node, return its input chain if it has one,
842 /// otherwise return a null sd operand.
843 static SDValue getInputChainForNode(SDNode *N) {
844 if (unsigned NumOps = N->getNumOperands()) {
845 if (N->getOperand(0).getValueType() == MVT::Other)
846 return N->getOperand(0);
847 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
848 return N->getOperand(NumOps-1);
849 for (unsigned i = 1; i < NumOps-1; ++i)
850 if (N->getOperand(i).getValueType() == MVT::Other)
851 return N->getOperand(i);
856 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
857 // If N has two operands, where one has an input chain equal to the other,
858 // the 'other' chain is redundant.
859 if (N->getNumOperands() == 2) {
860 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
861 return N->getOperand(0);
862 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
863 return N->getOperand(1);
866 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
867 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
868 SmallPtrSet<SDNode*, 16> SeenOps;
869 bool Changed = false; // If we should replace this token factor.
871 // Start out with this token factor.
874 // Iterate through token factors. The TFs grows when new token factors are
876 for (unsigned i = 0; i < TFs.size(); ++i) {
879 // Check each of the operands.
880 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
881 SDValue Op = TF->getOperand(i);
883 switch (Op.getOpcode()) {
884 case ISD::EntryToken:
885 // Entry tokens don't need to be added to the list. They are
890 case ISD::TokenFactor:
891 if (Op.hasOneUse() &&
892 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
893 // Queue up for processing.
894 TFs.push_back(Op.getNode());
895 // Clean up in case the token factor is removed.
896 AddToWorkList(Op.getNode());
903 // Only add if it isn't already in the list.
904 if (SeenOps.insert(Op.getNode()))
915 // If we've change things around then replace token factor.
918 // The entry token is the only possible outcome.
919 Result = DAG.getEntryNode();
921 // New and improved token factor.
922 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
923 MVT::Other, &Ops[0], Ops.size());
926 // Don't add users to work list.
927 return CombineTo(N, Result, false);
933 /// MERGE_VALUES can always be eliminated.
934 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
935 WorkListRemover DeadNodes(*this);
936 // Replacing results may cause a different MERGE_VALUES to suddenly
937 // be CSE'd with N, and carry its uses with it. Iterate until no
938 // uses remain, to ensure that the node can be safely deleted.
940 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
941 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
943 } while (!N->use_empty());
944 removeFromWorkList(N);
946 return SDValue(N, 0); // Return N so it doesn't get rechecked!
950 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
952 EVT VT = N0.getValueType();
953 SDValue N00 = N0.getOperand(0);
954 SDValue N01 = N0.getOperand(1);
955 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
957 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
958 isa<ConstantSDNode>(N00.getOperand(1))) {
959 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
960 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
961 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
962 N00.getOperand(0), N01),
963 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
964 N00.getOperand(1), N01));
965 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
971 SDValue DAGCombiner::visitADD(SDNode *N) {
972 SDValue N0 = N->getOperand(0);
973 SDValue N1 = N->getOperand(1);
974 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
975 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
976 EVT VT = N0.getValueType();
980 SDValue FoldedVOp = SimplifyVBinOp(N);
981 if (FoldedVOp.getNode()) return FoldedVOp;
984 // fold (add x, undef) -> undef
985 if (N0.getOpcode() == ISD::UNDEF)
987 if (N1.getOpcode() == ISD::UNDEF)
989 // fold (add c1, c2) -> c1+c2
991 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
992 // canonicalize constant to RHS
994 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
995 // fold (add x, 0) -> x
996 if (N1C && N1C->isNullValue())
998 // fold (add Sym, c) -> Sym+c
999 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1000 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1001 GA->getOpcode() == ISD::GlobalAddress)
1002 return DAG.getGlobalAddress(GA->getGlobal(), VT,
1004 (uint64_t)N1C->getSExtValue());
1005 // fold ((c1-A)+c2) -> (c1+c2)-A
1006 if (N1C && N0.getOpcode() == ISD::SUB)
1007 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1008 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1009 DAG.getConstant(N1C->getAPIntValue()+
1010 N0C->getAPIntValue(), VT),
1013 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1014 if (RADD.getNode() != 0)
1016 // fold ((0-A) + B) -> B-A
1017 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1018 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1019 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1020 // fold (A + (0-B)) -> A-B
1021 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1022 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1023 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1024 // fold (A+(B-A)) -> B
1025 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1026 return N1.getOperand(0);
1027 // fold ((B-A)+A) -> B
1028 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1029 return N0.getOperand(0);
1030 // fold (A+(B-(A+C))) to (B-C)
1031 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1032 N0 == N1.getOperand(1).getOperand(0))
1033 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1034 N1.getOperand(1).getOperand(1));
1035 // fold (A+(B-(C+A))) to (B-C)
1036 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1037 N0 == N1.getOperand(1).getOperand(1))
1038 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1039 N1.getOperand(1).getOperand(0));
1040 // fold (A+((B-A)+or-C)) to (B+or-C)
1041 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1042 N1.getOperand(0).getOpcode() == ISD::SUB &&
1043 N0 == N1.getOperand(0).getOperand(1))
1044 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1045 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1047 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1048 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1049 SDValue N00 = N0.getOperand(0);
1050 SDValue N01 = N0.getOperand(1);
1051 SDValue N10 = N1.getOperand(0);
1052 SDValue N11 = N1.getOperand(1);
1054 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1055 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1056 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1057 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1060 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1061 return SDValue(N, 0);
1063 // fold (a+b) -> (a|b) iff a and b share no bits.
1064 if (VT.isInteger() && !VT.isVector()) {
1065 APInt LHSZero, LHSOne;
1066 APInt RHSZero, RHSOne;
1067 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1068 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1070 if (LHSZero.getBoolValue()) {
1071 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1073 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1074 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1075 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1076 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1077 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1081 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1082 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1083 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1084 if (Result.getNode()) return Result;
1086 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1087 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1088 if (Result.getNode()) return Result;
1091 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1092 if (N1.getOpcode() == ISD::SHL &&
1093 N1.getOperand(0).getOpcode() == ISD::SUB)
1094 if (ConstantSDNode *C =
1095 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1096 if (C->getAPIntValue() == 0)
1097 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1098 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1099 N1.getOperand(0).getOperand(1),
1101 if (N0.getOpcode() == ISD::SHL &&
1102 N0.getOperand(0).getOpcode() == ISD::SUB)
1103 if (ConstantSDNode *C =
1104 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1105 if (C->getAPIntValue() == 0)
1106 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1107 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1108 N0.getOperand(0).getOperand(1),
1114 SDValue DAGCombiner::visitADDC(SDNode *N) {
1115 SDValue N0 = N->getOperand(0);
1116 SDValue N1 = N->getOperand(1);
1117 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1118 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1119 EVT VT = N0.getValueType();
1121 // If the flag result is dead, turn this into an ADD.
1122 if (N->hasNUsesOfValue(0, 1))
1123 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
1124 DAG.getNode(ISD::CARRY_FALSE,
1125 N->getDebugLoc(), MVT::Flag));
1127 // canonicalize constant to RHS.
1129 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1131 // fold (addc x, 0) -> x + no carry out
1132 if (N1C && N1C->isNullValue())
1133 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1134 N->getDebugLoc(), MVT::Flag));
1136 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1137 APInt LHSZero, LHSOne;
1138 APInt RHSZero, RHSOne;
1139 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1140 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1142 if (LHSZero.getBoolValue()) {
1143 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1145 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1146 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1147 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1148 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1149 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1150 DAG.getNode(ISD::CARRY_FALSE,
1151 N->getDebugLoc(), MVT::Flag));
1157 SDValue DAGCombiner::visitADDE(SDNode *N) {
1158 SDValue N0 = N->getOperand(0);
1159 SDValue N1 = N->getOperand(1);
1160 SDValue CarryIn = N->getOperand(2);
1161 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1162 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1164 // canonicalize constant to RHS
1166 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1169 // fold (adde x, y, false) -> (addc x, y)
1170 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1171 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1176 SDValue DAGCombiner::visitSUB(SDNode *N) {
1177 SDValue N0 = N->getOperand(0);
1178 SDValue N1 = N->getOperand(1);
1179 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1180 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1181 EVT VT = N0.getValueType();
1184 if (VT.isVector()) {
1185 SDValue FoldedVOp = SimplifyVBinOp(N);
1186 if (FoldedVOp.getNode()) return FoldedVOp;
1189 // fold (sub x, x) -> 0
1191 return DAG.getConstant(0, N->getValueType(0));
1192 // fold (sub c1, c2) -> c1-c2
1194 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1195 // fold (sub x, c) -> (add x, -c)
1197 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1198 DAG.getConstant(-N1C->getAPIntValue(), VT));
1199 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1200 if (N0C && N0C->isAllOnesValue())
1201 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1202 // fold (A+B)-A -> B
1203 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1204 return N0.getOperand(1);
1205 // fold (A+B)-B -> A
1206 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1207 return N0.getOperand(0);
1208 // fold ((A+(B+or-C))-B) -> A+or-C
1209 if (N0.getOpcode() == ISD::ADD &&
1210 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1211 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1212 N0.getOperand(1).getOperand(0) == N1)
1213 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1214 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1215 // fold ((A+(C+B))-B) -> A+C
1216 if (N0.getOpcode() == ISD::ADD &&
1217 N0.getOperand(1).getOpcode() == ISD::ADD &&
1218 N0.getOperand(1).getOperand(1) == N1)
1219 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1220 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1221 // fold ((A-(B-C))-C) -> A-B
1222 if (N0.getOpcode() == ISD::SUB &&
1223 N0.getOperand(1).getOpcode() == ISD::SUB &&
1224 N0.getOperand(1).getOperand(1) == N1)
1225 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1226 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1228 // If either operand of a sub is undef, the result is undef
1229 if (N0.getOpcode() == ISD::UNDEF)
1231 if (N1.getOpcode() == ISD::UNDEF)
1234 // If the relocation model supports it, consider symbol offsets.
1235 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1236 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1237 // fold (sub Sym, c) -> Sym-c
1238 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1239 return DAG.getGlobalAddress(GA->getGlobal(), VT,
1241 (uint64_t)N1C->getSExtValue());
1242 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1243 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1244 if (GA->getGlobal() == GB->getGlobal())
1245 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1252 SDValue DAGCombiner::visitMUL(SDNode *N) {
1253 SDValue N0 = N->getOperand(0);
1254 SDValue N1 = N->getOperand(1);
1255 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1256 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1257 EVT VT = N0.getValueType();
1260 if (VT.isVector()) {
1261 SDValue FoldedVOp = SimplifyVBinOp(N);
1262 if (FoldedVOp.getNode()) return FoldedVOp;
1265 // fold (mul x, undef) -> 0
1266 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1267 return DAG.getConstant(0, VT);
1268 // fold (mul c1, c2) -> c1*c2
1270 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1271 // canonicalize constant to RHS
1273 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1274 // fold (mul x, 0) -> 0
1275 if (N1C && N1C->isNullValue())
1277 // fold (mul x, -1) -> 0-x
1278 if (N1C && N1C->isAllOnesValue())
1279 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1280 DAG.getConstant(0, VT), N0);
1281 // fold (mul x, (1 << c)) -> x << c
1282 if (N1C && N1C->getAPIntValue().isPowerOf2())
1283 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1284 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1285 getShiftAmountTy()));
1286 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1287 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1288 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1289 // FIXME: If the input is something that is easily negated (e.g. a
1290 // single-use add), we should put the negate there.
1291 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1292 DAG.getConstant(0, VT),
1293 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1294 DAG.getConstant(Log2Val, getShiftAmountTy())));
1296 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1297 if (N1C && N0.getOpcode() == ISD::SHL &&
1298 isa<ConstantSDNode>(N0.getOperand(1))) {
1299 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1300 N1, N0.getOperand(1));
1301 AddToWorkList(C3.getNode());
1302 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1303 N0.getOperand(0), C3);
1306 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1309 SDValue Sh(0,0), Y(0,0);
1310 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1311 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1312 N0.getNode()->hasOneUse()) {
1314 } else if (N1.getOpcode() == ISD::SHL &&
1315 isa<ConstantSDNode>(N1.getOperand(1)) &&
1316 N1.getNode()->hasOneUse()) {
1321 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1322 Sh.getOperand(0), Y);
1323 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1324 Mul, Sh.getOperand(1));
1328 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1329 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1330 isa<ConstantSDNode>(N0.getOperand(1)))
1331 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1332 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1333 N0.getOperand(0), N1),
1334 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1335 N0.getOperand(1), N1));
1338 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1339 if (RMUL.getNode() != 0)
1345 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1346 SDValue N0 = N->getOperand(0);
1347 SDValue N1 = N->getOperand(1);
1348 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1349 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1350 EVT VT = N->getValueType(0);
1353 if (VT.isVector()) {
1354 SDValue FoldedVOp = SimplifyVBinOp(N);
1355 if (FoldedVOp.getNode()) return FoldedVOp;
1358 // fold (sdiv c1, c2) -> c1/c2
1359 if (N0C && N1C && !N1C->isNullValue())
1360 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1361 // fold (sdiv X, 1) -> X
1362 if (N1C && N1C->getSExtValue() == 1LL)
1364 // fold (sdiv X, -1) -> 0-X
1365 if (N1C && N1C->isAllOnesValue())
1366 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1367 DAG.getConstant(0, VT), N0);
1368 // If we know the sign bits of both operands are zero, strength reduce to a
1369 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1370 if (!VT.isVector()) {
1371 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1372 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1375 // fold (sdiv X, pow2) -> simple ops after legalize
1376 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
1377 (isPowerOf2_64(N1C->getSExtValue()) ||
1378 isPowerOf2_64(-N1C->getSExtValue()))) {
1379 // If dividing by powers of two is cheap, then don't perform the following
1381 if (TLI.isPow2DivCheap())
1384 int64_t pow2 = N1C->getSExtValue();
1385 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1386 unsigned lg2 = Log2_64(abs2);
1388 // Splat the sign bit into the register
1389 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1390 DAG.getConstant(VT.getSizeInBits()-1,
1391 getShiftAmountTy()));
1392 AddToWorkList(SGN.getNode());
1394 // Add (N0 < 0) ? abs2 - 1 : 0;
1395 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1396 DAG.getConstant(VT.getSizeInBits() - lg2,
1397 getShiftAmountTy()));
1398 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1399 AddToWorkList(SRL.getNode());
1400 AddToWorkList(ADD.getNode()); // Divide by pow2
1401 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1402 DAG.getConstant(lg2, getShiftAmountTy()));
1404 // If we're dividing by a positive value, we're done. Otherwise, we must
1405 // negate the result.
1409 AddToWorkList(SRA.getNode());
1410 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1411 DAG.getConstant(0, VT), SRA);
1414 // if integer divide is expensive and we satisfy the requirements, emit an
1415 // alternate sequence.
1416 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
1417 !TLI.isIntDivCheap()) {
1418 SDValue Op = BuildSDIV(N);
1419 if (Op.getNode()) return Op;
1423 if (N0.getOpcode() == ISD::UNDEF)
1424 return DAG.getConstant(0, VT);
1425 // X / undef -> undef
1426 if (N1.getOpcode() == ISD::UNDEF)
1432 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1433 SDValue N0 = N->getOperand(0);
1434 SDValue N1 = N->getOperand(1);
1435 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1436 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1437 EVT VT = N->getValueType(0);
1440 if (VT.isVector()) {
1441 SDValue FoldedVOp = SimplifyVBinOp(N);
1442 if (FoldedVOp.getNode()) return FoldedVOp;
1445 // fold (udiv c1, c2) -> c1/c2
1446 if (N0C && N1C && !N1C->isNullValue())
1447 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1448 // fold (udiv x, (1 << c)) -> x >>u c
1449 if (N1C && N1C->getAPIntValue().isPowerOf2())
1450 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1451 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1452 getShiftAmountTy()));
1453 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1454 if (N1.getOpcode() == ISD::SHL) {
1455 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1456 if (SHC->getAPIntValue().isPowerOf2()) {
1457 EVT ADDVT = N1.getOperand(1).getValueType();
1458 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1460 DAG.getConstant(SHC->getAPIntValue()
1463 AddToWorkList(Add.getNode());
1464 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1468 // fold (udiv x, c) -> alternate
1469 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1470 SDValue Op = BuildUDIV(N);
1471 if (Op.getNode()) return Op;
1475 if (N0.getOpcode() == ISD::UNDEF)
1476 return DAG.getConstant(0, VT);
1477 // X / undef -> undef
1478 if (N1.getOpcode() == ISD::UNDEF)
1484 SDValue DAGCombiner::visitSREM(SDNode *N) {
1485 SDValue N0 = N->getOperand(0);
1486 SDValue N1 = N->getOperand(1);
1487 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1488 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1489 EVT VT = N->getValueType(0);
1491 // fold (srem c1, c2) -> c1%c2
1492 if (N0C && N1C && !N1C->isNullValue())
1493 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1494 // If we know the sign bits of both operands are zero, strength reduce to a
1495 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1496 if (!VT.isVector()) {
1497 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1498 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1501 // If X/C can be simplified by the division-by-constant logic, lower
1502 // X%C to the equivalent of X-X/C*C.
1503 if (N1C && !N1C->isNullValue()) {
1504 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1505 AddToWorkList(Div.getNode());
1506 SDValue OptimizedDiv = combine(Div.getNode());
1507 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1508 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1510 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1511 AddToWorkList(Mul.getNode());
1517 if (N0.getOpcode() == ISD::UNDEF)
1518 return DAG.getConstant(0, VT);
1519 // X % undef -> undef
1520 if (N1.getOpcode() == ISD::UNDEF)
1526 SDValue DAGCombiner::visitUREM(SDNode *N) {
1527 SDValue N0 = N->getOperand(0);
1528 SDValue N1 = N->getOperand(1);
1529 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1530 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1531 EVT VT = N->getValueType(0);
1533 // fold (urem c1, c2) -> c1%c2
1534 if (N0C && N1C && !N1C->isNullValue())
1535 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
1536 // fold (urem x, pow2) -> (and x, pow2-1)
1537 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
1538 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
1539 DAG.getConstant(N1C->getAPIntValue()-1,VT));
1540 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1541 if (N1.getOpcode() == ISD::SHL) {
1542 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1543 if (SHC->getAPIntValue().isPowerOf2()) {
1545 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
1546 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
1548 AddToWorkList(Add.getNode());
1549 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
1554 // If X/C can be simplified by the division-by-constant logic, lower
1555 // X%C to the equivalent of X-X/C*C.
1556 if (N1C && !N1C->isNullValue()) {
1557 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
1558 AddToWorkList(Div.getNode());
1559 SDValue OptimizedDiv = combine(Div.getNode());
1560 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1561 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1563 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1564 AddToWorkList(Mul.getNode());
1570 if (N0.getOpcode() == ISD::UNDEF)
1571 return DAG.getConstant(0, VT);
1572 // X % undef -> undef
1573 if (N1.getOpcode() == ISD::UNDEF)
1579 SDValue DAGCombiner::visitMULHS(SDNode *N) {
1580 SDValue N0 = N->getOperand(0);
1581 SDValue N1 = N->getOperand(1);
1582 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1583 EVT VT = N->getValueType(0);
1585 // fold (mulhs x, 0) -> 0
1586 if (N1C && N1C->isNullValue())
1588 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1589 if (N1C && N1C->getAPIntValue() == 1)
1590 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
1591 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
1592 getShiftAmountTy()));
1593 // fold (mulhs x, undef) -> 0
1594 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1595 return DAG.getConstant(0, VT);
1600 SDValue DAGCombiner::visitMULHU(SDNode *N) {
1601 SDValue N0 = N->getOperand(0);
1602 SDValue N1 = N->getOperand(1);
1603 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1604 EVT VT = N->getValueType(0);
1606 // fold (mulhu x, 0) -> 0
1607 if (N1C && N1C->isNullValue())
1609 // fold (mulhu x, 1) -> 0
1610 if (N1C && N1C->getAPIntValue() == 1)
1611 return DAG.getConstant(0, N0.getValueType());
1612 // fold (mulhu x, undef) -> 0
1613 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1614 return DAG.getConstant(0, VT);
1619 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1620 /// compute two values. LoOp and HiOp give the opcodes for the two computations
1621 /// that are being performed. Return true if a simplification was made.
1623 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
1625 // If the high half is not needed, just compute the low half.
1626 bool HiExists = N->hasAnyUseOfValue(1);
1628 (!LegalOperations ||
1629 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1630 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1631 N->op_begin(), N->getNumOperands());
1632 return CombineTo(N, Res, Res);
1635 // If the low half is not needed, just compute the high half.
1636 bool LoExists = N->hasAnyUseOfValue(0);
1638 (!LegalOperations ||
1639 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
1640 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1641 N->op_begin(), N->getNumOperands());
1642 return CombineTo(N, Res, Res);
1645 // If both halves are used, return as it is.
1646 if (LoExists && HiExists)
1649 // If the two computed results can be simplified separately, separate them.
1651 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1652 N->op_begin(), N->getNumOperands());
1653 AddToWorkList(Lo.getNode());
1654 SDValue LoOpt = combine(Lo.getNode());
1655 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
1656 (!LegalOperations ||
1657 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
1658 return CombineTo(N, LoOpt, LoOpt);
1662 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1663 N->op_begin(), N->getNumOperands());
1664 AddToWorkList(Hi.getNode());
1665 SDValue HiOpt = combine(Hi.getNode());
1666 if (HiOpt.getNode() && HiOpt != Hi &&
1667 (!LegalOperations ||
1668 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
1669 return CombineTo(N, HiOpt, HiOpt);
1675 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
1676 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
1677 if (Res.getNode()) return Res;
1682 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
1683 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
1684 if (Res.getNode()) return Res;
1689 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
1690 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
1691 if (Res.getNode()) return Res;
1696 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
1697 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
1698 if (Res.getNode()) return Res;
1703 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1704 /// two operands of the same opcode, try to simplify it.
1705 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1706 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1707 EVT VT = N0.getValueType();
1708 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1710 // Bail early if none of these transforms apply.
1711 if (N0.getNode()->getNumOperands() == 0) return SDValue();
1713 // For each of OP in AND/OR/XOR:
1714 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1715 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1716 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1717 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1719 // do not sink logical op inside of a vector extend, since it may combine
1721 EVT Op0VT = N0.getOperand(0).getValueType();
1722 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
1723 N0.getOpcode() == ISD::ANY_EXTEND ||
1724 N0.getOpcode() == ISD::SIGN_EXTEND ||
1725 (N0.getOpcode() == ISD::TRUNCATE && TLI.isTypeLegal(Op0VT))) &&
1727 Op0VT == N1.getOperand(0).getValueType() &&
1728 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
1729 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
1730 N0.getOperand(0).getValueType(),
1731 N0.getOperand(0), N1.getOperand(0));
1732 AddToWorkList(ORNode.getNode());
1733 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
1736 // For each of OP in SHL/SRL/SRA/AND...
1737 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1738 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1739 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1740 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1741 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1742 N0.getOperand(1) == N1.getOperand(1)) {
1743 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
1744 N0.getOperand(0).getValueType(),
1745 N0.getOperand(0), N1.getOperand(0));
1746 AddToWorkList(ORNode.getNode());
1747 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
1748 ORNode, N0.getOperand(1));
1754 SDValue DAGCombiner::visitAND(SDNode *N) {
1755 SDValue N0 = N->getOperand(0);
1756 SDValue N1 = N->getOperand(1);
1757 SDValue LL, LR, RL, RR, CC0, CC1;
1758 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1759 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1760 EVT VT = N1.getValueType();
1761 unsigned BitWidth = VT.getScalarType().getSizeInBits();
1764 if (VT.isVector()) {
1765 SDValue FoldedVOp = SimplifyVBinOp(N);
1766 if (FoldedVOp.getNode()) return FoldedVOp;
1769 // fold (and x, undef) -> 0
1770 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1771 return DAG.getConstant(0, VT);
1772 // fold (and c1, c2) -> c1&c2
1774 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
1775 // canonicalize constant to RHS
1777 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
1778 // fold (and x, -1) -> x
1779 if (N1C && N1C->isAllOnesValue())
1781 // if (and x, c) is known to be zero, return 0
1782 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
1783 APInt::getAllOnesValue(BitWidth)))
1784 return DAG.getConstant(0, VT);
1786 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
1787 if (RAND.getNode() != 0)
1789 // fold (and (or x, C), D) -> D if (C & D) == D
1790 if (N1C && N0.getOpcode() == ISD::OR)
1791 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1792 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
1794 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1795 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1796 SDValue N0Op0 = N0.getOperand(0);
1797 APInt Mask = ~N1C->getAPIntValue();
1798 Mask.trunc(N0Op0.getValueSizeInBits());
1799 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
1800 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
1801 N0.getValueType(), N0Op0);
1803 // Replace uses of the AND with uses of the Zero extend node.
1806 // We actually want to replace all uses of the any_extend with the
1807 // zero_extend, to avoid duplicating things. This will later cause this
1808 // AND to be folded.
1809 CombineTo(N0.getNode(), Zext);
1810 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1813 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1814 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1815 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1816 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1818 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1819 LL.getValueType().isInteger()) {
1820 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
1821 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
1822 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
1823 LR.getValueType(), LL, RL);
1824 AddToWorkList(ORNode.getNode());
1825 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
1827 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
1828 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1829 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
1830 LR.getValueType(), LL, RL);
1831 AddToWorkList(ANDNode.getNode());
1832 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
1834 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
1835 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1836 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
1837 LR.getValueType(), LL, RL);
1838 AddToWorkList(ORNode.getNode());
1839 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
1842 // canonicalize equivalent to ll == rl
1843 if (LL == RR && LR == RL) {
1844 Op1 = ISD::getSetCCSwappedOperands(Op1);
1847 if (LL == RL && LR == RR) {
1848 bool isInteger = LL.getValueType().isInteger();
1849 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1850 if (Result != ISD::SETCC_INVALID &&
1851 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
1852 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
1857 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
1858 if (N0.getOpcode() == N1.getOpcode()) {
1859 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1860 if (Tmp.getNode()) return Tmp;
1863 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1864 // fold (and (sra)) -> (and (srl)) when possible.
1865 if (!VT.isVector() &&
1866 SimplifyDemandedBits(SDValue(N, 0)))
1867 return SDValue(N, 0);
1869 // fold (zext_inreg (extload x)) -> (zextload x)
1870 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
1871 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1872 EVT MemVT = LN0->getMemoryVT();
1873 // If we zero all the possible extended bits, then we can turn this into
1874 // a zextload if we are running before legalize or the operation is legal.
1875 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
1876 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1877 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
1878 ((!LegalOperations && !LN0->isVolatile()) ||
1879 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
1880 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
1881 LN0->getChain(), LN0->getBasePtr(),
1883 LN0->getSrcValueOffset(), MemVT,
1884 LN0->isVolatile(), LN0->isNonTemporal(),
1885 LN0->getAlignment());
1887 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
1888 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1891 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1892 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
1894 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1895 EVT MemVT = LN0->getMemoryVT();
1896 // If we zero all the possible extended bits, then we can turn this into
1897 // a zextload if we are running before legalize or the operation is legal.
1898 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
1899 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1900 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
1901 ((!LegalOperations && !LN0->isVolatile()) ||
1902 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
1903 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
1905 LN0->getBasePtr(), LN0->getSrcValue(),
1906 LN0->getSrcValueOffset(), MemVT,
1907 LN0->isVolatile(), LN0->isNonTemporal(),
1908 LN0->getAlignment());
1910 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
1911 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1915 // fold (and (load x), 255) -> (zextload x, i8)
1916 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1917 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
1918 if (N1C && (N0.getOpcode() == ISD::LOAD ||
1919 (N0.getOpcode() == ISD::ANY_EXTEND &&
1920 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
1921 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
1922 LoadSDNode *LN0 = HasAnyExt
1923 ? cast<LoadSDNode>(N0.getOperand(0))
1924 : cast<LoadSDNode>(N0);
1925 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1926 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
1927 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
1928 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
1929 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
1930 EVT LoadedVT = LN0->getMemoryVT();
1932 if (ExtVT == LoadedVT &&
1933 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
1934 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
1937 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
1938 LN0->getChain(), LN0->getBasePtr(),
1939 LN0->getSrcValue(), LN0->getSrcValueOffset(),
1940 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
1941 LN0->getAlignment());
1943 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
1944 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1947 // Do not change the width of a volatile load.
1948 // Do not generate loads of non-round integer types since these can
1949 // be expensive (and would be wrong if the type is not byte sized).
1950 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
1951 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
1952 EVT PtrType = LN0->getOperand(1).getValueType();
1954 unsigned Alignment = LN0->getAlignment();
1955 SDValue NewPtr = LN0->getBasePtr();
1957 // For big endian targets, we need to add an offset to the pointer
1958 // to load the correct bytes. For little endian systems, we merely
1959 // need to read fewer bytes from the same pointer.
1960 if (TLI.isBigEndian()) {
1961 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
1962 unsigned EVTStoreBytes = ExtVT.getStoreSize();
1963 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
1964 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
1965 NewPtr, DAG.getConstant(PtrOff, PtrType));
1966 Alignment = MinAlign(Alignment, PtrOff);
1969 AddToWorkList(NewPtr.getNode());
1971 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
1973 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
1974 LN0->getChain(), NewPtr,
1975 LN0->getSrcValue(), LN0->getSrcValueOffset(),
1976 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
1979 CombineTo(LN0, Load, Load.getValue(1));
1980 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1989 SDValue DAGCombiner::visitOR(SDNode *N) {
1990 SDValue N0 = N->getOperand(0);
1991 SDValue N1 = N->getOperand(1);
1992 SDValue LL, LR, RL, RR, CC0, CC1;
1993 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1994 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1995 EVT VT = N1.getValueType();
1998 if (VT.isVector()) {
1999 SDValue FoldedVOp = SimplifyVBinOp(N);
2000 if (FoldedVOp.getNode()) return FoldedVOp;
2003 // fold (or x, undef) -> -1
2004 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) {
2005 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
2006 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
2008 // fold (or c1, c2) -> c1|c2
2010 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
2011 // canonicalize constant to RHS
2013 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
2014 // fold (or x, 0) -> x
2015 if (N1C && N1C->isNullValue())
2017 // fold (or x, -1) -> -1
2018 if (N1C && N1C->isAllOnesValue())
2020 // fold (or x, c) -> c iff (x & ~c) == 0
2021 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
2024 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
2025 if (ROR.getNode() != 0)
2027 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
2028 // iff (c1 & c2) == 0.
2029 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
2030 isa<ConstantSDNode>(N0.getOperand(1))) {
2031 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
2032 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
2033 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
2034 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2035 N0.getOperand(0), N1),
2036 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
2038 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
2039 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2040 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2041 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2043 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2044 LL.getValueType().isInteger()) {
2045 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
2046 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
2047 if (cast<ConstantSDNode>(LR)->isNullValue() &&
2048 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
2049 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
2050 LR.getValueType(), LL, RL);
2051 AddToWorkList(ORNode.getNode());
2052 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2054 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
2055 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
2056 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2057 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
2058 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
2059 LR.getValueType(), LL, RL);
2060 AddToWorkList(ANDNode.getNode());
2061 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2064 // canonicalize equivalent to ll == rl
2065 if (LL == RR && LR == RL) {
2066 Op1 = ISD::getSetCCSwappedOperands(Op1);
2069 if (LL == RL && LR == RR) {
2070 bool isInteger = LL.getValueType().isInteger();
2071 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
2072 if (Result != ISD::SETCC_INVALID &&
2073 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2074 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2079 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
2080 if (N0.getOpcode() == N1.getOpcode()) {
2081 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2082 if (Tmp.getNode()) return Tmp;
2085 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
2086 if (N0.getOpcode() == ISD::AND &&
2087 N1.getOpcode() == ISD::AND &&
2088 N0.getOperand(1).getOpcode() == ISD::Constant &&
2089 N1.getOperand(1).getOpcode() == ISD::Constant &&
2090 // Don't increase # computations.
2091 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
2092 // We can only do this xform if we know that bits from X that are set in C2
2093 // but not in C1 are already zero. Likewise for Y.
2094 const APInt &LHSMask =
2095 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2096 const APInt &RHSMask =
2097 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
2099 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
2100 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
2101 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2102 N0.getOperand(0), N1.getOperand(0));
2103 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
2104 DAG.getConstant(LHSMask | RHSMask, VT));
2108 // See if this is some rotate idiom.
2109 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
2110 return SDValue(Rot, 0);
2115 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
2116 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
2117 if (Op.getOpcode() == ISD::AND) {
2118 if (isa<ConstantSDNode>(Op.getOperand(1))) {
2119 Mask = Op.getOperand(1);
2120 Op = Op.getOperand(0);
2126 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
2134 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
2135 // idioms for rotate, and if the target supports rotation instructions, generate
2137 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
2138 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
2139 EVT VT = LHS.getValueType();
2140 if (!TLI.isTypeLegal(VT)) return 0;
2142 // The target must have at least one rotate flavor.
2143 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
2144 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
2145 if (!HasROTL && !HasROTR) return 0;
2147 // Match "(X shl/srl V1) & V2" where V2 may not be present.
2148 SDValue LHSShift; // The shift.
2149 SDValue LHSMask; // AND value if any.
2150 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
2151 return 0; // Not part of a rotate.
2153 SDValue RHSShift; // The shift.
2154 SDValue RHSMask; // AND value if any.
2155 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
2156 return 0; // Not part of a rotate.
2158 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
2159 return 0; // Not shifting the same value.
2161 if (LHSShift.getOpcode() == RHSShift.getOpcode())
2162 return 0; // Shifts must disagree.
2164 // Canonicalize shl to left side in a shl/srl pair.
2165 if (RHSShift.getOpcode() == ISD::SHL) {
2166 std::swap(LHS, RHS);
2167 std::swap(LHSShift, RHSShift);
2168 std::swap(LHSMask , RHSMask );
2171 unsigned OpSizeInBits = VT.getSizeInBits();
2172 SDValue LHSShiftArg = LHSShift.getOperand(0);
2173 SDValue LHSShiftAmt = LHSShift.getOperand(1);
2174 SDValue RHSShiftAmt = RHSShift.getOperand(1);
2176 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
2177 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
2178 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
2179 RHSShiftAmt.getOpcode() == ISD::Constant) {
2180 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
2181 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
2182 if ((LShVal + RShVal) != OpSizeInBits)
2187 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
2189 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
2191 // If there is an AND of either shifted operand, apply it to the result.
2192 if (LHSMask.getNode() || RHSMask.getNode()) {
2193 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
2195 if (LHSMask.getNode()) {
2196 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
2197 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
2199 if (RHSMask.getNode()) {
2200 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
2201 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
2204 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
2207 return Rot.getNode();
2210 // If there is a mask here, and we have a variable shift, we can't be sure
2211 // that we're masking out the right stuff.
2212 if (LHSMask.getNode() || RHSMask.getNode())
2215 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
2216 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
2217 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
2218 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
2219 if (ConstantSDNode *SUBC =
2220 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
2221 if (SUBC->getAPIntValue() == OpSizeInBits) {
2223 return DAG.getNode(ISD::ROTL, DL, VT,
2224 LHSShiftArg, LHSShiftAmt).getNode();
2226 return DAG.getNode(ISD::ROTR, DL, VT,
2227 LHSShiftArg, RHSShiftAmt).getNode();
2232 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2233 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
2234 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
2235 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
2236 if (ConstantSDNode *SUBC =
2237 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
2238 if (SUBC->getAPIntValue() == OpSizeInBits) {
2240 return DAG.getNode(ISD::ROTR, DL, VT,
2241 LHSShiftArg, RHSShiftAmt).getNode();
2243 return DAG.getNode(ISD::ROTL, DL, VT,
2244 LHSShiftArg, LHSShiftAmt).getNode();
2249 // Look for sign/zext/any-extended or truncate cases:
2250 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2251 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2252 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2253 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
2254 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2255 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2256 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2257 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
2258 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
2259 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
2260 if (RExtOp0.getOpcode() == ISD::SUB &&
2261 RExtOp0.getOperand(1) == LExtOp0) {
2262 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2264 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2265 // (rotr x, (sub 32, y))
2266 if (ConstantSDNode *SUBC =
2267 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
2268 if (SUBC->getAPIntValue() == OpSizeInBits) {
2269 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
2271 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
2274 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2275 RExtOp0 == LExtOp0.getOperand(1)) {
2276 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2278 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2279 // (rotl x, (sub 32, y))
2280 if (ConstantSDNode *SUBC =
2281 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2282 if (SUBC->getAPIntValue() == OpSizeInBits) {
2283 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
2285 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
2294 SDValue DAGCombiner::visitXOR(SDNode *N) {
2295 SDValue N0 = N->getOperand(0);
2296 SDValue N1 = N->getOperand(1);
2297 SDValue LHS, RHS, CC;
2298 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2299 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2300 EVT VT = N0.getValueType();
2303 if (VT.isVector()) {
2304 SDValue FoldedVOp = SimplifyVBinOp(N);
2305 if (FoldedVOp.getNode()) return FoldedVOp;
2308 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
2309 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
2310 return DAG.getConstant(0, VT);
2311 // fold (xor x, undef) -> undef
2312 if (N0.getOpcode() == ISD::UNDEF)
2314 if (N1.getOpcode() == ISD::UNDEF)
2316 // fold (xor c1, c2) -> c1^c2
2318 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
2319 // canonicalize constant to RHS
2321 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
2322 // fold (xor x, 0) -> x
2323 if (N1C && N1C->isNullValue())
2326 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
2327 if (RXOR.getNode() != 0)
2330 // fold !(x cc y) -> (x !cc y)
2331 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2332 bool isInt = LHS.getValueType().isInteger();
2333 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2336 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
2337 switch (N0.getOpcode()) {
2339 llvm_unreachable("Unhandled SetCC Equivalent!");
2341 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
2342 case ISD::SELECT_CC:
2343 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
2344 N0.getOperand(3), NotCC);
2349 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2350 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2351 N0.getNode()->hasOneUse() &&
2352 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2353 SDValue V = N0.getOperand(0);
2354 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
2355 DAG.getConstant(1, V.getValueType()));
2356 AddToWorkList(V.getNode());
2357 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
2360 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
2361 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
2362 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2363 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2364 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2365 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2366 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2367 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2368 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2369 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2372 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
2373 if (N1C && N1C->isAllOnesValue() &&
2374 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2375 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2376 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2377 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2378 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2379 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2380 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2381 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2384 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
2385 if (N1C && N0.getOpcode() == ISD::XOR) {
2386 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2387 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2389 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
2390 DAG.getConstant(N1C->getAPIntValue() ^
2391 N00C->getAPIntValue(), VT));
2393 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
2394 DAG.getConstant(N1C->getAPIntValue() ^
2395 N01C->getAPIntValue(), VT));
2397 // fold (xor x, x) -> 0
2399 if (!VT.isVector()) {
2400 return DAG.getConstant(0, VT);
2401 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){
2402 // Produce a vector of zeros.
2403 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
2404 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
2405 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
2406 &Ops[0], Ops.size());
2410 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2411 if (N0.getOpcode() == N1.getOpcode()) {
2412 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2413 if (Tmp.getNode()) return Tmp;
2416 // Simplify the expression using non-local knowledge.
2417 if (!VT.isVector() &&
2418 SimplifyDemandedBits(SDValue(N, 0)))
2419 return SDValue(N, 0);
2424 /// visitShiftByConstant - Handle transforms common to the three shifts, when
2425 /// the shift amount is a constant.
2426 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
2427 SDNode *LHS = N->getOperand(0).getNode();
2428 if (!LHS->hasOneUse()) return SDValue();
2430 // We want to pull some binops through shifts, so that we have (and (shift))
2431 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
2432 // thing happens with address calculations, so it's important to canonicalize
2434 bool HighBitSet = false; // Can we transform this if the high bit is set?
2436 switch (LHS->getOpcode()) {
2437 default: return SDValue();
2440 HighBitSet = false; // We can only transform sra if the high bit is clear.
2443 HighBitSet = true; // We can only transform sra if the high bit is set.
2446 if (N->getOpcode() != ISD::SHL)
2447 return SDValue(); // only shl(add) not sr[al](add).
2448 HighBitSet = false; // We can only transform sra if the high bit is clear.
2452 // We require the RHS of the binop to be a constant as well.
2453 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
2454 if (!BinOpCst) return SDValue();
2456 // FIXME: disable this unless the input to the binop is a shift by a constant.
2457 // If it is not a shift, it pessimizes some common cases like:
2459 // void foo(int *X, int i) { X[i & 1235] = 1; }
2460 // int bar(int *X, int i) { return X[i & 255]; }
2461 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
2462 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
2463 BinOpLHSVal->getOpcode() != ISD::SRA &&
2464 BinOpLHSVal->getOpcode() != ISD::SRL) ||
2465 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
2468 EVT VT = N->getValueType(0);
2470 // If this is a signed shift right, and the high bit is modified by the
2471 // logical operation, do not perform the transformation. The highBitSet
2472 // boolean indicates the value of the high bit of the constant which would
2473 // cause it to be modified for this operation.
2474 if (N->getOpcode() == ISD::SRA) {
2475 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
2476 if (BinOpRHSSignSet != HighBitSet)
2480 // Fold the constants, shifting the binop RHS by the shift amount.
2481 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
2483 LHS->getOperand(1), N->getOperand(1));
2485 // Create the new shift.
2486 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(),
2487 VT, LHS->getOperand(0), N->getOperand(1));
2489 // Create the new binop.
2490 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
2493 SDValue DAGCombiner::visitSHL(SDNode *N) {
2494 SDValue N0 = N->getOperand(0);
2495 SDValue N1 = N->getOperand(1);
2496 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2497 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2498 EVT VT = N0.getValueType();
2499 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
2501 // fold (shl c1, c2) -> c1<<c2
2503 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
2504 // fold (shl 0, x) -> 0
2505 if (N0C && N0C->isNullValue())
2507 // fold (shl x, c >= size(x)) -> undef
2508 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2509 return DAG.getUNDEF(VT);
2510 // fold (shl x, 0) -> x
2511 if (N1C && N1C->isNullValue())
2513 // if (shl x, c) is known to be zero, return 0
2514 if (DAG.MaskedValueIsZero(SDValue(N, 0),
2515 APInt::getAllOnesValue(OpSizeInBits)))
2516 return DAG.getConstant(0, VT);
2517 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
2518 if (N1.getOpcode() == ISD::TRUNCATE &&
2519 N1.getOperand(0).getOpcode() == ISD::AND &&
2520 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2521 SDValue N101 = N1.getOperand(0).getOperand(1);
2522 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2523 EVT TruncVT = N1.getValueType();
2524 SDValue N100 = N1.getOperand(0).getOperand(0);
2525 APInt TruncC = N101C->getAPIntValue();
2526 TruncC.trunc(TruncVT.getSizeInBits());
2527 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
2528 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
2529 DAG.getNode(ISD::TRUNCATE,
2532 DAG.getConstant(TruncC, TruncVT)));
2536 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2537 return SDValue(N, 0);
2539 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
2540 if (N1C && N0.getOpcode() == ISD::SHL &&
2541 N0.getOperand(1).getOpcode() == ISD::Constant) {
2542 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2543 uint64_t c2 = N1C->getZExtValue();
2544 if (c1 + c2 > OpSizeInBits)
2545 return DAG.getConstant(0, VT);
2546 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
2547 DAG.getConstant(c1 + c2, N1.getValueType()));
2549 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or
2550 // (srl (and x, (shl -1, c1)), (sub c1, c2))
2551 if (N1C && N0.getOpcode() == ISD::SRL &&
2552 N0.getOperand(1).getOpcode() == ISD::Constant) {
2553 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2554 if (c1 < VT.getSizeInBits()) {
2555 uint64_t c2 = N1C->getZExtValue();
2556 SDValue HiBitsMask =
2557 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
2558 VT.getSizeInBits() - c1),
2560 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT,
2564 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask,
2565 DAG.getConstant(c2-c1, N1.getValueType()));
2567 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask,
2568 DAG.getConstant(c1-c2, N1.getValueType()));
2571 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
2572 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
2573 SDValue HiBitsMask =
2574 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
2575 VT.getSizeInBits() -
2576 N1C->getZExtValue()),
2578 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
2582 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2585 SDValue DAGCombiner::visitSRA(SDNode *N) {
2586 SDValue N0 = N->getOperand(0);
2587 SDValue N1 = N->getOperand(1);
2588 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2589 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2590 EVT VT = N0.getValueType();
2591 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
2593 // fold (sra c1, c2) -> (sra c1, c2)
2595 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
2596 // fold (sra 0, x) -> 0
2597 if (N0C && N0C->isNullValue())
2599 // fold (sra -1, x) -> -1
2600 if (N0C && N0C->isAllOnesValue())
2602 // fold (sra x, (setge c, size(x))) -> undef
2603 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2604 return DAG.getUNDEF(VT);
2605 // fold (sra x, 0) -> x
2606 if (N1C && N1C->isNullValue())
2608 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2610 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2611 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
2612 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
2614 ExtVT = EVT::getVectorVT(*DAG.getContext(),
2615 ExtVT, VT.getVectorNumElements());
2616 if ((!LegalOperations ||
2617 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
2618 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
2619 N0.getOperand(0), DAG.getValueType(ExtVT));
2622 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
2623 if (N1C && N0.getOpcode() == ISD::SRA) {
2624 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2625 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
2626 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
2627 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
2628 DAG.getConstant(Sum, N1C->getValueType(0)));
2632 // fold (sra (shl X, m), (sub result_size, n))
2633 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
2634 // result_size - n != m.
2635 // If truncate is free for the target sext(shl) is likely to result in better
2637 if (N0.getOpcode() == ISD::SHL) {
2638 // Get the two constanst of the shifts, CN0 = m, CN = n.
2639 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2641 // Determine what the truncate's result bitsize and type would be.
2643 EVT::getIntegerVT(*DAG.getContext(), OpSizeInBits - N1C->getZExtValue());
2644 // Determine the residual right-shift amount.
2645 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
2647 // If the shift is not a no-op (in which case this should be just a sign
2648 // extend already), the truncated to type is legal, sign_extend is legal
2649 // on that type, and the truncate to that type is both legal and free,
2650 // perform the transform.
2651 if ((ShiftAmt > 0) &&
2652 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
2653 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
2654 TLI.isTruncateFree(VT, TruncVT)) {
2656 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy());
2657 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
2658 N0.getOperand(0), Amt);
2659 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
2661 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
2662 N->getValueType(0), Trunc);
2667 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
2668 if (N1.getOpcode() == ISD::TRUNCATE &&
2669 N1.getOperand(0).getOpcode() == ISD::AND &&
2670 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2671 SDValue N101 = N1.getOperand(0).getOperand(1);
2672 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2673 EVT TruncVT = N1.getValueType();
2674 SDValue N100 = N1.getOperand(0).getOperand(0);
2675 APInt TruncC = N101C->getAPIntValue();
2676 TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
2677 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
2678 DAG.getNode(ISD::AND, N->getDebugLoc(),
2680 DAG.getNode(ISD::TRUNCATE,
2683 DAG.getConstant(TruncC, TruncVT)));
2687 // Simplify, based on bits shifted out of the LHS.
2688 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2689 return SDValue(N, 0);
2692 // If the sign bit is known to be zero, switch this to a SRL.
2693 if (DAG.SignBitIsZero(N0))
2694 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
2696 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2699 SDValue DAGCombiner::visitSRL(SDNode *N) {
2700 SDValue N0 = N->getOperand(0);
2701 SDValue N1 = N->getOperand(1);
2702 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2703 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2704 EVT VT = N0.getValueType();
2705 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
2707 // fold (srl c1, c2) -> c1 >>u c2
2709 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
2710 // fold (srl 0, x) -> 0
2711 if (N0C && N0C->isNullValue())
2713 // fold (srl x, c >= size(x)) -> undef
2714 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2715 return DAG.getUNDEF(VT);
2716 // fold (srl x, 0) -> x
2717 if (N1C && N1C->isNullValue())
2719 // if (srl x, c) is known to be zero, return 0
2720 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2721 APInt::getAllOnesValue(OpSizeInBits)))
2722 return DAG.getConstant(0, VT);
2724 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
2725 if (N1C && N0.getOpcode() == ISD::SRL &&
2726 N0.getOperand(1).getOpcode() == ISD::Constant) {
2727 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2728 uint64_t c2 = N1C->getZExtValue();
2729 if (c1 + c2 > OpSizeInBits)
2730 return DAG.getConstant(0, VT);
2731 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
2732 DAG.getConstant(c1 + c2, N1.getValueType()));
2735 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
2736 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2737 // Shifting in all undef bits?
2738 EVT SmallVT = N0.getOperand(0).getValueType();
2739 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
2740 return DAG.getUNDEF(VT);
2742 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
2743 N0.getOperand(0), N1);
2744 AddToWorkList(SmallShift.getNode());
2745 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
2748 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
2749 // bit, which is unmodified by sra.
2750 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
2751 if (N0.getOpcode() == ISD::SRA)
2752 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
2755 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
2756 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2757 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
2758 APInt KnownZero, KnownOne;
2759 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
2760 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
2762 // If any of the input bits are KnownOne, then the input couldn't be all
2763 // zeros, thus the result of the srl will always be zero.
2764 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
2766 // If all of the bits input the to ctlz node are known to be zero, then
2767 // the result of the ctlz is "32" and the result of the shift is one.
2768 APInt UnknownBits = ~KnownZero & Mask;
2769 if (UnknownBits == 0) return DAG.getConstant(1, VT);
2771 // Otherwise, check to see if there is exactly one bit input to the ctlz.
2772 if ((UnknownBits & (UnknownBits - 1)) == 0) {
2773 // Okay, we know that only that the single bit specified by UnknownBits
2774 // could be set on input to the CTLZ node. If this bit is set, the SRL
2775 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
2776 // to an SRL/XOR pair, which is likely to simplify more.
2777 unsigned ShAmt = UnknownBits.countTrailingZeros();
2778 SDValue Op = N0.getOperand(0);
2781 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
2782 DAG.getConstant(ShAmt, getShiftAmountTy()));
2783 AddToWorkList(Op.getNode());
2786 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
2787 Op, DAG.getConstant(1, VT));
2791 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
2792 if (N1.getOpcode() == ISD::TRUNCATE &&
2793 N1.getOperand(0).getOpcode() == ISD::AND &&
2794 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2795 SDValue N101 = N1.getOperand(0).getOperand(1);
2796 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2797 EVT TruncVT = N1.getValueType();
2798 SDValue N100 = N1.getOperand(0).getOperand(0);
2799 APInt TruncC = N101C->getAPIntValue();
2800 TruncC.trunc(TruncVT.getSizeInBits());
2801 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
2802 DAG.getNode(ISD::AND, N->getDebugLoc(),
2804 DAG.getNode(ISD::TRUNCATE,
2807 DAG.getConstant(TruncC, TruncVT)));
2811 // fold operands of srl based on knowledge that the low bits are not
2813 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2814 return SDValue(N, 0);
2817 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
2818 if (NewSRL.getNode())
2822 // Here is a common situation. We want to optimize:
2825 // %b = and i32 %a, 2
2826 // %c = srl i32 %b, 1
2827 // brcond i32 %c ...
2833 // %c = setcc eq %b, 0
2836 // However when after the source operand of SRL is optimized into AND, the SRL
2837 // itself may not be optimized further. Look for it and add the BRCOND into
2839 if (N->hasOneUse()) {
2840 SDNode *Use = *N->use_begin();
2841 if (Use->getOpcode() == ISD::BRCOND)
2843 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
2844 // Also look pass the truncate.
2845 Use = *Use->use_begin();
2846 if (Use->getOpcode() == ISD::BRCOND)
2854 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
2855 SDValue N0 = N->getOperand(0);
2856 EVT VT = N->getValueType(0);
2858 // fold (ctlz c1) -> c2
2859 if (isa<ConstantSDNode>(N0))
2860 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
2864 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
2865 SDValue N0 = N->getOperand(0);
2866 EVT VT = N->getValueType(0);
2868 // fold (cttz c1) -> c2
2869 if (isa<ConstantSDNode>(N0))
2870 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
2874 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
2875 SDValue N0 = N->getOperand(0);
2876 EVT VT = N->getValueType(0);
2878 // fold (ctpop c1) -> c2
2879 if (isa<ConstantSDNode>(N0))
2880 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
2884 SDValue DAGCombiner::visitSELECT(SDNode *N) {
2885 SDValue N0 = N->getOperand(0);
2886 SDValue N1 = N->getOperand(1);
2887 SDValue N2 = N->getOperand(2);
2888 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2889 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2890 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2891 EVT VT = N->getValueType(0);
2892 EVT VT0 = N0.getValueType();
2894 // fold (select C, X, X) -> X
2897 // fold (select true, X, Y) -> X
2898 if (N0C && !N0C->isNullValue())
2900 // fold (select false, X, Y) -> Y
2901 if (N0C && N0C->isNullValue())
2903 // fold (select C, 1, X) -> (or C, X)
2904 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
2905 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
2906 // fold (select C, 0, 1) -> (xor C, 1)
2907 if (VT.isInteger() &&
2910 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
2911 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
2914 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
2915 N0, DAG.getConstant(1, VT0));
2916 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
2917 N0, DAG.getConstant(1, VT0));
2918 AddToWorkList(XORNode.getNode());
2920 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
2921 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
2923 // fold (select C, 0, X) -> (and (not C), X)
2924 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
2925 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
2926 AddToWorkList(NOTNode.getNode());
2927 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
2929 // fold (select C, X, 1) -> (or (not C), X)
2930 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
2931 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
2932 AddToWorkList(NOTNode.getNode());
2933 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
2935 // fold (select C, X, 0) -> (and C, X)
2936 if (VT == MVT::i1 && N2C && N2C->isNullValue())
2937 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
2938 // fold (select X, X, Y) -> (or X, Y)
2939 // fold (select X, 1, Y) -> (or X, Y)
2940 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
2941 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
2942 // fold (select X, Y, X) -> (and X, Y)
2943 // fold (select X, Y, 0) -> (and X, Y)
2944 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
2945 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
2947 // If we can fold this based on the true/false value, do so.
2948 if (SimplifySelectOps(N, N1, N2))
2949 return SDValue(N, 0); // Don't revisit N.
2951 // fold selects based on a setcc into other things, such as min/max/abs
2952 if (N0.getOpcode() == ISD::SETCC) {
2954 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
2955 // having to say they don't support SELECT_CC on every type the DAG knows
2956 // about, since there is no way to mark an opcode illegal at all value types
2957 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
2958 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
2959 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
2960 N0.getOperand(0), N0.getOperand(1),
2961 N1, N2, N0.getOperand(2));
2962 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
2968 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
2969 SDValue N0 = N->getOperand(0);
2970 SDValue N1 = N->getOperand(1);
2971 SDValue N2 = N->getOperand(2);
2972 SDValue N3 = N->getOperand(3);
2973 SDValue N4 = N->getOperand(4);
2974 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
2976 // fold select_cc lhs, rhs, x, x, cc -> x
2980 // Determine if the condition we're dealing with is constant
2981 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
2982 N0, N1, CC, N->getDebugLoc(), false);
2983 if (SCC.getNode()) AddToWorkList(SCC.getNode());
2985 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
2986 if (!SCCC->isNullValue())
2987 return N2; // cond always true -> true val
2989 return N3; // cond always false -> false val
2992 // Fold to a simpler select_cc
2993 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
2994 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
2995 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
2998 // If we can fold this based on the true/false value, do so.
2999 if (SimplifySelectOps(N, N2, N3))
3000 return SDValue(N, 0); // Don't revisit N.
3002 // fold select_cc into other things, such as min/max/abs
3003 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
3006 SDValue DAGCombiner::visitSETCC(SDNode *N) {
3007 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
3008 cast<CondCodeSDNode>(N->getOperand(2))->get(),
3012 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
3013 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
3014 // transformation. Returns true if extension are possible and the above
3015 // mentioned transformation is profitable.
3016 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
3018 SmallVector<SDNode*, 4> &ExtendNodes,
3019 const TargetLowering &TLI) {
3020 bool HasCopyToRegUses = false;
3021 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
3022 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
3023 UE = N0.getNode()->use_end();
3028 if (UI.getUse().getResNo() != N0.getResNo())
3030 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
3031 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
3032 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
3033 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
3034 // Sign bits will be lost after a zext.
3037 for (unsigned i = 0; i != 2; ++i) {
3038 SDValue UseOp = User->getOperand(i);
3041 if (!isa<ConstantSDNode>(UseOp))
3046 ExtendNodes.push_back(User);
3049 // If truncates aren't free and there are users we can't
3050 // extend, it isn't worthwhile.
3053 // Remember if this value is live-out.
3054 if (User->getOpcode() == ISD::CopyToReg)
3055 HasCopyToRegUses = true;
3058 if (HasCopyToRegUses) {
3059 bool BothLiveOut = false;
3060 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3062 SDUse &Use = UI.getUse();
3063 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
3069 // Both unextended and extended values are live out. There had better be
3070 // good a reason for the transformation.
3071 return ExtendNodes.size();
3076 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
3077 SDValue N0 = N->getOperand(0);
3078 EVT VT = N->getValueType(0);
3080 // fold (sext c1) -> c1
3081 if (isa<ConstantSDNode>(N0))
3082 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
3084 // fold (sext (sext x)) -> (sext x)
3085 // fold (sext (aext x)) -> (sext x)
3086 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3087 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
3090 if (N0.getOpcode() == ISD::TRUNCATE) {
3091 // fold (sext (truncate (load x))) -> (sext (smaller load x))
3092 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
3093 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3094 if (NarrowLoad.getNode()) {
3095 if (NarrowLoad.getNode() != N0.getNode())
3096 CombineTo(N0.getNode(), NarrowLoad);
3097 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3100 // See if the value being truncated is already sign extended. If so, just
3101 // eliminate the trunc/sext pair.
3102 SDValue Op = N0.getOperand(0);
3103 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
3104 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
3105 unsigned DestBits = VT.getScalarType().getSizeInBits();
3106 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
3108 if (OpBits == DestBits) {
3109 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
3110 // bits, it is already ready.
3111 if (NumSignBits > DestBits-MidBits)
3113 } else if (OpBits < DestBits) {
3114 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
3115 // bits, just sext from i32.
3116 if (NumSignBits > OpBits-MidBits)
3117 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
3119 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
3120 // bits, just truncate to i32.
3121 if (NumSignBits > OpBits-MidBits)
3122 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3125 // fold (sext (truncate x)) -> (sextinreg x).
3126 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
3127 N0.getValueType())) {
3128 if (OpBits < DestBits)
3129 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
3130 else if (OpBits > DestBits)
3131 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
3132 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
3133 DAG.getValueType(N0.getValueType()));
3137 // fold (sext (load x)) -> (sext (truncate (sextload x)))
3138 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3139 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3140 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
3141 bool DoXform = true;
3142 SmallVector<SDNode*, 4> SetCCs;
3143 if (!N0.hasOneUse())
3144 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
3146 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3147 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3149 LN0->getBasePtr(), LN0->getSrcValue(),
3150 LN0->getSrcValueOffset(),
3152 LN0->isVolatile(), LN0->isNonTemporal(),
3153 LN0->getAlignment());
3154 CombineTo(N, ExtLoad);
3155 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3156 N0.getValueType(), ExtLoad);
3157 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3159 // Extend SetCC uses if necessary.
3160 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3161 SDNode *SetCC = SetCCs[i];
3162 SmallVector<SDValue, 4> Ops;
3164 for (unsigned j = 0; j != 2; ++j) {
3165 SDValue SOp = SetCC->getOperand(j);
3167 Ops.push_back(ExtLoad);
3169 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND,
3170 N->getDebugLoc(), VT, SOp));
3173 Ops.push_back(SetCC->getOperand(2));
3174 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3175 SetCC->getValueType(0),
3176 &Ops[0], Ops.size()));
3179 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3183 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
3184 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
3185 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3186 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3187 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3188 EVT MemVT = LN0->getMemoryVT();
3189 if ((!LegalOperations && !LN0->isVolatile()) ||
3190 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
3191 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3193 LN0->getBasePtr(), LN0->getSrcValue(),
3194 LN0->getSrcValueOffset(), MemVT,
3195 LN0->isVolatile(), LN0->isNonTemporal(),
3196 LN0->getAlignment());
3197 CombineTo(N, ExtLoad);
3198 CombineTo(N0.getNode(),
3199 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3200 N0.getValueType(), ExtLoad),
3201 ExtLoad.getValue(1));
3202 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3206 if (N0.getOpcode() == ISD::SETCC) {
3207 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
3208 if (VT.isVector() &&
3209 // We know that the # elements of the results is the same as the
3210 // # elements of the compare (and the # elements of the compare result
3211 // for that matter). Check to see that they are the same size. If so,
3212 // we know that the element size of the sext'd result matches the
3213 // element size of the compare operands.
3214 VT.getSizeInBits() == N0.getOperand(0).getValueType().getSizeInBits() &&
3216 // Only do this before legalize for now.
3218 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
3220 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3223 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
3225 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
3227 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3228 NegOne, DAG.getConstant(0, VT),
3229 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3230 if (SCC.getNode()) return SCC;
3231 if (!LegalOperations ||
3232 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
3233 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
3234 DAG.getSetCC(N->getDebugLoc(),
3235 TLI.getSetCCResultType(VT),
3236 N0.getOperand(0), N0.getOperand(1),
3237 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
3238 NegOne, DAG.getConstant(0, VT));
3243 // fold (sext x) -> (zext x) if the sign bit is known zero.
3244 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
3245 DAG.SignBitIsZero(N0))
3246 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3251 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
3252 SDValue N0 = N->getOperand(0);
3253 EVT VT = N->getValueType(0);
3255 // fold (zext c1) -> c1
3256 if (isa<ConstantSDNode>(N0))
3257 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3258 // fold (zext (zext x)) -> (zext x)
3259 // fold (zext (aext x)) -> (zext x)
3260 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3261 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
3264 // fold (zext (truncate (load x))) -> (zext (smaller load x))
3265 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
3266 if (N0.getOpcode() == ISD::TRUNCATE) {
3267 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3268 if (NarrowLoad.getNode()) {
3269 if (NarrowLoad.getNode() != N0.getNode())
3270 CombineTo(N0.getNode(), NarrowLoad);
3271 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3275 // fold (zext (truncate x)) -> (and x, mask)
3276 if (N0.getOpcode() == ISD::TRUNCATE &&
3277 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT)) &&
3278 (!TLI.isTruncateFree(N0.getOperand(0).getValueType(),
3279 N0.getValueType()) ||
3280 !TLI.isZExtFree(N0.getValueType(), VT))) {
3281 SDValue Op = N0.getOperand(0);
3282 if (Op.getValueType().bitsLT(VT)) {
3283 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
3284 } else if (Op.getValueType().bitsGT(VT)) {
3285 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3287 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
3288 N0.getValueType().getScalarType());
3291 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
3292 // if either of the casts is not free.
3293 if (N0.getOpcode() == ISD::AND &&
3294 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3295 N0.getOperand(1).getOpcode() == ISD::Constant &&
3296 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3297 N0.getValueType()) ||
3298 !TLI.isZExtFree(N0.getValueType(), VT))) {
3299 SDValue X = N0.getOperand(0).getOperand(0);
3300 if (X.getValueType().bitsLT(VT)) {
3301 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
3302 } else if (X.getValueType().bitsGT(VT)) {
3303 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
3305 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3306 Mask.zext(VT.getSizeInBits());
3307 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3308 X, DAG.getConstant(Mask, VT));
3311 // fold (zext (load x)) -> (zext (truncate (zextload x)))
3312 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3313 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3314 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
3315 bool DoXform = true;
3316 SmallVector<SDNode*, 4> SetCCs;
3317 if (!N0.hasOneUse())
3318 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
3320 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3321 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3323 LN0->getBasePtr(), LN0->getSrcValue(),
3324 LN0->getSrcValueOffset(),
3326 LN0->isVolatile(), LN0->isNonTemporal(),
3327 LN0->getAlignment());
3328 CombineTo(N, ExtLoad);
3329 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3330 N0.getValueType(), ExtLoad);
3331 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3333 // Extend SetCC uses if necessary.
3334 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3335 SDNode *SetCC = SetCCs[i];
3336 SmallVector<SDValue, 4> Ops;
3338 for (unsigned j = 0; j != 2; ++j) {
3339 SDValue SOp = SetCC->getOperand(j);
3341 Ops.push_back(ExtLoad);
3343 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND,
3344 N->getDebugLoc(), VT, SOp));
3347 Ops.push_back(SetCC->getOperand(2));
3348 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3349 SetCC->getValueType(0),
3350 &Ops[0], Ops.size()));
3353 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3357 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
3358 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
3359 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3360 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3361 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3362 EVT MemVT = LN0->getMemoryVT();
3363 if ((!LegalOperations && !LN0->isVolatile()) ||
3364 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
3365 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3367 LN0->getBasePtr(), LN0->getSrcValue(),
3368 LN0->getSrcValueOffset(), MemVT,
3369 LN0->isVolatile(), LN0->isNonTemporal(),
3370 LN0->getAlignment());
3371 CombineTo(N, ExtLoad);
3372 CombineTo(N0.getNode(),
3373 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
3375 ExtLoad.getValue(1));
3376 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3380 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3381 if (N0.getOpcode() == ISD::SETCC) {
3383 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3384 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3385 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3386 if (SCC.getNode()) return SCC;
3389 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
3390 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
3391 isa<ConstantSDNode>(N0.getOperand(1)) &&
3392 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
3394 if (N0.getOpcode() == ISD::SHL) {
3395 // If the original shl may be shifting out bits, do not perform this
3397 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3398 unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() -
3399 N0.getOperand(0).getOperand(0).getValueType().getSizeInBits();
3400 if (ShAmt > KnownZeroBits)
3403 DebugLoc dl = N->getDebugLoc();
3404 return DAG.getNode(N0.getOpcode(), dl, VT,
3405 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)),
3406 DAG.getNode(ISD::ZERO_EXTEND, dl,
3407 N0.getOperand(1).getValueType(),
3414 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
3415 SDValue N0 = N->getOperand(0);
3416 EVT VT = N->getValueType(0);
3418 // fold (aext c1) -> c1
3419 if (isa<ConstantSDNode>(N0))
3420 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
3421 // fold (aext (aext x)) -> (aext x)
3422 // fold (aext (zext x)) -> (zext x)
3423 // fold (aext (sext x)) -> (sext x)
3424 if (N0.getOpcode() == ISD::ANY_EXTEND ||
3425 N0.getOpcode() == ISD::ZERO_EXTEND ||
3426 N0.getOpcode() == ISD::SIGN_EXTEND)
3427 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
3429 // fold (aext (truncate (load x))) -> (aext (smaller load x))
3430 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
3431 if (N0.getOpcode() == ISD::TRUNCATE) {
3432 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3433 if (NarrowLoad.getNode()) {
3434 if (NarrowLoad.getNode() != N0.getNode())
3435 CombineTo(N0.getNode(), NarrowLoad);
3436 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3440 // fold (aext (truncate x))
3441 if (N0.getOpcode() == ISD::TRUNCATE) {
3442 SDValue TruncOp = N0.getOperand(0);
3443 if (TruncOp.getValueType() == VT)
3444 return TruncOp; // x iff x size == zext size.
3445 if (TruncOp.getValueType().bitsGT(VT))
3446 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
3447 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
3450 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
3451 // if the trunc is not free.
3452 if (N0.getOpcode() == ISD::AND &&
3453 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3454 N0.getOperand(1).getOpcode() == ISD::Constant &&
3455 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3456 N0.getValueType())) {
3457 SDValue X = N0.getOperand(0).getOperand(0);
3458 if (X.getValueType().bitsLT(VT)) {
3459 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
3460 } else if (X.getValueType().bitsGT(VT)) {
3461 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
3463 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3464 Mask.zext(VT.getSizeInBits());
3465 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3466 X, DAG.getConstant(Mask, VT));
3469 // fold (aext (load x)) -> (aext (truncate (extload x)))
3470 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3471 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3472 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
3473 bool DoXform = true;
3474 SmallVector<SDNode*, 4> SetCCs;
3475 if (!N0.hasOneUse())
3476 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
3478 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3479 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
3481 LN0->getBasePtr(), LN0->getSrcValue(),
3482 LN0->getSrcValueOffset(),
3484 LN0->isVolatile(), LN0->isNonTemporal(),
3485 LN0->getAlignment());
3486 CombineTo(N, ExtLoad);
3487 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3488 N0.getValueType(), ExtLoad);
3489 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3491 // Extend SetCC uses if necessary.
3492 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3493 SDNode *SetCC = SetCCs[i];
3494 SmallVector<SDValue, 4> Ops;
3496 for (unsigned j = 0; j != 2; ++j) {
3497 SDValue SOp = SetCC->getOperand(j);
3499 Ops.push_back(ExtLoad);
3501 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND,
3502 N->getDebugLoc(), VT, SOp));
3505 Ops.push_back(SetCC->getOperand(2));
3506 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3507 SetCC->getValueType(0),
3508 &Ops[0], Ops.size()));
3511 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3515 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
3516 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
3517 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
3518 if (N0.getOpcode() == ISD::LOAD &&
3519 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3521 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3522 EVT MemVT = LN0->getMemoryVT();
3523 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
3524 VT, LN0->getChain(), LN0->getBasePtr(),
3526 LN0->getSrcValueOffset(), MemVT,
3527 LN0->isVolatile(), LN0->isNonTemporal(),
3528 LN0->getAlignment());
3529 CombineTo(N, ExtLoad);
3530 CombineTo(N0.getNode(),
3531 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3532 N0.getValueType(), ExtLoad),
3533 ExtLoad.getValue(1));
3534 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3537 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3538 if (N0.getOpcode() == ISD::SETCC) {
3540 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3541 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3542 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3550 /// GetDemandedBits - See if the specified operand can be simplified with the
3551 /// knowledge that only the bits specified by Mask are used. If so, return the
3552 /// simpler operand, otherwise return a null SDValue.
3553 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
3554 switch (V.getOpcode()) {
3558 // If the LHS or RHS don't contribute bits to the or, drop them.
3559 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
3560 return V.getOperand(1);
3561 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
3562 return V.getOperand(0);
3565 // Only look at single-use SRLs.
3566 if (!V.getNode()->hasOneUse())
3568 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
3569 // See if we can recursively simplify the LHS.
3570 unsigned Amt = RHSC->getZExtValue();
3572 // Watch out for shift count overflow though.
3573 if (Amt >= Mask.getBitWidth()) break;
3574 APInt NewMask = Mask << Amt;
3575 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
3576 if (SimplifyLHS.getNode())
3577 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
3578 SimplifyLHS, V.getOperand(1));
3584 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
3585 /// bits and then truncated to a narrower type and where N is a multiple
3586 /// of number of bits of the narrower type, transform it to a narrower load
3587 /// from address + N / num of bits of new type. If the result is to be
3588 /// extended, also fold the extension to form a extending load.
3589 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
3590 unsigned Opc = N->getOpcode();
3591 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
3592 SDValue N0 = N->getOperand(0);
3593 EVT VT = N->getValueType(0);
3596 // This transformation isn't valid for vector loads.
3600 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
3602 if (Opc == ISD::SIGN_EXTEND_INREG) {
3603 ExtType = ISD::SEXTLOAD;
3604 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3605 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT))
3609 unsigned EVTBits = ExtVT.getSizeInBits();
3611 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() && ExtVT.isRound()) {
3612 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3613 ShAmt = N01->getZExtValue();
3614 // Is the shift amount a multiple of size of VT?
3615 if ((ShAmt & (EVTBits-1)) == 0) {
3616 N0 = N0.getOperand(0);
3617 // Is the load width a multiple of size of VT?
3618 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
3624 // Do not generate loads of non-round integer types since these can
3625 // be expensive (and would be wrong if the type is not byte sized).
3626 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() &&
3627 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits &&
3628 // Do not change the width of a volatile load.
3629 !cast<LoadSDNode>(N0)->isVolatile()) {
3630 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3631 EVT PtrType = N0.getOperand(1).getValueType();
3633 // For big endian targets, we need to adjust the offset to the pointer to
3634 // load the correct bytes.
3635 if (TLI.isBigEndian()) {
3636 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
3637 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
3638 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
3641 uint64_t PtrOff = ShAmt / 8;
3642 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
3643 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
3644 PtrType, LN0->getBasePtr(),
3645 DAG.getConstant(PtrOff, PtrType));
3646 AddToWorkList(NewPtr.getNode());
3648 SDValue Load = (ExtType == ISD::NON_EXTLOAD)
3649 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
3650 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
3651 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign)
3652 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr,
3653 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
3654 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
3657 // Replace the old load's chain with the new load's chain.
3658 WorkListRemover DeadNodes(*this);
3659 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
3662 // Return the new loaded value.
3669 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
3670 SDValue N0 = N->getOperand(0);
3671 SDValue N1 = N->getOperand(1);
3672 EVT VT = N->getValueType(0);
3673 EVT EVT = cast<VTSDNode>(N1)->getVT();
3674 unsigned VTBits = VT.getScalarType().getSizeInBits();
3675 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
3677 // fold (sext_in_reg c1) -> c1
3678 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
3679 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
3681 // If the input is already sign extended, just drop the extension.
3682 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
3685 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
3686 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3687 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
3688 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3689 N0.getOperand(0), N1);
3692 // fold (sext_in_reg (sext x)) -> (sext x)
3693 // fold (sext_in_reg (aext x)) -> (sext x)
3694 // if x is small enough.
3695 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
3696 SDValue N00 = N0.getOperand(0);
3697 if (N00.getValueType().getScalarType().getSizeInBits() < EVTBits)
3698 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
3701 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
3702 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
3703 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
3705 // fold operands of sext_in_reg based on knowledge that the top bits are not
3707 if (SimplifyDemandedBits(SDValue(N, 0)))
3708 return SDValue(N, 0);
3710 // fold (sext_in_reg (load x)) -> (smaller sextload x)
3711 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
3712 SDValue NarrowLoad = ReduceLoadWidth(N);
3713 if (NarrowLoad.getNode())
3716 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
3717 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
3718 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
3719 if (N0.getOpcode() == ISD::SRL) {
3720 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
3721 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
3722 // We can turn this into an SRA iff the input to the SRL is already sign
3724 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
3725 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
3726 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
3727 N0.getOperand(0), N0.getOperand(1));
3731 // fold (sext_inreg (extload x)) -> (sextload x)
3732 if (ISD::isEXTLoad(N0.getNode()) &&
3733 ISD::isUNINDEXEDLoad(N0.getNode()) &&
3734 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3735 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3736 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
3737 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3738 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3740 LN0->getBasePtr(), LN0->getSrcValue(),
3741 LN0->getSrcValueOffset(), EVT,
3742 LN0->isVolatile(), LN0->isNonTemporal(),
3743 LN0->getAlignment());
3744 CombineTo(N, ExtLoad);
3745 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3746 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3748 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
3749 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3751 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3752 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3753 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
3754 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3755 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3757 LN0->getBasePtr(), LN0->getSrcValue(),
3758 LN0->getSrcValueOffset(), EVT,
3759 LN0->isVolatile(), LN0->isNonTemporal(),
3760 LN0->getAlignment());
3761 CombineTo(N, ExtLoad);
3762 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3763 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3768 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
3769 SDValue N0 = N->getOperand(0);
3770 EVT VT = N->getValueType(0);
3773 if (N0.getValueType() == N->getValueType(0))
3775 // fold (truncate c1) -> c1
3776 if (isa<ConstantSDNode>(N0))
3777 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
3778 // fold (truncate (truncate x)) -> (truncate x)
3779 if (N0.getOpcode() == ISD::TRUNCATE)
3780 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
3781 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
3782 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
3783 N0.getOpcode() == ISD::ANY_EXTEND) {
3784 if (N0.getOperand(0).getValueType().bitsLT(VT))
3785 // if the source is smaller than the dest, we still need an extend
3786 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
3788 else if (N0.getOperand(0).getValueType().bitsGT(VT))
3789 // if the source is larger than the dest, than we just need the truncate
3790 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
3792 // if the source and dest are the same type, we can drop both the extend
3793 // and the truncate.
3794 return N0.getOperand(0);
3797 // See if we can simplify the input to this truncate through knowledge that
3798 // only the low bits are being used. For example "trunc (or (shl x, 8), y)"
3801 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
3802 VT.getSizeInBits()));
3803 if (Shorter.getNode())
3804 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
3806 // fold (truncate (load x)) -> (smaller load x)
3807 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
3808 return ReduceLoadWidth(N);
3811 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
3812 SDValue Elt = N->getOperand(i);
3813 if (Elt.getOpcode() != ISD::MERGE_VALUES)
3814 return Elt.getNode();
3815 return Elt.getOperand(Elt.getResNo()).getNode();
3818 /// CombineConsecutiveLoads - build_pair (load, load) -> load
3819 /// if load locations are consecutive.
3820 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
3821 assert(N->getOpcode() == ISD::BUILD_PAIR);
3823 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
3824 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
3825 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse())
3827 EVT LD1VT = LD1->getValueType(0);
3829 if (ISD::isNON_EXTLoad(LD2) &&
3831 // If both are volatile this would reduce the number of volatile loads.
3832 // If one is volatile it might be ok, but play conservative and bail out.
3833 !LD1->isVolatile() &&
3834 !LD2->isVolatile() &&
3835 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
3836 unsigned Align = LD1->getAlignment();
3837 unsigned NewAlign = TLI.getTargetData()->
3838 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
3840 if (NewAlign <= Align &&
3841 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
3842 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
3843 LD1->getBasePtr(), LD1->getSrcValue(),
3844 LD1->getSrcValueOffset(), false, false, Align);
3850 SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
3851 SDValue N0 = N->getOperand(0);
3852 EVT VT = N->getValueType(0);
3854 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
3855 // Only do this before legalize, since afterward the target may be depending
3856 // on the bitconvert.
3857 // First check to see if this is all constant.
3859 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
3861 bool isSimple = true;
3862 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
3863 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
3864 N0.getOperand(i).getOpcode() != ISD::Constant &&
3865 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
3870 EVT DestEltVT = N->getValueType(0).getVectorElementType();
3871 assert(!DestEltVT.isVector() &&
3872 "Element type of vector ValueType must not be vector!");
3874 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT);
3877 // If the input is a constant, let getNode fold it.
3878 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
3879 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0);
3880 if (Res.getNode() != N) {
3881 if (!LegalOperations ||
3882 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
3885 // Folding it resulted in an illegal node, and it's too late to
3886 // do that. Clean up the old node and forego the transformation.
3887 // Ideally this won't happen very often, because instcombine
3888 // and the earlier dagcombine runs (where illegal nodes are
3889 // permitted) should have folded most of them already.
3890 DAG.DeleteNode(Res.getNode());
3894 // (conv (conv x, t1), t2) -> (conv x, t2)
3895 if (N0.getOpcode() == ISD::BIT_CONVERT)
3896 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT,
3899 // fold (conv (load x)) -> (load (conv*)x)
3900 // If the resultant load doesn't need a higher alignment than the original!
3901 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
3902 // Do not change the width of a volatile load.
3903 !cast<LoadSDNode>(N0)->isVolatile() &&
3904 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
3905 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3906 unsigned Align = TLI.getTargetData()->
3907 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
3908 unsigned OrigAlign = LN0->getAlignment();
3910 if (Align <= OrigAlign) {
3911 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
3913 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3914 LN0->isVolatile(), LN0->isNonTemporal(),
3917 CombineTo(N0.getNode(),
3918 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
3919 N0.getValueType(), Load),
3925 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
3926 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
3927 // This often reduces constant pool loads.
3928 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
3929 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
3930 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT,
3932 AddToWorkList(NewConv.getNode());
3934 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
3935 if (N0.getOpcode() == ISD::FNEG)
3936 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3937 NewConv, DAG.getConstant(SignBit, VT));
3938 assert(N0.getOpcode() == ISD::FABS);
3939 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3940 NewConv, DAG.getConstant(~SignBit, VT));
3943 // fold (bitconvert (fcopysign cst, x)) ->
3944 // (or (and (bitconvert x), sign), (and cst, (not sign)))
3945 // Note that we don't handle (copysign x, cst) because this can always be
3946 // folded to an fneg or fabs.
3947 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
3948 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
3949 VT.isInteger() && !VT.isVector()) {
3950 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
3951 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
3952 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) {
3953 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
3954 IntXVT, N0.getOperand(1));
3955 AddToWorkList(X.getNode());
3957 // If X has a different width than the result/lhs, sext it or truncate it.
3958 unsigned VTWidth = VT.getSizeInBits();
3959 if (OrigXWidth < VTWidth) {
3960 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
3961 AddToWorkList(X.getNode());
3962 } else if (OrigXWidth > VTWidth) {
3963 // To get the sign bit in the right place, we have to shift it right
3964 // before truncating.
3965 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
3966 X.getValueType(), X,
3967 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
3968 AddToWorkList(X.getNode());
3969 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
3970 AddToWorkList(X.getNode());
3973 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
3974 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
3975 X, DAG.getConstant(SignBit, VT));
3976 AddToWorkList(X.getNode());
3978 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
3979 VT, N0.getOperand(0));
3980 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
3981 Cst, DAG.getConstant(~SignBit, VT));
3982 AddToWorkList(Cst.getNode());
3984 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
3988 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
3989 if (N0.getOpcode() == ISD::BUILD_PAIR) {
3990 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
3991 if (CombineLD.getNode())
3998 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
3999 EVT VT = N->getValueType(0);
4000 return CombineConsecutiveLoads(N, VT);
4003 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
4004 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
4005 /// destination element value type.
4006 SDValue DAGCombiner::
4007 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
4008 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
4010 // If this is already the right type, we're done.
4011 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
4013 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
4014 unsigned DstBitSize = DstEltVT.getSizeInBits();
4016 // If this is a conversion of N elements of one type to N elements of another
4017 // type, convert each element. This handles FP<->INT cases.
4018 if (SrcBitSize == DstBitSize) {
4019 SmallVector<SDValue, 8> Ops;
4020 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
4021 SDValue Op = BV->getOperand(i);
4022 // If the vector element type is not legal, the BUILD_VECTOR operands
4023 // are promoted and implicitly truncated. Make that explicit here.
4024 if (Op.getValueType() != SrcEltVT)
4025 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
4026 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(),
4028 AddToWorkList(Ops.back().getNode());
4030 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
4031 BV->getValueType(0).getVectorNumElements());
4032 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4033 &Ops[0], Ops.size());
4036 // Otherwise, we're growing or shrinking the elements. To avoid having to
4037 // handle annoying details of growing/shrinking FP values, we convert them to
4039 if (SrcEltVT.isFloatingPoint()) {
4040 // Convert the input float vector to a int vector where the elements are the
4042 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
4043 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
4044 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
4048 // Now we know the input is an integer vector. If the output is a FP type,
4049 // convert to integer first, then to FP of the right size.
4050 if (DstEltVT.isFloatingPoint()) {
4051 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
4052 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
4053 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
4055 // Next, convert to FP elements of the same size.
4056 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
4059 // Okay, we know the src/dst types are both integers of differing types.
4060 // Handling growing first.
4061 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
4062 if (SrcBitSize < DstBitSize) {
4063 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
4065 SmallVector<SDValue, 8> Ops;
4066 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
4067 i += NumInputsPerOutput) {
4068 bool isLE = TLI.isLittleEndian();
4069 APInt NewBits = APInt(DstBitSize, 0);
4070 bool EltIsUndef = true;
4071 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
4072 // Shift the previously computed bits over.
4073 NewBits <<= SrcBitSize;
4074 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
4075 if (Op.getOpcode() == ISD::UNDEF) continue;
4078 NewBits |= (APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).
4079 zextOrTrunc(SrcBitSize).zext(DstBitSize));
4083 Ops.push_back(DAG.getUNDEF(DstEltVT));
4085 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
4088 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
4089 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4090 &Ops[0], Ops.size());
4093 // Finally, this must be the case where we are shrinking elements: each input
4094 // turns into multiple outputs.
4095 bool isS2V = ISD::isScalarToVector(BV);
4096 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
4097 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
4098 NumOutputsPerInput*BV->getNumOperands());
4099 SmallVector<SDValue, 8> Ops;
4101 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
4102 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
4103 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
4104 Ops.push_back(DAG.getUNDEF(DstEltVT));
4108 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))->
4109 getAPIntValue()).zextOrTrunc(SrcBitSize);
4111 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
4112 APInt ThisVal = APInt(OpVal).trunc(DstBitSize);
4113 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
4114 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal)
4115 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
4116 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
4118 OpVal = OpVal.lshr(DstBitSize);
4121 // For big endian targets, swap the order of the pieces of each element.
4122 if (TLI.isBigEndian())
4123 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
4126 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4127 &Ops[0], Ops.size());
4130 SDValue DAGCombiner::visitFADD(SDNode *N) {
4131 SDValue N0 = N->getOperand(0);
4132 SDValue N1 = N->getOperand(1);
4133 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4134 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4135 EVT VT = N->getValueType(0);
4138 if (VT.isVector()) {
4139 SDValue FoldedVOp = SimplifyVBinOp(N);
4140 if (FoldedVOp.getNode()) return FoldedVOp;
4143 // fold (fadd c1, c2) -> (fadd c1, c2)
4144 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4145 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
4146 // canonicalize constant to RHS
4147 if (N0CFP && !N1CFP)
4148 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
4149 // fold (fadd A, 0) -> A
4150 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4152 // fold (fadd A, (fneg B)) -> (fsub A, B)
4153 if (isNegatibleForFree(N1, LegalOperations) == 2)
4154 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
4155 GetNegatedExpression(N1, DAG, LegalOperations));
4156 // fold (fadd (fneg A), B) -> (fsub B, A)
4157 if (isNegatibleForFree(N0, LegalOperations) == 2)
4158 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
4159 GetNegatedExpression(N0, DAG, LegalOperations));
4161 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
4162 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
4163 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4164 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
4165 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
4166 N0.getOperand(1), N1));
4171 SDValue DAGCombiner::visitFSUB(SDNode *N) {
4172 SDValue N0 = N->getOperand(0);
4173 SDValue N1 = N->getOperand(1);
4174 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4175 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4176 EVT VT = N->getValueType(0);
4179 if (VT.isVector()) {
4180 SDValue FoldedVOp = SimplifyVBinOp(N);
4181 if (FoldedVOp.getNode()) return FoldedVOp;
4184 // fold (fsub c1, c2) -> c1-c2
4185 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4186 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
4187 // fold (fsub A, 0) -> A
4188 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4190 // fold (fsub 0, B) -> -B
4191 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
4192 if (isNegatibleForFree(N1, LegalOperations))
4193 return GetNegatedExpression(N1, DAG, LegalOperations);
4194 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4195 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
4197 // fold (fsub A, (fneg B)) -> (fadd A, B)
4198 if (isNegatibleForFree(N1, LegalOperations))
4199 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
4200 GetNegatedExpression(N1, DAG, LegalOperations));
4205 SDValue DAGCombiner::visitFMUL(SDNode *N) {
4206 SDValue N0 = N->getOperand(0);
4207 SDValue N1 = N->getOperand(1);
4208 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4209 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4210 EVT VT = N->getValueType(0);
4213 if (VT.isVector()) {
4214 SDValue FoldedVOp = SimplifyVBinOp(N);
4215 if (FoldedVOp.getNode()) return FoldedVOp;
4218 // fold (fmul c1, c2) -> c1*c2
4219 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4220 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
4221 // canonicalize constant to RHS
4222 if (N0CFP && !N1CFP)
4223 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
4224 // fold (fmul A, 0) -> 0
4225 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4227 // fold (fmul A, 0) -> 0, vector edition.
4228 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode()))
4230 // fold (fmul X, 2.0) -> (fadd X, X)
4231 if (N1CFP && N1CFP->isExactlyValue(+2.0))
4232 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
4233 // fold (fmul X, -1.0) -> (fneg X)
4234 if (N1CFP && N1CFP->isExactlyValue(-1.0))
4235 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4236 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
4238 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
4239 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4240 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4241 // Both can be negated for free, check to see if at least one is cheaper
4243 if (LHSNeg == 2 || RHSNeg == 2)
4244 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4245 GetNegatedExpression(N0, DAG, LegalOperations),
4246 GetNegatedExpression(N1, DAG, LegalOperations));
4250 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
4251 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
4252 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4253 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
4254 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4255 N0.getOperand(1), N1));
4260 SDValue DAGCombiner::visitFDIV(SDNode *N) {
4261 SDValue N0 = N->getOperand(0);
4262 SDValue N1 = N->getOperand(1);
4263 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4264 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4265 EVT VT = N->getValueType(0);
4268 if (VT.isVector()) {
4269 SDValue FoldedVOp = SimplifyVBinOp(N);
4270 if (FoldedVOp.getNode()) return FoldedVOp;
4273 // fold (fdiv c1, c2) -> c1/c2
4274 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4275 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
4278 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
4279 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4280 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4281 // Both can be negated for free, check to see if at least one is cheaper
4283 if (LHSNeg == 2 || RHSNeg == 2)
4284 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
4285 GetNegatedExpression(N0, DAG, LegalOperations),
4286 GetNegatedExpression(N1, DAG, LegalOperations));
4293 SDValue DAGCombiner::visitFREM(SDNode *N) {
4294 SDValue N0 = N->getOperand(0);
4295 SDValue N1 = N->getOperand(1);
4296 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4297 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4298 EVT VT = N->getValueType(0);
4300 // fold (frem c1, c2) -> fmod(c1,c2)
4301 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4302 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
4307 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
4308 SDValue N0 = N->getOperand(0);
4309 SDValue N1 = N->getOperand(1);
4310 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4311 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4312 EVT VT = N->getValueType(0);
4314 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
4315 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
4318 const APFloat& V = N1CFP->getValueAPF();
4319 // copysign(x, c1) -> fabs(x) iff ispos(c1)
4320 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
4321 if (!V.isNegative()) {
4322 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
4323 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4325 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4326 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
4327 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
4331 // copysign(fabs(x), y) -> copysign(x, y)
4332 // copysign(fneg(x), y) -> copysign(x, y)
4333 // copysign(copysign(x,z), y) -> copysign(x, y)
4334 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
4335 N0.getOpcode() == ISD::FCOPYSIGN)
4336 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4337 N0.getOperand(0), N1);
4339 // copysign(x, abs(y)) -> abs(x)
4340 if (N1.getOpcode() == ISD::FABS)
4341 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4343 // copysign(x, copysign(y,z)) -> copysign(x, z)
4344 if (N1.getOpcode() == ISD::FCOPYSIGN)
4345 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4346 N0, N1.getOperand(1));
4348 // copysign(x, fp_extend(y)) -> copysign(x, y)
4349 // copysign(x, fp_round(y)) -> copysign(x, y)
4350 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
4351 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4352 N0, N1.getOperand(0));
4357 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
4358 SDValue N0 = N->getOperand(0);
4359 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4360 EVT VT = N->getValueType(0);
4361 EVT OpVT = N0.getValueType();
4363 // fold (sint_to_fp c1) -> c1fp
4364 if (N0C && OpVT != MVT::ppcf128)
4365 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4367 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
4368 // but UINT_TO_FP is legal on this target, try to convert.
4369 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
4370 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
4371 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
4372 if (DAG.SignBitIsZero(N0))
4373 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4379 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
4380 SDValue N0 = N->getOperand(0);
4381 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4382 EVT VT = N->getValueType(0);
4383 EVT OpVT = N0.getValueType();
4385 // fold (uint_to_fp c1) -> c1fp
4386 if (N0C && OpVT != MVT::ppcf128)
4387 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4389 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
4390 // but SINT_TO_FP is legal on this target, try to convert.
4391 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
4392 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
4393 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
4394 if (DAG.SignBitIsZero(N0))
4395 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4401 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
4402 SDValue N0 = N->getOperand(0);
4403 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4404 EVT VT = N->getValueType(0);
4406 // fold (fp_to_sint c1fp) -> c1
4408 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
4413 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
4414 SDValue N0 = N->getOperand(0);
4415 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4416 EVT VT = N->getValueType(0);
4418 // fold (fp_to_uint c1fp) -> c1
4419 if (N0CFP && VT != MVT::ppcf128)
4420 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
4425 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
4426 SDValue N0 = N->getOperand(0);
4427 SDValue N1 = N->getOperand(1);
4428 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4429 EVT VT = N->getValueType(0);
4431 // fold (fp_round c1fp) -> c1fp
4432 if (N0CFP && N0.getValueType() != MVT::ppcf128)
4433 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
4435 // fold (fp_round (fp_extend x)) -> x
4436 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
4437 return N0.getOperand(0);
4439 // fold (fp_round (fp_round x)) -> (fp_round x)
4440 if (N0.getOpcode() == ISD::FP_ROUND) {
4441 // This is a value preserving truncation if both round's are.
4442 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
4443 N0.getNode()->getConstantOperandVal(1) == 1;
4444 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
4445 DAG.getIntPtrConstant(IsTrunc));
4448 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
4449 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
4450 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
4451 N0.getOperand(0), N1);
4452 AddToWorkList(Tmp.getNode());
4453 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4454 Tmp, N0.getOperand(1));
4460 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
4461 SDValue N0 = N->getOperand(0);
4462 EVT VT = N->getValueType(0);
4463 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4464 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4466 // fold (fp_round_inreg c1fp) -> c1fp
4467 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) {
4468 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
4469 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
4475 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
4476 SDValue N0 = N->getOperand(0);
4477 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4478 EVT VT = N->getValueType(0);
4480 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
4481 if (N->hasOneUse() &&
4482 N->use_begin()->getOpcode() == ISD::FP_ROUND)
4485 // fold (fp_extend c1fp) -> c1fp
4486 if (N0CFP && VT != MVT::ppcf128)
4487 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
4489 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
4491 if (N0.getOpcode() == ISD::FP_ROUND
4492 && N0.getNode()->getConstantOperandVal(1) == 1) {
4493 SDValue In = N0.getOperand(0);
4494 if (In.getValueType() == VT) return In;
4495 if (VT.bitsLT(In.getValueType()))
4496 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
4497 In, N0.getOperand(1));
4498 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
4501 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
4502 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
4503 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4504 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4505 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4506 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4508 LN0->getBasePtr(), LN0->getSrcValue(),
4509 LN0->getSrcValueOffset(),
4511 LN0->isVolatile(), LN0->isNonTemporal(),
4512 LN0->getAlignment());
4513 CombineTo(N, ExtLoad);
4514 CombineTo(N0.getNode(),
4515 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
4516 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
4517 ExtLoad.getValue(1));
4518 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4524 SDValue DAGCombiner::visitFNEG(SDNode *N) {
4525 SDValue N0 = N->getOperand(0);
4526 EVT VT = N->getValueType(0);
4528 if (isNegatibleForFree(N0, LegalOperations))
4529 return GetNegatedExpression(N0, DAG, LegalOperations);
4531 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
4532 // constant pool values.
4533 if (N0.getOpcode() == ISD::BIT_CONVERT &&
4535 N0.getNode()->hasOneUse() &&
4536 N0.getOperand(0).getValueType().isInteger()) {
4537 SDValue Int = N0.getOperand(0);
4538 EVT IntVT = Int.getValueType();
4539 if (IntVT.isInteger() && !IntVT.isVector()) {
4540 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
4541 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
4542 AddToWorkList(Int.getNode());
4543 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4551 SDValue DAGCombiner::visitFABS(SDNode *N) {
4552 SDValue N0 = N->getOperand(0);
4553 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4554 EVT VT = N->getValueType(0);
4556 // fold (fabs c1) -> fabs(c1)
4557 if (N0CFP && VT != MVT::ppcf128)
4558 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4559 // fold (fabs (fabs x)) -> (fabs x)
4560 if (N0.getOpcode() == ISD::FABS)
4561 return N->getOperand(0);
4562 // fold (fabs (fneg x)) -> (fabs x)
4563 // fold (fabs (fcopysign x, y)) -> (fabs x)
4564 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
4565 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
4567 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
4568 // constant pool values.
4569 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
4570 N0.getOperand(0).getValueType().isInteger() &&
4571 !N0.getOperand(0).getValueType().isVector()) {
4572 SDValue Int = N0.getOperand(0);
4573 EVT IntVT = Int.getValueType();
4574 if (IntVT.isInteger() && !IntVT.isVector()) {
4575 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
4576 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
4577 AddToWorkList(Int.getNode());
4578 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4579 N->getValueType(0), Int);
4586 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
4587 SDValue Chain = N->getOperand(0);
4588 SDValue N1 = N->getOperand(1);
4589 SDValue N2 = N->getOperand(2);
4591 // If N is a constant we could fold this into a fallthrough or unconditional
4592 // branch. However that doesn't happen very often in normal code, because
4593 // Instcombine/SimplifyCFG should have handled the available opportunities.
4594 // If we did this folding here, it would be necessary to update the
4595 // MachineBasicBlock CFG, which is awkward.
4597 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
4599 if (N1.getOpcode() == ISD::SETCC &&
4600 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
4601 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
4602 Chain, N1.getOperand(2),
4603 N1.getOperand(0), N1.getOperand(1), N2);
4607 if (N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) {
4608 // Look pass truncate.
4609 Trunc = N1.getNode();
4610 N1 = N1.getOperand(0);
4613 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) {
4614 // Match this pattern so that we can generate simpler code:
4617 // %b = and i32 %a, 2
4618 // %c = srl i32 %b, 1
4619 // brcond i32 %c ...
4624 // %b = and i32 %a, 2
4625 // %c = setcc eq %b, 0
4628 // This applies only when the AND constant value has one bit set and the
4629 // SRL constant is equal to the log2 of the AND constant. The back-end is
4630 // smart enough to convert the result into a TEST/JMP sequence.
4631 SDValue Op0 = N1.getOperand(0);
4632 SDValue Op1 = N1.getOperand(1);
4634 if (Op0.getOpcode() == ISD::AND &&
4635 Op1.getOpcode() == ISD::Constant) {
4636 SDValue AndOp1 = Op0.getOperand(1);
4638 if (AndOp1.getOpcode() == ISD::Constant) {
4639 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
4641 if (AndConst.isPowerOf2() &&
4642 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
4644 DAG.getSetCC(N->getDebugLoc(),
4645 TLI.getSetCCResultType(Op0.getValueType()),
4646 Op0, DAG.getConstant(0, Op0.getValueType()),
4649 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
4650 MVT::Other, Chain, SetCC, N2);
4651 // Don't add the new BRCond into the worklist or else SimplifySelectCC
4652 // will convert it back to (X & C1) >> C2.
4653 CombineTo(N, NewBRCond, false);
4654 // Truncate is dead.
4656 removeFromWorkList(Trunc);
4657 DAG.DeleteNode(Trunc);
4659 // Replace the uses of SRL with SETCC
4660 WorkListRemover DeadNodes(*this);
4661 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
4662 removeFromWorkList(N1.getNode());
4663 DAG.DeleteNode(N1.getNode());
4664 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4670 // Transform br(xor(x, y)) -> br(x != y)
4671 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
4672 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
4673 SDNode *TheXor = N1.getNode();
4674 SDValue Op0 = TheXor->getOperand(0);
4675 SDValue Op1 = TheXor->getOperand(1);
4676 if (Op0.getOpcode() == Op1.getOpcode()) {
4677 // Avoid missing important xor optimizations.
4678 SDValue Tmp = visitXOR(TheXor);
4679 if (Tmp.getNode()) {
4680 DEBUG(dbgs() << "\nReplacing.8 ";
4682 dbgs() << "\nWith: ";
4683 Tmp.getNode()->dump(&DAG);
4685 WorkListRemover DeadNodes(*this);
4686 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes);
4687 removeFromWorkList(TheXor);
4688 DAG.DeleteNode(TheXor);
4689 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
4690 MVT::Other, Chain, Tmp, N2);
4694 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
4696 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
4697 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
4698 Op0.getOpcode() == ISD::XOR) {
4699 TheXor = Op0.getNode();
4703 EVT SetCCVT = N1.getValueType();
4705 SetCCVT = TLI.getSetCCResultType(SetCCVT);
4706 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
4709 Equal ? ISD::SETEQ : ISD::SETNE);
4710 // Replace the uses of XOR with SETCC
4711 WorkListRemover DeadNodes(*this);
4712 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
4713 removeFromWorkList(N1.getNode());
4714 DAG.DeleteNode(N1.getNode());
4715 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
4716 MVT::Other, Chain, SetCC, N2);
4723 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
4725 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
4726 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
4727 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
4729 // If N is a constant we could fold this into a fallthrough or unconditional
4730 // branch. However that doesn't happen very often in normal code, because
4731 // Instcombine/SimplifyCFG should have handled the available opportunities.
4732 // If we did this folding here, it would be necessary to update the
4733 // MachineBasicBlock CFG, which is awkward.
4735 // Use SimplifySetCC to simplify SETCC's.
4736 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
4737 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
4739 if (Simp.getNode()) AddToWorkList(Simp.getNode());
4741 // fold to a simpler setcc
4742 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
4743 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
4744 N->getOperand(0), Simp.getOperand(2),
4745 Simp.getOperand(0), Simp.getOperand(1),
4751 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
4752 /// pre-indexed load / store when the base pointer is an add or subtract
4753 /// and it has other uses besides the load / store. After the
4754 /// transformation, the new indexed load / store has effectively folded
4755 /// the add / subtract in and all of its other uses are redirected to the
4756 /// new load / store.
4757 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
4758 if (!LegalOperations)
4764 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4765 if (LD->isIndexed())
4767 VT = LD->getMemoryVT();
4768 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
4769 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
4771 Ptr = LD->getBasePtr();
4772 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4773 if (ST->isIndexed())
4775 VT = ST->getMemoryVT();
4776 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
4777 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
4779 Ptr = ST->getBasePtr();
4785 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
4786 // out. There is no reason to make this a preinc/predec.
4787 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
4788 Ptr.getNode()->hasOneUse())
4791 // Ask the target to do addressing mode selection.
4794 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4795 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
4797 // Don't create a indexed load / store with zero offset.
4798 if (isa<ConstantSDNode>(Offset) &&
4799 cast<ConstantSDNode>(Offset)->isNullValue())
4802 // Try turning it into a pre-indexed load / store except when:
4803 // 1) The new base ptr is a frame index.
4804 // 2) If N is a store and the new base ptr is either the same as or is a
4805 // predecessor of the value being stored.
4806 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
4807 // that would create a cycle.
4808 // 4) All uses are load / store ops that use it as old base ptr.
4810 // Check #1. Preinc'ing a frame index would require copying the stack pointer
4811 // (plus the implicit offset) to a register to preinc anyway.
4812 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
4817 SDValue Val = cast<StoreSDNode>(N)->getValue();
4818 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
4822 // Now check for #3 and #4.
4823 bool RealUse = false;
4824 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
4825 E = Ptr.getNode()->use_end(); I != E; ++I) {
4829 if (Use->isPredecessorOf(N))
4832 if (!((Use->getOpcode() == ISD::LOAD &&
4833 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
4834 (Use->getOpcode() == ISD::STORE &&
4835 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
4844 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
4845 BasePtr, Offset, AM);
4847 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
4848 BasePtr, Offset, AM);
4851 DEBUG(dbgs() << "\nReplacing.4 ";
4853 dbgs() << "\nWith: ";
4854 Result.getNode()->dump(&DAG);
4856 WorkListRemover DeadNodes(*this);
4858 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
4860 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
4863 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
4867 // Finally, since the node is now dead, remove it from the graph.
4870 // Replace the uses of Ptr with uses of the updated base value.
4871 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
4873 removeFromWorkList(Ptr.getNode());
4874 DAG.DeleteNode(Ptr.getNode());
4879 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
4880 /// add / sub of the base pointer node into a post-indexed load / store.
4881 /// The transformation folded the add / subtract into the new indexed
4882 /// load / store effectively and all of its uses are redirected to the
4883 /// new load / store.
4884 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
4885 if (!LegalOperations)
4891 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4892 if (LD->isIndexed())
4894 VT = LD->getMemoryVT();
4895 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
4896 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
4898 Ptr = LD->getBasePtr();
4899 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4900 if (ST->isIndexed())
4902 VT = ST->getMemoryVT();
4903 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
4904 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
4906 Ptr = ST->getBasePtr();
4912 if (Ptr.getNode()->hasOneUse())
4915 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
4916 E = Ptr.getNode()->use_end(); I != E; ++I) {
4919 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
4924 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4925 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
4926 if (Ptr == Offset && Op->getOpcode() == ISD::ADD)
4927 std::swap(BasePtr, Offset);
4930 // Don't create a indexed load / store with zero offset.
4931 if (isa<ConstantSDNode>(Offset) &&
4932 cast<ConstantSDNode>(Offset)->isNullValue())
4935 // Try turning it into a post-indexed load / store except when
4936 // 1) All uses are load / store ops that use it as base ptr.
4937 // 2) Op must be independent of N, i.e. Op is neither a predecessor
4938 // nor a successor of N. Otherwise, if Op is folded that would
4941 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
4945 bool TryNext = false;
4946 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
4947 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
4949 if (Use == Ptr.getNode())
4952 // If all the uses are load / store addresses, then don't do the
4954 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
4955 bool RealUse = false;
4956 for (SDNode::use_iterator III = Use->use_begin(),
4957 EEE = Use->use_end(); III != EEE; ++III) {
4958 SDNode *UseUse = *III;
4959 if (!((UseUse->getOpcode() == ISD::LOAD &&
4960 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) ||
4961 (UseUse->getOpcode() == ISD::STORE &&
4962 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use)))
4977 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
4978 SDValue Result = isLoad
4979 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
4980 BasePtr, Offset, AM)
4981 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
4982 BasePtr, Offset, AM);
4985 DEBUG(dbgs() << "\nReplacing.5 ";
4987 dbgs() << "\nWith: ";
4988 Result.getNode()->dump(&DAG);
4990 WorkListRemover DeadNodes(*this);
4992 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
4994 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
4997 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
5001 // Finally, since the node is now dead, remove it from the graph.
5004 // Replace the uses of Use with uses of the updated base value.
5005 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
5006 Result.getValue(isLoad ? 1 : 0),
5008 removeFromWorkList(Op);
5018 SDValue DAGCombiner::visitLOAD(SDNode *N) {
5019 LoadSDNode *LD = cast<LoadSDNode>(N);
5020 SDValue Chain = LD->getChain();
5021 SDValue Ptr = LD->getBasePtr();
5023 // Try to infer better alignment information than the load already has.
5024 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
5025 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
5026 if (Align > LD->getAlignment())
5027 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
5028 LD->getValueType(0),
5029 Chain, Ptr, LD->getSrcValue(),
5030 LD->getSrcValueOffset(), LD->getMemoryVT(),
5031 LD->isVolatile(), LD->isNonTemporal(), Align);
5035 // If load is not volatile and there are no uses of the loaded value (and
5036 // the updated indexed value in case of indexed loads), change uses of the
5037 // chain value into uses of the chain input (i.e. delete the dead load).
5038 if (!LD->isVolatile()) {
5039 if (N->getValueType(1) == MVT::Other) {
5041 if (N->hasNUsesOfValue(0, 0)) {
5042 // It's not safe to use the two value CombineTo variant here. e.g.
5043 // v1, chain2 = load chain1, loc
5044 // v2, chain3 = load chain2, loc
5046 // Now we replace use of chain2 with chain1. This makes the second load
5047 // isomorphic to the one we are deleting, and thus makes this load live.
5048 DEBUG(dbgs() << "\nReplacing.6 ";
5050 dbgs() << "\nWith chain: ";
5051 Chain.getNode()->dump(&DAG);
5053 WorkListRemover DeadNodes(*this);
5054 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
5056 if (N->use_empty()) {
5057 removeFromWorkList(N);
5061 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5065 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
5066 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
5067 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
5068 DEBUG(dbgs() << "\nReplacing.7 ";
5070 dbgs() << "\nWith: ";
5071 Undef.getNode()->dump(&DAG);
5072 dbgs() << " and 2 other values\n");
5073 WorkListRemover DeadNodes(*this);
5074 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
5075 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
5076 DAG.getUNDEF(N->getValueType(1)),
5078 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
5079 removeFromWorkList(N);
5081 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5086 // If this load is directly stored, replace the load value with the stored
5088 // TODO: Handle store large -> read small portion.
5089 // TODO: Handle TRUNCSTORE/LOADEXT
5090 if (LD->getExtensionType() == ISD::NON_EXTLOAD &&
5091 !LD->isVolatile()) {
5092 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
5093 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
5094 if (PrevST->getBasePtr() == Ptr &&
5095 PrevST->getValue().getValueType() == N->getValueType(0))
5096 return CombineTo(N, Chain.getOperand(1), Chain);
5101 // Walk up chain skipping non-aliasing memory nodes.
5102 SDValue BetterChain = FindBetterChain(N, Chain);
5104 // If there is a better chain.
5105 if (Chain != BetterChain) {
5108 // Replace the chain to void dependency.
5109 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
5110 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
5112 LD->getSrcValue(), LD->getSrcValueOffset(),
5113 LD->isVolatile(), LD->isNonTemporal(),
5114 LD->getAlignment());
5116 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
5117 LD->getValueType(0),
5118 BetterChain, Ptr, LD->getSrcValue(),
5119 LD->getSrcValueOffset(),
5122 LD->isNonTemporal(),
5123 LD->getAlignment());
5126 // Create token factor to keep old chain connected.
5127 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
5128 MVT::Other, Chain, ReplLoad.getValue(1));
5130 // Make sure the new and old chains are cleaned up.
5131 AddToWorkList(Token.getNode());
5133 // Replace uses with load result and token factor. Don't add users
5135 return CombineTo(N, ReplLoad.getValue(0), Token, false);
5139 // Try transforming N to an indexed load.
5140 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
5141 return SDValue(N, 0);
5147 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
5148 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
5149 /// of the loaded bits, try narrowing the load and store if it would end up
5150 /// being a win for performance or code size.
5151 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
5152 StoreSDNode *ST = cast<StoreSDNode>(N);
5153 if (ST->isVolatile())
5156 SDValue Chain = ST->getChain();
5157 SDValue Value = ST->getValue();
5158 SDValue Ptr = ST->getBasePtr();
5159 EVT VT = Value.getValueType();
5161 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
5164 unsigned Opc = Value.getOpcode();
5165 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
5166 Value.getOperand(1).getOpcode() != ISD::Constant)
5169 SDValue N0 = Value.getOperand(0);
5170 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) {
5171 LoadSDNode *LD = cast<LoadSDNode>(N0);
5172 if (LD->getBasePtr() != Ptr)
5175 // Find the type to narrow it the load / op / store to.
5176 SDValue N1 = Value.getOperand(1);
5177 unsigned BitWidth = N1.getValueSizeInBits();
5178 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
5179 if (Opc == ISD::AND)
5180 Imm ^= APInt::getAllOnesValue(BitWidth);
5181 if (Imm == 0 || Imm.isAllOnesValue())
5183 unsigned ShAmt = Imm.countTrailingZeros();
5184 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
5185 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
5186 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
5187 while (NewBW < BitWidth &&
5188 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
5189 TLI.isNarrowingProfitable(VT, NewVT))) {
5190 NewBW = NextPowerOf2(NewBW);
5191 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
5193 if (NewBW >= BitWidth)
5196 // If the lsb changed does not start at the type bitwidth boundary,
5197 // start at the previous one.
5199 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
5200 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
5201 if ((Imm & Mask) == Imm) {
5202 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
5203 if (Opc == ISD::AND)
5204 NewImm ^= APInt::getAllOnesValue(NewBW);
5205 uint64_t PtrOff = ShAmt / 8;
5206 // For big endian targets, we need to adjust the offset to the pointer to
5207 // load the correct bytes.
5208 if (TLI.isBigEndian())
5209 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
5211 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
5213 TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForEVT(*DAG.getContext())))
5216 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
5217 Ptr.getValueType(), Ptr,
5218 DAG.getConstant(PtrOff, Ptr.getValueType()));
5219 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
5220 LD->getChain(), NewPtr,
5221 LD->getSrcValue(), LD->getSrcValueOffset(),
5222 LD->isVolatile(), LD->isNonTemporal(),
5224 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
5225 DAG.getConstant(NewImm, NewVT));
5226 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
5228 ST->getSrcValue(), ST->getSrcValueOffset(),
5229 false, false, NewAlign);
5231 AddToWorkList(NewPtr.getNode());
5232 AddToWorkList(NewLD.getNode());
5233 AddToWorkList(NewVal.getNode());
5234 WorkListRemover DeadNodes(*this);
5235 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1),
5245 SDValue DAGCombiner::visitSTORE(SDNode *N) {
5246 StoreSDNode *ST = cast<StoreSDNode>(N);
5247 SDValue Chain = ST->getChain();
5248 SDValue Value = ST->getValue();
5249 SDValue Ptr = ST->getBasePtr();
5251 // Try to infer better alignment information than the store already has.
5252 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
5253 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
5254 if (Align > ST->getAlignment())
5255 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
5256 Ptr, ST->getSrcValue(),
5257 ST->getSrcValueOffset(), ST->getMemoryVT(),
5258 ST->isVolatile(), ST->isNonTemporal(), Align);
5262 // If this is a store of a bit convert, store the input value if the
5263 // resultant store does not need a higher alignment than the original.
5264 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
5265 ST->isUnindexed()) {
5266 unsigned OrigAlign = ST->getAlignment();
5267 EVT SVT = Value.getOperand(0).getValueType();
5268 unsigned Align = TLI.getTargetData()->
5269 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
5270 if (Align <= OrigAlign &&
5271 ((!LegalOperations && !ST->isVolatile()) ||
5272 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
5273 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
5274 Ptr, ST->getSrcValue(),
5275 ST->getSrcValueOffset(), ST->isVolatile(),
5276 ST->isNonTemporal(), OrigAlign);
5279 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
5280 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
5281 // NOTE: If the original store is volatile, this transform must not increase
5282 // the number of stores. For example, on x86-32 an f64 can be stored in one
5283 // processor operation but an i64 (which is not legal) requires two. So the
5284 // transform should not be done in this case.
5285 if (Value.getOpcode() != ISD::TargetConstantFP) {
5287 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
5288 default: llvm_unreachable("Unknown FP type");
5289 case MVT::f80: // We don't do this for these yet.
5294 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations &&
5295 !ST->isVolatile()) ||
5296 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
5297 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
5298 bitcastToAPInt().getZExtValue(), MVT::i32);
5299 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
5300 Ptr, ST->getSrcValue(),
5301 ST->getSrcValueOffset(), ST->isVolatile(),
5302 ST->isNonTemporal(), ST->getAlignment());
5306 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations &&
5307 !ST->isVolatile()) ||
5308 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
5309 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
5310 getZExtValue(), MVT::i64);
5311 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
5312 Ptr, ST->getSrcValue(),
5313 ST->getSrcValueOffset(), ST->isVolatile(),
5314 ST->isNonTemporal(), ST->getAlignment());
5315 } else if (!ST->isVolatile() &&
5316 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
5317 // Many FP stores are not made apparent until after legalize, e.g. for
5318 // argument passing. Since this is so common, custom legalize the
5319 // 64-bit integer store into two 32-bit stores.
5320 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
5321 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
5322 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
5323 if (TLI.isBigEndian()) std::swap(Lo, Hi);
5325 int SVOffset = ST->getSrcValueOffset();
5326 unsigned Alignment = ST->getAlignment();
5327 bool isVolatile = ST->isVolatile();
5328 bool isNonTemporal = ST->isNonTemporal();
5330 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
5331 Ptr, ST->getSrcValue(),
5332 ST->getSrcValueOffset(),
5333 isVolatile, isNonTemporal,
5334 ST->getAlignment());
5335 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
5336 DAG.getConstant(4, Ptr.getValueType()));
5338 Alignment = MinAlign(Alignment, 4U);
5339 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
5340 Ptr, ST->getSrcValue(),
5341 SVOffset, isVolatile, isNonTemporal,
5343 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
5353 // Walk up chain skipping non-aliasing memory nodes.
5354 SDValue BetterChain = FindBetterChain(N, Chain);
5356 // If there is a better chain.
5357 if (Chain != BetterChain) {
5360 // Replace the chain to avoid dependency.
5361 if (ST->isTruncatingStore()) {
5362 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
5363 ST->getSrcValue(),ST->getSrcValueOffset(),
5364 ST->getMemoryVT(), ST->isVolatile(),
5365 ST->isNonTemporal(), ST->getAlignment());
5367 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
5368 ST->getSrcValue(), ST->getSrcValueOffset(),
5369 ST->isVolatile(), ST->isNonTemporal(),
5370 ST->getAlignment());
5373 // Create token to keep both nodes around.
5374 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
5375 MVT::Other, Chain, ReplStore);
5377 // Make sure the new and old chains are cleaned up.
5378 AddToWorkList(Token.getNode());
5380 // Don't add users to work list.
5381 return CombineTo(N, Token, false);
5385 // Try transforming N to an indexed store.
5386 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
5387 return SDValue(N, 0);
5389 // FIXME: is there such a thing as a truncating indexed store?
5390 if (ST->isTruncatingStore() && ST->isUnindexed() &&
5391 Value.getValueType().isInteger()) {
5392 // See if we can simplify the input to this truncstore with knowledge that
5393 // only the low bits are being used. For example:
5394 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
5396 GetDemandedBits(Value,
5397 APInt::getLowBitsSet(Value.getValueSizeInBits(),
5398 ST->getMemoryVT().getSizeInBits()));
5399 AddToWorkList(Value.getNode());
5400 if (Shorter.getNode())
5401 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
5402 Ptr, ST->getSrcValue(),
5403 ST->getSrcValueOffset(), ST->getMemoryVT(),
5404 ST->isVolatile(), ST->isNonTemporal(),
5405 ST->getAlignment());
5407 // Otherwise, see if we can simplify the operation with
5408 // SimplifyDemandedBits, which only works if the value has a single use.
5409 if (SimplifyDemandedBits(Value,
5410 APInt::getLowBitsSet(
5411 Value.getValueType().getScalarType().getSizeInBits(),
5412 ST->getMemoryVT().getSizeInBits())))
5413 return SDValue(N, 0);
5416 // If this is a load followed by a store to the same location, then the store
5418 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
5419 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
5420 ST->isUnindexed() && !ST->isVolatile() &&
5421 // There can't be any side effects between the load and store, such as
5423 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
5424 // The store is dead, remove it.
5429 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
5430 // truncating store. We can do this even if this is already a truncstore.
5431 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
5432 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
5433 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
5434 ST->getMemoryVT())) {
5435 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
5436 Ptr, ST->getSrcValue(),
5437 ST->getSrcValueOffset(), ST->getMemoryVT(),
5438 ST->isVolatile(), ST->isNonTemporal(),
5439 ST->getAlignment());
5442 return ReduceLoadOpStoreWidth(N);
5445 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
5446 SDValue InVec = N->getOperand(0);
5447 SDValue InVal = N->getOperand(1);
5448 SDValue EltNo = N->getOperand(2);
5450 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
5451 // vector with the inserted element.
5452 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
5453 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5454 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
5455 InVec.getNode()->op_end());
5456 if (Elt < Ops.size())
5458 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5459 InVec.getValueType(), &Ops[0], Ops.size());
5461 // If the invec is an UNDEF and if EltNo is a constant, create a new
5462 // BUILD_VECTOR with undef elements and the inserted element.
5463 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF &&
5464 isa<ConstantSDNode>(EltNo)) {
5465 EVT VT = InVec.getValueType();
5466 EVT EltVT = VT.getVectorElementType();
5467 unsigned NElts = VT.getVectorNumElements();
5468 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT));
5470 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5471 if (Elt < Ops.size())
5473 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5474 InVec.getValueType(), &Ops[0], Ops.size());
5479 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
5480 // (vextract (scalar_to_vector val, 0) -> val
5481 SDValue InVec = N->getOperand(0);
5483 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5484 // Check if the result type doesn't match the inserted element type. A
5485 // SCALAR_TO_VECTOR may truncate the inserted element and the
5486 // EXTRACT_VECTOR_ELT may widen the extracted vector.
5487 EVT EltVT = InVec.getValueType().getVectorElementType();
5488 SDValue InOp = InVec.getOperand(0);
5489 EVT NVT = N->getValueType(0);
5490 if (InOp.getValueType() != NVT) {
5491 assert(InOp.getValueType().isInteger() && NVT.isInteger());
5492 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
5497 // Perform only after legalization to ensure build_vector / vector_shuffle
5498 // optimizations have already been done.
5499 if (!LegalOperations) return SDValue();
5501 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
5502 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
5503 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
5504 SDValue EltNo = N->getOperand(1);
5506 if (isa<ConstantSDNode>(EltNo)) {
5507 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5508 bool NewLoad = false;
5509 bool BCNumEltsChanged = false;
5510 EVT VT = InVec.getValueType();
5511 EVT ExtVT = VT.getVectorElementType();
5514 if (InVec.getOpcode() == ISD::BIT_CONVERT) {
5515 EVT BCVT = InVec.getOperand(0).getValueType();
5516 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
5518 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
5519 BCNumEltsChanged = true;
5520 InVec = InVec.getOperand(0);
5521 ExtVT = BCVT.getVectorElementType();
5525 LoadSDNode *LN0 = NULL;
5526 const ShuffleVectorSDNode *SVN = NULL;
5527 if (ISD::isNormalLoad(InVec.getNode())) {
5528 LN0 = cast<LoadSDNode>(InVec);
5529 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5530 InVec.getOperand(0).getValueType() == ExtVT &&
5531 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
5532 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
5533 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
5534 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
5536 // (load $addr+1*size)
5538 // If the bit convert changed the number of elements, it is unsafe
5539 // to examine the mask.
5540 if (BCNumEltsChanged)
5543 // Select the input vector, guarding against out of range extract vector.
5544 unsigned NumElems = VT.getVectorNumElements();
5545 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt);
5546 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
5548 if (InVec.getOpcode() == ISD::BIT_CONVERT)
5549 InVec = InVec.getOperand(0);
5550 if (ISD::isNormalLoad(InVec.getNode())) {
5551 LN0 = cast<LoadSDNode>(InVec);
5552 Elt = (Idx < (int)NumElems) ? Idx : Idx - NumElems;
5556 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile())
5559 unsigned Align = LN0->getAlignment();
5561 // Check the resultant load doesn't need a higher alignment than the
5564 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
5566 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
5572 SDValue NewPtr = LN0->getBasePtr();
5574 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8;
5575 EVT PtrType = NewPtr.getValueType();
5576 if (TLI.isBigEndian())
5577 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
5578 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
5579 DAG.getConstant(PtrOff, PtrType));
5582 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
5583 LN0->getSrcValue(), LN0->getSrcValueOffset(),
5584 LN0->isVolatile(), LN0->isNonTemporal(), Align);
5590 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
5591 unsigned NumInScalars = N->getNumOperands();
5592 EVT VT = N->getValueType(0);
5594 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
5595 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
5596 // at most two distinct vectors, turn this into a shuffle node.
5597 SDValue VecIn1, VecIn2;
5598 for (unsigned i = 0; i != NumInScalars; ++i) {
5599 // Ignore undef inputs.
5600 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5602 // If this input is something other than a EXTRACT_VECTOR_ELT with a
5603 // constant index, bail out.
5604 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5605 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
5606 VecIn1 = VecIn2 = SDValue(0, 0);
5610 // If the input vector type disagrees with the result of the build_vector,
5611 // we can't make a shuffle.
5612 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
5613 if (ExtractedFromVec.getValueType() != VT) {
5614 VecIn1 = VecIn2 = SDValue(0, 0);
5618 // Otherwise, remember this. We allow up to two distinct input vectors.
5619 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
5622 if (VecIn1.getNode() == 0) {
5623 VecIn1 = ExtractedFromVec;
5624 } else if (VecIn2.getNode() == 0) {
5625 VecIn2 = ExtractedFromVec;
5628 VecIn1 = VecIn2 = SDValue(0, 0);
5633 // If everything is good, we can make a shuffle operation.
5634 if (VecIn1.getNode()) {
5635 SmallVector<int, 8> Mask;
5636 for (unsigned i = 0; i != NumInScalars; ++i) {
5637 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
5642 // If extracting from the first vector, just use the index directly.
5643 SDValue Extract = N->getOperand(i);
5644 SDValue ExtVal = Extract.getOperand(1);
5645 if (Extract.getOperand(0) == VecIn1) {
5646 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
5647 if (ExtIndex > VT.getVectorNumElements())
5650 Mask.push_back(ExtIndex);
5654 // Otherwise, use InIdx + VecSize
5655 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
5656 Mask.push_back(Idx+NumInScalars);
5659 // Add count and size info.
5660 if (!TLI.isTypeLegal(VT) && LegalTypes)
5663 // Return the new VECTOR_SHUFFLE node.
5666 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5667 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
5673 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
5674 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
5675 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
5676 // inputs come from at most two distinct vectors, turn this into a shuffle
5679 // If we only have one input vector, we don't need to do any concatenation.
5680 if (N->getNumOperands() == 1)
5681 return N->getOperand(0);
5686 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
5689 EVT VT = N->getValueType(0);
5690 unsigned NumElts = VT.getVectorNumElements();
5692 SDValue N0 = N->getOperand(0);
5694 assert(N0.getValueType().getVectorNumElements() == NumElts &&
5695 "Vector shuffle must be normalized in DAG");
5697 // FIXME: implement canonicalizations from DAG.getVectorShuffle()
5699 // If it is a splat, check if the argument vector is a build_vector with
5700 // all scalar elements the same.
5701 if (cast<ShuffleVectorSDNode>(N)->isSplat()) {
5702 SDNode *V = N0.getNode();
5705 // If this is a bit convert that changes the element type of the vector but
5706 // not the number of vector elements, look through it. Be careful not to
5707 // look though conversions that change things like v4f32 to v2f64.
5708 if (V->getOpcode() == ISD::BIT_CONVERT) {
5709 SDValue ConvInput = V->getOperand(0);
5710 if (ConvInput.getValueType().isVector() &&
5711 ConvInput.getValueType().getVectorNumElements() == NumElts)
5712 V = ConvInput.getNode();
5715 if (V->getOpcode() == ISD::BUILD_VECTOR) {
5716 unsigned NumElems = V->getNumOperands();
5717 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex();
5718 if (NumElems > BaseIdx) {
5720 bool AllSame = true;
5721 for (unsigned i = 0; i != NumElems; ++i) {
5722 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
5723 Base = V->getOperand(i);
5727 // Splat of <u, u, u, u>, return <u, u, u, u>
5728 if (!Base.getNode())
5730 for (unsigned i = 0; i != NumElems; ++i) {
5731 if (V->getOperand(i) != Base) {
5736 // Splat of <x, x, x, x>, return <x, x, x, x>
5745 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
5746 /// an AND to a vector_shuffle with the destination vector and a zero vector.
5747 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
5748 /// vector_shuffle V, Zero, <0, 4, 2, 4>
5749 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
5750 EVT VT = N->getValueType(0);
5751 DebugLoc dl = N->getDebugLoc();
5752 SDValue LHS = N->getOperand(0);
5753 SDValue RHS = N->getOperand(1);
5754 if (N->getOpcode() == ISD::AND) {
5755 if (RHS.getOpcode() == ISD::BIT_CONVERT)
5756 RHS = RHS.getOperand(0);
5757 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
5758 SmallVector<int, 8> Indices;
5759 unsigned NumElts = RHS.getNumOperands();
5760 for (unsigned i = 0; i != NumElts; ++i) {
5761 SDValue Elt = RHS.getOperand(i);
5762 if (!isa<ConstantSDNode>(Elt))
5764 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
5765 Indices.push_back(i);
5766 else if (cast<ConstantSDNode>(Elt)->isNullValue())
5767 Indices.push_back(NumElts);
5772 // Let's see if the target supports this vector_shuffle.
5773 EVT RVT = RHS.getValueType();
5774 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
5777 // Return the new VECTOR_SHUFFLE node.
5778 EVT EltVT = RVT.getVectorElementType();
5779 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
5780 DAG.getConstant(0, EltVT));
5781 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5782 RVT, &ZeroOps[0], ZeroOps.size());
5783 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS);
5784 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
5785 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf);
5792 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
5793 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
5794 // After legalize, the target may be depending on adds and other
5795 // binary ops to provide legal ways to construct constants or other
5796 // things. Simplifying them may result in a loss of legality.
5797 if (LegalOperations) return SDValue();
5799 EVT VT = N->getValueType(0);
5800 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!");
5802 EVT EltType = VT.getVectorElementType();
5803 SDValue LHS = N->getOperand(0);
5804 SDValue RHS = N->getOperand(1);
5805 SDValue Shuffle = XformToShuffleWithZero(N);
5806 if (Shuffle.getNode()) return Shuffle;
5808 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
5810 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
5811 RHS.getOpcode() == ISD::BUILD_VECTOR) {
5812 SmallVector<SDValue, 8> Ops;
5813 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
5814 SDValue LHSOp = LHS.getOperand(i);
5815 SDValue RHSOp = RHS.getOperand(i);
5816 // If these two elements can't be folded, bail out.
5817 if ((LHSOp.getOpcode() != ISD::UNDEF &&
5818 LHSOp.getOpcode() != ISD::Constant &&
5819 LHSOp.getOpcode() != ISD::ConstantFP) ||
5820 (RHSOp.getOpcode() != ISD::UNDEF &&
5821 RHSOp.getOpcode() != ISD::Constant &&
5822 RHSOp.getOpcode() != ISD::ConstantFP))
5825 // Can't fold divide by zero.
5826 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
5827 N->getOpcode() == ISD::FDIV) {
5828 if ((RHSOp.getOpcode() == ISD::Constant &&
5829 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
5830 (RHSOp.getOpcode() == ISD::ConstantFP &&
5831 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
5835 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(),
5836 EltType, LHSOp, RHSOp));
5837 AddToWorkList(Ops.back().getNode());
5838 assert((Ops.back().getOpcode() == ISD::UNDEF ||
5839 Ops.back().getOpcode() == ISD::Constant ||
5840 Ops.back().getOpcode() == ISD::ConstantFP) &&
5841 "Scalar binop didn't fold!");
5844 if (Ops.size() == LHS.getNumOperands()) {
5845 EVT VT = LHS.getValueType();
5846 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
5847 &Ops[0], Ops.size());
5854 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
5855 SDValue N1, SDValue N2){
5856 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
5858 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
5859 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5861 // If we got a simplified select_cc node back from SimplifySelectCC, then
5862 // break it down into a new SETCC node, and a new SELECT node, and then return
5863 // the SELECT node, since we were called with a SELECT node.
5864 if (SCC.getNode()) {
5865 // Check to see if we got a select_cc back (to turn into setcc/select).
5866 // Otherwise, just return whatever node we got back, like fabs.
5867 if (SCC.getOpcode() == ISD::SELECT_CC) {
5868 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
5870 SCC.getOperand(0), SCC.getOperand(1),
5872 AddToWorkList(SETCC.getNode());
5873 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
5874 SCC.getOperand(2), SCC.getOperand(3), SETCC);
5882 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
5883 /// are the two values being selected between, see if we can simplify the
5884 /// select. Callers of this should assume that TheSelect is deleted if this
5885 /// returns true. As such, they should return the appropriate thing (e.g. the
5886 /// node) back to the top-level of the DAG combiner loop to avoid it being
5888 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
5891 // If this is a select from two identical things, try to pull the operation
5892 // through the select.
5893 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
5894 // If this is a load and the token chain is identical, replace the select
5895 // of two loads with a load through a select of the address to load from.
5896 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
5897 // constants have been dropped into the constant pool.
5898 if (LHS.getOpcode() == ISD::LOAD &&
5899 // Do not let this transformation reduce the number of volatile loads.
5900 !cast<LoadSDNode>(LHS)->isVolatile() &&
5901 !cast<LoadSDNode>(RHS)->isVolatile() &&
5902 // Token chains must be identical.
5903 LHS.getOperand(0) == RHS.getOperand(0)) {
5904 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
5905 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
5907 // If this is an EXTLOAD, the VT's must match.
5908 if (LLD->getMemoryVT() == RLD->getMemoryVT()) {
5909 // FIXME: this discards src value information. This is
5910 // over-conservative. It would be beneficial to be able to remember
5911 // both potential memory locations. Since we are discarding
5912 // src value info, don't do the transformation if the memory
5913 // locations are not in the default address space.
5914 unsigned LLDAddrSpace = 0, RLDAddrSpace = 0;
5915 if (const Value *LLDVal = LLD->getMemOperand()->getValue()) {
5916 if (const PointerType *PT = dyn_cast<PointerType>(LLDVal->getType()))
5917 LLDAddrSpace = PT->getAddressSpace();
5919 if (const Value *RLDVal = RLD->getMemOperand()->getValue()) {
5920 if (const PointerType *PT = dyn_cast<PointerType>(RLDVal->getType()))
5921 RLDAddrSpace = PT->getAddressSpace();
5924 if (LLDAddrSpace == 0 && RLDAddrSpace == 0) {
5925 if (TheSelect->getOpcode() == ISD::SELECT) {
5926 // Check that the condition doesn't reach either load. If so, folding
5927 // this will induce a cycle into the DAG.
5928 if ((!LLD->hasAnyUseOfValue(1) ||
5929 !LLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) &&
5930 (!RLD->hasAnyUseOfValue(1) ||
5931 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()))) {
5932 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
5933 LLD->getBasePtr().getValueType(),
5934 TheSelect->getOperand(0), LLD->getBasePtr(),
5938 // Check that the condition doesn't reach either load. If so, folding
5939 // this will induce a cycle into the DAG.
5940 if ((!LLD->hasAnyUseOfValue(1) ||
5941 (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5942 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()))) &&
5943 (!RLD->hasAnyUseOfValue(1) ||
5944 (!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5945 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())))) {
5946 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
5947 LLD->getBasePtr().getValueType(),
5948 TheSelect->getOperand(0),
5949 TheSelect->getOperand(1),
5950 LLD->getBasePtr(), RLD->getBasePtr(),
5951 TheSelect->getOperand(4));
5956 if (Addr.getNode()) {
5958 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
5959 Load = DAG.getLoad(TheSelect->getValueType(0),
5960 TheSelect->getDebugLoc(),
5964 LLD->isNonTemporal(),
5965 LLD->getAlignment());
5967 Load = DAG.getExtLoad(LLD->getExtensionType(),
5968 TheSelect->getDebugLoc(),
5969 TheSelect->getValueType(0),
5970 LLD->getChain(), Addr, 0, 0,
5973 LLD->isNonTemporal(),
5974 LLD->getAlignment());
5977 // Users of the select now use the result of the load.
5978 CombineTo(TheSelect, Load);
5980 // Users of the old loads now use the new load's chain. We know the
5981 // old-load value is dead now.
5982 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
5983 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
5993 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
5994 /// where 'cond' is the comparison specified by CC.
5995 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
5996 SDValue N2, SDValue N3,
5997 ISD::CondCode CC, bool NotExtCompare) {
5998 // (x ? y : y) -> y.
5999 if (N2 == N3) return N2;
6001 EVT VT = N2.getValueType();
6002 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
6003 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
6004 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
6006 // Determine if the condition we're dealing with is constant
6007 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
6008 N0, N1, CC, DL, false);
6009 if (SCC.getNode()) AddToWorkList(SCC.getNode());
6010 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
6012 // fold select_cc true, x, y -> x
6013 if (SCCC && !SCCC->isNullValue())
6015 // fold select_cc false, x, y -> y
6016 if (SCCC && SCCC->isNullValue())
6019 // Check to see if we can simplify the select into an fabs node
6020 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
6021 // Allow either -0.0 or 0.0
6022 if (CFP->getValueAPF().isZero()) {
6023 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
6024 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
6025 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
6026 N2 == N3.getOperand(0))
6027 return DAG.getNode(ISD::FABS, DL, VT, N0);
6029 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
6030 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
6031 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
6032 N2.getOperand(0) == N3)
6033 return DAG.getNode(ISD::FABS, DL, VT, N3);
6037 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
6038 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
6039 // in it. This is a win when the constant is not otherwise available because
6040 // it replaces two constant pool loads with one. We only do this if the FP
6041 // type is known to be legal, because if it isn't, then we are before legalize
6042 // types an we want the other legalization to happen first (e.g. to avoid
6043 // messing with soft float) and if the ConstantFP is not legal, because if
6044 // it is legal, we may not need to store the FP constant in a constant pool.
6045 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
6046 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
6047 if (TLI.isTypeLegal(N2.getValueType()) &&
6048 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
6049 TargetLowering::Legal) &&
6050 // If both constants have multiple uses, then we won't need to do an
6051 // extra load, they are likely around in registers for other users.
6052 (TV->hasOneUse() || FV->hasOneUse())) {
6053 Constant *Elts[] = {
6054 const_cast<ConstantFP*>(FV->getConstantFPValue()),
6055 const_cast<ConstantFP*>(TV->getConstantFPValue())
6057 const Type *FPTy = Elts[0]->getType();
6058 const TargetData &TD = *TLI.getTargetData();
6060 // Create a ConstantArray of the two constants.
6061 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2);
6062 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
6063 TD.getPrefTypeAlignment(FPTy));
6064 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6066 // Get the offsets to the 0 and 1 element of the array so that we can
6067 // select between them.
6068 SDValue Zero = DAG.getIntPtrConstant(0);
6069 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
6070 SDValue One = DAG.getIntPtrConstant(EltSize);
6072 SDValue Cond = DAG.getSetCC(DL,
6073 TLI.getSetCCResultType(N0.getValueType()),
6075 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
6077 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
6079 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
6080 PseudoSourceValue::getConstantPool(), 0, false,
6086 // Check to see if we can perform the "gzip trick", transforming
6087 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
6088 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
6089 N0.getValueType().isInteger() &&
6090 N2.getValueType().isInteger() &&
6091 (N1C->isNullValue() || // (a < 0) ? b : 0
6092 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
6093 EVT XType = N0.getValueType();
6094 EVT AType = N2.getValueType();
6095 if (XType.bitsGE(AType)) {
6096 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
6097 // single-bit constant.
6098 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
6099 unsigned ShCtV = N2C->getAPIntValue().logBase2();
6100 ShCtV = XType.getSizeInBits()-ShCtV-1;
6101 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy());
6102 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
6104 AddToWorkList(Shift.getNode());
6106 if (XType.bitsGT(AType)) {
6107 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
6108 AddToWorkList(Shift.getNode());
6111 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
6114 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
6116 DAG.getConstant(XType.getSizeInBits()-1,
6117 getShiftAmountTy()));
6118 AddToWorkList(Shift.getNode());
6120 if (XType.bitsGT(AType)) {
6121 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
6122 AddToWorkList(Shift.getNode());
6125 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
6129 // fold select C, 16, 0 -> shl C, 4
6130 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
6131 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {
6133 // If the caller doesn't want us to simplify this into a zext of a compare,
6135 if (NotExtCompare && N2C->getAPIntValue() == 1)
6138 // Get a SetCC of the condition
6139 // FIXME: Should probably make sure that setcc is legal if we ever have a
6140 // target where it isn't.
6142 // cast from setcc result type to select result type
6144 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
6146 if (N2.getValueType().bitsLT(SCC.getValueType()))
6147 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
6149 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
6150 N2.getValueType(), SCC);
6152 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
6153 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
6154 N2.getValueType(), SCC);
6157 AddToWorkList(SCC.getNode());
6158 AddToWorkList(Temp.getNode());
6160 if (N2C->getAPIntValue() == 1)
6163 // shl setcc result by log2 n2c
6164 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
6165 DAG.getConstant(N2C->getAPIntValue().logBase2(),
6166 getShiftAmountTy()));
6169 // Check to see if this is the equivalent of setcc
6170 // FIXME: Turn all of these into setcc if setcc if setcc is legal
6171 // otherwise, go ahead with the folds.
6172 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
6173 EVT XType = N0.getValueType();
6174 if (!LegalOperations ||
6175 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
6176 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
6177 if (Res.getValueType() != VT)
6178 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
6182 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
6183 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
6184 (!LegalOperations ||
6185 TLI.isOperationLegal(ISD::CTLZ, XType))) {
6186 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
6187 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
6188 DAG.getConstant(Log2_32(XType.getSizeInBits()),
6189 getShiftAmountTy()));
6191 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
6192 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
6193 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
6194 XType, DAG.getConstant(0, XType), N0);
6195 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
6196 return DAG.getNode(ISD::SRL, DL, XType,
6197 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
6198 DAG.getConstant(XType.getSizeInBits()-1,
6199 getShiftAmountTy()));
6201 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
6202 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
6203 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
6204 DAG.getConstant(XType.getSizeInBits()-1,
6205 getShiftAmountTy()));
6206 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
6210 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
6211 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
6212 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
6213 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
6214 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) {
6215 EVT XType = N0.getValueType();
6216 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0,
6217 DAG.getConstant(XType.getSizeInBits()-1,
6218 getShiftAmountTy()));
6219 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType,
6221 AddToWorkList(Shift.getNode());
6222 AddToWorkList(Add.getNode());
6223 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
6225 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
6226 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
6227 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
6228 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
6229 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
6230 EVT XType = N0.getValueType();
6231 if (SubC->isNullValue() && XType.isInteger()) {
6232 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
6234 DAG.getConstant(XType.getSizeInBits()-1,
6235 getShiftAmountTy()));
6236 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
6238 AddToWorkList(Shift.getNode());
6239 AddToWorkList(Add.getNode());
6240 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
6248 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
6249 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
6250 SDValue N1, ISD::CondCode Cond,
6251 DebugLoc DL, bool foldBooleans) {
6252 TargetLowering::DAGCombinerInfo
6253 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
6254 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
6257 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
6258 /// return a DAG expression to select that will generate the same value by
6259 /// multiplying by a magic number. See:
6260 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
6261 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
6262 std::vector<SDNode*> Built;
6263 SDValue S = TLI.BuildSDIV(N, DAG, &Built);
6265 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
6271 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
6272 /// return a DAG expression to select that will generate the same value by
6273 /// multiplying by a magic number. See:
6274 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
6275 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
6276 std::vector<SDNode*> Built;
6277 SDValue S = TLI.BuildUDIV(N, DAG, &Built);
6279 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
6285 /// FindBaseOffset - Return true if base is a frame index, which is known not
6286 // to alias with anything but itself. Provides base object and offset as results.
6287 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
6288 GlobalValue *&GV, void *&CV) {
6289 // Assume it is a primitive operation.
6290 Base = Ptr; Offset = 0; GV = 0; CV = 0;
6292 // If it's an adding a simple constant then integrate the offset.
6293 if (Base.getOpcode() == ISD::ADD) {
6294 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
6295 Base = Base.getOperand(0);
6296 Offset += C->getZExtValue();
6300 // Return the underlying GlobalValue, and update the Offset. Return false
6301 // for GlobalAddressSDNode since the same GlobalAddress may be represented
6302 // by multiple nodes with different offsets.
6303 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
6304 GV = G->getGlobal();
6305 Offset += G->getOffset();
6309 // Return the underlying Constant value, and update the Offset. Return false
6310 // for ConstantSDNodes since the same constant pool entry may be represented
6311 // by multiple nodes with different offsets.
6312 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
6313 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal()
6314 : (void *)C->getConstVal();
6315 Offset += C->getOffset();
6318 // If it's any of the following then it can't alias with anything but itself.
6319 return isa<FrameIndexSDNode>(Base);
6322 /// isAlias - Return true if there is any possibility that the two addresses
6324 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
6325 const Value *SrcValue1, int SrcValueOffset1,
6326 unsigned SrcValueAlign1,
6327 SDValue Ptr2, int64_t Size2,
6328 const Value *SrcValue2, int SrcValueOffset2,
6329 unsigned SrcValueAlign2) const {
6330 // If they are the same then they must be aliases.
6331 if (Ptr1 == Ptr2) return true;
6333 // Gather base node and offset information.
6334 SDValue Base1, Base2;
6335 int64_t Offset1, Offset2;
6336 GlobalValue *GV1, *GV2;
6338 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
6339 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
6341 // If they have a same base address then check to see if they overlap.
6342 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
6343 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
6345 // If we know what the bases are, and they aren't identical, then we know they
6347 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
6350 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
6351 // compared to the size and offset of the access, we may be able to prove they
6352 // do not alias. This check is conservative for now to catch cases created by
6353 // splitting vector types.
6354 if ((SrcValueAlign1 == SrcValueAlign2) &&
6355 (SrcValueOffset1 != SrcValueOffset2) &&
6356 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
6357 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
6358 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
6360 // There is no overlap between these relatively aligned accesses of similar
6361 // size, return no alias.
6362 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
6366 if (CombinerGlobalAA) {
6367 // Use alias analysis information.
6368 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
6369 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
6370 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
6371 AliasAnalysis::AliasResult AAResult =
6372 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
6373 if (AAResult == AliasAnalysis::NoAlias)
6377 // Otherwise we have to assume they alias.
6381 /// FindAliasInfo - Extracts the relevant alias information from the memory
6382 /// node. Returns true if the operand was a load.
6383 bool DAGCombiner::FindAliasInfo(SDNode *N,
6384 SDValue &Ptr, int64_t &Size,
6385 const Value *&SrcValue,
6386 int &SrcValueOffset,
6387 unsigned &SrcValueAlign) const {
6388 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6389 Ptr = LD->getBasePtr();
6390 Size = LD->getMemoryVT().getSizeInBits() >> 3;
6391 SrcValue = LD->getSrcValue();
6392 SrcValueOffset = LD->getSrcValueOffset();
6393 SrcValueAlign = LD->getOriginalAlignment();
6395 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6396 Ptr = ST->getBasePtr();
6397 Size = ST->getMemoryVT().getSizeInBits() >> 3;
6398 SrcValue = ST->getSrcValue();
6399 SrcValueOffset = ST->getSrcValueOffset();
6400 SrcValueAlign = ST->getOriginalAlignment();
6402 llvm_unreachable("FindAliasInfo expected a memory operand");
6408 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
6409 /// looking for aliasing nodes and adding them to the Aliases vector.
6410 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
6411 SmallVector<SDValue, 8> &Aliases) {
6412 SmallVector<SDValue, 8> Chains; // List of chains to visit.
6413 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
6415 // Get alias information for node.
6418 const Value *SrcValue;
6420 unsigned SrcValueAlign;
6421 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
6425 Chains.push_back(OriginalChain);
6428 // Look at each chain and determine if it is an alias. If so, add it to the
6429 // aliases list. If not, then continue up the chain looking for the next
6431 while (!Chains.empty()) {
6432 SDValue Chain = Chains.back();
6435 // For TokenFactor nodes, look at each operand and only continue up the
6436 // chain until we find two aliases. If we've seen two aliases, assume we'll
6437 // find more and revert to original chain since the xform is unlikely to be
6440 // FIXME: The depth check could be made to return the last non-aliasing
6441 // chain we found before we hit a tokenfactor rather than the original
6443 if (Depth > 6 || Aliases.size() == 2) {
6445 Aliases.push_back(OriginalChain);
6449 // Don't bother if we've been before.
6450 if (!Visited.insert(Chain.getNode()))
6453 switch (Chain.getOpcode()) {
6454 case ISD::EntryToken:
6455 // Entry token is ideal chain operand, but handled in FindBetterChain.
6460 // Get alias information for Chain.
6463 const Value *OpSrcValue;
6464 int OpSrcValueOffset;
6465 unsigned OpSrcValueAlign;
6466 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
6467 OpSrcValue, OpSrcValueOffset,
6470 // If chain is alias then stop here.
6471 if (!(IsLoad && IsOpLoad) &&
6472 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
6473 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
6475 Aliases.push_back(Chain);
6477 // Look further up the chain.
6478 Chains.push_back(Chain.getOperand(0));
6484 case ISD::TokenFactor:
6485 // We have to check each of the operands of the token factor for "small"
6486 // token factors, so we queue them up. Adding the operands to the queue
6487 // (stack) in reverse order maintains the original order and increases the
6488 // likelihood that getNode will find a matching token factor (CSE.)
6489 if (Chain.getNumOperands() > 16) {
6490 Aliases.push_back(Chain);
6493 for (unsigned n = Chain.getNumOperands(); n;)
6494 Chains.push_back(Chain.getOperand(--n));
6499 // For all other instructions we will just have to take what we can get.
6500 Aliases.push_back(Chain);
6506 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
6507 /// for a better chain (aliasing node.)
6508 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
6509 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
6511 // Accumulate all the aliases to this node.
6512 GatherAllAliases(N, OldChain, Aliases);
6514 if (Aliases.size() == 0) {
6515 // If no operands then chain to entry token.
6516 return DAG.getEntryNode();
6517 } else if (Aliases.size() == 1) {
6518 // If a single operand then chain to it. We don't need to revisit it.
6522 // Construct a custom tailored token factor.
6523 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
6524 &Aliases[0], Aliases.size());
6527 // SelectionDAG::Combine - This is the entry point for the file.
6529 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
6530 CodeGenOpt::Level OptLevel) {
6531 /// run - This is the main entry point to this class.
6533 DAGCombiner(*this, AA, OptLevel).Run(Level);