1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/Target/TargetData.h"
27 #include "llvm/Target/TargetLowering.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/ADT/SmallPtrSet.h"
31 #include "llvm/ADT/Statistic.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
40 STATISTIC(NodesCombined , "Number of dag nodes combined");
41 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
42 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
43 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
44 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
48 CombinerAA("combiner-alias-analysis", cl::Hidden,
49 cl::desc("Turn on alias analysis during testing"));
52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
53 cl::desc("Include global information in alias analysis"));
55 //------------------------------ DAGCombiner ---------------------------------//
59 const TargetLowering &TLI;
61 CodeGenOpt::Level OptLevel;
65 // Worklist of all of the nodes that need to be simplified.
66 std::vector<SDNode*> WorkList;
68 // AA - Used for DAG load/store alias analysis.
71 /// AddUsersToWorkList - When an instruction is simplified, add all users of
72 /// the instruction to the work lists because they might get more simplified
75 void AddUsersToWorkList(SDNode *N) {
76 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
81 /// visit - call the node-specific routine that knows how to fold each
82 /// particular type of node.
83 SDValue visit(SDNode *N);
86 /// AddToWorkList - Add to the work list making sure it's instance is at the
87 /// the back (next to be processed.)
88 void AddToWorkList(SDNode *N) {
89 removeFromWorkList(N);
90 WorkList.push_back(N);
93 /// removeFromWorkList - remove all instances of N from the worklist.
95 void removeFromWorkList(SDNode *N) {
96 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
100 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
103 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
104 return CombineTo(N, &Res, 1, AddTo);
107 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
109 SDValue To[] = { Res0, Res1 };
110 return CombineTo(N, To, 2, AddTo);
113 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
117 /// SimplifyDemandedBits - Check the specified integer node value to see if
118 /// it can be simplified or if things it uses can be simplified by bit
119 /// propagation. If so, return true.
120 bool SimplifyDemandedBits(SDValue Op) {
121 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
122 APInt Demanded = APInt::getAllOnesValue(BitWidth);
123 return SimplifyDemandedBits(Op, Demanded);
126 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
128 bool CombineToPreIndexedLoadStore(SDNode *N);
129 bool CombineToPostIndexedLoadStore(SDNode *N);
131 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
132 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
133 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
134 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
135 SDValue PromoteIntBinOp(SDValue Op);
136 SDValue PromoteIntShiftOp(SDValue Op);
137 SDValue PromoteExtend(SDValue Op);
138 bool PromoteLoad(SDValue Op);
140 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
141 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
142 ISD::NodeType ExtType);
144 /// combine - call the node-specific routine that knows how to fold each
145 /// particular type of node. If that doesn't do anything, try the
146 /// target-specific DAG combines.
147 SDValue combine(SDNode *N);
149 // Visitation implementation - Implement dag node combining for different
150 // node types. The semantics are as follows:
152 // SDValue.getNode() == 0 - No change was made
153 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
154 // otherwise - N should be replaced by the returned Operand.
156 SDValue visitTokenFactor(SDNode *N);
157 SDValue visitMERGE_VALUES(SDNode *N);
158 SDValue visitADD(SDNode *N);
159 SDValue visitSUB(SDNode *N);
160 SDValue visitADDC(SDNode *N);
161 SDValue visitSUBC(SDNode *N);
162 SDValue visitADDE(SDNode *N);
163 SDValue visitSUBE(SDNode *N);
164 SDValue visitMUL(SDNode *N);
165 SDValue visitSDIV(SDNode *N);
166 SDValue visitUDIV(SDNode *N);
167 SDValue visitSREM(SDNode *N);
168 SDValue visitUREM(SDNode *N);
169 SDValue visitMULHU(SDNode *N);
170 SDValue visitMULHS(SDNode *N);
171 SDValue visitSMUL_LOHI(SDNode *N);
172 SDValue visitUMUL_LOHI(SDNode *N);
173 SDValue visitSMULO(SDNode *N);
174 SDValue visitUMULO(SDNode *N);
175 SDValue visitSDIVREM(SDNode *N);
176 SDValue visitUDIVREM(SDNode *N);
177 SDValue visitAND(SDNode *N);
178 SDValue visitOR(SDNode *N);
179 SDValue visitXOR(SDNode *N);
180 SDValue SimplifyVBinOp(SDNode *N);
181 SDValue visitSHL(SDNode *N);
182 SDValue visitSRA(SDNode *N);
183 SDValue visitSRL(SDNode *N);
184 SDValue visitCTLZ(SDNode *N);
185 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
186 SDValue visitCTTZ(SDNode *N);
187 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
188 SDValue visitCTPOP(SDNode *N);
189 SDValue visitSELECT(SDNode *N);
190 SDValue visitSELECT_CC(SDNode *N);
191 SDValue visitSETCC(SDNode *N);
192 SDValue visitSIGN_EXTEND(SDNode *N);
193 SDValue visitZERO_EXTEND(SDNode *N);
194 SDValue visitANY_EXTEND(SDNode *N);
195 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
196 SDValue visitTRUNCATE(SDNode *N);
197 SDValue visitBITCAST(SDNode *N);
198 SDValue visitBUILD_PAIR(SDNode *N);
199 SDValue visitFADD(SDNode *N);
200 SDValue visitFSUB(SDNode *N);
201 SDValue visitFMUL(SDNode *N);
202 SDValue visitFDIV(SDNode *N);
203 SDValue visitFREM(SDNode *N);
204 SDValue visitFCOPYSIGN(SDNode *N);
205 SDValue visitSINT_TO_FP(SDNode *N);
206 SDValue visitUINT_TO_FP(SDNode *N);
207 SDValue visitFP_TO_SINT(SDNode *N);
208 SDValue visitFP_TO_UINT(SDNode *N);
209 SDValue visitFP_ROUND(SDNode *N);
210 SDValue visitFP_ROUND_INREG(SDNode *N);
211 SDValue visitFP_EXTEND(SDNode *N);
212 SDValue visitFNEG(SDNode *N);
213 SDValue visitFABS(SDNode *N);
214 SDValue visitBRCOND(SDNode *N);
215 SDValue visitBR_CC(SDNode *N);
216 SDValue visitLOAD(SDNode *N);
217 SDValue visitSTORE(SDNode *N);
218 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
219 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
220 SDValue visitBUILD_VECTOR(SDNode *N);
221 SDValue visitCONCAT_VECTORS(SDNode *N);
222 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
223 SDValue visitVECTOR_SHUFFLE(SDNode *N);
224 SDValue visitMEMBARRIER(SDNode *N);
226 SDValue XformToShuffleWithZero(SDNode *N);
227 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
229 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
231 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
232 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
233 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
234 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
235 SDValue N3, ISD::CondCode CC,
236 bool NotExtCompare = false);
237 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
238 DebugLoc DL, bool foldBooleans = true);
239 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
241 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
242 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
243 SDValue BuildSDIV(SDNode *N);
244 SDValue BuildUDIV(SDNode *N);
245 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
246 bool DemandHighBits = true);
247 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
248 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
249 SDValue ReduceLoadWidth(SDNode *N);
250 SDValue ReduceLoadOpStoreWidth(SDNode *N);
251 SDValue TransformFPLoadStorePair(SDNode *N);
253 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
255 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
256 /// looking for aliasing nodes and adding them to the Aliases vector.
257 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
258 SmallVector<SDValue, 8> &Aliases);
260 /// isAlias - Return true if there is any possibility that the two addresses
262 bool isAlias(SDValue Ptr1, int64_t Size1,
263 const Value *SrcValue1, int SrcValueOffset1,
264 unsigned SrcValueAlign1,
265 const MDNode *TBAAInfo1,
266 SDValue Ptr2, int64_t Size2,
267 const Value *SrcValue2, int SrcValueOffset2,
268 unsigned SrcValueAlign2,
269 const MDNode *TBAAInfo2) const;
271 /// FindAliasInfo - Extracts the relevant alias information from the memory
272 /// node. Returns true if the operand was a load.
273 bool FindAliasInfo(SDNode *N,
274 SDValue &Ptr, int64_t &Size,
275 const Value *&SrcValue, int &SrcValueOffset,
276 unsigned &SrcValueAlignment,
277 const MDNode *&TBAAInfo) const;
279 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
280 /// looking for a better chain (aliasing node.)
281 SDValue FindBetterChain(SDNode *N, SDValue Chain);
284 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
285 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
286 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
288 /// Run - runs the dag combiner on all nodes in the work list
289 void Run(CombineLevel AtLevel);
291 SelectionDAG &getDAG() const { return DAG; }
293 /// getShiftAmountTy - Returns a type large enough to hold any valid
294 /// shift amount - before type legalization these can be huge.
295 EVT getShiftAmountTy(EVT LHSTy) {
296 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy();
299 /// isTypeLegal - This method returns true if we are running before type
300 /// legalization or if the specified VT is legal.
301 bool isTypeLegal(const EVT &VT) {
302 if (!LegalTypes) return true;
303 return TLI.isTypeLegal(VT);
310 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
311 /// nodes from the worklist.
312 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
315 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
317 virtual void NodeDeleted(SDNode *N, SDNode *E) {
318 DC.removeFromWorkList(N);
321 virtual void NodeUpdated(SDNode *N) {
327 //===----------------------------------------------------------------------===//
328 // TargetLowering::DAGCombinerInfo implementation
329 //===----------------------------------------------------------------------===//
331 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
332 ((DAGCombiner*)DC)->AddToWorkList(N);
335 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
336 ((DAGCombiner*)DC)->removeFromWorkList(N);
339 SDValue TargetLowering::DAGCombinerInfo::
340 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
341 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
344 SDValue TargetLowering::DAGCombinerInfo::
345 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
346 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
350 SDValue TargetLowering::DAGCombinerInfo::
351 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
352 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
355 void TargetLowering::DAGCombinerInfo::
356 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
357 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
360 //===----------------------------------------------------------------------===//
362 //===----------------------------------------------------------------------===//
364 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
365 /// specified expression for the same cost as the expression itself, or 2 if we
366 /// can compute the negated form more cheaply than the expression itself.
367 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
368 const TargetOptions *Options,
369 unsigned Depth = 0) {
370 // No compile time optimizations on this type.
371 if (Op.getValueType() == MVT::ppcf128)
374 // fneg is removable even if it has multiple uses.
375 if (Op.getOpcode() == ISD::FNEG) return 2;
377 // Don't allow anything with multiple uses.
378 if (!Op.hasOneUse()) return 0;
380 // Don't recurse exponentially.
381 if (Depth > 6) return 0;
383 switch (Op.getOpcode()) {
384 default: return false;
385 case ISD::ConstantFP:
386 // Don't invert constant FP values after legalize. The negated constant
387 // isn't necessarily legal.
388 return LegalOperations ? 0 : 1;
390 // FIXME: determine better conditions for this xform.
391 if (!Options->UnsafeFPMath) return 0;
393 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
394 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Options,
397 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
398 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Options,
401 // We can't turn -(A-B) into B-A when we honor signed zeros.
402 if (!Options->UnsafeFPMath) return 0;
404 // fold (fneg (fsub A, B)) -> (fsub B, A)
409 if (Options->HonorSignDependentRoundingFPMath()) return 0;
411 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
412 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Options,
416 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Options,
422 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Options,
427 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
428 /// returns the newly negated expression.
429 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
430 bool LegalOperations, unsigned Depth = 0) {
431 // fneg is removable even if it has multiple uses.
432 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
434 // Don't allow anything with multiple uses.
435 assert(Op.hasOneUse() && "Unknown reuse!");
437 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
438 switch (Op.getOpcode()) {
439 default: llvm_unreachable("Unknown code");
440 case ISD::ConstantFP: {
441 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
443 return DAG.getConstantFP(V, Op.getValueType());
446 // FIXME: determine better conditions for this xform.
447 assert(DAG.getTarget().Options.UnsafeFPMath);
449 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
450 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
451 &DAG.getTarget().Options, Depth+1))
452 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
453 GetNegatedExpression(Op.getOperand(0), DAG,
454 LegalOperations, Depth+1),
456 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
457 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
458 GetNegatedExpression(Op.getOperand(1), DAG,
459 LegalOperations, Depth+1),
462 // We can't turn -(A-B) into B-A when we honor signed zeros.
463 assert(DAG.getTarget().Options.UnsafeFPMath);
465 // fold (fneg (fsub 0, B)) -> B
466 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
467 if (N0CFP->getValueAPF().isZero())
468 return Op.getOperand(1);
470 // fold (fneg (fsub A, B)) -> (fsub B, A)
471 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
472 Op.getOperand(1), Op.getOperand(0));
476 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath());
478 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
479 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
480 &DAG.getTarget().Options, Depth+1))
481 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
482 GetNegatedExpression(Op.getOperand(0), DAG,
483 LegalOperations, Depth+1),
486 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
487 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
489 GetNegatedExpression(Op.getOperand(1), DAG,
490 LegalOperations, Depth+1));
494 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
495 GetNegatedExpression(Op.getOperand(0), DAG,
496 LegalOperations, Depth+1));
498 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
499 GetNegatedExpression(Op.getOperand(0), DAG,
500 LegalOperations, Depth+1),
506 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
507 // that selects between the values 1 and 0, making it equivalent to a setcc.
508 // Also, set the incoming LHS, RHS, and CC references to the appropriate
509 // nodes based on the type of node we are checking. This simplifies life a
510 // bit for the callers.
511 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
513 if (N.getOpcode() == ISD::SETCC) {
514 LHS = N.getOperand(0);
515 RHS = N.getOperand(1);
516 CC = N.getOperand(2);
519 if (N.getOpcode() == ISD::SELECT_CC &&
520 N.getOperand(2).getOpcode() == ISD::Constant &&
521 N.getOperand(3).getOpcode() == ISD::Constant &&
522 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
523 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
524 LHS = N.getOperand(0);
525 RHS = N.getOperand(1);
526 CC = N.getOperand(4);
532 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
533 // one use. If this is true, it allows the users to invert the operation for
534 // free when it is profitable to do so.
535 static bool isOneUseSetCC(SDValue N) {
537 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
542 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
543 SDValue N0, SDValue N1) {
544 EVT VT = N0.getValueType();
545 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
546 if (isa<ConstantSDNode>(N1)) {
547 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
549 DAG.FoldConstantArithmetic(Opc, VT,
550 cast<ConstantSDNode>(N0.getOperand(1)),
551 cast<ConstantSDNode>(N1));
552 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
554 if (N0.hasOneUse()) {
555 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
556 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
557 N0.getOperand(0), N1);
558 AddToWorkList(OpNode.getNode());
559 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
563 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
564 if (isa<ConstantSDNode>(N0)) {
565 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
567 DAG.FoldConstantArithmetic(Opc, VT,
568 cast<ConstantSDNode>(N1.getOperand(1)),
569 cast<ConstantSDNode>(N0));
570 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
572 if (N1.hasOneUse()) {
573 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
574 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
575 N1.getOperand(0), N0);
576 AddToWorkList(OpNode.getNode());
577 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
584 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
586 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
588 DEBUG(dbgs() << "\nReplacing.1 ";
590 dbgs() << "\nWith: ";
591 To[0].getNode()->dump(&DAG);
592 dbgs() << " and " << NumTo-1 << " other values\n";
593 for (unsigned i = 0, e = NumTo; i != e; ++i)
594 assert((!To[i].getNode() ||
595 N->getValueType(i) == To[i].getValueType()) &&
596 "Cannot combine value to value of different type!"));
597 WorkListRemover DeadNodes(*this);
598 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
601 // Push the new nodes and any users onto the worklist
602 for (unsigned i = 0, e = NumTo; i != e; ++i) {
603 if (To[i].getNode()) {
604 AddToWorkList(To[i].getNode());
605 AddUsersToWorkList(To[i].getNode());
610 // Finally, if the node is now dead, remove it from the graph. The node
611 // may not be dead if the replacement process recursively simplified to
612 // something else needing this node.
613 if (N->use_empty()) {
614 // Nodes can be reintroduced into the worklist. Make sure we do not
615 // process a node that has been replaced.
616 removeFromWorkList(N);
618 // Finally, since the node is now dead, remove it from the graph.
621 return SDValue(N, 0);
625 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
626 // Replace all uses. If any nodes become isomorphic to other nodes and
627 // are deleted, make sure to remove them from our worklist.
628 WorkListRemover DeadNodes(*this);
629 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
631 // Push the new node and any (possibly new) users onto the worklist.
632 AddToWorkList(TLO.New.getNode());
633 AddUsersToWorkList(TLO.New.getNode());
635 // Finally, if the node is now dead, remove it from the graph. The node
636 // may not be dead if the replacement process recursively simplified to
637 // something else needing this node.
638 if (TLO.Old.getNode()->use_empty()) {
639 removeFromWorkList(TLO.Old.getNode());
641 // If the operands of this node are only used by the node, they will now
642 // be dead. Make sure to visit them first to delete dead nodes early.
643 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
644 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
645 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
647 DAG.DeleteNode(TLO.Old.getNode());
651 /// SimplifyDemandedBits - Check the specified integer node value to see if
652 /// it can be simplified or if things it uses can be simplified by bit
653 /// propagation. If so, return true.
654 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
655 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
656 APInt KnownZero, KnownOne;
657 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
661 AddToWorkList(Op.getNode());
663 // Replace the old value with the new one.
665 DEBUG(dbgs() << "\nReplacing.2 ";
666 TLO.Old.getNode()->dump(&DAG);
667 dbgs() << "\nWith: ";
668 TLO.New.getNode()->dump(&DAG);
671 CommitTargetLoweringOpt(TLO);
675 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
676 DebugLoc dl = Load->getDebugLoc();
677 EVT VT = Load->getValueType(0);
678 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
680 DEBUG(dbgs() << "\nReplacing.9 ";
682 dbgs() << "\nWith: ";
683 Trunc.getNode()->dump(&DAG);
685 WorkListRemover DeadNodes(*this);
686 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes);
687 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1),
689 removeFromWorkList(Load);
690 DAG.DeleteNode(Load);
691 AddToWorkList(Trunc.getNode());
694 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
696 DebugLoc dl = Op.getDebugLoc();
697 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
698 EVT MemVT = LD->getMemoryVT();
699 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
700 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
702 : LD->getExtensionType();
704 return DAG.getExtLoad(ExtType, dl, PVT,
705 LD->getChain(), LD->getBasePtr(),
706 LD->getPointerInfo(),
707 MemVT, LD->isVolatile(),
708 LD->isNonTemporal(), LD->getAlignment());
711 unsigned Opc = Op.getOpcode();
714 case ISD::AssertSext:
715 return DAG.getNode(ISD::AssertSext, dl, PVT,
716 SExtPromoteOperand(Op.getOperand(0), PVT),
718 case ISD::AssertZext:
719 return DAG.getNode(ISD::AssertZext, dl, PVT,
720 ZExtPromoteOperand(Op.getOperand(0), PVT),
722 case ISD::Constant: {
724 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
725 return DAG.getNode(ExtOpc, dl, PVT, Op);
729 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
731 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
734 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
735 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
737 EVT OldVT = Op.getValueType();
738 DebugLoc dl = Op.getDebugLoc();
739 bool Replace = false;
740 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
741 if (NewOp.getNode() == 0)
743 AddToWorkList(NewOp.getNode());
746 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
747 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
748 DAG.getValueType(OldVT));
751 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
752 EVT OldVT = Op.getValueType();
753 DebugLoc dl = Op.getDebugLoc();
754 bool Replace = false;
755 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
756 if (NewOp.getNode() == 0)
758 AddToWorkList(NewOp.getNode());
761 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
762 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
765 /// PromoteIntBinOp - Promote the specified integer binary operation if the
766 /// target indicates it is beneficial. e.g. On x86, it's usually better to
767 /// promote i16 operations to i32 since i16 instructions are longer.
768 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
769 if (!LegalOperations)
772 EVT VT = Op.getValueType();
773 if (VT.isVector() || !VT.isInteger())
776 // If operation type is 'undesirable', e.g. i16 on x86, consider
778 unsigned Opc = Op.getOpcode();
779 if (TLI.isTypeDesirableForOp(Opc, VT))
783 // Consult target whether it is a good idea to promote this operation and
784 // what's the right type to promote it to.
785 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
786 assert(PVT != VT && "Don't know what type to promote to!");
788 bool Replace0 = false;
789 SDValue N0 = Op.getOperand(0);
790 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
791 if (NN0.getNode() == 0)
794 bool Replace1 = false;
795 SDValue N1 = Op.getOperand(1);
800 NN1 = PromoteOperand(N1, PVT, Replace1);
801 if (NN1.getNode() == 0)
805 AddToWorkList(NN0.getNode());
807 AddToWorkList(NN1.getNode());
810 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
812 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
814 DEBUG(dbgs() << "\nPromoting ";
815 Op.getNode()->dump(&DAG));
816 DebugLoc dl = Op.getDebugLoc();
817 return DAG.getNode(ISD::TRUNCATE, dl, VT,
818 DAG.getNode(Opc, dl, PVT, NN0, NN1));
823 /// PromoteIntShiftOp - Promote the specified integer shift operation if the
824 /// target indicates it is beneficial. e.g. On x86, it's usually better to
825 /// promote i16 operations to i32 since i16 instructions are longer.
826 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
827 if (!LegalOperations)
830 EVT VT = Op.getValueType();
831 if (VT.isVector() || !VT.isInteger())
834 // If operation type is 'undesirable', e.g. i16 on x86, consider
836 unsigned Opc = Op.getOpcode();
837 if (TLI.isTypeDesirableForOp(Opc, VT))
841 // Consult target whether it is a good idea to promote this operation and
842 // what's the right type to promote it to.
843 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
844 assert(PVT != VT && "Don't know what type to promote to!");
846 bool Replace = false;
847 SDValue N0 = Op.getOperand(0);
849 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
850 else if (Opc == ISD::SRL)
851 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
853 N0 = PromoteOperand(N0, PVT, Replace);
854 if (N0.getNode() == 0)
857 AddToWorkList(N0.getNode());
859 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
861 DEBUG(dbgs() << "\nPromoting ";
862 Op.getNode()->dump(&DAG));
863 DebugLoc dl = Op.getDebugLoc();
864 return DAG.getNode(ISD::TRUNCATE, dl, VT,
865 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
870 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
871 if (!LegalOperations)
874 EVT VT = Op.getValueType();
875 if (VT.isVector() || !VT.isInteger())
878 // If operation type is 'undesirable', e.g. i16 on x86, consider
880 unsigned Opc = Op.getOpcode();
881 if (TLI.isTypeDesirableForOp(Opc, VT))
885 // Consult target whether it is a good idea to promote this operation and
886 // what's the right type to promote it to.
887 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
888 assert(PVT != VT && "Don't know what type to promote to!");
889 // fold (aext (aext x)) -> (aext x)
890 // fold (aext (zext x)) -> (zext x)
891 // fold (aext (sext x)) -> (sext x)
892 DEBUG(dbgs() << "\nPromoting ";
893 Op.getNode()->dump(&DAG));
894 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0));
899 bool DAGCombiner::PromoteLoad(SDValue Op) {
900 if (!LegalOperations)
903 EVT VT = Op.getValueType();
904 if (VT.isVector() || !VT.isInteger())
907 // If operation type is 'undesirable', e.g. i16 on x86, consider
909 unsigned Opc = Op.getOpcode();
910 if (TLI.isTypeDesirableForOp(Opc, VT))
914 // Consult target whether it is a good idea to promote this operation and
915 // what's the right type to promote it to.
916 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
917 assert(PVT != VT && "Don't know what type to promote to!");
919 DebugLoc dl = Op.getDebugLoc();
920 SDNode *N = Op.getNode();
921 LoadSDNode *LD = cast<LoadSDNode>(N);
922 EVT MemVT = LD->getMemoryVT();
923 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
924 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
926 : LD->getExtensionType();
927 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
928 LD->getChain(), LD->getBasePtr(),
929 LD->getPointerInfo(),
930 MemVT, LD->isVolatile(),
931 LD->isNonTemporal(), LD->getAlignment());
932 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
934 DEBUG(dbgs() << "\nPromoting ";
937 Result.getNode()->dump(&DAG);
939 WorkListRemover DeadNodes(*this);
940 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes);
941 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes);
942 removeFromWorkList(N);
944 AddToWorkList(Result.getNode());
951 //===----------------------------------------------------------------------===//
952 // Main DAG Combiner implementation
953 //===----------------------------------------------------------------------===//
955 void DAGCombiner::Run(CombineLevel AtLevel) {
956 // set the instance variables, so that the various visit routines may use it.
958 LegalOperations = Level >= AfterLegalizeVectorOps;
959 LegalTypes = Level >= AfterLegalizeTypes;
961 // Add all the dag nodes to the worklist.
962 WorkList.reserve(DAG.allnodes_size());
963 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
964 E = DAG.allnodes_end(); I != E; ++I)
965 WorkList.push_back(I);
967 // Create a dummy node (which is not added to allnodes), that adds a reference
968 // to the root node, preventing it from being deleted, and tracking any
969 // changes of the root.
970 HandleSDNode Dummy(DAG.getRoot());
972 // The root of the dag may dangle to deleted nodes until the dag combiner is
973 // done. Set it to null to avoid confusion.
974 DAG.setRoot(SDValue());
976 // while the worklist isn't empty, inspect the node on the end of it and
977 // try and combine it.
978 while (!WorkList.empty()) {
979 SDNode *N = WorkList.back();
982 // If N has no uses, it is dead. Make sure to revisit all N's operands once
983 // N is deleted from the DAG, since they too may now be dead or may have a
984 // reduced number of uses, allowing other xforms.
985 if (N->use_empty() && N != &Dummy) {
986 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
987 AddToWorkList(N->getOperand(i).getNode());
993 SDValue RV = combine(N);
995 if (RV.getNode() == 0)
1000 // If we get back the same node we passed in, rather than a new node or
1001 // zero, we know that the node must have defined multiple values and
1002 // CombineTo was used. Since CombineTo takes care of the worklist
1003 // mechanics for us, we have no work to do in this case.
1004 if (RV.getNode() == N)
1007 assert(N->getOpcode() != ISD::DELETED_NODE &&
1008 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1009 "Node was deleted but visit returned new node!");
1011 DEBUG(dbgs() << "\nReplacing.3 ";
1013 dbgs() << "\nWith: ";
1014 RV.getNode()->dump(&DAG);
1017 // Transfer debug value.
1018 DAG.TransferDbgValues(SDValue(N, 0), RV);
1019 WorkListRemover DeadNodes(*this);
1020 if (N->getNumValues() == RV.getNode()->getNumValues())
1021 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
1023 assert(N->getValueType(0) == RV.getValueType() &&
1024 N->getNumValues() == 1 && "Type mismatch");
1026 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
1029 // Push the new node and any users onto the worklist
1030 AddToWorkList(RV.getNode());
1031 AddUsersToWorkList(RV.getNode());
1033 // Add any uses of the old node to the worklist in case this node is the
1034 // last one that uses them. They may become dead after this node is
1036 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1037 AddToWorkList(N->getOperand(i).getNode());
1039 // Finally, if the node is now dead, remove it from the graph. The node
1040 // may not be dead if the replacement process recursively simplified to
1041 // something else needing this node.
1042 if (N->use_empty()) {
1043 // Nodes can be reintroduced into the worklist. Make sure we do not
1044 // process a node that has been replaced.
1045 removeFromWorkList(N);
1047 // Finally, since the node is now dead, remove it from the graph.
1052 // If the root changed (e.g. it was a dead load, update the root).
1053 DAG.setRoot(Dummy.getValue());
1056 SDValue DAGCombiner::visit(SDNode *N) {
1057 switch (N->getOpcode()) {
1059 case ISD::TokenFactor: return visitTokenFactor(N);
1060 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1061 case ISD::ADD: return visitADD(N);
1062 case ISD::SUB: return visitSUB(N);
1063 case ISD::ADDC: return visitADDC(N);
1064 case ISD::SUBC: return visitSUBC(N);
1065 case ISD::ADDE: return visitADDE(N);
1066 case ISD::SUBE: return visitSUBE(N);
1067 case ISD::MUL: return visitMUL(N);
1068 case ISD::SDIV: return visitSDIV(N);
1069 case ISD::UDIV: return visitUDIV(N);
1070 case ISD::SREM: return visitSREM(N);
1071 case ISD::UREM: return visitUREM(N);
1072 case ISD::MULHU: return visitMULHU(N);
1073 case ISD::MULHS: return visitMULHS(N);
1074 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1075 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1076 case ISD::SMULO: return visitSMULO(N);
1077 case ISD::UMULO: return visitUMULO(N);
1078 case ISD::SDIVREM: return visitSDIVREM(N);
1079 case ISD::UDIVREM: return visitUDIVREM(N);
1080 case ISD::AND: return visitAND(N);
1081 case ISD::OR: return visitOR(N);
1082 case ISD::XOR: return visitXOR(N);
1083 case ISD::SHL: return visitSHL(N);
1084 case ISD::SRA: return visitSRA(N);
1085 case ISD::SRL: return visitSRL(N);
1086 case ISD::CTLZ: return visitCTLZ(N);
1087 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1088 case ISD::CTTZ: return visitCTTZ(N);
1089 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1090 case ISD::CTPOP: return visitCTPOP(N);
1091 case ISD::SELECT: return visitSELECT(N);
1092 case ISD::SELECT_CC: return visitSELECT_CC(N);
1093 case ISD::SETCC: return visitSETCC(N);
1094 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1095 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1096 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1097 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1098 case ISD::TRUNCATE: return visitTRUNCATE(N);
1099 case ISD::BITCAST: return visitBITCAST(N);
1100 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1101 case ISD::FADD: return visitFADD(N);
1102 case ISD::FSUB: return visitFSUB(N);
1103 case ISD::FMUL: return visitFMUL(N);
1104 case ISD::FDIV: return visitFDIV(N);
1105 case ISD::FREM: return visitFREM(N);
1106 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1107 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1108 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1109 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1110 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1111 case ISD::FP_ROUND: return visitFP_ROUND(N);
1112 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1113 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1114 case ISD::FNEG: return visitFNEG(N);
1115 case ISD::FABS: return visitFABS(N);
1116 case ISD::BRCOND: return visitBRCOND(N);
1117 case ISD::BR_CC: return visitBR_CC(N);
1118 case ISD::LOAD: return visitLOAD(N);
1119 case ISD::STORE: return visitSTORE(N);
1120 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1121 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1122 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1123 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1124 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1125 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1126 case ISD::MEMBARRIER: return visitMEMBARRIER(N);
1131 SDValue DAGCombiner::combine(SDNode *N) {
1132 SDValue RV = visit(N);
1134 // If nothing happened, try a target-specific DAG combine.
1135 if (RV.getNode() == 0) {
1136 assert(N->getOpcode() != ISD::DELETED_NODE &&
1137 "Node was deleted but visit returned NULL!");
1139 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1140 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1142 // Expose the DAG combiner to the target combiner impls.
1143 TargetLowering::DAGCombinerInfo
1144 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
1146 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1150 // If nothing happened still, try promoting the operation.
1151 if (RV.getNode() == 0) {
1152 switch (N->getOpcode()) {
1160 RV = PromoteIntBinOp(SDValue(N, 0));
1165 RV = PromoteIntShiftOp(SDValue(N, 0));
1167 case ISD::SIGN_EXTEND:
1168 case ISD::ZERO_EXTEND:
1169 case ISD::ANY_EXTEND:
1170 RV = PromoteExtend(SDValue(N, 0));
1173 if (PromoteLoad(SDValue(N, 0)))
1179 // If N is a commutative binary node, try commuting it to enable more
1181 if (RV.getNode() == 0 &&
1182 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1183 N->getNumValues() == 1) {
1184 SDValue N0 = N->getOperand(0);
1185 SDValue N1 = N->getOperand(1);
1187 // Constant operands are canonicalized to RHS.
1188 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1189 SDValue Ops[] = { N1, N0 };
1190 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1193 return SDValue(CSENode, 0);
1200 /// getInputChainForNode - Given a node, return its input chain if it has one,
1201 /// otherwise return a null sd operand.
1202 static SDValue getInputChainForNode(SDNode *N) {
1203 if (unsigned NumOps = N->getNumOperands()) {
1204 if (N->getOperand(0).getValueType() == MVT::Other)
1205 return N->getOperand(0);
1206 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1207 return N->getOperand(NumOps-1);
1208 for (unsigned i = 1; i < NumOps-1; ++i)
1209 if (N->getOperand(i).getValueType() == MVT::Other)
1210 return N->getOperand(i);
1215 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1216 // If N has two operands, where one has an input chain equal to the other,
1217 // the 'other' chain is redundant.
1218 if (N->getNumOperands() == 2) {
1219 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1220 return N->getOperand(0);
1221 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1222 return N->getOperand(1);
1225 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1226 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1227 SmallPtrSet<SDNode*, 16> SeenOps;
1228 bool Changed = false; // If we should replace this token factor.
1230 // Start out with this token factor.
1233 // Iterate through token factors. The TFs grows when new token factors are
1235 for (unsigned i = 0; i < TFs.size(); ++i) {
1236 SDNode *TF = TFs[i];
1238 // Check each of the operands.
1239 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1240 SDValue Op = TF->getOperand(i);
1242 switch (Op.getOpcode()) {
1243 case ISD::EntryToken:
1244 // Entry tokens don't need to be added to the list. They are
1249 case ISD::TokenFactor:
1250 if (Op.hasOneUse() &&
1251 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1252 // Queue up for processing.
1253 TFs.push_back(Op.getNode());
1254 // Clean up in case the token factor is removed.
1255 AddToWorkList(Op.getNode());
1262 // Only add if it isn't already in the list.
1263 if (SeenOps.insert(Op.getNode()))
1274 // If we've change things around then replace token factor.
1277 // The entry token is the only possible outcome.
1278 Result = DAG.getEntryNode();
1280 // New and improved token factor.
1281 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
1282 MVT::Other, &Ops[0], Ops.size());
1285 // Don't add users to work list.
1286 return CombineTo(N, Result, false);
1292 /// MERGE_VALUES can always be eliminated.
1293 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1294 WorkListRemover DeadNodes(*this);
1295 // Replacing results may cause a different MERGE_VALUES to suddenly
1296 // be CSE'd with N, and carry its uses with it. Iterate until no
1297 // uses remain, to ensure that the node can be safely deleted.
1299 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1300 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
1302 } while (!N->use_empty());
1303 removeFromWorkList(N);
1305 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1309 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
1310 SelectionDAG &DAG) {
1311 EVT VT = N0.getValueType();
1312 SDValue N00 = N0.getOperand(0);
1313 SDValue N01 = N0.getOperand(1);
1314 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1316 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1317 isa<ConstantSDNode>(N00.getOperand(1))) {
1318 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1319 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1320 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1321 N00.getOperand(0), N01),
1322 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1323 N00.getOperand(1), N01));
1324 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1330 SDValue DAGCombiner::visitADD(SDNode *N) {
1331 SDValue N0 = N->getOperand(0);
1332 SDValue N1 = N->getOperand(1);
1333 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1334 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1335 EVT VT = N0.getValueType();
1338 if (VT.isVector()) {
1339 SDValue FoldedVOp = SimplifyVBinOp(N);
1340 if (FoldedVOp.getNode()) return FoldedVOp;
1343 // fold (add x, undef) -> undef
1344 if (N0.getOpcode() == ISD::UNDEF)
1346 if (N1.getOpcode() == ISD::UNDEF)
1348 // fold (add c1, c2) -> c1+c2
1350 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1351 // canonicalize constant to RHS
1353 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1354 // fold (add x, 0) -> x
1355 if (N1C && N1C->isNullValue())
1357 // fold (add Sym, c) -> Sym+c
1358 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1359 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1360 GA->getOpcode() == ISD::GlobalAddress)
1361 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1363 (uint64_t)N1C->getSExtValue());
1364 // fold ((c1-A)+c2) -> (c1+c2)-A
1365 if (N1C && N0.getOpcode() == ISD::SUB)
1366 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1367 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1368 DAG.getConstant(N1C->getAPIntValue()+
1369 N0C->getAPIntValue(), VT),
1372 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1373 if (RADD.getNode() != 0)
1375 // fold ((0-A) + B) -> B-A
1376 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1377 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1378 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1379 // fold (A + (0-B)) -> A-B
1380 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1381 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1382 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1383 // fold (A+(B-A)) -> B
1384 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1385 return N1.getOperand(0);
1386 // fold ((B-A)+A) -> B
1387 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1388 return N0.getOperand(0);
1389 // fold (A+(B-(A+C))) to (B-C)
1390 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1391 N0 == N1.getOperand(1).getOperand(0))
1392 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1393 N1.getOperand(1).getOperand(1));
1394 // fold (A+(B-(C+A))) to (B-C)
1395 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1396 N0 == N1.getOperand(1).getOperand(1))
1397 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1398 N1.getOperand(1).getOperand(0));
1399 // fold (A+((B-A)+or-C)) to (B+or-C)
1400 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1401 N1.getOperand(0).getOpcode() == ISD::SUB &&
1402 N0 == N1.getOperand(0).getOperand(1))
1403 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1404 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1406 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1407 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1408 SDValue N00 = N0.getOperand(0);
1409 SDValue N01 = N0.getOperand(1);
1410 SDValue N10 = N1.getOperand(0);
1411 SDValue N11 = N1.getOperand(1);
1413 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1414 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1415 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1416 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1419 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1420 return SDValue(N, 0);
1422 // fold (a+b) -> (a|b) iff a and b share no bits.
1423 if (VT.isInteger() && !VT.isVector()) {
1424 APInt LHSZero, LHSOne;
1425 APInt RHSZero, RHSOne;
1426 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1427 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1429 if (LHSZero.getBoolValue()) {
1430 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1432 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1433 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1434 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1435 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1436 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1440 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1441 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1442 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1443 if (Result.getNode()) return Result;
1445 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1446 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1447 if (Result.getNode()) return Result;
1450 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1451 if (N1.getOpcode() == ISD::SHL &&
1452 N1.getOperand(0).getOpcode() == ISD::SUB)
1453 if (ConstantSDNode *C =
1454 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1455 if (C->getAPIntValue() == 0)
1456 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1457 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1458 N1.getOperand(0).getOperand(1),
1460 if (N0.getOpcode() == ISD::SHL &&
1461 N0.getOperand(0).getOpcode() == ISD::SUB)
1462 if (ConstantSDNode *C =
1463 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1464 if (C->getAPIntValue() == 0)
1465 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1466 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1467 N0.getOperand(0).getOperand(1),
1470 if (N1.getOpcode() == ISD::AND) {
1471 SDValue AndOp0 = N1.getOperand(0);
1472 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1473 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1474 unsigned DestBits = VT.getScalarType().getSizeInBits();
1476 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1477 // and similar xforms where the inner op is either ~0 or 0.
1478 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1479 DebugLoc DL = N->getDebugLoc();
1480 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1484 // add (sext i1), X -> sub X, (zext i1)
1485 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1486 N0.getOperand(0).getValueType() == MVT::i1 &&
1487 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1488 DebugLoc DL = N->getDebugLoc();
1489 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1490 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1496 SDValue DAGCombiner::visitADDC(SDNode *N) {
1497 SDValue N0 = N->getOperand(0);
1498 SDValue N1 = N->getOperand(1);
1499 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1500 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1501 EVT VT = N0.getValueType();
1503 // If the flag result is dead, turn this into an ADD.
1504 if (!N->hasAnyUseOfValue(1))
1505 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1),
1506 DAG.getNode(ISD::CARRY_FALSE,
1507 N->getDebugLoc(), MVT::Glue));
1509 // canonicalize constant to RHS.
1511 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1513 // fold (addc x, 0) -> x + no carry out
1514 if (N1C && N1C->isNullValue())
1515 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1516 N->getDebugLoc(), MVT::Glue));
1518 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1519 APInt LHSZero, LHSOne;
1520 APInt RHSZero, RHSOne;
1521 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1522 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1524 if (LHSZero.getBoolValue()) {
1525 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1527 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1528 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1529 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1530 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1531 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1532 DAG.getNode(ISD::CARRY_FALSE,
1533 N->getDebugLoc(), MVT::Glue));
1539 SDValue DAGCombiner::visitADDE(SDNode *N) {
1540 SDValue N0 = N->getOperand(0);
1541 SDValue N1 = N->getOperand(1);
1542 SDValue CarryIn = N->getOperand(2);
1543 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1544 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1546 // canonicalize constant to RHS
1548 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1551 // fold (adde x, y, false) -> (addc x, y)
1552 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1553 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1);
1558 // Since it may not be valid to emit a fold to zero for vector initializers
1559 // check if we can before folding.
1560 static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT,
1561 SelectionDAG &DAG, bool LegalOperations) {
1562 if (!VT.isVector()) {
1563 return DAG.getConstant(0, VT);
1565 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1566 // Produce a vector of zeros.
1567 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
1568 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
1569 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
1570 &Ops[0], Ops.size());
1575 SDValue DAGCombiner::visitSUB(SDNode *N) {
1576 SDValue N0 = N->getOperand(0);
1577 SDValue N1 = N->getOperand(1);
1578 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1579 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1580 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 :
1581 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1582 EVT VT = N0.getValueType();
1585 if (VT.isVector()) {
1586 SDValue FoldedVOp = SimplifyVBinOp(N);
1587 if (FoldedVOp.getNode()) return FoldedVOp;
1590 // fold (sub x, x) -> 0
1591 // FIXME: Refactor this and xor and other similar operations together.
1593 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
1594 // fold (sub c1, c2) -> c1-c2
1596 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1597 // fold (sub x, c) -> (add x, -c)
1599 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1600 DAG.getConstant(-N1C->getAPIntValue(), VT));
1601 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1602 if (N0C && N0C->isAllOnesValue())
1603 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1604 // fold A-(A-B) -> B
1605 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1606 return N1.getOperand(1);
1607 // fold (A+B)-A -> B
1608 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1609 return N0.getOperand(1);
1610 // fold (A+B)-B -> A
1611 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1612 return N0.getOperand(0);
1613 // fold C2-(A+C1) -> (C2-C1)-A
1614 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1615 SDValue NewC = DAG.getConstant((N0C->getAPIntValue() - N1C1->getAPIntValue()), VT);
1616 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC,
1619 // fold ((A+(B+or-C))-B) -> A+or-C
1620 if (N0.getOpcode() == ISD::ADD &&
1621 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1622 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1623 N0.getOperand(1).getOperand(0) == N1)
1624 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1625 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1626 // fold ((A+(C+B))-B) -> A+C
1627 if (N0.getOpcode() == ISD::ADD &&
1628 N0.getOperand(1).getOpcode() == ISD::ADD &&
1629 N0.getOperand(1).getOperand(1) == N1)
1630 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1631 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1632 // fold ((A-(B-C))-C) -> A-B
1633 if (N0.getOpcode() == ISD::SUB &&
1634 N0.getOperand(1).getOpcode() == ISD::SUB &&
1635 N0.getOperand(1).getOperand(1) == N1)
1636 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1637 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1639 // If either operand of a sub is undef, the result is undef
1640 if (N0.getOpcode() == ISD::UNDEF)
1642 if (N1.getOpcode() == ISD::UNDEF)
1645 // If the relocation model supports it, consider symbol offsets.
1646 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1647 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1648 // fold (sub Sym, c) -> Sym-c
1649 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1650 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1652 (uint64_t)N1C->getSExtValue());
1653 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1654 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1655 if (GA->getGlobal() == GB->getGlobal())
1656 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1663 SDValue DAGCombiner::visitSUBC(SDNode *N) {
1664 SDValue N0 = N->getOperand(0);
1665 SDValue N1 = N->getOperand(1);
1666 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1667 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1668 EVT VT = N0.getValueType();
1670 // If the flag result is dead, turn this into an SUB.
1671 if (!N->hasAnyUseOfValue(1))
1672 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1),
1673 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1676 // fold (subc x, x) -> 0 + no borrow
1678 return CombineTo(N, DAG.getConstant(0, VT),
1679 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1682 // fold (subc x, 0) -> x + no borrow
1683 if (N1C && N1C->isNullValue())
1684 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1687 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
1688 if (N0C && N0C->isAllOnesValue())
1689 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0),
1690 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1696 SDValue DAGCombiner::visitSUBE(SDNode *N) {
1697 SDValue N0 = N->getOperand(0);
1698 SDValue N1 = N->getOperand(1);
1699 SDValue CarryIn = N->getOperand(2);
1701 // fold (sube x, y, false) -> (subc x, y)
1702 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1703 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1);
1708 SDValue DAGCombiner::visitMUL(SDNode *N) {
1709 SDValue N0 = N->getOperand(0);
1710 SDValue N1 = N->getOperand(1);
1711 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1712 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1713 EVT VT = N0.getValueType();
1716 if (VT.isVector()) {
1717 SDValue FoldedVOp = SimplifyVBinOp(N);
1718 if (FoldedVOp.getNode()) return FoldedVOp;
1721 // fold (mul x, undef) -> 0
1722 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1723 return DAG.getConstant(0, VT);
1724 // fold (mul c1, c2) -> c1*c2
1726 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1727 // canonicalize constant to RHS
1729 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1730 // fold (mul x, 0) -> 0
1731 if (N1C && N1C->isNullValue())
1733 // fold (mul x, -1) -> 0-x
1734 if (N1C && N1C->isAllOnesValue())
1735 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1736 DAG.getConstant(0, VT), N0);
1737 // fold (mul x, (1 << c)) -> x << c
1738 if (N1C && N1C->getAPIntValue().isPowerOf2())
1739 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1740 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1741 getShiftAmountTy(N0.getValueType())));
1742 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1743 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1744 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1745 // FIXME: If the input is something that is easily negated (e.g. a
1746 // single-use add), we should put the negate there.
1747 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1748 DAG.getConstant(0, VT),
1749 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1750 DAG.getConstant(Log2Val,
1751 getShiftAmountTy(N0.getValueType()))));
1753 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1754 if (N1C && N0.getOpcode() == ISD::SHL &&
1755 isa<ConstantSDNode>(N0.getOperand(1))) {
1756 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1757 N1, N0.getOperand(1));
1758 AddToWorkList(C3.getNode());
1759 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1760 N0.getOperand(0), C3);
1763 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1766 SDValue Sh(0,0), Y(0,0);
1767 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1768 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1769 N0.getNode()->hasOneUse()) {
1771 } else if (N1.getOpcode() == ISD::SHL &&
1772 isa<ConstantSDNode>(N1.getOperand(1)) &&
1773 N1.getNode()->hasOneUse()) {
1778 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1779 Sh.getOperand(0), Y);
1780 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1781 Mul, Sh.getOperand(1));
1785 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1786 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1787 isa<ConstantSDNode>(N0.getOperand(1)))
1788 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1789 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1790 N0.getOperand(0), N1),
1791 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1792 N0.getOperand(1), N1));
1795 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1796 if (RMUL.getNode() != 0)
1802 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1803 SDValue N0 = N->getOperand(0);
1804 SDValue N1 = N->getOperand(1);
1805 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1806 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1807 EVT VT = N->getValueType(0);
1810 if (VT.isVector()) {
1811 SDValue FoldedVOp = SimplifyVBinOp(N);
1812 if (FoldedVOp.getNode()) return FoldedVOp;
1815 // fold (sdiv c1, c2) -> c1/c2
1816 if (N0C && N1C && !N1C->isNullValue())
1817 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1818 // fold (sdiv X, 1) -> X
1819 if (N1C && N1C->getAPIntValue() == 1LL)
1821 // fold (sdiv X, -1) -> 0-X
1822 if (N1C && N1C->isAllOnesValue())
1823 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1824 DAG.getConstant(0, VT), N0);
1825 // If we know the sign bits of both operands are zero, strength reduce to a
1826 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1827 if (!VT.isVector()) {
1828 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1829 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1832 // fold (sdiv X, pow2) -> simple ops after legalize
1833 if (N1C && !N1C->isNullValue() &&
1834 (N1C->getAPIntValue().isPowerOf2() ||
1835 (-N1C->getAPIntValue()).isPowerOf2())) {
1836 // If dividing by powers of two is cheap, then don't perform the following
1838 if (TLI.isPow2DivCheap())
1841 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
1843 // Splat the sign bit into the register
1844 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1845 DAG.getConstant(VT.getSizeInBits()-1,
1846 getShiftAmountTy(N0.getValueType())));
1847 AddToWorkList(SGN.getNode());
1849 // Add (N0 < 0) ? abs2 - 1 : 0;
1850 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1851 DAG.getConstant(VT.getSizeInBits() - lg2,
1852 getShiftAmountTy(SGN.getValueType())));
1853 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1854 AddToWorkList(SRL.getNode());
1855 AddToWorkList(ADD.getNode()); // Divide by pow2
1856 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1857 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
1859 // If we're dividing by a positive value, we're done. Otherwise, we must
1860 // negate the result.
1861 if (N1C->getAPIntValue().isNonNegative())
1864 AddToWorkList(SRA.getNode());
1865 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1866 DAG.getConstant(0, VT), SRA);
1869 // if integer divide is expensive and we satisfy the requirements, emit an
1870 // alternate sequence.
1871 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1872 SDValue Op = BuildSDIV(N);
1873 if (Op.getNode()) return Op;
1877 if (N0.getOpcode() == ISD::UNDEF)
1878 return DAG.getConstant(0, VT);
1879 // X / undef -> undef
1880 if (N1.getOpcode() == ISD::UNDEF)
1886 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1887 SDValue N0 = N->getOperand(0);
1888 SDValue N1 = N->getOperand(1);
1889 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1890 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1891 EVT VT = N->getValueType(0);
1894 if (VT.isVector()) {
1895 SDValue FoldedVOp = SimplifyVBinOp(N);
1896 if (FoldedVOp.getNode()) return FoldedVOp;
1899 // fold (udiv c1, c2) -> c1/c2
1900 if (N0C && N1C && !N1C->isNullValue())
1901 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1902 // fold (udiv x, (1 << c)) -> x >>u c
1903 if (N1C && N1C->getAPIntValue().isPowerOf2())
1904 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1905 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1906 getShiftAmountTy(N0.getValueType())));
1907 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1908 if (N1.getOpcode() == ISD::SHL) {
1909 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1910 if (SHC->getAPIntValue().isPowerOf2()) {
1911 EVT ADDVT = N1.getOperand(1).getValueType();
1912 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1914 DAG.getConstant(SHC->getAPIntValue()
1917 AddToWorkList(Add.getNode());
1918 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1922 // fold (udiv x, c) -> alternate
1923 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1924 SDValue Op = BuildUDIV(N);
1925 if (Op.getNode()) return Op;
1929 if (N0.getOpcode() == ISD::UNDEF)
1930 return DAG.getConstant(0, VT);
1931 // X / undef -> undef
1932 if (N1.getOpcode() == ISD::UNDEF)
1938 SDValue DAGCombiner::visitSREM(SDNode *N) {
1939 SDValue N0 = N->getOperand(0);
1940 SDValue N1 = N->getOperand(1);
1941 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1942 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1943 EVT VT = N->getValueType(0);
1945 // fold (srem c1, c2) -> c1%c2
1946 if (N0C && N1C && !N1C->isNullValue())
1947 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1948 // If we know the sign bits of both operands are zero, strength reduce to a
1949 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1950 if (!VT.isVector()) {
1951 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1952 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1955 // If X/C can be simplified by the division-by-constant logic, lower
1956 // X%C to the equivalent of X-X/C*C.
1957 if (N1C && !N1C->isNullValue()) {
1958 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1959 AddToWorkList(Div.getNode());
1960 SDValue OptimizedDiv = combine(Div.getNode());
1961 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1962 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1964 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1965 AddToWorkList(Mul.getNode());
1971 if (N0.getOpcode() == ISD::UNDEF)
1972 return DAG.getConstant(0, VT);
1973 // X % undef -> undef
1974 if (N1.getOpcode() == ISD::UNDEF)
1980 SDValue DAGCombiner::visitUREM(SDNode *N) {
1981 SDValue N0 = N->getOperand(0);
1982 SDValue N1 = N->getOperand(1);
1983 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1984 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1985 EVT VT = N->getValueType(0);
1987 // fold (urem c1, c2) -> c1%c2
1988 if (N0C && N1C && !N1C->isNullValue())
1989 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
1990 // fold (urem x, pow2) -> (and x, pow2-1)
1991 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
1992 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
1993 DAG.getConstant(N1C->getAPIntValue()-1,VT));
1994 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1995 if (N1.getOpcode() == ISD::SHL) {
1996 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1997 if (SHC->getAPIntValue().isPowerOf2()) {
1999 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
2000 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
2002 AddToWorkList(Add.getNode());
2003 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
2008 // If X/C can be simplified by the division-by-constant logic, lower
2009 // X%C to the equivalent of X-X/C*C.
2010 if (N1C && !N1C->isNullValue()) {
2011 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
2012 AddToWorkList(Div.getNode());
2013 SDValue OptimizedDiv = combine(Div.getNode());
2014 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2015 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
2017 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
2018 AddToWorkList(Mul.getNode());
2024 if (N0.getOpcode() == ISD::UNDEF)
2025 return DAG.getConstant(0, VT);
2026 // X % undef -> undef
2027 if (N1.getOpcode() == ISD::UNDEF)
2033 SDValue DAGCombiner::visitMULHS(SDNode *N) {
2034 SDValue N0 = N->getOperand(0);
2035 SDValue N1 = N->getOperand(1);
2036 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2037 EVT VT = N->getValueType(0);
2038 DebugLoc DL = N->getDebugLoc();
2040 // fold (mulhs x, 0) -> 0
2041 if (N1C && N1C->isNullValue())
2043 // fold (mulhs x, 1) -> (sra x, size(x)-1)
2044 if (N1C && N1C->getAPIntValue() == 1)
2045 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
2046 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2047 getShiftAmountTy(N0.getValueType())));
2048 // fold (mulhs x, undef) -> 0
2049 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2050 return DAG.getConstant(0, VT);
2052 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2054 if (VT.isSimple() && !VT.isVector()) {
2055 MVT Simple = VT.getSimpleVT();
2056 unsigned SimpleSize = Simple.getSizeInBits();
2057 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2058 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2059 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2060 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2061 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2062 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2063 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2064 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2071 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2072 SDValue N0 = N->getOperand(0);
2073 SDValue N1 = N->getOperand(1);
2074 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2075 EVT VT = N->getValueType(0);
2076 DebugLoc DL = N->getDebugLoc();
2078 // fold (mulhu x, 0) -> 0
2079 if (N1C && N1C->isNullValue())
2081 // fold (mulhu x, 1) -> 0
2082 if (N1C && N1C->getAPIntValue() == 1)
2083 return DAG.getConstant(0, N0.getValueType());
2084 // fold (mulhu x, undef) -> 0
2085 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2086 return DAG.getConstant(0, VT);
2088 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2090 if (VT.isSimple() && !VT.isVector()) {
2091 MVT Simple = VT.getSimpleVT();
2092 unsigned SimpleSize = Simple.getSizeInBits();
2093 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2094 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2095 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2096 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2097 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2098 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2099 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2100 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2107 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
2108 /// compute two values. LoOp and HiOp give the opcodes for the two computations
2109 /// that are being performed. Return true if a simplification was made.
2111 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2113 // If the high half is not needed, just compute the low half.
2114 bool HiExists = N->hasAnyUseOfValue(1);
2116 (!LegalOperations ||
2117 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
2118 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2119 N->op_begin(), N->getNumOperands());
2120 return CombineTo(N, Res, Res);
2123 // If the low half is not needed, just compute the high half.
2124 bool LoExists = N->hasAnyUseOfValue(0);
2126 (!LegalOperations ||
2127 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2128 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2129 N->op_begin(), N->getNumOperands());
2130 return CombineTo(N, Res, Res);
2133 // If both halves are used, return as it is.
2134 if (LoExists && HiExists)
2137 // If the two computed results can be simplified separately, separate them.
2139 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2140 N->op_begin(), N->getNumOperands());
2141 AddToWorkList(Lo.getNode());
2142 SDValue LoOpt = combine(Lo.getNode());
2143 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2144 (!LegalOperations ||
2145 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2146 return CombineTo(N, LoOpt, LoOpt);
2150 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2151 N->op_begin(), N->getNumOperands());
2152 AddToWorkList(Hi.getNode());
2153 SDValue HiOpt = combine(Hi.getNode());
2154 if (HiOpt.getNode() && HiOpt != Hi &&
2155 (!LegalOperations ||
2156 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2157 return CombineTo(N, HiOpt, HiOpt);
2163 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2164 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2165 if (Res.getNode()) return Res;
2167 EVT VT = N->getValueType(0);
2168 DebugLoc DL = N->getDebugLoc();
2170 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2172 if (VT.isSimple() && !VT.isVector()) {
2173 MVT Simple = VT.getSimpleVT();
2174 unsigned SimpleSize = Simple.getSizeInBits();
2175 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2176 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2177 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2178 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2179 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2180 // Compute the high part as N1.
2181 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2182 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2183 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2184 // Compute the low part as N0.
2185 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2186 return CombineTo(N, Lo, Hi);
2193 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2194 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2195 if (Res.getNode()) return Res;
2197 EVT VT = N->getValueType(0);
2198 DebugLoc DL = N->getDebugLoc();
2200 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2202 if (VT.isSimple() && !VT.isVector()) {
2203 MVT Simple = VT.getSimpleVT();
2204 unsigned SimpleSize = Simple.getSizeInBits();
2205 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2206 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2207 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2208 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2209 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2210 // Compute the high part as N1.
2211 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2212 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2213 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2214 // Compute the low part as N0.
2215 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2216 return CombineTo(N, Lo, Hi);
2223 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2224 // (smulo x, 2) -> (saddo x, x)
2225 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2226 if (C2->getAPIntValue() == 2)
2227 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(),
2228 N->getOperand(0), N->getOperand(0));
2233 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2234 // (umulo x, 2) -> (uaddo x, x)
2235 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2236 if (C2->getAPIntValue() == 2)
2237 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(),
2238 N->getOperand(0), N->getOperand(0));
2243 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2244 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2245 if (Res.getNode()) return Res;
2250 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2251 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2252 if (Res.getNode()) return Res;
2257 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2258 /// two operands of the same opcode, try to simplify it.
2259 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2260 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2261 EVT VT = N0.getValueType();
2262 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2264 // Bail early if none of these transforms apply.
2265 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2267 // For each of OP in AND/OR/XOR:
2268 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2269 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2270 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2271 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2273 // do not sink logical op inside of a vector extend, since it may combine
2275 EVT Op0VT = N0.getOperand(0).getValueType();
2276 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2277 N0.getOpcode() == ISD::SIGN_EXTEND ||
2278 // Avoid infinite looping with PromoteIntBinOp.
2279 (N0.getOpcode() == ISD::ANY_EXTEND &&
2280 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2281 (N0.getOpcode() == ISD::TRUNCATE &&
2282 (!TLI.isZExtFree(VT, Op0VT) ||
2283 !TLI.isTruncateFree(Op0VT, VT)) &&
2284 TLI.isTypeLegal(Op0VT))) &&
2286 Op0VT == N1.getOperand(0).getValueType() &&
2287 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2288 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2289 N0.getOperand(0).getValueType(),
2290 N0.getOperand(0), N1.getOperand(0));
2291 AddToWorkList(ORNode.getNode());
2292 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
2295 // For each of OP in SHL/SRL/SRA/AND...
2296 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2297 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2298 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2299 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2300 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2301 N0.getOperand(1) == N1.getOperand(1)) {
2302 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2303 N0.getOperand(0).getValueType(),
2304 N0.getOperand(0), N1.getOperand(0));
2305 AddToWorkList(ORNode.getNode());
2306 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
2307 ORNode, N0.getOperand(1));
2313 SDValue DAGCombiner::visitAND(SDNode *N) {
2314 SDValue N0 = N->getOperand(0);
2315 SDValue N1 = N->getOperand(1);
2316 SDValue LL, LR, RL, RR, CC0, CC1;
2317 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2318 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2319 EVT VT = N1.getValueType();
2320 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2323 if (VT.isVector()) {
2324 SDValue FoldedVOp = SimplifyVBinOp(N);
2325 if (FoldedVOp.getNode()) return FoldedVOp;
2328 // fold (and x, undef) -> 0
2329 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2330 return DAG.getConstant(0, VT);
2331 // fold (and c1, c2) -> c1&c2
2333 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2334 // canonicalize constant to RHS
2336 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
2337 // fold (and x, -1) -> x
2338 if (N1C && N1C->isAllOnesValue())
2340 // if (and x, c) is known to be zero, return 0
2341 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2342 APInt::getAllOnesValue(BitWidth)))
2343 return DAG.getConstant(0, VT);
2345 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
2346 if (RAND.getNode() != 0)
2348 // fold (and (or x, C), D) -> D if (C & D) == D
2349 if (N1C && N0.getOpcode() == ISD::OR)
2350 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2351 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2353 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2354 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2355 SDValue N0Op0 = N0.getOperand(0);
2356 APInt Mask = ~N1C->getAPIntValue();
2357 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2358 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2359 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
2360 N0.getValueType(), N0Op0);
2362 // Replace uses of the AND with uses of the Zero extend node.
2365 // We actually want to replace all uses of the any_extend with the
2366 // zero_extend, to avoid duplicating things. This will later cause this
2367 // AND to be folded.
2368 CombineTo(N0.getNode(), Zext);
2369 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2372 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2373 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2374 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2375 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2377 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2378 LL.getValueType().isInteger()) {
2379 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2380 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2381 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2382 LR.getValueType(), LL, RL);
2383 AddToWorkList(ORNode.getNode());
2384 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2386 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2387 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2388 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
2389 LR.getValueType(), LL, RL);
2390 AddToWorkList(ANDNode.getNode());
2391 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2393 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2394 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2395 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2396 LR.getValueType(), LL, RL);
2397 AddToWorkList(ORNode.getNode());
2398 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2401 // canonicalize equivalent to ll == rl
2402 if (LL == RR && LR == RL) {
2403 Op1 = ISD::getSetCCSwappedOperands(Op1);
2406 if (LL == RL && LR == RR) {
2407 bool isInteger = LL.getValueType().isInteger();
2408 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2409 if (Result != ISD::SETCC_INVALID &&
2410 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2411 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2416 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2417 if (N0.getOpcode() == N1.getOpcode()) {
2418 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2419 if (Tmp.getNode()) return Tmp;
2422 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2423 // fold (and (sra)) -> (and (srl)) when possible.
2424 if (!VT.isVector() &&
2425 SimplifyDemandedBits(SDValue(N, 0)))
2426 return SDValue(N, 0);
2428 // fold (zext_inreg (extload x)) -> (zextload x)
2429 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2430 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2431 EVT MemVT = LN0->getMemoryVT();
2432 // If we zero all the possible extended bits, then we can turn this into
2433 // a zextload if we are running before legalize or the operation is legal.
2434 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2435 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2436 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2437 ((!LegalOperations && !LN0->isVolatile()) ||
2438 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2439 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2440 LN0->getChain(), LN0->getBasePtr(),
2441 LN0->getPointerInfo(), MemVT,
2442 LN0->isVolatile(), LN0->isNonTemporal(),
2443 LN0->getAlignment());
2445 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2446 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2449 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2450 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2452 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2453 EVT MemVT = LN0->getMemoryVT();
2454 // If we zero all the possible extended bits, then we can turn this into
2455 // a zextload if we are running before legalize or the operation is legal.
2456 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2457 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2458 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2459 ((!LegalOperations && !LN0->isVolatile()) ||
2460 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2461 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2463 LN0->getBasePtr(), LN0->getPointerInfo(),
2465 LN0->isVolatile(), LN0->isNonTemporal(),
2466 LN0->getAlignment());
2468 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2469 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2473 // fold (and (load x), 255) -> (zextload x, i8)
2474 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2475 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2476 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2477 (N0.getOpcode() == ISD::ANY_EXTEND &&
2478 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2479 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2480 LoadSDNode *LN0 = HasAnyExt
2481 ? cast<LoadSDNode>(N0.getOperand(0))
2482 : cast<LoadSDNode>(N0);
2483 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2484 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2485 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2486 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2487 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2488 EVT LoadedVT = LN0->getMemoryVT();
2490 if (ExtVT == LoadedVT &&
2491 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2492 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2495 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2496 LN0->getChain(), LN0->getBasePtr(),
2497 LN0->getPointerInfo(),
2498 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2499 LN0->getAlignment());
2501 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2502 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2505 // Do not change the width of a volatile load.
2506 // Do not generate loads of non-round integer types since these can
2507 // be expensive (and would be wrong if the type is not byte sized).
2508 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2509 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2510 EVT PtrType = LN0->getOperand(1).getValueType();
2512 unsigned Alignment = LN0->getAlignment();
2513 SDValue NewPtr = LN0->getBasePtr();
2515 // For big endian targets, we need to add an offset to the pointer
2516 // to load the correct bytes. For little endian systems, we merely
2517 // need to read fewer bytes from the same pointer.
2518 if (TLI.isBigEndian()) {
2519 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2520 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2521 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2522 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2523 NewPtr, DAG.getConstant(PtrOff, PtrType));
2524 Alignment = MinAlign(Alignment, PtrOff);
2527 AddToWorkList(NewPtr.getNode());
2529 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2531 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2532 LN0->getChain(), NewPtr,
2533 LN0->getPointerInfo(),
2534 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2537 CombineTo(LN0, Load, Load.getValue(1));
2538 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2547 /// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16
2549 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
2550 bool DemandHighBits) {
2551 if (!LegalOperations)
2554 EVT VT = N->getValueType(0);
2555 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
2557 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2560 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
2561 bool LookPassAnd0 = false;
2562 bool LookPassAnd1 = false;
2563 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2565 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
2567 if (N0.getOpcode() == ISD::AND) {
2568 if (!N0.getNode()->hasOneUse())
2570 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2571 if (!N01C || N01C->getZExtValue() != 0xFF00)
2573 N0 = N0.getOperand(0);
2574 LookPassAnd0 = true;
2577 if (N1.getOpcode() == ISD::AND) {
2578 if (!N1.getNode()->hasOneUse())
2580 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2581 if (!N11C || N11C->getZExtValue() != 0xFF)
2583 N1 = N1.getOperand(0);
2584 LookPassAnd1 = true;
2587 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2589 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2591 if (!N0.getNode()->hasOneUse() ||
2592 !N1.getNode()->hasOneUse())
2595 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2596 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2599 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
2602 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
2603 SDValue N00 = N0->getOperand(0);
2604 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
2605 if (!N00.getNode()->hasOneUse())
2607 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
2608 if (!N001C || N001C->getZExtValue() != 0xFF)
2610 N00 = N00.getOperand(0);
2611 LookPassAnd0 = true;
2614 SDValue N10 = N1->getOperand(0);
2615 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
2616 if (!N10.getNode()->hasOneUse())
2618 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
2619 if (!N101C || N101C->getZExtValue() != 0xFF00)
2621 N10 = N10.getOperand(0);
2622 LookPassAnd1 = true;
2628 // Make sure everything beyond the low halfword is zero since the SRL 16
2629 // will clear the top bits.
2630 unsigned OpSizeInBits = VT.getSizeInBits();
2631 if (DemandHighBits && OpSizeInBits > 16 &&
2632 (!LookPassAnd0 || !LookPassAnd1) &&
2633 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16)))
2636 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00);
2637 if (OpSizeInBits > 16)
2638 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res,
2639 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT)));
2643 /// isBSwapHWordElement - Return true if the specified node is an element
2644 /// that makes up a 32-bit packed halfword byteswap. i.e.
2645 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2646 static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) {
2647 if (!N.getNode()->hasOneUse())
2650 unsigned Opc = N.getOpcode();
2651 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
2654 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2659 switch (N1C->getZExtValue()) {
2662 case 0xFF: Num = 0; break;
2663 case 0xFF00: Num = 1; break;
2664 case 0xFF0000: Num = 2; break;
2665 case 0xFF000000: Num = 3; break;
2668 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
2669 SDValue N0 = N.getOperand(0);
2670 if (Opc == ISD::AND) {
2671 if (Num == 0 || Num == 2) {
2673 // (x >> 8) & 0xff0000
2674 if (N0.getOpcode() != ISD::SRL)
2676 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2677 if (!C || C->getZExtValue() != 8)
2680 // (x << 8) & 0xff00
2681 // (x << 8) & 0xff000000
2682 if (N0.getOpcode() != ISD::SHL)
2684 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2685 if (!C || C->getZExtValue() != 8)
2688 } else if (Opc == ISD::SHL) {
2690 // (x & 0xff0000) << 8
2691 if (Num != 0 && Num != 2)
2693 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2694 if (!C || C->getZExtValue() != 8)
2696 } else { // Opc == ISD::SRL
2697 // (x & 0xff00) >> 8
2698 // (x & 0xff000000) >> 8
2699 if (Num != 1 && Num != 3)
2701 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2702 if (!C || C->getZExtValue() != 8)
2709 Parts[Num] = N0.getOperand(0).getNode();
2713 /// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is
2714 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2715 /// => (rotl (bswap x), 16)
2716 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
2717 if (!LegalOperations)
2720 EVT VT = N->getValueType(0);
2723 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2726 SmallVector<SDNode*,4> Parts(4, (SDNode*)0);
2728 // (or (or (and), (and)), (or (and), (and)))
2729 // (or (or (or (and), (and)), (and)), (and))
2730 if (N0.getOpcode() != ISD::OR)
2732 SDValue N00 = N0.getOperand(0);
2733 SDValue N01 = N0.getOperand(1);
2735 if (N1.getOpcode() == ISD::OR) {
2736 // (or (or (and), (and)), (or (and), (and)))
2737 SDValue N000 = N00.getOperand(0);
2738 if (!isBSwapHWordElement(N000, Parts))
2741 SDValue N001 = N00.getOperand(1);
2742 if (!isBSwapHWordElement(N001, Parts))
2744 SDValue N010 = N01.getOperand(0);
2745 if (!isBSwapHWordElement(N010, Parts))
2747 SDValue N011 = N01.getOperand(1);
2748 if (!isBSwapHWordElement(N011, Parts))
2751 // (or (or (or (and), (and)), (and)), (and))
2752 if (!isBSwapHWordElement(N1, Parts))
2754 if (!isBSwapHWordElement(N01, Parts))
2756 if (N00.getOpcode() != ISD::OR)
2758 SDValue N000 = N00.getOperand(0);
2759 if (!isBSwapHWordElement(N000, Parts))
2761 SDValue N001 = N00.getOperand(1);
2762 if (!isBSwapHWordElement(N001, Parts))
2766 // Make sure the parts are all coming from the same node.
2767 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
2770 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT,
2771 SDValue(Parts[0],0));
2773 // Result of the bswap should be rotated by 16. If it's not legal, than
2774 // do (x << 16) | (x >> 16).
2775 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT));
2776 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
2777 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt);
2778 else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
2779 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt);
2780 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT,
2781 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt),
2782 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt));
2785 SDValue DAGCombiner::visitOR(SDNode *N) {
2786 SDValue N0 = N->getOperand(0);
2787 SDValue N1 = N->getOperand(1);
2788 SDValue LL, LR, RL, RR, CC0, CC1;
2789 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2790 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2791 EVT VT = N1.getValueType();
2794 if (VT.isVector()) {
2795 SDValue FoldedVOp = SimplifyVBinOp(N);
2796 if (FoldedVOp.getNode()) return FoldedVOp;
2799 // fold (or x, undef) -> -1
2800 if (!LegalOperations &&
2801 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
2802 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
2803 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
2805 // fold (or c1, c2) -> c1|c2
2807 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
2808 // canonicalize constant to RHS
2810 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
2811 // fold (or x, 0) -> x
2812 if (N1C && N1C->isNullValue())
2814 // fold (or x, -1) -> -1
2815 if (N1C && N1C->isAllOnesValue())
2817 // fold (or x, c) -> c iff (x & ~c) == 0
2818 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
2821 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
2822 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
2823 if (BSwap.getNode() != 0)
2825 BSwap = MatchBSwapHWordLow(N, N0, N1);
2826 if (BSwap.getNode() != 0)
2830 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
2831 if (ROR.getNode() != 0)
2833 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
2834 // iff (c1 & c2) == 0.
2835 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
2836 isa<ConstantSDNode>(N0.getOperand(1))) {
2837 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
2838 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
2839 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
2840 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2841 N0.getOperand(0), N1),
2842 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
2844 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
2845 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2846 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2847 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2849 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2850 LL.getValueType().isInteger()) {
2851 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
2852 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
2853 if (cast<ConstantSDNode>(LR)->isNullValue() &&
2854 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
2855 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
2856 LR.getValueType(), LL, RL);
2857 AddToWorkList(ORNode.getNode());
2858 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2860 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
2861 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
2862 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2863 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
2864 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
2865 LR.getValueType(), LL, RL);
2866 AddToWorkList(ANDNode.getNode());
2867 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2870 // canonicalize equivalent to ll == rl
2871 if (LL == RR && LR == RL) {
2872 Op1 = ISD::getSetCCSwappedOperands(Op1);
2875 if (LL == RL && LR == RR) {
2876 bool isInteger = LL.getValueType().isInteger();
2877 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
2878 if (Result != ISD::SETCC_INVALID &&
2879 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2880 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2885 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
2886 if (N0.getOpcode() == N1.getOpcode()) {
2887 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2888 if (Tmp.getNode()) return Tmp;
2891 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
2892 if (N0.getOpcode() == ISD::AND &&
2893 N1.getOpcode() == ISD::AND &&
2894 N0.getOperand(1).getOpcode() == ISD::Constant &&
2895 N1.getOperand(1).getOpcode() == ISD::Constant &&
2896 // Don't increase # computations.
2897 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
2898 // We can only do this xform if we know that bits from X that are set in C2
2899 // but not in C1 are already zero. Likewise for Y.
2900 const APInt &LHSMask =
2901 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2902 const APInt &RHSMask =
2903 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
2905 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
2906 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
2907 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2908 N0.getOperand(0), N1.getOperand(0));
2909 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
2910 DAG.getConstant(LHSMask | RHSMask, VT));
2914 // See if this is some rotate idiom.
2915 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
2916 return SDValue(Rot, 0);
2918 // Simplify the operands using demanded-bits information.
2919 if (!VT.isVector() &&
2920 SimplifyDemandedBits(SDValue(N, 0)))
2921 return SDValue(N, 0);
2926 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
2927 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
2928 if (Op.getOpcode() == ISD::AND) {
2929 if (isa<ConstantSDNode>(Op.getOperand(1))) {
2930 Mask = Op.getOperand(1);
2931 Op = Op.getOperand(0);
2937 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
2945 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
2946 // idioms for rotate, and if the target supports rotation instructions, generate
2948 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
2949 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
2950 EVT VT = LHS.getValueType();
2951 if (!TLI.isTypeLegal(VT)) return 0;
2953 // The target must have at least one rotate flavor.
2954 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
2955 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
2956 if (!HasROTL && !HasROTR) return 0;
2958 // Match "(X shl/srl V1) & V2" where V2 may not be present.
2959 SDValue LHSShift; // The shift.
2960 SDValue LHSMask; // AND value if any.
2961 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
2962 return 0; // Not part of a rotate.
2964 SDValue RHSShift; // The shift.
2965 SDValue RHSMask; // AND value if any.
2966 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
2967 return 0; // Not part of a rotate.
2969 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
2970 return 0; // Not shifting the same value.
2972 if (LHSShift.getOpcode() == RHSShift.getOpcode())
2973 return 0; // Shifts must disagree.
2975 // Canonicalize shl to left side in a shl/srl pair.
2976 if (RHSShift.getOpcode() == ISD::SHL) {
2977 std::swap(LHS, RHS);
2978 std::swap(LHSShift, RHSShift);
2979 std::swap(LHSMask , RHSMask );
2982 unsigned OpSizeInBits = VT.getSizeInBits();
2983 SDValue LHSShiftArg = LHSShift.getOperand(0);
2984 SDValue LHSShiftAmt = LHSShift.getOperand(1);
2985 SDValue RHSShiftAmt = RHSShift.getOperand(1);
2987 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
2988 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
2989 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
2990 RHSShiftAmt.getOpcode() == ISD::Constant) {
2991 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
2992 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
2993 if ((LShVal + RShVal) != OpSizeInBits)
2998 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
3000 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
3002 // If there is an AND of either shifted operand, apply it to the result.
3003 if (LHSMask.getNode() || RHSMask.getNode()) {
3004 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
3006 if (LHSMask.getNode()) {
3007 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
3008 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
3010 if (RHSMask.getNode()) {
3011 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
3012 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
3015 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
3018 return Rot.getNode();
3021 // If there is a mask here, and we have a variable shift, we can't be sure
3022 // that we're masking out the right stuff.
3023 if (LHSMask.getNode() || RHSMask.getNode())
3026 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
3027 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
3028 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
3029 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
3030 if (ConstantSDNode *SUBC =
3031 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
3032 if (SUBC->getAPIntValue() == OpSizeInBits) {
3034 return DAG.getNode(ISD::ROTL, DL, VT,
3035 LHSShiftArg, LHSShiftAmt).getNode();
3037 return DAG.getNode(ISD::ROTR, DL, VT,
3038 LHSShiftArg, RHSShiftAmt).getNode();
3043 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
3044 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
3045 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
3046 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
3047 if (ConstantSDNode *SUBC =
3048 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
3049 if (SUBC->getAPIntValue() == OpSizeInBits) {
3051 return DAG.getNode(ISD::ROTR, DL, VT,
3052 LHSShiftArg, RHSShiftAmt).getNode();
3054 return DAG.getNode(ISD::ROTL, DL, VT,
3055 LHSShiftArg, LHSShiftAmt).getNode();
3060 // Look for sign/zext/any-extended or truncate cases:
3061 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
3062 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
3063 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
3064 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3065 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
3066 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
3067 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
3068 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3069 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
3070 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
3071 if (RExtOp0.getOpcode() == ISD::SUB &&
3072 RExtOp0.getOperand(1) == LExtOp0) {
3073 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3075 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3076 // (rotr x, (sub 32, y))
3077 if (ConstantSDNode *SUBC =
3078 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
3079 if (SUBC->getAPIntValue() == OpSizeInBits) {
3080 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3082 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
3085 } else if (LExtOp0.getOpcode() == ISD::SUB &&
3086 RExtOp0 == LExtOp0.getOperand(1)) {
3087 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3089 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3090 // (rotl x, (sub 32, y))
3091 if (ConstantSDNode *SUBC =
3092 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
3093 if (SUBC->getAPIntValue() == OpSizeInBits) {
3094 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
3096 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
3105 SDValue DAGCombiner::visitXOR(SDNode *N) {
3106 SDValue N0 = N->getOperand(0);
3107 SDValue N1 = N->getOperand(1);
3108 SDValue LHS, RHS, CC;
3109 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3110 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3111 EVT VT = N0.getValueType();
3114 if (VT.isVector()) {
3115 SDValue FoldedVOp = SimplifyVBinOp(N);
3116 if (FoldedVOp.getNode()) return FoldedVOp;
3119 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3120 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3121 return DAG.getConstant(0, VT);
3122 // fold (xor x, undef) -> undef
3123 if (N0.getOpcode() == ISD::UNDEF)
3125 if (N1.getOpcode() == ISD::UNDEF)
3127 // fold (xor c1, c2) -> c1^c2
3129 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3130 // canonicalize constant to RHS
3132 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
3133 // fold (xor x, 0) -> x
3134 if (N1C && N1C->isNullValue())
3137 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
3138 if (RXOR.getNode() != 0)
3141 // fold !(x cc y) -> (x !cc y)
3142 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3143 bool isInt = LHS.getValueType().isInteger();
3144 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3147 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
3148 switch (N0.getOpcode()) {
3150 llvm_unreachable("Unhandled SetCC Equivalent!");
3152 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
3153 case ISD::SELECT_CC:
3154 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
3155 N0.getOperand(3), NotCC);
3160 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
3161 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3162 N0.getNode()->hasOneUse() &&
3163 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3164 SDValue V = N0.getOperand(0);
3165 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
3166 DAG.getConstant(1, V.getValueType()));
3167 AddToWorkList(V.getNode());
3168 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
3171 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
3172 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
3173 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3174 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3175 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
3176 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3177 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3178 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3179 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3180 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3183 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
3184 if (N1C && N1C->isAllOnesValue() &&
3185 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3186 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3187 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
3188 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3189 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3190 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3191 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3192 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3195 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
3196 if (N1C && N0.getOpcode() == ISD::XOR) {
3197 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3198 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3200 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
3201 DAG.getConstant(N1C->getAPIntValue() ^
3202 N00C->getAPIntValue(), VT));
3204 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
3205 DAG.getConstant(N1C->getAPIntValue() ^
3206 N01C->getAPIntValue(), VT));
3208 // fold (xor x, x) -> 0
3210 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
3212 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
3213 if (N0.getOpcode() == N1.getOpcode()) {
3214 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3215 if (Tmp.getNode()) return Tmp;
3218 // Simplify the expression using non-local knowledge.
3219 if (!VT.isVector() &&
3220 SimplifyDemandedBits(SDValue(N, 0)))
3221 return SDValue(N, 0);
3226 /// visitShiftByConstant - Handle transforms common to the three shifts, when
3227 /// the shift amount is a constant.
3228 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
3229 SDNode *LHS = N->getOperand(0).getNode();
3230 if (!LHS->hasOneUse()) return SDValue();
3232 // We want to pull some binops through shifts, so that we have (and (shift))
3233 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
3234 // thing happens with address calculations, so it's important to canonicalize
3236 bool HighBitSet = false; // Can we transform this if the high bit is set?
3238 switch (LHS->getOpcode()) {
3239 default: return SDValue();
3242 HighBitSet = false; // We can only transform sra if the high bit is clear.
3245 HighBitSet = true; // We can only transform sra if the high bit is set.
3248 if (N->getOpcode() != ISD::SHL)
3249 return SDValue(); // only shl(add) not sr[al](add).
3250 HighBitSet = false; // We can only transform sra if the high bit is clear.
3254 // We require the RHS of the binop to be a constant as well.
3255 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
3256 if (!BinOpCst) return SDValue();
3258 // FIXME: disable this unless the input to the binop is a shift by a constant.
3259 // If it is not a shift, it pessimizes some common cases like:
3261 // void foo(int *X, int i) { X[i & 1235] = 1; }
3262 // int bar(int *X, int i) { return X[i & 255]; }
3263 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
3264 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
3265 BinOpLHSVal->getOpcode() != ISD::SRA &&
3266 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3267 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
3270 EVT VT = N->getValueType(0);
3272 // If this is a signed shift right, and the high bit is modified by the
3273 // logical operation, do not perform the transformation. The highBitSet
3274 // boolean indicates the value of the high bit of the constant which would
3275 // cause it to be modified for this operation.
3276 if (N->getOpcode() == ISD::SRA) {
3277 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
3278 if (BinOpRHSSignSet != HighBitSet)
3282 // Fold the constants, shifting the binop RHS by the shift amount.
3283 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
3285 LHS->getOperand(1), N->getOperand(1));
3287 // Create the new shift.
3288 SDValue NewShift = DAG.getNode(N->getOpcode(),
3289 LHS->getOperand(0).getDebugLoc(),
3290 VT, LHS->getOperand(0), N->getOperand(1));
3292 // Create the new binop.
3293 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
3296 SDValue DAGCombiner::visitSHL(SDNode *N) {
3297 SDValue N0 = N->getOperand(0);
3298 SDValue N1 = N->getOperand(1);
3299 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3300 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3301 EVT VT = N0.getValueType();
3302 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3304 // fold (shl c1, c2) -> c1<<c2
3306 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
3307 // fold (shl 0, x) -> 0
3308 if (N0C && N0C->isNullValue())
3310 // fold (shl x, c >= size(x)) -> undef
3311 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3312 return DAG.getUNDEF(VT);
3313 // fold (shl x, 0) -> x
3314 if (N1C && N1C->isNullValue())
3316 // fold (shl undef, x) -> 0
3317 if (N0.getOpcode() == ISD::UNDEF)
3318 return DAG.getConstant(0, VT);
3319 // if (shl x, c) is known to be zero, return 0
3320 if (DAG.MaskedValueIsZero(SDValue(N, 0),
3321 APInt::getAllOnesValue(OpSizeInBits)))
3322 return DAG.getConstant(0, VT);
3323 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
3324 if (N1.getOpcode() == ISD::TRUNCATE &&
3325 N1.getOperand(0).getOpcode() == ISD::AND &&
3326 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3327 SDValue N101 = N1.getOperand(0).getOperand(1);
3328 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3329 EVT TruncVT = N1.getValueType();
3330 SDValue N100 = N1.getOperand(0).getOperand(0);
3331 APInt TruncC = N101C->getAPIntValue();
3332 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3333 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
3334 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
3335 DAG.getNode(ISD::TRUNCATE,
3338 DAG.getConstant(TruncC, TruncVT)));
3342 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3343 return SDValue(N, 0);
3345 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
3346 if (N1C && N0.getOpcode() == ISD::SHL &&
3347 N0.getOperand(1).getOpcode() == ISD::Constant) {
3348 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3349 uint64_t c2 = N1C->getZExtValue();
3350 if (c1 + c2 >= OpSizeInBits)
3351 return DAG.getConstant(0, VT);
3352 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3353 DAG.getConstant(c1 + c2, N1.getValueType()));
3356 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
3357 // For this to be valid, the second form must not preserve any of the bits
3358 // that are shifted out by the inner shift in the first form. This means
3359 // the outer shift size must be >= the number of bits added by the ext.
3360 // As a corollary, we don't care what kind of ext it is.
3361 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
3362 N0.getOpcode() == ISD::ANY_EXTEND ||
3363 N0.getOpcode() == ISD::SIGN_EXTEND) &&
3364 N0.getOperand(0).getOpcode() == ISD::SHL &&
3365 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3367 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3368 uint64_t c2 = N1C->getZExtValue();
3369 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3370 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3371 if (c2 >= OpSizeInBits - InnerShiftSize) {
3372 if (c1 + c2 >= OpSizeInBits)
3373 return DAG.getConstant(0, VT);
3374 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT,
3375 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT,
3376 N0.getOperand(0)->getOperand(0)),
3377 DAG.getConstant(c1 + c2, N1.getValueType()));
3381 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
3382 // (and (srl x, (sub c1, c2), MASK)
3383 // Only fold this if the inner shift has no other uses -- if it does, folding
3384 // this will increase the total number of instructions.
3385 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() &&
3386 N0.getOperand(1).getOpcode() == ISD::Constant) {
3387 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3388 if (c1 < VT.getSizeInBits()) {
3389 uint64_t c2 = N1C->getZExtValue();
3390 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
3391 VT.getSizeInBits() - c1);
3394 Mask = Mask.shl(c2-c1);
3395 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3396 DAG.getConstant(c2-c1, N1.getValueType()));
3398 Mask = Mask.lshr(c1-c2);
3399 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3400 DAG.getConstant(c1-c2, N1.getValueType()));
3402 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift,
3403 DAG.getConstant(Mask, VT));
3406 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
3407 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
3408 SDValue HiBitsMask =
3409 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
3410 VT.getSizeInBits() -
3411 N1C->getZExtValue()),
3413 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3418 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
3419 if (NewSHL.getNode())
3426 SDValue DAGCombiner::visitSRA(SDNode *N) {
3427 SDValue N0 = N->getOperand(0);
3428 SDValue N1 = N->getOperand(1);
3429 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3430 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3431 EVT VT = N0.getValueType();
3432 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3434 // fold (sra c1, c2) -> (sra c1, c2)
3436 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
3437 // fold (sra 0, x) -> 0
3438 if (N0C && N0C->isNullValue())
3440 // fold (sra -1, x) -> -1
3441 if (N0C && N0C->isAllOnesValue())
3443 // fold (sra x, (setge c, size(x))) -> undef
3444 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3445 return DAG.getUNDEF(VT);
3446 // fold (sra x, 0) -> x
3447 if (N1C && N1C->isNullValue())
3449 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
3451 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
3452 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
3453 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
3455 ExtVT = EVT::getVectorVT(*DAG.getContext(),
3456 ExtVT, VT.getVectorNumElements());
3457 if ((!LegalOperations ||
3458 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
3459 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3460 N0.getOperand(0), DAG.getValueType(ExtVT));
3463 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
3464 if (N1C && N0.getOpcode() == ISD::SRA) {
3465 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3466 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
3467 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
3468 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
3469 DAG.getConstant(Sum, N1C->getValueType(0)));
3473 // fold (sra (shl X, m), (sub result_size, n))
3474 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
3475 // result_size - n != m.
3476 // If truncate is free for the target sext(shl) is likely to result in better
3478 if (N0.getOpcode() == ISD::SHL) {
3479 // Get the two constanst of the shifts, CN0 = m, CN = n.
3480 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3482 // Determine what the truncate's result bitsize and type would be.
3484 EVT::getIntegerVT(*DAG.getContext(),
3485 OpSizeInBits - N1C->getZExtValue());
3486 // Determine the residual right-shift amount.
3487 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
3489 // If the shift is not a no-op (in which case this should be just a sign
3490 // extend already), the truncated to type is legal, sign_extend is legal
3491 // on that type, and the truncate to that type is both legal and free,
3492 // perform the transform.
3493 if ((ShiftAmt > 0) &&
3494 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
3495 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
3496 TLI.isTruncateFree(VT, TruncVT)) {
3498 SDValue Amt = DAG.getConstant(ShiftAmt,
3499 getShiftAmountTy(N0.getOperand(0).getValueType()));
3500 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3501 N0.getOperand(0), Amt);
3502 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
3504 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
3505 N->getValueType(0), Trunc);
3510 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
3511 if (N1.getOpcode() == ISD::TRUNCATE &&
3512 N1.getOperand(0).getOpcode() == ISD::AND &&
3513 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3514 SDValue N101 = N1.getOperand(0).getOperand(1);
3515 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3516 EVT TruncVT = N1.getValueType();
3517 SDValue N100 = N1.getOperand(0).getOperand(0);
3518 APInt TruncC = N101C->getAPIntValue();
3519 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
3520 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
3521 DAG.getNode(ISD::AND, N->getDebugLoc(),
3523 DAG.getNode(ISD::TRUNCATE,
3526 DAG.getConstant(TruncC, TruncVT)));
3530 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2))
3531 // if c1 is equal to the number of bits the trunc removes
3532 if (N0.getOpcode() == ISD::TRUNCATE &&
3533 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3534 N0.getOperand(0).getOpcode() == ISD::SRA) &&
3535 N0.getOperand(0).hasOneUse() &&
3536 N0.getOperand(0).getOperand(1).hasOneUse() &&
3537 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) {
3538 EVT LargeVT = N0.getOperand(0).getValueType();
3539 ConstantSDNode *LargeShiftAmt =
3540 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1));
3542 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits ==
3543 LargeShiftAmt->getZExtValue()) {
3545 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(),
3546 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType()));
3547 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT,
3548 N0.getOperand(0).getOperand(0), Amt);
3549 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA);
3553 // Simplify, based on bits shifted out of the LHS.
3554 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3555 return SDValue(N, 0);
3558 // If the sign bit is known to be zero, switch this to a SRL.
3559 if (DAG.SignBitIsZero(N0))
3560 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3563 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
3564 if (NewSRA.getNode())
3571 SDValue DAGCombiner::visitSRL(SDNode *N) {
3572 SDValue N0 = N->getOperand(0);
3573 SDValue N1 = N->getOperand(1);
3574 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3575 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3576 EVT VT = N0.getValueType();
3577 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3579 // fold (srl c1, c2) -> c1 >>u c2
3581 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3582 // fold (srl 0, x) -> 0
3583 if (N0C && N0C->isNullValue())
3585 // fold (srl x, c >= size(x)) -> undef
3586 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3587 return DAG.getUNDEF(VT);
3588 // fold (srl x, 0) -> x
3589 if (N1C && N1C->isNullValue())
3591 // if (srl x, c) is known to be zero, return 0
3592 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3593 APInt::getAllOnesValue(OpSizeInBits)))
3594 return DAG.getConstant(0, VT);
3596 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3597 if (N1C && N0.getOpcode() == ISD::SRL &&
3598 N0.getOperand(1).getOpcode() == ISD::Constant) {
3599 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3600 uint64_t c2 = N1C->getZExtValue();
3601 if (c1 + c2 >= OpSizeInBits)
3602 return DAG.getConstant(0, VT);
3603 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3604 DAG.getConstant(c1 + c2, N1.getValueType()));
3607 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
3608 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
3609 N0.getOperand(0).getOpcode() == ISD::SRL &&
3610 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3612 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3613 uint64_t c2 = N1C->getZExtValue();
3614 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3615 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
3616 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3617 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
3618 if (c1 + OpSizeInBits == InnerShiftSize) {
3619 if (c1 + c2 >= InnerShiftSize)
3620 return DAG.getConstant(0, VT);
3621 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT,
3622 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
3623 N0.getOperand(0)->getOperand(0),
3624 DAG.getConstant(c1 + c2, ShiftCountVT)));
3628 // fold (srl (shl x, c), c) -> (and x, cst2)
3629 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3630 N0.getValueSizeInBits() <= 64) {
3631 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3632 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3633 DAG.getConstant(~0ULL >> ShAmt, VT));
3637 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3638 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3639 // Shifting in all undef bits?
3640 EVT SmallVT = N0.getOperand(0).getValueType();
3641 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
3642 return DAG.getUNDEF(VT);
3644 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3645 uint64_t ShiftAmt = N1C->getZExtValue();
3646 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3648 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));
3649 AddToWorkList(SmallShift.getNode());
3650 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
3654 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
3655 // bit, which is unmodified by sra.
3656 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
3657 if (N0.getOpcode() == ISD::SRA)
3658 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3661 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3662 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3663 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
3664 APInt KnownZero, KnownOne;
3665 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
3666 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
3668 // If any of the input bits are KnownOne, then the input couldn't be all
3669 // zeros, thus the result of the srl will always be zero.
3670 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
3672 // If all of the bits input the to ctlz node are known to be zero, then
3673 // the result of the ctlz is "32" and the result of the shift is one.
3674 APInt UnknownBits = ~KnownZero & Mask;
3675 if (UnknownBits == 0) return DAG.getConstant(1, VT);
3677 // Otherwise, check to see if there is exactly one bit input to the ctlz.
3678 if ((UnknownBits & (UnknownBits - 1)) == 0) {
3679 // Okay, we know that only that the single bit specified by UnknownBits
3680 // could be set on input to the CTLZ node. If this bit is set, the SRL
3681 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3682 // to an SRL/XOR pair, which is likely to simplify more.
3683 unsigned ShAmt = UnknownBits.countTrailingZeros();
3684 SDValue Op = N0.getOperand(0);
3687 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3688 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType())));
3689 AddToWorkList(Op.getNode());
3692 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3693 Op, DAG.getConstant(1, VT));
3697 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3698 if (N1.getOpcode() == ISD::TRUNCATE &&
3699 N1.getOperand(0).getOpcode() == ISD::AND &&
3700 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3701 SDValue N101 = N1.getOperand(0).getOperand(1);
3702 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3703 EVT TruncVT = N1.getValueType();
3704 SDValue N100 = N1.getOperand(0).getOperand(0);
3705 APInt TruncC = N101C->getAPIntValue();
3706 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3707 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3708 DAG.getNode(ISD::AND, N->getDebugLoc(),
3710 DAG.getNode(ISD::TRUNCATE,
3713 DAG.getConstant(TruncC, TruncVT)));
3717 // fold operands of srl based on knowledge that the low bits are not
3719 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3720 return SDValue(N, 0);
3723 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
3724 if (NewSRL.getNode())
3728 // Attempt to convert a srl of a load into a narrower zero-extending load.
3729 SDValue NarrowLoad = ReduceLoadWidth(N);
3730 if (NarrowLoad.getNode())
3733 // Here is a common situation. We want to optimize:
3736 // %b = and i32 %a, 2
3737 // %c = srl i32 %b, 1
3738 // brcond i32 %c ...
3744 // %c = setcc eq %b, 0
3747 // However when after the source operand of SRL is optimized into AND, the SRL
3748 // itself may not be optimized further. Look for it and add the BRCOND into
3750 if (N->hasOneUse()) {
3751 SDNode *Use = *N->use_begin();
3752 if (Use->getOpcode() == ISD::BRCOND)
3754 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
3755 // Also look pass the truncate.
3756 Use = *Use->use_begin();
3757 if (Use->getOpcode() == ISD::BRCOND)
3765 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
3766 SDValue N0 = N->getOperand(0);
3767 EVT VT = N->getValueType(0);
3769 // fold (ctlz c1) -> c2
3770 if (isa<ConstantSDNode>(N0))
3771 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
3775 SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) {
3776 SDValue N0 = N->getOperand(0);
3777 EVT VT = N->getValueType(0);
3779 // fold (ctlz_zero_undef c1) -> c2
3780 if (isa<ConstantSDNode>(N0))
3781 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0);
3785 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
3786 SDValue N0 = N->getOperand(0);
3787 EVT VT = N->getValueType(0);
3789 // fold (cttz c1) -> c2
3790 if (isa<ConstantSDNode>(N0))
3791 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
3795 SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) {
3796 SDValue N0 = N->getOperand(0);
3797 EVT VT = N->getValueType(0);
3799 // fold (cttz_zero_undef c1) -> c2
3800 if (isa<ConstantSDNode>(N0))
3801 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0);
3805 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
3806 SDValue N0 = N->getOperand(0);
3807 EVT VT = N->getValueType(0);
3809 // fold (ctpop c1) -> c2
3810 if (isa<ConstantSDNode>(N0))
3811 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
3815 SDValue DAGCombiner::visitSELECT(SDNode *N) {
3816 SDValue N0 = N->getOperand(0);
3817 SDValue N1 = N->getOperand(1);
3818 SDValue N2 = N->getOperand(2);
3819 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3820 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3821 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
3822 EVT VT = N->getValueType(0);
3823 EVT VT0 = N0.getValueType();
3825 // fold (select C, X, X) -> X
3828 // fold (select true, X, Y) -> X
3829 if (N0C && !N0C->isNullValue())
3831 // fold (select false, X, Y) -> Y
3832 if (N0C && N0C->isNullValue())
3834 // fold (select C, 1, X) -> (or C, X)
3835 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
3836 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3837 // fold (select C, 0, 1) -> (xor C, 1)
3838 if (VT.isInteger() &&
3841 TLI.getBooleanContents(false) == TargetLowering::ZeroOrOneBooleanContent)) &&
3842 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
3845 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
3846 N0, DAG.getConstant(1, VT0));
3847 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
3848 N0, DAG.getConstant(1, VT0));
3849 AddToWorkList(XORNode.getNode());
3851 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
3852 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
3854 // fold (select C, 0, X) -> (and (not C), X)
3855 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
3856 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3857 AddToWorkList(NOTNode.getNode());
3858 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
3860 // fold (select C, X, 1) -> (or (not C), X)
3861 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
3862 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3863 AddToWorkList(NOTNode.getNode());
3864 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
3866 // fold (select C, X, 0) -> (and C, X)
3867 if (VT == MVT::i1 && N2C && N2C->isNullValue())
3868 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3869 // fold (select X, X, Y) -> (or X, Y)
3870 // fold (select X, 1, Y) -> (or X, Y)
3871 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
3872 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3873 // fold (select X, Y, X) -> (and X, Y)
3874 // fold (select X, Y, 0) -> (and X, Y)
3875 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
3876 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3878 // If we can fold this based on the true/false value, do so.
3879 if (SimplifySelectOps(N, N1, N2))
3880 return SDValue(N, 0); // Don't revisit N.
3882 // fold selects based on a setcc into other things, such as min/max/abs
3883 if (N0.getOpcode() == ISD::SETCC) {
3885 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
3886 // having to say they don't support SELECT_CC on every type the DAG knows
3887 // about, since there is no way to mark an opcode illegal at all value types
3888 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
3889 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
3890 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
3891 N0.getOperand(0), N0.getOperand(1),
3892 N1, N2, N0.getOperand(2));
3893 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
3899 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
3900 SDValue N0 = N->getOperand(0);
3901 SDValue N1 = N->getOperand(1);
3902 SDValue N2 = N->getOperand(2);
3903 SDValue N3 = N->getOperand(3);
3904 SDValue N4 = N->getOperand(4);
3905 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
3907 // fold select_cc lhs, rhs, x, x, cc -> x
3911 // Determine if the condition we're dealing with is constant
3912 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
3913 N0, N1, CC, N->getDebugLoc(), false);
3914 if (SCC.getNode()) AddToWorkList(SCC.getNode());
3916 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
3917 if (!SCCC->isNullValue())
3918 return N2; // cond always true -> true val
3920 return N3; // cond always false -> false val
3923 // Fold to a simpler select_cc
3924 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
3925 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
3926 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
3929 // If we can fold this based on the true/false value, do so.
3930 if (SimplifySelectOps(N, N2, N3))
3931 return SDValue(N, 0); // Don't revisit N.
3933 // fold select_cc into other things, such as min/max/abs
3934 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
3937 SDValue DAGCombiner::visitSETCC(SDNode *N) {
3938 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
3939 cast<CondCodeSDNode>(N->getOperand(2))->get(),
3943 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
3944 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
3945 // transformation. Returns true if extension are possible and the above
3946 // mentioned transformation is profitable.
3947 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
3949 SmallVector<SDNode*, 4> &ExtendNodes,
3950 const TargetLowering &TLI) {
3951 bool HasCopyToRegUses = false;
3952 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
3953 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
3954 UE = N0.getNode()->use_end();
3959 if (UI.getUse().getResNo() != N0.getResNo())
3961 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
3962 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
3963 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
3964 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
3965 // Sign bits will be lost after a zext.
3968 for (unsigned i = 0; i != 2; ++i) {
3969 SDValue UseOp = User->getOperand(i);
3972 if (!isa<ConstantSDNode>(UseOp))
3977 ExtendNodes.push_back(User);
3980 // If truncates aren't free and there are users we can't
3981 // extend, it isn't worthwhile.
3984 // Remember if this value is live-out.
3985 if (User->getOpcode() == ISD::CopyToReg)
3986 HasCopyToRegUses = true;
3989 if (HasCopyToRegUses) {
3990 bool BothLiveOut = false;
3991 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3993 SDUse &Use = UI.getUse();
3994 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
4000 // Both unextended and extended values are live out. There had better be
4001 // a good reason for the transformation.
4002 return ExtendNodes.size();
4007 void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
4008 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
4009 ISD::NodeType ExtType) {
4010 // Extend SetCC uses if necessary.
4011 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
4012 SDNode *SetCC = SetCCs[i];
4013 SmallVector<SDValue, 4> Ops;
4015 for (unsigned j = 0; j != 2; ++j) {
4016 SDValue SOp = SetCC->getOperand(j);
4018 Ops.push_back(ExtLoad);
4020 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
4023 Ops.push_back(SetCC->getOperand(2));
4024 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0),
4025 &Ops[0], Ops.size()));
4029 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
4030 SDValue N0 = N->getOperand(0);
4031 EVT VT = N->getValueType(0);
4033 // fold (sext c1) -> c1
4034 if (isa<ConstantSDNode>(N0))
4035 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
4037 // fold (sext (sext x)) -> (sext x)
4038 // fold (sext (aext x)) -> (sext x)
4039 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4040 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
4043 if (N0.getOpcode() == ISD::TRUNCATE) {
4044 // fold (sext (truncate (load x))) -> (sext (smaller load x))
4045 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
4046 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4047 if (NarrowLoad.getNode()) {
4048 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4049 if (NarrowLoad.getNode() != N0.getNode()) {
4050 CombineTo(N0.getNode(), NarrowLoad);
4051 // CombineTo deleted the truncate, if needed, but not what's under it.
4054 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4057 // See if the value being truncated is already sign extended. If so, just
4058 // eliminate the trunc/sext pair.
4059 SDValue Op = N0.getOperand(0);
4060 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
4061 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
4062 unsigned DestBits = VT.getScalarType().getSizeInBits();
4063 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
4065 if (OpBits == DestBits) {
4066 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
4067 // bits, it is already ready.
4068 if (NumSignBits > DestBits-MidBits)
4070 } else if (OpBits < DestBits) {
4071 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
4072 // bits, just sext from i32.
4073 if (NumSignBits > OpBits-MidBits)
4074 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
4076 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
4077 // bits, just truncate to i32.
4078 if (NumSignBits > OpBits-MidBits)
4079 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4082 // fold (sext (truncate x)) -> (sextinreg x).
4083 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
4084 N0.getValueType())) {
4085 if (OpBits < DestBits)
4086 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
4087 else if (OpBits > DestBits)
4088 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
4089 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
4090 DAG.getValueType(N0.getValueType()));
4094 // fold (sext (load x)) -> (sext (truncate (sextload x)))
4095 // None of the supported targets knows how to perform load and sign extend
4096 // on vectors in one instruction. We only perform this transformation on
4098 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4099 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4100 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
4101 bool DoXform = true;
4102 SmallVector<SDNode*, 4> SetCCs;
4103 if (!N0.hasOneUse())
4104 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
4106 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4107 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4109 LN0->getBasePtr(), LN0->getPointerInfo(),
4111 LN0->isVolatile(), LN0->isNonTemporal(),
4112 LN0->getAlignment());
4113 CombineTo(N, ExtLoad);
4114 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4115 N0.getValueType(), ExtLoad);
4116 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4117 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4119 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4123 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
4124 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
4125 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4126 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4127 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4128 EVT MemVT = LN0->getMemoryVT();
4129 if ((!LegalOperations && !LN0->isVolatile()) ||
4130 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
4131 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4133 LN0->getBasePtr(), LN0->getPointerInfo(),
4135 LN0->isVolatile(), LN0->isNonTemporal(),
4136 LN0->getAlignment());
4137 CombineTo(N, ExtLoad);
4138 CombineTo(N0.getNode(),
4139 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4140 N0.getValueType(), ExtLoad),
4141 ExtLoad.getValue(1));
4142 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4146 // fold (sext (and/or/xor (load x), cst)) ->
4147 // (and/or/xor (sextload x), (sext cst))
4148 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4149 N0.getOpcode() == ISD::XOR) &&
4150 isa<LoadSDNode>(N0.getOperand(0)) &&
4151 N0.getOperand(1).getOpcode() == ISD::Constant &&
4152 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
4153 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4154 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4155 if (LN0->getExtensionType() != ISD::ZEXTLOAD) {
4156 bool DoXform = true;
4157 SmallVector<SDNode*, 4> SetCCs;
4158 if (!N0.hasOneUse())
4159 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
4162 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT,
4163 LN0->getChain(), LN0->getBasePtr(),
4164 LN0->getPointerInfo(),
4167 LN0->isNonTemporal(),
4168 LN0->getAlignment());
4169 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4170 Mask = Mask.sext(VT.getSizeInBits());
4171 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4172 ExtLoad, DAG.getConstant(Mask, VT));
4173 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4174 N0.getOperand(0).getDebugLoc(),
4175 N0.getOperand(0).getValueType(), ExtLoad);
4177 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4178 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4180 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4185 if (N0.getOpcode() == ISD::SETCC) {
4186 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
4187 // Only do this before legalize for now.
4188 if (VT.isVector() && !LegalOperations) {
4189 EVT N0VT = N0.getOperand(0).getValueType();
4190 // We know that the # elements of the results is the same as the
4191 // # elements of the compare (and the # elements of the compare result
4192 // for that matter). Check to see that they are the same size. If so,
4193 // we know that the element size of the sext'd result matches the
4194 // element size of the compare operands.
4195 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4196 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4198 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4199 // If the desired elements are smaller or larger than the source
4200 // elements we can use a matching integer vector type and then
4201 // truncate/sign extend
4203 EVT MatchingElementType =
4204 EVT::getIntegerVT(*DAG.getContext(),
4205 N0VT.getScalarType().getSizeInBits());
4206 EVT MatchingVectorType =
4207 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4208 N0VT.getVectorNumElements());
4210 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4212 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4213 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4217 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
4218 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
4220 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
4222 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4223 NegOne, DAG.getConstant(0, VT),
4224 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4225 if (SCC.getNode()) return SCC;
4226 if (!LegalOperations ||
4227 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
4228 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4229 DAG.getSetCC(N->getDebugLoc(),
4230 TLI.getSetCCResultType(VT),
4231 N0.getOperand(0), N0.getOperand(1),
4232 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4233 NegOne, DAG.getConstant(0, VT));
4236 // fold (sext x) -> (zext x) if the sign bit is known zero.
4237 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
4238 DAG.SignBitIsZero(N0))
4239 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4244 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
4245 SDValue N0 = N->getOperand(0);
4246 EVT VT = N->getValueType(0);
4248 // fold (zext c1) -> c1
4249 if (isa<ConstantSDNode>(N0))
4250 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4251 // fold (zext (zext x)) -> (zext x)
4252 // fold (zext (aext x)) -> (zext x)
4253 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4254 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
4257 // fold (zext (truncate x)) -> (zext x) or
4258 // (zext (truncate x)) -> (truncate x)
4259 // This is valid when the truncated bits of x are already zero.
4260 // FIXME: We should extend this to work for vectors too.
4261 if (N0.getOpcode() == ISD::TRUNCATE && !VT.isVector()) {
4262 SDValue Op = N0.getOperand(0);
4264 = APInt::getBitsSet(Op.getValueSizeInBits(),
4265 N0.getValueSizeInBits(),
4266 std::min(Op.getValueSizeInBits(),
4267 VT.getSizeInBits()));
4268 APInt KnownZero, KnownOne;
4269 DAG.ComputeMaskedBits(Op, TruncatedBits, KnownZero, KnownOne);
4270 if (TruncatedBits == KnownZero) {
4271 if (VT.bitsGT(Op.getValueType()))
4272 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op);
4273 if (VT.bitsLT(Op.getValueType()))
4274 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4280 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4281 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
4282 if (N0.getOpcode() == ISD::TRUNCATE) {
4283 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4284 if (NarrowLoad.getNode()) {
4285 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4286 if (NarrowLoad.getNode() != N0.getNode()) {
4287 CombineTo(N0.getNode(), NarrowLoad);
4288 // CombineTo deleted the truncate, if needed, but not what's under it.
4291 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4295 // fold (zext (truncate x)) -> (and x, mask)
4296 if (N0.getOpcode() == ISD::TRUNCATE &&
4297 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
4299 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4300 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
4301 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4302 if (NarrowLoad.getNode()) {
4303 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4304 if (NarrowLoad.getNode() != N0.getNode()) {
4305 CombineTo(N0.getNode(), NarrowLoad);
4306 // CombineTo deleted the truncate, if needed, but not what's under it.
4309 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4312 SDValue Op = N0.getOperand(0);
4313 if (Op.getValueType().bitsLT(VT)) {
4314 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
4315 } else if (Op.getValueType().bitsGT(VT)) {
4316 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4318 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
4319 N0.getValueType().getScalarType());
4322 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
4323 // if either of the casts is not free.
4324 if (N0.getOpcode() == ISD::AND &&
4325 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4326 N0.getOperand(1).getOpcode() == ISD::Constant &&
4327 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4328 N0.getValueType()) ||
4329 !TLI.isZExtFree(N0.getValueType(), VT))) {
4330 SDValue X = N0.getOperand(0).getOperand(0);
4331 if (X.getValueType().bitsLT(VT)) {
4332 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
4333 } else if (X.getValueType().bitsGT(VT)) {
4334 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4336 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4337 Mask = Mask.zext(VT.getSizeInBits());
4338 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4339 X, DAG.getConstant(Mask, VT));
4342 // fold (zext (load x)) -> (zext (truncate (zextload x)))
4343 // None of the supported targets knows how to perform load and vector_zext
4344 // on vectors in one instruction. We only perform this transformation on
4346 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4347 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4348 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
4349 bool DoXform = true;
4350 SmallVector<SDNode*, 4> SetCCs;
4351 if (!N0.hasOneUse())
4352 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
4354 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4355 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4357 LN0->getBasePtr(), LN0->getPointerInfo(),
4359 LN0->isVolatile(), LN0->isNonTemporal(),
4360 LN0->getAlignment());
4361 CombineTo(N, ExtLoad);
4362 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4363 N0.getValueType(), ExtLoad);
4364 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4366 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4368 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4372 // fold (zext (and/or/xor (load x), cst)) ->
4373 // (and/or/xor (zextload x), (zext cst))
4374 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4375 N0.getOpcode() == ISD::XOR) &&
4376 isa<LoadSDNode>(N0.getOperand(0)) &&
4377 N0.getOperand(1).getOpcode() == ISD::Constant &&
4378 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
4379 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4380 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4381 if (LN0->getExtensionType() != ISD::SEXTLOAD) {
4382 bool DoXform = true;
4383 SmallVector<SDNode*, 4> SetCCs;
4384 if (!N0.hasOneUse())
4385 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
4388 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT,
4389 LN0->getChain(), LN0->getBasePtr(),
4390 LN0->getPointerInfo(),
4393 LN0->isNonTemporal(),
4394 LN0->getAlignment());
4395 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4396 Mask = Mask.zext(VT.getSizeInBits());
4397 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4398 ExtLoad, DAG.getConstant(Mask, VT));
4399 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4400 N0.getOperand(0).getDebugLoc(),
4401 N0.getOperand(0).getValueType(), ExtLoad);
4403 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4404 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4406 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4411 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
4412 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
4413 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4414 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4415 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4416 EVT MemVT = LN0->getMemoryVT();
4417 if ((!LegalOperations && !LN0->isVolatile()) ||
4418 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
4419 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4421 LN0->getBasePtr(), LN0->getPointerInfo(),
4423 LN0->isVolatile(), LN0->isNonTemporal(),
4424 LN0->getAlignment());
4425 CombineTo(N, ExtLoad);
4426 CombineTo(N0.getNode(),
4427 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
4429 ExtLoad.getValue(1));
4430 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4434 if (N0.getOpcode() == ISD::SETCC) {
4435 if (!LegalOperations && VT.isVector()) {
4436 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
4437 // Only do this before legalize for now.
4438 EVT N0VT = N0.getOperand(0).getValueType();
4439 EVT EltVT = VT.getVectorElementType();
4440 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
4441 DAG.getConstant(1, EltVT));
4442 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4443 // We know that the # elements of the results is the same as the
4444 // # elements of the compare (and the # elements of the compare result
4445 // for that matter). Check to see that they are the same size. If so,
4446 // we know that the element size of the sext'd result matches the
4447 // element size of the compare operands.
4448 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4449 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4451 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4452 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4453 &OneOps[0], OneOps.size()));
4455 // If the desired elements are smaller or larger than the source
4456 // elements we can use a matching integer vector type and then
4457 // truncate/sign extend
4458 EVT MatchingElementType =
4459 EVT::getIntegerVT(*DAG.getContext(),
4460 N0VT.getScalarType().getSizeInBits());
4461 EVT MatchingVectorType =
4462 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4463 N0VT.getVectorNumElements());
4465 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4467 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4468 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4469 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT),
4470 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4471 &OneOps[0], OneOps.size()));
4474 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4476 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4477 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4478 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4479 if (SCC.getNode()) return SCC;
4482 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
4483 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
4484 isa<ConstantSDNode>(N0.getOperand(1)) &&
4485 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
4487 SDValue ShAmt = N0.getOperand(1);
4488 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
4489 if (N0.getOpcode() == ISD::SHL) {
4490 SDValue InnerZExt = N0.getOperand(0);
4491 // If the original shl may be shifting out bits, do not perform this
4493 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
4494 InnerZExt.getOperand(0).getValueType().getSizeInBits();
4495 if (ShAmtVal > KnownZeroBits)
4499 DebugLoc DL = N->getDebugLoc();
4501 // Ensure that the shift amount is wide enough for the shifted value.
4502 if (VT.getSizeInBits() >= 256)
4503 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
4505 return DAG.getNode(N0.getOpcode(), DL, VT,
4506 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
4513 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
4514 SDValue N0 = N->getOperand(0);
4515 EVT VT = N->getValueType(0);
4517 // fold (aext c1) -> c1
4518 if (isa<ConstantSDNode>(N0))
4519 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
4520 // fold (aext (aext x)) -> (aext x)
4521 // fold (aext (zext x)) -> (zext x)
4522 // fold (aext (sext x)) -> (sext x)
4523 if (N0.getOpcode() == ISD::ANY_EXTEND ||
4524 N0.getOpcode() == ISD::ZERO_EXTEND ||
4525 N0.getOpcode() == ISD::SIGN_EXTEND)
4526 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
4528 // fold (aext (truncate (load x))) -> (aext (smaller load x))
4529 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
4530 if (N0.getOpcode() == ISD::TRUNCATE) {
4531 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4532 if (NarrowLoad.getNode()) {
4533 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4534 if (NarrowLoad.getNode() != N0.getNode()) {
4535 CombineTo(N0.getNode(), NarrowLoad);
4536 // CombineTo deleted the truncate, if needed, but not what's under it.
4539 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4543 // fold (aext (truncate x))
4544 if (N0.getOpcode() == ISD::TRUNCATE) {
4545 SDValue TruncOp = N0.getOperand(0);
4546 if (TruncOp.getValueType() == VT)
4547 return TruncOp; // x iff x size == zext size.
4548 if (TruncOp.getValueType().bitsGT(VT))
4549 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
4550 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
4553 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
4554 // if the trunc is not free.
4555 if (N0.getOpcode() == ISD::AND &&
4556 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4557 N0.getOperand(1).getOpcode() == ISD::Constant &&
4558 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4559 N0.getValueType())) {
4560 SDValue X = N0.getOperand(0).getOperand(0);
4561 if (X.getValueType().bitsLT(VT)) {
4562 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
4563 } else if (X.getValueType().bitsGT(VT)) {
4564 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
4566 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4567 Mask = Mask.zext(VT.getSizeInBits());
4568 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4569 X, DAG.getConstant(Mask, VT));
4572 // fold (aext (load x)) -> (aext (truncate (extload x)))
4573 // None of the supported targets knows how to perform load and any_ext
4574 // on vectors in one instruction. We only perform this transformation on
4576 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4577 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4578 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4579 bool DoXform = true;
4580 SmallVector<SDNode*, 4> SetCCs;
4581 if (!N0.hasOneUse())
4582 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
4584 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4585 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4587 LN0->getBasePtr(), LN0->getPointerInfo(),
4589 LN0->isVolatile(), LN0->isNonTemporal(),
4590 LN0->getAlignment());
4591 CombineTo(N, ExtLoad);
4592 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4593 N0.getValueType(), ExtLoad);
4594 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4595 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4597 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4601 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
4602 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
4603 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
4604 if (N0.getOpcode() == ISD::LOAD &&
4605 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4607 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4608 EVT MemVT = LN0->getMemoryVT();
4609 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
4610 VT, LN0->getChain(), LN0->getBasePtr(),
4611 LN0->getPointerInfo(), MemVT,
4612 LN0->isVolatile(), LN0->isNonTemporal(),
4613 LN0->getAlignment());
4614 CombineTo(N, ExtLoad);
4615 CombineTo(N0.getNode(),
4616 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4617 N0.getValueType(), ExtLoad),
4618 ExtLoad.getValue(1));
4619 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4622 if (N0.getOpcode() == ISD::SETCC) {
4623 // aext(setcc) -> sext_in_reg(vsetcc) for vectors.
4624 // Only do this before legalize for now.
4625 if (VT.isVector() && !LegalOperations) {
4626 EVT N0VT = N0.getOperand(0).getValueType();
4627 // We know that the # elements of the results is the same as the
4628 // # elements of the compare (and the # elements of the compare result
4629 // for that matter). Check to see that they are the same size. If so,
4630 // we know that the element size of the sext'd result matches the
4631 // element size of the compare operands.
4632 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4633 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4635 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4636 // If the desired elements are smaller or larger than the source
4637 // elements we can use a matching integer vector type and then
4638 // truncate/sign extend
4640 EVT MatchingElementType =
4641 EVT::getIntegerVT(*DAG.getContext(),
4642 N0VT.getScalarType().getSizeInBits());
4643 EVT MatchingVectorType =
4644 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4645 N0VT.getVectorNumElements());
4647 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4649 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4650 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4654 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4656 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4657 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4658 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4666 /// GetDemandedBits - See if the specified operand can be simplified with the
4667 /// knowledge that only the bits specified by Mask are used. If so, return the
4668 /// simpler operand, otherwise return a null SDValue.
4669 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
4670 switch (V.getOpcode()) {
4672 case ISD::Constant: {
4673 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode());
4674 assert(CV != 0 && "Const value should be ConstSDNode.");
4675 const APInt &CVal = CV->getAPIntValue();
4676 APInt NewVal = CVal & Mask;
4677 if (NewVal != CVal) {
4678 return DAG.getConstant(NewVal, V.getValueType());
4684 // If the LHS or RHS don't contribute bits to the or, drop them.
4685 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
4686 return V.getOperand(1);
4687 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
4688 return V.getOperand(0);
4691 // Only look at single-use SRLs.
4692 if (!V.getNode()->hasOneUse())
4694 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
4695 // See if we can recursively simplify the LHS.
4696 unsigned Amt = RHSC->getZExtValue();
4698 // Watch out for shift count overflow though.
4699 if (Amt >= Mask.getBitWidth()) break;
4700 APInt NewMask = Mask << Amt;
4701 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
4702 if (SimplifyLHS.getNode())
4703 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
4704 SimplifyLHS, V.getOperand(1));
4710 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
4711 /// bits and then truncated to a narrower type and where N is a multiple
4712 /// of number of bits of the narrower type, transform it to a narrower load
4713 /// from address + N / num of bits of new type. If the result is to be
4714 /// extended, also fold the extension to form a extending load.
4715 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
4716 unsigned Opc = N->getOpcode();
4718 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
4719 SDValue N0 = N->getOperand(0);
4720 EVT VT = N->getValueType(0);
4723 // This transformation isn't valid for vector loads.
4727 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
4729 if (Opc == ISD::SIGN_EXTEND_INREG) {
4730 ExtType = ISD::SEXTLOAD;
4731 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4732 } else if (Opc == ISD::SRL) {
4733 // Another special-case: SRL is basically zero-extending a narrower value.
4734 ExtType = ISD::ZEXTLOAD;
4736 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4737 if (!N01) return SDValue();
4738 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
4739 VT.getSizeInBits() - N01->getZExtValue());
4741 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
4744 unsigned EVTBits = ExtVT.getSizeInBits();
4746 // Do not generate loads of non-round integer types since these can
4747 // be expensive (and would be wrong if the type is not byte sized).
4748 if (!ExtVT.isRound())
4752 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4753 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4754 ShAmt = N01->getZExtValue();
4755 // Is the shift amount a multiple of size of VT?
4756 if ((ShAmt & (EVTBits-1)) == 0) {
4757 N0 = N0.getOperand(0);
4758 // Is the load width a multiple of size of VT?
4759 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
4763 // At this point, we must have a load or else we can't do the transform.
4764 if (!isa<LoadSDNode>(N0)) return SDValue();
4766 // If the shift amount is larger than the input type then we're not
4767 // accessing any of the loaded bytes. If the load was a zextload/extload
4768 // then the result of the shift+trunc is zero/undef (handled elsewhere).
4769 // If the load was a sextload then the result is a splat of the sign bit
4770 // of the extended byte. This is not worth optimizing for.
4771 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
4776 // If the load is shifted left (and the result isn't shifted back right),
4777 // we can fold the truncate through the shift.
4778 unsigned ShLeftAmt = 0;
4779 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
4780 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
4781 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4782 ShLeftAmt = N01->getZExtValue();
4783 N0 = N0.getOperand(0);
4787 // If we haven't found a load, we can't narrow it. Don't transform one with
4788 // multiple uses, this would require adding a new load.
4789 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() ||
4790 // Don't change the width of a volatile load.
4791 cast<LoadSDNode>(N0)->isVolatile())
4794 // Verify that we are actually reducing a load width here.
4795 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits)
4798 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4799 EVT PtrType = N0.getOperand(1).getValueType();
4801 // For big endian targets, we need to adjust the offset to the pointer to
4802 // load the correct bytes.
4803 if (TLI.isBigEndian()) {
4804 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
4805 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
4806 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
4809 uint64_t PtrOff = ShAmt / 8;
4810 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
4811 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
4812 PtrType, LN0->getBasePtr(),
4813 DAG.getConstant(PtrOff, PtrType));
4814 AddToWorkList(NewPtr.getNode());
4817 if (ExtType == ISD::NON_EXTLOAD)
4818 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
4819 LN0->getPointerInfo().getWithOffset(PtrOff),
4820 LN0->isVolatile(), LN0->isNonTemporal(),
4821 LN0->isInvariant(), NewAlign);
4823 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr,
4824 LN0->getPointerInfo().getWithOffset(PtrOff),
4825 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
4828 // Replace the old load's chain with the new load's chain.
4829 WorkListRemover DeadNodes(*this);
4830 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
4833 // Shift the result left, if we've swallowed a left shift.
4834 SDValue Result = Load;
4835 if (ShLeftAmt != 0) {
4836 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
4837 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
4839 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT,
4840 Result, DAG.getConstant(ShLeftAmt, ShImmTy));
4843 // Return the new loaded value.
4847 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
4848 SDValue N0 = N->getOperand(0);
4849 SDValue N1 = N->getOperand(1);
4850 EVT VT = N->getValueType(0);
4851 EVT EVT = cast<VTSDNode>(N1)->getVT();
4852 unsigned VTBits = VT.getScalarType().getSizeInBits();
4853 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
4855 // fold (sext_in_reg c1) -> c1
4856 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
4857 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
4859 // If the input is already sign extended, just drop the extension.
4860 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
4863 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
4864 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
4865 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
4866 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
4867 N0.getOperand(0), N1);
4870 // fold (sext_in_reg (sext x)) -> (sext x)
4871 // fold (sext_in_reg (aext x)) -> (sext x)
4872 // if x is small enough.
4873 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
4874 SDValue N00 = N0.getOperand(0);
4875 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
4876 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
4877 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
4880 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
4881 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
4882 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
4884 // fold operands of sext_in_reg based on knowledge that the top bits are not
4886 if (SimplifyDemandedBits(SDValue(N, 0)))
4887 return SDValue(N, 0);
4889 // fold (sext_in_reg (load x)) -> (smaller sextload x)
4890 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
4891 SDValue NarrowLoad = ReduceLoadWidth(N);
4892 if (NarrowLoad.getNode())
4895 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
4896 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
4897 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
4898 if (N0.getOpcode() == ISD::SRL) {
4899 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
4900 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
4901 // We can turn this into an SRA iff the input to the SRL is already sign
4903 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
4904 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
4905 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
4906 N0.getOperand(0), N0.getOperand(1));
4910 // fold (sext_inreg (extload x)) -> (sextload x)
4911 if (ISD::isEXTLoad(N0.getNode()) &&
4912 ISD::isUNINDEXEDLoad(N0.getNode()) &&
4913 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4914 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4915 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
4916 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4917 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4919 LN0->getBasePtr(), LN0->getPointerInfo(),
4921 LN0->isVolatile(), LN0->isNonTemporal(),
4922 LN0->getAlignment());
4923 CombineTo(N, ExtLoad);
4924 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4925 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4927 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
4928 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4930 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4931 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4932 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
4933 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4934 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4936 LN0->getBasePtr(), LN0->getPointerInfo(),
4938 LN0->isVolatile(), LN0->isNonTemporal(),
4939 LN0->getAlignment());
4940 CombineTo(N, ExtLoad);
4941 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4942 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4945 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
4946 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
4947 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
4948 N0.getOperand(1), false);
4949 if (BSwap.getNode() != 0)
4950 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
4957 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
4958 SDValue N0 = N->getOperand(0);
4959 EVT VT = N->getValueType(0);
4960 bool isLE = TLI.isLittleEndian();
4963 if (N0.getValueType() == N->getValueType(0))
4965 // fold (truncate c1) -> c1
4966 if (isa<ConstantSDNode>(N0))
4967 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
4968 // fold (truncate (truncate x)) -> (truncate x)
4969 if (N0.getOpcode() == ISD::TRUNCATE)
4970 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4971 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
4972 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
4973 N0.getOpcode() == ISD::SIGN_EXTEND ||
4974 N0.getOpcode() == ISD::ANY_EXTEND) {
4975 if (N0.getOperand(0).getValueType().bitsLT(VT))
4976 // if the source is smaller than the dest, we still need an extend
4977 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4979 else if (N0.getOperand(0).getValueType().bitsGT(VT))
4980 // if the source is larger than the dest, than we just need the truncate
4981 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4983 // if the source and dest are the same type, we can drop both the extend
4984 // and the truncate.
4985 return N0.getOperand(0);
4988 // Fold Extract-and-trunc into a narrow extract:
4989 // trunc(extract(x)) -> extract(bitcast(x))
4990 // We only run this optimization after type legalization (which often
4991 // creates this pattern) and before operation legalization after which
4992 // we need to be more careful about the vector instructions that we generate.
4993 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4994 LegalTypes && !LegalOperations && N0->hasOneUse()) {
4996 EVT VecTy = N0.getOperand(0).getValueType();
4997 EVT ExTy = N0.getValueType();
4998 EVT TrTy = N->getValueType(0);
5000 unsigned NumElem = VecTy.getVectorNumElements();
5001 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits();
5003 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem);
5004 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size");
5006 SDValue EltNo = N0->getOperand(1);
5007 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
5008 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5010 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
5012 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5013 NVT, N0.getOperand(0));
5015 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
5016 N->getDebugLoc(), TrTy, V,
5017 DAG.getConstant(Index, MVT::i32));
5021 // See if we can simplify the input to this truncate through knowledge that
5022 // only the low bits are being used.
5023 // For example "trunc (or (shl x, 8), y)" // -> trunc y
5024 // Currently we only perform this optimization on scalars because vectors
5025 // may have different active low bits.
5026 if (!VT.isVector()) {
5028 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
5029 VT.getSizeInBits()));
5030 if (Shorter.getNode())
5031 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
5033 // fold (truncate (load x)) -> (smaller load x)
5034 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
5035 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
5036 SDValue Reduced = ReduceLoadWidth(N);
5037 if (Reduced.getNode())
5041 // Simplify the operands using demanded-bits information.
5042 if (!VT.isVector() &&
5043 SimplifyDemandedBits(SDValue(N, 0)))
5044 return SDValue(N, 0);
5049 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
5050 SDValue Elt = N->getOperand(i);
5051 if (Elt.getOpcode() != ISD::MERGE_VALUES)
5052 return Elt.getNode();
5053 return Elt.getOperand(Elt.getResNo()).getNode();
5056 /// CombineConsecutiveLoads - build_pair (load, load) -> load
5057 /// if load locations are consecutive.
5058 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
5059 assert(N->getOpcode() == ISD::BUILD_PAIR);
5061 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
5062 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
5063 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
5064 LD1->getPointerInfo().getAddrSpace() !=
5065 LD2->getPointerInfo().getAddrSpace())
5067 EVT LD1VT = LD1->getValueType(0);
5069 if (ISD::isNON_EXTLoad(LD2) &&
5071 // If both are volatile this would reduce the number of volatile loads.
5072 // If one is volatile it might be ok, but play conservative and bail out.
5073 !LD1->isVolatile() &&
5074 !LD2->isVolatile() &&
5075 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
5076 unsigned Align = LD1->getAlignment();
5077 unsigned NewAlign = TLI.getTargetData()->
5078 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5080 if (NewAlign <= Align &&
5081 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
5082 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
5083 LD1->getBasePtr(), LD1->getPointerInfo(),
5084 false, false, false, Align);
5090 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
5091 SDValue N0 = N->getOperand(0);
5092 EVT VT = N->getValueType(0);
5094 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
5095 // Only do this before legalize, since afterward the target may be depending
5096 // on the bitconvert.
5097 // First check to see if this is all constant.
5099 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
5101 bool isSimple = true;
5102 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
5103 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
5104 N0.getOperand(i).getOpcode() != ISD::Constant &&
5105 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
5110 EVT DestEltVT = N->getValueType(0).getVectorElementType();
5111 assert(!DestEltVT.isVector() &&
5112 "Element type of vector ValueType must not be vector!");
5114 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
5117 // If the input is a constant, let getNode fold it.
5118 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
5119 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0);
5120 if (Res.getNode() != N) {
5121 if (!LegalOperations ||
5122 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
5125 // Folding it resulted in an illegal node, and it's too late to
5126 // do that. Clean up the old node and forego the transformation.
5127 // Ideally this won't happen very often, because instcombine
5128 // and the earlier dagcombine runs (where illegal nodes are
5129 // permitted) should have folded most of them already.
5130 DAG.DeleteNode(Res.getNode());
5134 // (conv (conv x, t1), t2) -> (conv x, t2)
5135 if (N0.getOpcode() == ISD::BITCAST)
5136 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT,
5139 // fold (conv (load x)) -> (load (conv*)x)
5140 // If the resultant load doesn't need a higher alignment than the original!
5141 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
5142 // Do not change the width of a volatile load.
5143 !cast<LoadSDNode>(N0)->isVolatile() &&
5144 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
5145 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5146 unsigned Align = TLI.getTargetData()->
5147 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5148 unsigned OrigAlign = LN0->getAlignment();
5150 if (Align <= OrigAlign) {
5151 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
5152 LN0->getBasePtr(), LN0->getPointerInfo(),
5153 LN0->isVolatile(), LN0->isNonTemporal(),
5154 LN0->isInvariant(), OrigAlign);
5156 CombineTo(N0.getNode(),
5157 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5158 N0.getValueType(), Load),
5164 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
5165 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
5166 // This often reduces constant pool loads.
5167 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
5168 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
5169 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT,
5171 AddToWorkList(NewConv.getNode());
5173 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5174 if (N0.getOpcode() == ISD::FNEG)
5175 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
5176 NewConv, DAG.getConstant(SignBit, VT));
5177 assert(N0.getOpcode() == ISD::FABS);
5178 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
5179 NewConv, DAG.getConstant(~SignBit, VT));
5182 // fold (bitconvert (fcopysign cst, x)) ->
5183 // (or (and (bitconvert x), sign), (and cst, (not sign)))
5184 // Note that we don't handle (copysign x, cst) because this can always be
5185 // folded to an fneg or fabs.
5186 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
5187 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
5188 VT.isInteger() && !VT.isVector()) {
5189 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
5190 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
5191 if (isTypeLegal(IntXVT)) {
5192 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5193 IntXVT, N0.getOperand(1));
5194 AddToWorkList(X.getNode());
5196 // If X has a different width than the result/lhs, sext it or truncate it.
5197 unsigned VTWidth = VT.getSizeInBits();
5198 if (OrigXWidth < VTWidth) {
5199 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
5200 AddToWorkList(X.getNode());
5201 } else if (OrigXWidth > VTWidth) {
5202 // To get the sign bit in the right place, we have to shift it right
5203 // before truncating.
5204 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
5205 X.getValueType(), X,
5206 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
5207 AddToWorkList(X.getNode());
5208 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
5209 AddToWorkList(X.getNode());
5212 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5213 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
5214 X, DAG.getConstant(SignBit, VT));
5215 AddToWorkList(X.getNode());
5217 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5218 VT, N0.getOperand(0));
5219 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
5220 Cst, DAG.getConstant(~SignBit, VT));
5221 AddToWorkList(Cst.getNode());
5223 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
5227 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
5228 if (N0.getOpcode() == ISD::BUILD_PAIR) {
5229 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
5230 if (CombineLD.getNode())
5237 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
5238 EVT VT = N->getValueType(0);
5239 return CombineConsecutiveLoads(N, VT);
5242 /// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector
5243 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
5244 /// destination element value type.
5245 SDValue DAGCombiner::
5246 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
5247 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
5249 // If this is already the right type, we're done.
5250 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
5252 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
5253 unsigned DstBitSize = DstEltVT.getSizeInBits();
5255 // If this is a conversion of N elements of one type to N elements of another
5256 // type, convert each element. This handles FP<->INT cases.
5257 if (SrcBitSize == DstBitSize) {
5258 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5259 BV->getValueType(0).getVectorNumElements());
5261 // Due to the FP element handling below calling this routine recursively,
5262 // we can end up with a scalar-to-vector node here.
5263 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
5264 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5265 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5266 DstEltVT, BV->getOperand(0)));
5268 SmallVector<SDValue, 8> Ops;
5269 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5270 SDValue Op = BV->getOperand(i);
5271 // If the vector element type is not legal, the BUILD_VECTOR operands
5272 // are promoted and implicitly truncated. Make that explicit here.
5273 if (Op.getValueType() != SrcEltVT)
5274 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
5275 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5277 AddToWorkList(Ops.back().getNode());
5279 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5280 &Ops[0], Ops.size());
5283 // Otherwise, we're growing or shrinking the elements. To avoid having to
5284 // handle annoying details of growing/shrinking FP values, we convert them to
5286 if (SrcEltVT.isFloatingPoint()) {
5287 // Convert the input float vector to a int vector where the elements are the
5289 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
5290 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
5291 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
5295 // Now we know the input is an integer vector. If the output is a FP type,
5296 // convert to integer first, then to FP of the right size.
5297 if (DstEltVT.isFloatingPoint()) {
5298 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
5299 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
5300 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
5302 // Next, convert to FP elements of the same size.
5303 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
5306 // Okay, we know the src/dst types are both integers of differing types.
5307 // Handling growing first.
5308 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
5309 if (SrcBitSize < DstBitSize) {
5310 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
5312 SmallVector<SDValue, 8> Ops;
5313 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
5314 i += NumInputsPerOutput) {
5315 bool isLE = TLI.isLittleEndian();
5316 APInt NewBits = APInt(DstBitSize, 0);
5317 bool EltIsUndef = true;
5318 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
5319 // Shift the previously computed bits over.
5320 NewBits <<= SrcBitSize;
5321 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
5322 if (Op.getOpcode() == ISD::UNDEF) continue;
5325 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
5326 zextOrTrunc(SrcBitSize).zext(DstBitSize);
5330 Ops.push_back(DAG.getUNDEF(DstEltVT));
5332 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
5335 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
5336 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5337 &Ops[0], Ops.size());
5340 // Finally, this must be the case where we are shrinking elements: each input
5341 // turns into multiple outputs.
5342 bool isS2V = ISD::isScalarToVector(BV);
5343 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
5344 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5345 NumOutputsPerInput*BV->getNumOperands());
5346 SmallVector<SDValue, 8> Ops;
5348 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5349 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
5350 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
5351 Ops.push_back(DAG.getUNDEF(DstEltVT));
5355 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
5356 getAPIntValue().zextOrTrunc(SrcBitSize);
5358 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
5359 APInt ThisVal = OpVal.trunc(DstBitSize);
5360 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
5361 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
5362 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
5363 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5365 OpVal = OpVal.lshr(DstBitSize);
5368 // For big endian targets, swap the order of the pieces of each element.
5369 if (TLI.isBigEndian())
5370 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
5373 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5374 &Ops[0], Ops.size());
5377 SDValue DAGCombiner::visitFADD(SDNode *N) {
5378 SDValue N0 = N->getOperand(0);
5379 SDValue N1 = N->getOperand(1);
5380 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5381 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5382 EVT VT = N->getValueType(0);
5385 if (VT.isVector()) {
5386 SDValue FoldedVOp = SimplifyVBinOp(N);
5387 if (FoldedVOp.getNode()) return FoldedVOp;
5390 // fold (fadd c1, c2) -> (fadd c1, c2)
5391 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5392 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
5393 // canonicalize constant to RHS
5394 if (N0CFP && !N1CFP)
5395 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
5396 // fold (fadd A, 0) -> A
5397 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5398 N1CFP->getValueAPF().isZero())
5400 // fold (fadd A, (fneg B)) -> (fsub A, B)
5401 if (isNegatibleForFree(N1, LegalOperations, &DAG.getTarget().Options) == 2)
5402 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
5403 GetNegatedExpression(N1, DAG, LegalOperations));
5404 // fold (fadd (fneg A), B) -> (fsub B, A)
5405 if (isNegatibleForFree(N0, LegalOperations, &DAG.getTarget().Options) == 2)
5406 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
5407 GetNegatedExpression(N0, DAG, LegalOperations));
5409 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
5410 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5411 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
5412 isa<ConstantFPSDNode>(N0.getOperand(1)))
5413 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
5414 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5415 N0.getOperand(1), N1));
5420 SDValue DAGCombiner::visitFSUB(SDNode *N) {
5421 SDValue N0 = N->getOperand(0);
5422 SDValue N1 = N->getOperand(1);
5423 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5424 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5425 EVT VT = N->getValueType(0);
5428 if (VT.isVector()) {
5429 SDValue FoldedVOp = SimplifyVBinOp(N);
5430 if (FoldedVOp.getNode()) return FoldedVOp;
5433 // fold (fsub c1, c2) -> c1-c2
5434 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5435 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
5436 // fold (fsub A, 0) -> A
5437 if (DAG.getTarget().Options.UnsafeFPMath &&
5438 N1CFP && N1CFP->getValueAPF().isZero())
5440 // fold (fsub 0, B) -> -B
5441 if (DAG.getTarget().Options.UnsafeFPMath &&
5442 N0CFP && N0CFP->getValueAPF().isZero()) {
5443 if (isNegatibleForFree(N1, LegalOperations, &DAG.getTarget().Options))
5444 return GetNegatedExpression(N1, DAG, LegalOperations);
5445 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5446 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
5448 // fold (fsub A, (fneg B)) -> (fadd A, B)
5449 if (isNegatibleForFree(N1, LegalOperations, &DAG.getTarget().Options))
5450 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
5451 GetNegatedExpression(N1, DAG, LegalOperations));
5456 SDValue DAGCombiner::visitFMUL(SDNode *N) {
5457 SDValue N0 = N->getOperand(0);
5458 SDValue N1 = N->getOperand(1);
5459 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5460 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5461 EVT VT = N->getValueType(0);
5464 if (VT.isVector()) {
5465 SDValue FoldedVOp = SimplifyVBinOp(N);
5466 if (FoldedVOp.getNode()) return FoldedVOp;
5469 // fold (fmul c1, c2) -> c1*c2
5470 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5471 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
5472 // canonicalize constant to RHS
5473 if (N0CFP && !N1CFP)
5474 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
5475 // fold (fmul A, 0) -> 0
5476 if (DAG.getTarget().Options.UnsafeFPMath &&
5477 N1CFP && N1CFP->getValueAPF().isZero())
5479 // fold (fmul A, 0) -> 0, vector edition.
5480 if (DAG.getTarget().Options.UnsafeFPMath &&
5481 ISD::isBuildVectorAllZeros(N1.getNode()))
5483 // fold (fmul X, 2.0) -> (fadd X, X)
5484 if (N1CFP && N1CFP->isExactlyValue(+2.0))
5485 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
5486 // fold (fmul X, -1.0) -> (fneg X)
5487 if (N1CFP && N1CFP->isExactlyValue(-1.0))
5488 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5489 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
5491 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
5492 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations,
5493 &DAG.getTarget().Options)) {
5494 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations,
5495 &DAG.getTarget().Options)) {
5496 // Both can be negated for free, check to see if at least one is cheaper
5498 if (LHSNeg == 2 || RHSNeg == 2)
5499 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5500 GetNegatedExpression(N0, DAG, LegalOperations),
5501 GetNegatedExpression(N1, DAG, LegalOperations));
5505 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
5506 if (DAG.getTarget().Options.UnsafeFPMath &&
5507 N1CFP && N0.getOpcode() == ISD::FMUL &&
5508 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
5509 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
5510 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5511 N0.getOperand(1), N1));
5516 SDValue DAGCombiner::visitFDIV(SDNode *N) {
5517 SDValue N0 = N->getOperand(0);
5518 SDValue N1 = N->getOperand(1);
5519 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5520 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5521 EVT VT = N->getValueType(0);
5524 if (VT.isVector()) {
5525 SDValue FoldedVOp = SimplifyVBinOp(N);
5526 if (FoldedVOp.getNode()) return FoldedVOp;
5529 // fold (fdiv c1, c2) -> c1/c2
5530 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5531 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
5534 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
5535 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations,
5536 &DAG.getTarget().Options)) {
5537 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations,
5538 &DAG.getTarget().Options)) {
5539 // Both can be negated for free, check to see if at least one is cheaper
5541 if (LHSNeg == 2 || RHSNeg == 2)
5542 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
5543 GetNegatedExpression(N0, DAG, LegalOperations),
5544 GetNegatedExpression(N1, DAG, LegalOperations));
5551 SDValue DAGCombiner::visitFREM(SDNode *N) {
5552 SDValue N0 = N->getOperand(0);
5553 SDValue N1 = N->getOperand(1);
5554 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5555 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5556 EVT VT = N->getValueType(0);
5558 // fold (frem c1, c2) -> fmod(c1,c2)
5559 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5560 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
5565 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
5566 SDValue N0 = N->getOperand(0);
5567 SDValue N1 = N->getOperand(1);
5568 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5569 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5570 EVT VT = N->getValueType(0);
5572 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
5573 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
5576 const APFloat& V = N1CFP->getValueAPF();
5577 // copysign(x, c1) -> fabs(x) iff ispos(c1)
5578 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
5579 if (!V.isNegative()) {
5580 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
5581 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5583 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5584 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
5585 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
5589 // copysign(fabs(x), y) -> copysign(x, y)
5590 // copysign(fneg(x), y) -> copysign(x, y)
5591 // copysign(copysign(x,z), y) -> copysign(x, y)
5592 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
5593 N0.getOpcode() == ISD::FCOPYSIGN)
5594 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5595 N0.getOperand(0), N1);
5597 // copysign(x, abs(y)) -> abs(x)
5598 if (N1.getOpcode() == ISD::FABS)
5599 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5601 // copysign(x, copysign(y,z)) -> copysign(x, z)
5602 if (N1.getOpcode() == ISD::FCOPYSIGN)
5603 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5604 N0, N1.getOperand(1));
5606 // copysign(x, fp_extend(y)) -> copysign(x, y)
5607 // copysign(x, fp_round(y)) -> copysign(x, y)
5608 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
5609 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5610 N0, N1.getOperand(0));
5615 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
5616 SDValue N0 = N->getOperand(0);
5617 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
5618 EVT VT = N->getValueType(0);
5619 EVT OpVT = N0.getValueType();
5621 // fold (sint_to_fp c1) -> c1fp
5622 if (N0C && OpVT != MVT::ppcf128 &&
5623 // ...but only if the target supports immediate floating-point values
5624 (!LegalOperations ||
5625 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
5626 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5628 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
5629 // but UINT_TO_FP is legal on this target, try to convert.
5630 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
5631 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
5632 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
5633 if (DAG.SignBitIsZero(N0))
5634 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5640 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
5641 SDValue N0 = N->getOperand(0);
5642 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
5643 EVT VT = N->getValueType(0);
5644 EVT OpVT = N0.getValueType();
5646 // fold (uint_to_fp c1) -> c1fp
5647 if (N0C && OpVT != MVT::ppcf128 &&
5648 // ...but only if the target supports immediate floating-point values
5649 (!LegalOperations ||
5650 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
5651 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5653 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
5654 // but SINT_TO_FP is legal on this target, try to convert.
5655 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
5656 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
5657 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
5658 if (DAG.SignBitIsZero(N0))
5659 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5665 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
5666 SDValue N0 = N->getOperand(0);
5667 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5668 EVT VT = N->getValueType(0);
5670 // fold (fp_to_sint c1fp) -> c1
5672 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
5677 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
5678 SDValue N0 = N->getOperand(0);
5679 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5680 EVT VT = N->getValueType(0);
5682 // fold (fp_to_uint c1fp) -> c1
5683 if (N0CFP && VT != MVT::ppcf128)
5684 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
5689 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
5690 SDValue N0 = N->getOperand(0);
5691 SDValue N1 = N->getOperand(1);
5692 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5693 EVT VT = N->getValueType(0);
5695 // fold (fp_round c1fp) -> c1fp
5696 if (N0CFP && N0.getValueType() != MVT::ppcf128)
5697 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
5699 // fold (fp_round (fp_extend x)) -> x
5700 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
5701 return N0.getOperand(0);
5703 // fold (fp_round (fp_round x)) -> (fp_round x)
5704 if (N0.getOpcode() == ISD::FP_ROUND) {
5705 // This is a value preserving truncation if both round's are.
5706 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
5707 N0.getNode()->getConstantOperandVal(1) == 1;
5708 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
5709 DAG.getIntPtrConstant(IsTrunc));
5712 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
5713 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
5714 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
5715 N0.getOperand(0), N1);
5716 AddToWorkList(Tmp.getNode());
5717 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5718 Tmp, N0.getOperand(1));
5724 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
5725 SDValue N0 = N->getOperand(0);
5726 EVT VT = N->getValueType(0);
5727 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
5728 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5730 // fold (fp_round_inreg c1fp) -> c1fp
5731 if (N0CFP && isTypeLegal(EVT)) {
5732 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
5733 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
5739 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
5740 SDValue N0 = N->getOperand(0);
5741 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5742 EVT VT = N->getValueType(0);
5744 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
5745 if (N->hasOneUse() &&
5746 N->use_begin()->getOpcode() == ISD::FP_ROUND)
5749 // fold (fp_extend c1fp) -> c1fp
5750 if (N0CFP && VT != MVT::ppcf128)
5751 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
5753 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
5755 if (N0.getOpcode() == ISD::FP_ROUND
5756 && N0.getNode()->getConstantOperandVal(1) == 1) {
5757 SDValue In = N0.getOperand(0);
5758 if (In.getValueType() == VT) return In;
5759 if (VT.bitsLT(In.getValueType()))
5760 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
5761 In, N0.getOperand(1));
5762 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
5765 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
5766 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
5767 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5768 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
5769 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5770 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
5772 LN0->getBasePtr(), LN0->getPointerInfo(),
5774 LN0->isVolatile(), LN0->isNonTemporal(),
5775 LN0->getAlignment());
5776 CombineTo(N, ExtLoad);
5777 CombineTo(N0.getNode(),
5778 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
5779 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
5780 ExtLoad.getValue(1));
5781 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5787 SDValue DAGCombiner::visitFNEG(SDNode *N) {
5788 SDValue N0 = N->getOperand(0);
5789 EVT VT = N->getValueType(0);
5791 if (isNegatibleForFree(N0, LegalOperations, &DAG.getTarget().Options))
5792 return GetNegatedExpression(N0, DAG, LegalOperations);
5794 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
5795 // constant pool values.
5796 if (N0.getOpcode() == ISD::BITCAST &&
5798 N0.getNode()->hasOneUse() &&
5799 N0.getOperand(0).getValueType().isInteger()) {
5800 SDValue Int = N0.getOperand(0);
5801 EVT IntVT = Int.getValueType();
5802 if (IntVT.isInteger() && !IntVT.isVector()) {
5803 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
5804 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5805 AddToWorkList(Int.getNode());
5806 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5814 SDValue DAGCombiner::visitFABS(SDNode *N) {
5815 SDValue N0 = N->getOperand(0);
5816 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5817 EVT VT = N->getValueType(0);
5819 // fold (fabs c1) -> fabs(c1)
5820 if (N0CFP && VT != MVT::ppcf128)
5821 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5822 // fold (fabs (fabs x)) -> (fabs x)
5823 if (N0.getOpcode() == ISD::FABS)
5824 return N->getOperand(0);
5825 // fold (fabs (fneg x)) -> (fabs x)
5826 // fold (fabs (fcopysign x, y)) -> (fabs x)
5827 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
5828 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
5830 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
5831 // constant pool values.
5832 if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
5833 N0.getOperand(0).getValueType().isInteger() &&
5834 !N0.getOperand(0).getValueType().isVector()) {
5835 SDValue Int = N0.getOperand(0);
5836 EVT IntVT = Int.getValueType();
5837 if (IntVT.isInteger() && !IntVT.isVector()) {
5838 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
5839 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5840 AddToWorkList(Int.getNode());
5841 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5842 N->getValueType(0), Int);
5849 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
5850 SDValue Chain = N->getOperand(0);
5851 SDValue N1 = N->getOperand(1);
5852 SDValue N2 = N->getOperand(2);
5854 // If N is a constant we could fold this into a fallthrough or unconditional
5855 // branch. However that doesn't happen very often in normal code, because
5856 // Instcombine/SimplifyCFG should have handled the available opportunities.
5857 // If we did this folding here, it would be necessary to update the
5858 // MachineBasicBlock CFG, which is awkward.
5860 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
5862 if (N1.getOpcode() == ISD::SETCC &&
5863 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
5864 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5865 Chain, N1.getOperand(2),
5866 N1.getOperand(0), N1.getOperand(1), N2);
5869 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
5870 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
5871 (N1.getOperand(0).hasOneUse() &&
5872 N1.getOperand(0).getOpcode() == ISD::SRL))) {
5874 if (N1.getOpcode() == ISD::TRUNCATE) {
5875 // Look pass the truncate.
5876 Trunc = N1.getNode();
5877 N1 = N1.getOperand(0);
5880 // Match this pattern so that we can generate simpler code:
5883 // %b = and i32 %a, 2
5884 // %c = srl i32 %b, 1
5885 // brcond i32 %c ...
5890 // %b = and i32 %a, 2
5891 // %c = setcc eq %b, 0
5894 // This applies only when the AND constant value has one bit set and the
5895 // SRL constant is equal to the log2 of the AND constant. The back-end is
5896 // smart enough to convert the result into a TEST/JMP sequence.
5897 SDValue Op0 = N1.getOperand(0);
5898 SDValue Op1 = N1.getOperand(1);
5900 if (Op0.getOpcode() == ISD::AND &&
5901 Op1.getOpcode() == ISD::Constant) {
5902 SDValue AndOp1 = Op0.getOperand(1);
5904 if (AndOp1.getOpcode() == ISD::Constant) {
5905 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
5907 if (AndConst.isPowerOf2() &&
5908 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
5910 DAG.getSetCC(N->getDebugLoc(),
5911 TLI.getSetCCResultType(Op0.getValueType()),
5912 Op0, DAG.getConstant(0, Op0.getValueType()),
5915 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5916 MVT::Other, Chain, SetCC, N2);
5917 // Don't add the new BRCond into the worklist or else SimplifySelectCC
5918 // will convert it back to (X & C1) >> C2.
5919 CombineTo(N, NewBRCond, false);
5920 // Truncate is dead.
5922 removeFromWorkList(Trunc);
5923 DAG.DeleteNode(Trunc);
5925 // Replace the uses of SRL with SETCC
5926 WorkListRemover DeadNodes(*this);
5927 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
5928 removeFromWorkList(N1.getNode());
5929 DAG.DeleteNode(N1.getNode());
5930 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5936 // Restore N1 if the above transformation doesn't match.
5937 N1 = N->getOperand(1);
5940 // Transform br(xor(x, y)) -> br(x != y)
5941 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
5942 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
5943 SDNode *TheXor = N1.getNode();
5944 SDValue Op0 = TheXor->getOperand(0);
5945 SDValue Op1 = TheXor->getOperand(1);
5946 if (Op0.getOpcode() == Op1.getOpcode()) {
5947 // Avoid missing important xor optimizations.
5948 SDValue Tmp = visitXOR(TheXor);
5949 if (Tmp.getNode() && Tmp.getNode() != TheXor) {
5950 DEBUG(dbgs() << "\nReplacing.8 ";
5952 dbgs() << "\nWith: ";
5953 Tmp.getNode()->dump(&DAG);
5955 WorkListRemover DeadNodes(*this);
5956 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes);
5957 removeFromWorkList(TheXor);
5958 DAG.DeleteNode(TheXor);
5959 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5960 MVT::Other, Chain, Tmp, N2);
5964 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
5966 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
5967 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
5968 Op0.getOpcode() == ISD::XOR) {
5969 TheXor = Op0.getNode();
5973 EVT SetCCVT = N1.getValueType();
5975 SetCCVT = TLI.getSetCCResultType(SetCCVT);
5976 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
5979 Equal ? ISD::SETEQ : ISD::SETNE);
5980 // Replace the uses of XOR with SETCC
5981 WorkListRemover DeadNodes(*this);
5982 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
5983 removeFromWorkList(N1.getNode());
5984 DAG.DeleteNode(N1.getNode());
5985 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5986 MVT::Other, Chain, SetCC, N2);
5993 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
5995 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
5996 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
5997 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
5999 // If N is a constant we could fold this into a fallthrough or unconditional
6000 // branch. However that doesn't happen very often in normal code, because
6001 // Instcombine/SimplifyCFG should have handled the available opportunities.
6002 // If we did this folding here, it would be necessary to update the
6003 // MachineBasicBlock CFG, which is awkward.
6005 // Use SimplifySetCC to simplify SETCC's.
6006 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
6007 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
6009 if (Simp.getNode()) AddToWorkList(Simp.getNode());
6011 // fold to a simpler setcc
6012 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
6013 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
6014 N->getOperand(0), Simp.getOperand(2),
6015 Simp.getOperand(0), Simp.getOperand(1),
6021 /// canFoldInAddressingMode - Return true if 'Use' is a load or a store that
6022 /// uses N as its base pointer and that N may be folded in the load / store
6023 /// addressing mode. FIXME: This currently only looks for folding of
6024 /// [reg +/- imm] addressing modes.
6025 static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
6027 const TargetLowering &TLI) {
6029 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) {
6030 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
6032 VT = Use->getValueType(0);
6033 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) {
6034 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
6036 VT = ST->getValue().getValueType();
6040 TargetLowering::AddrMode AM;
6041 if (N->getOpcode() == ISD::ADD) {
6042 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
6044 AM.BaseOffs = Offset->getSExtValue();
6047 } else if (N->getOpcode() == ISD::SUB) {
6048 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
6050 AM.BaseOffs = -Offset->getSExtValue();
6056 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext()));
6059 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
6060 /// pre-indexed load / store when the base pointer is an add or subtract
6061 /// and it has other uses besides the load / store. After the
6062 /// transformation, the new indexed load / store has effectively folded
6063 /// the add / subtract in and all of its other uses are redirected to the
6064 /// new load / store.
6065 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
6066 if (Level < AfterLegalizeDAG)
6072 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6073 if (LD->isIndexed())
6075 VT = LD->getMemoryVT();
6076 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
6077 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
6079 Ptr = LD->getBasePtr();
6080 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6081 if (ST->isIndexed())
6083 VT = ST->getMemoryVT();
6084 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
6085 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
6087 Ptr = ST->getBasePtr();
6093 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
6094 // out. There is no reason to make this a preinc/predec.
6095 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
6096 Ptr.getNode()->hasOneUse())
6099 // Ask the target to do addressing mode selection.
6102 ISD::MemIndexedMode AM = ISD::UNINDEXED;
6103 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
6105 // Don't create a indexed load / store with zero offset.
6106 if (isa<ConstantSDNode>(Offset) &&
6107 cast<ConstantSDNode>(Offset)->isNullValue())
6110 // Try turning it into a pre-indexed load / store except when:
6111 // 1) The new base ptr is a frame index.
6112 // 2) If N is a store and the new base ptr is either the same as or is a
6113 // predecessor of the value being stored.
6114 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
6115 // that would create a cycle.
6116 // 4) All uses are load / store ops that use it as old base ptr.
6118 // Check #1. Preinc'ing a frame index would require copying the stack pointer
6119 // (plus the implicit offset) to a register to preinc anyway.
6120 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
6125 SDValue Val = cast<StoreSDNode>(N)->getValue();
6126 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
6130 // Now check for #3 and #4.
6131 bool RealUse = false;
6133 // Caches for hasPredecessorHelper
6134 SmallPtrSet<const SDNode *, 32> Visited;
6135 SmallVector<const SDNode *, 16> Worklist;
6137 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
6138 E = Ptr.getNode()->use_end(); I != E; ++I) {
6142 if (N->hasPredecessorHelper(Use, Visited, Worklist))
6145 // If Ptr may be folded in addressing mode of other use, then it's
6146 // not profitable to do this transformation.
6147 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI))
6156 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
6157 BasePtr, Offset, AM);
6159 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
6160 BasePtr, Offset, AM);
6163 DEBUG(dbgs() << "\nReplacing.4 ";
6165 dbgs() << "\nWith: ";
6166 Result.getNode()->dump(&DAG);
6168 WorkListRemover DeadNodes(*this);
6170 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
6172 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
6175 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
6179 // Finally, since the node is now dead, remove it from the graph.
6182 // Replace the uses of Ptr with uses of the updated base value.
6183 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
6185 removeFromWorkList(Ptr.getNode());
6186 DAG.DeleteNode(Ptr.getNode());
6191 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
6192 /// add / sub of the base pointer node into a post-indexed load / store.
6193 /// The transformation folded the add / subtract into the new indexed
6194 /// load / store effectively and all of its uses are redirected to the
6195 /// new load / store.
6196 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
6197 if (Level < AfterLegalizeDAG)
6203 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6204 if (LD->isIndexed())
6206 VT = LD->getMemoryVT();
6207 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
6208 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
6210 Ptr = LD->getBasePtr();
6211 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6212 if (ST->isIndexed())
6214 VT = ST->getMemoryVT();
6215 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
6216 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
6218 Ptr = ST->getBasePtr();
6224 if (Ptr.getNode()->hasOneUse())
6227 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
6228 E = Ptr.getNode()->use_end(); I != E; ++I) {
6231 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
6236 ISD::MemIndexedMode AM = ISD::UNINDEXED;
6237 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
6238 // Don't create a indexed load / store with zero offset.
6239 if (isa<ConstantSDNode>(Offset) &&
6240 cast<ConstantSDNode>(Offset)->isNullValue())
6243 // Try turning it into a post-indexed load / store except when
6244 // 1) All uses are load / store ops that use it as base ptr (and
6245 // it may be folded as addressing mmode).
6246 // 2) Op must be independent of N, i.e. Op is neither a predecessor
6247 // nor a successor of N. Otherwise, if Op is folded that would
6250 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
6254 bool TryNext = false;
6255 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
6256 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
6258 if (Use == Ptr.getNode())
6261 // If all the uses are load / store addresses, then don't do the
6263 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
6264 bool RealUse = false;
6265 for (SDNode::use_iterator III = Use->use_begin(),
6266 EEE = Use->use_end(); III != EEE; ++III) {
6267 SDNode *UseUse = *III;
6268 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI))
6283 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
6284 SDValue Result = isLoad
6285 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
6286 BasePtr, Offset, AM)
6287 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
6288 BasePtr, Offset, AM);
6291 DEBUG(dbgs() << "\nReplacing.5 ";
6293 dbgs() << "\nWith: ";
6294 Result.getNode()->dump(&DAG);
6296 WorkListRemover DeadNodes(*this);
6298 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
6300 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
6303 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
6307 // Finally, since the node is now dead, remove it from the graph.
6310 // Replace the uses of Use with uses of the updated base value.
6311 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
6312 Result.getValue(isLoad ? 1 : 0),
6314 removeFromWorkList(Op);
6324 SDValue DAGCombiner::visitLOAD(SDNode *N) {
6325 LoadSDNode *LD = cast<LoadSDNode>(N);
6326 SDValue Chain = LD->getChain();
6327 SDValue Ptr = LD->getBasePtr();
6329 // If load is not volatile and there are no uses of the loaded value (and
6330 // the updated indexed value in case of indexed loads), change uses of the
6331 // chain value into uses of the chain input (i.e. delete the dead load).
6332 if (!LD->isVolatile()) {
6333 if (N->getValueType(1) == MVT::Other) {
6335 if (!N->hasAnyUseOfValue(0)) {
6336 // It's not safe to use the two value CombineTo variant here. e.g.
6337 // v1, chain2 = load chain1, loc
6338 // v2, chain3 = load chain2, loc
6340 // Now we replace use of chain2 with chain1. This makes the second load
6341 // isomorphic to the one we are deleting, and thus makes this load live.
6342 DEBUG(dbgs() << "\nReplacing.6 ";
6344 dbgs() << "\nWith chain: ";
6345 Chain.getNode()->dump(&DAG);
6347 WorkListRemover DeadNodes(*this);
6348 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
6350 if (N->use_empty()) {
6351 removeFromWorkList(N);
6355 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6359 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
6360 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) {
6361 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
6362 DEBUG(dbgs() << "\nReplacing.7 ";
6364 dbgs() << "\nWith: ";
6365 Undef.getNode()->dump(&DAG);
6366 dbgs() << " and 2 other values\n");
6367 WorkListRemover DeadNodes(*this);
6368 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
6369 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
6370 DAG.getUNDEF(N->getValueType(1)),
6372 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
6373 removeFromWorkList(N);
6375 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6380 // If this load is directly stored, replace the load value with the stored
6382 // TODO: Handle store large -> read small portion.
6383 // TODO: Handle TRUNCSTORE/LOADEXT
6384 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
6385 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
6386 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
6387 if (PrevST->getBasePtr() == Ptr &&
6388 PrevST->getValue().getValueType() == N->getValueType(0))
6389 return CombineTo(N, Chain.getOperand(1), Chain);
6393 // Try to infer better alignment information than the load already has.
6394 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
6395 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
6396 if (Align > LD->getAlignment())
6397 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
6398 LD->getValueType(0),
6399 Chain, Ptr, LD->getPointerInfo(),
6401 LD->isVolatile(), LD->isNonTemporal(), Align);
6406 // Walk up chain skipping non-aliasing memory nodes.
6407 SDValue BetterChain = FindBetterChain(N, Chain);
6409 // If there is a better chain.
6410 if (Chain != BetterChain) {
6413 // Replace the chain to void dependency.
6414 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
6415 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
6416 BetterChain, Ptr, LD->getPointerInfo(),
6417 LD->isVolatile(), LD->isNonTemporal(),
6418 LD->isInvariant(), LD->getAlignment());
6420 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
6421 LD->getValueType(0),
6422 BetterChain, Ptr, LD->getPointerInfo(),
6425 LD->isNonTemporal(),
6426 LD->getAlignment());
6429 // Create token factor to keep old chain connected.
6430 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
6431 MVT::Other, Chain, ReplLoad.getValue(1));
6433 // Make sure the new and old chains are cleaned up.
6434 AddToWorkList(Token.getNode());
6436 // Replace uses with load result and token factor. Don't add users
6438 return CombineTo(N, ReplLoad.getValue(0), Token, false);
6442 // Try transforming N to an indexed load.
6443 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
6444 return SDValue(N, 0);
6449 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
6450 /// load is having specific bytes cleared out. If so, return the byte size
6451 /// being masked out and the shift amount.
6452 static std::pair<unsigned, unsigned>
6453 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
6454 std::pair<unsigned, unsigned> Result(0, 0);
6456 // Check for the structure we're looking for.
6457 if (V->getOpcode() != ISD::AND ||
6458 !isa<ConstantSDNode>(V->getOperand(1)) ||
6459 !ISD::isNormalLoad(V->getOperand(0).getNode()))
6462 // Check the chain and pointer.
6463 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
6464 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
6466 // The store should be chained directly to the load or be an operand of a
6468 if (LD == Chain.getNode())
6470 else if (Chain->getOpcode() != ISD::TokenFactor)
6471 return Result; // Fail.
6474 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
6475 if (Chain->getOperand(i).getNode() == LD) {
6479 if (!isOk) return Result;
6482 // This only handles simple types.
6483 if (V.getValueType() != MVT::i16 &&
6484 V.getValueType() != MVT::i32 &&
6485 V.getValueType() != MVT::i64)
6488 // Check the constant mask. Invert it so that the bits being masked out are
6489 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
6490 // follow the sign bit for uniformity.
6491 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
6492 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask);
6493 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
6494 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask);
6495 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
6496 if (NotMaskLZ == 64) return Result; // All zero mask.
6498 // See if we have a continuous run of bits. If so, we have 0*1+0*
6499 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
6502 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
6503 if (V.getValueType() != MVT::i64 && NotMaskLZ)
6504 NotMaskLZ -= 64-V.getValueSizeInBits();
6506 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
6507 switch (MaskedBytes) {
6511 default: return Result; // All one mask, or 5-byte mask.
6514 // Verify that the first bit starts at a multiple of mask so that the access
6515 // is aligned the same as the access width.
6516 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
6518 Result.first = MaskedBytes;
6519 Result.second = NotMaskTZ/8;
6524 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
6525 /// provides a value as specified by MaskInfo. If so, replace the specified
6526 /// store with a narrower store of truncated IVal.
6528 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
6529 SDValue IVal, StoreSDNode *St,
6531 unsigned NumBytes = MaskInfo.first;
6532 unsigned ByteShift = MaskInfo.second;
6533 SelectionDAG &DAG = DC->getDAG();
6535 // Check to see if IVal is all zeros in the part being masked in by the 'or'
6536 // that uses this. If not, this is not a replacement.
6537 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
6538 ByteShift*8, (ByteShift+NumBytes)*8);
6539 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
6541 // Check that it is legal on the target to do this. It is legal if the new
6542 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
6544 MVT VT = MVT::getIntegerVT(NumBytes*8);
6545 if (!DC->isTypeLegal(VT))
6548 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
6549 // shifted by ByteShift and truncated down to NumBytes.
6551 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
6552 DAG.getConstant(ByteShift*8,
6553 DC->getShiftAmountTy(IVal.getValueType())));
6555 // Figure out the offset for the store and the alignment of the access.
6557 unsigned NewAlign = St->getAlignment();
6559 if (DAG.getTargetLoweringInfo().isLittleEndian())
6560 StOffset = ByteShift;
6562 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
6564 SDValue Ptr = St->getBasePtr();
6566 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
6567 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
6568 NewAlign = MinAlign(NewAlign, StOffset);
6571 // Truncate down to the new size.
6572 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
6575 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr,
6576 St->getPointerInfo().getWithOffset(StOffset),
6577 false, false, NewAlign).getNode();
6581 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
6582 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
6583 /// of the loaded bits, try narrowing the load and store if it would end up
6584 /// being a win for performance or code size.
6585 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
6586 StoreSDNode *ST = cast<StoreSDNode>(N);
6587 if (ST->isVolatile())
6590 SDValue Chain = ST->getChain();
6591 SDValue Value = ST->getValue();
6592 SDValue Ptr = ST->getBasePtr();
6593 EVT VT = Value.getValueType();
6595 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
6598 unsigned Opc = Value.getOpcode();
6600 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
6601 // is a byte mask indicating a consecutive number of bytes, check to see if
6602 // Y is known to provide just those bytes. If so, we try to replace the
6603 // load + replace + store sequence with a single (narrower) store, which makes
6605 if (Opc == ISD::OR) {
6606 std::pair<unsigned, unsigned> MaskedLoad;
6607 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
6608 if (MaskedLoad.first)
6609 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
6610 Value.getOperand(1), ST,this))
6611 return SDValue(NewST, 0);
6613 // Or is commutative, so try swapping X and Y.
6614 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
6615 if (MaskedLoad.first)
6616 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
6617 Value.getOperand(0), ST,this))
6618 return SDValue(NewST, 0);
6621 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
6622 Value.getOperand(1).getOpcode() != ISD::Constant)
6625 SDValue N0 = Value.getOperand(0);
6626 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6627 Chain == SDValue(N0.getNode(), 1)) {
6628 LoadSDNode *LD = cast<LoadSDNode>(N0);
6629 if (LD->getBasePtr() != Ptr ||
6630 LD->getPointerInfo().getAddrSpace() !=
6631 ST->getPointerInfo().getAddrSpace())
6634 // Find the type to narrow it the load / op / store to.
6635 SDValue N1 = Value.getOperand(1);
6636 unsigned BitWidth = N1.getValueSizeInBits();
6637 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
6638 if (Opc == ISD::AND)
6639 Imm ^= APInt::getAllOnesValue(BitWidth);
6640 if (Imm == 0 || Imm.isAllOnesValue())
6642 unsigned ShAmt = Imm.countTrailingZeros();
6643 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
6644 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
6645 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
6646 while (NewBW < BitWidth &&
6647 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
6648 TLI.isNarrowingProfitable(VT, NewVT))) {
6649 NewBW = NextPowerOf2(NewBW);
6650 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
6652 if (NewBW >= BitWidth)
6655 // If the lsb changed does not start at the type bitwidth boundary,
6656 // start at the previous one.
6658 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
6659 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
6660 if ((Imm & Mask) == Imm) {
6661 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
6662 if (Opc == ISD::AND)
6663 NewImm ^= APInt::getAllOnesValue(NewBW);
6664 uint64_t PtrOff = ShAmt / 8;
6665 // For big endian targets, we need to adjust the offset to the pointer to
6666 // load the correct bytes.
6667 if (TLI.isBigEndian())
6668 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
6670 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
6671 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
6672 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy))
6675 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
6676 Ptr.getValueType(), Ptr,
6677 DAG.getConstant(PtrOff, Ptr.getValueType()));
6678 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
6679 LD->getChain(), NewPtr,
6680 LD->getPointerInfo().getWithOffset(PtrOff),
6681 LD->isVolatile(), LD->isNonTemporal(),
6682 LD->isInvariant(), NewAlign);
6683 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
6684 DAG.getConstant(NewImm, NewVT));
6685 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
6687 ST->getPointerInfo().getWithOffset(PtrOff),
6688 false, false, NewAlign);
6690 AddToWorkList(NewPtr.getNode());
6691 AddToWorkList(NewLD.getNode());
6692 AddToWorkList(NewVal.getNode());
6693 WorkListRemover DeadNodes(*this);
6694 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1),
6704 /// TransformFPLoadStorePair - For a given floating point load / store pair,
6705 /// if the load value isn't used by any other operations, then consider
6706 /// transforming the pair to integer load / store operations if the target
6707 /// deems the transformation profitable.
6708 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
6709 StoreSDNode *ST = cast<StoreSDNode>(N);
6710 SDValue Chain = ST->getChain();
6711 SDValue Value = ST->getValue();
6712 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
6713 Value.hasOneUse() &&
6714 Chain == SDValue(Value.getNode(), 1)) {
6715 LoadSDNode *LD = cast<LoadSDNode>(Value);
6716 EVT VT = LD->getMemoryVT();
6717 if (!VT.isFloatingPoint() ||
6718 VT != ST->getMemoryVT() ||
6719 LD->isNonTemporal() ||
6720 ST->isNonTemporal() ||
6721 LD->getPointerInfo().getAddrSpace() != 0 ||
6722 ST->getPointerInfo().getAddrSpace() != 0)
6725 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
6726 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
6727 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
6728 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
6729 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
6732 unsigned LDAlign = LD->getAlignment();
6733 unsigned STAlign = ST->getAlignment();
6734 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
6735 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy);
6736 if (LDAlign < ABIAlign || STAlign < ABIAlign)
6739 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(),
6740 LD->getChain(), LD->getBasePtr(),
6741 LD->getPointerInfo(),
6742 false, false, false, LDAlign);
6744 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(),
6745 NewLD, ST->getBasePtr(),
6746 ST->getPointerInfo(),
6747 false, false, STAlign);
6749 AddToWorkList(NewLD.getNode());
6750 AddToWorkList(NewST.getNode());
6751 WorkListRemover DeadNodes(*this);
6752 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1),
6761 SDValue DAGCombiner::visitSTORE(SDNode *N) {
6762 StoreSDNode *ST = cast<StoreSDNode>(N);
6763 SDValue Chain = ST->getChain();
6764 SDValue Value = ST->getValue();
6765 SDValue Ptr = ST->getBasePtr();
6767 // If this is a store of a bit convert, store the input value if the
6768 // resultant store does not need a higher alignment than the original.
6769 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
6770 ST->isUnindexed()) {
6771 unsigned OrigAlign = ST->getAlignment();
6772 EVT SVT = Value.getOperand(0).getValueType();
6773 unsigned Align = TLI.getTargetData()->
6774 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
6775 if (Align <= OrigAlign &&
6776 ((!LegalOperations && !ST->isVolatile()) ||
6777 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
6778 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
6779 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6780 ST->isNonTemporal(), OrigAlign);
6783 // Turn 'store undef, Ptr' -> nothing.
6784 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
6787 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
6788 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
6789 // NOTE: If the original store is volatile, this transform must not increase
6790 // the number of stores. For example, on x86-32 an f64 can be stored in one
6791 // processor operation but an i64 (which is not legal) requires two. So the
6792 // transform should not be done in this case.
6793 if (Value.getOpcode() != ISD::TargetConstantFP) {
6795 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
6796 default: llvm_unreachable("Unknown FP type");
6797 case MVT::f80: // We don't do this for these yet.
6802 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
6803 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
6804 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
6805 bitcastToAPInt().getZExtValue(), MVT::i32);
6806 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
6807 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6808 ST->isNonTemporal(), ST->getAlignment());
6812 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
6813 !ST->isVolatile()) ||
6814 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
6815 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
6816 getZExtValue(), MVT::i64);
6817 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
6818 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6819 ST->isNonTemporal(), ST->getAlignment());
6822 if (!ST->isVolatile() &&
6823 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
6824 // Many FP stores are not made apparent until after legalize, e.g. for
6825 // argument passing. Since this is so common, custom legalize the
6826 // 64-bit integer store into two 32-bit stores.
6827 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
6828 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
6829 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
6830 if (TLI.isBigEndian()) std::swap(Lo, Hi);
6832 unsigned Alignment = ST->getAlignment();
6833 bool isVolatile = ST->isVolatile();
6834 bool isNonTemporal = ST->isNonTemporal();
6836 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
6837 Ptr, ST->getPointerInfo(),
6838 isVolatile, isNonTemporal,
6839 ST->getAlignment());
6840 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
6841 DAG.getConstant(4, Ptr.getValueType()));
6842 Alignment = MinAlign(Alignment, 4U);
6843 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
6844 Ptr, ST->getPointerInfo().getWithOffset(4),
6845 isVolatile, isNonTemporal,
6847 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
6856 // Try to infer better alignment information than the store already has.
6857 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
6858 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
6859 if (Align > ST->getAlignment())
6860 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
6861 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6862 ST->isVolatile(), ST->isNonTemporal(), Align);
6866 // Try transforming a pair floating point load / store ops to integer
6867 // load / store ops.
6868 SDValue NewST = TransformFPLoadStorePair(N);
6869 if (NewST.getNode())
6873 // Walk up chain skipping non-aliasing memory nodes.
6874 SDValue BetterChain = FindBetterChain(N, Chain);
6876 // If there is a better chain.
6877 if (Chain != BetterChain) {
6880 // Replace the chain to avoid dependency.
6881 if (ST->isTruncatingStore()) {
6882 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
6883 ST->getPointerInfo(),
6884 ST->getMemoryVT(), ST->isVolatile(),
6885 ST->isNonTemporal(), ST->getAlignment());
6887 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
6888 ST->getPointerInfo(),
6889 ST->isVolatile(), ST->isNonTemporal(),
6890 ST->getAlignment());
6893 // Create token to keep both nodes around.
6894 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
6895 MVT::Other, Chain, ReplStore);
6897 // Make sure the new and old chains are cleaned up.
6898 AddToWorkList(Token.getNode());
6900 // Don't add users to work list.
6901 return CombineTo(N, Token, false);
6905 // Try transforming N to an indexed store.
6906 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
6907 return SDValue(N, 0);
6909 // FIXME: is there such a thing as a truncating indexed store?
6910 if (ST->isTruncatingStore() && ST->isUnindexed() &&
6911 Value.getValueType().isInteger()) {
6912 // See if we can simplify the input to this truncstore with knowledge that
6913 // only the low bits are being used. For example:
6914 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
6916 GetDemandedBits(Value,
6917 APInt::getLowBitsSet(
6918 Value.getValueType().getScalarType().getSizeInBits(),
6919 ST->getMemoryVT().getScalarType().getSizeInBits()));
6920 AddToWorkList(Value.getNode());
6921 if (Shorter.getNode())
6922 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
6923 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6924 ST->isVolatile(), ST->isNonTemporal(),
6925 ST->getAlignment());
6927 // Otherwise, see if we can simplify the operation with
6928 // SimplifyDemandedBits, which only works if the value has a single use.
6929 if (SimplifyDemandedBits(Value,
6930 APInt::getLowBitsSet(
6931 Value.getValueType().getScalarType().getSizeInBits(),
6932 ST->getMemoryVT().getScalarType().getSizeInBits())))
6933 return SDValue(N, 0);
6936 // If this is a load followed by a store to the same location, then the store
6938 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
6939 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
6940 ST->isUnindexed() && !ST->isVolatile() &&
6941 // There can't be any side effects between the load and store, such as
6943 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
6944 // The store is dead, remove it.
6949 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
6950 // truncating store. We can do this even if this is already a truncstore.
6951 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
6952 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
6953 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
6954 ST->getMemoryVT())) {
6955 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
6956 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6957 ST->isVolatile(), ST->isNonTemporal(),
6958 ST->getAlignment());
6961 return ReduceLoadOpStoreWidth(N);
6964 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
6965 SDValue InVec = N->getOperand(0);
6966 SDValue InVal = N->getOperand(1);
6967 SDValue EltNo = N->getOperand(2);
6968 DebugLoc dl = N->getDebugLoc();
6970 // If the inserted element is an UNDEF, just use the input vector.
6971 if (InVal.getOpcode() == ISD::UNDEF)
6974 EVT VT = InVec.getValueType();
6976 // If we can't generate a legal BUILD_VECTOR, exit
6977 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
6980 // Check that we know which element is being inserted
6981 if (!isa<ConstantSDNode>(EltNo))
6983 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6985 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
6986 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
6988 SmallVector<SDValue, 8> Ops;
6989 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
6990 Ops.append(InVec.getNode()->op_begin(),
6991 InVec.getNode()->op_end());
6992 } else if (InVec.getOpcode() == ISD::UNDEF) {
6993 unsigned NElts = VT.getVectorNumElements();
6994 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
6999 // Insert the element
7000 if (Elt < Ops.size()) {
7001 // All the operands of BUILD_VECTOR must have the same type;
7002 // we enforce that here.
7003 EVT OpVT = Ops[0].getValueType();
7004 if (InVal.getValueType() != OpVT)
7005 InVal = OpVT.bitsGT(InVal.getValueType()) ?
7006 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
7007 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
7011 // Return the new vector
7012 return DAG.getNode(ISD::BUILD_VECTOR, dl,
7013 VT, &Ops[0], Ops.size());
7016 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
7017 // (vextract (scalar_to_vector val, 0) -> val
7018 SDValue InVec = N->getOperand(0);
7019 EVT VT = InVec.getValueType();
7020 EVT NVT = N->getValueType(0);
7022 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
7023 // Check if the result type doesn't match the inserted element type. A
7024 // SCALAR_TO_VECTOR may truncate the inserted element and the
7025 // EXTRACT_VECTOR_ELT may widen the extracted vector.
7026 SDValue InOp = InVec.getOperand(0);
7027 if (InOp.getValueType() != NVT) {
7028 assert(InOp.getValueType().isInteger() && NVT.isInteger());
7029 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
7034 SDValue EltNo = N->getOperand(1);
7035 bool ConstEltNo = isa<ConstantSDNode>(EltNo);
7037 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
7038 // We only perform this optimization before the op legalization phase because
7039 // we may introduce new vector instructions which are not backed by TD patterns.
7040 // For example on AVX, extracting elements from a wide vector without using
7041 // extract_subvector.
7042 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
7043 && ConstEltNo && !LegalOperations) {
7044 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
7045 int NumElem = VT.getVectorNumElements();
7046 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
7047 // Find the new index to extract from.
7048 int OrigElt = SVOp->getMaskElt(Elt);
7050 // Extracting an undef index is undef.
7052 return DAG.getUNDEF(NVT);
7054 // Select the right vector half to extract from.
7055 if (OrigElt < NumElem) {
7056 InVec = InVec->getOperand(0);
7058 InVec = InVec->getOperand(1);
7062 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT,
7063 InVec, DAG.getConstant(OrigElt, MVT::i32));
7066 // Perform only after legalization to ensure build_vector / vector_shuffle
7067 // optimizations have already been done.
7068 if (!LegalOperations) return SDValue();
7070 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
7071 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
7072 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
7075 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
7076 bool NewLoad = false;
7077 bool BCNumEltsChanged = false;
7078 EVT ExtVT = VT.getVectorElementType();
7081 if (InVec.getOpcode() == ISD::BITCAST) {
7082 // Don't duplicate a load with other uses.
7083 if (!InVec.hasOneUse())
7086 EVT BCVT = InVec.getOperand(0).getValueType();
7087 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
7089 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
7090 BCNumEltsChanged = true;
7091 InVec = InVec.getOperand(0);
7092 ExtVT = BCVT.getVectorElementType();
7096 LoadSDNode *LN0 = NULL;
7097 const ShuffleVectorSDNode *SVN = NULL;
7098 if (ISD::isNormalLoad(InVec.getNode())) {
7099 LN0 = cast<LoadSDNode>(InVec);
7100 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7101 InVec.getOperand(0).getValueType() == ExtVT &&
7102 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
7103 // Don't duplicate a load with other uses.
7104 if (!InVec.hasOneUse())
7107 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
7108 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
7109 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
7111 // (load $addr+1*size)
7113 // Don't duplicate a load with other uses.
7114 if (!InVec.hasOneUse())
7117 // If the bit convert changed the number of elements, it is unsafe
7118 // to examine the mask.
7119 if (BCNumEltsChanged)
7122 // Select the input vector, guarding against out of range extract vector.
7123 unsigned NumElems = VT.getVectorNumElements();
7124 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
7125 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
7127 if (InVec.getOpcode() == ISD::BITCAST) {
7128 // Don't duplicate a load with other uses.
7129 if (!InVec.hasOneUse())
7132 InVec = InVec.getOperand(0);
7134 if (ISD::isNormalLoad(InVec.getNode())) {
7135 LN0 = cast<LoadSDNode>(InVec);
7136 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
7140 // Make sure we found a non-volatile load and the extractelement is
7142 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
7145 // If Idx was -1 above, Elt is going to be -1, so just return undef.
7147 return DAG.getUNDEF(LVT);
7149 unsigned Align = LN0->getAlignment();
7151 // Check the resultant load doesn't need a higher alignment than the
7155 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
7157 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
7163 SDValue NewPtr = LN0->getBasePtr();
7164 unsigned PtrOff = 0;
7167 PtrOff = LVT.getSizeInBits() * Elt / 8;
7168 EVT PtrType = NewPtr.getValueType();
7169 if (TLI.isBigEndian())
7170 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
7171 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
7172 DAG.getConstant(PtrOff, PtrType));
7175 // The replacement we need to do here is a little tricky: we need to
7176 // replace an extractelement of a load with a load.
7177 // Use ReplaceAllUsesOfValuesWith to do the replacement.
7178 // Note that this replacement assumes that the extractvalue is the only
7179 // use of the load; that's okay because we don't want to perform this
7180 // transformation in other cases anyway.
7181 SDValue Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
7182 LN0->getPointerInfo().getWithOffset(PtrOff),
7183 LN0->isVolatile(), LN0->isNonTemporal(),
7184 LN0->isInvariant(), Align);
7185 WorkListRemover DeadNodes(*this);
7186 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) };
7187 SDValue To[] = { Load.getValue(0), Load.getValue(1) };
7188 DAG.ReplaceAllUsesOfValuesWith(From, To, 2, &DeadNodes);
7189 // Since we're explcitly calling ReplaceAllUses, add the new node to the
7190 // worklist explicitly as well.
7191 AddToWorkList(Load.getNode());
7192 // Make sure to revisit this node to clean it up; it will usually be dead.
7194 return SDValue(N, 0);
7200 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
7201 unsigned NumInScalars = N->getNumOperands();
7202 DebugLoc dl = N->getDebugLoc();
7203 EVT VT = N->getValueType(0);
7204 // Check to see if this is a BUILD_VECTOR of a bunch of values
7205 // which come from any_extend or zero_extend nodes. If so, we can create
7206 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR
7207 // optimizations. We do not handle sign-extend because we can't fill the sign
7209 EVT SourceType = MVT::Other;
7210 bool AllAnyExt = true;
7211 bool AllUndef = true;
7212 for (unsigned i = 0; i != NumInScalars; ++i) {
7213 SDValue In = N->getOperand(i);
7214 // Ignore undef inputs.
7215 if (In.getOpcode() == ISD::UNDEF) continue;
7218 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
7219 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
7221 // Abort if the element is not an extension.
7222 if (!ZeroExt && !AnyExt) {
7223 SourceType = MVT::Other;
7227 // The input is a ZeroExt or AnyExt. Check the original type.
7228 EVT InTy = In.getOperand(0).getValueType();
7230 // Check that all of the widened source types are the same.
7231 if (SourceType == MVT::Other)
7234 else if (InTy != SourceType) {
7235 // Multiple income types. Abort.
7236 SourceType = MVT::Other;
7240 // Check if all of the extends are ANY_EXTENDs.
7241 AllAnyExt &= AnyExt;
7245 return DAG.getUNDEF(VT);
7247 // In order to have valid types, all of the inputs must be extended from the
7248 // same source type and all of the inputs must be any or zero extend.
7249 // Scalar sizes must be a power of two.
7250 EVT OutScalarTy = N->getValueType(0).getScalarType();
7251 bool validTypes = SourceType != MVT::Other &&
7252 isPowerOf2_32(OutScalarTy.getSizeInBits()) &&
7253 isPowerOf2_32(SourceType.getSizeInBits());
7255 // We perform this optimization post type-legalization because
7256 // the type-legalizer often scalarizes integer-promoted vectors.
7257 // Performing this optimization before may create bit-casts which
7258 // will be type-legalized to complex code sequences.
7259 // We perform this optimization only before the operation legalizer because we
7260 // may introduce illegal operations.
7261 if (LegalTypes && !LegalOperations && validTypes) {
7262 bool isLE = TLI.isLittleEndian();
7263 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits();
7264 assert(ElemRatio > 1 && "Invalid element size ratio");
7265 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType):
7266 DAG.getConstant(0, SourceType);
7268 unsigned NewBVElems = ElemRatio * N->getValueType(0).getVectorNumElements();
7269 SmallVector<SDValue, 8> Ops(NewBVElems, Filler);
7271 // Populate the new build_vector
7272 for (unsigned i=0; i < N->getNumOperands(); ++i) {
7273 SDValue Cast = N->getOperand(i);
7274 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
7275 Cast.getOpcode() == ISD::ZERO_EXTEND ||
7276 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
7278 if (Cast.getOpcode() == ISD::UNDEF)
7279 In = DAG.getUNDEF(SourceType);
7281 In = Cast->getOperand(0);
7282 unsigned Index = isLE ? (i * ElemRatio) :
7283 (i * ElemRatio + (ElemRatio - 1));
7285 assert(Index < Ops.size() && "Invalid index");
7289 // The type of the new BUILD_VECTOR node.
7290 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems);
7291 assert(VecVT.getSizeInBits() == N->getValueType(0).getSizeInBits() &&
7292 "Invalid vector size");
7293 // Check if the new vector type is legal.
7294 if (!isTypeLegal(VecVT)) return SDValue();
7296 // Make the new BUILD_VECTOR.
7297 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
7298 VecVT, &Ops[0], Ops.size());
7300 // Bitcast to the desired type.
7301 return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV);
7304 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
7305 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
7306 // at most two distinct vectors, turn this into a shuffle node.
7307 SDValue VecIn1, VecIn2;
7308 for (unsigned i = 0; i != NumInScalars; ++i) {
7309 // Ignore undef inputs.
7310 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
7312 // If this input is something other than a EXTRACT_VECTOR_ELT with a
7313 // constant index, bail out.
7314 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
7315 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
7316 VecIn1 = VecIn2 = SDValue(0, 0);
7320 // If the input vector type disagrees with the result of the build_vector,
7321 // we can't make a shuffle.
7322 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
7323 if (ExtractedFromVec.getValueType() != VT) {
7324 VecIn1 = VecIn2 = SDValue(0, 0);
7328 // Otherwise, remember this. We allow up to two distinct input vectors.
7329 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
7332 if (VecIn1.getNode() == 0) {
7333 VecIn1 = ExtractedFromVec;
7334 } else if (VecIn2.getNode() == 0) {
7335 VecIn2 = ExtractedFromVec;
7338 VecIn1 = VecIn2 = SDValue(0, 0);
7343 // If everything is good, we can make a shuffle operation.
7344 if (VecIn1.getNode()) {
7345 SmallVector<int, 8> Mask;
7346 for (unsigned i = 0; i != NumInScalars; ++i) {
7347 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
7352 // If extracting from the first vector, just use the index directly.
7353 SDValue Extract = N->getOperand(i);
7354 SDValue ExtVal = Extract.getOperand(1);
7355 if (Extract.getOperand(0) == VecIn1) {
7356 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
7357 if (ExtIndex > VT.getVectorNumElements())
7360 Mask.push_back(ExtIndex);
7364 // Otherwise, use InIdx + VecSize
7365 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
7366 Mask.push_back(Idx+NumInScalars);
7369 // Add count and size info.
7370 if (!isTypeLegal(VT))
7373 // Return the new VECTOR_SHUFFLE node.
7376 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
7377 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
7383 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
7384 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
7385 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
7386 // inputs come from at most two distinct vectors, turn this into a shuffle
7389 // If we only have one input vector, we don't need to do any concatenation.
7390 if (N->getNumOperands() == 1)
7391 return N->getOperand(0);
7396 SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
7397 EVT NVT = N->getValueType(0);
7398 SDValue V = N->getOperand(0);
7400 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
7401 // Handle only simple case where vector being inserted and vector
7402 // being extracted are of same type, and are half size of larger vectors.
7403 EVT BigVT = V->getOperand(0).getValueType();
7404 EVT SmallVT = V->getOperand(1).getValueType();
7405 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits())
7408 // Only handle cases where both indexes are constants with the same type.
7409 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
7410 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(V->getOperand(2));
7412 if (InsIdx && ExtIdx &&
7413 InsIdx->getValueType(0).getSizeInBits() <= 64 &&
7414 ExtIdx->getValueType(0).getSizeInBits() <= 64) {
7416 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx)
7418 // indices are equal => V1
7419 // otherwise => (extract_subvec V1, ExtIdx)
7420 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue())
7421 return V->getOperand(1);
7422 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT,
7423 V->getOperand(0), N->getOperand(1));
7430 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
7431 EVT VT = N->getValueType(0);
7432 unsigned NumElts = VT.getVectorNumElements();
7434 SDValue N0 = N->getOperand(0);
7435 SDValue N1 = N->getOperand(1);
7437 assert(N0.getValueType().getVectorNumElements() == NumElts &&
7438 "Vector shuffle must be normalized in DAG");
7440 // Canonicalize shuffle undef, undef -> undef
7441 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
7442 return DAG.getUNDEF(VT);
7444 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
7446 // Canonicalize shuffle v, v -> v, undef
7448 SmallVector<int, 8> NewMask;
7449 for (unsigned i = 0; i != NumElts; ++i) {
7450 int Idx = SVN->getMaskElt(i);
7451 if (Idx >= (int)NumElts) Idx -= NumElts;
7452 NewMask.push_back(Idx);
7454 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT),
7458 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
7459 if (N0.getOpcode() == ISD::UNDEF) {
7460 SmallVector<int, 8> NewMask;
7461 for (unsigned i = 0; i != NumElts; ++i) {
7462 int Idx = SVN->getMaskElt(i);
7464 NewMask.push_back(Idx);
7465 else if (Idx < (int)NumElts)
7466 NewMask.push_back(Idx + NumElts);
7468 NewMask.push_back(Idx - NumElts);
7470 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT),
7474 // Remove references to rhs if it is undef
7475 if (N1.getOpcode() == ISD::UNDEF) {
7476 bool Changed = false;
7477 SmallVector<int, 8> NewMask;
7478 for (unsigned i = 0; i != NumElts; ++i) {
7479 int Idx = SVN->getMaskElt(i);
7480 if (Idx >= (int)NumElts) {
7484 NewMask.push_back(Idx);
7487 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]);
7490 // If it is a splat, check if the argument vector is another splat or a
7491 // build_vector with all scalar elements the same.
7492 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
7493 SDNode *V = N0.getNode();
7495 // If this is a bit convert that changes the element type of the vector but
7496 // not the number of vector elements, look through it. Be careful not to
7497 // look though conversions that change things like v4f32 to v2f64.
7498 if (V->getOpcode() == ISD::BITCAST) {
7499 SDValue ConvInput = V->getOperand(0);
7500 if (ConvInput.getValueType().isVector() &&
7501 ConvInput.getValueType().getVectorNumElements() == NumElts)
7502 V = ConvInput.getNode();
7505 if (V->getOpcode() == ISD::BUILD_VECTOR) {
7506 assert(V->getNumOperands() == NumElts &&
7507 "BUILD_VECTOR has wrong number of operands");
7509 bool AllSame = true;
7510 for (unsigned i = 0; i != NumElts; ++i) {
7511 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
7512 Base = V->getOperand(i);
7516 // Splat of <u, u, u, u>, return <u, u, u, u>
7517 if (!Base.getNode())
7519 for (unsigned i = 0; i != NumElts; ++i) {
7520 if (V->getOperand(i) != Base) {
7525 // Splat of <x, x, x, x>, return <x, x, x, x>
7533 SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) {
7534 if (!TLI.getShouldFoldAtomicFences())
7537 SDValue atomic = N->getOperand(0);
7538 switch (atomic.getOpcode()) {
7539 case ISD::ATOMIC_CMP_SWAP:
7540 case ISD::ATOMIC_SWAP:
7541 case ISD::ATOMIC_LOAD_ADD:
7542 case ISD::ATOMIC_LOAD_SUB:
7543 case ISD::ATOMIC_LOAD_AND:
7544 case ISD::ATOMIC_LOAD_OR:
7545 case ISD::ATOMIC_LOAD_XOR:
7546 case ISD::ATOMIC_LOAD_NAND:
7547 case ISD::ATOMIC_LOAD_MIN:
7548 case ISD::ATOMIC_LOAD_MAX:
7549 case ISD::ATOMIC_LOAD_UMIN:
7550 case ISD::ATOMIC_LOAD_UMAX:
7556 SDValue fence = atomic.getOperand(0);
7557 if (fence.getOpcode() != ISD::MEMBARRIER)
7560 switch (atomic.getOpcode()) {
7561 case ISD::ATOMIC_CMP_SWAP:
7562 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
7563 fence.getOperand(0),
7564 atomic.getOperand(1), atomic.getOperand(2),
7565 atomic.getOperand(3)), atomic.getResNo());
7566 case ISD::ATOMIC_SWAP:
7567 case ISD::ATOMIC_LOAD_ADD:
7568 case ISD::ATOMIC_LOAD_SUB:
7569 case ISD::ATOMIC_LOAD_AND:
7570 case ISD::ATOMIC_LOAD_OR:
7571 case ISD::ATOMIC_LOAD_XOR:
7572 case ISD::ATOMIC_LOAD_NAND:
7573 case ISD::ATOMIC_LOAD_MIN:
7574 case ISD::ATOMIC_LOAD_MAX:
7575 case ISD::ATOMIC_LOAD_UMIN:
7576 case ISD::ATOMIC_LOAD_UMAX:
7577 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
7578 fence.getOperand(0),
7579 atomic.getOperand(1), atomic.getOperand(2)),
7586 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
7587 /// an AND to a vector_shuffle with the destination vector and a zero vector.
7588 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
7589 /// vector_shuffle V, Zero, <0, 4, 2, 4>
7590 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
7591 EVT VT = N->getValueType(0);
7592 DebugLoc dl = N->getDebugLoc();
7593 SDValue LHS = N->getOperand(0);
7594 SDValue RHS = N->getOperand(1);
7595 if (N->getOpcode() == ISD::AND) {
7596 if (RHS.getOpcode() == ISD::BITCAST)
7597 RHS = RHS.getOperand(0);
7598 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
7599 SmallVector<int, 8> Indices;
7600 unsigned NumElts = RHS.getNumOperands();
7601 for (unsigned i = 0; i != NumElts; ++i) {
7602 SDValue Elt = RHS.getOperand(i);
7603 if (!isa<ConstantSDNode>(Elt))
7605 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
7606 Indices.push_back(i);
7607 else if (cast<ConstantSDNode>(Elt)->isNullValue())
7608 Indices.push_back(NumElts);
7613 // Let's see if the target supports this vector_shuffle.
7614 EVT RVT = RHS.getValueType();
7615 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
7618 // Return the new VECTOR_SHUFFLE node.
7619 EVT EltVT = RVT.getVectorElementType();
7620 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
7621 DAG.getConstant(0, EltVT));
7622 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
7623 RVT, &ZeroOps[0], ZeroOps.size());
7624 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
7625 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
7626 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
7633 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
7634 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
7635 // After legalize, the target may be depending on adds and other
7636 // binary ops to provide legal ways to construct constants or other
7637 // things. Simplifying them may result in a loss of legality.
7638 if (LegalOperations) return SDValue();
7640 assert(N->getValueType(0).isVector() &&
7641 "SimplifyVBinOp only works on vectors!");
7643 SDValue LHS = N->getOperand(0);
7644 SDValue RHS = N->getOperand(1);
7645 SDValue Shuffle = XformToShuffleWithZero(N);
7646 if (Shuffle.getNode()) return Shuffle;
7648 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
7650 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
7651 RHS.getOpcode() == ISD::BUILD_VECTOR) {
7652 SmallVector<SDValue, 8> Ops;
7653 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
7654 SDValue LHSOp = LHS.getOperand(i);
7655 SDValue RHSOp = RHS.getOperand(i);
7656 // If these two elements can't be folded, bail out.
7657 if ((LHSOp.getOpcode() != ISD::UNDEF &&
7658 LHSOp.getOpcode() != ISD::Constant &&
7659 LHSOp.getOpcode() != ISD::ConstantFP) ||
7660 (RHSOp.getOpcode() != ISD::UNDEF &&
7661 RHSOp.getOpcode() != ISD::Constant &&
7662 RHSOp.getOpcode() != ISD::ConstantFP))
7665 // Can't fold divide by zero.
7666 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
7667 N->getOpcode() == ISD::FDIV) {
7668 if ((RHSOp.getOpcode() == ISD::Constant &&
7669 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
7670 (RHSOp.getOpcode() == ISD::ConstantFP &&
7671 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
7675 EVT VT = LHSOp.getValueType();
7676 EVT RVT = RHSOp.getValueType();
7678 // Integer BUILD_VECTOR operands may have types larger than the element
7679 // size (e.g., when the element type is not legal). Prior to type
7680 // legalization, the types may not match between the two BUILD_VECTORS.
7681 // Truncate one of the operands to make them match.
7682 if (RVT.getSizeInBits() > VT.getSizeInBits()) {
7683 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp);
7685 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp);
7689 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT,
7691 if (FoldOp.getOpcode() != ISD::UNDEF &&
7692 FoldOp.getOpcode() != ISD::Constant &&
7693 FoldOp.getOpcode() != ISD::ConstantFP)
7695 Ops.push_back(FoldOp);
7696 AddToWorkList(FoldOp.getNode());
7699 if (Ops.size() == LHS.getNumOperands())
7700 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
7701 LHS.getValueType(), &Ops[0], Ops.size());
7707 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
7708 SDValue N1, SDValue N2){
7709 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
7711 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
7712 cast<CondCodeSDNode>(N0.getOperand(2))->get());
7714 // If we got a simplified select_cc node back from SimplifySelectCC, then
7715 // break it down into a new SETCC node, and a new SELECT node, and then return
7716 // the SELECT node, since we were called with a SELECT node.
7717 if (SCC.getNode()) {
7718 // Check to see if we got a select_cc back (to turn into setcc/select).
7719 // Otherwise, just return whatever node we got back, like fabs.
7720 if (SCC.getOpcode() == ISD::SELECT_CC) {
7721 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
7723 SCC.getOperand(0), SCC.getOperand(1),
7725 AddToWorkList(SETCC.getNode());
7726 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
7727 SCC.getOperand(2), SCC.getOperand(3), SETCC);
7735 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
7736 /// are the two values being selected between, see if we can simplify the
7737 /// select. Callers of this should assume that TheSelect is deleted if this
7738 /// returns true. As such, they should return the appropriate thing (e.g. the
7739 /// node) back to the top-level of the DAG combiner loop to avoid it being
7741 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
7744 // Cannot simplify select with vector condition
7745 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
7747 // If this is a select from two identical things, try to pull the operation
7748 // through the select.
7749 if (LHS.getOpcode() != RHS.getOpcode() ||
7750 !LHS.hasOneUse() || !RHS.hasOneUse())
7753 // If this is a load and the token chain is identical, replace the select
7754 // of two loads with a load through a select of the address to load from.
7755 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
7756 // constants have been dropped into the constant pool.
7757 if (LHS.getOpcode() == ISD::LOAD) {
7758 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
7759 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
7761 // Token chains must be identical.
7762 if (LHS.getOperand(0) != RHS.getOperand(0) ||
7763 // Do not let this transformation reduce the number of volatile loads.
7764 LLD->isVolatile() || RLD->isVolatile() ||
7765 // If this is an EXTLOAD, the VT's must match.
7766 LLD->getMemoryVT() != RLD->getMemoryVT() ||
7767 // If this is an EXTLOAD, the kind of extension must match.
7768 (LLD->getExtensionType() != RLD->getExtensionType() &&
7769 // The only exception is if one of the extensions is anyext.
7770 LLD->getExtensionType() != ISD::EXTLOAD &&
7771 RLD->getExtensionType() != ISD::EXTLOAD) ||
7772 // FIXME: this discards src value information. This is
7773 // over-conservative. It would be beneficial to be able to remember
7774 // both potential memory locations. Since we are discarding
7775 // src value info, don't do the transformation if the memory
7776 // locations are not in the default address space.
7777 LLD->getPointerInfo().getAddrSpace() != 0 ||
7778 RLD->getPointerInfo().getAddrSpace() != 0)
7781 // Check that the select condition doesn't reach either load. If so,
7782 // folding this will induce a cycle into the DAG. If not, this is safe to
7783 // xform, so create a select of the addresses.
7785 if (TheSelect->getOpcode() == ISD::SELECT) {
7786 SDNode *CondNode = TheSelect->getOperand(0).getNode();
7787 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
7788 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
7790 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
7791 LLD->getBasePtr().getValueType(),
7792 TheSelect->getOperand(0), LLD->getBasePtr(),
7794 } else { // Otherwise SELECT_CC
7795 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
7796 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
7798 if ((LLD->hasAnyUseOfValue(1) &&
7799 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
7800 (LLD->hasAnyUseOfValue(1) &&
7801 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))))
7804 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
7805 LLD->getBasePtr().getValueType(),
7806 TheSelect->getOperand(0),
7807 TheSelect->getOperand(1),
7808 LLD->getBasePtr(), RLD->getBasePtr(),
7809 TheSelect->getOperand(4));
7813 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
7814 Load = DAG.getLoad(TheSelect->getValueType(0),
7815 TheSelect->getDebugLoc(),
7816 // FIXME: Discards pointer info.
7817 LLD->getChain(), Addr, MachinePointerInfo(),
7818 LLD->isVolatile(), LLD->isNonTemporal(),
7819 LLD->isInvariant(), LLD->getAlignment());
7821 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
7822 RLD->getExtensionType() : LLD->getExtensionType(),
7823 TheSelect->getDebugLoc(),
7824 TheSelect->getValueType(0),
7825 // FIXME: Discards pointer info.
7826 LLD->getChain(), Addr, MachinePointerInfo(),
7827 LLD->getMemoryVT(), LLD->isVolatile(),
7828 LLD->isNonTemporal(), LLD->getAlignment());
7831 // Users of the select now use the result of the load.
7832 CombineTo(TheSelect, Load);
7834 // Users of the old loads now use the new load's chain. We know the
7835 // old-load value is dead now.
7836 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
7837 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
7844 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
7845 /// where 'cond' is the comparison specified by CC.
7846 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
7847 SDValue N2, SDValue N3,
7848 ISD::CondCode CC, bool NotExtCompare) {
7849 // (x ? y : y) -> y.
7850 if (N2 == N3) return N2;
7852 EVT VT = N2.getValueType();
7853 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
7854 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
7855 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
7857 // Determine if the condition we're dealing with is constant
7858 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
7859 N0, N1, CC, DL, false);
7860 if (SCC.getNode()) AddToWorkList(SCC.getNode());
7861 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
7863 // fold select_cc true, x, y -> x
7864 if (SCCC && !SCCC->isNullValue())
7866 // fold select_cc false, x, y -> y
7867 if (SCCC && SCCC->isNullValue())
7870 // Check to see if we can simplify the select into an fabs node
7871 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
7872 // Allow either -0.0 or 0.0
7873 if (CFP->getValueAPF().isZero()) {
7874 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
7875 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
7876 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
7877 N2 == N3.getOperand(0))
7878 return DAG.getNode(ISD::FABS, DL, VT, N0);
7880 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
7881 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
7882 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
7883 N2.getOperand(0) == N3)
7884 return DAG.getNode(ISD::FABS, DL, VT, N3);
7888 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
7889 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
7890 // in it. This is a win when the constant is not otherwise available because
7891 // it replaces two constant pool loads with one. We only do this if the FP
7892 // type is known to be legal, because if it isn't, then we are before legalize
7893 // types an we want the other legalization to happen first (e.g. to avoid
7894 // messing with soft float) and if the ConstantFP is not legal, because if
7895 // it is legal, we may not need to store the FP constant in a constant pool.
7896 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
7897 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
7898 if (TLI.isTypeLegal(N2.getValueType()) &&
7899 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
7900 TargetLowering::Legal) &&
7901 // If both constants have multiple uses, then we won't need to do an
7902 // extra load, they are likely around in registers for other users.
7903 (TV->hasOneUse() || FV->hasOneUse())) {
7904 Constant *Elts[] = {
7905 const_cast<ConstantFP*>(FV->getConstantFPValue()),
7906 const_cast<ConstantFP*>(TV->getConstantFPValue())
7908 Type *FPTy = Elts[0]->getType();
7909 const TargetData &TD = *TLI.getTargetData();
7911 // Create a ConstantArray of the two constants.
7912 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
7913 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
7914 TD.getPrefTypeAlignment(FPTy));
7915 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
7917 // Get the offsets to the 0 and 1 element of the array so that we can
7918 // select between them.
7919 SDValue Zero = DAG.getIntPtrConstant(0);
7920 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
7921 SDValue One = DAG.getIntPtrConstant(EltSize);
7923 SDValue Cond = DAG.getSetCC(DL,
7924 TLI.getSetCCResultType(N0.getValueType()),
7926 AddToWorkList(Cond.getNode());
7927 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
7929 AddToWorkList(CstOffset.getNode());
7930 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
7932 AddToWorkList(CPIdx.getNode());
7933 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
7934 MachinePointerInfo::getConstantPool(), false,
7935 false, false, Alignment);
7940 // Check to see if we can perform the "gzip trick", transforming
7941 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
7942 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
7943 (N1C->isNullValue() || // (a < 0) ? b : 0
7944 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
7945 EVT XType = N0.getValueType();
7946 EVT AType = N2.getValueType();
7947 if (XType.bitsGE(AType)) {
7948 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
7949 // single-bit constant.
7950 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
7951 unsigned ShCtV = N2C->getAPIntValue().logBase2();
7952 ShCtV = XType.getSizeInBits()-ShCtV-1;
7953 SDValue ShCt = DAG.getConstant(ShCtV,
7954 getShiftAmountTy(N0.getValueType()));
7955 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
7957 AddToWorkList(Shift.getNode());
7959 if (XType.bitsGT(AType)) {
7960 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
7961 AddToWorkList(Shift.getNode());
7964 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
7967 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
7969 DAG.getConstant(XType.getSizeInBits()-1,
7970 getShiftAmountTy(N0.getValueType())));
7971 AddToWorkList(Shift.getNode());
7973 if (XType.bitsGT(AType)) {
7974 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
7975 AddToWorkList(Shift.getNode());
7978 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
7982 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
7983 // where y is has a single bit set.
7984 // A plaintext description would be, we can turn the SELECT_CC into an AND
7985 // when the condition can be materialized as an all-ones register. Any
7986 // single bit-test can be materialized as an all-ones register with
7987 // shift-left and shift-right-arith.
7988 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
7989 N0->getValueType(0) == VT &&
7990 N1C && N1C->isNullValue() &&
7991 N2C && N2C->isNullValue()) {
7992 SDValue AndLHS = N0->getOperand(0);
7993 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
7994 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
7995 // Shift the tested bit over the sign bit.
7996 APInt AndMask = ConstAndRHS->getAPIntValue();
7998 DAG.getConstant(AndMask.countLeadingZeros(),
7999 getShiftAmountTy(AndLHS.getValueType()));
8000 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt);
8002 // Now arithmetic right shift it all the way over, so the result is either
8003 // all-ones, or zero.
8005 DAG.getConstant(AndMask.getBitWidth()-1,
8006 getShiftAmountTy(Shl.getValueType()));
8007 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt);
8009 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
8013 // fold select C, 16, 0 -> shl C, 4
8014 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
8015 TLI.getBooleanContents(N0.getValueType().isVector()) ==
8016 TargetLowering::ZeroOrOneBooleanContent) {
8018 // If the caller doesn't want us to simplify this into a zext of a compare,
8020 if (NotExtCompare && N2C->getAPIntValue() == 1)
8023 // Get a SetCC of the condition
8024 // FIXME: Should probably make sure that setcc is legal if we ever have a
8025 // target where it isn't.
8027 // cast from setcc result type to select result type
8029 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
8031 if (N2.getValueType().bitsLT(SCC.getValueType()))
8032 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
8034 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
8035 N2.getValueType(), SCC);
8037 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
8038 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
8039 N2.getValueType(), SCC);
8042 AddToWorkList(SCC.getNode());
8043 AddToWorkList(Temp.getNode());
8045 if (N2C->getAPIntValue() == 1)
8048 // shl setcc result by log2 n2c
8049 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
8050 DAG.getConstant(N2C->getAPIntValue().logBase2(),
8051 getShiftAmountTy(Temp.getValueType())));
8054 // Check to see if this is the equivalent of setcc
8055 // FIXME: Turn all of these into setcc if setcc if setcc is legal
8056 // otherwise, go ahead with the folds.
8057 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
8058 EVT XType = N0.getValueType();
8059 if (!LegalOperations ||
8060 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
8061 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
8062 if (Res.getValueType() != VT)
8063 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
8067 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
8068 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
8069 (!LegalOperations ||
8070 TLI.isOperationLegal(ISD::CTLZ, XType))) {
8071 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
8072 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
8073 DAG.getConstant(Log2_32(XType.getSizeInBits()),
8074 getShiftAmountTy(Ctlz.getValueType())));
8076 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
8077 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
8078 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
8079 XType, DAG.getConstant(0, XType), N0);
8080 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
8081 return DAG.getNode(ISD::SRL, DL, XType,
8082 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
8083 DAG.getConstant(XType.getSizeInBits()-1,
8084 getShiftAmountTy(XType)));
8086 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
8087 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
8088 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
8089 DAG.getConstant(XType.getSizeInBits()-1,
8090 getShiftAmountTy(N0.getValueType())));
8091 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
8095 // Check to see if this is an integer abs.
8096 // select_cc setg[te] X, 0, X, -X ->
8097 // select_cc setgt X, -1, X, -X ->
8098 // select_cc setl[te] X, 0, -X, X ->
8099 // select_cc setlt X, 1, -X, X ->
8100 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
8102 ConstantSDNode *SubC = NULL;
8103 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
8104 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
8105 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
8106 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
8107 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
8108 (N1C->isOne() && CC == ISD::SETLT)) &&
8109 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
8110 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
8112 EVT XType = N0.getValueType();
8113 if (SubC && SubC->isNullValue() && XType.isInteger()) {
8114 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
8116 DAG.getConstant(XType.getSizeInBits()-1,
8117 getShiftAmountTy(N0.getValueType())));
8118 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
8120 AddToWorkList(Shift.getNode());
8121 AddToWorkList(Add.getNode());
8122 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
8129 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
8130 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
8131 SDValue N1, ISD::CondCode Cond,
8132 DebugLoc DL, bool foldBooleans) {
8133 TargetLowering::DAGCombinerInfo
8134 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
8135 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
8138 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
8139 /// return a DAG expression to select that will generate the same value by
8140 /// multiplying by a magic number. See:
8141 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
8142 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
8143 std::vector<SDNode*> Built;
8144 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built);
8146 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
8152 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
8153 /// return a DAG expression to select that will generate the same value by
8154 /// multiplying by a magic number. See:
8155 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
8156 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
8157 std::vector<SDNode*> Built;
8158 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built);
8160 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
8166 /// FindBaseOffset - Return true if base is a frame index, which is known not
8167 // to alias with anything but itself. Provides base object and offset as
8169 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
8170 const GlobalValue *&GV, void *&CV) {
8171 // Assume it is a primitive operation.
8172 Base = Ptr; Offset = 0; GV = 0; CV = 0;
8174 // If it's an adding a simple constant then integrate the offset.
8175 if (Base.getOpcode() == ISD::ADD) {
8176 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
8177 Base = Base.getOperand(0);
8178 Offset += C->getZExtValue();
8182 // Return the underlying GlobalValue, and update the Offset. Return false
8183 // for GlobalAddressSDNode since the same GlobalAddress may be represented
8184 // by multiple nodes with different offsets.
8185 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
8186 GV = G->getGlobal();
8187 Offset += G->getOffset();
8191 // Return the underlying Constant value, and update the Offset. Return false
8192 // for ConstantSDNodes since the same constant pool entry may be represented
8193 // by multiple nodes with different offsets.
8194 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
8195 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal()
8196 : (void *)C->getConstVal();
8197 Offset += C->getOffset();
8200 // If it's any of the following then it can't alias with anything but itself.
8201 return isa<FrameIndexSDNode>(Base);
8204 /// isAlias - Return true if there is any possibility that the two addresses
8206 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
8207 const Value *SrcValue1, int SrcValueOffset1,
8208 unsigned SrcValueAlign1,
8209 const MDNode *TBAAInfo1,
8210 SDValue Ptr2, int64_t Size2,
8211 const Value *SrcValue2, int SrcValueOffset2,
8212 unsigned SrcValueAlign2,
8213 const MDNode *TBAAInfo2) const {
8214 // If they are the same then they must be aliases.
8215 if (Ptr1 == Ptr2) return true;
8217 // Gather base node and offset information.
8218 SDValue Base1, Base2;
8219 int64_t Offset1, Offset2;
8220 const GlobalValue *GV1, *GV2;
8222 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
8223 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
8225 // If they have a same base address then check to see if they overlap.
8226 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
8227 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
8229 // It is possible for different frame indices to alias each other, mostly
8230 // when tail call optimization reuses return address slots for arguments.
8231 // To catch this case, look up the actual index of frame indices to compute
8232 // the real alias relationship.
8233 if (isFrameIndex1 && isFrameIndex2) {
8234 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8235 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
8236 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
8237 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
8240 // Otherwise, if we know what the bases are, and they aren't identical, then
8241 // we know they cannot alias.
8242 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
8245 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
8246 // compared to the size and offset of the access, we may be able to prove they
8247 // do not alias. This check is conservative for now to catch cases created by
8248 // splitting vector types.
8249 if ((SrcValueAlign1 == SrcValueAlign2) &&
8250 (SrcValueOffset1 != SrcValueOffset2) &&
8251 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
8252 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
8253 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
8255 // There is no overlap between these relatively aligned accesses of similar
8256 // size, return no alias.
8257 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
8261 if (CombinerGlobalAA) {
8262 // Use alias analysis information.
8263 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
8264 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
8265 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
8266 AliasAnalysis::AliasResult AAResult =
8267 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1),
8268 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2));
8269 if (AAResult == AliasAnalysis::NoAlias)
8273 // Otherwise we have to assume they alias.
8277 /// FindAliasInfo - Extracts the relevant alias information from the memory
8278 /// node. Returns true if the operand was a load.
8279 bool DAGCombiner::FindAliasInfo(SDNode *N,
8280 SDValue &Ptr, int64_t &Size,
8281 const Value *&SrcValue,
8282 int &SrcValueOffset,
8283 unsigned &SrcValueAlign,
8284 const MDNode *&TBAAInfo) const {
8285 LSBaseSDNode *LS = cast<LSBaseSDNode>(N);
8287 Ptr = LS->getBasePtr();
8288 Size = LS->getMemoryVT().getSizeInBits() >> 3;
8289 SrcValue = LS->getSrcValue();
8290 SrcValueOffset = LS->getSrcValueOffset();
8291 SrcValueAlign = LS->getOriginalAlignment();
8292 TBAAInfo = LS->getTBAAInfo();
8293 return isa<LoadSDNode>(LS);
8296 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
8297 /// looking for aliasing nodes and adding them to the Aliases vector.
8298 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
8299 SmallVector<SDValue, 8> &Aliases) {
8300 SmallVector<SDValue, 8> Chains; // List of chains to visit.
8301 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
8303 // Get alias information for node.
8306 const Value *SrcValue;
8308 unsigned SrcValueAlign;
8309 const MDNode *SrcTBAAInfo;
8310 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
8311 SrcValueAlign, SrcTBAAInfo);
8314 Chains.push_back(OriginalChain);
8317 // Look at each chain and determine if it is an alias. If so, add it to the
8318 // aliases list. If not, then continue up the chain looking for the next
8320 while (!Chains.empty()) {
8321 SDValue Chain = Chains.back();
8324 // For TokenFactor nodes, look at each operand and only continue up the
8325 // chain until we find two aliases. If we've seen two aliases, assume we'll
8326 // find more and revert to original chain since the xform is unlikely to be
8329 // FIXME: The depth check could be made to return the last non-aliasing
8330 // chain we found before we hit a tokenfactor rather than the original
8332 if (Depth > 6 || Aliases.size() == 2) {
8334 Aliases.push_back(OriginalChain);
8338 // Don't bother if we've been before.
8339 if (!Visited.insert(Chain.getNode()))
8342 switch (Chain.getOpcode()) {
8343 case ISD::EntryToken:
8344 // Entry token is ideal chain operand, but handled in FindBetterChain.
8349 // Get alias information for Chain.
8352 const Value *OpSrcValue;
8353 int OpSrcValueOffset;
8354 unsigned OpSrcValueAlign;
8355 const MDNode *OpSrcTBAAInfo;
8356 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
8357 OpSrcValue, OpSrcValueOffset,
8361 // If chain is alias then stop here.
8362 if (!(IsLoad && IsOpLoad) &&
8363 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
8365 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
8366 OpSrcValueAlign, OpSrcTBAAInfo)) {
8367 Aliases.push_back(Chain);
8369 // Look further up the chain.
8370 Chains.push_back(Chain.getOperand(0));
8376 case ISD::TokenFactor:
8377 // We have to check each of the operands of the token factor for "small"
8378 // token factors, so we queue them up. Adding the operands to the queue
8379 // (stack) in reverse order maintains the original order and increases the
8380 // likelihood that getNode will find a matching token factor (CSE.)
8381 if (Chain.getNumOperands() > 16) {
8382 Aliases.push_back(Chain);
8385 for (unsigned n = Chain.getNumOperands(); n;)
8386 Chains.push_back(Chain.getOperand(--n));
8391 // For all other instructions we will just have to take what we can get.
8392 Aliases.push_back(Chain);
8398 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
8399 /// for a better chain (aliasing node.)
8400 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
8401 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
8403 // Accumulate all the aliases to this node.
8404 GatherAllAliases(N, OldChain, Aliases);
8406 // If no operands then chain to entry token.
8407 if (Aliases.size() == 0)
8408 return DAG.getEntryNode();
8410 // If a single operand then chain to it. We don't need to revisit it.
8411 if (Aliases.size() == 1)
8414 // Construct a custom tailored token factor.
8415 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
8416 &Aliases[0], Aliases.size());
8419 // SelectionDAG::Combine - This is the entry point for the file.
8421 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
8422 CodeGenOpt::Level OptLevel) {
8423 /// run - This is the main entry point to this class.
8425 DAGCombiner(*this, AA, OptLevel).Run(Level);