1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "dagcombine"
16 #include "llvm/CodeGen/SelectionDAG.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Target/TargetData.h"
21 #include "llvm/Target/TargetFrameInfo.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/SmallPtrSet.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/MathExtras.h"
34 STATISTIC(NodesCombined , "Number of dag nodes combined");
35 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
36 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
41 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
42 cl::desc("Pop up a window to show dags before the first "
45 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
46 cl::desc("Pop up a window to show dags before the second "
49 static const bool ViewDAGCombine1 = false;
50 static const bool ViewDAGCombine2 = false;
54 CombinerAA("combiner-alias-analysis", cl::Hidden,
55 cl::desc("Turn on alias analysis during testing"));
58 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
59 cl::desc("Include global information in alias analysis"));
61 //------------------------------ DAGCombiner ---------------------------------//
63 class VISIBILITY_HIDDEN DAGCombiner {
68 // Worklist of all of the nodes that need to be simplified.
69 std::vector<SDNode*> WorkList;
71 // AA - Used for DAG load/store alias analysis.
74 /// AddUsersToWorkList - When an instruction is simplified, add all users of
75 /// the instruction to the work lists because they might get more simplified
78 void AddUsersToWorkList(SDNode *N) {
79 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
84 /// removeFromWorkList - remove all instances of N from the worklist.
86 void removeFromWorkList(SDNode *N) {
87 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
91 /// visit - call the node-specific routine that knows how to fold each
92 /// particular type of node.
93 SDOperand visit(SDNode *N);
96 /// AddToWorkList - Add to the work list making sure it's instance is at the
97 /// the back (next to be processed.)
98 void AddToWorkList(SDNode *N) {
99 removeFromWorkList(N);
100 WorkList.push_back(N);
103 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
105 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
107 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
108 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
109 DOUT << " and " << NumTo-1 << " other values\n";
110 std::vector<SDNode*> NowDead;
111 DAG.ReplaceAllUsesWith(N, To, &NowDead);
114 // Push the new nodes and any users onto the worklist
115 for (unsigned i = 0, e = NumTo; i != e; ++i) {
116 AddToWorkList(To[i].Val);
117 AddUsersToWorkList(To[i].Val);
121 // Nodes can be reintroduced into the worklist. Make sure we do not
122 // process a node that has been replaced.
123 removeFromWorkList(N);
124 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
125 removeFromWorkList(NowDead[i]);
127 // Finally, since the node is now dead, remove it from the graph.
129 return SDOperand(N, 0);
132 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
133 return CombineTo(N, &Res, 1, AddTo);
136 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
138 SDOperand To[] = { Res0, Res1 };
139 return CombineTo(N, To, 2, AddTo);
144 /// SimplifyDemandedBits - Check the specified integer node value to see if
145 /// it can be simplified or if things it uses can be simplified by bit
146 /// propagation. If so, return true.
147 bool SimplifyDemandedBits(SDOperand Op, uint64_t Demanded = ~0ULL) {
148 TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize);
149 uint64_t KnownZero, KnownOne;
150 Demanded &= MVT::getIntVTBitMask(Op.getValueType());
151 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
155 AddToWorkList(Op.Val);
157 // Replace the old value with the new one.
159 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG));
160 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
163 std::vector<SDNode*> NowDead;
164 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &NowDead);
166 // Push the new node and any (possibly new) users onto the worklist.
167 AddToWorkList(TLO.New.Val);
168 AddUsersToWorkList(TLO.New.Val);
170 // Nodes can end up on the worklist more than once. Make sure we do
171 // not process a node that has been replaced.
172 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
173 removeFromWorkList(NowDead[i]);
175 // Finally, if the node is now dead, remove it from the graph. The node
176 // may not be dead if the replacement process recursively simplified to
177 // something else needing this node.
178 if (TLO.Old.Val->use_empty()) {
179 removeFromWorkList(TLO.Old.Val);
181 // If the operands of this node are only used by the node, they will now
182 // be dead. Make sure to visit them first to delete dead nodes early.
183 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i)
184 if (TLO.Old.Val->getOperand(i).Val->hasOneUse())
185 AddToWorkList(TLO.Old.Val->getOperand(i).Val);
187 DAG.DeleteNode(TLO.Old.Val);
192 bool CombineToPreIndexedLoadStore(SDNode *N);
193 bool CombineToPostIndexedLoadStore(SDNode *N);
196 /// combine - call the node-specific routine that knows how to fold each
197 /// particular type of node. If that doesn't do anything, try the
198 /// target-specific DAG combines.
199 SDOperand combine(SDNode *N);
201 // Visitation implementation - Implement dag node combining for different
202 // node types. The semantics are as follows:
204 // SDOperand.Val == 0 - No change was made
205 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
206 // otherwise - N should be replaced by the returned Operand.
208 SDOperand visitTokenFactor(SDNode *N);
209 SDOperand visitADD(SDNode *N);
210 SDOperand visitSUB(SDNode *N);
211 SDOperand visitADDC(SDNode *N);
212 SDOperand visitADDE(SDNode *N);
213 SDOperand visitMUL(SDNode *N);
214 SDOperand visitSDIV(SDNode *N);
215 SDOperand visitUDIV(SDNode *N);
216 SDOperand visitSREM(SDNode *N);
217 SDOperand visitUREM(SDNode *N);
218 SDOperand visitMULHU(SDNode *N);
219 SDOperand visitMULHS(SDNode *N);
220 SDOperand visitSMUL_LOHI(SDNode *N);
221 SDOperand visitUMUL_LOHI(SDNode *N);
222 SDOperand visitSDIVREM(SDNode *N);
223 SDOperand visitUDIVREM(SDNode *N);
224 SDOperand visitAND(SDNode *N);
225 SDOperand visitOR(SDNode *N);
226 SDOperand visitXOR(SDNode *N);
227 SDOperand SimplifyVBinOp(SDNode *N);
228 SDOperand visitSHL(SDNode *N);
229 SDOperand visitSRA(SDNode *N);
230 SDOperand visitSRL(SDNode *N);
231 SDOperand visitCTLZ(SDNode *N);
232 SDOperand visitCTTZ(SDNode *N);
233 SDOperand visitCTPOP(SDNode *N);
234 SDOperand visitSELECT(SDNode *N);
235 SDOperand visitSELECT_CC(SDNode *N);
236 SDOperand visitSETCC(SDNode *N);
237 SDOperand visitSIGN_EXTEND(SDNode *N);
238 SDOperand visitZERO_EXTEND(SDNode *N);
239 SDOperand visitANY_EXTEND(SDNode *N);
240 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
241 SDOperand visitTRUNCATE(SDNode *N);
242 SDOperand visitBIT_CONVERT(SDNode *N);
243 SDOperand visitFADD(SDNode *N);
244 SDOperand visitFSUB(SDNode *N);
245 SDOperand visitFMUL(SDNode *N);
246 SDOperand visitFDIV(SDNode *N);
247 SDOperand visitFREM(SDNode *N);
248 SDOperand visitFCOPYSIGN(SDNode *N);
249 SDOperand visitSINT_TO_FP(SDNode *N);
250 SDOperand visitUINT_TO_FP(SDNode *N);
251 SDOperand visitFP_TO_SINT(SDNode *N);
252 SDOperand visitFP_TO_UINT(SDNode *N);
253 SDOperand visitFP_ROUND(SDNode *N);
254 SDOperand visitFP_ROUND_INREG(SDNode *N);
255 SDOperand visitFP_EXTEND(SDNode *N);
256 SDOperand visitFNEG(SDNode *N);
257 SDOperand visitFABS(SDNode *N);
258 SDOperand visitBRCOND(SDNode *N);
259 SDOperand visitBR_CC(SDNode *N);
260 SDOperand visitLOAD(SDNode *N);
261 SDOperand visitSTORE(SDNode *N);
262 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
263 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N);
264 SDOperand visitBUILD_VECTOR(SDNode *N);
265 SDOperand visitCONCAT_VECTORS(SDNode *N);
266 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
268 SDOperand XformToShuffleWithZero(SDNode *N);
269 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
271 SDOperand visitShiftByConstant(SDNode *N, unsigned Amt);
273 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
274 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
275 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
276 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
277 SDOperand N3, ISD::CondCode CC,
278 bool NotExtCompare = false);
279 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
280 ISD::CondCode Cond, bool foldBooleans = true);
281 SDOperand SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
283 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType);
284 SDOperand BuildSDIV(SDNode *N);
285 SDOperand BuildUDIV(SDNode *N);
286 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
287 SDOperand ReduceLoadWidth(SDNode *N);
289 SDOperand GetDemandedBits(SDOperand V, uint64_t Mask);
291 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
292 /// looking for aliasing nodes and adding them to the Aliases vector.
293 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
294 SmallVector<SDOperand, 8> &Aliases);
296 /// isAlias - Return true if there is any possibility that the two addresses
298 bool isAlias(SDOperand Ptr1, int64_t Size1,
299 const Value *SrcValue1, int SrcValueOffset1,
300 SDOperand Ptr2, int64_t Size2,
301 const Value *SrcValue2, int SrcValueOffset2);
303 /// FindAliasInfo - Extracts the relevant alias information from the memory
304 /// node. Returns true if the operand was a load.
305 bool FindAliasInfo(SDNode *N,
306 SDOperand &Ptr, int64_t &Size,
307 const Value *&SrcValue, int &SrcValueOffset);
309 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
310 /// looking for a better chain (aliasing node.)
311 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
314 DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
316 TLI(D.getTargetLoweringInfo()),
317 AfterLegalize(false),
320 /// Run - runs the dag combiner on all nodes in the work list
321 void Run(bool RunningAfterLegalize);
325 //===----------------------------------------------------------------------===//
326 // TargetLowering::DAGCombinerInfo implementation
327 //===----------------------------------------------------------------------===//
329 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
330 ((DAGCombiner*)DC)->AddToWorkList(N);
333 SDOperand TargetLowering::DAGCombinerInfo::
334 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
335 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
338 SDOperand TargetLowering::DAGCombinerInfo::
339 CombineTo(SDNode *N, SDOperand Res) {
340 return ((DAGCombiner*)DC)->CombineTo(N, Res);
344 SDOperand TargetLowering::DAGCombinerInfo::
345 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
346 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
350 //===----------------------------------------------------------------------===//
352 //===----------------------------------------------------------------------===//
354 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
355 /// specified expression for the same cost as the expression itself, or 2 if we
356 /// can compute the negated form more cheaply than the expression itself.
357 static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) {
358 // No compile time optimizations on this type.
359 if (Op.getValueType() == MVT::ppcf128)
362 // fneg is removable even if it has multiple uses.
363 if (Op.getOpcode() == ISD::FNEG) return 2;
365 // Don't allow anything with multiple uses.
366 if (!Op.hasOneUse()) return 0;
368 // Don't recurse exponentially.
369 if (Depth > 6) return 0;
371 switch (Op.getOpcode()) {
372 default: return false;
373 case ISD::ConstantFP:
376 // FIXME: determine better conditions for this xform.
377 if (!UnsafeFPMath) return 0;
380 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
383 return isNegatibleForFree(Op.getOperand(1), Depth+1);
385 // We can't turn -(A-B) into B-A when we honor signed zeros.
386 if (!UnsafeFPMath) return 0;
393 if (HonorSignDependentRoundingFPMath()) return 0;
395 // -(X*Y) -> (-X * Y) or (X*-Y)
396 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
399 return isNegatibleForFree(Op.getOperand(1), Depth+1);
404 return isNegatibleForFree(Op.getOperand(0), Depth+1);
408 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
409 /// returns the newly negated expression.
410 static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG,
411 unsigned Depth = 0) {
412 // fneg is removable even if it has multiple uses.
413 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
415 // Don't allow anything with multiple uses.
416 assert(Op.hasOneUse() && "Unknown reuse!");
418 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
419 switch (Op.getOpcode()) {
420 default: assert(0 && "Unknown code");
421 case ISD::ConstantFP: {
422 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
424 return DAG.getConstantFP(V, Op.getValueType());
427 // FIXME: determine better conditions for this xform.
428 assert(UnsafeFPMath);
431 if (isNegatibleForFree(Op.getOperand(0), Depth+1))
432 return DAG.getNode(ISD::FSUB, Op.getValueType(),
433 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
436 return DAG.getNode(ISD::FSUB, Op.getValueType(),
437 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1),
440 // We can't turn -(A-B) into B-A when we honor signed zeros.
441 assert(UnsafeFPMath);
444 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
445 if (N0CFP->getValueAPF().isZero())
446 return Op.getOperand(1);
449 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1),
454 assert(!HonorSignDependentRoundingFPMath());
457 if (isNegatibleForFree(Op.getOperand(0), Depth+1))
458 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
459 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
463 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
465 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1));
469 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
470 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1));
472 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(),
473 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
479 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
480 // that selects between the values 1 and 0, making it equivalent to a setcc.
481 // Also, set the incoming LHS, RHS, and CC references to the appropriate
482 // nodes based on the type of node we are checking. This simplifies life a
483 // bit for the callers.
484 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
486 if (N.getOpcode() == ISD::SETCC) {
487 LHS = N.getOperand(0);
488 RHS = N.getOperand(1);
489 CC = N.getOperand(2);
492 if (N.getOpcode() == ISD::SELECT_CC &&
493 N.getOperand(2).getOpcode() == ISD::Constant &&
494 N.getOperand(3).getOpcode() == ISD::Constant &&
495 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
496 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
497 LHS = N.getOperand(0);
498 RHS = N.getOperand(1);
499 CC = N.getOperand(4);
505 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
506 // one use. If this is true, it allows the users to invert the operation for
507 // free when it is profitable to do so.
508 static bool isOneUseSetCC(SDOperand N) {
509 SDOperand N0, N1, N2;
510 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
515 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
516 MVT::ValueType VT = N0.getValueType();
517 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
518 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
519 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
520 if (isa<ConstantSDNode>(N1)) {
521 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
522 AddToWorkList(OpNode.Val);
523 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
524 } else if (N0.hasOneUse()) {
525 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
526 AddToWorkList(OpNode.Val);
527 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
530 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
531 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
532 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
533 if (isa<ConstantSDNode>(N0)) {
534 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
535 AddToWorkList(OpNode.Val);
536 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
537 } else if (N1.hasOneUse()) {
538 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
539 AddToWorkList(OpNode.Val);
540 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
546 //===----------------------------------------------------------------------===//
547 // Main DAG Combiner implementation
548 //===----------------------------------------------------------------------===//
550 void DAGCombiner::Run(bool RunningAfterLegalize) {
551 // set the instance variable, so that the various visit routines may use it.
552 AfterLegalize = RunningAfterLegalize;
554 // Add all the dag nodes to the worklist.
555 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
556 E = DAG.allnodes_end(); I != E; ++I)
557 WorkList.push_back(I);
559 // Create a dummy node (which is not added to allnodes), that adds a reference
560 // to the root node, preventing it from being deleted, and tracking any
561 // changes of the root.
562 HandleSDNode Dummy(DAG.getRoot());
564 // The root of the dag may dangle to deleted nodes until the dag combiner is
565 // done. Set it to null to avoid confusion.
566 DAG.setRoot(SDOperand());
568 // while the worklist isn't empty, inspect the node on the end of it and
569 // try and combine it.
570 while (!WorkList.empty()) {
571 SDNode *N = WorkList.back();
574 // If N has no uses, it is dead. Make sure to revisit all N's operands once
575 // N is deleted from the DAG, since they too may now be dead or may have a
576 // reduced number of uses, allowing other xforms.
577 if (N->use_empty() && N != &Dummy) {
578 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
579 AddToWorkList(N->getOperand(i).Val);
585 SDOperand RV = combine(N);
592 // If we get back the same node we passed in, rather than a new node or
593 // zero, we know that the node must have defined multiple values and
594 // CombineTo was used. Since CombineTo takes care of the worklist
595 // mechanics for us, we have no work to do in this case.
599 assert(N->getOpcode() != ISD::DELETED_NODE &&
600 RV.Val->getOpcode() != ISD::DELETED_NODE &&
601 "Node was deleted but visit returned new node!");
603 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
604 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
606 std::vector<SDNode*> NowDead;
607 if (N->getNumValues() == RV.Val->getNumValues())
608 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
610 assert(N->getValueType(0) == RV.getValueType() &&
611 N->getNumValues() == 1 && "Type mismatch");
613 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
616 // Push the new node and any users onto the worklist
617 AddToWorkList(RV.Val);
618 AddUsersToWorkList(RV.Val);
620 // Add any uses of the old node to the worklist in case this node is the
621 // last one that uses them. They may become dead after this node is
623 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
624 AddToWorkList(N->getOperand(i).Val);
626 // Nodes can be reintroduced into the worklist. Make sure we do not
627 // process a node that has been replaced.
628 removeFromWorkList(N);
629 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
630 removeFromWorkList(NowDead[i]);
632 // Finally, since the node is now dead, remove it from the graph.
636 // If the root changed (e.g. it was a dead load, update the root).
637 DAG.setRoot(Dummy.getValue());
640 SDOperand DAGCombiner::visit(SDNode *N) {
641 switch(N->getOpcode()) {
643 case ISD::TokenFactor: return visitTokenFactor(N);
644 case ISD::ADD: return visitADD(N);
645 case ISD::SUB: return visitSUB(N);
646 case ISD::ADDC: return visitADDC(N);
647 case ISD::ADDE: return visitADDE(N);
648 case ISD::MUL: return visitMUL(N);
649 case ISD::SDIV: return visitSDIV(N);
650 case ISD::UDIV: return visitUDIV(N);
651 case ISD::SREM: return visitSREM(N);
652 case ISD::UREM: return visitUREM(N);
653 case ISD::MULHU: return visitMULHU(N);
654 case ISD::MULHS: return visitMULHS(N);
655 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
656 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
657 case ISD::SDIVREM: return visitSDIVREM(N);
658 case ISD::UDIVREM: return visitUDIVREM(N);
659 case ISD::AND: return visitAND(N);
660 case ISD::OR: return visitOR(N);
661 case ISD::XOR: return visitXOR(N);
662 case ISD::SHL: return visitSHL(N);
663 case ISD::SRA: return visitSRA(N);
664 case ISD::SRL: return visitSRL(N);
665 case ISD::CTLZ: return visitCTLZ(N);
666 case ISD::CTTZ: return visitCTTZ(N);
667 case ISD::CTPOP: return visitCTPOP(N);
668 case ISD::SELECT: return visitSELECT(N);
669 case ISD::SELECT_CC: return visitSELECT_CC(N);
670 case ISD::SETCC: return visitSETCC(N);
671 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
672 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
673 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
674 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
675 case ISD::TRUNCATE: return visitTRUNCATE(N);
676 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
677 case ISD::FADD: return visitFADD(N);
678 case ISD::FSUB: return visitFSUB(N);
679 case ISD::FMUL: return visitFMUL(N);
680 case ISD::FDIV: return visitFDIV(N);
681 case ISD::FREM: return visitFREM(N);
682 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
683 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
684 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
685 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
686 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
687 case ISD::FP_ROUND: return visitFP_ROUND(N);
688 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
689 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
690 case ISD::FNEG: return visitFNEG(N);
691 case ISD::FABS: return visitFABS(N);
692 case ISD::BRCOND: return visitBRCOND(N);
693 case ISD::BR_CC: return visitBR_CC(N);
694 case ISD::LOAD: return visitLOAD(N);
695 case ISD::STORE: return visitSTORE(N);
696 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
697 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
698 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
699 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
700 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
705 SDOperand DAGCombiner::combine(SDNode *N) {
707 SDOperand RV = visit(N);
709 // If nothing happened, try a target-specific DAG combine.
711 assert(N->getOpcode() != ISD::DELETED_NODE &&
712 "Node was deleted but visit returned NULL!");
714 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
715 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
717 // Expose the DAG combiner to the target combiner impls.
718 TargetLowering::DAGCombinerInfo
719 DagCombineInfo(DAG, !AfterLegalize, false, this);
721 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
728 /// getInputChainForNode - Given a node, return its input chain if it has one,
729 /// otherwise return a null sd operand.
730 static SDOperand getInputChainForNode(SDNode *N) {
731 if (unsigned NumOps = N->getNumOperands()) {
732 if (N->getOperand(0).getValueType() == MVT::Other)
733 return N->getOperand(0);
734 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
735 return N->getOperand(NumOps-1);
736 for (unsigned i = 1; i < NumOps-1; ++i)
737 if (N->getOperand(i).getValueType() == MVT::Other)
738 return N->getOperand(i);
740 return SDOperand(0, 0);
743 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
744 // If N has two operands, where one has an input chain equal to the other,
745 // the 'other' chain is redundant.
746 if (N->getNumOperands() == 2) {
747 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
748 return N->getOperand(0);
749 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
750 return N->getOperand(1);
753 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
754 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
755 SmallPtrSet<SDNode*, 16> SeenOps;
756 bool Changed = false; // If we should replace this token factor.
758 // Start out with this token factor.
761 // Iterate through token factors. The TFs grows when new token factors are
763 for (unsigned i = 0; i < TFs.size(); ++i) {
766 // Check each of the operands.
767 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
768 SDOperand Op = TF->getOperand(i);
770 switch (Op.getOpcode()) {
771 case ISD::EntryToken:
772 // Entry tokens don't need to be added to the list. They are
777 case ISD::TokenFactor:
778 if ((CombinerAA || Op.hasOneUse()) &&
779 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
780 // Queue up for processing.
781 TFs.push_back(Op.Val);
782 // Clean up in case the token factor is removed.
783 AddToWorkList(Op.Val);
790 // Only add if it isn't already in the list.
791 if (SeenOps.insert(Op.Val))
802 // If we've change things around then replace token factor.
804 if (Ops.size() == 0) {
805 // The entry token is the only possible outcome.
806 Result = DAG.getEntryNode();
808 // New and improved token factor.
809 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
812 // Don't add users to work list.
813 return CombineTo(N, Result, false);
820 SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
821 MVT::ValueType VT = N0.getValueType();
822 SDOperand N00 = N0.getOperand(0);
823 SDOperand N01 = N0.getOperand(1);
824 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
825 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
826 isa<ConstantSDNode>(N00.getOperand(1))) {
827 N0 = DAG.getNode(ISD::ADD, VT,
828 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01),
829 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01));
830 return DAG.getNode(ISD::ADD, VT, N0, N1);
836 SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp,
838 MVT::ValueType VT = N->getValueType(0);
839 unsigned Opc = N->getOpcode();
840 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
841 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
842 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
843 ISD::CondCode CC = ISD::SETCC_INVALID;
845 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
847 SDOperand CCOp = Slct.getOperand(0);
848 if (CCOp.getOpcode() == ISD::SETCC)
849 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
852 bool DoXform = false;
854 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
856 if (LHS.getOpcode() == ISD::Constant &&
857 cast<ConstantSDNode>(LHS)->isNullValue())
859 else if (CC != ISD::SETCC_INVALID &&
860 RHS.getOpcode() == ISD::Constant &&
861 cast<ConstantSDNode>(RHS)->isNullValue()) {
863 SDOperand Op0 = Slct.getOperand(0);
864 bool isInt = MVT::isInteger(isSlctCC ? Op0.getValueType()
865 : Op0.getOperand(0).getValueType());
866 CC = ISD::getSetCCInverse(CC, isInt);
872 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS);
874 return DAG.getSelectCC(OtherOp, Result,
875 Slct.getOperand(0), Slct.getOperand(1), CC);
876 SDOperand CCOp = Slct.getOperand(0);
878 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0),
879 CCOp.getOperand(1), CC);
880 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result);
885 SDOperand DAGCombiner::visitADD(SDNode *N) {
886 SDOperand N0 = N->getOperand(0);
887 SDOperand N1 = N->getOperand(1);
888 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
889 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
890 MVT::ValueType VT = N0.getValueType();
893 if (MVT::isVector(VT)) {
894 SDOperand FoldedVOp = SimplifyVBinOp(N);
895 if (FoldedVOp.Val) return FoldedVOp;
898 // fold (add x, undef) -> undef
899 if (N0.getOpcode() == ISD::UNDEF)
901 if (N1.getOpcode() == ISD::UNDEF)
903 // fold (add c1, c2) -> c1+c2
905 return DAG.getNode(ISD::ADD, VT, N0, N1);
906 // canonicalize constant to RHS
908 return DAG.getNode(ISD::ADD, VT, N1, N0);
909 // fold (add x, 0) -> x
910 if (N1C && N1C->isNullValue())
912 // fold ((c1-A)+c2) -> (c1+c2)-A
913 if (N1C && N0.getOpcode() == ISD::SUB)
914 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
915 return DAG.getNode(ISD::SUB, VT,
916 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
919 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
922 // fold ((0-A) + B) -> B-A
923 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
924 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
925 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
926 // fold (A + (0-B)) -> A-B
927 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
928 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
929 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
930 // fold (A+(B-A)) -> B
931 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
932 return N1.getOperand(0);
934 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
935 return SDOperand(N, 0);
937 // fold (a+b) -> (a|b) iff a and b share no bits.
938 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
939 uint64_t LHSZero, LHSOne;
940 uint64_t RHSZero, RHSOne;
941 uint64_t Mask = MVT::getIntVTBitMask(VT);
942 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
944 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
946 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
947 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
948 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
949 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
950 return DAG.getNode(ISD::OR, VT, N0, N1);
954 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
955 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) {
956 SDOperand Result = combineShlAddConstant(N0, N1, DAG);
957 if (Result.Val) return Result;
959 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) {
960 SDOperand Result = combineShlAddConstant(N1, N0, DAG);
961 if (Result.Val) return Result;
964 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
965 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) {
966 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG);
967 if (Result.Val) return Result;
969 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
970 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
971 if (Result.Val) return Result;
977 SDOperand DAGCombiner::visitADDC(SDNode *N) {
978 SDOperand N0 = N->getOperand(0);
979 SDOperand N1 = N->getOperand(1);
980 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
981 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
982 MVT::ValueType VT = N0.getValueType();
984 // If the flag result is dead, turn this into an ADD.
985 if (N->hasNUsesOfValue(0, 1))
986 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0),
987 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
989 // canonicalize constant to RHS.
991 SDOperand Ops[] = { N1, N0 };
992 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
995 // fold (addc x, 0) -> x + no carry out
996 if (N1C && N1C->isNullValue())
997 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
999 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1000 uint64_t LHSZero, LHSOne;
1001 uint64_t RHSZero, RHSOne;
1002 uint64_t Mask = MVT::getIntVTBitMask(VT);
1003 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1005 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1007 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1008 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1009 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1010 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1011 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1),
1012 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
1018 SDOperand DAGCombiner::visitADDE(SDNode *N) {
1019 SDOperand N0 = N->getOperand(0);
1020 SDOperand N1 = N->getOperand(1);
1021 SDOperand CarryIn = N->getOperand(2);
1022 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1023 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1024 //MVT::ValueType VT = N0.getValueType();
1026 // canonicalize constant to RHS
1028 SDOperand Ops[] = { N1, N0, CarryIn };
1029 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3);
1032 // fold (adde x, y, false) -> (addc x, y)
1033 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) {
1034 SDOperand Ops[] = { N1, N0 };
1035 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
1043 SDOperand DAGCombiner::visitSUB(SDNode *N) {
1044 SDOperand N0 = N->getOperand(0);
1045 SDOperand N1 = N->getOperand(1);
1046 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1047 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1048 MVT::ValueType VT = N0.getValueType();
1051 if (MVT::isVector(VT)) {
1052 SDOperand FoldedVOp = SimplifyVBinOp(N);
1053 if (FoldedVOp.Val) return FoldedVOp;
1056 // fold (sub x, x) -> 0
1058 return DAG.getConstant(0, N->getValueType(0));
1059 // fold (sub c1, c2) -> c1-c2
1061 return DAG.getNode(ISD::SUB, VT, N0, N1);
1062 // fold (sub x, c) -> (add x, -c)
1064 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
1065 // fold (A+B)-A -> B
1066 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1067 return N0.getOperand(1);
1068 // fold (A+B)-B -> A
1069 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1070 return N0.getOperand(0);
1071 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1072 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
1073 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
1074 if (Result.Val) return Result;
1076 // If either operand of a sub is undef, the result is undef
1077 if (N0.getOpcode() == ISD::UNDEF)
1079 if (N1.getOpcode() == ISD::UNDEF)
1085 SDOperand DAGCombiner::visitMUL(SDNode *N) {
1086 SDOperand N0 = N->getOperand(0);
1087 SDOperand N1 = N->getOperand(1);
1088 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1089 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1090 MVT::ValueType VT = N0.getValueType();
1093 if (MVT::isVector(VT)) {
1094 SDOperand FoldedVOp = SimplifyVBinOp(N);
1095 if (FoldedVOp.Val) return FoldedVOp;
1098 // fold (mul x, undef) -> 0
1099 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1100 return DAG.getConstant(0, VT);
1101 // fold (mul c1, c2) -> c1*c2
1103 return DAG.getNode(ISD::MUL, VT, N0, N1);
1104 // canonicalize constant to RHS
1106 return DAG.getNode(ISD::MUL, VT, N1, N0);
1107 // fold (mul x, 0) -> 0
1108 if (N1C && N1C->isNullValue())
1110 // fold (mul x, -1) -> 0-x
1111 if (N1C && N1C->isAllOnesValue())
1112 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1113 // fold (mul x, (1 << c)) -> x << c
1114 if (N1C && isPowerOf2_64(N1C->getValue()))
1115 return DAG.getNode(ISD::SHL, VT, N0,
1116 DAG.getConstant(Log2_64(N1C->getValue()),
1117 TLI.getShiftAmountTy()));
1118 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1119 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
1120 // FIXME: If the input is something that is easily negated (e.g. a
1121 // single-use add), we should put the negate there.
1122 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
1123 DAG.getNode(ISD::SHL, VT, N0,
1124 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
1125 TLI.getShiftAmountTy())));
1128 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1129 if (N1C && N0.getOpcode() == ISD::SHL &&
1130 isa<ConstantSDNode>(N0.getOperand(1))) {
1131 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
1132 AddToWorkList(C3.Val);
1133 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
1136 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1139 SDOperand Sh(0,0), Y(0,0);
1140 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1141 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1142 N0.Val->hasOneUse()) {
1144 } else if (N1.getOpcode() == ISD::SHL &&
1145 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
1149 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
1150 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
1153 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1154 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1155 isa<ConstantSDNode>(N0.getOperand(1))) {
1156 return DAG.getNode(ISD::ADD, VT,
1157 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
1158 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
1162 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
1169 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
1170 SDOperand N0 = N->getOperand(0);
1171 SDOperand N1 = N->getOperand(1);
1172 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1173 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1174 MVT::ValueType VT = N->getValueType(0);
1177 if (MVT::isVector(VT)) {
1178 SDOperand FoldedVOp = SimplifyVBinOp(N);
1179 if (FoldedVOp.Val) return FoldedVOp;
1182 // fold (sdiv c1, c2) -> c1/c2
1183 if (N0C && N1C && !N1C->isNullValue())
1184 return DAG.getNode(ISD::SDIV, VT, N0, N1);
1185 // fold (sdiv X, 1) -> X
1186 if (N1C && N1C->getSignExtended() == 1LL)
1188 // fold (sdiv X, -1) -> 0-X
1189 if (N1C && N1C->isAllOnesValue())
1190 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1191 // If we know the sign bits of both operands are zero, strength reduce to a
1192 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1193 uint64_t SignBit = MVT::getIntVTSignBit(VT);
1194 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1195 DAG.MaskedValueIsZero(N0, SignBit))
1196 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
1197 // fold (sdiv X, pow2) -> simple ops after legalize
1198 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
1199 (isPowerOf2_64(N1C->getSignExtended()) ||
1200 isPowerOf2_64(-N1C->getSignExtended()))) {
1201 // If dividing by powers of two is cheap, then don't perform the following
1203 if (TLI.isPow2DivCheap())
1205 int64_t pow2 = N1C->getSignExtended();
1206 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1207 unsigned lg2 = Log2_64(abs2);
1208 // Splat the sign bit into the register
1209 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
1210 DAG.getConstant(MVT::getSizeInBits(VT)-1,
1211 TLI.getShiftAmountTy()));
1212 AddToWorkList(SGN.Val);
1213 // Add (N0 < 0) ? abs2 - 1 : 0;
1214 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
1215 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
1216 TLI.getShiftAmountTy()));
1217 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
1218 AddToWorkList(SRL.Val);
1219 AddToWorkList(ADD.Val); // Divide by pow2
1220 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
1221 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
1222 // If we're dividing by a positive value, we're done. Otherwise, we must
1223 // negate the result.
1226 AddToWorkList(SRA.Val);
1227 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
1229 // if integer divide is expensive and we satisfy the requirements, emit an
1230 // alternate sequence.
1231 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
1232 !TLI.isIntDivCheap()) {
1233 SDOperand Op = BuildSDIV(N);
1234 if (Op.Val) return Op;
1238 if (N0.getOpcode() == ISD::UNDEF)
1239 return DAG.getConstant(0, VT);
1240 // X / undef -> undef
1241 if (N1.getOpcode() == ISD::UNDEF)
1247 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
1248 SDOperand N0 = N->getOperand(0);
1249 SDOperand N1 = N->getOperand(1);
1250 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1251 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1252 MVT::ValueType VT = N->getValueType(0);
1255 if (MVT::isVector(VT)) {
1256 SDOperand FoldedVOp = SimplifyVBinOp(N);
1257 if (FoldedVOp.Val) return FoldedVOp;
1260 // fold (udiv c1, c2) -> c1/c2
1261 if (N0C && N1C && !N1C->isNullValue())
1262 return DAG.getNode(ISD::UDIV, VT, N0, N1);
1263 // fold (udiv x, (1 << c)) -> x >>u c
1264 if (N1C && isPowerOf2_64(N1C->getValue()))
1265 return DAG.getNode(ISD::SRL, VT, N0,
1266 DAG.getConstant(Log2_64(N1C->getValue()),
1267 TLI.getShiftAmountTy()));
1268 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1269 if (N1.getOpcode() == ISD::SHL) {
1270 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1271 if (isPowerOf2_64(SHC->getValue())) {
1272 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
1273 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
1274 DAG.getConstant(Log2_64(SHC->getValue()),
1276 AddToWorkList(Add.Val);
1277 return DAG.getNode(ISD::SRL, VT, N0, Add);
1281 // fold (udiv x, c) -> alternate
1282 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
1283 SDOperand Op = BuildUDIV(N);
1284 if (Op.Val) return Op;
1288 if (N0.getOpcode() == ISD::UNDEF)
1289 return DAG.getConstant(0, VT);
1290 // X / undef -> undef
1291 if (N1.getOpcode() == ISD::UNDEF)
1297 SDOperand DAGCombiner::visitSREM(SDNode *N) {
1298 SDOperand N0 = N->getOperand(0);
1299 SDOperand N1 = N->getOperand(1);
1300 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1301 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1302 MVT::ValueType VT = N->getValueType(0);
1304 // fold (srem c1, c2) -> c1%c2
1305 if (N0C && N1C && !N1C->isNullValue())
1306 return DAG.getNode(ISD::SREM, VT, N0, N1);
1307 // If we know the sign bits of both operands are zero, strength reduce to a
1308 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1309 if (!MVT::isVector(VT)) {
1310 uint64_t SignBit = MVT::getIntVTSignBit(VT);
1311 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1312 DAG.MaskedValueIsZero(N0, SignBit))
1313 return DAG.getNode(ISD::UREM, VT, N0, N1);
1316 // If X/C can be simplified by the division-by-constant logic, lower
1317 // X%C to the equivalent of X-X/C*C.
1318 if (N1C && !N1C->isNullValue()) {
1319 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
1320 AddToWorkList(Div.Val);
1321 SDOperand OptimizedDiv = combine(Div.Val);
1322 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) {
1323 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
1324 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1325 AddToWorkList(Mul.Val);
1331 if (N0.getOpcode() == ISD::UNDEF)
1332 return DAG.getConstant(0, VT);
1333 // X % undef -> undef
1334 if (N1.getOpcode() == ISD::UNDEF)
1340 SDOperand DAGCombiner::visitUREM(SDNode *N) {
1341 SDOperand N0 = N->getOperand(0);
1342 SDOperand N1 = N->getOperand(1);
1343 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1344 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1345 MVT::ValueType VT = N->getValueType(0);
1347 // fold (urem c1, c2) -> c1%c2
1348 if (N0C && N1C && !N1C->isNullValue())
1349 return DAG.getNode(ISD::UREM, VT, N0, N1);
1350 // fold (urem x, pow2) -> (and x, pow2-1)
1351 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
1352 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
1353 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1354 if (N1.getOpcode() == ISD::SHL) {
1355 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1356 if (isPowerOf2_64(SHC->getValue())) {
1357 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
1358 AddToWorkList(Add.Val);
1359 return DAG.getNode(ISD::AND, VT, N0, Add);
1364 // If X/C can be simplified by the division-by-constant logic, lower
1365 // X%C to the equivalent of X-X/C*C.
1366 if (N1C && !N1C->isNullValue()) {
1367 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
1368 SDOperand OptimizedDiv = combine(Div.Val);
1369 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) {
1370 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
1371 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1372 AddToWorkList(Mul.Val);
1378 if (N0.getOpcode() == ISD::UNDEF)
1379 return DAG.getConstant(0, VT);
1380 // X % undef -> undef
1381 if (N1.getOpcode() == ISD::UNDEF)
1387 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
1388 SDOperand N0 = N->getOperand(0);
1389 SDOperand N1 = N->getOperand(1);
1390 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1391 MVT::ValueType VT = N->getValueType(0);
1393 // fold (mulhs x, 0) -> 0
1394 if (N1C && N1C->isNullValue())
1396 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1397 if (N1C && N1C->getValue() == 1)
1398 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
1399 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
1400 TLI.getShiftAmountTy()));
1401 // fold (mulhs x, undef) -> 0
1402 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1403 return DAG.getConstant(0, VT);
1408 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
1409 SDOperand N0 = N->getOperand(0);
1410 SDOperand N1 = N->getOperand(1);
1411 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1412 MVT::ValueType VT = N->getValueType(0);
1414 // fold (mulhu x, 0) -> 0
1415 if (N1C && N1C->isNullValue())
1417 // fold (mulhu x, 1) -> 0
1418 if (N1C && N1C->getValue() == 1)
1419 return DAG.getConstant(0, N0.getValueType());
1420 // fold (mulhu x, undef) -> 0
1421 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1422 return DAG.getConstant(0, VT);
1427 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1428 /// compute two values. LoOp and HiOp give the opcodes for the two computations
1429 /// that are being performed. Return true if a simplification was made.
1431 SDOperand DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
1433 // If the high half is not needed, just compute the low half.
1434 bool HiExists = N->hasAnyUseOfValue(1);
1437 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1438 SDOperand Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(),
1439 N->getNumOperands());
1440 return CombineTo(N, Res, Res);
1443 // If the low half is not needed, just compute the high half.
1444 bool LoExists = N->hasAnyUseOfValue(0);
1447 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
1448 SDOperand Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(),
1449 N->getNumOperands());
1450 return CombineTo(N, Res, Res);
1453 // If both halves are used, return as it is.
1454 if (LoExists && HiExists)
1457 // If the two computed results can be simplified separately, separate them.
1459 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0),
1460 N->op_begin(), N->getNumOperands());
1461 AddToWorkList(Lo.Val);
1462 SDOperand LoOpt = combine(Lo.Val);
1463 if (LoOpt.Val && LoOpt.Val != Lo.Val &&
1464 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))
1465 return CombineTo(N, LoOpt, LoOpt);
1469 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1),
1470 N->op_begin(), N->getNumOperands());
1471 AddToWorkList(Hi.Val);
1472 SDOperand HiOpt = combine(Hi.Val);
1473 if (HiOpt.Val && HiOpt != Hi &&
1474 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))
1475 return CombineTo(N, HiOpt, HiOpt);
1480 SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) {
1481 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
1482 if (Res.Val) return Res;
1487 SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) {
1488 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
1489 if (Res.Val) return Res;
1494 SDOperand DAGCombiner::visitSDIVREM(SDNode *N) {
1495 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
1496 if (Res.Val) return Res;
1501 SDOperand DAGCombiner::visitUDIVREM(SDNode *N) {
1502 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
1503 if (Res.Val) return Res;
1508 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1509 /// two operands of the same opcode, try to simplify it.
1510 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1511 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
1512 MVT::ValueType VT = N0.getValueType();
1513 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1515 // For each of OP in AND/OR/XOR:
1516 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1517 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1518 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1519 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1520 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1521 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1522 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1523 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1524 N0.getOperand(0).getValueType(),
1525 N0.getOperand(0), N1.getOperand(0));
1526 AddToWorkList(ORNode.Val);
1527 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1530 // For each of OP in SHL/SRL/SRA/AND...
1531 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1532 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1533 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1534 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1535 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1536 N0.getOperand(1) == N1.getOperand(1)) {
1537 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1538 N0.getOperand(0).getValueType(),
1539 N0.getOperand(0), N1.getOperand(0));
1540 AddToWorkList(ORNode.Val);
1541 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1547 SDOperand DAGCombiner::visitAND(SDNode *N) {
1548 SDOperand N0 = N->getOperand(0);
1549 SDOperand N1 = N->getOperand(1);
1550 SDOperand LL, LR, RL, RR, CC0, CC1;
1551 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1552 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1553 MVT::ValueType VT = N1.getValueType();
1556 if (MVT::isVector(VT)) {
1557 SDOperand FoldedVOp = SimplifyVBinOp(N);
1558 if (FoldedVOp.Val) return FoldedVOp;
1561 // fold (and x, undef) -> 0
1562 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1563 return DAG.getConstant(0, VT);
1564 // fold (and c1, c2) -> c1&c2
1566 return DAG.getNode(ISD::AND, VT, N0, N1);
1567 // canonicalize constant to RHS
1569 return DAG.getNode(ISD::AND, VT, N1, N0);
1570 // fold (and x, -1) -> x
1571 if (N1C && N1C->isAllOnesValue())
1573 // if (and x, c) is known to be zero, return 0
1574 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1575 return DAG.getConstant(0, VT);
1577 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1580 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1581 if (N1C && N0.getOpcode() == ISD::OR)
1582 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1583 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1585 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1586 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1587 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1588 if (DAG.MaskedValueIsZero(N0.getOperand(0),
1589 ~N1C->getValue() & InMask)) {
1590 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1593 // Replace uses of the AND with uses of the Zero extend node.
1596 // We actually want to replace all uses of the any_extend with the
1597 // zero_extend, to avoid duplicating things. This will later cause this
1598 // AND to be folded.
1599 CombineTo(N0.Val, Zext);
1600 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1603 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1604 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1605 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1606 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1608 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1609 MVT::isInteger(LL.getValueType())) {
1610 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1611 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1612 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1613 AddToWorkList(ORNode.Val);
1614 return DAG.getSetCC(VT, ORNode, LR, Op1);
1616 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1617 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1618 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1619 AddToWorkList(ANDNode.Val);
1620 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1622 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1623 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1624 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1625 AddToWorkList(ORNode.Val);
1626 return DAG.getSetCC(VT, ORNode, LR, Op1);
1629 // canonicalize equivalent to ll == rl
1630 if (LL == RR && LR == RL) {
1631 Op1 = ISD::getSetCCSwappedOperands(Op1);
1634 if (LL == RL && LR == RR) {
1635 bool isInteger = MVT::isInteger(LL.getValueType());
1636 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1637 if (Result != ISD::SETCC_INVALID)
1638 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1642 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1643 if (N0.getOpcode() == N1.getOpcode()) {
1644 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1645 if (Tmp.Val) return Tmp;
1648 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1649 // fold (and (sra)) -> (and (srl)) when possible.
1650 if (!MVT::isVector(VT) &&
1651 SimplifyDemandedBits(SDOperand(N, 0)))
1652 return SDOperand(N, 0);
1653 // fold (zext_inreg (extload x)) -> (zextload x)
1654 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
1655 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1656 MVT::ValueType EVT = LN0->getLoadedVT();
1657 // If we zero all the possible extended bits, then we can turn this into
1658 // a zextload if we are running before legalize or the operation is legal.
1659 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1660 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1661 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1662 LN0->getBasePtr(), LN0->getSrcValue(),
1663 LN0->getSrcValueOffset(), EVT,
1665 LN0->getAlignment());
1667 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1668 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1671 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1672 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
1674 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1675 MVT::ValueType EVT = LN0->getLoadedVT();
1676 // If we zero all the possible extended bits, then we can turn this into
1677 // a zextload if we are running before legalize or the operation is legal.
1678 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1679 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1680 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1681 LN0->getBasePtr(), LN0->getSrcValue(),
1682 LN0->getSrcValueOffset(), EVT,
1684 LN0->getAlignment());
1686 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1687 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1691 // fold (and (load x), 255) -> (zextload x, i8)
1692 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1693 if (N1C && N0.getOpcode() == ISD::LOAD) {
1694 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1695 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1696 LN0->isUnindexed() && N0.hasOneUse()) {
1697 MVT::ValueType EVT, LoadedVT;
1698 if (N1C->getValue() == 255)
1700 else if (N1C->getValue() == 65535)
1702 else if (N1C->getValue() == ~0U)
1707 LoadedVT = LN0->getLoadedVT();
1708 if (EVT != MVT::Other && LoadedVT > EVT &&
1709 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1710 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1711 // For big endian targets, we need to add an offset to the pointer to
1712 // load the correct bytes. For little endian systems, we merely need to
1713 // read fewer bytes from the same pointer.
1714 unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8;
1715 unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8;
1716 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
1717 unsigned Alignment = LN0->getAlignment();
1718 SDOperand NewPtr = LN0->getBasePtr();
1719 if (!TLI.isLittleEndian()) {
1720 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1721 DAG.getConstant(PtrOff, PtrType));
1722 Alignment = MinAlign(Alignment, PtrOff);
1724 AddToWorkList(NewPtr.Val);
1726 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1727 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
1728 LN0->isVolatile(), Alignment);
1730 CombineTo(N0.Val, Load, Load.getValue(1));
1731 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1739 SDOperand DAGCombiner::visitOR(SDNode *N) {
1740 SDOperand N0 = N->getOperand(0);
1741 SDOperand N1 = N->getOperand(1);
1742 SDOperand LL, LR, RL, RR, CC0, CC1;
1743 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1744 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1745 MVT::ValueType VT = N1.getValueType();
1746 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1749 if (MVT::isVector(VT)) {
1750 SDOperand FoldedVOp = SimplifyVBinOp(N);
1751 if (FoldedVOp.Val) return FoldedVOp;
1754 // fold (or x, undef) -> -1
1755 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1756 return DAG.getConstant(~0ULL, VT);
1757 // fold (or c1, c2) -> c1|c2
1759 return DAG.getNode(ISD::OR, VT, N0, N1);
1760 // canonicalize constant to RHS
1762 return DAG.getNode(ISD::OR, VT, N1, N0);
1763 // fold (or x, 0) -> x
1764 if (N1C && N1C->isNullValue())
1766 // fold (or x, -1) -> -1
1767 if (N1C && N1C->isAllOnesValue())
1769 // fold (or x, c) -> c iff (x & ~c) == 0
1771 DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1774 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1777 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1778 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1779 isa<ConstantSDNode>(N0.getOperand(1))) {
1780 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1781 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1783 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1785 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1786 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1787 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1788 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1790 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1791 MVT::isInteger(LL.getValueType())) {
1792 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1793 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1794 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1795 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1796 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1797 AddToWorkList(ORNode.Val);
1798 return DAG.getSetCC(VT, ORNode, LR, Op1);
1800 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1801 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1802 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1803 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1804 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1805 AddToWorkList(ANDNode.Val);
1806 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1809 // canonicalize equivalent to ll == rl
1810 if (LL == RR && LR == RL) {
1811 Op1 = ISD::getSetCCSwappedOperands(Op1);
1814 if (LL == RL && LR == RR) {
1815 bool isInteger = MVT::isInteger(LL.getValueType());
1816 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1817 if (Result != ISD::SETCC_INVALID)
1818 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1822 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1823 if (N0.getOpcode() == N1.getOpcode()) {
1824 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1825 if (Tmp.Val) return Tmp;
1828 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1829 if (N0.getOpcode() == ISD::AND &&
1830 N1.getOpcode() == ISD::AND &&
1831 N0.getOperand(1).getOpcode() == ISD::Constant &&
1832 N1.getOperand(1).getOpcode() == ISD::Constant &&
1833 // Don't increase # computations.
1834 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1835 // We can only do this xform if we know that bits from X that are set in C2
1836 // but not in C1 are already zero. Likewise for Y.
1837 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1838 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1840 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1841 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1842 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1843 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1848 // See if this is some rotate idiom.
1849 if (SDNode *Rot = MatchRotate(N0, N1))
1850 return SDOperand(Rot, 0);
1856 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1857 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1858 if (Op.getOpcode() == ISD::AND) {
1859 if (isa<ConstantSDNode>(Op.getOperand(1))) {
1860 Mask = Op.getOperand(1);
1861 Op = Op.getOperand(0);
1867 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1875 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1876 // idioms for rotate, and if the target supports rotation instructions, generate
1878 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1879 // Must be a legal type. Expanded an promoted things won't work with rotates.
1880 MVT::ValueType VT = LHS.getValueType();
1881 if (!TLI.isTypeLegal(VT)) return 0;
1883 // The target must have at least one rotate flavor.
1884 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1885 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1886 if (!HasROTL && !HasROTR) return 0;
1888 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1889 SDOperand LHSShift; // The shift.
1890 SDOperand LHSMask; // AND value if any.
1891 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1892 return 0; // Not part of a rotate.
1894 SDOperand RHSShift; // The shift.
1895 SDOperand RHSMask; // AND value if any.
1896 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1897 return 0; // Not part of a rotate.
1899 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1900 return 0; // Not shifting the same value.
1902 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1903 return 0; // Shifts must disagree.
1905 // Canonicalize shl to left side in a shl/srl pair.
1906 if (RHSShift.getOpcode() == ISD::SHL) {
1907 std::swap(LHS, RHS);
1908 std::swap(LHSShift, RHSShift);
1909 std::swap(LHSMask , RHSMask );
1912 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1913 SDOperand LHSShiftArg = LHSShift.getOperand(0);
1914 SDOperand LHSShiftAmt = LHSShift.getOperand(1);
1915 SDOperand RHSShiftAmt = RHSShift.getOperand(1);
1917 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1918 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1919 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
1920 RHSShiftAmt.getOpcode() == ISD::Constant) {
1921 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue();
1922 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue();
1923 if ((LShVal + RShVal) != OpSizeInBits)
1928 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt);
1930 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
1932 // If there is an AND of either shifted operand, apply it to the result.
1933 if (LHSMask.Val || RHSMask.Val) {
1934 uint64_t Mask = MVT::getIntVTBitMask(VT);
1937 uint64_t RHSBits = (1ULL << LShVal)-1;
1938 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1941 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1942 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1945 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1951 // If there is a mask here, and we have a variable shift, we can't be sure
1952 // that we're masking out the right stuff.
1953 if (LHSMask.Val || RHSMask.Val)
1956 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1957 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1958 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
1959 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
1960 if (ConstantSDNode *SUBC =
1961 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
1962 if (SUBC->getValue() == OpSizeInBits)
1964 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1966 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1970 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1971 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1972 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
1973 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
1974 if (ConstantSDNode *SUBC =
1975 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
1976 if (SUBC->getValue() == OpSizeInBits)
1978 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1980 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1984 // Look for sign/zext/any-extended cases:
1985 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1986 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1987 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) &&
1988 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1989 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1990 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) {
1991 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0);
1992 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0);
1993 if (RExtOp0.getOpcode() == ISD::SUB &&
1994 RExtOp0.getOperand(1) == LExtOp0) {
1995 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1997 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1998 // (rotl x, (sub 32, y))
1999 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
2000 if (SUBC->getValue() == OpSizeInBits) {
2002 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
2004 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
2007 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2008 RExtOp0 == LExtOp0.getOperand(1)) {
2009 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
2011 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
2012 // (rotr x, (sub 32, y))
2013 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2014 if (SUBC->getValue() == OpSizeInBits) {
2016 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val;
2018 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
2028 SDOperand DAGCombiner::visitXOR(SDNode *N) {
2029 SDOperand N0 = N->getOperand(0);
2030 SDOperand N1 = N->getOperand(1);
2031 SDOperand LHS, RHS, CC;
2032 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2033 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2034 MVT::ValueType VT = N0.getValueType();
2037 if (MVT::isVector(VT)) {
2038 SDOperand FoldedVOp = SimplifyVBinOp(N);
2039 if (FoldedVOp.Val) return FoldedVOp;
2042 // fold (xor x, undef) -> undef
2043 if (N0.getOpcode() == ISD::UNDEF)
2045 if (N1.getOpcode() == ISD::UNDEF)
2047 // fold (xor c1, c2) -> c1^c2
2049 return DAG.getNode(ISD::XOR, VT, N0, N1);
2050 // canonicalize constant to RHS
2052 return DAG.getNode(ISD::XOR, VT, N1, N0);
2053 // fold (xor x, 0) -> x
2054 if (N1C && N1C->isNullValue())
2057 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
2060 // fold !(x cc y) -> (x !cc y)
2061 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2062 bool isInt = MVT::isInteger(LHS.getValueType());
2063 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2065 if (N0.getOpcode() == ISD::SETCC)
2066 return DAG.getSetCC(VT, LHS, RHS, NotCC);
2067 if (N0.getOpcode() == ISD::SELECT_CC)
2068 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
2069 assert(0 && "Unhandled SetCC Equivalent!");
2072 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2073 if (N1C && N1C->getValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2074 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2075 SDOperand V = N0.getOperand(0);
2076 V = DAG.getNode(ISD::XOR, V.getValueType(), V,
2077 DAG.getConstant(1, V.getValueType()));
2078 AddToWorkList(V.Val);
2079 return DAG.getNode(ISD::ZERO_EXTEND, VT, V);
2082 // fold !(x or y) -> (!x and !y) iff x or y are setcc
2083 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 &&
2084 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2085 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2086 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2087 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2088 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
2089 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
2090 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
2091 return DAG.getNode(NewOpcode, VT, LHS, RHS);
2094 // fold !(x or y) -> (!x and !y) iff x or y are constants
2095 if (N1C && N1C->isAllOnesValue() &&
2096 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2097 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2098 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2099 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2100 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
2101 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
2102 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
2103 return DAG.getNode(NewOpcode, VT, LHS, RHS);
2106 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
2107 if (N1C && N0.getOpcode() == ISD::XOR) {
2108 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2109 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2111 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
2112 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
2114 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
2115 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
2117 // fold (xor x, x) -> 0
2119 if (!MVT::isVector(VT)) {
2120 return DAG.getConstant(0, VT);
2121 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
2122 // Produce a vector of zeros.
2123 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT));
2124 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
2125 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
2129 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2130 if (N0.getOpcode() == N1.getOpcode()) {
2131 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2132 if (Tmp.Val) return Tmp;
2135 // Simplify the expression using non-local knowledge.
2136 if (!MVT::isVector(VT) &&
2137 SimplifyDemandedBits(SDOperand(N, 0)))
2138 return SDOperand(N, 0);
2143 /// visitShiftByConstant - Handle transforms common to the three shifts, when
2144 /// the shift amount is a constant.
2145 SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
2146 SDNode *LHS = N->getOperand(0).Val;
2147 if (!LHS->hasOneUse()) return SDOperand();
2149 // We want to pull some binops through shifts, so that we have (and (shift))
2150 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
2151 // thing happens with address calculations, so it's important to canonicalize
2153 bool HighBitSet = false; // Can we transform this if the high bit is set?
2155 switch (LHS->getOpcode()) {
2156 default: return SDOperand();
2159 HighBitSet = false; // We can only transform sra if the high bit is clear.
2162 HighBitSet = true; // We can only transform sra if the high bit is set.
2165 if (N->getOpcode() != ISD::SHL)
2166 return SDOperand(); // only shl(add) not sr[al](add).
2167 HighBitSet = false; // We can only transform sra if the high bit is clear.
2171 // We require the RHS of the binop to be a constant as well.
2172 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
2173 if (!BinOpCst) return SDOperand();
2176 // FIXME: disable this for unless the input to the binop is a shift by a
2177 // constant. If it is not a shift, it pessimizes some common cases like:
2179 //void foo(int *X, int i) { X[i & 1235] = 1; }
2180 //int bar(int *X, int i) { return X[i & 255]; }
2181 SDNode *BinOpLHSVal = LHS->getOperand(0).Val;
2182 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
2183 BinOpLHSVal->getOpcode() != ISD::SRA &&
2184 BinOpLHSVal->getOpcode() != ISD::SRL) ||
2185 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
2188 MVT::ValueType VT = N->getValueType(0);
2190 // If this is a signed shift right, and the high bit is modified
2191 // by the logical operation, do not perform the transformation.
2192 // The highBitSet boolean indicates the value of the high bit of
2193 // the constant which would cause it to be modified for this
2195 if (N->getOpcode() == ISD::SRA) {
2196 uint64_t BinOpRHSSign = BinOpCst->getValue() >> MVT::getSizeInBits(VT)-1;
2197 if ((bool)BinOpRHSSign != HighBitSet)
2201 // Fold the constants, shifting the binop RHS by the shift amount.
2202 SDOperand NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0),
2203 LHS->getOperand(1), N->getOperand(1));
2205 // Create the new shift.
2206 SDOperand NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0),
2209 // Create the new binop.
2210 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS);
2214 SDOperand DAGCombiner::visitSHL(SDNode *N) {
2215 SDOperand N0 = N->getOperand(0);
2216 SDOperand N1 = N->getOperand(1);
2217 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2218 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2219 MVT::ValueType VT = N0.getValueType();
2220 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2222 // fold (shl c1, c2) -> c1<<c2
2224 return DAG.getNode(ISD::SHL, VT, N0, N1);
2225 // fold (shl 0, x) -> 0
2226 if (N0C && N0C->isNullValue())
2228 // fold (shl x, c >= size(x)) -> undef
2229 if (N1C && N1C->getValue() >= OpSizeInBits)
2230 return DAG.getNode(ISD::UNDEF, VT);
2231 // fold (shl x, 0) -> x
2232 if (N1C && N1C->isNullValue())
2234 // if (shl x, c) is known to be zero, return 0
2235 if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
2236 return DAG.getConstant(0, VT);
2237 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2238 return SDOperand(N, 0);
2239 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
2240 if (N1C && N0.getOpcode() == ISD::SHL &&
2241 N0.getOperand(1).getOpcode() == ISD::Constant) {
2242 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2243 uint64_t c2 = N1C->getValue();
2244 if (c1 + c2 > OpSizeInBits)
2245 return DAG.getConstant(0, VT);
2246 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
2247 DAG.getConstant(c1 + c2, N1.getValueType()));
2249 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
2250 // (srl (and x, -1 << c1), c1-c2)
2251 if (N1C && N0.getOpcode() == ISD::SRL &&
2252 N0.getOperand(1).getOpcode() == ISD::Constant) {
2253 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2254 uint64_t c2 = N1C->getValue();
2255 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2256 DAG.getConstant(~0ULL << c1, VT));
2258 return DAG.getNode(ISD::SHL, VT, Mask,
2259 DAG.getConstant(c2-c1, N1.getValueType()));
2261 return DAG.getNode(ISD::SRL, VT, Mask,
2262 DAG.getConstant(c1-c2, N1.getValueType()));
2264 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
2265 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
2266 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2267 DAG.getConstant(~0ULL << N1C->getValue(), VT));
2269 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand();
2272 SDOperand DAGCombiner::visitSRA(SDNode *N) {
2273 SDOperand N0 = N->getOperand(0);
2274 SDOperand N1 = N->getOperand(1);
2275 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2276 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2277 MVT::ValueType VT = N0.getValueType();
2279 // fold (sra c1, c2) -> c1>>c2
2281 return DAG.getNode(ISD::SRA, VT, N0, N1);
2282 // fold (sra 0, x) -> 0
2283 if (N0C && N0C->isNullValue())
2285 // fold (sra -1, x) -> -1
2286 if (N0C && N0C->isAllOnesValue())
2288 // fold (sra x, c >= size(x)) -> undef
2289 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
2290 return DAG.getNode(ISD::UNDEF, VT);
2291 // fold (sra x, 0) -> x
2292 if (N1C && N1C->isNullValue())
2294 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2296 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2297 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
2300 default: EVT = MVT::Other; break;
2301 case 1: EVT = MVT::i1; break;
2302 case 8: EVT = MVT::i8; break;
2303 case 16: EVT = MVT::i16; break;
2304 case 32: EVT = MVT::i32; break;
2306 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
2307 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
2308 DAG.getValueType(EVT));
2311 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
2312 if (N1C && N0.getOpcode() == ISD::SRA) {
2313 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2314 unsigned Sum = N1C->getValue() + C1->getValue();
2315 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
2316 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
2317 DAG.getConstant(Sum, N1C->getValueType(0)));
2321 // Simplify, based on bits shifted out of the LHS.
2322 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2323 return SDOperand(N, 0);
2326 // If the sign bit is known to be zero, switch this to a SRL.
2327 if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
2328 return DAG.getNode(ISD::SRL, VT, N0, N1);
2330 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand();
2333 SDOperand DAGCombiner::visitSRL(SDNode *N) {
2334 SDOperand N0 = N->getOperand(0);
2335 SDOperand N1 = N->getOperand(1);
2336 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2337 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2338 MVT::ValueType VT = N0.getValueType();
2339 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2341 // fold (srl c1, c2) -> c1 >>u c2
2343 return DAG.getNode(ISD::SRL, VT, N0, N1);
2344 // fold (srl 0, x) -> 0
2345 if (N0C && N0C->isNullValue())
2347 // fold (srl x, c >= size(x)) -> undef
2348 if (N1C && N1C->getValue() >= OpSizeInBits)
2349 return DAG.getNode(ISD::UNDEF, VT);
2350 // fold (srl x, 0) -> x
2351 if (N1C && N1C->isNullValue())
2353 // if (srl x, c) is known to be zero, return 0
2354 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
2355 return DAG.getConstant(0, VT);
2357 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
2358 if (N1C && N0.getOpcode() == ISD::SRL &&
2359 N0.getOperand(1).getOpcode() == ISD::Constant) {
2360 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2361 uint64_t c2 = N1C->getValue();
2362 if (c1 + c2 > OpSizeInBits)
2363 return DAG.getConstant(0, VT);
2364 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
2365 DAG.getConstant(c1 + c2, N1.getValueType()));
2368 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
2369 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2370 // Shifting in all undef bits?
2371 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
2372 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
2373 return DAG.getNode(ISD::UNDEF, VT);
2375 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
2376 AddToWorkList(SmallShift.Val);
2377 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
2380 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
2381 // bit, which is unmodified by sra.
2382 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
2383 if (N0.getOpcode() == ISD::SRA)
2384 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
2387 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
2388 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2389 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
2390 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
2391 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
2393 // If any of the input bits are KnownOne, then the input couldn't be all
2394 // zeros, thus the result of the srl will always be zero.
2395 if (KnownOne) return DAG.getConstant(0, VT);
2397 // If all of the bits input the to ctlz node are known to be zero, then
2398 // the result of the ctlz is "32" and the result of the shift is one.
2399 uint64_t UnknownBits = ~KnownZero & Mask;
2400 if (UnknownBits == 0) return DAG.getConstant(1, VT);
2402 // Otherwise, check to see if there is exactly one bit input to the ctlz.
2403 if ((UnknownBits & (UnknownBits-1)) == 0) {
2404 // Okay, we know that only that the single bit specified by UnknownBits
2405 // could be set on input to the CTLZ node. If this bit is set, the SRL
2406 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
2407 // to an SRL,XOR pair, which is likely to simplify more.
2408 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
2409 SDOperand Op = N0.getOperand(0);
2411 Op = DAG.getNode(ISD::SRL, VT, Op,
2412 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
2413 AddToWorkList(Op.Val);
2415 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
2419 // fold operands of srl based on knowledge that the low bits are not
2421 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2422 return SDOperand(N, 0);
2424 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand();
2427 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
2428 SDOperand N0 = N->getOperand(0);
2429 MVT::ValueType VT = N->getValueType(0);
2431 // fold (ctlz c1) -> c2
2432 if (isa<ConstantSDNode>(N0))
2433 return DAG.getNode(ISD::CTLZ, VT, N0);
2437 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
2438 SDOperand N0 = N->getOperand(0);
2439 MVT::ValueType VT = N->getValueType(0);
2441 // fold (cttz c1) -> c2
2442 if (isa<ConstantSDNode>(N0))
2443 return DAG.getNode(ISD::CTTZ, VT, N0);
2447 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
2448 SDOperand N0 = N->getOperand(0);
2449 MVT::ValueType VT = N->getValueType(0);
2451 // fold (ctpop c1) -> c2
2452 if (isa<ConstantSDNode>(N0))
2453 return DAG.getNode(ISD::CTPOP, VT, N0);
2457 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
2458 SDOperand N0 = N->getOperand(0);
2459 SDOperand N1 = N->getOperand(1);
2460 SDOperand N2 = N->getOperand(2);
2461 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2462 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2463 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2464 MVT::ValueType VT = N->getValueType(0);
2465 MVT::ValueType VT0 = N0.getValueType();
2467 // fold select C, X, X -> X
2470 // fold select true, X, Y -> X
2471 if (N0C && !N0C->isNullValue())
2473 // fold select false, X, Y -> Y
2474 if (N0C && N0C->isNullValue())
2476 // fold select C, 1, X -> C | X
2477 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
2478 return DAG.getNode(ISD::OR, VT, N0, N2);
2479 // fold select C, 0, 1 -> ~C
2480 if (MVT::isInteger(VT) && MVT::isInteger(VT0) &&
2481 N1C && N2C && N1C->isNullValue() && N2C->getValue() == 1) {
2482 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0));
2485 AddToWorkList(XORNode.Val);
2486 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0))
2487 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
2488 return DAG.getNode(ISD::TRUNCATE, VT, XORNode);
2490 // fold select C, 0, X -> ~C & X
2491 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
2492 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2493 AddToWorkList(XORNode.Val);
2494 return DAG.getNode(ISD::AND, VT, XORNode, N2);
2496 // fold select C, X, 1 -> ~C | X
2497 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getValue() == 1) {
2498 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2499 AddToWorkList(XORNode.Val);
2500 return DAG.getNode(ISD::OR, VT, XORNode, N1);
2502 // fold select C, X, 0 -> C & X
2503 // FIXME: this should check for C type == X type, not i1?
2504 if (MVT::i1 == VT && N2C && N2C->isNullValue())
2505 return DAG.getNode(ISD::AND, VT, N0, N1);
2506 // fold X ? X : Y --> X ? 1 : Y --> X | Y
2507 if (MVT::i1 == VT && N0 == N1)
2508 return DAG.getNode(ISD::OR, VT, N0, N2);
2509 // fold X ? Y : X --> X ? Y : 0 --> X & Y
2510 if (MVT::i1 == VT && N0 == N2)
2511 return DAG.getNode(ISD::AND, VT, N0, N1);
2513 // If we can fold this based on the true/false value, do so.
2514 if (SimplifySelectOps(N, N1, N2))
2515 return SDOperand(N, 0); // Don't revisit N.
2517 // fold selects based on a setcc into other things, such as min/max/abs
2518 if (N0.getOpcode() == ISD::SETCC)
2520 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
2521 // having to say they don't support SELECT_CC on every type the DAG knows
2522 // about, since there is no way to mark an opcode illegal at all value types
2523 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
2524 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
2525 N1, N2, N0.getOperand(2));
2527 return SimplifySelect(N0, N1, N2);
2531 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
2532 SDOperand N0 = N->getOperand(0);
2533 SDOperand N1 = N->getOperand(1);
2534 SDOperand N2 = N->getOperand(2);
2535 SDOperand N3 = N->getOperand(3);
2536 SDOperand N4 = N->getOperand(4);
2537 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
2539 // fold select_cc lhs, rhs, x, x, cc -> x
2543 // Determine if the condition we're dealing with is constant
2544 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
2545 if (SCC.Val) AddToWorkList(SCC.Val);
2547 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
2548 if (SCCC->getValue())
2549 return N2; // cond always true -> true val
2551 return N3; // cond always false -> false val
2554 // Fold to a simpler select_cc
2555 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
2556 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
2557 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
2560 // If we can fold this based on the true/false value, do so.
2561 if (SimplifySelectOps(N, N2, N3))
2562 return SDOperand(N, 0); // Don't revisit N.
2564 // fold select_cc into other things, such as min/max/abs
2565 return SimplifySelectCC(N0, N1, N2, N3, CC);
2568 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
2569 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
2570 cast<CondCodeSDNode>(N->getOperand(2))->get());
2573 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
2574 // "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))"
2575 // transformation. Returns true if extension are possible and the above
2576 // mentioned transformation is profitable.
2577 static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0,
2579 SmallVector<SDNode*, 4> &ExtendNodes,
2580 TargetLowering &TLI) {
2581 bool HasCopyToRegUses = false;
2582 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
2583 for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end();
2588 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
2589 if (User->getOpcode() == ISD::SETCC) {
2590 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
2591 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
2592 // Sign bits will be lost after a zext.
2595 for (unsigned i = 0; i != 2; ++i) {
2596 SDOperand UseOp = User->getOperand(i);
2599 if (!isa<ConstantSDNode>(UseOp))
2604 ExtendNodes.push_back(User);
2606 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2607 SDOperand UseOp = User->getOperand(i);
2609 // If truncate from extended type to original load type is free
2610 // on this target, then it's ok to extend a CopyToReg.
2611 if (isTruncFree && User->getOpcode() == ISD::CopyToReg)
2612 HasCopyToRegUses = true;
2620 if (HasCopyToRegUses) {
2621 bool BothLiveOut = false;
2622 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
2625 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2626 SDOperand UseOp = User->getOperand(i);
2627 if (UseOp.Val == N && UseOp.ResNo == 0) {
2634 // Both unextended and extended values are live out. There had better be
2635 // good a reason for the transformation.
2636 return ExtendNodes.size();
2641 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
2642 SDOperand N0 = N->getOperand(0);
2643 MVT::ValueType VT = N->getValueType(0);
2645 // fold (sext c1) -> c1
2646 if (isa<ConstantSDNode>(N0))
2647 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
2649 // fold (sext (sext x)) -> (sext x)
2650 // fold (sext (aext x)) -> (sext x)
2651 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2652 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
2654 // fold (sext (truncate (load x))) -> (sext (smaller load x))
2655 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
2656 if (N0.getOpcode() == ISD::TRUNCATE) {
2657 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2658 if (NarrowLoad.Val) {
2659 if (NarrowLoad.Val != N0.Val)
2660 CombineTo(N0.Val, NarrowLoad);
2661 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad);
2665 // See if the value being truncated is already sign extended. If so, just
2666 // eliminate the trunc/sext pair.
2667 if (N0.getOpcode() == ISD::TRUNCATE) {
2668 SDOperand Op = N0.getOperand(0);
2669 unsigned OpBits = MVT::getSizeInBits(Op.getValueType());
2670 unsigned MidBits = MVT::getSizeInBits(N0.getValueType());
2671 unsigned DestBits = MVT::getSizeInBits(VT);
2672 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
2674 if (OpBits == DestBits) {
2675 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
2676 // bits, it is already ready.
2677 if (NumSignBits > DestBits-MidBits)
2679 } else if (OpBits < DestBits) {
2680 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
2681 // bits, just sext from i32.
2682 if (NumSignBits > OpBits-MidBits)
2683 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op);
2685 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
2686 // bits, just truncate to i32.
2687 if (NumSignBits > OpBits-MidBits)
2688 return DAG.getNode(ISD::TRUNCATE, VT, Op);
2691 // fold (sext (truncate x)) -> (sextinreg x).
2692 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
2693 N0.getValueType())) {
2694 if (Op.getValueType() < VT)
2695 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2696 else if (Op.getValueType() > VT)
2697 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2698 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
2699 DAG.getValueType(N0.getValueType()));
2703 // fold (sext (load x)) -> (sext (truncate (sextload x)))
2704 if (ISD::isNON_EXTLoad(N0.Val) &&
2705 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
2706 bool DoXform = true;
2707 SmallVector<SDNode*, 4> SetCCs;
2708 if (!N0.hasOneUse())
2709 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
2711 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2712 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2713 LN0->getBasePtr(), LN0->getSrcValue(),
2714 LN0->getSrcValueOffset(),
2717 LN0->getAlignment());
2718 CombineTo(N, ExtLoad);
2719 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
2720 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
2721 // Extend SetCC uses if necessary.
2722 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
2723 SDNode *SetCC = SetCCs[i];
2724 SmallVector<SDOperand, 4> Ops;
2725 for (unsigned j = 0; j != 2; ++j) {
2726 SDOperand SOp = SetCC->getOperand(j);
2728 Ops.push_back(ExtLoad);
2730 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp));
2732 Ops.push_back(SetCC->getOperand(2));
2733 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0),
2734 &Ops[0], Ops.size()));
2736 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2740 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
2741 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
2742 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2743 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2744 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2745 MVT::ValueType EVT = LN0->getLoadedVT();
2746 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
2747 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2748 LN0->getBasePtr(), LN0->getSrcValue(),
2749 LN0->getSrcValueOffset(), EVT,
2751 LN0->getAlignment());
2752 CombineTo(N, ExtLoad);
2753 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2754 ExtLoad.getValue(1));
2755 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2759 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc
2760 if (N0.getOpcode() == ISD::SETCC) {
2762 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2763 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
2764 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2765 if (SCC.Val) return SCC;
2771 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
2772 SDOperand N0 = N->getOperand(0);
2773 MVT::ValueType VT = N->getValueType(0);
2775 // fold (zext c1) -> c1
2776 if (isa<ConstantSDNode>(N0))
2777 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2778 // fold (zext (zext x)) -> (zext x)
2779 // fold (zext (aext x)) -> (zext x)
2780 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2781 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
2783 // fold (zext (truncate (load x))) -> (zext (smaller load x))
2784 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
2785 if (N0.getOpcode() == ISD::TRUNCATE) {
2786 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2787 if (NarrowLoad.Val) {
2788 if (NarrowLoad.Val != N0.Val)
2789 CombineTo(N0.Val, NarrowLoad);
2790 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad);
2794 // fold (zext (truncate x)) -> (and x, mask)
2795 if (N0.getOpcode() == ISD::TRUNCATE &&
2796 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
2797 SDOperand Op = N0.getOperand(0);
2798 if (Op.getValueType() < VT) {
2799 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2800 } else if (Op.getValueType() > VT) {
2801 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2803 return DAG.getZeroExtendInReg(Op, N0.getValueType());
2806 // fold (zext (and (trunc x), cst)) -> (and x, cst).
2807 if (N0.getOpcode() == ISD::AND &&
2808 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2809 N0.getOperand(1).getOpcode() == ISD::Constant) {
2810 SDOperand X = N0.getOperand(0).getOperand(0);
2811 if (X.getValueType() < VT) {
2812 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2813 } else if (X.getValueType() > VT) {
2814 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2816 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2817 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2820 // fold (zext (load x)) -> (zext (truncate (zextload x)))
2821 if (ISD::isNON_EXTLoad(N0.Val) &&
2822 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
2823 bool DoXform = true;
2824 SmallVector<SDNode*, 4> SetCCs;
2825 if (!N0.hasOneUse())
2826 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
2828 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2829 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2830 LN0->getBasePtr(), LN0->getSrcValue(),
2831 LN0->getSrcValueOffset(),
2834 LN0->getAlignment());
2835 CombineTo(N, ExtLoad);
2836 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
2837 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
2838 // Extend SetCC uses if necessary.
2839 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
2840 SDNode *SetCC = SetCCs[i];
2841 SmallVector<SDOperand, 4> Ops;
2842 for (unsigned j = 0; j != 2; ++j) {
2843 SDOperand SOp = SetCC->getOperand(j);
2845 Ops.push_back(ExtLoad);
2847 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp));
2849 Ops.push_back(SetCC->getOperand(2));
2850 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0),
2851 &Ops[0], Ops.size()));
2853 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2857 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
2858 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
2859 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2860 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2861 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2862 MVT::ValueType EVT = LN0->getLoadedVT();
2863 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2864 LN0->getBasePtr(), LN0->getSrcValue(),
2865 LN0->getSrcValueOffset(), EVT,
2867 LN0->getAlignment());
2868 CombineTo(N, ExtLoad);
2869 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2870 ExtLoad.getValue(1));
2871 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2874 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2875 if (N0.getOpcode() == ISD::SETCC) {
2877 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2878 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2879 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2880 if (SCC.Val) return SCC;
2886 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
2887 SDOperand N0 = N->getOperand(0);
2888 MVT::ValueType VT = N->getValueType(0);
2890 // fold (aext c1) -> c1
2891 if (isa<ConstantSDNode>(N0))
2892 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
2893 // fold (aext (aext x)) -> (aext x)
2894 // fold (aext (zext x)) -> (zext x)
2895 // fold (aext (sext x)) -> (sext x)
2896 if (N0.getOpcode() == ISD::ANY_EXTEND ||
2897 N0.getOpcode() == ISD::ZERO_EXTEND ||
2898 N0.getOpcode() == ISD::SIGN_EXTEND)
2899 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2901 // fold (aext (truncate (load x))) -> (aext (smaller load x))
2902 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
2903 if (N0.getOpcode() == ISD::TRUNCATE) {
2904 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2905 if (NarrowLoad.Val) {
2906 if (NarrowLoad.Val != N0.Val)
2907 CombineTo(N0.Val, NarrowLoad);
2908 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad);
2912 // fold (aext (truncate x))
2913 if (N0.getOpcode() == ISD::TRUNCATE) {
2914 SDOperand TruncOp = N0.getOperand(0);
2915 if (TruncOp.getValueType() == VT)
2916 return TruncOp; // x iff x size == zext size.
2917 if (TruncOp.getValueType() > VT)
2918 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
2919 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
2922 // fold (aext (and (trunc x), cst)) -> (and x, cst).
2923 if (N0.getOpcode() == ISD::AND &&
2924 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2925 N0.getOperand(1).getOpcode() == ISD::Constant) {
2926 SDOperand X = N0.getOperand(0).getOperand(0);
2927 if (X.getValueType() < VT) {
2928 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2929 } else if (X.getValueType() > VT) {
2930 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2932 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2933 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2936 // fold (aext (load x)) -> (aext (truncate (extload x)))
2937 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2938 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2939 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2940 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2941 LN0->getBasePtr(), LN0->getSrcValue(),
2942 LN0->getSrcValueOffset(),
2945 LN0->getAlignment());
2946 CombineTo(N, ExtLoad);
2947 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2948 ExtLoad.getValue(1));
2949 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2952 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2953 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2954 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2955 if (N0.getOpcode() == ISD::LOAD &&
2956 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
2958 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2959 MVT::ValueType EVT = LN0->getLoadedVT();
2960 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2961 LN0->getChain(), LN0->getBasePtr(),
2963 LN0->getSrcValueOffset(), EVT,
2965 LN0->getAlignment());
2966 CombineTo(N, ExtLoad);
2967 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2968 ExtLoad.getValue(1));
2969 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2972 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2973 if (N0.getOpcode() == ISD::SETCC) {
2975 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2976 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2977 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2985 /// GetDemandedBits - See if the specified operand can be simplified with the
2986 /// knowledge that only the bits specified by Mask are used. If so, return the
2987 /// simpler operand, otherwise return a null SDOperand.
2988 SDOperand DAGCombiner::GetDemandedBits(SDOperand V, uint64_t Mask) {
2989 switch (V.getOpcode()) {
2993 // If the LHS or RHS don't contribute bits to the or, drop them.
2994 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
2995 return V.getOperand(1);
2996 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
2997 return V.getOperand(0);
3000 // Only look at single-use SRLs.
3001 if (!V.Val->hasOneUse())
3003 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
3004 // See if we can recursively simplify the LHS.
3005 unsigned Amt = RHSC->getValue();
3006 Mask = (Mask << Amt) & MVT::getIntVTBitMask(V.getValueType());
3007 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), Mask);
3008 if (SimplifyLHS.Val) {
3009 return DAG.getNode(ISD::SRL, V.getValueType(),
3010 SimplifyLHS, V.getOperand(1));
3017 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
3018 /// bits and then truncated to a narrower type and where N is a multiple
3019 /// of number of bits of the narrower type, transform it to a narrower load
3020 /// from address + N / num of bits of new type. If the result is to be
3021 /// extended, also fold the extension to form a extending load.
3022 SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
3023 unsigned Opc = N->getOpcode();
3024 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
3025 SDOperand N0 = N->getOperand(0);
3026 MVT::ValueType VT = N->getValueType(0);
3027 MVT::ValueType EVT = N->getValueType(0);
3029 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
3031 if (Opc == ISD::SIGN_EXTEND_INREG) {
3032 ExtType = ISD::SEXTLOAD;
3033 EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3034 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))
3038 unsigned EVTBits = MVT::getSizeInBits(EVT);
3040 bool CombineSRL = false;
3041 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
3042 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3043 ShAmt = N01->getValue();
3044 // Is the shift amount a multiple of size of VT?
3045 if ((ShAmt & (EVTBits-1)) == 0) {
3046 N0 = N0.getOperand(0);
3047 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits)
3054 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
3055 // Do not allow folding to i1 here. i1 is implicitly stored in memory in
3056 // zero extended form: by shrinking the load, we lose track of the fact
3057 // that it is already zero extended.
3058 // FIXME: This should be reevaluated.
3060 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits &&
3061 "Cannot truncate to larger type!");
3062 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3063 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
3064 // For big endian targets, we need to adjust the offset to the pointer to
3065 // load the correct bytes.
3066 if (!TLI.isLittleEndian()) {
3067 unsigned LVTStoreBits = MVT::getStoreSizeInBits(N0.getValueType());
3068 unsigned EVTStoreBits = MVT::getStoreSizeInBits(EVT);
3069 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
3071 uint64_t PtrOff = ShAmt / 8;
3072 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
3073 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
3074 DAG.getConstant(PtrOff, PtrType));
3075 AddToWorkList(NewPtr.Val);
3076 SDOperand Load = (ExtType == ISD::NON_EXTLOAD)
3077 ? DAG.getLoad(VT, LN0->getChain(), NewPtr,
3078 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3079 LN0->isVolatile(), NewAlign)
3080 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr,
3081 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
3082 LN0->isVolatile(), NewAlign);
3085 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
3086 CombineTo(N->getOperand(0).Val, Load);
3088 CombineTo(N0.Val, Load, Load.getValue(1));
3090 if (Opc == ISD::SIGN_EXTEND_INREG)
3091 return DAG.getNode(Opc, VT, Load, N->getOperand(1));
3093 return DAG.getNode(Opc, VT, Load);
3095 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3102 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
3103 SDOperand N0 = N->getOperand(0);
3104 SDOperand N1 = N->getOperand(1);
3105 MVT::ValueType VT = N->getValueType(0);
3106 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
3107 unsigned EVTBits = MVT::getSizeInBits(EVT);
3109 // fold (sext_in_reg c1) -> c1
3110 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
3111 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
3113 // If the input is already sign extended, just drop the extension.
3114 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
3117 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
3118 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3119 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
3120 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
3123 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
3124 if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
3125 return DAG.getZeroExtendInReg(N0, EVT);
3127 // fold operands of sext_in_reg based on knowledge that the top bits are not
3129 if (SimplifyDemandedBits(SDOperand(N, 0)))
3130 return SDOperand(N, 0);
3132 // fold (sext_in_reg (load x)) -> (smaller sextload x)
3133 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
3134 SDOperand NarrowLoad = ReduceLoadWidth(N);
3138 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
3139 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
3140 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
3141 if (N0.getOpcode() == ISD::SRL) {
3142 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
3143 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
3144 // We can turn this into an SRA iff the input to the SRL is already sign
3146 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
3147 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
3148 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
3152 // fold (sext_inreg (extload x)) -> (sextload x)
3153 if (ISD::isEXTLoad(N0.Val) &&
3154 ISD::isUNINDEXEDLoad(N0.Val) &&
3155 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
3156 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
3157 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3158 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
3159 LN0->getBasePtr(), LN0->getSrcValue(),
3160 LN0->getSrcValueOffset(), EVT,
3162 LN0->getAlignment());
3163 CombineTo(N, ExtLoad);
3164 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
3165 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3167 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
3168 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
3170 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
3171 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
3172 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3173 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
3174 LN0->getBasePtr(), LN0->getSrcValue(),
3175 LN0->getSrcValueOffset(), EVT,
3177 LN0->getAlignment());
3178 CombineTo(N, ExtLoad);
3179 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
3180 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3185 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
3186 SDOperand N0 = N->getOperand(0);
3187 MVT::ValueType VT = N->getValueType(0);
3190 if (N0.getValueType() == N->getValueType(0))
3192 // fold (truncate c1) -> c1
3193 if (isa<ConstantSDNode>(N0))
3194 return DAG.getNode(ISD::TRUNCATE, VT, N0);
3195 // fold (truncate (truncate x)) -> (truncate x)
3196 if (N0.getOpcode() == ISD::TRUNCATE)
3197 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
3198 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
3199 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
3200 N0.getOpcode() == ISD::ANY_EXTEND) {
3201 if (N0.getOperand(0).getValueType() < VT)
3202 // if the source is smaller than the dest, we still need an extend
3203 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
3204 else if (N0.getOperand(0).getValueType() > VT)
3205 // if the source is larger than the dest, than we just need the truncate
3206 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
3208 // if the source and dest are the same type, we can drop both the extend
3210 return N0.getOperand(0);
3213 // See if we can simplify the input to this truncate through knowledge that
3214 // only the low bits are being used. For example "trunc (or (shl x, 8), y)"
3216 SDOperand Shorter = GetDemandedBits(N0, MVT::getIntVTBitMask(VT));
3218 return DAG.getNode(ISD::TRUNCATE, VT, Shorter);
3220 // fold (truncate (load x)) -> (smaller load x)
3221 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
3222 return ReduceLoadWidth(N);
3225 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
3226 SDOperand N0 = N->getOperand(0);
3227 MVT::ValueType VT = N->getValueType(0);
3229 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
3230 // Only do this before legalize, since afterward the target may be depending
3231 // on the bitconvert.
3232 // First check to see if this is all constant.
3233 if (!AfterLegalize &&
3234 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() &&
3235 MVT::isVector(VT)) {
3236 bool isSimple = true;
3237 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
3238 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
3239 N0.getOperand(i).getOpcode() != ISD::Constant &&
3240 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
3245 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0));
3246 assert(!MVT::isVector(DestEltVT) &&
3247 "Element type of vector ValueType must not be vector!");
3249 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT);
3253 // If the input is a constant, let getNode() fold it.
3254 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
3255 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
3256 if (Res.Val != N) return Res;
3259 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
3260 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
3262 // fold (conv (load x)) -> (load (conv*)x)
3263 // If the resultant load doesn't need a higher alignment than the original!
3264 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() &&
3265 TLI.isOperationLegal(ISD::LOAD, VT)) {
3266 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3267 unsigned Align = TLI.getTargetMachine().getTargetData()->
3268 getABITypeAlignment(MVT::getTypeForValueType(VT));
3269 unsigned OrigAlign = LN0->getAlignment();
3270 if (Align <= OrigAlign) {
3271 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
3272 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3273 LN0->isVolatile(), Align);
3275 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
3281 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit)
3282 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit)
3283 // This often reduces constant pool loads.
3284 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
3285 N0.Val->hasOneUse() && MVT::isInteger(VT) && !MVT::isVector(VT)) {
3286 SDOperand NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
3287 AddToWorkList(NewConv.Val);
3289 uint64_t SignBit = MVT::getIntVTSignBit(VT);
3290 if (N0.getOpcode() == ISD::FNEG)
3291 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT));
3292 assert(N0.getOpcode() == ISD::FABS);
3293 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT));
3296 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign'
3297 // Note that we don't handle copysign(x,cst) because this can always be folded
3298 // to an fneg or fabs.
3299 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse() &&
3300 isa<ConstantFPSDNode>(N0.getOperand(0))) {
3301 unsigned OrigXWidth = MVT::getSizeInBits(N0.getOperand(1).getValueType());
3302 SDOperand X = DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerType(OrigXWidth),
3304 AddToWorkList(X.Val);
3306 // If X has a different width than the result/lhs, sext it or truncate it.
3307 unsigned VTWidth = MVT::getSizeInBits(VT);
3308 if (OrigXWidth < VTWidth) {
3309 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X);
3310 AddToWorkList(X.Val);
3311 } else if (OrigXWidth > VTWidth) {
3312 // To get the sign bit in the right place, we have to shift it right
3313 // before truncating.
3314 X = DAG.getNode(ISD::SRL, X.getValueType(), X,
3315 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
3316 AddToWorkList(X.Val);
3317 X = DAG.getNode(ISD::TRUNCATE, VT, X);
3318 AddToWorkList(X.Val);
3321 uint64_t SignBit = MVT::getIntVTSignBit(VT);
3322 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT));
3323 AddToWorkList(X.Val);
3325 SDOperand Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
3326 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT));
3327 AddToWorkList(Cst.Val);
3329 return DAG.getNode(ISD::OR, VT, X, Cst);
3335 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
3336 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
3337 /// destination element value type.
3338 SDOperand DAGCombiner::
3339 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
3340 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
3342 // If this is already the right type, we're done.
3343 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
3345 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
3346 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
3348 // If this is a conversion of N elements of one type to N elements of another
3349 // type, convert each element. This handles FP<->INT cases.
3350 if (SrcBitSize == DstBitSize) {
3351 SmallVector<SDOperand, 8> Ops;
3352 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3353 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
3354 AddToWorkList(Ops.back().Val);
3357 MVT::getVectorType(DstEltVT,
3358 MVT::getVectorNumElements(BV->getValueType(0)));
3359 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3362 // Otherwise, we're growing or shrinking the elements. To avoid having to
3363 // handle annoying details of growing/shrinking FP values, we convert them to
3365 if (MVT::isFloatingPoint(SrcEltVT)) {
3366 // Convert the input float vector to a int vector where the elements are the
3368 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
3369 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
3370 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val;
3374 // Now we know the input is an integer vector. If the output is a FP type,
3375 // convert to integer first, then to FP of the right size.
3376 if (MVT::isFloatingPoint(DstEltVT)) {
3377 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
3378 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
3379 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val;
3381 // Next, convert to FP elements of the same size.
3382 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
3385 // Okay, we know the src/dst types are both integers of differing types.
3386 // Handling growing first.
3387 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
3388 if (SrcBitSize < DstBitSize) {
3389 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
3391 SmallVector<SDOperand, 8> Ops;
3392 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
3393 i += NumInputsPerOutput) {
3394 bool isLE = TLI.isLittleEndian();
3395 uint64_t NewBits = 0;
3396 bool EltIsUndef = true;
3397 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
3398 // Shift the previously computed bits over.
3399 NewBits <<= SrcBitSize;
3400 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
3401 if (Op.getOpcode() == ISD::UNDEF) continue;
3404 NewBits |= cast<ConstantSDNode>(Op)->getValue();
3408 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3410 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
3413 MVT::ValueType VT = MVT::getVectorType(DstEltVT,
3415 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3418 // Finally, this must be the case where we are shrinking elements: each input
3419 // turns into multiple outputs.
3420 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
3421 SmallVector<SDOperand, 8> Ops;
3422 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3423 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
3424 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
3425 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3428 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
3430 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
3431 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
3432 OpVal >>= DstBitSize;
3433 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
3436 // For big endian targets, swap the order of the pieces of each element.
3437 if (!TLI.isLittleEndian())
3438 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
3440 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size());
3441 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3446 SDOperand DAGCombiner::visitFADD(SDNode *N) {
3447 SDOperand N0 = N->getOperand(0);
3448 SDOperand N1 = N->getOperand(1);
3449 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3450 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3451 MVT::ValueType VT = N->getValueType(0);
3454 if (MVT::isVector(VT)) {
3455 SDOperand FoldedVOp = SimplifyVBinOp(N);
3456 if (FoldedVOp.Val) return FoldedVOp;
3459 // fold (fadd c1, c2) -> c1+c2
3460 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3461 return DAG.getNode(ISD::FADD, VT, N0, N1);
3462 // canonicalize constant to RHS
3463 if (N0CFP && !N1CFP)
3464 return DAG.getNode(ISD::FADD, VT, N1, N0);
3465 // fold (A + (-B)) -> A-B
3466 if (isNegatibleForFree(N1) == 2)
3467 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG));
3468 // fold ((-A) + B) -> B-A
3469 if (isNegatibleForFree(N0) == 2)
3470 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG));
3472 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
3473 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
3474 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3475 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
3476 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1));
3481 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
3482 SDOperand N0 = N->getOperand(0);
3483 SDOperand N1 = N->getOperand(1);
3484 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3485 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3486 MVT::ValueType VT = N->getValueType(0);
3489 if (MVT::isVector(VT)) {
3490 SDOperand FoldedVOp = SimplifyVBinOp(N);
3491 if (FoldedVOp.Val) return FoldedVOp;
3494 // fold (fsub c1, c2) -> c1-c2
3495 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3496 return DAG.getNode(ISD::FSUB, VT, N0, N1);
3498 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
3499 if (isNegatibleForFree(N1))
3500 return GetNegatedExpression(N1, DAG);
3501 return DAG.getNode(ISD::FNEG, VT, N1);
3503 // fold (A-(-B)) -> A+B
3504 if (isNegatibleForFree(N1))
3505 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG));
3510 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
3511 SDOperand N0 = N->getOperand(0);
3512 SDOperand N1 = N->getOperand(1);
3513 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3514 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3515 MVT::ValueType VT = N->getValueType(0);
3518 if (MVT::isVector(VT)) {
3519 SDOperand FoldedVOp = SimplifyVBinOp(N);
3520 if (FoldedVOp.Val) return FoldedVOp;
3523 // fold (fmul c1, c2) -> c1*c2
3524 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3525 return DAG.getNode(ISD::FMUL, VT, N0, N1);
3526 // canonicalize constant to RHS
3527 if (N0CFP && !N1CFP)
3528 return DAG.getNode(ISD::FMUL, VT, N1, N0);
3529 // fold (fmul X, 2.0) -> (fadd X, X)
3530 if (N1CFP && N1CFP->isExactlyValue(+2.0))
3531 return DAG.getNode(ISD::FADD, VT, N0, N0);
3532 // fold (fmul X, -1.0) -> (fneg X)
3533 if (N1CFP && N1CFP->isExactlyValue(-1.0))
3534 return DAG.getNode(ISD::FNEG, VT, N0);
3537 if (char LHSNeg = isNegatibleForFree(N0)) {
3538 if (char RHSNeg = isNegatibleForFree(N1)) {
3539 // Both can be negated for free, check to see if at least one is cheaper
3541 if (LHSNeg == 2 || RHSNeg == 2)
3542 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG),
3543 GetNegatedExpression(N1, DAG));
3547 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
3548 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
3549 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3550 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
3551 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1));
3556 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
3557 SDOperand N0 = N->getOperand(0);
3558 SDOperand N1 = N->getOperand(1);
3559 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3560 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3561 MVT::ValueType VT = N->getValueType(0);
3564 if (MVT::isVector(VT)) {
3565 SDOperand FoldedVOp = SimplifyVBinOp(N);
3566 if (FoldedVOp.Val) return FoldedVOp;
3569 // fold (fdiv c1, c2) -> c1/c2
3570 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3571 return DAG.getNode(ISD::FDIV, VT, N0, N1);
3575 if (char LHSNeg = isNegatibleForFree(N0)) {
3576 if (char RHSNeg = isNegatibleForFree(N1)) {
3577 // Both can be negated for free, check to see if at least one is cheaper
3579 if (LHSNeg == 2 || RHSNeg == 2)
3580 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG),
3581 GetNegatedExpression(N1, DAG));
3588 SDOperand DAGCombiner::visitFREM(SDNode *N) {
3589 SDOperand N0 = N->getOperand(0);
3590 SDOperand N1 = N->getOperand(1);
3591 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3592 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3593 MVT::ValueType VT = N->getValueType(0);
3595 // fold (frem c1, c2) -> fmod(c1,c2)
3596 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3597 return DAG.getNode(ISD::FREM, VT, N0, N1);
3602 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
3603 SDOperand N0 = N->getOperand(0);
3604 SDOperand N1 = N->getOperand(1);
3605 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3606 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3607 MVT::ValueType VT = N->getValueType(0);
3609 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
3610 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
3613 const APFloat& V = N1CFP->getValueAPF();
3614 // copysign(x, c1) -> fabs(x) iff ispos(c1)
3615 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
3616 if (!V.isNegative())
3617 return DAG.getNode(ISD::FABS, VT, N0);
3619 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
3622 // copysign(fabs(x), y) -> copysign(x, y)
3623 // copysign(fneg(x), y) -> copysign(x, y)
3624 // copysign(copysign(x,z), y) -> copysign(x, y)
3625 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
3626 N0.getOpcode() == ISD::FCOPYSIGN)
3627 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
3629 // copysign(x, abs(y)) -> abs(x)
3630 if (N1.getOpcode() == ISD::FABS)
3631 return DAG.getNode(ISD::FABS, VT, N0);
3633 // copysign(x, copysign(y,z)) -> copysign(x, z)
3634 if (N1.getOpcode() == ISD::FCOPYSIGN)
3635 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
3637 // copysign(x, fp_extend(y)) -> copysign(x, y)
3638 // copysign(x, fp_round(y)) -> copysign(x, y)
3639 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
3640 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
3647 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
3648 SDOperand N0 = N->getOperand(0);
3649 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3650 MVT::ValueType VT = N->getValueType(0);
3652 // fold (sint_to_fp c1) -> c1fp
3653 if (N0C && N0.getValueType() != MVT::ppcf128)
3654 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
3658 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
3659 SDOperand N0 = N->getOperand(0);
3660 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3661 MVT::ValueType VT = N->getValueType(0);
3663 // fold (uint_to_fp c1) -> c1fp
3664 if (N0C && N0.getValueType() != MVT::ppcf128)
3665 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
3669 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
3670 SDOperand N0 = N->getOperand(0);
3671 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3672 MVT::ValueType VT = N->getValueType(0);
3674 // fold (fp_to_sint c1fp) -> c1
3676 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
3680 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
3681 SDOperand N0 = N->getOperand(0);
3682 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3683 MVT::ValueType VT = N->getValueType(0);
3685 // fold (fp_to_uint c1fp) -> c1
3686 if (N0CFP && VT != MVT::ppcf128)
3687 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
3691 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
3692 SDOperand N0 = N->getOperand(0);
3693 SDOperand N1 = N->getOperand(1);
3694 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3695 MVT::ValueType VT = N->getValueType(0);
3697 // fold (fp_round c1fp) -> c1fp
3698 if (N0CFP && N0.getValueType() != MVT::ppcf128)
3699 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1);
3701 // fold (fp_round (fp_extend x)) -> x
3702 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
3703 return N0.getOperand(0);
3705 // fold (fp_round (fp_round x)) -> (fp_round x)
3706 if (N0.getOpcode() == ISD::FP_ROUND) {
3707 // This is a value preserving truncation if both round's are.
3708 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
3709 N0.Val->getConstantOperandVal(1) == 1;
3710 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0),
3711 DAG.getIntPtrConstant(IsTrunc));
3714 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
3715 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
3716 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1);
3717 AddToWorkList(Tmp.Val);
3718 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
3724 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
3725 SDOperand N0 = N->getOperand(0);
3726 MVT::ValueType VT = N->getValueType(0);
3727 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3728 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3730 // fold (fp_round_inreg c1fp) -> c1fp
3732 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT);
3733 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
3738 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
3739 SDOperand N0 = N->getOperand(0);
3740 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3741 MVT::ValueType VT = N->getValueType(0);
3743 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
3744 if (N->hasOneUse() && (*N->use_begin())->getOpcode() == ISD::FP_ROUND)
3747 // fold (fp_extend c1fp) -> c1fp
3748 if (N0CFP && VT != MVT::ppcf128)
3749 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
3751 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
3753 if (N0.getOpcode() == ISD::FP_ROUND && N0.Val->getConstantOperandVal(1) == 1){
3754 SDOperand In = N0.getOperand(0);
3755 if (In.getValueType() == VT) return In;
3756 if (VT < In.getValueType())
3757 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1));
3758 return DAG.getNode(ISD::FP_EXTEND, VT, In);
3761 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
3762 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
3763 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
3764 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3765 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
3766 LN0->getBasePtr(), LN0->getSrcValue(),
3767 LN0->getSrcValueOffset(),
3770 LN0->getAlignment());
3771 CombineTo(N, ExtLoad);
3772 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad,
3773 DAG.getIntPtrConstant(1)),
3774 ExtLoad.getValue(1));
3775 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3782 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
3783 SDOperand N0 = N->getOperand(0);
3785 if (isNegatibleForFree(N0))
3786 return GetNegatedExpression(N0, DAG);
3788 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
3789 // constant pool values.
3790 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse()) {
3791 SDOperand Int = N0.getOperand(0);
3792 MVT::ValueType IntVT = Int.getValueType();
3793 if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) {
3794 Int = DAG.getNode(ISD::XOR, IntVT, Int,
3795 DAG.getConstant(MVT::getIntVTSignBit(IntVT), IntVT));
3796 AddToWorkList(Int.Val);
3797 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int);
3804 SDOperand DAGCombiner::visitFABS(SDNode *N) {
3805 SDOperand N0 = N->getOperand(0);
3806 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3807 MVT::ValueType VT = N->getValueType(0);
3809 // fold (fabs c1) -> fabs(c1)
3810 if (N0CFP && VT != MVT::ppcf128)
3811 return DAG.getNode(ISD::FABS, VT, N0);
3812 // fold (fabs (fabs x)) -> (fabs x)
3813 if (N0.getOpcode() == ISD::FABS)
3814 return N->getOperand(0);
3815 // fold (fabs (fneg x)) -> (fabs x)
3816 // fold (fabs (fcopysign x, y)) -> (fabs x)
3817 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
3818 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
3820 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
3821 // constant pool values.
3822 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse()) {
3823 SDOperand Int = N0.getOperand(0);
3824 MVT::ValueType IntVT = Int.getValueType();
3825 if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) {
3826 Int = DAG.getNode(ISD::AND, IntVT, Int,
3827 DAG.getConstant(~MVT::getIntVTSignBit(IntVT), IntVT));
3828 AddToWorkList(Int.Val);
3829 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int);
3836 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
3837 SDOperand Chain = N->getOperand(0);
3838 SDOperand N1 = N->getOperand(1);
3839 SDOperand N2 = N->getOperand(2);
3840 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3842 // never taken branch, fold to chain
3843 if (N1C && N1C->isNullValue())
3845 // unconditional branch
3846 if (N1C && N1C->getValue() == 1)
3847 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
3848 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
3850 if (N1.getOpcode() == ISD::SETCC &&
3851 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
3852 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
3853 N1.getOperand(0), N1.getOperand(1), N2);
3858 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
3860 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
3861 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
3862 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
3864 // Use SimplifySetCC to simplify SETCC's.
3865 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
3866 if (Simp.Val) AddToWorkList(Simp.Val);
3868 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
3870 // fold br_cc true, dest -> br dest (unconditional branch)
3871 if (SCCC && SCCC->getValue())
3872 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
3874 // fold br_cc false, dest -> unconditional fall through
3875 if (SCCC && SCCC->isNullValue())
3876 return N->getOperand(0);
3878 // fold to a simpler setcc
3879 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
3880 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
3881 Simp.getOperand(2), Simp.getOperand(0),
3882 Simp.getOperand(1), N->getOperand(4));
3887 /// CombineToPreIndexedLoadStore - Try turning a load / store and a
3888 /// pre-indexed load / store when the base pointer is a add or subtract
3889 /// and it has other uses besides the load / store. After the
3890 /// transformation, the new indexed load / store has effectively folded
3891 /// the add / subtract in and all of its other uses are redirected to the
3892 /// new load / store.
3893 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
3900 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3901 if (LD->isIndexed())
3903 VT = LD->getLoadedVT();
3904 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
3905 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
3907 Ptr = LD->getBasePtr();
3908 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3909 if (ST->isIndexed())
3911 VT = ST->getStoredVT();
3912 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
3913 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
3915 Ptr = ST->getBasePtr();
3920 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
3921 // out. There is no reason to make this a preinc/predec.
3922 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
3923 Ptr.Val->hasOneUse())
3926 // Ask the target to do addressing mode selection.
3929 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3930 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
3932 // Don't create a indexed load / store with zero offset.
3933 if (isa<ConstantSDNode>(Offset) &&
3934 cast<ConstantSDNode>(Offset)->getValue() == 0)
3937 // Try turning it into a pre-indexed load / store except when:
3938 // 1) The new base ptr is a frame index.
3939 // 2) If N is a store and the new base ptr is either the same as or is a
3940 // predecessor of the value being stored.
3941 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
3942 // that would create a cycle.
3943 // 4) All uses are load / store ops that use it as old base ptr.
3945 // Check #1. Preinc'ing a frame index would require copying the stack pointer
3946 // (plus the implicit offset) to a register to preinc anyway.
3947 if (isa<FrameIndexSDNode>(BasePtr))
3952 SDOperand Val = cast<StoreSDNode>(N)->getValue();
3953 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val))
3957 // Now check for #3 and #4.
3958 bool RealUse = false;
3959 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3960 E = Ptr.Val->use_end(); I != E; ++I) {
3964 if (Use->isPredecessor(N))
3967 if (!((Use->getOpcode() == ISD::LOAD &&
3968 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
3969 (Use->getOpcode() == ISD::STORE) &&
3970 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))
3978 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM);
3980 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
3983 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
3984 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
3986 std::vector<SDNode*> NowDead;
3988 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
3990 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
3993 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
3997 // Nodes can end up on the worklist more than once. Make sure we do
3998 // not process a node that has been replaced.
3999 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
4000 removeFromWorkList(NowDead[i]);
4001 // Finally, since the node is now dead, remove it from the graph.
4004 // Replace the uses of Ptr with uses of the updated base value.
4005 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
4007 removeFromWorkList(Ptr.Val);
4008 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
4009 removeFromWorkList(NowDead[i]);
4010 DAG.DeleteNode(Ptr.Val);
4015 /// CombineToPostIndexedLoadStore - Try combine a load / store with a
4016 /// add / sub of the base pointer node into a post-indexed load / store.
4017 /// The transformation folded the add / subtract into the new indexed
4018 /// load / store effectively and all of its uses are redirected to the
4019 /// new load / store.
4020 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
4027 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4028 if (LD->isIndexed())
4030 VT = LD->getLoadedVT();
4031 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
4032 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
4034 Ptr = LD->getBasePtr();
4035 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4036 if (ST->isIndexed())
4038 VT = ST->getStoredVT();
4039 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
4040 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
4042 Ptr = ST->getBasePtr();
4047 if (Ptr.Val->hasOneUse())
4050 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
4051 E = Ptr.Val->use_end(); I != E; ++I) {
4054 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
4059 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4060 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
4062 std::swap(BasePtr, Offset);
4065 // Don't create a indexed load / store with zero offset.
4066 if (isa<ConstantSDNode>(Offset) &&
4067 cast<ConstantSDNode>(Offset)->getValue() == 0)
4070 // Try turning it into a post-indexed load / store except when
4071 // 1) All uses are load / store ops that use it as base ptr.
4072 // 2) Op must be independent of N, i.e. Op is neither a predecessor
4073 // nor a successor of N. Otherwise, if Op is folded that would
4077 bool TryNext = false;
4078 for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
4079 EE = BasePtr.Val->use_end(); II != EE; ++II) {
4084 // If all the uses are load / store addresses, then don't do the
4086 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
4087 bool RealUse = false;
4088 for (SDNode::use_iterator III = Use->use_begin(),
4089 EEE = Use->use_end(); III != EEE; ++III) {
4090 SDNode *UseUse = *III;
4091 if (!((UseUse->getOpcode() == ISD::LOAD &&
4092 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
4093 (UseUse->getOpcode() == ISD::STORE) &&
4094 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))
4108 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) {
4109 SDOperand Result = isLoad
4110 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
4111 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
4114 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
4115 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
4117 std::vector<SDNode*> NowDead;
4119 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
4121 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
4124 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
4128 // Nodes can end up on the worklist more than once. Make sure we do
4129 // not process a node that has been replaced.
4130 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
4131 removeFromWorkList(NowDead[i]);
4132 // Finally, since the node is now dead, remove it from the graph.
4135 // Replace the uses of Use with uses of the updated base value.
4136 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0),
4137 Result.getValue(isLoad ? 1 : 0),
4139 removeFromWorkList(Op);
4140 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
4141 removeFromWorkList(NowDead[i]);
4151 /// InferAlignment - If we can infer some alignment information from this
4152 /// pointer, return it.
4153 static unsigned InferAlignment(SDOperand Ptr, SelectionDAG &DAG) {
4154 // If this is a direct reference to a stack slot, use information about the
4155 // stack slot's alignment.
4156 int FrameIdx = 1 << 31;
4157 int64_t FrameOffset = 0;
4158 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) {
4159 FrameIdx = FI->getIndex();
4160 } else if (Ptr.getOpcode() == ISD::ADD &&
4161 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
4162 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4163 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4164 FrameOffset = Ptr.getConstantOperandVal(1);
4167 if (FrameIdx != (1 << 31)) {
4168 // FIXME: Handle FI+CST.
4169 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo();
4170 if (MFI.isFixedObjectIndex(FrameIdx)) {
4171 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx);
4173 // The alignment of the frame index can be determined from its offset from
4174 // the incoming frame position. If the frame object is at offset 32 and
4175 // the stack is guaranteed to be 16-byte aligned, then we know that the
4176 // object is 16-byte aligned.
4177 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment();
4178 unsigned Align = MinAlign(ObjectOffset, StackAlign);
4180 // Finally, the frame object itself may have a known alignment. Factor
4181 // the alignment + offset into a new alignment. For example, if we know
4182 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a
4183 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte
4184 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc.
4185 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx),
4187 return std::max(Align, FIInfoAlign);
4194 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
4195 LoadSDNode *LD = cast<LoadSDNode>(N);
4196 SDOperand Chain = LD->getChain();
4197 SDOperand Ptr = LD->getBasePtr();
4199 // Try to infer better alignment information than the load already has.
4200 if (LD->isUnindexed()) {
4201 if (unsigned Align = InferAlignment(Ptr, DAG)) {
4202 if (Align > LD->getAlignment())
4203 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0),
4204 Chain, Ptr, LD->getSrcValue(),
4205 LD->getSrcValueOffset(), LD->getLoadedVT(),
4206 LD->isVolatile(), Align);
4211 // If load is not volatile and there are no uses of the loaded value (and
4212 // the updated indexed value in case of indexed loads), change uses of the
4213 // chain value into uses of the chain input (i.e. delete the dead load).
4214 if (!LD->isVolatile()) {
4215 if (N->getValueType(1) == MVT::Other) {
4217 if (N->hasNUsesOfValue(0, 0)) {
4218 // It's not safe to use the two value CombineTo variant here. e.g.
4219 // v1, chain2 = load chain1, loc
4220 // v2, chain3 = load chain2, loc
4222 // Now we replace use of chain2 with chain1. This makes the second load
4223 // isomorphic to the one we are deleting, and thus makes this load live.
4224 std::vector<SDNode*> NowDead;
4225 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4226 DOUT << "\nWith chain: "; DEBUG(Chain.Val->dump(&DAG));
4228 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Chain, &NowDead);
4229 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
4230 removeFromWorkList(NowDead[i]);
4231 if (N->use_empty()) {
4232 removeFromWorkList(N);
4235 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
4239 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
4240 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
4241 std::vector<SDNode*> NowDead;
4242 SDOperand Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0));
4243 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4244 DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG));
4245 DOUT << " and 2 other values\n";
4246 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Undef, &NowDead);
4247 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1),
4248 DAG.getNode(ISD::UNDEF, N->getValueType(1)),
4250 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 2), Chain, &NowDead);
4251 removeFromWorkList(N);
4252 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
4253 removeFromWorkList(NowDead[i]);
4255 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
4260 // If this load is directly stored, replace the load value with the stored
4262 // TODO: Handle store large -> read small portion.
4263 // TODO: Handle TRUNCSTORE/LOADEXT
4264 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
4265 if (ISD::isNON_TRUNCStore(Chain.Val)) {
4266 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
4267 if (PrevST->getBasePtr() == Ptr &&
4268 PrevST->getValue().getValueType() == N->getValueType(0))
4269 return CombineTo(N, Chain.getOperand(1), Chain);
4274 // Walk up chain skipping non-aliasing memory nodes.
4275 SDOperand BetterChain = FindBetterChain(N, Chain);
4277 // If there is a better chain.
4278 if (Chain != BetterChain) {
4281 // Replace the chain to void dependency.
4282 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
4283 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
4284 LD->getSrcValue(), LD->getSrcValueOffset(),
4285 LD->isVolatile(), LD->getAlignment());
4287 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
4288 LD->getValueType(0),
4289 BetterChain, Ptr, LD->getSrcValue(),
4290 LD->getSrcValueOffset(),
4293 LD->getAlignment());
4296 // Create token factor to keep old chain connected.
4297 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
4298 Chain, ReplLoad.getValue(1));
4300 // Replace uses with load result and token factor. Don't add users
4302 return CombineTo(N, ReplLoad.getValue(0), Token, false);
4306 // Try transforming N to an indexed load.
4307 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4308 return SDOperand(N, 0);
4314 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
4315 StoreSDNode *ST = cast<StoreSDNode>(N);
4316 SDOperand Chain = ST->getChain();
4317 SDOperand Value = ST->getValue();
4318 SDOperand Ptr = ST->getBasePtr();
4320 // Try to infer better alignment information than the store already has.
4321 if (ST->isUnindexed()) {
4322 if (unsigned Align = InferAlignment(Ptr, DAG)) {
4323 if (Align > ST->getAlignment())
4324 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(),
4325 ST->getSrcValueOffset(), ST->getStoredVT(),
4326 ST->isVolatile(), Align);
4330 // If this is a store of a bit convert, store the input value if the
4331 // resultant store does not need a higher alignment than the original.
4332 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
4333 ST->isUnindexed()) {
4334 unsigned Align = ST->getAlignment();
4335 MVT::ValueType SVT = Value.getOperand(0).getValueType();
4336 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
4337 getABITypeAlignment(MVT::getTypeForValueType(SVT));
4338 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT))
4339 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
4340 ST->getSrcValueOffset(), ST->isVolatile(), Align);
4343 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
4344 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
4345 if (Value.getOpcode() != ISD::TargetConstantFP) {
4347 switch (CFP->getValueType(0)) {
4348 default: assert(0 && "Unknown FP type");
4349 case MVT::f80: // We don't do this for these yet.
4354 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) {
4355 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
4356 convertToAPInt().getZExtValue(), MVT::i32);
4357 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
4358 ST->getSrcValueOffset(), ST->isVolatile(),
4359 ST->getAlignment());
4363 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) {
4364 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
4365 getZExtValue(), MVT::i64);
4366 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
4367 ST->getSrcValueOffset(), ST->isVolatile(),
4368 ST->getAlignment());
4369 } else if (TLI.isTypeLegal(MVT::i32)) {
4370 // Many FP stores are not made apparent until after legalize, e.g. for
4371 // argument passing. Since this is so common, custom legalize the
4372 // 64-bit integer store into two 32-bit stores.
4373 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue();
4374 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
4375 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32);
4376 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
4378 int SVOffset = ST->getSrcValueOffset();
4379 unsigned Alignment = ST->getAlignment();
4380 bool isVolatile = ST->isVolatile();
4382 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(),
4383 ST->getSrcValueOffset(),
4384 isVolatile, ST->getAlignment());
4385 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4386 DAG.getConstant(4, Ptr.getValueType()));
4388 Alignment = MinAlign(Alignment, 4U);
4389 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(),
4390 SVOffset, isVolatile, Alignment);
4391 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1);
4399 // Walk up chain skipping non-aliasing memory nodes.
4400 SDOperand BetterChain = FindBetterChain(N, Chain);
4402 // If there is a better chain.
4403 if (Chain != BetterChain) {
4404 // Replace the chain to avoid dependency.
4405 SDOperand ReplStore;
4406 if (ST->isTruncatingStore()) {
4407 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
4408 ST->getSrcValue(),ST->getSrcValueOffset(),
4410 ST->isVolatile(), ST->getAlignment());
4412 ReplStore = DAG.getStore(BetterChain, Value, Ptr,
4413 ST->getSrcValue(), ST->getSrcValueOffset(),
4414 ST->isVolatile(), ST->getAlignment());
4417 // Create token to keep both nodes around.
4419 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
4421 // Don't add users to work list.
4422 return CombineTo(N, Token, false);
4426 // Try transforming N to an indexed store.
4427 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4428 return SDOperand(N, 0);
4430 // FIXME: is there such a thing as a truncating indexed store?
4431 if (ST->isTruncatingStore() && ST->isUnindexed() &&
4432 MVT::isInteger(Value.getValueType())) {
4433 // See if we can simplify the input to this truncstore with knowledge that
4434 // only the low bits are being used. For example:
4435 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
4437 GetDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT()));
4438 AddToWorkList(Value.Val);
4440 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(),
4441 ST->getSrcValueOffset(), ST->getStoredVT(),
4442 ST->isVolatile(), ST->getAlignment());
4444 // Otherwise, see if we can simplify the operation with
4445 // SimplifyDemandedBits, which only works if the value has a single use.
4446 if (SimplifyDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT())))
4447 return SDOperand(N, 0);
4450 // If this is a load followed by a store to the same location, then the store
4452 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
4453 if (Ld->getBasePtr() == Ptr && ST->getStoredVT() == Ld->getLoadedVT() &&
4454 ST->isUnindexed() && !ST->isVolatile() &&
4455 // There can't be any side effects between the load and store, such as
4457 Chain.reachesChainWithoutSideEffects(SDOperand(Ld, 1))) {
4458 // The store is dead, remove it.
4463 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
4464 // truncating store. We can do this even if this is already a truncstore.
4465 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
4466 && TLI.isTypeLegal(Value.getOperand(0).getValueType()) &&
4467 Value.Val->hasOneUse() && ST->isUnindexed() &&
4468 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
4469 ST->getStoredVT())) {
4470 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
4471 ST->getSrcValueOffset(), ST->getStoredVT(),
4472 ST->isVolatile(), ST->getAlignment());
4478 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
4479 SDOperand InVec = N->getOperand(0);
4480 SDOperand InVal = N->getOperand(1);
4481 SDOperand EltNo = N->getOperand(2);
4483 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
4484 // vector with the inserted element.
4485 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
4486 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
4487 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
4488 if (Elt < Ops.size())
4490 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
4491 &Ops[0], Ops.size());
4497 SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
4498 SDOperand InVec = N->getOperand(0);
4499 SDOperand EltNo = N->getOperand(1);
4501 // (vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr)
4502 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr)
4503 if (isa<ConstantSDNode>(EltNo)) {
4504 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
4505 bool NewLoad = false;
4507 MVT::ValueType VT = InVec.getValueType();
4508 MVT::ValueType EVT = MVT::getVectorElementType(VT);
4509 MVT::ValueType LVT = EVT;
4510 unsigned NumElts = MVT::getVectorNumElements(VT);
4511 if (InVec.getOpcode() == ISD::BIT_CONVERT) {
4512 MVT::ValueType BCVT = InVec.getOperand(0).getValueType();
4513 if (!MVT::isVector(BCVT) ||
4514 NumElts != MVT::getVectorNumElements(BCVT))
4516 InVec = InVec.getOperand(0);
4517 EVT = MVT::getVectorElementType(BCVT);
4520 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4521 InVec.getOperand(0).getValueType() == EVT &&
4522 ISD::isNormalLoad(InVec.getOperand(0).Val) &&
4523 InVec.getOperand(0).hasOneUse()) {
4524 LoadSDNode *LN0 = cast<LoadSDNode>(InVec.getOperand(0));
4525 unsigned Align = LN0->getAlignment();
4527 // Check the resultant load doesn't need a higher alignment than the
4529 unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
4530 getABITypeAlignment(MVT::getTypeForValueType(LVT));
4531 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align)
4536 return DAG.getLoad(LVT, LN0->getChain(), LN0->getBasePtr(),
4537 LN0->getSrcValue(), LN0->getSrcValueOffset(),
4538 LN0->isVolatile(), Align);
4546 SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
4547 unsigned NumInScalars = N->getNumOperands();
4548 MVT::ValueType VT = N->getValueType(0);
4549 unsigned NumElts = MVT::getVectorNumElements(VT);
4550 MVT::ValueType EltType = MVT::getVectorElementType(VT);
4552 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
4553 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
4554 // at most two distinct vectors, turn this into a shuffle node.
4555 SDOperand VecIn1, VecIn2;
4556 for (unsigned i = 0; i != NumInScalars; ++i) {
4557 // Ignore undef inputs.
4558 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4560 // If this input is something other than a EXTRACT_VECTOR_ELT with a
4561 // constant index, bail out.
4562 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4563 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
4564 VecIn1 = VecIn2 = SDOperand(0, 0);
4568 // If the input vector type disagrees with the result of the build_vector,
4569 // we can't make a shuffle.
4570 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
4571 if (ExtractedFromVec.getValueType() != VT) {
4572 VecIn1 = VecIn2 = SDOperand(0, 0);
4576 // Otherwise, remember this. We allow up to two distinct input vectors.
4577 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
4580 if (VecIn1.Val == 0) {
4581 VecIn1 = ExtractedFromVec;
4582 } else if (VecIn2.Val == 0) {
4583 VecIn2 = ExtractedFromVec;
4586 VecIn1 = VecIn2 = SDOperand(0, 0);
4591 // If everything is good, we can make a shuffle operation.
4593 SmallVector<SDOperand, 8> BuildVecIndices;
4594 for (unsigned i = 0; i != NumInScalars; ++i) {
4595 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
4596 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy()));
4600 SDOperand Extract = N->getOperand(i);
4602 // If extracting from the first vector, just use the index directly.
4603 if (Extract.getOperand(0) == VecIn1) {
4604 BuildVecIndices.push_back(Extract.getOperand(1));
4608 // Otherwise, use InIdx + VecSize
4609 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
4610 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars));
4613 // Add count and size info.
4614 MVT::ValueType BuildVecVT = MVT::getVectorType(TLI.getPointerTy(), NumElts);
4616 // Return the new VECTOR_SHUFFLE node.
4622 // Use an undef build_vector as input for the second operand.
4623 std::vector<SDOperand> UnOps(NumInScalars,
4624 DAG.getNode(ISD::UNDEF,
4626 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT,
4627 &UnOps[0], UnOps.size());
4628 AddToWorkList(Ops[1].Val);
4630 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT,
4631 &BuildVecIndices[0], BuildVecIndices.size());
4632 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3);
4638 SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
4639 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
4640 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
4641 // inputs come from at most two distinct vectors, turn this into a shuffle
4644 // If we only have one input vector, we don't need to do any concatenation.
4645 if (N->getNumOperands() == 1) {
4646 return N->getOperand(0);
4652 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
4653 SDOperand ShufMask = N->getOperand(2);
4654 unsigned NumElts = ShufMask.getNumOperands();
4656 // If the shuffle mask is an identity operation on the LHS, return the LHS.
4657 bool isIdentity = true;
4658 for (unsigned i = 0; i != NumElts; ++i) {
4659 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4660 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
4665 if (isIdentity) return N->getOperand(0);
4667 // If the shuffle mask is an identity operation on the RHS, return the RHS.
4669 for (unsigned i = 0; i != NumElts; ++i) {
4670 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4671 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
4676 if (isIdentity) return N->getOperand(1);
4678 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
4680 bool isUnary = true;
4681 bool isSplat = true;
4683 unsigned BaseIdx = 0;
4684 for (unsigned i = 0; i != NumElts; ++i)
4685 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
4686 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
4687 int V = (Idx < NumElts) ? 0 : 1;
4701 SDOperand N0 = N->getOperand(0);
4702 SDOperand N1 = N->getOperand(1);
4703 // Normalize unary shuffle so the RHS is undef.
4704 if (isUnary && VecNum == 1)
4707 // If it is a splat, check if the argument vector is a build_vector with
4708 // all scalar elements the same.
4712 // If this is a bit convert that changes the element type of the vector but
4713 // not the number of vector elements, look through it. Be careful not to
4714 // look though conversions that change things like v4f32 to v2f64.
4715 if (V->getOpcode() == ISD::BIT_CONVERT) {
4716 SDOperand ConvInput = V->getOperand(0);
4717 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts)
4721 if (V->getOpcode() == ISD::BUILD_VECTOR) {
4722 unsigned NumElems = V->getNumOperands();
4723 if (NumElems > BaseIdx) {
4725 bool AllSame = true;
4726 for (unsigned i = 0; i != NumElems; ++i) {
4727 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
4728 Base = V->getOperand(i);
4732 // Splat of <u, u, u, u>, return <u, u, u, u>
4735 for (unsigned i = 0; i != NumElems; ++i) {
4736 if (V->getOperand(i) != Base) {
4741 // Splat of <x, x, x, x>, return <x, x, x, x>
4748 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
4750 if (isUnary || N0 == N1) {
4751 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
4753 SmallVector<SDOperand, 8> MappedOps;
4754 for (unsigned i = 0; i != NumElts; ++i) {
4755 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
4756 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
4757 MappedOps.push_back(ShufMask.getOperand(i));
4760 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
4761 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
4764 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
4765 &MappedOps[0], MappedOps.size());
4766 AddToWorkList(ShufMask.Val);
4767 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
4769 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
4776 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
4777 /// an AND to a vector_shuffle with the destination vector and a zero vector.
4778 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
4779 /// vector_shuffle V, Zero, <0, 4, 2, 4>
4780 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
4781 SDOperand LHS = N->getOperand(0);
4782 SDOperand RHS = N->getOperand(1);
4783 if (N->getOpcode() == ISD::AND) {
4784 if (RHS.getOpcode() == ISD::BIT_CONVERT)
4785 RHS = RHS.getOperand(0);
4786 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
4787 std::vector<SDOperand> IdxOps;
4788 unsigned NumOps = RHS.getNumOperands();
4789 unsigned NumElts = NumOps;
4790 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType());
4791 for (unsigned i = 0; i != NumElts; ++i) {
4792 SDOperand Elt = RHS.getOperand(i);
4793 if (!isa<ConstantSDNode>(Elt))
4795 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
4796 IdxOps.push_back(DAG.getConstant(i, EVT));
4797 else if (cast<ConstantSDNode>(Elt)->isNullValue())
4798 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
4803 // Let's see if the target supports this vector_shuffle.
4804 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
4807 // Return the new VECTOR_SHUFFLE node.
4808 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts);
4809 std::vector<SDOperand> Ops;
4810 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS);
4812 AddToWorkList(LHS.Val);
4813 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
4814 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
4815 &ZeroOps[0], ZeroOps.size()));
4816 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
4817 &IdxOps[0], IdxOps.size()));
4818 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT,
4819 &Ops[0], Ops.size());
4820 if (VT != LHS.getValueType()) {
4821 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result);
4829 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
4830 SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) {
4831 // After legalize, the target may be depending on adds and other
4832 // binary ops to provide legal ways to construct constants or other
4833 // things. Simplifying them may result in a loss of legality.
4834 if (AfterLegalize) return SDOperand();
4836 MVT::ValueType VT = N->getValueType(0);
4837 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!");
4839 MVT::ValueType EltType = MVT::getVectorElementType(VT);
4840 SDOperand LHS = N->getOperand(0);
4841 SDOperand RHS = N->getOperand(1);
4842 SDOperand Shuffle = XformToShuffleWithZero(N);
4843 if (Shuffle.Val) return Shuffle;
4845 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
4847 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
4848 RHS.getOpcode() == ISD::BUILD_VECTOR) {
4849 SmallVector<SDOperand, 8> Ops;
4850 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
4851 SDOperand LHSOp = LHS.getOperand(i);
4852 SDOperand RHSOp = RHS.getOperand(i);
4853 // If these two elements can't be folded, bail out.
4854 if ((LHSOp.getOpcode() != ISD::UNDEF &&
4855 LHSOp.getOpcode() != ISD::Constant &&
4856 LHSOp.getOpcode() != ISD::ConstantFP) ||
4857 (RHSOp.getOpcode() != ISD::UNDEF &&
4858 RHSOp.getOpcode() != ISD::Constant &&
4859 RHSOp.getOpcode() != ISD::ConstantFP))
4861 // Can't fold divide by zero.
4862 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
4863 N->getOpcode() == ISD::FDIV) {
4864 if ((RHSOp.getOpcode() == ISD::Constant &&
4865 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
4866 (RHSOp.getOpcode() == ISD::ConstantFP &&
4867 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero()))
4870 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp));
4871 AddToWorkList(Ops.back().Val);
4872 assert((Ops.back().getOpcode() == ISD::UNDEF ||
4873 Ops.back().getOpcode() == ISD::Constant ||
4874 Ops.back().getOpcode() == ISD::ConstantFP) &&
4875 "Scalar binop didn't fold!");
4878 if (Ops.size() == LHS.getNumOperands()) {
4879 MVT::ValueType VT = LHS.getValueType();
4880 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
4887 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
4888 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
4890 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
4891 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4892 // If we got a simplified select_cc node back from SimplifySelectCC, then
4893 // break it down into a new SETCC node, and a new SELECT node, and then return
4894 // the SELECT node, since we were called with a SELECT node.
4896 // Check to see if we got a select_cc back (to turn into setcc/select).
4897 // Otherwise, just return whatever node we got back, like fabs.
4898 if (SCC.getOpcode() == ISD::SELECT_CC) {
4899 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
4900 SCC.getOperand(0), SCC.getOperand(1),
4902 AddToWorkList(SETCC.Val);
4903 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
4904 SCC.getOperand(3), SETCC);
4911 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
4912 /// are the two values being selected between, see if we can simplify the
4913 /// select. Callers of this should assume that TheSelect is deleted if this
4914 /// returns true. As such, they should return the appropriate thing (e.g. the
4915 /// node) back to the top-level of the DAG combiner loop to avoid it being
4918 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
4921 // If this is a select from two identical things, try to pull the operation
4922 // through the select.
4923 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
4924 // If this is a load and the token chain is identical, replace the select
4925 // of two loads with a load through a select of the address to load from.
4926 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
4927 // constants have been dropped into the constant pool.
4928 if (LHS.getOpcode() == ISD::LOAD &&
4929 // Token chains must be identical.
4930 LHS.getOperand(0) == RHS.getOperand(0)) {
4931 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
4932 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
4934 // If this is an EXTLOAD, the VT's must match.
4935 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
4936 // FIXME: this conflates two src values, discarding one. This is not
4937 // the right thing to do, but nothing uses srcvalues now. When they do,
4938 // turn SrcValue into a list of locations.
4940 if (TheSelect->getOpcode() == ISD::SELECT) {
4941 // Check that the condition doesn't reach either load. If so, folding
4942 // this will induce a cycle into the DAG.
4943 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4944 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) {
4945 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
4946 TheSelect->getOperand(0), LLD->getBasePtr(),
4950 // Check that the condition doesn't reach either load. If so, folding
4951 // this will induce a cycle into the DAG.
4952 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4953 !RLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4954 !LLD->isPredecessor(TheSelect->getOperand(1).Val) &&
4955 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) {
4956 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
4957 TheSelect->getOperand(0),
4958 TheSelect->getOperand(1),
4959 LLD->getBasePtr(), RLD->getBasePtr(),
4960 TheSelect->getOperand(4));
4966 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
4967 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
4968 Addr,LLD->getSrcValue(),
4969 LLD->getSrcValueOffset(),
4971 LLD->getAlignment());
4973 Load = DAG.getExtLoad(LLD->getExtensionType(),
4974 TheSelect->getValueType(0),
4975 LLD->getChain(), Addr, LLD->getSrcValue(),
4976 LLD->getSrcValueOffset(),
4979 LLD->getAlignment());
4981 // Users of the select now use the result of the load.
4982 CombineTo(TheSelect, Load);
4984 // Users of the old loads now use the new load's chain. We know the
4985 // old-load value is dead now.
4986 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
4987 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
4997 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
4998 SDOperand N2, SDOperand N3,
4999 ISD::CondCode CC, bool NotExtCompare) {
5001 MVT::ValueType VT = N2.getValueType();
5002 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
5003 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
5004 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
5006 // Determine if the condition we're dealing with is constant
5007 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
5008 if (SCC.Val) AddToWorkList(SCC.Val);
5009 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
5011 // fold select_cc true, x, y -> x
5012 if (SCCC && SCCC->getValue())
5014 // fold select_cc false, x, y -> y
5015 if (SCCC && SCCC->getValue() == 0)
5018 // Check to see if we can simplify the select into an fabs node
5019 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
5020 // Allow either -0.0 or 0.0
5021 if (CFP->getValueAPF().isZero()) {
5022 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
5023 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
5024 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
5025 N2 == N3.getOperand(0))
5026 return DAG.getNode(ISD::FABS, VT, N0);
5028 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
5029 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
5030 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
5031 N2.getOperand(0) == N3)
5032 return DAG.getNode(ISD::FABS, VT, N3);
5036 // Check to see if we can perform the "gzip trick", transforming
5037 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
5038 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
5039 MVT::isInteger(N0.getValueType()) &&
5040 MVT::isInteger(N2.getValueType()) &&
5041 (N1C->isNullValue() || // (a < 0) ? b : 0
5042 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
5043 MVT::ValueType XType = N0.getValueType();
5044 MVT::ValueType AType = N2.getValueType();
5045 if (XType >= AType) {
5046 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
5047 // single-bit constant.
5048 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
5049 unsigned ShCtV = Log2_64(N2C->getValue());
5050 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
5051 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
5052 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
5053 AddToWorkList(Shift.Val);
5054 if (XType > AType) {
5055 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
5056 AddToWorkList(Shift.Val);
5058 return DAG.getNode(ISD::AND, AType, Shift, N2);
5060 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
5061 DAG.getConstant(MVT::getSizeInBits(XType)-1,
5062 TLI.getShiftAmountTy()));
5063 AddToWorkList(Shift.Val);
5064 if (XType > AType) {
5065 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
5066 AddToWorkList(Shift.Val);
5068 return DAG.getNode(ISD::AND, AType, Shift, N2);
5072 // fold select C, 16, 0 -> shl C, 4
5073 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
5074 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
5076 // If the caller doesn't want us to simplify this into a zext of a compare,
5078 if (NotExtCompare && N2C->getValue() == 1)
5081 // Get a SetCC of the condition
5082 // FIXME: Should probably make sure that setcc is legal if we ever have a
5083 // target where it isn't.
5084 SDOperand Temp, SCC;
5085 // cast from setcc result type to select result type
5086 if (AfterLegalize) {
5087 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
5088 if (N2.getValueType() < SCC.getValueType())
5089 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
5091 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
5093 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
5094 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
5096 AddToWorkList(SCC.Val);
5097 AddToWorkList(Temp.Val);
5099 if (N2C->getValue() == 1)
5101 // shl setcc result by log2 n2c
5102 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
5103 DAG.getConstant(Log2_64(N2C->getValue()),
5104 TLI.getShiftAmountTy()));
5107 // Check to see if this is the equivalent of setcc
5108 // FIXME: Turn all of these into setcc if setcc if setcc is legal
5109 // otherwise, go ahead with the folds.
5110 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
5111 MVT::ValueType XType = N0.getValueType();
5112 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
5113 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
5114 if (Res.getValueType() != VT)
5115 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
5119 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
5120 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
5121 TLI.isOperationLegal(ISD::CTLZ, XType)) {
5122 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
5123 return DAG.getNode(ISD::SRL, XType, Ctlz,
5124 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
5125 TLI.getShiftAmountTy()));
5127 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
5128 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
5129 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
5131 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
5132 DAG.getConstant(~0ULL, XType));
5133 return DAG.getNode(ISD::SRL, XType,
5134 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
5135 DAG.getConstant(MVT::getSizeInBits(XType)-1,
5136 TLI.getShiftAmountTy()));
5138 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
5139 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
5140 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
5141 DAG.getConstant(MVT::getSizeInBits(XType)-1,
5142 TLI.getShiftAmountTy()));
5143 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
5147 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
5148 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5149 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
5150 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
5151 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) {
5152 MVT::ValueType XType = N0.getValueType();
5153 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
5154 DAG.getConstant(MVT::getSizeInBits(XType)-1,
5155 TLI.getShiftAmountTy()));
5156 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
5157 AddToWorkList(Shift.Val);
5158 AddToWorkList(Add.Val);
5159 return DAG.getNode(ISD::XOR, XType, Add, Shift);
5161 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
5162 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5163 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
5164 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
5165 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
5166 MVT::ValueType XType = N0.getValueType();
5167 if (SubC->isNullValue() && MVT::isInteger(XType)) {
5168 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
5169 DAG.getConstant(MVT::getSizeInBits(XType)-1,
5170 TLI.getShiftAmountTy()));
5171 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
5172 AddToWorkList(Shift.Val);
5173 AddToWorkList(Add.Val);
5174 return DAG.getNode(ISD::XOR, XType, Add, Shift);
5182 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
5183 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
5184 SDOperand N1, ISD::CondCode Cond,
5185 bool foldBooleans) {
5186 TargetLowering::DAGCombinerInfo
5187 DagCombineInfo(DAG, !AfterLegalize, false, this);
5188 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo);
5191 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
5192 /// return a DAG expression to select that will generate the same value by
5193 /// multiplying by a magic number. See:
5194 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
5195 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
5196 std::vector<SDNode*> Built;
5197 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
5199 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
5205 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
5206 /// return a DAG expression to select that will generate the same value by
5207 /// multiplying by a magic number. See:
5208 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
5209 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
5210 std::vector<SDNode*> Built;
5211 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
5213 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
5219 /// FindBaseOffset - Return true if base is known not to alias with anything
5220 /// but itself. Provides base object and offset as results.
5221 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
5222 // Assume it is a primitive operation.
5223 Base = Ptr; Offset = 0;
5225 // If it's an adding a simple constant then integrate the offset.
5226 if (Base.getOpcode() == ISD::ADD) {
5227 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
5228 Base = Base.getOperand(0);
5229 Offset += C->getValue();
5233 // If it's any of the following then it can't alias with anything but itself.
5234 return isa<FrameIndexSDNode>(Base) ||
5235 isa<ConstantPoolSDNode>(Base) ||
5236 isa<GlobalAddressSDNode>(Base);
5239 /// isAlias - Return true if there is any possibility that the two addresses
5241 bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1,
5242 const Value *SrcValue1, int SrcValueOffset1,
5243 SDOperand Ptr2, int64_t Size2,
5244 const Value *SrcValue2, int SrcValueOffset2)
5246 // If they are the same then they must be aliases.
5247 if (Ptr1 == Ptr2) return true;
5249 // Gather base node and offset information.
5250 SDOperand Base1, Base2;
5251 int64_t Offset1, Offset2;
5252 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
5253 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
5255 // If they have a same base address then...
5256 if (Base1 == Base2) {
5257 // Check to see if the addresses overlap.
5258 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
5261 // If we know both bases then they can't alias.
5262 if (KnownBase1 && KnownBase2) return false;
5264 if (CombinerGlobalAA) {
5265 // Use alias analysis information.
5266 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
5267 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
5268 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
5269 AliasAnalysis::AliasResult AAResult =
5270 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
5271 if (AAResult == AliasAnalysis::NoAlias)
5275 // Otherwise we have to assume they alias.
5279 /// FindAliasInfo - Extracts the relevant alias information from the memory
5280 /// node. Returns true if the operand was a load.
5281 bool DAGCombiner::FindAliasInfo(SDNode *N,
5282 SDOperand &Ptr, int64_t &Size,
5283 const Value *&SrcValue, int &SrcValueOffset) {
5284 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5285 Ptr = LD->getBasePtr();
5286 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3;
5287 SrcValue = LD->getSrcValue();
5288 SrcValueOffset = LD->getSrcValueOffset();
5290 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5291 Ptr = ST->getBasePtr();
5292 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3;
5293 SrcValue = ST->getSrcValue();
5294 SrcValueOffset = ST->getSrcValueOffset();
5296 assert(0 && "FindAliasInfo expected a memory operand");
5302 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
5303 /// looking for aliasing nodes and adding them to the Aliases vector.
5304 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
5305 SmallVector<SDOperand, 8> &Aliases) {
5306 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
5307 std::set<SDNode *> Visited; // Visited node set.
5309 // Get alias information for node.
5312 const Value *SrcValue;
5314 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
5317 Chains.push_back(OriginalChain);
5319 // Look at each chain and determine if it is an alias. If so, add it to the
5320 // aliases list. If not, then continue up the chain looking for the next
5322 while (!Chains.empty()) {
5323 SDOperand Chain = Chains.back();
5326 // Don't bother if we've been before.
5327 if (Visited.find(Chain.Val) != Visited.end()) continue;
5328 Visited.insert(Chain.Val);
5330 switch (Chain.getOpcode()) {
5331 case ISD::EntryToken:
5332 // Entry token is ideal chain operand, but handled in FindBetterChain.
5337 // Get alias information for Chain.
5340 const Value *OpSrcValue;
5341 int OpSrcValueOffset;
5342 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
5343 OpSrcValue, OpSrcValueOffset);
5345 // If chain is alias then stop here.
5346 if (!(IsLoad && IsOpLoad) &&
5347 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
5348 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
5349 Aliases.push_back(Chain);
5351 // Look further up the chain.
5352 Chains.push_back(Chain.getOperand(0));
5353 // Clean up old chain.
5354 AddToWorkList(Chain.Val);
5359 case ISD::TokenFactor:
5360 // We have to check each of the operands of the token factor, so we queue
5361 // then up. Adding the operands to the queue (stack) in reverse order
5362 // maintains the original order and increases the likelihood that getNode
5363 // will find a matching token factor (CSE.)
5364 for (unsigned n = Chain.getNumOperands(); n;)
5365 Chains.push_back(Chain.getOperand(--n));
5366 // Eliminate the token factor if we can.
5367 AddToWorkList(Chain.Val);
5371 // For all other instructions we will just have to take what we can get.
5372 Aliases.push_back(Chain);
5378 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
5379 /// for a better chain (aliasing node.)
5380 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
5381 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
5383 // Accumulate all the aliases to this node.
5384 GatherAllAliases(N, OldChain, Aliases);
5386 if (Aliases.size() == 0) {
5387 // If no operands then chain to entry token.
5388 return DAG.getEntryNode();
5389 } else if (Aliases.size() == 1) {
5390 // If a single operand then chain to it. We don't need to revisit it.
5394 // Construct a custom tailored token factor.
5395 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5396 &Aliases[0], Aliases.size());
5398 // Make sure the old chain gets cleaned up.
5399 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
5404 // SelectionDAG::Combine - This is the entry point for the file.
5406 void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
5407 if (!RunningAfterLegalize && ViewDAGCombine1)
5409 if (RunningAfterLegalize && ViewDAGCombine2)
5411 /// run - This is the main entry point to this class.
5413 DAGCombiner(*this, AA).Run(RunningAfterLegalize);