1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Analysis/AliasAnalysis.h"
27 #include "llvm/Target/TargetData.h"
28 #include "llvm/Target/TargetFrameInfo.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/ADT/SmallPtrSet.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
42 STATISTIC(NodesCombined , "Number of dag nodes combined");
43 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
44 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
45 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
49 CombinerAA("combiner-alias-analysis", cl::Hidden,
50 cl::desc("Turn on alias analysis during testing"));
53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
54 cl::desc("Include global information in alias analysis"));
56 //------------------------------ DAGCombiner ---------------------------------//
60 const TargetLowering &TLI;
62 CodeGenOpt::Level OptLevel;
66 // Worklist of all of the nodes that need to be simplified.
67 std::vector<SDNode*> WorkList;
69 // AA - Used for DAG load/store alias analysis.
72 /// AddUsersToWorkList - When an instruction is simplified, add all users of
73 /// the instruction to the work lists because they might get more simplified
76 void AddUsersToWorkList(SDNode *N) {
77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
82 /// visit - call the node-specific routine that knows how to fold each
83 /// particular type of node.
84 SDValue visit(SDNode *N);
87 /// AddToWorkList - Add to the work list making sure it's instance is at the
88 /// the back (next to be processed.)
89 void AddToWorkList(SDNode *N) {
90 removeFromWorkList(N);
91 WorkList.push_back(N);
94 /// removeFromWorkList - remove all instances of N from the worklist.
96 void removeFromWorkList(SDNode *N) {
97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
105 return CombineTo(N, &Res, 1, AddTo);
108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
110 SDValue To[] = { Res0, Res1 };
111 return CombineTo(N, To, 2, AddTo);
114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
118 /// SimplifyDemandedBits - Check the specified integer node value to see if
119 /// it can be simplified or if things it uses can be simplified by bit
120 /// propagation. If so, return true.
121 bool SimplifyDemandedBits(SDValue Op) {
122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
123 APInt Demanded = APInt::getAllOnesValue(BitWidth);
124 return SimplifyDemandedBits(Op, Demanded);
127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
129 bool CombineToPreIndexedLoadStore(SDNode *N);
130 bool CombineToPostIndexedLoadStore(SDNode *N);
132 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
133 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
134 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
135 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
136 SDValue PromoteIntBinOp(SDValue Op);
137 SDValue PromoteIntShiftOp(SDValue Op);
138 SDValue PromoteExtend(SDValue Op);
139 bool PromoteLoad(SDValue Op);
141 /// combine - call the node-specific routine that knows how to fold each
142 /// particular type of node. If that doesn't do anything, try the
143 /// target-specific DAG combines.
144 SDValue combine(SDNode *N);
146 // Visitation implementation - Implement dag node combining for different
147 // node types. The semantics are as follows:
149 // SDValue.getNode() == 0 - No change was made
150 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
151 // otherwise - N should be replaced by the returned Operand.
153 SDValue visitTokenFactor(SDNode *N);
154 SDValue visitMERGE_VALUES(SDNode *N);
155 SDValue visitADD(SDNode *N);
156 SDValue visitSUB(SDNode *N);
157 SDValue visitADDC(SDNode *N);
158 SDValue visitADDE(SDNode *N);
159 SDValue visitMUL(SDNode *N);
160 SDValue visitSDIV(SDNode *N);
161 SDValue visitUDIV(SDNode *N);
162 SDValue visitSREM(SDNode *N);
163 SDValue visitUREM(SDNode *N);
164 SDValue visitMULHU(SDNode *N);
165 SDValue visitMULHS(SDNode *N);
166 SDValue visitSMUL_LOHI(SDNode *N);
167 SDValue visitUMUL_LOHI(SDNode *N);
168 SDValue visitSDIVREM(SDNode *N);
169 SDValue visitUDIVREM(SDNode *N);
170 SDValue visitAND(SDNode *N);
171 SDValue visitOR(SDNode *N);
172 SDValue visitXOR(SDNode *N);
173 SDValue SimplifyVBinOp(SDNode *N);
174 SDValue visitSHL(SDNode *N);
175 SDValue visitSRA(SDNode *N);
176 SDValue visitSRL(SDNode *N);
177 SDValue visitCTLZ(SDNode *N);
178 SDValue visitCTTZ(SDNode *N);
179 SDValue visitCTPOP(SDNode *N);
180 SDValue visitSELECT(SDNode *N);
181 SDValue visitSELECT_CC(SDNode *N);
182 SDValue visitSETCC(SDNode *N);
183 SDValue visitSIGN_EXTEND(SDNode *N);
184 SDValue visitZERO_EXTEND(SDNode *N);
185 SDValue visitANY_EXTEND(SDNode *N);
186 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
187 SDValue visitTRUNCATE(SDNode *N);
188 SDValue visitBIT_CONVERT(SDNode *N);
189 SDValue visitBUILD_PAIR(SDNode *N);
190 SDValue visitFADD(SDNode *N);
191 SDValue visitFSUB(SDNode *N);
192 SDValue visitFMUL(SDNode *N);
193 SDValue visitFDIV(SDNode *N);
194 SDValue visitFREM(SDNode *N);
195 SDValue visitFCOPYSIGN(SDNode *N);
196 SDValue visitSINT_TO_FP(SDNode *N);
197 SDValue visitUINT_TO_FP(SDNode *N);
198 SDValue visitFP_TO_SINT(SDNode *N);
199 SDValue visitFP_TO_UINT(SDNode *N);
200 SDValue visitFP_ROUND(SDNode *N);
201 SDValue visitFP_ROUND_INREG(SDNode *N);
202 SDValue visitFP_EXTEND(SDNode *N);
203 SDValue visitFNEG(SDNode *N);
204 SDValue visitFABS(SDNode *N);
205 SDValue visitBRCOND(SDNode *N);
206 SDValue visitBR_CC(SDNode *N);
207 SDValue visitLOAD(SDNode *N);
208 SDValue visitSTORE(SDNode *N);
209 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
210 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
211 SDValue visitBUILD_VECTOR(SDNode *N);
212 SDValue visitCONCAT_VECTORS(SDNode *N);
213 SDValue visitVECTOR_SHUFFLE(SDNode *N);
214 SDValue visitMEMBARRIER(SDNode *N);
216 SDValue XformToShuffleWithZero(SDNode *N);
217 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
219 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
221 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
222 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
223 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
224 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
225 SDValue N3, ISD::CondCode CC,
226 bool NotExtCompare = false);
227 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
228 DebugLoc DL, bool foldBooleans = true);
229 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
231 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
232 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT);
233 SDValue BuildSDIV(SDNode *N);
234 SDValue BuildUDIV(SDNode *N);
235 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
236 SDValue ReduceLoadWidth(SDNode *N);
237 SDValue ReduceLoadOpStoreWidth(SDNode *N);
239 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
241 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
242 /// looking for aliasing nodes and adding them to the Aliases vector.
243 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
244 SmallVector<SDValue, 8> &Aliases);
246 /// isAlias - Return true if there is any possibility that the two addresses
248 bool isAlias(SDValue Ptr1, int64_t Size1,
249 const Value *SrcValue1, int SrcValueOffset1,
250 unsigned SrcValueAlign1,
251 SDValue Ptr2, int64_t Size2,
252 const Value *SrcValue2, int SrcValueOffset2,
253 unsigned SrcValueAlign2) const;
255 /// FindAliasInfo - Extracts the relevant alias information from the memory
256 /// node. Returns true if the operand was a load.
257 bool FindAliasInfo(SDNode *N,
258 SDValue &Ptr, int64_t &Size,
259 const Value *&SrcValue, int &SrcValueOffset,
260 unsigned &SrcValueAlignment) const;
262 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
263 /// looking for a better chain (aliasing node.)
264 SDValue FindBetterChain(SDNode *N, SDValue Chain);
267 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
268 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted),
269 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
271 /// Run - runs the dag combiner on all nodes in the work list
272 void Run(CombineLevel AtLevel);
274 SelectionDAG &getDAG() const { return DAG; }
276 /// getShiftAmountTy - Returns a type large enough to hold any valid
277 /// shift amount - before type legalization these can be huge.
278 EVT getShiftAmountTy() {
279 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy();
282 /// isTypeLegal - This method returns true if we are running before type
283 /// legalization or if the specified VT is legal.
284 bool isTypeLegal(const EVT &VT) {
285 if (!LegalTypes) return true;
286 return TLI.isTypeLegal(VT);
293 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
294 /// nodes from the worklist.
295 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
298 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
300 virtual void NodeDeleted(SDNode *N, SDNode *E) {
301 DC.removeFromWorkList(N);
304 virtual void NodeUpdated(SDNode *N) {
310 //===----------------------------------------------------------------------===//
311 // TargetLowering::DAGCombinerInfo implementation
312 //===----------------------------------------------------------------------===//
314 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
315 ((DAGCombiner*)DC)->AddToWorkList(N);
318 SDValue TargetLowering::DAGCombinerInfo::
319 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
320 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
323 SDValue TargetLowering::DAGCombinerInfo::
324 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
325 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
329 SDValue TargetLowering::DAGCombinerInfo::
330 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
331 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
334 void TargetLowering::DAGCombinerInfo::
335 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
336 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
339 //===----------------------------------------------------------------------===//
341 //===----------------------------------------------------------------------===//
343 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
344 /// specified expression for the same cost as the expression itself, or 2 if we
345 /// can compute the negated form more cheaply than the expression itself.
346 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
347 unsigned Depth = 0) {
348 // No compile time optimizations on this type.
349 if (Op.getValueType() == MVT::ppcf128)
352 // fneg is removable even if it has multiple uses.
353 if (Op.getOpcode() == ISD::FNEG) return 2;
355 // Don't allow anything with multiple uses.
356 if (!Op.hasOneUse()) return 0;
358 // Don't recurse exponentially.
359 if (Depth > 6) return 0;
361 switch (Op.getOpcode()) {
362 default: return false;
363 case ISD::ConstantFP:
364 // Don't invert constant FP values after legalize. The negated constant
365 // isn't necessarily legal.
366 return LegalOperations ? 0 : 1;
368 // FIXME: determine better conditions for this xform.
369 if (!UnsafeFPMath) return 0;
371 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
372 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
374 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
375 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
377 // We can't turn -(A-B) into B-A when we honor signed zeros.
378 if (!UnsafeFPMath) return 0;
380 // fold (fneg (fsub A, B)) -> (fsub B, A)
385 if (HonorSignDependentRoundingFPMath()) return 0;
387 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
388 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
391 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
396 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1);
400 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
401 /// returns the newly negated expression.
402 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
403 bool LegalOperations, unsigned Depth = 0) {
404 // fneg is removable even if it has multiple uses.
405 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
407 // Don't allow anything with multiple uses.
408 assert(Op.hasOneUse() && "Unknown reuse!");
410 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
411 switch (Op.getOpcode()) {
412 default: llvm_unreachable("Unknown code");
413 case ISD::ConstantFP: {
414 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
416 return DAG.getConstantFP(V, Op.getValueType());
419 // FIXME: determine better conditions for this xform.
420 assert(UnsafeFPMath);
422 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
423 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
424 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
425 GetNegatedExpression(Op.getOperand(0), DAG,
426 LegalOperations, Depth+1),
428 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
429 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
430 GetNegatedExpression(Op.getOperand(1), DAG,
431 LegalOperations, Depth+1),
434 // We can't turn -(A-B) into B-A when we honor signed zeros.
435 assert(UnsafeFPMath);
437 // fold (fneg (fsub 0, B)) -> B
438 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
439 if (N0CFP->getValueAPF().isZero())
440 return Op.getOperand(1);
442 // fold (fneg (fsub A, B)) -> (fsub B, A)
443 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
444 Op.getOperand(1), Op.getOperand(0));
448 assert(!HonorSignDependentRoundingFPMath());
450 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
451 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
452 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
453 GetNegatedExpression(Op.getOperand(0), DAG,
454 LegalOperations, Depth+1),
457 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
458 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
460 GetNegatedExpression(Op.getOperand(1), DAG,
461 LegalOperations, Depth+1));
465 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
466 GetNegatedExpression(Op.getOperand(0), DAG,
467 LegalOperations, Depth+1));
469 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
470 GetNegatedExpression(Op.getOperand(0), DAG,
471 LegalOperations, Depth+1),
477 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
478 // that selects between the values 1 and 0, making it equivalent to a setcc.
479 // Also, set the incoming LHS, RHS, and CC references to the appropriate
480 // nodes based on the type of node we are checking. This simplifies life a
481 // bit for the callers.
482 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
484 if (N.getOpcode() == ISD::SETCC) {
485 LHS = N.getOperand(0);
486 RHS = N.getOperand(1);
487 CC = N.getOperand(2);
490 if (N.getOpcode() == ISD::SELECT_CC &&
491 N.getOperand(2).getOpcode() == ISD::Constant &&
492 N.getOperand(3).getOpcode() == ISD::Constant &&
493 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
494 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
495 LHS = N.getOperand(0);
496 RHS = N.getOperand(1);
497 CC = N.getOperand(4);
503 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
504 // one use. If this is true, it allows the users to invert the operation for
505 // free when it is profitable to do so.
506 static bool isOneUseSetCC(SDValue N) {
508 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
513 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
514 SDValue N0, SDValue N1) {
515 EVT VT = N0.getValueType();
516 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
517 if (isa<ConstantSDNode>(N1)) {
518 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
520 DAG.FoldConstantArithmetic(Opc, VT,
521 cast<ConstantSDNode>(N0.getOperand(1)),
522 cast<ConstantSDNode>(N1));
523 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
524 } else if (N0.hasOneUse()) {
525 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
526 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
527 N0.getOperand(0), N1);
528 AddToWorkList(OpNode.getNode());
529 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
533 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
534 if (isa<ConstantSDNode>(N0)) {
535 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
537 DAG.FoldConstantArithmetic(Opc, VT,
538 cast<ConstantSDNode>(N1.getOperand(1)),
539 cast<ConstantSDNode>(N0));
540 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
541 } else if (N1.hasOneUse()) {
542 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
543 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
544 N1.getOperand(0), N0);
545 AddToWorkList(OpNode.getNode());
546 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
553 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
555 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
557 DEBUG(dbgs() << "\nReplacing.1 ";
559 dbgs() << "\nWith: ";
560 To[0].getNode()->dump(&DAG);
561 dbgs() << " and " << NumTo-1 << " other values\n";
562 for (unsigned i = 0, e = NumTo; i != e; ++i)
563 assert((!To[i].getNode() ||
564 N->getValueType(i) == To[i].getValueType()) &&
565 "Cannot combine value to value of different type!"));
566 WorkListRemover DeadNodes(*this);
567 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
570 // Push the new nodes and any users onto the worklist
571 for (unsigned i = 0, e = NumTo; i != e; ++i) {
572 if (To[i].getNode()) {
573 AddToWorkList(To[i].getNode());
574 AddUsersToWorkList(To[i].getNode());
579 // Finally, if the node is now dead, remove it from the graph. The node
580 // may not be dead if the replacement process recursively simplified to
581 // something else needing this node.
582 if (N->use_empty()) {
583 // Nodes can be reintroduced into the worklist. Make sure we do not
584 // process a node that has been replaced.
585 removeFromWorkList(N);
587 // Finally, since the node is now dead, remove it from the graph.
590 return SDValue(N, 0);
594 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
595 // Replace all uses. If any nodes become isomorphic to other nodes and
596 // are deleted, make sure to remove them from our worklist.
597 WorkListRemover DeadNodes(*this);
598 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
600 // Push the new node and any (possibly new) users onto the worklist.
601 AddToWorkList(TLO.New.getNode());
602 AddUsersToWorkList(TLO.New.getNode());
604 // Finally, if the node is now dead, remove it from the graph. The node
605 // may not be dead if the replacement process recursively simplified to
606 // something else needing this node.
607 if (TLO.Old.getNode()->use_empty()) {
608 removeFromWorkList(TLO.Old.getNode());
610 // If the operands of this node are only used by the node, they will now
611 // be dead. Make sure to visit them first to delete dead nodes early.
612 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
613 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
614 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
616 DAG.DeleteNode(TLO.Old.getNode());
620 /// SimplifyDemandedBits - Check the specified integer node value to see if
621 /// it can be simplified or if things it uses can be simplified by bit
622 /// propagation. If so, return true.
623 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
624 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
625 APInt KnownZero, KnownOne;
626 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
630 AddToWorkList(Op.getNode());
632 // Replace the old value with the new one.
634 DEBUG(dbgs() << "\nReplacing.2 ";
635 TLO.Old.getNode()->dump(&DAG);
636 dbgs() << "\nWith: ";
637 TLO.New.getNode()->dump(&DAG);
640 CommitTargetLoweringOpt(TLO);
644 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
645 DebugLoc dl = Load->getDebugLoc();
646 EVT VT = Load->getValueType(0);
647 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
649 DEBUG(dbgs() << "\nReplacing.9 ";
651 dbgs() << "\nWith: ";
652 Trunc.getNode()->dump(&DAG);
654 WorkListRemover DeadNodes(*this);
655 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes);
656 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1),
658 removeFromWorkList(Load);
659 DAG.DeleteNode(Load);
660 AddToWorkList(Trunc.getNode());
663 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
665 DebugLoc dl = Op.getDebugLoc();
666 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
667 EVT MemVT = LD->getMemoryVT();
668 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
669 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD : ISD::EXTLOAD)
670 : LD->getExtensionType();
672 return DAG.getExtLoad(ExtType, PVT, dl,
673 LD->getChain(), LD->getBasePtr(),
674 LD->getPointerInfo(),
675 MemVT, LD->isVolatile(),
676 LD->isNonTemporal(), LD->getAlignment());
679 unsigned Opc = Op.getOpcode();
682 case ISD::AssertSext:
683 return DAG.getNode(ISD::AssertSext, dl, PVT,
684 SExtPromoteOperand(Op.getOperand(0), PVT),
686 case ISD::AssertZext:
687 return DAG.getNode(ISD::AssertZext, dl, PVT,
688 ZExtPromoteOperand(Op.getOperand(0), PVT),
690 case ISD::Constant: {
692 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
693 return DAG.getNode(ExtOpc, dl, PVT, Op);
697 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
699 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
702 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
703 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
705 EVT OldVT = Op.getValueType();
706 DebugLoc dl = Op.getDebugLoc();
707 bool Replace = false;
708 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
709 if (NewOp.getNode() == 0)
711 AddToWorkList(NewOp.getNode());
714 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
715 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
716 DAG.getValueType(OldVT));
719 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
720 EVT OldVT = Op.getValueType();
721 DebugLoc dl = Op.getDebugLoc();
722 bool Replace = false;
723 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
724 if (NewOp.getNode() == 0)
726 AddToWorkList(NewOp.getNode());
729 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
730 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
733 /// PromoteIntBinOp - Promote the specified integer binary operation if the
734 /// target indicates it is beneficial. e.g. On x86, it's usually better to
735 /// promote i16 operations to i32 since i16 instructions are longer.
736 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
737 if (!LegalOperations)
740 EVT VT = Op.getValueType();
741 if (VT.isVector() || !VT.isInteger())
744 // If operation type is 'undesirable', e.g. i16 on x86, consider
746 unsigned Opc = Op.getOpcode();
747 if (TLI.isTypeDesirableForOp(Opc, VT))
751 // Consult target whether it is a good idea to promote this operation and
752 // what's the right type to promote it to.
753 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
754 assert(PVT != VT && "Don't know what type to promote to!");
756 bool Replace0 = false;
757 SDValue N0 = Op.getOperand(0);
758 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
759 if (NN0.getNode() == 0)
762 bool Replace1 = false;
763 SDValue N1 = Op.getOperand(1);
768 NN1 = PromoteOperand(N1, PVT, Replace1);
769 if (NN1.getNode() == 0)
773 AddToWorkList(NN0.getNode());
775 AddToWorkList(NN1.getNode());
778 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
780 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
782 DEBUG(dbgs() << "\nPromoting ";
783 Op.getNode()->dump(&DAG));
784 DebugLoc dl = Op.getDebugLoc();
785 return DAG.getNode(ISD::TRUNCATE, dl, VT,
786 DAG.getNode(Opc, dl, PVT, NN0, NN1));
791 /// PromoteIntShiftOp - Promote the specified integer shift operation if the
792 /// target indicates it is beneficial. e.g. On x86, it's usually better to
793 /// promote i16 operations to i32 since i16 instructions are longer.
794 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
795 if (!LegalOperations)
798 EVT VT = Op.getValueType();
799 if (VT.isVector() || !VT.isInteger())
802 // If operation type is 'undesirable', e.g. i16 on x86, consider
804 unsigned Opc = Op.getOpcode();
805 if (TLI.isTypeDesirableForOp(Opc, VT))
809 // Consult target whether it is a good idea to promote this operation and
810 // what's the right type to promote it to.
811 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
812 assert(PVT != VT && "Don't know what type to promote to!");
814 bool Replace = false;
815 SDValue N0 = Op.getOperand(0);
817 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
818 else if (Opc == ISD::SRL)
819 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
821 N0 = PromoteOperand(N0, PVT, Replace);
822 if (N0.getNode() == 0)
825 AddToWorkList(N0.getNode());
827 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
829 DEBUG(dbgs() << "\nPromoting ";
830 Op.getNode()->dump(&DAG));
831 DebugLoc dl = Op.getDebugLoc();
832 return DAG.getNode(ISD::TRUNCATE, dl, VT,
833 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
838 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
839 if (!LegalOperations)
842 EVT VT = Op.getValueType();
843 if (VT.isVector() || !VT.isInteger())
846 // If operation type is 'undesirable', e.g. i16 on x86, consider
848 unsigned Opc = Op.getOpcode();
849 if (TLI.isTypeDesirableForOp(Opc, VT))
853 // Consult target whether it is a good idea to promote this operation and
854 // what's the right type to promote it to.
855 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
856 assert(PVT != VT && "Don't know what type to promote to!");
857 // fold (aext (aext x)) -> (aext x)
858 // fold (aext (zext x)) -> (zext x)
859 // fold (aext (sext x)) -> (sext x)
860 DEBUG(dbgs() << "\nPromoting ";
861 Op.getNode()->dump(&DAG));
862 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0));
867 bool DAGCombiner::PromoteLoad(SDValue Op) {
868 if (!LegalOperations)
871 EVT VT = Op.getValueType();
872 if (VT.isVector() || !VT.isInteger())
875 // If operation type is 'undesirable', e.g. i16 on x86, consider
877 unsigned Opc = Op.getOpcode();
878 if (TLI.isTypeDesirableForOp(Opc, VT))
882 // Consult target whether it is a good idea to promote this operation and
883 // what's the right type to promote it to.
884 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
885 assert(PVT != VT && "Don't know what type to promote to!");
887 DebugLoc dl = Op.getDebugLoc();
888 SDNode *N = Op.getNode();
889 LoadSDNode *LD = cast<LoadSDNode>(N);
890 EVT MemVT = LD->getMemoryVT();
891 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
892 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD : ISD::EXTLOAD)
893 : LD->getExtensionType();
894 SDValue NewLD = DAG.getExtLoad(ExtType, PVT, dl,
895 LD->getChain(), LD->getBasePtr(),
896 LD->getPointerInfo(),
897 MemVT, LD->isVolatile(),
898 LD->isNonTemporal(), LD->getAlignment());
899 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
901 DEBUG(dbgs() << "\nPromoting ";
904 Result.getNode()->dump(&DAG);
906 WorkListRemover DeadNodes(*this);
907 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes);
908 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes);
909 removeFromWorkList(N);
911 AddToWorkList(Result.getNode());
918 //===----------------------------------------------------------------------===//
919 // Main DAG Combiner implementation
920 //===----------------------------------------------------------------------===//
922 void DAGCombiner::Run(CombineLevel AtLevel) {
923 // set the instance variables, so that the various visit routines may use it.
925 LegalOperations = Level >= NoIllegalOperations;
926 LegalTypes = Level >= NoIllegalTypes;
928 // Add all the dag nodes to the worklist.
929 WorkList.reserve(DAG.allnodes_size());
930 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
931 E = DAG.allnodes_end(); I != E; ++I)
932 WorkList.push_back(I);
934 // Create a dummy node (which is not added to allnodes), that adds a reference
935 // to the root node, preventing it from being deleted, and tracking any
936 // changes of the root.
937 HandleSDNode Dummy(DAG.getRoot());
939 // The root of the dag may dangle to deleted nodes until the dag combiner is
940 // done. Set it to null to avoid confusion.
941 DAG.setRoot(SDValue());
943 // while the worklist isn't empty, inspect the node on the end of it and
944 // try and combine it.
945 while (!WorkList.empty()) {
946 SDNode *N = WorkList.back();
949 // If N has no uses, it is dead. Make sure to revisit all N's operands once
950 // N is deleted from the DAG, since they too may now be dead or may have a
951 // reduced number of uses, allowing other xforms.
952 if (N->use_empty() && N != &Dummy) {
953 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
954 AddToWorkList(N->getOperand(i).getNode());
960 SDValue RV = combine(N);
962 if (RV.getNode() == 0)
967 // If we get back the same node we passed in, rather than a new node or
968 // zero, we know that the node must have defined multiple values and
969 // CombineTo was used. Since CombineTo takes care of the worklist
970 // mechanics for us, we have no work to do in this case.
971 if (RV.getNode() == N)
974 assert(N->getOpcode() != ISD::DELETED_NODE &&
975 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
976 "Node was deleted but visit returned new node!");
978 DEBUG(dbgs() << "\nReplacing.3 ";
980 dbgs() << "\nWith: ";
981 RV.getNode()->dump(&DAG);
983 WorkListRemover DeadNodes(*this);
984 if (N->getNumValues() == RV.getNode()->getNumValues())
985 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
987 assert(N->getValueType(0) == RV.getValueType() &&
988 N->getNumValues() == 1 && "Type mismatch");
990 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
993 // Push the new node and any users onto the worklist
994 AddToWorkList(RV.getNode());
995 AddUsersToWorkList(RV.getNode());
997 // Add any uses of the old node to the worklist in case this node is the
998 // last one that uses them. They may become dead after this node is
1000 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1001 AddToWorkList(N->getOperand(i).getNode());
1003 // Finally, if the node is now dead, remove it from the graph. The node
1004 // may not be dead if the replacement process recursively simplified to
1005 // something else needing this node.
1006 if (N->use_empty()) {
1007 // Nodes can be reintroduced into the worklist. Make sure we do not
1008 // process a node that has been replaced.
1009 removeFromWorkList(N);
1011 // Finally, since the node is now dead, remove it from the graph.
1016 // If the root changed (e.g. it was a dead load, update the root).
1017 DAG.setRoot(Dummy.getValue());
1020 SDValue DAGCombiner::visit(SDNode *N) {
1021 switch (N->getOpcode()) {
1023 case ISD::TokenFactor: return visitTokenFactor(N);
1024 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1025 case ISD::ADD: return visitADD(N);
1026 case ISD::SUB: return visitSUB(N);
1027 case ISD::ADDC: return visitADDC(N);
1028 case ISD::ADDE: return visitADDE(N);
1029 case ISD::MUL: return visitMUL(N);
1030 case ISD::SDIV: return visitSDIV(N);
1031 case ISD::UDIV: return visitUDIV(N);
1032 case ISD::SREM: return visitSREM(N);
1033 case ISD::UREM: return visitUREM(N);
1034 case ISD::MULHU: return visitMULHU(N);
1035 case ISD::MULHS: return visitMULHS(N);
1036 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1037 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1038 case ISD::SDIVREM: return visitSDIVREM(N);
1039 case ISD::UDIVREM: return visitUDIVREM(N);
1040 case ISD::AND: return visitAND(N);
1041 case ISD::OR: return visitOR(N);
1042 case ISD::XOR: return visitXOR(N);
1043 case ISD::SHL: return visitSHL(N);
1044 case ISD::SRA: return visitSRA(N);
1045 case ISD::SRL: return visitSRL(N);
1046 case ISD::CTLZ: return visitCTLZ(N);
1047 case ISD::CTTZ: return visitCTTZ(N);
1048 case ISD::CTPOP: return visitCTPOP(N);
1049 case ISD::SELECT: return visitSELECT(N);
1050 case ISD::SELECT_CC: return visitSELECT_CC(N);
1051 case ISD::SETCC: return visitSETCC(N);
1052 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1053 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1054 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1055 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1056 case ISD::TRUNCATE: return visitTRUNCATE(N);
1057 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
1058 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1059 case ISD::FADD: return visitFADD(N);
1060 case ISD::FSUB: return visitFSUB(N);
1061 case ISD::FMUL: return visitFMUL(N);
1062 case ISD::FDIV: return visitFDIV(N);
1063 case ISD::FREM: return visitFREM(N);
1064 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1065 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1066 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1067 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1068 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1069 case ISD::FP_ROUND: return visitFP_ROUND(N);
1070 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1071 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1072 case ISD::FNEG: return visitFNEG(N);
1073 case ISD::FABS: return visitFABS(N);
1074 case ISD::BRCOND: return visitBRCOND(N);
1075 case ISD::BR_CC: return visitBR_CC(N);
1076 case ISD::LOAD: return visitLOAD(N);
1077 case ISD::STORE: return visitSTORE(N);
1078 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1079 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1080 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1081 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1082 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1083 case ISD::MEMBARRIER: return visitMEMBARRIER(N);
1088 SDValue DAGCombiner::combine(SDNode *N) {
1089 SDValue RV = visit(N);
1091 // If nothing happened, try a target-specific DAG combine.
1092 if (RV.getNode() == 0) {
1093 assert(N->getOpcode() != ISD::DELETED_NODE &&
1094 "Node was deleted but visit returned NULL!");
1096 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1097 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1099 // Expose the DAG combiner to the target combiner impls.
1100 TargetLowering::DAGCombinerInfo
1101 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
1103 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1107 // If nothing happened still, try promoting the operation.
1108 if (RV.getNode() == 0) {
1109 switch (N->getOpcode()) {
1117 RV = PromoteIntBinOp(SDValue(N, 0));
1122 RV = PromoteIntShiftOp(SDValue(N, 0));
1124 case ISD::SIGN_EXTEND:
1125 case ISD::ZERO_EXTEND:
1126 case ISD::ANY_EXTEND:
1127 RV = PromoteExtend(SDValue(N, 0));
1130 if (PromoteLoad(SDValue(N, 0)))
1136 // If N is a commutative binary node, try commuting it to enable more
1138 if (RV.getNode() == 0 &&
1139 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1140 N->getNumValues() == 1) {
1141 SDValue N0 = N->getOperand(0);
1142 SDValue N1 = N->getOperand(1);
1144 // Constant operands are canonicalized to RHS.
1145 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1146 SDValue Ops[] = { N1, N0 };
1147 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1150 return SDValue(CSENode, 0);
1157 /// getInputChainForNode - Given a node, return its input chain if it has one,
1158 /// otherwise return a null sd operand.
1159 static SDValue getInputChainForNode(SDNode *N) {
1160 if (unsigned NumOps = N->getNumOperands()) {
1161 if (N->getOperand(0).getValueType() == MVT::Other)
1162 return N->getOperand(0);
1163 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1164 return N->getOperand(NumOps-1);
1165 for (unsigned i = 1; i < NumOps-1; ++i)
1166 if (N->getOperand(i).getValueType() == MVT::Other)
1167 return N->getOperand(i);
1172 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1173 // If N has two operands, where one has an input chain equal to the other,
1174 // the 'other' chain is redundant.
1175 if (N->getNumOperands() == 2) {
1176 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1177 return N->getOperand(0);
1178 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1179 return N->getOperand(1);
1182 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1183 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1184 SmallPtrSet<SDNode*, 16> SeenOps;
1185 bool Changed = false; // If we should replace this token factor.
1187 // Start out with this token factor.
1190 // Iterate through token factors. The TFs grows when new token factors are
1192 for (unsigned i = 0; i < TFs.size(); ++i) {
1193 SDNode *TF = TFs[i];
1195 // Check each of the operands.
1196 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1197 SDValue Op = TF->getOperand(i);
1199 switch (Op.getOpcode()) {
1200 case ISD::EntryToken:
1201 // Entry tokens don't need to be added to the list. They are
1206 case ISD::TokenFactor:
1207 if (Op.hasOneUse() &&
1208 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1209 // Queue up for processing.
1210 TFs.push_back(Op.getNode());
1211 // Clean up in case the token factor is removed.
1212 AddToWorkList(Op.getNode());
1219 // Only add if it isn't already in the list.
1220 if (SeenOps.insert(Op.getNode()))
1231 // If we've change things around then replace token factor.
1234 // The entry token is the only possible outcome.
1235 Result = DAG.getEntryNode();
1237 // New and improved token factor.
1238 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
1239 MVT::Other, &Ops[0], Ops.size());
1242 // Don't add users to work list.
1243 return CombineTo(N, Result, false);
1249 /// MERGE_VALUES can always be eliminated.
1250 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1251 WorkListRemover DeadNodes(*this);
1252 // Replacing results may cause a different MERGE_VALUES to suddenly
1253 // be CSE'd with N, and carry its uses with it. Iterate until no
1254 // uses remain, to ensure that the node can be safely deleted.
1256 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1257 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
1259 } while (!N->use_empty());
1260 removeFromWorkList(N);
1262 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1266 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
1267 SelectionDAG &DAG) {
1268 EVT VT = N0.getValueType();
1269 SDValue N00 = N0.getOperand(0);
1270 SDValue N01 = N0.getOperand(1);
1271 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1273 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1274 isa<ConstantSDNode>(N00.getOperand(1))) {
1275 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1276 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1277 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1278 N00.getOperand(0), N01),
1279 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1280 N00.getOperand(1), N01));
1281 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1287 SDValue DAGCombiner::visitADD(SDNode *N) {
1288 SDValue N0 = N->getOperand(0);
1289 SDValue N1 = N->getOperand(1);
1290 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1291 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1292 EVT VT = N0.getValueType();
1295 if (VT.isVector()) {
1296 SDValue FoldedVOp = SimplifyVBinOp(N);
1297 if (FoldedVOp.getNode()) return FoldedVOp;
1300 // fold (add x, undef) -> undef
1301 if (N0.getOpcode() == ISD::UNDEF)
1303 if (N1.getOpcode() == ISD::UNDEF)
1305 // fold (add c1, c2) -> c1+c2
1307 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1308 // canonicalize constant to RHS
1310 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1311 // fold (add x, 0) -> x
1312 if (N1C && N1C->isNullValue())
1314 // fold (add Sym, c) -> Sym+c
1315 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1316 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1317 GA->getOpcode() == ISD::GlobalAddress)
1318 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1320 (uint64_t)N1C->getSExtValue());
1321 // fold ((c1-A)+c2) -> (c1+c2)-A
1322 if (N1C && N0.getOpcode() == ISD::SUB)
1323 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1324 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1325 DAG.getConstant(N1C->getAPIntValue()+
1326 N0C->getAPIntValue(), VT),
1329 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1330 if (RADD.getNode() != 0)
1332 // fold ((0-A) + B) -> B-A
1333 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1334 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1335 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1336 // fold (A + (0-B)) -> A-B
1337 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1338 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1339 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1340 // fold (A+(B-A)) -> B
1341 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1342 return N1.getOperand(0);
1343 // fold ((B-A)+A) -> B
1344 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1345 return N0.getOperand(0);
1346 // fold (A+(B-(A+C))) to (B-C)
1347 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1348 N0 == N1.getOperand(1).getOperand(0))
1349 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1350 N1.getOperand(1).getOperand(1));
1351 // fold (A+(B-(C+A))) to (B-C)
1352 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1353 N0 == N1.getOperand(1).getOperand(1))
1354 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1355 N1.getOperand(1).getOperand(0));
1356 // fold (A+((B-A)+or-C)) to (B+or-C)
1357 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1358 N1.getOperand(0).getOpcode() == ISD::SUB &&
1359 N0 == N1.getOperand(0).getOperand(1))
1360 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1361 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1363 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1364 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1365 SDValue N00 = N0.getOperand(0);
1366 SDValue N01 = N0.getOperand(1);
1367 SDValue N10 = N1.getOperand(0);
1368 SDValue N11 = N1.getOperand(1);
1370 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1371 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1372 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1373 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1376 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1377 return SDValue(N, 0);
1379 // fold (a+b) -> (a|b) iff a and b share no bits.
1380 if (VT.isInteger() && !VT.isVector()) {
1381 APInt LHSZero, LHSOne;
1382 APInt RHSZero, RHSOne;
1383 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1384 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1386 if (LHSZero.getBoolValue()) {
1387 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1389 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1390 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1391 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1392 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1393 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1397 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1398 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1399 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1400 if (Result.getNode()) return Result;
1402 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1403 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1404 if (Result.getNode()) return Result;
1407 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1408 if (N1.getOpcode() == ISD::SHL &&
1409 N1.getOperand(0).getOpcode() == ISD::SUB)
1410 if (ConstantSDNode *C =
1411 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1412 if (C->getAPIntValue() == 0)
1413 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1414 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1415 N1.getOperand(0).getOperand(1),
1417 if (N0.getOpcode() == ISD::SHL &&
1418 N0.getOperand(0).getOpcode() == ISD::SUB)
1419 if (ConstantSDNode *C =
1420 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1421 if (C->getAPIntValue() == 0)
1422 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1423 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1424 N0.getOperand(0).getOperand(1),
1427 if (N1.getOpcode() == ISD::AND) {
1428 SDValue AndOp0 = N1.getOperand(0);
1429 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1430 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1431 unsigned DestBits = VT.getScalarType().getSizeInBits();
1433 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1434 // and similar xforms where the inner op is either ~0 or 0.
1435 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1436 DebugLoc DL = N->getDebugLoc();
1437 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1444 SDValue DAGCombiner::visitADDC(SDNode *N) {
1445 SDValue N0 = N->getOperand(0);
1446 SDValue N1 = N->getOperand(1);
1447 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1448 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1449 EVT VT = N0.getValueType();
1451 // If the flag result is dead, turn this into an ADD.
1452 if (N->hasNUsesOfValue(0, 1))
1453 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
1454 DAG.getNode(ISD::CARRY_FALSE,
1455 N->getDebugLoc(), MVT::Flag));
1457 // canonicalize constant to RHS.
1459 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1461 // fold (addc x, 0) -> x + no carry out
1462 if (N1C && N1C->isNullValue())
1463 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1464 N->getDebugLoc(), MVT::Flag));
1466 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1467 APInt LHSZero, LHSOne;
1468 APInt RHSZero, RHSOne;
1469 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1470 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1472 if (LHSZero.getBoolValue()) {
1473 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1475 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1476 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1477 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1478 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1479 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1480 DAG.getNode(ISD::CARRY_FALSE,
1481 N->getDebugLoc(), MVT::Flag));
1487 SDValue DAGCombiner::visitADDE(SDNode *N) {
1488 SDValue N0 = N->getOperand(0);
1489 SDValue N1 = N->getOperand(1);
1490 SDValue CarryIn = N->getOperand(2);
1491 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1492 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1494 // canonicalize constant to RHS
1496 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1499 // fold (adde x, y, false) -> (addc x, y)
1500 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1501 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1506 SDValue DAGCombiner::visitSUB(SDNode *N) {
1507 SDValue N0 = N->getOperand(0);
1508 SDValue N1 = N->getOperand(1);
1509 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1510 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1511 EVT VT = N0.getValueType();
1514 if (VT.isVector()) {
1515 SDValue FoldedVOp = SimplifyVBinOp(N);
1516 if (FoldedVOp.getNode()) return FoldedVOp;
1519 // fold (sub x, x) -> 0
1521 return DAG.getConstant(0, N->getValueType(0));
1522 // fold (sub c1, c2) -> c1-c2
1524 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1525 // fold (sub x, c) -> (add x, -c)
1527 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1528 DAG.getConstant(-N1C->getAPIntValue(), VT));
1529 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1530 if (N0C && N0C->isAllOnesValue())
1531 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1532 // fold (A+B)-A -> B
1533 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1534 return N0.getOperand(1);
1535 // fold (A+B)-B -> A
1536 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1537 return N0.getOperand(0);
1538 // fold ((A+(B+or-C))-B) -> A+or-C
1539 if (N0.getOpcode() == ISD::ADD &&
1540 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1541 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1542 N0.getOperand(1).getOperand(0) == N1)
1543 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1544 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1545 // fold ((A+(C+B))-B) -> A+C
1546 if (N0.getOpcode() == ISD::ADD &&
1547 N0.getOperand(1).getOpcode() == ISD::ADD &&
1548 N0.getOperand(1).getOperand(1) == N1)
1549 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1550 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1551 // fold ((A-(B-C))-C) -> A-B
1552 if (N0.getOpcode() == ISD::SUB &&
1553 N0.getOperand(1).getOpcode() == ISD::SUB &&
1554 N0.getOperand(1).getOperand(1) == N1)
1555 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1556 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1558 // If either operand of a sub is undef, the result is undef
1559 if (N0.getOpcode() == ISD::UNDEF)
1561 if (N1.getOpcode() == ISD::UNDEF)
1564 // If the relocation model supports it, consider symbol offsets.
1565 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1566 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1567 // fold (sub Sym, c) -> Sym-c
1568 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1569 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1571 (uint64_t)N1C->getSExtValue());
1572 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1573 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1574 if (GA->getGlobal() == GB->getGlobal())
1575 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1582 SDValue DAGCombiner::visitMUL(SDNode *N) {
1583 SDValue N0 = N->getOperand(0);
1584 SDValue N1 = N->getOperand(1);
1585 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1586 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1587 EVT VT = N0.getValueType();
1590 if (VT.isVector()) {
1591 SDValue FoldedVOp = SimplifyVBinOp(N);
1592 if (FoldedVOp.getNode()) return FoldedVOp;
1595 // fold (mul x, undef) -> 0
1596 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1597 return DAG.getConstant(0, VT);
1598 // fold (mul c1, c2) -> c1*c2
1600 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1601 // canonicalize constant to RHS
1603 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1604 // fold (mul x, 0) -> 0
1605 if (N1C && N1C->isNullValue())
1607 // fold (mul x, -1) -> 0-x
1608 if (N1C && N1C->isAllOnesValue())
1609 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1610 DAG.getConstant(0, VT), N0);
1611 // fold (mul x, (1 << c)) -> x << c
1612 if (N1C && N1C->getAPIntValue().isPowerOf2())
1613 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1614 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1615 getShiftAmountTy()));
1616 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1617 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1618 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1619 // FIXME: If the input is something that is easily negated (e.g. a
1620 // single-use add), we should put the negate there.
1621 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1622 DAG.getConstant(0, VT),
1623 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1624 DAG.getConstant(Log2Val, getShiftAmountTy())));
1626 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1627 if (N1C && N0.getOpcode() == ISD::SHL &&
1628 isa<ConstantSDNode>(N0.getOperand(1))) {
1629 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1630 N1, N0.getOperand(1));
1631 AddToWorkList(C3.getNode());
1632 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1633 N0.getOperand(0), C3);
1636 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1639 SDValue Sh(0,0), Y(0,0);
1640 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1641 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1642 N0.getNode()->hasOneUse()) {
1644 } else if (N1.getOpcode() == ISD::SHL &&
1645 isa<ConstantSDNode>(N1.getOperand(1)) &&
1646 N1.getNode()->hasOneUse()) {
1651 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1652 Sh.getOperand(0), Y);
1653 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1654 Mul, Sh.getOperand(1));
1658 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1659 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1660 isa<ConstantSDNode>(N0.getOperand(1)))
1661 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1662 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1663 N0.getOperand(0), N1),
1664 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1665 N0.getOperand(1), N1));
1668 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1669 if (RMUL.getNode() != 0)
1675 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1676 SDValue N0 = N->getOperand(0);
1677 SDValue N1 = N->getOperand(1);
1678 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1679 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1680 EVT VT = N->getValueType(0);
1683 if (VT.isVector()) {
1684 SDValue FoldedVOp = SimplifyVBinOp(N);
1685 if (FoldedVOp.getNode()) return FoldedVOp;
1688 // fold (sdiv c1, c2) -> c1/c2
1689 if (N0C && N1C && !N1C->isNullValue())
1690 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1691 // fold (sdiv X, 1) -> X
1692 if (N1C && N1C->getSExtValue() == 1LL)
1694 // fold (sdiv X, -1) -> 0-X
1695 if (N1C && N1C->isAllOnesValue())
1696 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1697 DAG.getConstant(0, VT), N0);
1698 // If we know the sign bits of both operands are zero, strength reduce to a
1699 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1700 if (!VT.isVector()) {
1701 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1702 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1705 // fold (sdiv X, pow2) -> simple ops after legalize
1706 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
1707 (isPowerOf2_64(N1C->getSExtValue()) ||
1708 isPowerOf2_64(-N1C->getSExtValue()))) {
1709 // If dividing by powers of two is cheap, then don't perform the following
1711 if (TLI.isPow2DivCheap())
1714 int64_t pow2 = N1C->getSExtValue();
1715 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1716 unsigned lg2 = Log2_64(abs2);
1718 // Splat the sign bit into the register
1719 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1720 DAG.getConstant(VT.getSizeInBits()-1,
1721 getShiftAmountTy()));
1722 AddToWorkList(SGN.getNode());
1724 // Add (N0 < 0) ? abs2 - 1 : 0;
1725 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1726 DAG.getConstant(VT.getSizeInBits() - lg2,
1727 getShiftAmountTy()));
1728 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1729 AddToWorkList(SRL.getNode());
1730 AddToWorkList(ADD.getNode()); // Divide by pow2
1731 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1732 DAG.getConstant(lg2, getShiftAmountTy()));
1734 // If we're dividing by a positive value, we're done. Otherwise, we must
1735 // negate the result.
1739 AddToWorkList(SRA.getNode());
1740 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1741 DAG.getConstant(0, VT), SRA);
1744 // if integer divide is expensive and we satisfy the requirements, emit an
1745 // alternate sequence.
1746 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
1747 !TLI.isIntDivCheap()) {
1748 SDValue Op = BuildSDIV(N);
1749 if (Op.getNode()) return Op;
1753 if (N0.getOpcode() == ISD::UNDEF)
1754 return DAG.getConstant(0, VT);
1755 // X / undef -> undef
1756 if (N1.getOpcode() == ISD::UNDEF)
1762 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1763 SDValue N0 = N->getOperand(0);
1764 SDValue N1 = N->getOperand(1);
1765 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1766 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1767 EVT VT = N->getValueType(0);
1770 if (VT.isVector()) {
1771 SDValue FoldedVOp = SimplifyVBinOp(N);
1772 if (FoldedVOp.getNode()) return FoldedVOp;
1775 // fold (udiv c1, c2) -> c1/c2
1776 if (N0C && N1C && !N1C->isNullValue())
1777 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1778 // fold (udiv x, (1 << c)) -> x >>u c
1779 if (N1C && N1C->getAPIntValue().isPowerOf2())
1780 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1781 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1782 getShiftAmountTy()));
1783 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1784 if (N1.getOpcode() == ISD::SHL) {
1785 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1786 if (SHC->getAPIntValue().isPowerOf2()) {
1787 EVT ADDVT = N1.getOperand(1).getValueType();
1788 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1790 DAG.getConstant(SHC->getAPIntValue()
1793 AddToWorkList(Add.getNode());
1794 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1798 // fold (udiv x, c) -> alternate
1799 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1800 SDValue Op = BuildUDIV(N);
1801 if (Op.getNode()) return Op;
1805 if (N0.getOpcode() == ISD::UNDEF)
1806 return DAG.getConstant(0, VT);
1807 // X / undef -> undef
1808 if (N1.getOpcode() == ISD::UNDEF)
1814 SDValue DAGCombiner::visitSREM(SDNode *N) {
1815 SDValue N0 = N->getOperand(0);
1816 SDValue N1 = N->getOperand(1);
1817 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1818 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1819 EVT VT = N->getValueType(0);
1821 // fold (srem c1, c2) -> c1%c2
1822 if (N0C && N1C && !N1C->isNullValue())
1823 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1824 // If we know the sign bits of both operands are zero, strength reduce to a
1825 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1826 if (!VT.isVector()) {
1827 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1828 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1831 // If X/C can be simplified by the division-by-constant logic, lower
1832 // X%C to the equivalent of X-X/C*C.
1833 if (N1C && !N1C->isNullValue()) {
1834 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1835 AddToWorkList(Div.getNode());
1836 SDValue OptimizedDiv = combine(Div.getNode());
1837 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1838 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1840 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1841 AddToWorkList(Mul.getNode());
1847 if (N0.getOpcode() == ISD::UNDEF)
1848 return DAG.getConstant(0, VT);
1849 // X % undef -> undef
1850 if (N1.getOpcode() == ISD::UNDEF)
1856 SDValue DAGCombiner::visitUREM(SDNode *N) {
1857 SDValue N0 = N->getOperand(0);
1858 SDValue N1 = N->getOperand(1);
1859 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1860 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1861 EVT VT = N->getValueType(0);
1863 // fold (urem c1, c2) -> c1%c2
1864 if (N0C && N1C && !N1C->isNullValue())
1865 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
1866 // fold (urem x, pow2) -> (and x, pow2-1)
1867 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
1868 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
1869 DAG.getConstant(N1C->getAPIntValue()-1,VT));
1870 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1871 if (N1.getOpcode() == ISD::SHL) {
1872 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1873 if (SHC->getAPIntValue().isPowerOf2()) {
1875 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
1876 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
1878 AddToWorkList(Add.getNode());
1879 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
1884 // If X/C can be simplified by the division-by-constant logic, lower
1885 // X%C to the equivalent of X-X/C*C.
1886 if (N1C && !N1C->isNullValue()) {
1887 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
1888 AddToWorkList(Div.getNode());
1889 SDValue OptimizedDiv = combine(Div.getNode());
1890 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1891 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1893 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1894 AddToWorkList(Mul.getNode());
1900 if (N0.getOpcode() == ISD::UNDEF)
1901 return DAG.getConstant(0, VT);
1902 // X % undef -> undef
1903 if (N1.getOpcode() == ISD::UNDEF)
1909 SDValue DAGCombiner::visitMULHS(SDNode *N) {
1910 SDValue N0 = N->getOperand(0);
1911 SDValue N1 = N->getOperand(1);
1912 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1913 EVT VT = N->getValueType(0);
1915 // fold (mulhs x, 0) -> 0
1916 if (N1C && N1C->isNullValue())
1918 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1919 if (N1C && N1C->getAPIntValue() == 1)
1920 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
1921 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
1922 getShiftAmountTy()));
1923 // fold (mulhs x, undef) -> 0
1924 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1925 return DAG.getConstant(0, VT);
1930 SDValue DAGCombiner::visitMULHU(SDNode *N) {
1931 SDValue N0 = N->getOperand(0);
1932 SDValue N1 = N->getOperand(1);
1933 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1934 EVT VT = N->getValueType(0);
1936 // fold (mulhu x, 0) -> 0
1937 if (N1C && N1C->isNullValue())
1939 // fold (mulhu x, 1) -> 0
1940 if (N1C && N1C->getAPIntValue() == 1)
1941 return DAG.getConstant(0, N0.getValueType());
1942 // fold (mulhu x, undef) -> 0
1943 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1944 return DAG.getConstant(0, VT);
1949 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1950 /// compute two values. LoOp and HiOp give the opcodes for the two computations
1951 /// that are being performed. Return true if a simplification was made.
1953 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
1955 // If the high half is not needed, just compute the low half.
1956 bool HiExists = N->hasAnyUseOfValue(1);
1958 (!LegalOperations ||
1959 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1960 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1961 N->op_begin(), N->getNumOperands());
1962 return CombineTo(N, Res, Res);
1965 // If the low half is not needed, just compute the high half.
1966 bool LoExists = N->hasAnyUseOfValue(0);
1968 (!LegalOperations ||
1969 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
1970 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1971 N->op_begin(), N->getNumOperands());
1972 return CombineTo(N, Res, Res);
1975 // If both halves are used, return as it is.
1976 if (LoExists && HiExists)
1979 // If the two computed results can be simplified separately, separate them.
1981 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1982 N->op_begin(), N->getNumOperands());
1983 AddToWorkList(Lo.getNode());
1984 SDValue LoOpt = combine(Lo.getNode());
1985 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
1986 (!LegalOperations ||
1987 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
1988 return CombineTo(N, LoOpt, LoOpt);
1992 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1993 N->op_begin(), N->getNumOperands());
1994 AddToWorkList(Hi.getNode());
1995 SDValue HiOpt = combine(Hi.getNode());
1996 if (HiOpt.getNode() && HiOpt != Hi &&
1997 (!LegalOperations ||
1998 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
1999 return CombineTo(N, HiOpt, HiOpt);
2005 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2006 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2007 if (Res.getNode()) return Res;
2012 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2013 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2014 if (Res.getNode()) return Res;
2019 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2020 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2021 if (Res.getNode()) return Res;
2026 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2027 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2028 if (Res.getNode()) return Res;
2033 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2034 /// two operands of the same opcode, try to simplify it.
2035 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2036 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2037 EVT VT = N0.getValueType();
2038 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2040 // Bail early if none of these transforms apply.
2041 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2043 // For each of OP in AND/OR/XOR:
2044 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2045 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2046 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2047 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2049 // do not sink logical op inside of a vector extend, since it may combine
2051 EVT Op0VT = N0.getOperand(0).getValueType();
2052 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2053 N0.getOpcode() == ISD::SIGN_EXTEND ||
2054 // Avoid infinite looping with PromoteIntBinOp.
2055 (N0.getOpcode() == ISD::ANY_EXTEND &&
2056 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2057 (N0.getOpcode() == ISD::TRUNCATE &&
2058 (!TLI.isZExtFree(VT, Op0VT) ||
2059 !TLI.isTruncateFree(Op0VT, VT)) &&
2060 TLI.isTypeLegal(Op0VT))) &&
2062 Op0VT == N1.getOperand(0).getValueType() &&
2063 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2064 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2065 N0.getOperand(0).getValueType(),
2066 N0.getOperand(0), N1.getOperand(0));
2067 AddToWorkList(ORNode.getNode());
2068 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
2071 // For each of OP in SHL/SRL/SRA/AND...
2072 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2073 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2074 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2075 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2076 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2077 N0.getOperand(1) == N1.getOperand(1)) {
2078 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2079 N0.getOperand(0).getValueType(),
2080 N0.getOperand(0), N1.getOperand(0));
2081 AddToWorkList(ORNode.getNode());
2082 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
2083 ORNode, N0.getOperand(1));
2089 SDValue DAGCombiner::visitAND(SDNode *N) {
2090 SDValue N0 = N->getOperand(0);
2091 SDValue N1 = N->getOperand(1);
2092 SDValue LL, LR, RL, RR, CC0, CC1;
2093 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2094 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2095 EVT VT = N1.getValueType();
2096 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2099 if (VT.isVector()) {
2100 SDValue FoldedVOp = SimplifyVBinOp(N);
2101 if (FoldedVOp.getNode()) return FoldedVOp;
2104 // fold (and x, undef) -> 0
2105 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2106 return DAG.getConstant(0, VT);
2107 // fold (and c1, c2) -> c1&c2
2109 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2110 // canonicalize constant to RHS
2112 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
2113 // fold (and x, -1) -> x
2114 if (N1C && N1C->isAllOnesValue())
2116 // if (and x, c) is known to be zero, return 0
2117 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2118 APInt::getAllOnesValue(BitWidth)))
2119 return DAG.getConstant(0, VT);
2121 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
2122 if (RAND.getNode() != 0)
2124 // fold (and (or x, C), D) -> D if (C & D) == D
2125 if (N1C && N0.getOpcode() == ISD::OR)
2126 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2127 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2129 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2130 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2131 SDValue N0Op0 = N0.getOperand(0);
2132 APInt Mask = ~N1C->getAPIntValue();
2133 Mask.trunc(N0Op0.getValueSizeInBits());
2134 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2135 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
2136 N0.getValueType(), N0Op0);
2138 // Replace uses of the AND with uses of the Zero extend node.
2141 // We actually want to replace all uses of the any_extend with the
2142 // zero_extend, to avoid duplicating things. This will later cause this
2143 // AND to be folded.
2144 CombineTo(N0.getNode(), Zext);
2145 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2148 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2149 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2150 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2151 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2153 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2154 LL.getValueType().isInteger()) {
2155 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2156 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2157 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2158 LR.getValueType(), LL, RL);
2159 AddToWorkList(ORNode.getNode());
2160 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2162 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2163 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2164 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
2165 LR.getValueType(), LL, RL);
2166 AddToWorkList(ANDNode.getNode());
2167 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2169 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2170 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2171 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2172 LR.getValueType(), LL, RL);
2173 AddToWorkList(ORNode.getNode());
2174 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2177 // canonicalize equivalent to ll == rl
2178 if (LL == RR && LR == RL) {
2179 Op1 = ISD::getSetCCSwappedOperands(Op1);
2182 if (LL == RL && LR == RR) {
2183 bool isInteger = LL.getValueType().isInteger();
2184 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2185 if (Result != ISD::SETCC_INVALID &&
2186 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2187 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2192 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2193 if (N0.getOpcode() == N1.getOpcode()) {
2194 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2195 if (Tmp.getNode()) return Tmp;
2198 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2199 // fold (and (sra)) -> (and (srl)) when possible.
2200 if (!VT.isVector() &&
2201 SimplifyDemandedBits(SDValue(N, 0)))
2202 return SDValue(N, 0);
2204 // fold (zext_inreg (extload x)) -> (zextload x)
2205 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2206 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2207 EVT MemVT = LN0->getMemoryVT();
2208 // If we zero all the possible extended bits, then we can turn this into
2209 // a zextload if we are running before legalize or the operation is legal.
2210 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2211 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2212 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2213 ((!LegalOperations && !LN0->isVolatile()) ||
2214 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2215 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getDebugLoc(),
2216 LN0->getChain(), LN0->getBasePtr(),
2217 LN0->getPointerInfo(), MemVT,
2218 LN0->isVolatile(), LN0->isNonTemporal(),
2219 LN0->getAlignment());
2221 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2222 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2225 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2226 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2228 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2229 EVT MemVT = LN0->getMemoryVT();
2230 // If we zero all the possible extended bits, then we can turn this into
2231 // a zextload if we are running before legalize or the operation is legal.
2232 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2233 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2234 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2235 ((!LegalOperations && !LN0->isVolatile()) ||
2236 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2237 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getDebugLoc(),
2239 LN0->getBasePtr(), LN0->getPointerInfo(),
2241 LN0->isVolatile(), LN0->isNonTemporal(),
2242 LN0->getAlignment());
2244 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2245 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2249 // fold (and (load x), 255) -> (zextload x, i8)
2250 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2251 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2252 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2253 (N0.getOpcode() == ISD::ANY_EXTEND &&
2254 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2255 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2256 LoadSDNode *LN0 = HasAnyExt
2257 ? cast<LoadSDNode>(N0.getOperand(0))
2258 : cast<LoadSDNode>(N0);
2259 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2260 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2261 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2262 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2263 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2264 EVT LoadedVT = LN0->getMemoryVT();
2266 if (ExtVT == LoadedVT &&
2267 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2268 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2271 DAG.getExtLoad(ISD::ZEXTLOAD, LoadResultTy, LN0->getDebugLoc(),
2272 LN0->getChain(), LN0->getBasePtr(),
2273 LN0->getPointerInfo(),
2274 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2275 LN0->getAlignment());
2277 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2278 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2281 // Do not change the width of a volatile load.
2282 // Do not generate loads of non-round integer types since these can
2283 // be expensive (and would be wrong if the type is not byte sized).
2284 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2285 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2286 EVT PtrType = LN0->getOperand(1).getValueType();
2288 unsigned Alignment = LN0->getAlignment();
2289 SDValue NewPtr = LN0->getBasePtr();
2291 // For big endian targets, we need to add an offset to the pointer
2292 // to load the correct bytes. For little endian systems, we merely
2293 // need to read fewer bytes from the same pointer.
2294 if (TLI.isBigEndian()) {
2295 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2296 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2297 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2298 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2299 NewPtr, DAG.getConstant(PtrOff, PtrType));
2300 Alignment = MinAlign(Alignment, PtrOff);
2303 AddToWorkList(NewPtr.getNode());
2305 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2307 DAG.getExtLoad(ISD::ZEXTLOAD, LoadResultTy, LN0->getDebugLoc(),
2308 LN0->getChain(), NewPtr,
2309 LN0->getPointerInfo(),
2310 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2313 CombineTo(LN0, Load, Load.getValue(1));
2314 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2323 SDValue DAGCombiner::visitOR(SDNode *N) {
2324 SDValue N0 = N->getOperand(0);
2325 SDValue N1 = N->getOperand(1);
2326 SDValue LL, LR, RL, RR, CC0, CC1;
2327 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2328 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2329 EVT VT = N1.getValueType();
2332 if (VT.isVector()) {
2333 SDValue FoldedVOp = SimplifyVBinOp(N);
2334 if (FoldedVOp.getNode()) return FoldedVOp;
2337 // fold (or x, undef) -> -1
2338 if (!LegalOperations &&
2339 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
2340 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
2341 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
2343 // fold (or c1, c2) -> c1|c2
2345 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
2346 // canonicalize constant to RHS
2348 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
2349 // fold (or x, 0) -> x
2350 if (N1C && N1C->isNullValue())
2352 // fold (or x, -1) -> -1
2353 if (N1C && N1C->isAllOnesValue())
2355 // fold (or x, c) -> c iff (x & ~c) == 0
2356 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
2359 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
2360 if (ROR.getNode() != 0)
2362 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
2363 // iff (c1 & c2) == 0.
2364 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
2365 isa<ConstantSDNode>(N0.getOperand(1))) {
2366 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
2367 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
2368 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
2369 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2370 N0.getOperand(0), N1),
2371 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
2373 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
2374 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2375 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2376 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2378 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2379 LL.getValueType().isInteger()) {
2380 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
2381 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
2382 if (cast<ConstantSDNode>(LR)->isNullValue() &&
2383 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
2384 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
2385 LR.getValueType(), LL, RL);
2386 AddToWorkList(ORNode.getNode());
2387 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2389 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
2390 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
2391 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2392 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
2393 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
2394 LR.getValueType(), LL, RL);
2395 AddToWorkList(ANDNode.getNode());
2396 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2399 // canonicalize equivalent to ll == rl
2400 if (LL == RR && LR == RL) {
2401 Op1 = ISD::getSetCCSwappedOperands(Op1);
2404 if (LL == RL && LR == RR) {
2405 bool isInteger = LL.getValueType().isInteger();
2406 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
2407 if (Result != ISD::SETCC_INVALID &&
2408 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2409 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2414 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
2415 if (N0.getOpcode() == N1.getOpcode()) {
2416 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2417 if (Tmp.getNode()) return Tmp;
2420 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
2421 if (N0.getOpcode() == ISD::AND &&
2422 N1.getOpcode() == ISD::AND &&
2423 N0.getOperand(1).getOpcode() == ISD::Constant &&
2424 N1.getOperand(1).getOpcode() == ISD::Constant &&
2425 // Don't increase # computations.
2426 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
2427 // We can only do this xform if we know that bits from X that are set in C2
2428 // but not in C1 are already zero. Likewise for Y.
2429 const APInt &LHSMask =
2430 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2431 const APInt &RHSMask =
2432 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
2434 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
2435 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
2436 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2437 N0.getOperand(0), N1.getOperand(0));
2438 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
2439 DAG.getConstant(LHSMask | RHSMask, VT));
2443 // See if this is some rotate idiom.
2444 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
2445 return SDValue(Rot, 0);
2447 // Simplify the operands using demanded-bits information.
2448 if (!VT.isVector() &&
2449 SimplifyDemandedBits(SDValue(N, 0)))
2450 return SDValue(N, 0);
2455 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
2456 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
2457 if (Op.getOpcode() == ISD::AND) {
2458 if (isa<ConstantSDNode>(Op.getOperand(1))) {
2459 Mask = Op.getOperand(1);
2460 Op = Op.getOperand(0);
2466 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
2474 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
2475 // idioms for rotate, and if the target supports rotation instructions, generate
2477 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
2478 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
2479 EVT VT = LHS.getValueType();
2480 if (!TLI.isTypeLegal(VT)) return 0;
2482 // The target must have at least one rotate flavor.
2483 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
2484 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
2485 if (!HasROTL && !HasROTR) return 0;
2487 // Match "(X shl/srl V1) & V2" where V2 may not be present.
2488 SDValue LHSShift; // The shift.
2489 SDValue LHSMask; // AND value if any.
2490 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
2491 return 0; // Not part of a rotate.
2493 SDValue RHSShift; // The shift.
2494 SDValue RHSMask; // AND value if any.
2495 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
2496 return 0; // Not part of a rotate.
2498 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
2499 return 0; // Not shifting the same value.
2501 if (LHSShift.getOpcode() == RHSShift.getOpcode())
2502 return 0; // Shifts must disagree.
2504 // Canonicalize shl to left side in a shl/srl pair.
2505 if (RHSShift.getOpcode() == ISD::SHL) {
2506 std::swap(LHS, RHS);
2507 std::swap(LHSShift, RHSShift);
2508 std::swap(LHSMask , RHSMask );
2511 unsigned OpSizeInBits = VT.getSizeInBits();
2512 SDValue LHSShiftArg = LHSShift.getOperand(0);
2513 SDValue LHSShiftAmt = LHSShift.getOperand(1);
2514 SDValue RHSShiftAmt = RHSShift.getOperand(1);
2516 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
2517 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
2518 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
2519 RHSShiftAmt.getOpcode() == ISD::Constant) {
2520 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
2521 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
2522 if ((LShVal + RShVal) != OpSizeInBits)
2527 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
2529 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
2531 // If there is an AND of either shifted operand, apply it to the result.
2532 if (LHSMask.getNode() || RHSMask.getNode()) {
2533 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
2535 if (LHSMask.getNode()) {
2536 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
2537 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
2539 if (RHSMask.getNode()) {
2540 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
2541 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
2544 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
2547 return Rot.getNode();
2550 // If there is a mask here, and we have a variable shift, we can't be sure
2551 // that we're masking out the right stuff.
2552 if (LHSMask.getNode() || RHSMask.getNode())
2555 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
2556 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
2557 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
2558 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
2559 if (ConstantSDNode *SUBC =
2560 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
2561 if (SUBC->getAPIntValue() == OpSizeInBits) {
2563 return DAG.getNode(ISD::ROTL, DL, VT,
2564 LHSShiftArg, LHSShiftAmt).getNode();
2566 return DAG.getNode(ISD::ROTR, DL, VT,
2567 LHSShiftArg, RHSShiftAmt).getNode();
2572 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2573 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
2574 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
2575 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
2576 if (ConstantSDNode *SUBC =
2577 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
2578 if (SUBC->getAPIntValue() == OpSizeInBits) {
2580 return DAG.getNode(ISD::ROTR, DL, VT,
2581 LHSShiftArg, RHSShiftAmt).getNode();
2583 return DAG.getNode(ISD::ROTL, DL, VT,
2584 LHSShiftArg, LHSShiftAmt).getNode();
2589 // Look for sign/zext/any-extended or truncate cases:
2590 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2591 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2592 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2593 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
2594 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2595 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2596 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2597 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
2598 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
2599 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
2600 if (RExtOp0.getOpcode() == ISD::SUB &&
2601 RExtOp0.getOperand(1) == LExtOp0) {
2602 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2604 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2605 // (rotr x, (sub 32, y))
2606 if (ConstantSDNode *SUBC =
2607 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
2608 if (SUBC->getAPIntValue() == OpSizeInBits) {
2609 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
2611 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
2614 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2615 RExtOp0 == LExtOp0.getOperand(1)) {
2616 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2618 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2619 // (rotl x, (sub 32, y))
2620 if (ConstantSDNode *SUBC =
2621 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2622 if (SUBC->getAPIntValue() == OpSizeInBits) {
2623 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
2625 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
2634 SDValue DAGCombiner::visitXOR(SDNode *N) {
2635 SDValue N0 = N->getOperand(0);
2636 SDValue N1 = N->getOperand(1);
2637 SDValue LHS, RHS, CC;
2638 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2639 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2640 EVT VT = N0.getValueType();
2643 if (VT.isVector()) {
2644 SDValue FoldedVOp = SimplifyVBinOp(N);
2645 if (FoldedVOp.getNode()) return FoldedVOp;
2648 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
2649 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
2650 return DAG.getConstant(0, VT);
2651 // fold (xor x, undef) -> undef
2652 if (N0.getOpcode() == ISD::UNDEF)
2654 if (N1.getOpcode() == ISD::UNDEF)
2656 // fold (xor c1, c2) -> c1^c2
2658 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
2659 // canonicalize constant to RHS
2661 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
2662 // fold (xor x, 0) -> x
2663 if (N1C && N1C->isNullValue())
2666 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
2667 if (RXOR.getNode() != 0)
2670 // fold !(x cc y) -> (x !cc y)
2671 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2672 bool isInt = LHS.getValueType().isInteger();
2673 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2676 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
2677 switch (N0.getOpcode()) {
2679 llvm_unreachable("Unhandled SetCC Equivalent!");
2681 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
2682 case ISD::SELECT_CC:
2683 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
2684 N0.getOperand(3), NotCC);
2689 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2690 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2691 N0.getNode()->hasOneUse() &&
2692 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2693 SDValue V = N0.getOperand(0);
2694 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
2695 DAG.getConstant(1, V.getValueType()));
2696 AddToWorkList(V.getNode());
2697 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
2700 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
2701 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
2702 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2703 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2704 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2705 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2706 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2707 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2708 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2709 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2712 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
2713 if (N1C && N1C->isAllOnesValue() &&
2714 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2715 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2716 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2717 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2718 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2719 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2720 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2721 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2724 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
2725 if (N1C && N0.getOpcode() == ISD::XOR) {
2726 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2727 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2729 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
2730 DAG.getConstant(N1C->getAPIntValue() ^
2731 N00C->getAPIntValue(), VT));
2733 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
2734 DAG.getConstant(N1C->getAPIntValue() ^
2735 N01C->getAPIntValue(), VT));
2737 // fold (xor x, x) -> 0
2739 if (!VT.isVector()) {
2740 return DAG.getConstant(0, VT);
2741 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){
2742 // Produce a vector of zeros.
2743 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
2744 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
2745 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
2746 &Ops[0], Ops.size());
2750 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2751 if (N0.getOpcode() == N1.getOpcode()) {
2752 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2753 if (Tmp.getNode()) return Tmp;
2756 // Simplify the expression using non-local knowledge.
2757 if (!VT.isVector() &&
2758 SimplifyDemandedBits(SDValue(N, 0)))
2759 return SDValue(N, 0);
2764 /// visitShiftByConstant - Handle transforms common to the three shifts, when
2765 /// the shift amount is a constant.
2766 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
2767 SDNode *LHS = N->getOperand(0).getNode();
2768 if (!LHS->hasOneUse()) return SDValue();
2770 // We want to pull some binops through shifts, so that we have (and (shift))
2771 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
2772 // thing happens with address calculations, so it's important to canonicalize
2774 bool HighBitSet = false; // Can we transform this if the high bit is set?
2776 switch (LHS->getOpcode()) {
2777 default: return SDValue();
2780 HighBitSet = false; // We can only transform sra if the high bit is clear.
2783 HighBitSet = true; // We can only transform sra if the high bit is set.
2786 if (N->getOpcode() != ISD::SHL)
2787 return SDValue(); // only shl(add) not sr[al](add).
2788 HighBitSet = false; // We can only transform sra if the high bit is clear.
2792 // We require the RHS of the binop to be a constant as well.
2793 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
2794 if (!BinOpCst) return SDValue();
2796 // FIXME: disable this unless the input to the binop is a shift by a constant.
2797 // If it is not a shift, it pessimizes some common cases like:
2799 // void foo(int *X, int i) { X[i & 1235] = 1; }
2800 // int bar(int *X, int i) { return X[i & 255]; }
2801 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
2802 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
2803 BinOpLHSVal->getOpcode() != ISD::SRA &&
2804 BinOpLHSVal->getOpcode() != ISD::SRL) ||
2805 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
2808 EVT VT = N->getValueType(0);
2810 // If this is a signed shift right, and the high bit is modified by the
2811 // logical operation, do not perform the transformation. The highBitSet
2812 // boolean indicates the value of the high bit of the constant which would
2813 // cause it to be modified for this operation.
2814 if (N->getOpcode() == ISD::SRA) {
2815 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
2816 if (BinOpRHSSignSet != HighBitSet)
2820 // Fold the constants, shifting the binop RHS by the shift amount.
2821 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
2823 LHS->getOperand(1), N->getOperand(1));
2825 // Create the new shift.
2826 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(),
2827 VT, LHS->getOperand(0), N->getOperand(1));
2829 // Create the new binop.
2830 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
2833 SDValue DAGCombiner::visitSHL(SDNode *N) {
2834 SDValue N0 = N->getOperand(0);
2835 SDValue N1 = N->getOperand(1);
2836 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2837 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2838 EVT VT = N0.getValueType();
2839 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
2841 // fold (shl c1, c2) -> c1<<c2
2843 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
2844 // fold (shl 0, x) -> 0
2845 if (N0C && N0C->isNullValue())
2847 // fold (shl x, c >= size(x)) -> undef
2848 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2849 return DAG.getUNDEF(VT);
2850 // fold (shl x, 0) -> x
2851 if (N1C && N1C->isNullValue())
2853 // if (shl x, c) is known to be zero, return 0
2854 if (DAG.MaskedValueIsZero(SDValue(N, 0),
2855 APInt::getAllOnesValue(OpSizeInBits)))
2856 return DAG.getConstant(0, VT);
2857 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
2858 if (N1.getOpcode() == ISD::TRUNCATE &&
2859 N1.getOperand(0).getOpcode() == ISD::AND &&
2860 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2861 SDValue N101 = N1.getOperand(0).getOperand(1);
2862 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2863 EVT TruncVT = N1.getValueType();
2864 SDValue N100 = N1.getOperand(0).getOperand(0);
2865 APInt TruncC = N101C->getAPIntValue();
2866 TruncC.trunc(TruncVT.getSizeInBits());
2867 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
2868 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
2869 DAG.getNode(ISD::TRUNCATE,
2872 DAG.getConstant(TruncC, TruncVT)));
2876 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2877 return SDValue(N, 0);
2879 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
2880 if (N1C && N0.getOpcode() == ISD::SHL &&
2881 N0.getOperand(1).getOpcode() == ISD::Constant) {
2882 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2883 uint64_t c2 = N1C->getZExtValue();
2884 if (c1 + c2 > OpSizeInBits)
2885 return DAG.getConstant(0, VT);
2886 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
2887 DAG.getConstant(c1 + c2, N1.getValueType()));
2889 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or
2890 // (srl (and x, (shl -1, c1)), (sub c1, c2))
2891 if (N1C && N0.getOpcode() == ISD::SRL &&
2892 N0.getOperand(1).getOpcode() == ISD::Constant) {
2893 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2894 if (c1 < VT.getSizeInBits()) {
2895 uint64_t c2 = N1C->getZExtValue();
2896 SDValue HiBitsMask =
2897 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
2898 VT.getSizeInBits() - c1),
2900 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT,
2904 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask,
2905 DAG.getConstant(c2-c1, N1.getValueType()));
2907 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask,
2908 DAG.getConstant(c1-c2, N1.getValueType()));
2911 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
2912 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
2913 SDValue HiBitsMask =
2914 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
2915 VT.getSizeInBits() -
2916 N1C->getZExtValue()),
2918 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
2923 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
2924 if (NewSHL.getNode())
2931 SDValue DAGCombiner::visitSRA(SDNode *N) {
2932 SDValue N0 = N->getOperand(0);
2933 SDValue N1 = N->getOperand(1);
2934 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2935 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2936 EVT VT = N0.getValueType();
2937 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
2939 // fold (sra c1, c2) -> (sra c1, c2)
2941 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
2942 // fold (sra 0, x) -> 0
2943 if (N0C && N0C->isNullValue())
2945 // fold (sra -1, x) -> -1
2946 if (N0C && N0C->isAllOnesValue())
2948 // fold (sra x, (setge c, size(x))) -> undef
2949 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2950 return DAG.getUNDEF(VT);
2951 // fold (sra x, 0) -> x
2952 if (N1C && N1C->isNullValue())
2954 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2956 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2957 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
2958 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
2960 ExtVT = EVT::getVectorVT(*DAG.getContext(),
2961 ExtVT, VT.getVectorNumElements());
2962 if ((!LegalOperations ||
2963 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
2964 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
2965 N0.getOperand(0), DAG.getValueType(ExtVT));
2968 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
2969 if (N1C && N0.getOpcode() == ISD::SRA) {
2970 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2971 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
2972 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
2973 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
2974 DAG.getConstant(Sum, N1C->getValueType(0)));
2978 // fold (sra (shl X, m), (sub result_size, n))
2979 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
2980 // result_size - n != m.
2981 // If truncate is free for the target sext(shl) is likely to result in better
2983 if (N0.getOpcode() == ISD::SHL) {
2984 // Get the two constanst of the shifts, CN0 = m, CN = n.
2985 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2987 // Determine what the truncate's result bitsize and type would be.
2989 EVT::getIntegerVT(*DAG.getContext(), OpSizeInBits - N1C->getZExtValue());
2990 // Determine the residual right-shift amount.
2991 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
2993 // If the shift is not a no-op (in which case this should be just a sign
2994 // extend already), the truncated to type is legal, sign_extend is legal
2995 // on that type, and the truncate to that type is both legal and free,
2996 // perform the transform.
2997 if ((ShiftAmt > 0) &&
2998 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
2999 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
3000 TLI.isTruncateFree(VT, TruncVT)) {
3002 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy());
3003 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3004 N0.getOperand(0), Amt);
3005 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
3007 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
3008 N->getValueType(0), Trunc);
3013 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
3014 if (N1.getOpcode() == ISD::TRUNCATE &&
3015 N1.getOperand(0).getOpcode() == ISD::AND &&
3016 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3017 SDValue N101 = N1.getOperand(0).getOperand(1);
3018 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3019 EVT TruncVT = N1.getValueType();
3020 SDValue N100 = N1.getOperand(0).getOperand(0);
3021 APInt TruncC = N101C->getAPIntValue();
3022 TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
3023 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
3024 DAG.getNode(ISD::AND, N->getDebugLoc(),
3026 DAG.getNode(ISD::TRUNCATE,
3029 DAG.getConstant(TruncC, TruncVT)));
3033 // Simplify, based on bits shifted out of the LHS.
3034 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3035 return SDValue(N, 0);
3038 // If the sign bit is known to be zero, switch this to a SRL.
3039 if (DAG.SignBitIsZero(N0))
3040 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3043 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
3044 if (NewSRA.getNode())
3051 SDValue DAGCombiner::visitSRL(SDNode *N) {
3052 SDValue N0 = N->getOperand(0);
3053 SDValue N1 = N->getOperand(1);
3054 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3055 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3056 EVT VT = N0.getValueType();
3057 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3059 // fold (srl c1, c2) -> c1 >>u c2
3061 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3062 // fold (srl 0, x) -> 0
3063 if (N0C && N0C->isNullValue())
3065 // fold (srl x, c >= size(x)) -> undef
3066 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3067 return DAG.getUNDEF(VT);
3068 // fold (srl x, 0) -> x
3069 if (N1C && N1C->isNullValue())
3071 // if (srl x, c) is known to be zero, return 0
3072 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3073 APInt::getAllOnesValue(OpSizeInBits)))
3074 return DAG.getConstant(0, VT);
3076 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3077 if (N1C && N0.getOpcode() == ISD::SRL &&
3078 N0.getOperand(1).getOpcode() == ISD::Constant) {
3079 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3080 uint64_t c2 = N1C->getZExtValue();
3081 if (c1 + c2 > OpSizeInBits)
3082 return DAG.getConstant(0, VT);
3083 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3084 DAG.getConstant(c1 + c2, N1.getValueType()));
3087 // fold (srl (shl x, c), c) -> (and x, cst2)
3088 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3089 N0.getValueSizeInBits() <= 64) {
3090 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3091 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3092 DAG.getConstant(~0ULL >> ShAmt, VT));
3096 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3097 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3098 // Shifting in all undef bits?
3099 EVT SmallVT = N0.getOperand(0).getValueType();
3100 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
3101 return DAG.getUNDEF(VT);
3103 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3104 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3105 N0.getOperand(0), N1);
3106 AddToWorkList(SmallShift.getNode());
3107 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
3111 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
3112 // bit, which is unmodified by sra.
3113 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
3114 if (N0.getOpcode() == ISD::SRA)
3115 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3118 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3119 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3120 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
3121 APInt KnownZero, KnownOne;
3122 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
3123 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
3125 // If any of the input bits are KnownOne, then the input couldn't be all
3126 // zeros, thus the result of the srl will always be zero.
3127 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
3129 // If all of the bits input the to ctlz node are known to be zero, then
3130 // the result of the ctlz is "32" and the result of the shift is one.
3131 APInt UnknownBits = ~KnownZero & Mask;
3132 if (UnknownBits == 0) return DAG.getConstant(1, VT);
3134 // Otherwise, check to see if there is exactly one bit input to the ctlz.
3135 if ((UnknownBits & (UnknownBits - 1)) == 0) {
3136 // Okay, we know that only that the single bit specified by UnknownBits
3137 // could be set on input to the CTLZ node. If this bit is set, the SRL
3138 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3139 // to an SRL/XOR pair, which is likely to simplify more.
3140 unsigned ShAmt = UnknownBits.countTrailingZeros();
3141 SDValue Op = N0.getOperand(0);
3144 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3145 DAG.getConstant(ShAmt, getShiftAmountTy()));
3146 AddToWorkList(Op.getNode());
3149 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3150 Op, DAG.getConstant(1, VT));
3154 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3155 if (N1.getOpcode() == ISD::TRUNCATE &&
3156 N1.getOperand(0).getOpcode() == ISD::AND &&
3157 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3158 SDValue N101 = N1.getOperand(0).getOperand(1);
3159 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3160 EVT TruncVT = N1.getValueType();
3161 SDValue N100 = N1.getOperand(0).getOperand(0);
3162 APInt TruncC = N101C->getAPIntValue();
3163 TruncC.trunc(TruncVT.getSizeInBits());
3164 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3165 DAG.getNode(ISD::AND, N->getDebugLoc(),
3167 DAG.getNode(ISD::TRUNCATE,
3170 DAG.getConstant(TruncC, TruncVT)));
3174 // fold operands of srl based on knowledge that the low bits are not
3176 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3177 return SDValue(N, 0);
3180 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
3181 if (NewSRL.getNode())
3185 // Attempt to convert a srl of a load into a narrower zero-extending load.
3186 SDValue NarrowLoad = ReduceLoadWidth(N);
3187 if (NarrowLoad.getNode())
3190 // Here is a common situation. We want to optimize:
3193 // %b = and i32 %a, 2
3194 // %c = srl i32 %b, 1
3195 // brcond i32 %c ...
3201 // %c = setcc eq %b, 0
3204 // However when after the source operand of SRL is optimized into AND, the SRL
3205 // itself may not be optimized further. Look for it and add the BRCOND into
3207 if (N->hasOneUse()) {
3208 SDNode *Use = *N->use_begin();
3209 if (Use->getOpcode() == ISD::BRCOND)
3211 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
3212 // Also look pass the truncate.
3213 Use = *Use->use_begin();
3214 if (Use->getOpcode() == ISD::BRCOND)
3222 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
3223 SDValue N0 = N->getOperand(0);
3224 EVT VT = N->getValueType(0);
3226 // fold (ctlz c1) -> c2
3227 if (isa<ConstantSDNode>(N0))
3228 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
3232 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
3233 SDValue N0 = N->getOperand(0);
3234 EVT VT = N->getValueType(0);
3236 // fold (cttz c1) -> c2
3237 if (isa<ConstantSDNode>(N0))
3238 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
3242 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
3243 SDValue N0 = N->getOperand(0);
3244 EVT VT = N->getValueType(0);
3246 // fold (ctpop c1) -> c2
3247 if (isa<ConstantSDNode>(N0))
3248 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
3252 SDValue DAGCombiner::visitSELECT(SDNode *N) {
3253 SDValue N0 = N->getOperand(0);
3254 SDValue N1 = N->getOperand(1);
3255 SDValue N2 = N->getOperand(2);
3256 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3257 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3258 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
3259 EVT VT = N->getValueType(0);
3260 EVT VT0 = N0.getValueType();
3262 // fold (select C, X, X) -> X
3265 // fold (select true, X, Y) -> X
3266 if (N0C && !N0C->isNullValue())
3268 // fold (select false, X, Y) -> Y
3269 if (N0C && N0C->isNullValue())
3271 // fold (select C, 1, X) -> (or C, X)
3272 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
3273 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3274 // fold (select C, 0, 1) -> (xor C, 1)
3275 if (VT.isInteger() &&
3278 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
3279 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
3282 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
3283 N0, DAG.getConstant(1, VT0));
3284 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
3285 N0, DAG.getConstant(1, VT0));
3286 AddToWorkList(XORNode.getNode());
3288 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
3289 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
3291 // fold (select C, 0, X) -> (and (not C), X)
3292 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
3293 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3294 AddToWorkList(NOTNode.getNode());
3295 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
3297 // fold (select C, X, 1) -> (or (not C), X)
3298 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
3299 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3300 AddToWorkList(NOTNode.getNode());
3301 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
3303 // fold (select C, X, 0) -> (and C, X)
3304 if (VT == MVT::i1 && N2C && N2C->isNullValue())
3305 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3306 // fold (select X, X, Y) -> (or X, Y)
3307 // fold (select X, 1, Y) -> (or X, Y)
3308 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
3309 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3310 // fold (select X, Y, X) -> (and X, Y)
3311 // fold (select X, Y, 0) -> (and X, Y)
3312 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
3313 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3315 // If we can fold this based on the true/false value, do so.
3316 if (SimplifySelectOps(N, N1, N2))
3317 return SDValue(N, 0); // Don't revisit N.
3319 // fold selects based on a setcc into other things, such as min/max/abs
3320 if (N0.getOpcode() == ISD::SETCC) {
3322 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
3323 // having to say they don't support SELECT_CC on every type the DAG knows
3324 // about, since there is no way to mark an opcode illegal at all value types
3325 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
3326 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
3327 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
3328 N0.getOperand(0), N0.getOperand(1),
3329 N1, N2, N0.getOperand(2));
3330 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
3336 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
3337 SDValue N0 = N->getOperand(0);
3338 SDValue N1 = N->getOperand(1);
3339 SDValue N2 = N->getOperand(2);
3340 SDValue N3 = N->getOperand(3);
3341 SDValue N4 = N->getOperand(4);
3342 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
3344 // fold select_cc lhs, rhs, x, x, cc -> x
3348 // Determine if the condition we're dealing with is constant
3349 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
3350 N0, N1, CC, N->getDebugLoc(), false);
3351 if (SCC.getNode()) AddToWorkList(SCC.getNode());
3353 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
3354 if (!SCCC->isNullValue())
3355 return N2; // cond always true -> true val
3357 return N3; // cond always false -> false val
3360 // Fold to a simpler select_cc
3361 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
3362 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
3363 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
3366 // If we can fold this based on the true/false value, do so.
3367 if (SimplifySelectOps(N, N2, N3))
3368 return SDValue(N, 0); // Don't revisit N.
3370 // fold select_cc into other things, such as min/max/abs
3371 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
3374 SDValue DAGCombiner::visitSETCC(SDNode *N) {
3375 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
3376 cast<CondCodeSDNode>(N->getOperand(2))->get(),
3380 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
3381 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
3382 // transformation. Returns true if extension are possible and the above
3383 // mentioned transformation is profitable.
3384 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
3386 SmallVector<SDNode*, 4> &ExtendNodes,
3387 const TargetLowering &TLI) {
3388 bool HasCopyToRegUses = false;
3389 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
3390 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
3391 UE = N0.getNode()->use_end();
3396 if (UI.getUse().getResNo() != N0.getResNo())
3398 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
3399 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
3400 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
3401 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
3402 // Sign bits will be lost after a zext.
3405 for (unsigned i = 0; i != 2; ++i) {
3406 SDValue UseOp = User->getOperand(i);
3409 if (!isa<ConstantSDNode>(UseOp))
3414 ExtendNodes.push_back(User);
3417 // If truncates aren't free and there are users we can't
3418 // extend, it isn't worthwhile.
3421 // Remember if this value is live-out.
3422 if (User->getOpcode() == ISD::CopyToReg)
3423 HasCopyToRegUses = true;
3426 if (HasCopyToRegUses) {
3427 bool BothLiveOut = false;
3428 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3430 SDUse &Use = UI.getUse();
3431 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
3437 // Both unextended and extended values are live out. There had better be
3438 // good a reason for the transformation.
3439 return ExtendNodes.size();
3444 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
3445 SDValue N0 = N->getOperand(0);
3446 EVT VT = N->getValueType(0);
3448 // fold (sext c1) -> c1
3449 if (isa<ConstantSDNode>(N0))
3450 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
3452 // fold (sext (sext x)) -> (sext x)
3453 // fold (sext (aext x)) -> (sext x)
3454 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3455 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
3458 if (N0.getOpcode() == ISD::TRUNCATE) {
3459 // fold (sext (truncate (load x))) -> (sext (smaller load x))
3460 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
3461 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3462 if (NarrowLoad.getNode()) {
3463 SDNode* oye = N0.getNode()->getOperand(0).getNode();
3464 if (NarrowLoad.getNode() != N0.getNode()) {
3465 CombineTo(N0.getNode(), NarrowLoad);
3466 // CombineTo deleted the truncate, if needed, but not what's under it.
3469 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3472 // See if the value being truncated is already sign extended. If so, just
3473 // eliminate the trunc/sext pair.
3474 SDValue Op = N0.getOperand(0);
3475 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
3476 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
3477 unsigned DestBits = VT.getScalarType().getSizeInBits();
3478 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
3480 if (OpBits == DestBits) {
3481 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
3482 // bits, it is already ready.
3483 if (NumSignBits > DestBits-MidBits)
3485 } else if (OpBits < DestBits) {
3486 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
3487 // bits, just sext from i32.
3488 if (NumSignBits > OpBits-MidBits)
3489 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
3491 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
3492 // bits, just truncate to i32.
3493 if (NumSignBits > OpBits-MidBits)
3494 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3497 // fold (sext (truncate x)) -> (sextinreg x).
3498 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
3499 N0.getValueType())) {
3500 if (OpBits < DestBits)
3501 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
3502 else if (OpBits > DestBits)
3503 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
3504 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
3505 DAG.getValueType(N0.getValueType()));
3509 // fold (sext (load x)) -> (sext (truncate (sextload x)))
3510 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3511 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3512 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
3513 bool DoXform = true;
3514 SmallVector<SDNode*, 4> SetCCs;
3515 if (!N0.hasOneUse())
3516 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
3518 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3519 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(),
3521 LN0->getBasePtr(), LN0->getPointerInfo(),
3523 LN0->isVolatile(), LN0->isNonTemporal(),
3524 LN0->getAlignment());
3525 CombineTo(N, ExtLoad);
3526 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3527 N0.getValueType(), ExtLoad);
3528 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3530 // Extend SetCC uses if necessary.
3531 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3532 SDNode *SetCC = SetCCs[i];
3533 SmallVector<SDValue, 4> Ops;
3535 for (unsigned j = 0; j != 2; ++j) {
3536 SDValue SOp = SetCC->getOperand(j);
3538 Ops.push_back(ExtLoad);
3540 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND,
3541 N->getDebugLoc(), VT, SOp));
3544 Ops.push_back(SetCC->getOperand(2));
3545 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3546 SetCC->getValueType(0),
3547 &Ops[0], Ops.size()));
3550 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3554 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
3555 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
3556 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3557 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3558 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3559 EVT MemVT = LN0->getMemoryVT();
3560 if ((!LegalOperations && !LN0->isVolatile()) ||
3561 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
3562 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(),
3564 LN0->getBasePtr(), LN0->getPointerInfo(),
3566 LN0->isVolatile(), LN0->isNonTemporal(),
3567 LN0->getAlignment());
3568 CombineTo(N, ExtLoad);
3569 CombineTo(N0.getNode(),
3570 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3571 N0.getValueType(), ExtLoad),
3572 ExtLoad.getValue(1));
3573 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3577 if (N0.getOpcode() == ISD::SETCC) {
3578 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
3579 // Only do this before legalize for now.
3580 if (VT.isVector() && !LegalOperations) {
3581 EVT N0VT = N0.getOperand(0).getValueType();
3582 // We know that the # elements of the results is the same as the
3583 // # elements of the compare (and the # elements of the compare result
3584 // for that matter). Check to see that they are the same size. If so,
3585 // we know that the element size of the sext'd result matches the
3586 // element size of the compare operands.
3587 if (VT.getSizeInBits() == N0VT.getSizeInBits())
3588 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
3590 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3591 // If the desired elements are smaller or larger than the source
3592 // elements we can use a matching integer vector type and then
3593 // truncate/sign extend
3595 EVT MatchingElementType =
3596 EVT::getIntegerVT(*DAG.getContext(),
3597 N0VT.getScalarType().getSizeInBits());
3598 EVT MatchingVectorType =
3599 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
3600 N0VT.getVectorNumElements());
3602 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
3604 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3605 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
3609 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
3610 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
3612 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
3614 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3615 NegOne, DAG.getConstant(0, VT),
3616 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3617 if (SCC.getNode()) return SCC;
3618 if (!LegalOperations ||
3619 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
3620 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
3621 DAG.getSetCC(N->getDebugLoc(),
3622 TLI.getSetCCResultType(VT),
3623 N0.getOperand(0), N0.getOperand(1),
3624 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
3625 NegOne, DAG.getConstant(0, VT));
3628 // fold (sext x) -> (zext x) if the sign bit is known zero.
3629 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
3630 DAG.SignBitIsZero(N0))
3631 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3636 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
3637 SDValue N0 = N->getOperand(0);
3638 EVT VT = N->getValueType(0);
3640 // fold (zext c1) -> c1
3641 if (isa<ConstantSDNode>(N0))
3642 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3643 // fold (zext (zext x)) -> (zext x)
3644 // fold (zext (aext x)) -> (zext x)
3645 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3646 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
3649 // fold (zext (truncate (load x))) -> (zext (smaller load x))
3650 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
3651 if (N0.getOpcode() == ISD::TRUNCATE) {
3652 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3653 if (NarrowLoad.getNode()) {
3654 SDNode* oye = N0.getNode()->getOperand(0).getNode();
3655 if (NarrowLoad.getNode() != N0.getNode()) {
3656 CombineTo(N0.getNode(), NarrowLoad);
3657 // CombineTo deleted the truncate, if needed, but not what's under it.
3660 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3664 // fold (zext (truncate x)) -> (and x, mask)
3665 if (N0.getOpcode() == ISD::TRUNCATE &&
3666 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
3667 SDValue Op = N0.getOperand(0);
3668 if (Op.getValueType().bitsLT(VT)) {
3669 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
3670 } else if (Op.getValueType().bitsGT(VT)) {
3671 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3673 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
3674 N0.getValueType().getScalarType());
3677 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
3678 // if either of the casts is not free.
3679 if (N0.getOpcode() == ISD::AND &&
3680 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3681 N0.getOperand(1).getOpcode() == ISD::Constant &&
3682 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3683 N0.getValueType()) ||
3684 !TLI.isZExtFree(N0.getValueType(), VT))) {
3685 SDValue X = N0.getOperand(0).getOperand(0);
3686 if (X.getValueType().bitsLT(VT)) {
3687 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
3688 } else if (X.getValueType().bitsGT(VT)) {
3689 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
3691 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3692 Mask.zext(VT.getSizeInBits());
3693 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3694 X, DAG.getConstant(Mask, VT));
3697 // fold (zext (load x)) -> (zext (truncate (zextload x)))
3698 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3699 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3700 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
3701 bool DoXform = true;
3702 SmallVector<SDNode*, 4> SetCCs;
3703 if (!N0.hasOneUse())
3704 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
3706 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3707 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N->getDebugLoc(),
3709 LN0->getBasePtr(), LN0->getPointerInfo(),
3711 LN0->isVolatile(), LN0->isNonTemporal(),
3712 LN0->getAlignment());
3713 CombineTo(N, ExtLoad);
3714 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3715 N0.getValueType(), ExtLoad);
3716 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3718 // Extend SetCC uses if necessary.
3719 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3720 SDNode *SetCC = SetCCs[i];
3721 SmallVector<SDValue, 4> Ops;
3723 for (unsigned j = 0; j != 2; ++j) {
3724 SDValue SOp = SetCC->getOperand(j);
3726 Ops.push_back(ExtLoad);
3728 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND,
3729 N->getDebugLoc(), VT, SOp));
3732 Ops.push_back(SetCC->getOperand(2));
3733 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3734 SetCC->getValueType(0),
3735 &Ops[0], Ops.size()));
3738 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3742 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
3743 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
3744 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3745 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3746 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3747 EVT MemVT = LN0->getMemoryVT();
3748 if ((!LegalOperations && !LN0->isVolatile()) ||
3749 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
3750 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N->getDebugLoc(),
3752 LN0->getBasePtr(), LN0->getPointerInfo(),
3754 LN0->isVolatile(), LN0->isNonTemporal(),
3755 LN0->getAlignment());
3756 CombineTo(N, ExtLoad);
3757 CombineTo(N0.getNode(),
3758 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
3760 ExtLoad.getValue(1));
3761 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3765 if (N0.getOpcode() == ISD::SETCC) {
3766 if (!LegalOperations && VT.isVector()) {
3767 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
3768 // Only do this before legalize for now.
3769 EVT N0VT = N0.getOperand(0).getValueType();
3770 EVT EltVT = VT.getVectorElementType();
3771 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
3772 DAG.getConstant(1, EltVT));
3773 if (VT.getSizeInBits() == N0VT.getSizeInBits()) {
3774 // We know that the # elements of the results is the same as the
3775 // # elements of the compare (and the # elements of the compare result
3776 // for that matter). Check to see that they are the same size. If so,
3777 // we know that the element size of the sext'd result matches the
3778 // element size of the compare operands.
3779 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3780 DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
3782 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
3783 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
3784 &OneOps[0], OneOps.size()));
3786 // If the desired elements are smaller or larger than the source
3787 // elements we can use a matching integer vector type and then
3788 // truncate/sign extend
3789 EVT MatchingElementType =
3790 EVT::getIntegerVT(*DAG.getContext(),
3791 N0VT.getScalarType().getSizeInBits());
3792 EVT MatchingVectorType =
3793 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
3794 N0VT.getVectorNumElements());
3796 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
3798 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3799 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3800 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT),
3801 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
3802 &OneOps[0], OneOps.size()));
3806 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3808 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3809 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3810 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3811 if (SCC.getNode()) return SCC;
3814 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
3815 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
3816 isa<ConstantSDNode>(N0.getOperand(1)) &&
3817 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
3819 if (N0.getOpcode() == ISD::SHL) {
3820 // If the original shl may be shifting out bits, do not perform this
3822 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3823 unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() -
3824 N0.getOperand(0).getOperand(0).getValueType().getSizeInBits();
3825 if (ShAmt > KnownZeroBits)
3828 DebugLoc dl = N->getDebugLoc();
3829 return DAG.getNode(N0.getOpcode(), dl, VT,
3830 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)),
3831 DAG.getNode(ISD::ZERO_EXTEND, dl,
3832 N0.getOperand(1).getValueType(),
3839 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
3840 SDValue N0 = N->getOperand(0);
3841 EVT VT = N->getValueType(0);
3843 // fold (aext c1) -> c1
3844 if (isa<ConstantSDNode>(N0))
3845 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
3846 // fold (aext (aext x)) -> (aext x)
3847 // fold (aext (zext x)) -> (zext x)
3848 // fold (aext (sext x)) -> (sext x)
3849 if (N0.getOpcode() == ISD::ANY_EXTEND ||
3850 N0.getOpcode() == ISD::ZERO_EXTEND ||
3851 N0.getOpcode() == ISD::SIGN_EXTEND)
3852 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
3854 // fold (aext (truncate (load x))) -> (aext (smaller load x))
3855 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
3856 if (N0.getOpcode() == ISD::TRUNCATE) {
3857 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3858 if (NarrowLoad.getNode()) {
3859 SDNode* oye = N0.getNode()->getOperand(0).getNode();
3860 if (NarrowLoad.getNode() != N0.getNode()) {
3861 CombineTo(N0.getNode(), NarrowLoad);
3862 // CombineTo deleted the truncate, if needed, but not what's under it.
3865 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3869 // fold (aext (truncate x))
3870 if (N0.getOpcode() == ISD::TRUNCATE) {
3871 SDValue TruncOp = N0.getOperand(0);
3872 if (TruncOp.getValueType() == VT)
3873 return TruncOp; // x iff x size == zext size.
3874 if (TruncOp.getValueType().bitsGT(VT))
3875 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
3876 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
3879 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
3880 // if the trunc is not free.
3881 if (N0.getOpcode() == ISD::AND &&
3882 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3883 N0.getOperand(1).getOpcode() == ISD::Constant &&
3884 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3885 N0.getValueType())) {
3886 SDValue X = N0.getOperand(0).getOperand(0);
3887 if (X.getValueType().bitsLT(VT)) {
3888 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
3889 } else if (X.getValueType().bitsGT(VT)) {
3890 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
3892 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3893 Mask.zext(VT.getSizeInBits());
3894 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3895 X, DAG.getConstant(Mask, VT));
3898 // fold (aext (load x)) -> (aext (truncate (extload x)))
3899 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3900 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3901 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
3902 bool DoXform = true;
3903 SmallVector<SDNode*, 4> SetCCs;
3904 if (!N0.hasOneUse())
3905 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
3907 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3908 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N->getDebugLoc(),
3910 LN0->getBasePtr(), LN0->getPointerInfo(),
3912 LN0->isVolatile(), LN0->isNonTemporal(),
3913 LN0->getAlignment());
3914 CombineTo(N, ExtLoad);
3915 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3916 N0.getValueType(), ExtLoad);
3917 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3919 // Extend SetCC uses if necessary.
3920 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3921 SDNode *SetCC = SetCCs[i];
3922 SmallVector<SDValue, 4> Ops;
3924 for (unsigned j = 0; j != 2; ++j) {
3925 SDValue SOp = SetCC->getOperand(j);
3927 Ops.push_back(ExtLoad);
3929 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND,
3930 N->getDebugLoc(), VT, SOp));
3933 Ops.push_back(SetCC->getOperand(2));
3934 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3935 SetCC->getValueType(0),
3936 &Ops[0], Ops.size()));
3939 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3943 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
3944 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
3945 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
3946 if (N0.getOpcode() == ISD::LOAD &&
3947 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3949 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3950 EVT MemVT = LN0->getMemoryVT();
3951 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
3953 LN0->getChain(), LN0->getBasePtr(),
3954 LN0->getPointerInfo(), MemVT,
3955 LN0->isVolatile(), LN0->isNonTemporal(),
3956 LN0->getAlignment());
3957 CombineTo(N, ExtLoad);
3958 CombineTo(N0.getNode(),
3959 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3960 N0.getValueType(), ExtLoad),
3961 ExtLoad.getValue(1));
3962 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3965 if (N0.getOpcode() == ISD::SETCC) {
3966 // aext(setcc) -> sext_in_reg(vsetcc) for vectors.
3967 // Only do this before legalize for now.
3968 if (VT.isVector() && !LegalOperations) {
3969 EVT N0VT = N0.getOperand(0).getValueType();
3970 // We know that the # elements of the results is the same as the
3971 // # elements of the compare (and the # elements of the compare result
3972 // for that matter). Check to see that they are the same size. If so,
3973 // we know that the element size of the sext'd result matches the
3974 // element size of the compare operands.
3975 if (VT.getSizeInBits() == N0VT.getSizeInBits())
3976 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
3978 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3979 // If the desired elements are smaller or larger than the source
3980 // elements we can use a matching integer vector type and then
3981 // truncate/sign extend
3983 EVT MatchingElementType =
3984 EVT::getIntegerVT(*DAG.getContext(),
3985 N0VT.getScalarType().getSizeInBits());
3986 EVT MatchingVectorType =
3987 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
3988 N0VT.getVectorNumElements());
3990 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
3992 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3993 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
3997 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3999 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4000 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4001 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4009 /// GetDemandedBits - See if the specified operand can be simplified with the
4010 /// knowledge that only the bits specified by Mask are used. If so, return the
4011 /// simpler operand, otherwise return a null SDValue.
4012 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
4013 switch (V.getOpcode()) {
4017 // If the LHS or RHS don't contribute bits to the or, drop them.
4018 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
4019 return V.getOperand(1);
4020 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
4021 return V.getOperand(0);
4024 // Only look at single-use SRLs.
4025 if (!V.getNode()->hasOneUse())
4027 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
4028 // See if we can recursively simplify the LHS.
4029 unsigned Amt = RHSC->getZExtValue();
4031 // Watch out for shift count overflow though.
4032 if (Amt >= Mask.getBitWidth()) break;
4033 APInt NewMask = Mask << Amt;
4034 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
4035 if (SimplifyLHS.getNode())
4036 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
4037 SimplifyLHS, V.getOperand(1));
4043 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
4044 /// bits and then truncated to a narrower type and where N is a multiple
4045 /// of number of bits of the narrower type, transform it to a narrower load
4046 /// from address + N / num of bits of new type. If the result is to be
4047 /// extended, also fold the extension to form a extending load.
4048 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
4049 unsigned Opc = N->getOpcode();
4051 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
4052 SDValue N0 = N->getOperand(0);
4053 EVT VT = N->getValueType(0);
4056 // This transformation isn't valid for vector loads.
4060 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
4062 if (Opc == ISD::SIGN_EXTEND_INREG) {
4063 ExtType = ISD::SEXTLOAD;
4064 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4065 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT))
4067 } else if (Opc == ISD::SRL) {
4068 // Annother special-case: SRL is basically zero-extending a narrower
4070 ExtType = ISD::ZEXTLOAD;
4072 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4073 if (!N01) return SDValue();
4074 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
4075 VT.getSizeInBits() - N01->getZExtValue());
4078 unsigned EVTBits = ExtVT.getSizeInBits();
4080 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() && ExtVT.isRound()) {
4081 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4082 ShAmt = N01->getZExtValue();
4083 // Is the shift amount a multiple of size of VT?
4084 if ((ShAmt & (EVTBits-1)) == 0) {
4085 N0 = N0.getOperand(0);
4086 // Is the load width a multiple of size of VT?
4087 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
4091 // If the shift amount is larger than the input type then we're not
4092 // accessing any of the loaded bytes. If the load was a zextload/extload
4093 // then the result of the shift+trunc is zero/undef (handled elsewhere).
4094 // If the load was a sextload then the result is a splat of the sign bit
4095 // of the extended byte. This is not worth optimizing for.
4096 if (ShAmt >= VT.getSizeInBits())
4102 // Do not generate loads of non-round integer types since these can
4103 // be expensive (and would be wrong if the type is not byte sized).
4104 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() &&
4105 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() >= EVTBits &&
4106 // Do not change the width of a volatile load.
4107 !cast<LoadSDNode>(N0)->isVolatile()) {
4108 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4109 EVT PtrType = N0.getOperand(1).getValueType();
4111 // For big endian targets, we need to adjust the offset to the pointer to
4112 // load the correct bytes.
4113 if (TLI.isBigEndian()) {
4114 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
4115 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
4116 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
4119 uint64_t PtrOff = ShAmt / 8;
4120 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
4121 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
4122 PtrType, LN0->getBasePtr(),
4123 DAG.getConstant(PtrOff, PtrType));
4124 AddToWorkList(NewPtr.getNode());
4126 SDValue Load = (ExtType == ISD::NON_EXTLOAD)
4127 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
4128 LN0->getPointerInfo().getWithOffset(PtrOff),
4129 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign)
4130 : DAG.getExtLoad(ExtType, VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
4131 LN0->getPointerInfo().getWithOffset(PtrOff),
4132 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
4135 // Replace the old load's chain with the new load's chain.
4136 WorkListRemover DeadNodes(*this);
4137 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
4140 // Return the new loaded value.
4147 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
4148 SDValue N0 = N->getOperand(0);
4149 SDValue N1 = N->getOperand(1);
4150 EVT VT = N->getValueType(0);
4151 EVT EVT = cast<VTSDNode>(N1)->getVT();
4152 unsigned VTBits = VT.getScalarType().getSizeInBits();
4153 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
4155 // fold (sext_in_reg c1) -> c1
4156 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
4157 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
4159 // If the input is already sign extended, just drop the extension.
4160 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
4163 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
4164 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
4165 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
4166 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
4167 N0.getOperand(0), N1);
4170 // fold (sext_in_reg (sext x)) -> (sext x)
4171 // fold (sext_in_reg (aext x)) -> (sext x)
4172 // if x is small enough.
4173 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
4174 SDValue N00 = N0.getOperand(0);
4175 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
4176 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
4177 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
4180 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
4181 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
4182 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
4184 // fold operands of sext_in_reg based on knowledge that the top bits are not
4186 if (SimplifyDemandedBits(SDValue(N, 0)))
4187 return SDValue(N, 0);
4189 // fold (sext_in_reg (load x)) -> (smaller sextload x)
4190 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
4191 SDValue NarrowLoad = ReduceLoadWidth(N);
4192 if (NarrowLoad.getNode())
4195 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
4196 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
4197 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
4198 if (N0.getOpcode() == ISD::SRL) {
4199 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
4200 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
4201 // We can turn this into an SRA iff the input to the SRL is already sign
4203 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
4204 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
4205 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
4206 N0.getOperand(0), N0.getOperand(1));
4210 // fold (sext_inreg (extload x)) -> (sextload x)
4211 if (ISD::isEXTLoad(N0.getNode()) &&
4212 ISD::isUNINDEXEDLoad(N0.getNode()) &&
4213 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4214 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4215 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
4216 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4217 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(),
4219 LN0->getBasePtr(), LN0->getPointerInfo(),
4221 LN0->isVolatile(), LN0->isNonTemporal(),
4222 LN0->getAlignment());
4223 CombineTo(N, ExtLoad);
4224 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4225 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4227 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
4228 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4230 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4231 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4232 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
4233 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4234 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(),
4236 LN0->getBasePtr(), LN0->getPointerInfo(),
4238 LN0->isVolatile(), LN0->isNonTemporal(),
4239 LN0->getAlignment());
4240 CombineTo(N, ExtLoad);
4241 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4242 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4247 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
4248 SDValue N0 = N->getOperand(0);
4249 EVT VT = N->getValueType(0);
4252 if (N0.getValueType() == N->getValueType(0))
4254 // fold (truncate c1) -> c1
4255 if (isa<ConstantSDNode>(N0))
4256 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
4257 // fold (truncate (truncate x)) -> (truncate x)
4258 if (N0.getOpcode() == ISD::TRUNCATE)
4259 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4260 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
4261 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
4262 N0.getOpcode() == ISD::SIGN_EXTEND ||
4263 N0.getOpcode() == ISD::ANY_EXTEND) {
4264 if (N0.getOperand(0).getValueType().bitsLT(VT))
4265 // if the source is smaller than the dest, we still need an extend
4266 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4268 else if (N0.getOperand(0).getValueType().bitsGT(VT))
4269 // if the source is larger than the dest, than we just need the truncate
4270 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4272 // if the source and dest are the same type, we can drop both the extend
4273 // and the truncate.
4274 return N0.getOperand(0);
4277 // See if we can simplify the input to this truncate through knowledge that
4278 // only the low bits are being used. For example "trunc (or (shl x, 8), y)"
4281 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
4282 VT.getSizeInBits()));
4283 if (Shorter.getNode())
4284 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
4286 // fold (truncate (load x)) -> (smaller load x)
4287 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
4288 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
4289 SDValue Reduced = ReduceLoadWidth(N);
4290 if (Reduced.getNode())
4294 // Simplify the operands using demanded-bits information.
4295 if (!VT.isVector() &&
4296 SimplifyDemandedBits(SDValue(N, 0)))
4297 return SDValue(N, 0);
4302 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
4303 SDValue Elt = N->getOperand(i);
4304 if (Elt.getOpcode() != ISD::MERGE_VALUES)
4305 return Elt.getNode();
4306 return Elt.getOperand(Elt.getResNo()).getNode();
4309 /// CombineConsecutiveLoads - build_pair (load, load) -> load
4310 /// if load locations are consecutive.
4311 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
4312 assert(N->getOpcode() == ISD::BUILD_PAIR);
4314 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
4315 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
4316 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
4317 LD1->getPointerInfo().getAddrSpace() !=
4318 LD2->getPointerInfo().getAddrSpace())
4320 EVT LD1VT = LD1->getValueType(0);
4322 if (ISD::isNON_EXTLoad(LD2) &&
4324 // If both are volatile this would reduce the number of volatile loads.
4325 // If one is volatile it might be ok, but play conservative and bail out.
4326 !LD1->isVolatile() &&
4327 !LD2->isVolatile() &&
4328 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
4329 unsigned Align = LD1->getAlignment();
4330 unsigned NewAlign = TLI.getTargetData()->
4331 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
4333 if (NewAlign <= Align &&
4334 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
4335 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
4336 LD1->getBasePtr(), LD1->getPointerInfo(),
4337 false, false, Align);
4343 SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
4344 SDValue N0 = N->getOperand(0);
4345 EVT VT = N->getValueType(0);
4347 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
4348 // Only do this before legalize, since afterward the target may be depending
4349 // on the bitconvert.
4350 // First check to see if this is all constant.
4352 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
4354 bool isSimple = true;
4355 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
4356 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
4357 N0.getOperand(i).getOpcode() != ISD::Constant &&
4358 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
4363 EVT DestEltVT = N->getValueType(0).getVectorElementType();
4364 assert(!DestEltVT.isVector() &&
4365 "Element type of vector ValueType must not be vector!");
4367 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT);
4370 // If the input is a constant, let getNode fold it.
4371 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
4372 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0);
4373 if (Res.getNode() != N) {
4374 if (!LegalOperations ||
4375 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
4378 // Folding it resulted in an illegal node, and it's too late to
4379 // do that. Clean up the old node and forego the transformation.
4380 // Ideally this won't happen very often, because instcombine
4381 // and the earlier dagcombine runs (where illegal nodes are
4382 // permitted) should have folded most of them already.
4383 DAG.DeleteNode(Res.getNode());
4387 // (conv (conv x, t1), t2) -> (conv x, t2)
4388 if (N0.getOpcode() == ISD::BIT_CONVERT)
4389 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT,
4392 // fold (conv (load x)) -> (load (conv*)x)
4393 // If the resultant load doesn't need a higher alignment than the original!
4394 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
4395 // Do not change the width of a volatile load.
4396 !cast<LoadSDNode>(N0)->isVolatile() &&
4397 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
4398 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4399 unsigned Align = TLI.getTargetData()->
4400 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
4401 unsigned OrigAlign = LN0->getAlignment();
4403 if (Align <= OrigAlign) {
4404 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
4405 LN0->getBasePtr(), LN0->getPointerInfo(),
4406 LN0->isVolatile(), LN0->isNonTemporal(),
4409 CombineTo(N0.getNode(),
4410 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
4411 N0.getValueType(), Load),
4417 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
4418 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
4419 // This often reduces constant pool loads.
4420 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
4421 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
4422 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT,
4424 AddToWorkList(NewConv.getNode());
4426 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
4427 if (N0.getOpcode() == ISD::FNEG)
4428 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
4429 NewConv, DAG.getConstant(SignBit, VT));
4430 assert(N0.getOpcode() == ISD::FABS);
4431 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4432 NewConv, DAG.getConstant(~SignBit, VT));
4435 // fold (bitconvert (fcopysign cst, x)) ->
4436 // (or (and (bitconvert x), sign), (and cst, (not sign)))
4437 // Note that we don't handle (copysign x, cst) because this can always be
4438 // folded to an fneg or fabs.
4439 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
4440 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
4441 VT.isInteger() && !VT.isVector()) {
4442 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
4443 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
4444 if (isTypeLegal(IntXVT)) {
4445 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
4446 IntXVT, N0.getOperand(1));
4447 AddToWorkList(X.getNode());
4449 // If X has a different width than the result/lhs, sext it or truncate it.
4450 unsigned VTWidth = VT.getSizeInBits();
4451 if (OrigXWidth < VTWidth) {
4452 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
4453 AddToWorkList(X.getNode());
4454 } else if (OrigXWidth > VTWidth) {
4455 // To get the sign bit in the right place, we have to shift it right
4456 // before truncating.
4457 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
4458 X.getValueType(), X,
4459 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
4460 AddToWorkList(X.getNode());
4461 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4462 AddToWorkList(X.getNode());
4465 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
4466 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
4467 X, DAG.getConstant(SignBit, VT));
4468 AddToWorkList(X.getNode());
4470 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
4471 VT, N0.getOperand(0));
4472 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
4473 Cst, DAG.getConstant(~SignBit, VT));
4474 AddToWorkList(Cst.getNode());
4476 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
4480 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
4481 if (N0.getOpcode() == ISD::BUILD_PAIR) {
4482 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
4483 if (CombineLD.getNode())
4490 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
4491 EVT VT = N->getValueType(0);
4492 return CombineConsecutiveLoads(N, VT);
4495 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
4496 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
4497 /// destination element value type.
4498 SDValue DAGCombiner::
4499 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
4500 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
4502 // If this is already the right type, we're done.
4503 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
4505 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
4506 unsigned DstBitSize = DstEltVT.getSizeInBits();
4508 // If this is a conversion of N elements of one type to N elements of another
4509 // type, convert each element. This handles FP<->INT cases.
4510 if (SrcBitSize == DstBitSize) {
4511 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
4512 BV->getValueType(0).getVectorNumElements());
4514 // Due to the FP element handling below calling this routine recursively,
4515 // we can end up with a scalar-to-vector node here.
4516 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
4517 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
4518 DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(),
4519 DstEltVT, BV->getOperand(0)));
4521 SmallVector<SDValue, 8> Ops;
4522 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
4523 SDValue Op = BV->getOperand(i);
4524 // If the vector element type is not legal, the BUILD_VECTOR operands
4525 // are promoted and implicitly truncated. Make that explicit here.
4526 if (Op.getValueType() != SrcEltVT)
4527 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
4528 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(),
4530 AddToWorkList(Ops.back().getNode());
4532 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4533 &Ops[0], Ops.size());
4536 // Otherwise, we're growing or shrinking the elements. To avoid having to
4537 // handle annoying details of growing/shrinking FP values, we convert them to
4539 if (SrcEltVT.isFloatingPoint()) {
4540 // Convert the input float vector to a int vector where the elements are the
4542 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
4543 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
4544 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
4548 // Now we know the input is an integer vector. If the output is a FP type,
4549 // convert to integer first, then to FP of the right size.
4550 if (DstEltVT.isFloatingPoint()) {
4551 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
4552 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
4553 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
4555 // Next, convert to FP elements of the same size.
4556 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
4559 // Okay, we know the src/dst types are both integers of differing types.
4560 // Handling growing first.
4561 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
4562 if (SrcBitSize < DstBitSize) {
4563 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
4565 SmallVector<SDValue, 8> Ops;
4566 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
4567 i += NumInputsPerOutput) {
4568 bool isLE = TLI.isLittleEndian();
4569 APInt NewBits = APInt(DstBitSize, 0);
4570 bool EltIsUndef = true;
4571 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
4572 // Shift the previously computed bits over.
4573 NewBits <<= SrcBitSize;
4574 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
4575 if (Op.getOpcode() == ISD::UNDEF) continue;
4578 NewBits |= APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).
4579 zextOrTrunc(SrcBitSize).zext(DstBitSize);
4583 Ops.push_back(DAG.getUNDEF(DstEltVT));
4585 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
4588 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
4589 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4590 &Ops[0], Ops.size());
4593 // Finally, this must be the case where we are shrinking elements: each input
4594 // turns into multiple outputs.
4595 bool isS2V = ISD::isScalarToVector(BV);
4596 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
4597 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
4598 NumOutputsPerInput*BV->getNumOperands());
4599 SmallVector<SDValue, 8> Ops;
4601 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
4602 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
4603 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
4604 Ops.push_back(DAG.getUNDEF(DstEltVT));
4608 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))->
4609 getAPIntValue()).zextOrTrunc(SrcBitSize);
4611 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
4612 APInt ThisVal = APInt(OpVal).trunc(DstBitSize);
4613 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
4614 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal)
4615 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
4616 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
4618 OpVal = OpVal.lshr(DstBitSize);
4621 // For big endian targets, swap the order of the pieces of each element.
4622 if (TLI.isBigEndian())
4623 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
4626 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4627 &Ops[0], Ops.size());
4630 SDValue DAGCombiner::visitFADD(SDNode *N) {
4631 SDValue N0 = N->getOperand(0);
4632 SDValue N1 = N->getOperand(1);
4633 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4634 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4635 EVT VT = N->getValueType(0);
4638 if (VT.isVector()) {
4639 SDValue FoldedVOp = SimplifyVBinOp(N);
4640 if (FoldedVOp.getNode()) return FoldedVOp;
4643 // fold (fadd c1, c2) -> (fadd c1, c2)
4644 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4645 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
4646 // canonicalize constant to RHS
4647 if (N0CFP && !N1CFP)
4648 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
4649 // fold (fadd A, 0) -> A
4650 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4652 // fold (fadd A, (fneg B)) -> (fsub A, B)
4653 if (isNegatibleForFree(N1, LegalOperations) == 2)
4654 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
4655 GetNegatedExpression(N1, DAG, LegalOperations));
4656 // fold (fadd (fneg A), B) -> (fsub B, A)
4657 if (isNegatibleForFree(N0, LegalOperations) == 2)
4658 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
4659 GetNegatedExpression(N0, DAG, LegalOperations));
4661 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
4662 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
4663 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4664 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
4665 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
4666 N0.getOperand(1), N1));
4671 SDValue DAGCombiner::visitFSUB(SDNode *N) {
4672 SDValue N0 = N->getOperand(0);
4673 SDValue N1 = N->getOperand(1);
4674 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4675 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4676 EVT VT = N->getValueType(0);
4679 if (VT.isVector()) {
4680 SDValue FoldedVOp = SimplifyVBinOp(N);
4681 if (FoldedVOp.getNode()) return FoldedVOp;
4684 // fold (fsub c1, c2) -> c1-c2
4685 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4686 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
4687 // fold (fsub A, 0) -> A
4688 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4690 // fold (fsub 0, B) -> -B
4691 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
4692 if (isNegatibleForFree(N1, LegalOperations))
4693 return GetNegatedExpression(N1, DAG, LegalOperations);
4694 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4695 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
4697 // fold (fsub A, (fneg B)) -> (fadd A, B)
4698 if (isNegatibleForFree(N1, LegalOperations))
4699 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
4700 GetNegatedExpression(N1, DAG, LegalOperations));
4705 SDValue DAGCombiner::visitFMUL(SDNode *N) {
4706 SDValue N0 = N->getOperand(0);
4707 SDValue N1 = N->getOperand(1);
4708 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4709 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4710 EVT VT = N->getValueType(0);
4713 if (VT.isVector()) {
4714 SDValue FoldedVOp = SimplifyVBinOp(N);
4715 if (FoldedVOp.getNode()) return FoldedVOp;
4718 // fold (fmul c1, c2) -> c1*c2
4719 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4720 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
4721 // canonicalize constant to RHS
4722 if (N0CFP && !N1CFP)
4723 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
4724 // fold (fmul A, 0) -> 0
4725 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4727 // fold (fmul A, 0) -> 0, vector edition.
4728 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode()))
4730 // fold (fmul X, 2.0) -> (fadd X, X)
4731 if (N1CFP && N1CFP->isExactlyValue(+2.0))
4732 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
4733 // fold (fmul X, -1.0) -> (fneg X)
4734 if (N1CFP && N1CFP->isExactlyValue(-1.0))
4735 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4736 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
4738 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
4739 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4740 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4741 // Both can be negated for free, check to see if at least one is cheaper
4743 if (LHSNeg == 2 || RHSNeg == 2)
4744 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4745 GetNegatedExpression(N0, DAG, LegalOperations),
4746 GetNegatedExpression(N1, DAG, LegalOperations));
4750 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
4751 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
4752 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4753 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
4754 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4755 N0.getOperand(1), N1));
4760 SDValue DAGCombiner::visitFDIV(SDNode *N) {
4761 SDValue N0 = N->getOperand(0);
4762 SDValue N1 = N->getOperand(1);
4763 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4764 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4765 EVT VT = N->getValueType(0);
4768 if (VT.isVector()) {
4769 SDValue FoldedVOp = SimplifyVBinOp(N);
4770 if (FoldedVOp.getNode()) return FoldedVOp;
4773 // fold (fdiv c1, c2) -> c1/c2
4774 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4775 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
4778 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
4779 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4780 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4781 // Both can be negated for free, check to see if at least one is cheaper
4783 if (LHSNeg == 2 || RHSNeg == 2)
4784 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
4785 GetNegatedExpression(N0, DAG, LegalOperations),
4786 GetNegatedExpression(N1, DAG, LegalOperations));
4793 SDValue DAGCombiner::visitFREM(SDNode *N) {
4794 SDValue N0 = N->getOperand(0);
4795 SDValue N1 = N->getOperand(1);
4796 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4797 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4798 EVT VT = N->getValueType(0);
4800 // fold (frem c1, c2) -> fmod(c1,c2)
4801 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4802 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
4807 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
4808 SDValue N0 = N->getOperand(0);
4809 SDValue N1 = N->getOperand(1);
4810 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4811 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4812 EVT VT = N->getValueType(0);
4814 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
4815 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
4818 const APFloat& V = N1CFP->getValueAPF();
4819 // copysign(x, c1) -> fabs(x) iff ispos(c1)
4820 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
4821 if (!V.isNegative()) {
4822 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
4823 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4825 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4826 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
4827 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
4831 // copysign(fabs(x), y) -> copysign(x, y)
4832 // copysign(fneg(x), y) -> copysign(x, y)
4833 // copysign(copysign(x,z), y) -> copysign(x, y)
4834 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
4835 N0.getOpcode() == ISD::FCOPYSIGN)
4836 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4837 N0.getOperand(0), N1);
4839 // copysign(x, abs(y)) -> abs(x)
4840 if (N1.getOpcode() == ISD::FABS)
4841 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4843 // copysign(x, copysign(y,z)) -> copysign(x, z)
4844 if (N1.getOpcode() == ISD::FCOPYSIGN)
4845 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4846 N0, N1.getOperand(1));
4848 // copysign(x, fp_extend(y)) -> copysign(x, y)
4849 // copysign(x, fp_round(y)) -> copysign(x, y)
4850 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
4851 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4852 N0, N1.getOperand(0));
4857 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
4858 SDValue N0 = N->getOperand(0);
4859 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4860 EVT VT = N->getValueType(0);
4861 EVT OpVT = N0.getValueType();
4863 // fold (sint_to_fp c1) -> c1fp
4864 if (N0C && OpVT != MVT::ppcf128)
4865 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4867 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
4868 // but UINT_TO_FP is legal on this target, try to convert.
4869 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
4870 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
4871 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
4872 if (DAG.SignBitIsZero(N0))
4873 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4879 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
4880 SDValue N0 = N->getOperand(0);
4881 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4882 EVT VT = N->getValueType(0);
4883 EVT OpVT = N0.getValueType();
4885 // fold (uint_to_fp c1) -> c1fp
4886 if (N0C && OpVT != MVT::ppcf128)
4887 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4889 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
4890 // but SINT_TO_FP is legal on this target, try to convert.
4891 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
4892 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
4893 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
4894 if (DAG.SignBitIsZero(N0))
4895 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4901 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
4902 SDValue N0 = N->getOperand(0);
4903 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4904 EVT VT = N->getValueType(0);
4906 // fold (fp_to_sint c1fp) -> c1
4908 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
4913 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
4914 SDValue N0 = N->getOperand(0);
4915 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4916 EVT VT = N->getValueType(0);
4918 // fold (fp_to_uint c1fp) -> c1
4919 if (N0CFP && VT != MVT::ppcf128)
4920 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
4925 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
4926 SDValue N0 = N->getOperand(0);
4927 SDValue N1 = N->getOperand(1);
4928 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4929 EVT VT = N->getValueType(0);
4931 // fold (fp_round c1fp) -> c1fp
4932 if (N0CFP && N0.getValueType() != MVT::ppcf128)
4933 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
4935 // fold (fp_round (fp_extend x)) -> x
4936 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
4937 return N0.getOperand(0);
4939 // fold (fp_round (fp_round x)) -> (fp_round x)
4940 if (N0.getOpcode() == ISD::FP_ROUND) {
4941 // This is a value preserving truncation if both round's are.
4942 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
4943 N0.getNode()->getConstantOperandVal(1) == 1;
4944 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
4945 DAG.getIntPtrConstant(IsTrunc));
4948 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
4949 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
4950 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
4951 N0.getOperand(0), N1);
4952 AddToWorkList(Tmp.getNode());
4953 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4954 Tmp, N0.getOperand(1));
4960 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
4961 SDValue N0 = N->getOperand(0);
4962 EVT VT = N->getValueType(0);
4963 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4964 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4966 // fold (fp_round_inreg c1fp) -> c1fp
4967 if (N0CFP && isTypeLegal(EVT)) {
4968 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
4969 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
4975 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
4976 SDValue N0 = N->getOperand(0);
4977 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4978 EVT VT = N->getValueType(0);
4980 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
4981 if (N->hasOneUse() &&
4982 N->use_begin()->getOpcode() == ISD::FP_ROUND)
4985 // fold (fp_extend c1fp) -> c1fp
4986 if (N0CFP && VT != MVT::ppcf128)
4987 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
4989 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
4991 if (N0.getOpcode() == ISD::FP_ROUND
4992 && N0.getNode()->getConstantOperandVal(1) == 1) {
4993 SDValue In = N0.getOperand(0);
4994 if (In.getValueType() == VT) return In;
4995 if (VT.bitsLT(In.getValueType()))
4996 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
4997 In, N0.getOperand(1));
4998 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
5001 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
5002 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
5003 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5004 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
5005 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5006 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N->getDebugLoc(),
5008 LN0->getBasePtr(), LN0->getPointerInfo(),
5010 LN0->isVolatile(), LN0->isNonTemporal(),
5011 LN0->getAlignment());
5012 CombineTo(N, ExtLoad);
5013 CombineTo(N0.getNode(),
5014 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
5015 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
5016 ExtLoad.getValue(1));
5017 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5023 SDValue DAGCombiner::visitFNEG(SDNode *N) {
5024 SDValue N0 = N->getOperand(0);
5025 EVT VT = N->getValueType(0);
5027 if (isNegatibleForFree(N0, LegalOperations))
5028 return GetNegatedExpression(N0, DAG, LegalOperations);
5030 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
5031 // constant pool values.
5032 if (N0.getOpcode() == ISD::BIT_CONVERT &&
5034 N0.getNode()->hasOneUse() &&
5035 N0.getOperand(0).getValueType().isInteger()) {
5036 SDValue Int = N0.getOperand(0);
5037 EVT IntVT = Int.getValueType();
5038 if (IntVT.isInteger() && !IntVT.isVector()) {
5039 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
5040 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5041 AddToWorkList(Int.getNode());
5042 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
5050 SDValue DAGCombiner::visitFABS(SDNode *N) {
5051 SDValue N0 = N->getOperand(0);
5052 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5053 EVT VT = N->getValueType(0);
5055 // fold (fabs c1) -> fabs(c1)
5056 if (N0CFP && VT != MVT::ppcf128)
5057 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5058 // fold (fabs (fabs x)) -> (fabs x)
5059 if (N0.getOpcode() == ISD::FABS)
5060 return N->getOperand(0);
5061 // fold (fabs (fneg x)) -> (fabs x)
5062 // fold (fabs (fcopysign x, y)) -> (fabs x)
5063 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
5064 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
5066 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
5067 // constant pool values.
5068 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
5069 N0.getOperand(0).getValueType().isInteger() &&
5070 !N0.getOperand(0).getValueType().isVector()) {
5071 SDValue Int = N0.getOperand(0);
5072 EVT IntVT = Int.getValueType();
5073 if (IntVT.isInteger() && !IntVT.isVector()) {
5074 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
5075 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5076 AddToWorkList(Int.getNode());
5077 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
5078 N->getValueType(0), Int);
5085 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
5086 SDValue Chain = N->getOperand(0);
5087 SDValue N1 = N->getOperand(1);
5088 SDValue N2 = N->getOperand(2);
5090 // If N is a constant we could fold this into a fallthrough or unconditional
5091 // branch. However that doesn't happen very often in normal code, because
5092 // Instcombine/SimplifyCFG should have handled the available opportunities.
5093 // If we did this folding here, it would be necessary to update the
5094 // MachineBasicBlock CFG, which is awkward.
5096 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
5098 if (N1.getOpcode() == ISD::SETCC &&
5099 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
5100 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5101 Chain, N1.getOperand(2),
5102 N1.getOperand(0), N1.getOperand(1), N2);
5105 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
5106 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
5107 (N1.getOperand(0).hasOneUse() &&
5108 N1.getOperand(0).getOpcode() == ISD::SRL))) {
5110 if (N1.getOpcode() == ISD::TRUNCATE) {
5111 // Look pass the truncate.
5112 Trunc = N1.getNode();
5113 N1 = N1.getOperand(0);
5116 // Match this pattern so that we can generate simpler code:
5119 // %b = and i32 %a, 2
5120 // %c = srl i32 %b, 1
5121 // brcond i32 %c ...
5126 // %b = and i32 %a, 2
5127 // %c = setcc eq %b, 0
5130 // This applies only when the AND constant value has one bit set and the
5131 // SRL constant is equal to the log2 of the AND constant. The back-end is
5132 // smart enough to convert the result into a TEST/JMP sequence.
5133 SDValue Op0 = N1.getOperand(0);
5134 SDValue Op1 = N1.getOperand(1);
5136 if (Op0.getOpcode() == ISD::AND &&
5137 Op1.getOpcode() == ISD::Constant) {
5138 SDValue AndOp1 = Op0.getOperand(1);
5140 if (AndOp1.getOpcode() == ISD::Constant) {
5141 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
5143 if (AndConst.isPowerOf2() &&
5144 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
5146 DAG.getSetCC(N->getDebugLoc(),
5147 TLI.getSetCCResultType(Op0.getValueType()),
5148 Op0, DAG.getConstant(0, Op0.getValueType()),
5151 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5152 MVT::Other, Chain, SetCC, N2);
5153 // Don't add the new BRCond into the worklist or else SimplifySelectCC
5154 // will convert it back to (X & C1) >> C2.
5155 CombineTo(N, NewBRCond, false);
5156 // Truncate is dead.
5158 removeFromWorkList(Trunc);
5159 DAG.DeleteNode(Trunc);
5161 // Replace the uses of SRL with SETCC
5162 WorkListRemover DeadNodes(*this);
5163 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
5164 removeFromWorkList(N1.getNode());
5165 DAG.DeleteNode(N1.getNode());
5166 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5172 // Restore N1 if the above transformation doesn't match.
5173 N1 = N->getOperand(1);
5176 // Transform br(xor(x, y)) -> br(x != y)
5177 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
5178 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
5179 SDNode *TheXor = N1.getNode();
5180 SDValue Op0 = TheXor->getOperand(0);
5181 SDValue Op1 = TheXor->getOperand(1);
5182 if (Op0.getOpcode() == Op1.getOpcode()) {
5183 // Avoid missing important xor optimizations.
5184 SDValue Tmp = visitXOR(TheXor);
5185 if (Tmp.getNode() && Tmp.getNode() != TheXor) {
5186 DEBUG(dbgs() << "\nReplacing.8 ";
5188 dbgs() << "\nWith: ";
5189 Tmp.getNode()->dump(&DAG);
5191 WorkListRemover DeadNodes(*this);
5192 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes);
5193 removeFromWorkList(TheXor);
5194 DAG.DeleteNode(TheXor);
5195 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5196 MVT::Other, Chain, Tmp, N2);
5200 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
5202 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
5203 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
5204 Op0.getOpcode() == ISD::XOR) {
5205 TheXor = Op0.getNode();
5209 EVT SetCCVT = N1.getValueType();
5211 SetCCVT = TLI.getSetCCResultType(SetCCVT);
5212 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
5215 Equal ? ISD::SETEQ : ISD::SETNE);
5216 // Replace the uses of XOR with SETCC
5217 WorkListRemover DeadNodes(*this);
5218 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
5219 removeFromWorkList(N1.getNode());
5220 DAG.DeleteNode(N1.getNode());
5221 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5222 MVT::Other, Chain, SetCC, N2);
5229 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
5231 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
5232 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
5233 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
5235 // If N is a constant we could fold this into a fallthrough or unconditional
5236 // branch. However that doesn't happen very often in normal code, because
5237 // Instcombine/SimplifyCFG should have handled the available opportunities.
5238 // If we did this folding here, it would be necessary to update the
5239 // MachineBasicBlock CFG, which is awkward.
5241 // Use SimplifySetCC to simplify SETCC's.
5242 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
5243 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
5245 if (Simp.getNode()) AddToWorkList(Simp.getNode());
5247 // fold to a simpler setcc
5248 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
5249 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5250 N->getOperand(0), Simp.getOperand(2),
5251 Simp.getOperand(0), Simp.getOperand(1),
5257 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
5258 /// pre-indexed load / store when the base pointer is an add or subtract
5259 /// and it has other uses besides the load / store. After the
5260 /// transformation, the new indexed load / store has effectively folded
5261 /// the add / subtract in and all of its other uses are redirected to the
5262 /// new load / store.
5263 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
5264 if (!LegalOperations)
5270 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5271 if (LD->isIndexed())
5273 VT = LD->getMemoryVT();
5274 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
5275 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
5277 Ptr = LD->getBasePtr();
5278 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5279 if (ST->isIndexed())
5281 VT = ST->getMemoryVT();
5282 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
5283 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
5285 Ptr = ST->getBasePtr();
5291 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
5292 // out. There is no reason to make this a preinc/predec.
5293 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
5294 Ptr.getNode()->hasOneUse())
5297 // Ask the target to do addressing mode selection.
5300 ISD::MemIndexedMode AM = ISD::UNINDEXED;
5301 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
5303 // Don't create a indexed load / store with zero offset.
5304 if (isa<ConstantSDNode>(Offset) &&
5305 cast<ConstantSDNode>(Offset)->isNullValue())
5308 // Try turning it into a pre-indexed load / store except when:
5309 // 1) The new base ptr is a frame index.
5310 // 2) If N is a store and the new base ptr is either the same as or is a
5311 // predecessor of the value being stored.
5312 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
5313 // that would create a cycle.
5314 // 4) All uses are load / store ops that use it as old base ptr.
5316 // Check #1. Preinc'ing a frame index would require copying the stack pointer
5317 // (plus the implicit offset) to a register to preinc anyway.
5318 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
5323 SDValue Val = cast<StoreSDNode>(N)->getValue();
5324 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
5328 // Now check for #3 and #4.
5329 bool RealUse = false;
5330 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
5331 E = Ptr.getNode()->use_end(); I != E; ++I) {
5335 if (Use->isPredecessorOf(N))
5338 if (!((Use->getOpcode() == ISD::LOAD &&
5339 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
5340 (Use->getOpcode() == ISD::STORE &&
5341 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
5350 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
5351 BasePtr, Offset, AM);
5353 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
5354 BasePtr, Offset, AM);
5357 DEBUG(dbgs() << "\nReplacing.4 ";
5359 dbgs() << "\nWith: ";
5360 Result.getNode()->dump(&DAG);
5362 WorkListRemover DeadNodes(*this);
5364 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
5366 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
5369 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
5373 // Finally, since the node is now dead, remove it from the graph.
5376 // Replace the uses of Ptr with uses of the updated base value.
5377 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
5379 removeFromWorkList(Ptr.getNode());
5380 DAG.DeleteNode(Ptr.getNode());
5385 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
5386 /// add / sub of the base pointer node into a post-indexed load / store.
5387 /// The transformation folded the add / subtract into the new indexed
5388 /// load / store effectively and all of its uses are redirected to the
5389 /// new load / store.
5390 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
5391 if (!LegalOperations)
5397 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5398 if (LD->isIndexed())
5400 VT = LD->getMemoryVT();
5401 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
5402 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
5404 Ptr = LD->getBasePtr();
5405 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5406 if (ST->isIndexed())
5408 VT = ST->getMemoryVT();
5409 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
5410 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
5412 Ptr = ST->getBasePtr();
5418 if (Ptr.getNode()->hasOneUse())
5421 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
5422 E = Ptr.getNode()->use_end(); I != E; ++I) {
5425 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
5430 ISD::MemIndexedMode AM = ISD::UNINDEXED;
5431 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
5432 // Don't create a indexed load / store with zero offset.
5433 if (isa<ConstantSDNode>(Offset) &&
5434 cast<ConstantSDNode>(Offset)->isNullValue())
5437 // Try turning it into a post-indexed load / store except when
5438 // 1) All uses are load / store ops that use it as base ptr.
5439 // 2) Op must be independent of N, i.e. Op is neither a predecessor
5440 // nor a successor of N. Otherwise, if Op is folded that would
5443 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
5447 bool TryNext = false;
5448 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
5449 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
5451 if (Use == Ptr.getNode())
5454 // If all the uses are load / store addresses, then don't do the
5456 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
5457 bool RealUse = false;
5458 for (SDNode::use_iterator III = Use->use_begin(),
5459 EEE = Use->use_end(); III != EEE; ++III) {
5460 SDNode *UseUse = *III;
5461 if (!((UseUse->getOpcode() == ISD::LOAD &&
5462 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) ||
5463 (UseUse->getOpcode() == ISD::STORE &&
5464 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use)))
5479 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
5480 SDValue Result = isLoad
5481 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
5482 BasePtr, Offset, AM)
5483 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
5484 BasePtr, Offset, AM);
5487 DEBUG(dbgs() << "\nReplacing.5 ";
5489 dbgs() << "\nWith: ";
5490 Result.getNode()->dump(&DAG);
5492 WorkListRemover DeadNodes(*this);
5494 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
5496 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
5499 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
5503 // Finally, since the node is now dead, remove it from the graph.
5506 // Replace the uses of Use with uses of the updated base value.
5507 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
5508 Result.getValue(isLoad ? 1 : 0),
5510 removeFromWorkList(Op);
5520 SDValue DAGCombiner::visitLOAD(SDNode *N) {
5521 LoadSDNode *LD = cast<LoadSDNode>(N);
5522 SDValue Chain = LD->getChain();
5523 SDValue Ptr = LD->getBasePtr();
5525 // If load is not volatile and there are no uses of the loaded value (and
5526 // the updated indexed value in case of indexed loads), change uses of the
5527 // chain value into uses of the chain input (i.e. delete the dead load).
5528 if (!LD->isVolatile()) {
5529 if (N->getValueType(1) == MVT::Other) {
5531 if (N->hasNUsesOfValue(0, 0)) {
5532 // It's not safe to use the two value CombineTo variant here. e.g.
5533 // v1, chain2 = load chain1, loc
5534 // v2, chain3 = load chain2, loc
5536 // Now we replace use of chain2 with chain1. This makes the second load
5537 // isomorphic to the one we are deleting, and thus makes this load live.
5538 DEBUG(dbgs() << "\nReplacing.6 ";
5540 dbgs() << "\nWith chain: ";
5541 Chain.getNode()->dump(&DAG);
5543 WorkListRemover DeadNodes(*this);
5544 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
5546 if (N->use_empty()) {
5547 removeFromWorkList(N);
5551 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5555 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
5556 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
5557 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
5558 DEBUG(dbgs() << "\nReplacing.7 ";
5560 dbgs() << "\nWith: ";
5561 Undef.getNode()->dump(&DAG);
5562 dbgs() << " and 2 other values\n");
5563 WorkListRemover DeadNodes(*this);
5564 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
5565 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
5566 DAG.getUNDEF(N->getValueType(1)),
5568 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
5569 removeFromWorkList(N);
5571 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5576 // If this load is directly stored, replace the load value with the stored
5578 // TODO: Handle store large -> read small portion.
5579 // TODO: Handle TRUNCSTORE/LOADEXT
5580 if (LD->getExtensionType() == ISD::NON_EXTLOAD &&
5581 !LD->isVolatile()) {
5582 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
5583 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
5584 if (PrevST->getBasePtr() == Ptr &&
5585 PrevST->getValue().getValueType() == N->getValueType(0))
5586 return CombineTo(N, Chain.getOperand(1), Chain);
5590 // Try to infer better alignment information than the load already has.
5591 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
5592 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
5593 if (Align > LD->getAlignment())
5594 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0),
5596 Chain, Ptr, LD->getPointerInfo(),
5598 LD->isVolatile(), LD->isNonTemporal(), Align);
5603 // Walk up chain skipping non-aliasing memory nodes.
5604 SDValue BetterChain = FindBetterChain(N, Chain);
5606 // If there is a better chain.
5607 if (Chain != BetterChain) {
5610 // Replace the chain to void dependency.
5611 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
5612 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
5613 BetterChain, Ptr, LD->getPointerInfo(),
5614 LD->isVolatile(), LD->isNonTemporal(),
5615 LD->getAlignment());
5617 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0),
5619 BetterChain, Ptr, LD->getPointerInfo(),
5622 LD->isNonTemporal(),
5623 LD->getAlignment());
5626 // Create token factor to keep old chain connected.
5627 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
5628 MVT::Other, Chain, ReplLoad.getValue(1));
5630 // Make sure the new and old chains are cleaned up.
5631 AddToWorkList(Token.getNode());
5633 // Replace uses with load result and token factor. Don't add users
5635 return CombineTo(N, ReplLoad.getValue(0), Token, false);
5639 // Try transforming N to an indexed load.
5640 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
5641 return SDValue(N, 0);
5646 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
5647 /// load is having specific bytes cleared out. If so, return the byte size
5648 /// being masked out and the shift amount.
5649 static std::pair<unsigned, unsigned>
5650 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
5651 std::pair<unsigned, unsigned> Result(0, 0);
5653 // Check for the structure we're looking for.
5654 if (V->getOpcode() != ISD::AND ||
5655 !isa<ConstantSDNode>(V->getOperand(1)) ||
5656 !ISD::isNormalLoad(V->getOperand(0).getNode()))
5659 // Check the chain and pointer.
5660 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
5661 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
5663 // The store should be chained directly to the load or be an operand of a
5665 if (LD == Chain.getNode())
5667 else if (Chain->getOpcode() != ISD::TokenFactor)
5668 return Result; // Fail.
5671 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
5672 if (Chain->getOperand(i).getNode() == LD) {
5676 if (!isOk) return Result;
5679 // This only handles simple types.
5680 if (V.getValueType() != MVT::i16 &&
5681 V.getValueType() != MVT::i32 &&
5682 V.getValueType() != MVT::i64)
5685 // Check the constant mask. Invert it so that the bits being masked out are
5686 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
5687 // follow the sign bit for uniformity.
5688 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
5689 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask);
5690 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
5691 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask);
5692 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
5693 if (NotMaskLZ == 64) return Result; // All zero mask.
5695 // See if we have a continuous run of bits. If so, we have 0*1+0*
5696 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
5699 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
5700 if (V.getValueType() != MVT::i64 && NotMaskLZ)
5701 NotMaskLZ -= 64-V.getValueSizeInBits();
5703 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
5704 switch (MaskedBytes) {
5708 default: return Result; // All one mask, or 5-byte mask.
5711 // Verify that the first bit starts at a multiple of mask so that the access
5712 // is aligned the same as the access width.
5713 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
5715 Result.first = MaskedBytes;
5716 Result.second = NotMaskTZ/8;
5721 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
5722 /// provides a value as specified by MaskInfo. If so, replace the specified
5723 /// store with a narrower store of truncated IVal.
5725 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
5726 SDValue IVal, StoreSDNode *St,
5728 unsigned NumBytes = MaskInfo.first;
5729 unsigned ByteShift = MaskInfo.second;
5730 SelectionDAG &DAG = DC->getDAG();
5732 // Check to see if IVal is all zeros in the part being masked in by the 'or'
5733 // that uses this. If not, this is not a replacement.
5734 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
5735 ByteShift*8, (ByteShift+NumBytes)*8);
5736 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
5738 // Check that it is legal on the target to do this. It is legal if the new
5739 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
5741 MVT VT = MVT::getIntegerVT(NumBytes*8);
5742 if (!DC->isTypeLegal(VT))
5745 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
5746 // shifted by ByteShift and truncated down to NumBytes.
5748 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
5749 DAG.getConstant(ByteShift*8, DC->getShiftAmountTy()));
5751 // Figure out the offset for the store and the alignment of the access.
5753 unsigned NewAlign = St->getAlignment();
5755 if (DAG.getTargetLoweringInfo().isLittleEndian())
5756 StOffset = ByteShift;
5758 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
5760 SDValue Ptr = St->getBasePtr();
5762 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
5763 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
5764 NewAlign = MinAlign(NewAlign, StOffset);
5767 // Truncate down to the new size.
5768 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
5771 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr,
5772 St->getPointerInfo().getWithOffset(StOffset),
5773 false, false, NewAlign).getNode();
5777 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
5778 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
5779 /// of the loaded bits, try narrowing the load and store if it would end up
5780 /// being a win for performance or code size.
5781 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
5782 StoreSDNode *ST = cast<StoreSDNode>(N);
5783 if (ST->isVolatile())
5786 SDValue Chain = ST->getChain();
5787 SDValue Value = ST->getValue();
5788 SDValue Ptr = ST->getBasePtr();
5789 EVT VT = Value.getValueType();
5791 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
5794 unsigned Opc = Value.getOpcode();
5796 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
5797 // is a byte mask indicating a consecutive number of bytes, check to see if
5798 // Y is known to provide just those bytes. If so, we try to replace the
5799 // load + replace + store sequence with a single (narrower) store, which makes
5801 if (Opc == ISD::OR) {
5802 std::pair<unsigned, unsigned> MaskedLoad;
5803 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
5804 if (MaskedLoad.first)
5805 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
5806 Value.getOperand(1), ST,this))
5807 return SDValue(NewST, 0);
5809 // Or is commutative, so try swapping X and Y.
5810 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
5811 if (MaskedLoad.first)
5812 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
5813 Value.getOperand(0), ST,this))
5814 return SDValue(NewST, 0);
5817 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
5818 Value.getOperand(1).getOpcode() != ISD::Constant)
5821 SDValue N0 = Value.getOperand(0);
5822 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
5823 Chain == SDValue(N0.getNode(), 1)) {
5824 LoadSDNode *LD = cast<LoadSDNode>(N0);
5825 if (LD->getBasePtr() != Ptr ||
5826 LD->getPointerInfo().getAddrSpace() !=
5827 ST->getPointerInfo().getAddrSpace())
5830 // Find the type to narrow it the load / op / store to.
5831 SDValue N1 = Value.getOperand(1);
5832 unsigned BitWidth = N1.getValueSizeInBits();
5833 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
5834 if (Opc == ISD::AND)
5835 Imm ^= APInt::getAllOnesValue(BitWidth);
5836 if (Imm == 0 || Imm.isAllOnesValue())
5838 unsigned ShAmt = Imm.countTrailingZeros();
5839 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
5840 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
5841 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
5842 while (NewBW < BitWidth &&
5843 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
5844 TLI.isNarrowingProfitable(VT, NewVT))) {
5845 NewBW = NextPowerOf2(NewBW);
5846 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
5848 if (NewBW >= BitWidth)
5851 // If the lsb changed does not start at the type bitwidth boundary,
5852 // start at the previous one.
5854 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
5855 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
5856 if ((Imm & Mask) == Imm) {
5857 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
5858 if (Opc == ISD::AND)
5859 NewImm ^= APInt::getAllOnesValue(NewBW);
5860 uint64_t PtrOff = ShAmt / 8;
5861 // For big endian targets, we need to adjust the offset to the pointer to
5862 // load the correct bytes.
5863 if (TLI.isBigEndian())
5864 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
5866 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
5867 const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
5868 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy))
5871 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
5872 Ptr.getValueType(), Ptr,
5873 DAG.getConstant(PtrOff, Ptr.getValueType()));
5874 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
5875 LD->getChain(), NewPtr,
5876 LD->getPointerInfo().getWithOffset(PtrOff),
5877 LD->isVolatile(), LD->isNonTemporal(),
5879 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
5880 DAG.getConstant(NewImm, NewVT));
5881 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
5883 ST->getPointerInfo().getWithOffset(PtrOff),
5884 false, false, NewAlign);
5886 AddToWorkList(NewPtr.getNode());
5887 AddToWorkList(NewLD.getNode());
5888 AddToWorkList(NewVal.getNode());
5889 WorkListRemover DeadNodes(*this);
5890 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1),
5900 SDValue DAGCombiner::visitSTORE(SDNode *N) {
5901 StoreSDNode *ST = cast<StoreSDNode>(N);
5902 SDValue Chain = ST->getChain();
5903 SDValue Value = ST->getValue();
5904 SDValue Ptr = ST->getBasePtr();
5906 // If this is a store of a bit convert, store the input value if the
5907 // resultant store does not need a higher alignment than the original.
5908 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
5909 ST->isUnindexed()) {
5910 unsigned OrigAlign = ST->getAlignment();
5911 EVT SVT = Value.getOperand(0).getValueType();
5912 unsigned Align = TLI.getTargetData()->
5913 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
5914 if (Align <= OrigAlign &&
5915 ((!LegalOperations && !ST->isVolatile()) ||
5916 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
5917 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
5918 Ptr, ST->getPointerInfo(), ST->isVolatile(),
5919 ST->isNonTemporal(), OrigAlign);
5922 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
5923 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
5924 // NOTE: If the original store is volatile, this transform must not increase
5925 // the number of stores. For example, on x86-32 an f64 can be stored in one
5926 // processor operation but an i64 (which is not legal) requires two. So the
5927 // transform should not be done in this case.
5928 if (Value.getOpcode() != ISD::TargetConstantFP) {
5930 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
5931 default: llvm_unreachable("Unknown FP type");
5932 case MVT::f80: // We don't do this for these yet.
5937 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
5938 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
5939 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
5940 bitcastToAPInt().getZExtValue(), MVT::i32);
5941 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
5942 Ptr, ST->getPointerInfo(), ST->isVolatile(),
5943 ST->isNonTemporal(), ST->getAlignment());
5947 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
5948 !ST->isVolatile()) ||
5949 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
5950 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
5951 getZExtValue(), MVT::i64);
5952 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
5953 Ptr, ST->getPointerInfo(), ST->isVolatile(),
5954 ST->isNonTemporal(), ST->getAlignment());
5955 } else if (!ST->isVolatile() &&
5956 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
5957 // Many FP stores are not made apparent until after legalize, e.g. for
5958 // argument passing. Since this is so common, custom legalize the
5959 // 64-bit integer store into two 32-bit stores.
5960 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
5961 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
5962 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
5963 if (TLI.isBigEndian()) std::swap(Lo, Hi);
5965 unsigned Alignment = ST->getAlignment();
5966 bool isVolatile = ST->isVolatile();
5967 bool isNonTemporal = ST->isNonTemporal();
5969 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
5970 Ptr, ST->getPointerInfo(),
5971 isVolatile, isNonTemporal,
5972 ST->getAlignment());
5973 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
5974 DAG.getConstant(4, Ptr.getValueType()));
5975 Alignment = MinAlign(Alignment, 4U);
5976 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
5977 Ptr, ST->getPointerInfo().getWithOffset(4),
5978 isVolatile, isNonTemporal,
5980 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
5989 // Try to infer better alignment information than the store already has.
5990 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
5991 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
5992 if (Align > ST->getAlignment())
5993 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
5994 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
5995 ST->isVolatile(), ST->isNonTemporal(), Align);
6000 // Walk up chain skipping non-aliasing memory nodes.
6001 SDValue BetterChain = FindBetterChain(N, Chain);
6003 // If there is a better chain.
6004 if (Chain != BetterChain) {
6007 // Replace the chain to avoid dependency.
6008 if (ST->isTruncatingStore()) {
6009 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
6010 ST->getPointerInfo(),
6011 ST->getMemoryVT(), ST->isVolatile(),
6012 ST->isNonTemporal(), ST->getAlignment());
6014 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
6015 ST->getPointerInfo(),
6016 ST->isVolatile(), ST->isNonTemporal(),
6017 ST->getAlignment());
6020 // Create token to keep both nodes around.
6021 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
6022 MVT::Other, Chain, ReplStore);
6024 // Make sure the new and old chains are cleaned up.
6025 AddToWorkList(Token.getNode());
6027 // Don't add users to work list.
6028 return CombineTo(N, Token, false);
6032 // Try transforming N to an indexed store.
6033 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
6034 return SDValue(N, 0);
6036 // FIXME: is there such a thing as a truncating indexed store?
6037 if (ST->isTruncatingStore() && ST->isUnindexed() &&
6038 Value.getValueType().isInteger()) {
6039 // See if we can simplify the input to this truncstore with knowledge that
6040 // only the low bits are being used. For example:
6041 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
6043 GetDemandedBits(Value,
6044 APInt::getLowBitsSet(Value.getValueSizeInBits(),
6045 ST->getMemoryVT().getSizeInBits()));
6046 AddToWorkList(Value.getNode());
6047 if (Shorter.getNode())
6048 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
6049 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6050 ST->isVolatile(), ST->isNonTemporal(),
6051 ST->getAlignment());
6053 // Otherwise, see if we can simplify the operation with
6054 // SimplifyDemandedBits, which only works if the value has a single use.
6055 if (SimplifyDemandedBits(Value,
6056 APInt::getLowBitsSet(
6057 Value.getValueType().getScalarType().getSizeInBits(),
6058 ST->getMemoryVT().getScalarType().getSizeInBits())))
6059 return SDValue(N, 0);
6062 // If this is a load followed by a store to the same location, then the store
6064 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
6065 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
6066 ST->isUnindexed() && !ST->isVolatile() &&
6067 // There can't be any side effects between the load and store, such as
6069 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
6070 // The store is dead, remove it.
6075 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
6076 // truncating store. We can do this even if this is already a truncstore.
6077 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
6078 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
6079 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
6080 ST->getMemoryVT())) {
6081 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
6082 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6083 ST->isVolatile(), ST->isNonTemporal(),
6084 ST->getAlignment());
6087 return ReduceLoadOpStoreWidth(N);
6090 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
6091 SDValue InVec = N->getOperand(0);
6092 SDValue InVal = N->getOperand(1);
6093 SDValue EltNo = N->getOperand(2);
6095 // If the inserted element is an UNDEF, just use the input vector.
6096 if (InVal.getOpcode() == ISD::UNDEF)
6099 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
6100 // vector with the inserted element.
6101 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
6102 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6103 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
6104 InVec.getNode()->op_end());
6105 if (Elt < Ops.size())
6107 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6108 InVec.getValueType(), &Ops[0], Ops.size());
6110 // If the invec is an UNDEF and if EltNo is a constant, create a new
6111 // BUILD_VECTOR with undef elements and the inserted element.
6112 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF &&
6113 isa<ConstantSDNode>(EltNo)) {
6114 EVT VT = InVec.getValueType();
6115 EVT EltVT = VT.getVectorElementType();
6116 unsigned NElts = VT.getVectorNumElements();
6117 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT));
6119 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6120 if (Elt < Ops.size())
6122 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6123 InVec.getValueType(), &Ops[0], Ops.size());
6128 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
6129 // (vextract (scalar_to_vector val, 0) -> val
6130 SDValue InVec = N->getOperand(0);
6132 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
6133 // Check if the result type doesn't match the inserted element type. A
6134 // SCALAR_TO_VECTOR may truncate the inserted element and the
6135 // EXTRACT_VECTOR_ELT may widen the extracted vector.
6136 SDValue InOp = InVec.getOperand(0);
6137 EVT NVT = N->getValueType(0);
6138 if (InOp.getValueType() != NVT) {
6139 assert(InOp.getValueType().isInteger() && NVT.isInteger());
6140 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
6145 // Perform only after legalization to ensure build_vector / vector_shuffle
6146 // optimizations have already been done.
6147 if (!LegalOperations) return SDValue();
6149 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
6150 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
6151 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
6152 SDValue EltNo = N->getOperand(1);
6154 if (isa<ConstantSDNode>(EltNo)) {
6155 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6156 bool NewLoad = false;
6157 bool BCNumEltsChanged = false;
6158 EVT VT = InVec.getValueType();
6159 EVT ExtVT = VT.getVectorElementType();
6162 if (InVec.getOpcode() == ISD::BIT_CONVERT) {
6163 EVT BCVT = InVec.getOperand(0).getValueType();
6164 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
6166 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
6167 BCNumEltsChanged = true;
6168 InVec = InVec.getOperand(0);
6169 ExtVT = BCVT.getVectorElementType();
6173 LoadSDNode *LN0 = NULL;
6174 const ShuffleVectorSDNode *SVN = NULL;
6175 if (ISD::isNormalLoad(InVec.getNode())) {
6176 LN0 = cast<LoadSDNode>(InVec);
6177 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6178 InVec.getOperand(0).getValueType() == ExtVT &&
6179 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
6180 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
6181 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
6182 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
6184 // (load $addr+1*size)
6186 // If the bit convert changed the number of elements, it is unsafe
6187 // to examine the mask.
6188 if (BCNumEltsChanged)
6191 // Select the input vector, guarding against out of range extract vector.
6192 unsigned NumElems = VT.getVectorNumElements();
6193 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt);
6194 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
6196 if (InVec.getOpcode() == ISD::BIT_CONVERT)
6197 InVec = InVec.getOperand(0);
6198 if (ISD::isNormalLoad(InVec.getNode())) {
6199 LN0 = cast<LoadSDNode>(InVec);
6200 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
6204 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile())
6207 unsigned Align = LN0->getAlignment();
6209 // Check the resultant load doesn't need a higher alignment than the
6212 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
6214 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
6220 SDValue NewPtr = LN0->getBasePtr();
6221 unsigned PtrOff = 0;
6223 PtrOff = LVT.getSizeInBits() * Elt / 8;
6224 EVT PtrType = NewPtr.getValueType();
6225 if (TLI.isBigEndian())
6226 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
6227 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
6228 DAG.getConstant(PtrOff, PtrType));
6231 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
6232 LN0->getPointerInfo().getWithOffset(PtrOff),
6233 LN0->isVolatile(), LN0->isNonTemporal(), Align);
6239 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
6240 unsigned NumInScalars = N->getNumOperands();
6241 EVT VT = N->getValueType(0);
6243 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
6244 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
6245 // at most two distinct vectors, turn this into a shuffle node.
6246 SDValue VecIn1, VecIn2;
6247 for (unsigned i = 0; i != NumInScalars; ++i) {
6248 // Ignore undef inputs.
6249 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6251 // If this input is something other than a EXTRACT_VECTOR_ELT with a
6252 // constant index, bail out.
6253 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6254 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
6255 VecIn1 = VecIn2 = SDValue(0, 0);
6259 // If the input vector type disagrees with the result of the build_vector,
6260 // we can't make a shuffle.
6261 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
6262 if (ExtractedFromVec.getValueType() != VT) {
6263 VecIn1 = VecIn2 = SDValue(0, 0);
6267 // Otherwise, remember this. We allow up to two distinct input vectors.
6268 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
6271 if (VecIn1.getNode() == 0) {
6272 VecIn1 = ExtractedFromVec;
6273 } else if (VecIn2.getNode() == 0) {
6274 VecIn2 = ExtractedFromVec;
6277 VecIn1 = VecIn2 = SDValue(0, 0);
6282 // If everything is good, we can make a shuffle operation.
6283 if (VecIn1.getNode()) {
6284 SmallVector<int, 8> Mask;
6285 for (unsigned i = 0; i != NumInScalars; ++i) {
6286 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
6291 // If extracting from the first vector, just use the index directly.
6292 SDValue Extract = N->getOperand(i);
6293 SDValue ExtVal = Extract.getOperand(1);
6294 if (Extract.getOperand(0) == VecIn1) {
6295 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
6296 if (ExtIndex > VT.getVectorNumElements())
6299 Mask.push_back(ExtIndex);
6303 // Otherwise, use InIdx + VecSize
6304 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
6305 Mask.push_back(Idx+NumInScalars);
6308 // Add count and size info.
6309 if (!isTypeLegal(VT))
6312 // Return the new VECTOR_SHUFFLE node.
6315 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6316 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
6322 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
6323 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
6324 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
6325 // inputs come from at most two distinct vectors, turn this into a shuffle
6328 // If we only have one input vector, we don't need to do any concatenation.
6329 if (N->getNumOperands() == 1)
6330 return N->getOperand(0);
6335 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
6336 EVT VT = N->getValueType(0);
6337 unsigned NumElts = VT.getVectorNumElements();
6339 SDValue N0 = N->getOperand(0);
6341 assert(N0.getValueType().getVectorNumElements() == NumElts &&
6342 "Vector shuffle must be normalized in DAG");
6344 // FIXME: implement canonicalizations from DAG.getVectorShuffle()
6346 // If it is a splat, check if the argument vector is a build_vector with
6347 // all scalar elements the same.
6348 if (cast<ShuffleVectorSDNode>(N)->isSplat()) {
6349 SDNode *V = N0.getNode();
6351 // If this is a bit convert that changes the element type of the vector but
6352 // not the number of vector elements, look through it. Be careful not to
6353 // look though conversions that change things like v4f32 to v2f64.
6354 if (V->getOpcode() == ISD::BIT_CONVERT) {
6355 SDValue ConvInput = V->getOperand(0);
6356 if (ConvInput.getValueType().isVector() &&
6357 ConvInput.getValueType().getVectorNumElements() == NumElts)
6358 V = ConvInput.getNode();
6361 if (V->getOpcode() == ISD::BUILD_VECTOR) {
6362 unsigned NumElems = V->getNumOperands();
6363 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex();
6364 if (NumElems > BaseIdx) {
6366 bool AllSame = true;
6367 for (unsigned i = 0; i != NumElems; ++i) {
6368 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
6369 Base = V->getOperand(i);
6373 // Splat of <u, u, u, u>, return <u, u, u, u>
6374 if (!Base.getNode())
6376 for (unsigned i = 0; i != NumElems; ++i) {
6377 if (V->getOperand(i) != Base) {
6382 // Splat of <x, x, x, x>, return <x, x, x, x>
6391 SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) {
6392 if (!TLI.getShouldFoldAtomicFences())
6395 SDValue atomic = N->getOperand(0);
6396 switch (atomic.getOpcode()) {
6397 case ISD::ATOMIC_CMP_SWAP:
6398 case ISD::ATOMIC_SWAP:
6399 case ISD::ATOMIC_LOAD_ADD:
6400 case ISD::ATOMIC_LOAD_SUB:
6401 case ISD::ATOMIC_LOAD_AND:
6402 case ISD::ATOMIC_LOAD_OR:
6403 case ISD::ATOMIC_LOAD_XOR:
6404 case ISD::ATOMIC_LOAD_NAND:
6405 case ISD::ATOMIC_LOAD_MIN:
6406 case ISD::ATOMIC_LOAD_MAX:
6407 case ISD::ATOMIC_LOAD_UMIN:
6408 case ISD::ATOMIC_LOAD_UMAX:
6414 SDValue fence = atomic.getOperand(0);
6415 if (fence.getOpcode() != ISD::MEMBARRIER)
6418 switch (atomic.getOpcode()) {
6419 case ISD::ATOMIC_CMP_SWAP:
6420 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
6421 fence.getOperand(0),
6422 atomic.getOperand(1), atomic.getOperand(2),
6423 atomic.getOperand(3)), atomic.getResNo());
6424 case ISD::ATOMIC_SWAP:
6425 case ISD::ATOMIC_LOAD_ADD:
6426 case ISD::ATOMIC_LOAD_SUB:
6427 case ISD::ATOMIC_LOAD_AND:
6428 case ISD::ATOMIC_LOAD_OR:
6429 case ISD::ATOMIC_LOAD_XOR:
6430 case ISD::ATOMIC_LOAD_NAND:
6431 case ISD::ATOMIC_LOAD_MIN:
6432 case ISD::ATOMIC_LOAD_MAX:
6433 case ISD::ATOMIC_LOAD_UMIN:
6434 case ISD::ATOMIC_LOAD_UMAX:
6435 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
6436 fence.getOperand(0),
6437 atomic.getOperand(1), atomic.getOperand(2)),
6444 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
6445 /// an AND to a vector_shuffle with the destination vector and a zero vector.
6446 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
6447 /// vector_shuffle V, Zero, <0, 4, 2, 4>
6448 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
6449 EVT VT = N->getValueType(0);
6450 DebugLoc dl = N->getDebugLoc();
6451 SDValue LHS = N->getOperand(0);
6452 SDValue RHS = N->getOperand(1);
6453 if (N->getOpcode() == ISD::AND) {
6454 if (RHS.getOpcode() == ISD::BIT_CONVERT)
6455 RHS = RHS.getOperand(0);
6456 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
6457 SmallVector<int, 8> Indices;
6458 unsigned NumElts = RHS.getNumOperands();
6459 for (unsigned i = 0; i != NumElts; ++i) {
6460 SDValue Elt = RHS.getOperand(i);
6461 if (!isa<ConstantSDNode>(Elt))
6463 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
6464 Indices.push_back(i);
6465 else if (cast<ConstantSDNode>(Elt)->isNullValue())
6466 Indices.push_back(NumElts);
6471 // Let's see if the target supports this vector_shuffle.
6472 EVT RVT = RHS.getValueType();
6473 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
6476 // Return the new VECTOR_SHUFFLE node.
6477 EVT EltVT = RVT.getVectorElementType();
6478 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
6479 DAG.getConstant(0, EltVT));
6480 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6481 RVT, &ZeroOps[0], ZeroOps.size());
6482 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS);
6483 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
6484 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf);
6491 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
6492 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
6493 // After legalize, the target may be depending on adds and other
6494 // binary ops to provide legal ways to construct constants or other
6495 // things. Simplifying them may result in a loss of legality.
6496 if (LegalOperations) return SDValue();
6498 EVT VT = N->getValueType(0);
6499 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!");
6501 EVT EltType = VT.getVectorElementType();
6502 SDValue LHS = N->getOperand(0);
6503 SDValue RHS = N->getOperand(1);
6504 SDValue Shuffle = XformToShuffleWithZero(N);
6505 if (Shuffle.getNode()) return Shuffle;
6507 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
6509 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
6510 RHS.getOpcode() == ISD::BUILD_VECTOR) {
6511 SmallVector<SDValue, 8> Ops;
6512 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
6513 SDValue LHSOp = LHS.getOperand(i);
6514 SDValue RHSOp = RHS.getOperand(i);
6515 // If these two elements can't be folded, bail out.
6516 if ((LHSOp.getOpcode() != ISD::UNDEF &&
6517 LHSOp.getOpcode() != ISD::Constant &&
6518 LHSOp.getOpcode() != ISD::ConstantFP) ||
6519 (RHSOp.getOpcode() != ISD::UNDEF &&
6520 RHSOp.getOpcode() != ISD::Constant &&
6521 RHSOp.getOpcode() != ISD::ConstantFP))
6524 // Can't fold divide by zero.
6525 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
6526 N->getOpcode() == ISD::FDIV) {
6527 if ((RHSOp.getOpcode() == ISD::Constant &&
6528 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
6529 (RHSOp.getOpcode() == ISD::ConstantFP &&
6530 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
6534 // If the vector element type is not legal, the BUILD_VECTOR operands
6535 // are promoted and implicitly truncated. Make that explicit here.
6536 if (LHSOp.getValueType() != EltType)
6537 LHSOp = DAG.getNode(ISD::TRUNCATE, LHS.getDebugLoc(), EltType, LHSOp);
6538 if (RHSOp.getValueType() != EltType)
6539 RHSOp = DAG.getNode(ISD::TRUNCATE, RHS.getDebugLoc(), EltType, RHSOp);
6541 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), EltType,
6543 if (FoldOp.getOpcode() != ISD::UNDEF &&
6544 FoldOp.getOpcode() != ISD::Constant &&
6545 FoldOp.getOpcode() != ISD::ConstantFP)
6547 Ops.push_back(FoldOp);
6548 AddToWorkList(FoldOp.getNode());
6551 if (Ops.size() == LHS.getNumOperands()) {
6552 EVT VT = LHS.getValueType();
6553 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
6554 &Ops[0], Ops.size());
6561 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
6562 SDValue N1, SDValue N2){
6563 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
6565 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
6566 cast<CondCodeSDNode>(N0.getOperand(2))->get());
6568 // If we got a simplified select_cc node back from SimplifySelectCC, then
6569 // break it down into a new SETCC node, and a new SELECT node, and then return
6570 // the SELECT node, since we were called with a SELECT node.
6571 if (SCC.getNode()) {
6572 // Check to see if we got a select_cc back (to turn into setcc/select).
6573 // Otherwise, just return whatever node we got back, like fabs.
6574 if (SCC.getOpcode() == ISD::SELECT_CC) {
6575 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
6577 SCC.getOperand(0), SCC.getOperand(1),
6579 AddToWorkList(SETCC.getNode());
6580 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
6581 SCC.getOperand(2), SCC.getOperand(3), SETCC);
6589 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
6590 /// are the two values being selected between, see if we can simplify the
6591 /// select. Callers of this should assume that TheSelect is deleted if this
6592 /// returns true. As such, they should return the appropriate thing (e.g. the
6593 /// node) back to the top-level of the DAG combiner loop to avoid it being
6595 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
6598 // If this is a select from two identical things, try to pull the operation
6599 // through the select.
6600 if (LHS.getOpcode() != RHS.getOpcode() ||
6601 !LHS.hasOneUse() || !RHS.hasOneUse())
6604 // If this is a load and the token chain is identical, replace the select
6605 // of two loads with a load through a select of the address to load from.
6606 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
6607 // constants have been dropped into the constant pool.
6608 if (LHS.getOpcode() == ISD::LOAD) {
6609 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
6610 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
6612 // Token chains must be identical.
6613 if (LHS.getOperand(0) != RHS.getOperand(0) ||
6614 // Do not let this transformation reduce the number of volatile loads.
6615 LLD->isVolatile() || RLD->isVolatile() ||
6616 // If this is an EXTLOAD, the VT's must match.
6617 LLD->getMemoryVT() != RLD->getMemoryVT() ||
6618 // FIXME: this discards src value information. This is
6619 // over-conservative. It would be beneficial to be able to remember
6620 // both potential memory locations. Since we are discarding
6621 // src value info, don't do the transformation if the memory
6622 // locations are not in the default address space.
6623 LLD->getPointerInfo().getAddrSpace() != 0 ||
6624 RLD->getPointerInfo().getAddrSpace() != 0)
6627 // Check that the select condition doesn't reach either load. If so,
6628 // folding this will induce a cycle into the DAG. If not, this is safe to
6629 // xform, so create a select of the addresses.
6631 if (TheSelect->getOpcode() == ISD::SELECT) {
6632 SDNode *CondNode = TheSelect->getOperand(0).getNode();
6633 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
6634 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
6636 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
6637 LLD->getBasePtr().getValueType(),
6638 TheSelect->getOperand(0), LLD->getBasePtr(),
6640 } else { // Otherwise SELECT_CC
6641 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
6642 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
6644 if ((LLD->hasAnyUseOfValue(1) &&
6645 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
6646 (LLD->hasAnyUseOfValue(1) &&
6647 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))))
6650 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
6651 LLD->getBasePtr().getValueType(),
6652 TheSelect->getOperand(0),
6653 TheSelect->getOperand(1),
6654 LLD->getBasePtr(), RLD->getBasePtr(),
6655 TheSelect->getOperand(4));
6659 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
6660 Load = DAG.getLoad(TheSelect->getValueType(0),
6661 TheSelect->getDebugLoc(),
6662 // FIXME: Discards pointer info.
6663 LLD->getChain(), Addr, MachinePointerInfo(),
6664 LLD->isVolatile(), LLD->isNonTemporal(),
6665 LLD->getAlignment());
6667 Load = DAG.getExtLoad(LLD->getExtensionType(),
6668 TheSelect->getValueType(0),
6669 TheSelect->getDebugLoc(),
6670 // FIXME: Discards pointer info.
6671 LLD->getChain(), Addr, MachinePointerInfo(),
6672 LLD->getMemoryVT(), LLD->isVolatile(),
6673 LLD->isNonTemporal(), LLD->getAlignment());
6676 // Users of the select now use the result of the load.
6677 CombineTo(TheSelect, Load);
6679 // Users of the old loads now use the new load's chain. We know the
6680 // old-load value is dead now.
6681 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
6682 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
6689 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
6690 /// where 'cond' is the comparison specified by CC.
6691 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
6692 SDValue N2, SDValue N3,
6693 ISD::CondCode CC, bool NotExtCompare) {
6694 // (x ? y : y) -> y.
6695 if (N2 == N3) return N2;
6697 EVT VT = N2.getValueType();
6698 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
6699 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
6700 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
6702 // Determine if the condition we're dealing with is constant
6703 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
6704 N0, N1, CC, DL, false);
6705 if (SCC.getNode()) AddToWorkList(SCC.getNode());
6706 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
6708 // fold select_cc true, x, y -> x
6709 if (SCCC && !SCCC->isNullValue())
6711 // fold select_cc false, x, y -> y
6712 if (SCCC && SCCC->isNullValue())
6715 // Check to see if we can simplify the select into an fabs node
6716 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
6717 // Allow either -0.0 or 0.0
6718 if (CFP->getValueAPF().isZero()) {
6719 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
6720 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
6721 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
6722 N2 == N3.getOperand(0))
6723 return DAG.getNode(ISD::FABS, DL, VT, N0);
6725 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
6726 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
6727 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
6728 N2.getOperand(0) == N3)
6729 return DAG.getNode(ISD::FABS, DL, VT, N3);
6733 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
6734 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
6735 // in it. This is a win when the constant is not otherwise available because
6736 // it replaces two constant pool loads with one. We only do this if the FP
6737 // type is known to be legal, because if it isn't, then we are before legalize
6738 // types an we want the other legalization to happen first (e.g. to avoid
6739 // messing with soft float) and if the ConstantFP is not legal, because if
6740 // it is legal, we may not need to store the FP constant in a constant pool.
6741 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
6742 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
6743 if (TLI.isTypeLegal(N2.getValueType()) &&
6744 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
6745 TargetLowering::Legal) &&
6746 // If both constants have multiple uses, then we won't need to do an
6747 // extra load, they are likely around in registers for other users.
6748 (TV->hasOneUse() || FV->hasOneUse())) {
6749 Constant *Elts[] = {
6750 const_cast<ConstantFP*>(FV->getConstantFPValue()),
6751 const_cast<ConstantFP*>(TV->getConstantFPValue())
6753 const Type *FPTy = Elts[0]->getType();
6754 const TargetData &TD = *TLI.getTargetData();
6756 // Create a ConstantArray of the two constants.
6757 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2);
6758 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
6759 TD.getPrefTypeAlignment(FPTy));
6760 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6762 // Get the offsets to the 0 and 1 element of the array so that we can
6763 // select between them.
6764 SDValue Zero = DAG.getIntPtrConstant(0);
6765 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
6766 SDValue One = DAG.getIntPtrConstant(EltSize);
6768 SDValue Cond = DAG.getSetCC(DL,
6769 TLI.getSetCCResultType(N0.getValueType()),
6771 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
6773 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
6775 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
6776 MachinePointerInfo::getConstantPool(), false,
6782 // Check to see if we can perform the "gzip trick", transforming
6783 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
6784 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
6785 N0.getValueType().isInteger() &&
6786 N2.getValueType().isInteger() &&
6787 (N1C->isNullValue() || // (a < 0) ? b : 0
6788 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
6789 EVT XType = N0.getValueType();
6790 EVT AType = N2.getValueType();
6791 if (XType.bitsGE(AType)) {
6792 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
6793 // single-bit constant.
6794 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
6795 unsigned ShCtV = N2C->getAPIntValue().logBase2();
6796 ShCtV = XType.getSizeInBits()-ShCtV-1;
6797 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy());
6798 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
6800 AddToWorkList(Shift.getNode());
6802 if (XType.bitsGT(AType)) {
6803 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
6804 AddToWorkList(Shift.getNode());
6807 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
6810 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
6812 DAG.getConstant(XType.getSizeInBits()-1,
6813 getShiftAmountTy()));
6814 AddToWorkList(Shift.getNode());
6816 if (XType.bitsGT(AType)) {
6817 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
6818 AddToWorkList(Shift.getNode());
6821 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
6825 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
6826 // where y is has a single bit set.
6827 // A plaintext description would be, we can turn the SELECT_CC into an AND
6828 // when the condition can be materialized as an all-ones register. Any
6829 // single bit-test can be materialized as an all-ones register with
6830 // shift-left and shift-right-arith.
6831 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
6832 N0->getValueType(0) == VT &&
6833 N1C && N1C->isNullValue() &&
6834 N2C && N2C->isNullValue()) {
6835 SDValue AndLHS = N0->getOperand(0);
6836 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
6837 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
6838 // Shift the tested bit over the sign bit.
6839 APInt AndMask = ConstAndRHS->getAPIntValue();
6841 DAG.getConstant(AndMask.countLeadingZeros(), getShiftAmountTy());
6842 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt);
6844 // Now arithmetic right shift it all the way over, so the result is either
6845 // all-ones, or zero.
6847 DAG.getConstant(AndMask.getBitWidth()-1, getShiftAmountTy());
6848 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt);
6850 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
6854 // fold select C, 16, 0 -> shl C, 4
6855 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
6856 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {
6858 // If the caller doesn't want us to simplify this into a zext of a compare,
6860 if (NotExtCompare && N2C->getAPIntValue() == 1)
6863 // Get a SetCC of the condition
6864 // FIXME: Should probably make sure that setcc is legal if we ever have a
6865 // target where it isn't.
6867 // cast from setcc result type to select result type
6869 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
6871 if (N2.getValueType().bitsLT(SCC.getValueType()))
6872 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
6874 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
6875 N2.getValueType(), SCC);
6877 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
6878 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
6879 N2.getValueType(), SCC);
6882 AddToWorkList(SCC.getNode());
6883 AddToWorkList(Temp.getNode());
6885 if (N2C->getAPIntValue() == 1)
6888 // shl setcc result by log2 n2c
6889 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
6890 DAG.getConstant(N2C->getAPIntValue().logBase2(),
6891 getShiftAmountTy()));
6894 // Check to see if this is the equivalent of setcc
6895 // FIXME: Turn all of these into setcc if setcc if setcc is legal
6896 // otherwise, go ahead with the folds.
6897 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
6898 EVT XType = N0.getValueType();
6899 if (!LegalOperations ||
6900 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
6901 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
6902 if (Res.getValueType() != VT)
6903 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
6907 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
6908 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
6909 (!LegalOperations ||
6910 TLI.isOperationLegal(ISD::CTLZ, XType))) {
6911 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
6912 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
6913 DAG.getConstant(Log2_32(XType.getSizeInBits()),
6914 getShiftAmountTy()));
6916 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
6917 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
6918 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
6919 XType, DAG.getConstant(0, XType), N0);
6920 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
6921 return DAG.getNode(ISD::SRL, DL, XType,
6922 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
6923 DAG.getConstant(XType.getSizeInBits()-1,
6924 getShiftAmountTy()));
6926 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
6927 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
6928 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
6929 DAG.getConstant(XType.getSizeInBits()-1,
6930 getShiftAmountTy()));
6931 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
6935 // Check to see if this is an integer abs.
6936 // select_cc setg[te] X, 0, X, -X ->
6937 // select_cc setgt X, -1, X, -X ->
6938 // select_cc setl[te] X, 0, -X, X ->
6939 // select_cc setlt X, 1, -X, X ->
6940 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
6942 ConstantSDNode *SubC = NULL;
6943 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
6944 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
6945 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
6946 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
6947 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
6948 (N1C->isOne() && CC == ISD::SETLT)) &&
6949 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
6950 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
6952 EVT XType = N0.getValueType();
6953 if (SubC && SubC->isNullValue() && XType.isInteger()) {
6954 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
6956 DAG.getConstant(XType.getSizeInBits()-1,
6957 getShiftAmountTy()));
6958 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
6960 AddToWorkList(Shift.getNode());
6961 AddToWorkList(Add.getNode());
6962 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
6969 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
6970 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
6971 SDValue N1, ISD::CondCode Cond,
6972 DebugLoc DL, bool foldBooleans) {
6973 TargetLowering::DAGCombinerInfo
6974 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
6975 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
6978 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
6979 /// return a DAG expression to select that will generate the same value by
6980 /// multiplying by a magic number. See:
6981 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
6982 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
6983 std::vector<SDNode*> Built;
6984 SDValue S = TLI.BuildSDIV(N, DAG, &Built);
6986 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
6992 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
6993 /// return a DAG expression to select that will generate the same value by
6994 /// multiplying by a magic number. See:
6995 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
6996 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
6997 std::vector<SDNode*> Built;
6998 SDValue S = TLI.BuildUDIV(N, DAG, &Built);
7000 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
7006 /// FindBaseOffset - Return true if base is a frame index, which is known not
7007 // to alias with anything but itself. Provides base object and offset as results.
7008 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
7009 const GlobalValue *&GV, void *&CV) {
7010 // Assume it is a primitive operation.
7011 Base = Ptr; Offset = 0; GV = 0; CV = 0;
7013 // If it's an adding a simple constant then integrate the offset.
7014 if (Base.getOpcode() == ISD::ADD) {
7015 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
7016 Base = Base.getOperand(0);
7017 Offset += C->getZExtValue();
7021 // Return the underlying GlobalValue, and update the Offset. Return false
7022 // for GlobalAddressSDNode since the same GlobalAddress may be represented
7023 // by multiple nodes with different offsets.
7024 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
7025 GV = G->getGlobal();
7026 Offset += G->getOffset();
7030 // Return the underlying Constant value, and update the Offset. Return false
7031 // for ConstantSDNodes since the same constant pool entry may be represented
7032 // by multiple nodes with different offsets.
7033 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
7034 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal()
7035 : (void *)C->getConstVal();
7036 Offset += C->getOffset();
7039 // If it's any of the following then it can't alias with anything but itself.
7040 return isa<FrameIndexSDNode>(Base);
7043 /// isAlias - Return true if there is any possibility that the two addresses
7045 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
7046 const Value *SrcValue1, int SrcValueOffset1,
7047 unsigned SrcValueAlign1,
7048 SDValue Ptr2, int64_t Size2,
7049 const Value *SrcValue2, int SrcValueOffset2,
7050 unsigned SrcValueAlign2) const {
7051 // If they are the same then they must be aliases.
7052 if (Ptr1 == Ptr2) return true;
7054 // Gather base node and offset information.
7055 SDValue Base1, Base2;
7056 int64_t Offset1, Offset2;
7057 const GlobalValue *GV1, *GV2;
7059 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
7060 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
7062 // If they have a same base address then check to see if they overlap.
7063 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
7064 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
7066 // It is possible for different frame indices to alias each other, mostly
7067 // when tail call optimization reuses return address slots for arguments.
7068 // To catch this case, look up the actual index of frame indices to compute
7069 // the real alias relationship.
7070 if (isFrameIndex1 && isFrameIndex2) {
7071 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7072 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
7073 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
7074 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
7077 // Otherwise, if we know what the bases are, and they aren't identical, then
7078 // we know they cannot alias.
7079 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
7082 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
7083 // compared to the size and offset of the access, we may be able to prove they
7084 // do not alias. This check is conservative for now to catch cases created by
7085 // splitting vector types.
7086 if ((SrcValueAlign1 == SrcValueAlign2) &&
7087 (SrcValueOffset1 != SrcValueOffset2) &&
7088 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
7089 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
7090 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
7092 // There is no overlap between these relatively aligned accesses of similar
7093 // size, return no alias.
7094 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
7098 if (CombinerGlobalAA) {
7099 // Use alias analysis information.
7100 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
7101 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
7102 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
7103 AliasAnalysis::AliasResult AAResult =
7104 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
7105 if (AAResult == AliasAnalysis::NoAlias)
7109 // Otherwise we have to assume they alias.
7113 /// FindAliasInfo - Extracts the relevant alias information from the memory
7114 /// node. Returns true if the operand was a load.
7115 bool DAGCombiner::FindAliasInfo(SDNode *N,
7116 SDValue &Ptr, int64_t &Size,
7117 const Value *&SrcValue,
7118 int &SrcValueOffset,
7119 unsigned &SrcValueAlign) const {
7120 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7121 Ptr = LD->getBasePtr();
7122 Size = LD->getMemoryVT().getSizeInBits() >> 3;
7123 SrcValue = LD->getSrcValue();
7124 SrcValueOffset = LD->getSrcValueOffset();
7125 SrcValueAlign = LD->getOriginalAlignment();
7127 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7128 Ptr = ST->getBasePtr();
7129 Size = ST->getMemoryVT().getSizeInBits() >> 3;
7130 SrcValue = ST->getSrcValue();
7131 SrcValueOffset = ST->getSrcValueOffset();
7132 SrcValueAlign = ST->getOriginalAlignment();
7134 llvm_unreachable("FindAliasInfo expected a memory operand");
7140 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
7141 /// looking for aliasing nodes and adding them to the Aliases vector.
7142 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
7143 SmallVector<SDValue, 8> &Aliases) {
7144 SmallVector<SDValue, 8> Chains; // List of chains to visit.
7145 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
7147 // Get alias information for node.
7150 const Value *SrcValue;
7152 unsigned SrcValueAlign;
7153 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
7157 Chains.push_back(OriginalChain);
7160 // Look at each chain and determine if it is an alias. If so, add it to the
7161 // aliases list. If not, then continue up the chain looking for the next
7163 while (!Chains.empty()) {
7164 SDValue Chain = Chains.back();
7167 // For TokenFactor nodes, look at each operand and only continue up the
7168 // chain until we find two aliases. If we've seen two aliases, assume we'll
7169 // find more and revert to original chain since the xform is unlikely to be
7172 // FIXME: The depth check could be made to return the last non-aliasing
7173 // chain we found before we hit a tokenfactor rather than the original
7175 if (Depth > 6 || Aliases.size() == 2) {
7177 Aliases.push_back(OriginalChain);
7181 // Don't bother if we've been before.
7182 if (!Visited.insert(Chain.getNode()))
7185 switch (Chain.getOpcode()) {
7186 case ISD::EntryToken:
7187 // Entry token is ideal chain operand, but handled in FindBetterChain.
7192 // Get alias information for Chain.
7195 const Value *OpSrcValue;
7196 int OpSrcValueOffset;
7197 unsigned OpSrcValueAlign;
7198 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
7199 OpSrcValue, OpSrcValueOffset,
7202 // If chain is alias then stop here.
7203 if (!(IsLoad && IsOpLoad) &&
7204 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
7205 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
7207 Aliases.push_back(Chain);
7209 // Look further up the chain.
7210 Chains.push_back(Chain.getOperand(0));
7216 case ISD::TokenFactor:
7217 // We have to check each of the operands of the token factor for "small"
7218 // token factors, so we queue them up. Adding the operands to the queue
7219 // (stack) in reverse order maintains the original order and increases the
7220 // likelihood that getNode will find a matching token factor (CSE.)
7221 if (Chain.getNumOperands() > 16) {
7222 Aliases.push_back(Chain);
7225 for (unsigned n = Chain.getNumOperands(); n;)
7226 Chains.push_back(Chain.getOperand(--n));
7231 // For all other instructions we will just have to take what we can get.
7232 Aliases.push_back(Chain);
7238 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
7239 /// for a better chain (aliasing node.)
7240 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
7241 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
7243 // Accumulate all the aliases to this node.
7244 GatherAllAliases(N, OldChain, Aliases);
7246 if (Aliases.size() == 0) {
7247 // If no operands then chain to entry token.
7248 return DAG.getEntryNode();
7249 } else if (Aliases.size() == 1) {
7250 // If a single operand then chain to it. We don't need to revisit it.
7254 // Construct a custom tailored token factor.
7255 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
7256 &Aliases[0], Aliases.size());
7259 // SelectionDAG::Combine - This is the entry point for the file.
7261 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
7262 CodeGenOpt::Level OptLevel) {
7263 /// run - This is the main entry point to this class.
7265 DAGCombiner(*this, AA, OptLevel).Run(Level);