1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Analysis/AliasAnalysis.h"
27 #include "llvm/Target/TargetData.h"
28 #include "llvm/Target/TargetFrameInfo.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/ADT/SmallPtrSet.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
42 STATISTIC(NodesCombined , "Number of dag nodes combined");
43 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
44 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
45 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
49 CombinerAA("combiner-alias-analysis", cl::Hidden,
50 cl::desc("Turn on alias analysis during testing"));
53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
54 cl::desc("Include global information in alias analysis"));
56 //------------------------------ DAGCombiner ---------------------------------//
60 const TargetLowering &TLI;
62 CodeGenOpt::Level OptLevel;
66 // Worklist of all of the nodes that need to be simplified.
67 std::vector<SDNode*> WorkList;
69 // AA - Used for DAG load/store alias analysis.
72 /// AddUsersToWorkList - When an instruction is simplified, add all users of
73 /// the instruction to the work lists because they might get more simplified
76 void AddUsersToWorkList(SDNode *N) {
77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
82 /// visit - call the node-specific routine that knows how to fold each
83 /// particular type of node.
84 SDValue visit(SDNode *N);
87 /// AddToWorkList - Add to the work list making sure it's instance is at the
88 /// the back (next to be processed.)
89 void AddToWorkList(SDNode *N) {
90 removeFromWorkList(N);
91 WorkList.push_back(N);
94 /// removeFromWorkList - remove all instances of N from the worklist.
96 void removeFromWorkList(SDNode *N) {
97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
105 return CombineTo(N, &Res, 1, AddTo);
108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
110 SDValue To[] = { Res0, Res1 };
111 return CombineTo(N, To, 2, AddTo);
114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
118 /// SimplifyDemandedBits - Check the specified integer node value to see if
119 /// it can be simplified or if things it uses can be simplified by bit
120 /// propagation. If so, return true.
121 bool SimplifyDemandedBits(SDValue Op) {
122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
123 APInt Demanded = APInt::getAllOnesValue(BitWidth);
124 return SimplifyDemandedBits(Op, Demanded);
127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
129 bool CombineToPreIndexedLoadStore(SDNode *N);
130 bool CombineToPostIndexedLoadStore(SDNode *N);
132 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
133 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
134 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
135 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
136 SDValue PromoteIntBinOp(SDValue Op);
137 SDValue PromoteIntShiftOp(SDValue Op);
138 SDValue PromoteExtend(SDValue Op);
139 bool PromoteLoad(SDValue Op);
141 /// combine - call the node-specific routine that knows how to fold each
142 /// particular type of node. If that doesn't do anything, try the
143 /// target-specific DAG combines.
144 SDValue combine(SDNode *N);
146 // Visitation implementation - Implement dag node combining for different
147 // node types. The semantics are as follows:
149 // SDValue.getNode() == 0 - No change was made
150 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
151 // otherwise - N should be replaced by the returned Operand.
153 SDValue visitTokenFactor(SDNode *N);
154 SDValue visitMERGE_VALUES(SDNode *N);
155 SDValue visitADD(SDNode *N);
156 SDValue visitSUB(SDNode *N);
157 SDValue visitADDC(SDNode *N);
158 SDValue visitADDE(SDNode *N);
159 SDValue visitMUL(SDNode *N);
160 SDValue visitSDIV(SDNode *N);
161 SDValue visitUDIV(SDNode *N);
162 SDValue visitSREM(SDNode *N);
163 SDValue visitUREM(SDNode *N);
164 SDValue visitMULHU(SDNode *N);
165 SDValue visitMULHS(SDNode *N);
166 SDValue visitSMUL_LOHI(SDNode *N);
167 SDValue visitUMUL_LOHI(SDNode *N);
168 SDValue visitSDIVREM(SDNode *N);
169 SDValue visitUDIVREM(SDNode *N);
170 SDValue visitAND(SDNode *N);
171 SDValue visitOR(SDNode *N);
172 SDValue visitXOR(SDNode *N);
173 SDValue SimplifyVBinOp(SDNode *N);
174 SDValue visitSHL(SDNode *N);
175 SDValue visitSRA(SDNode *N);
176 SDValue visitSRL(SDNode *N);
177 SDValue visitCTLZ(SDNode *N);
178 SDValue visitCTTZ(SDNode *N);
179 SDValue visitCTPOP(SDNode *N);
180 SDValue visitSELECT(SDNode *N);
181 SDValue visitSELECT_CC(SDNode *N);
182 SDValue visitSETCC(SDNode *N);
183 SDValue visitSIGN_EXTEND(SDNode *N);
184 SDValue visitZERO_EXTEND(SDNode *N);
185 SDValue visitANY_EXTEND(SDNode *N);
186 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
187 SDValue visitTRUNCATE(SDNode *N);
188 SDValue visitBIT_CONVERT(SDNode *N);
189 SDValue visitBUILD_PAIR(SDNode *N);
190 SDValue visitFADD(SDNode *N);
191 SDValue visitFSUB(SDNode *N);
192 SDValue visitFMUL(SDNode *N);
193 SDValue visitFDIV(SDNode *N);
194 SDValue visitFREM(SDNode *N);
195 SDValue visitFCOPYSIGN(SDNode *N);
196 SDValue visitSINT_TO_FP(SDNode *N);
197 SDValue visitUINT_TO_FP(SDNode *N);
198 SDValue visitFP_TO_SINT(SDNode *N);
199 SDValue visitFP_TO_UINT(SDNode *N);
200 SDValue visitFP_ROUND(SDNode *N);
201 SDValue visitFP_ROUND_INREG(SDNode *N);
202 SDValue visitFP_EXTEND(SDNode *N);
203 SDValue visitFNEG(SDNode *N);
204 SDValue visitFABS(SDNode *N);
205 SDValue visitBRCOND(SDNode *N);
206 SDValue visitBR_CC(SDNode *N);
207 SDValue visitLOAD(SDNode *N);
208 SDValue visitSTORE(SDNode *N);
209 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
210 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
211 SDValue visitBUILD_VECTOR(SDNode *N);
212 SDValue visitCONCAT_VECTORS(SDNode *N);
213 SDValue visitVECTOR_SHUFFLE(SDNode *N);
215 SDValue XformToShuffleWithZero(SDNode *N);
216 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
218 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
220 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
221 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
222 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
223 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
224 SDValue N3, ISD::CondCode CC,
225 bool NotExtCompare = false);
226 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
227 DebugLoc DL, bool foldBooleans = true);
228 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
230 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
231 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT);
232 SDValue BuildSDIV(SDNode *N);
233 SDValue BuildUDIV(SDNode *N);
234 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
235 SDValue ReduceLoadWidth(SDNode *N);
236 SDValue ReduceLoadOpStoreWidth(SDNode *N);
238 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
240 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
241 /// looking for aliasing nodes and adding them to the Aliases vector.
242 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
243 SmallVector<SDValue, 8> &Aliases);
245 /// isAlias - Return true if there is any possibility that the two addresses
247 bool isAlias(SDValue Ptr1, int64_t Size1,
248 const Value *SrcValue1, int SrcValueOffset1,
249 unsigned SrcValueAlign1,
250 SDValue Ptr2, int64_t Size2,
251 const Value *SrcValue2, int SrcValueOffset2,
252 unsigned SrcValueAlign2) const;
254 /// FindAliasInfo - Extracts the relevant alias information from the memory
255 /// node. Returns true if the operand was a load.
256 bool FindAliasInfo(SDNode *N,
257 SDValue &Ptr, int64_t &Size,
258 const Value *&SrcValue, int &SrcValueOffset,
259 unsigned &SrcValueAlignment) const;
261 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
262 /// looking for a better chain (aliasing node.)
263 SDValue FindBetterChain(SDNode *N, SDValue Chain);
266 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
267 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted),
268 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
270 /// Run - runs the dag combiner on all nodes in the work list
271 void Run(CombineLevel AtLevel);
273 SelectionDAG &getDAG() const { return DAG; }
275 /// getShiftAmountTy - Returns a type large enough to hold any valid
276 /// shift amount - before type legalization these can be huge.
277 EVT getShiftAmountTy() {
278 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy();
281 /// isTypeLegal - This method returns true if we are running before type
282 /// legalization or if the specified VT is legal.
283 bool isTypeLegal(const EVT &VT) {
284 if (!LegalTypes) return true;
285 return TLI.isTypeLegal(VT);
292 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
293 /// nodes from the worklist.
294 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
297 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
299 virtual void NodeDeleted(SDNode *N, SDNode *E) {
300 DC.removeFromWorkList(N);
303 virtual void NodeUpdated(SDNode *N) {
309 //===----------------------------------------------------------------------===//
310 // TargetLowering::DAGCombinerInfo implementation
311 //===----------------------------------------------------------------------===//
313 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
314 ((DAGCombiner*)DC)->AddToWorkList(N);
317 SDValue TargetLowering::DAGCombinerInfo::
318 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
319 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
322 SDValue TargetLowering::DAGCombinerInfo::
323 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
324 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
328 SDValue TargetLowering::DAGCombinerInfo::
329 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
330 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
333 void TargetLowering::DAGCombinerInfo::
334 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
335 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
338 //===----------------------------------------------------------------------===//
340 //===----------------------------------------------------------------------===//
342 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
343 /// specified expression for the same cost as the expression itself, or 2 if we
344 /// can compute the negated form more cheaply than the expression itself.
345 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
346 unsigned Depth = 0) {
347 // No compile time optimizations on this type.
348 if (Op.getValueType() == MVT::ppcf128)
351 // fneg is removable even if it has multiple uses.
352 if (Op.getOpcode() == ISD::FNEG) return 2;
354 // Don't allow anything with multiple uses.
355 if (!Op.hasOneUse()) return 0;
357 // Don't recurse exponentially.
358 if (Depth > 6) return 0;
360 switch (Op.getOpcode()) {
361 default: return false;
362 case ISD::ConstantFP:
363 // Don't invert constant FP values after legalize. The negated constant
364 // isn't necessarily legal.
365 return LegalOperations ? 0 : 1;
367 // FIXME: determine better conditions for this xform.
368 if (!UnsafeFPMath) return 0;
370 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
371 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
373 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
374 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
376 // We can't turn -(A-B) into B-A when we honor signed zeros.
377 if (!UnsafeFPMath) return 0;
379 // fold (fneg (fsub A, B)) -> (fsub B, A)
384 if (HonorSignDependentRoundingFPMath()) return 0;
386 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
387 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
390 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
395 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1);
399 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
400 /// returns the newly negated expression.
401 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
402 bool LegalOperations, unsigned Depth = 0) {
403 // fneg is removable even if it has multiple uses.
404 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
406 // Don't allow anything with multiple uses.
407 assert(Op.hasOneUse() && "Unknown reuse!");
409 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
410 switch (Op.getOpcode()) {
411 default: llvm_unreachable("Unknown code");
412 case ISD::ConstantFP: {
413 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
415 return DAG.getConstantFP(V, Op.getValueType());
418 // FIXME: determine better conditions for this xform.
419 assert(UnsafeFPMath);
421 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
422 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
423 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
424 GetNegatedExpression(Op.getOperand(0), DAG,
425 LegalOperations, Depth+1),
427 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
428 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
429 GetNegatedExpression(Op.getOperand(1), DAG,
430 LegalOperations, Depth+1),
433 // We can't turn -(A-B) into B-A when we honor signed zeros.
434 assert(UnsafeFPMath);
436 // fold (fneg (fsub 0, B)) -> B
437 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
438 if (N0CFP->getValueAPF().isZero())
439 return Op.getOperand(1);
441 // fold (fneg (fsub A, B)) -> (fsub B, A)
442 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
443 Op.getOperand(1), Op.getOperand(0));
447 assert(!HonorSignDependentRoundingFPMath());
449 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
450 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
451 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
452 GetNegatedExpression(Op.getOperand(0), DAG,
453 LegalOperations, Depth+1),
456 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
457 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
459 GetNegatedExpression(Op.getOperand(1), DAG,
460 LegalOperations, Depth+1));
464 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
465 GetNegatedExpression(Op.getOperand(0), DAG,
466 LegalOperations, Depth+1));
468 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
469 GetNegatedExpression(Op.getOperand(0), DAG,
470 LegalOperations, Depth+1),
476 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
477 // that selects between the values 1 and 0, making it equivalent to a setcc.
478 // Also, set the incoming LHS, RHS, and CC references to the appropriate
479 // nodes based on the type of node we are checking. This simplifies life a
480 // bit for the callers.
481 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
483 if (N.getOpcode() == ISD::SETCC) {
484 LHS = N.getOperand(0);
485 RHS = N.getOperand(1);
486 CC = N.getOperand(2);
489 if (N.getOpcode() == ISD::SELECT_CC &&
490 N.getOperand(2).getOpcode() == ISD::Constant &&
491 N.getOperand(3).getOpcode() == ISD::Constant &&
492 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
493 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
494 LHS = N.getOperand(0);
495 RHS = N.getOperand(1);
496 CC = N.getOperand(4);
502 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
503 // one use. If this is true, it allows the users to invert the operation for
504 // free when it is profitable to do so.
505 static bool isOneUseSetCC(SDValue N) {
507 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
512 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
513 SDValue N0, SDValue N1) {
514 EVT VT = N0.getValueType();
515 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
516 if (isa<ConstantSDNode>(N1)) {
517 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
519 DAG.FoldConstantArithmetic(Opc, VT,
520 cast<ConstantSDNode>(N0.getOperand(1)),
521 cast<ConstantSDNode>(N1));
522 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
523 } else if (N0.hasOneUse()) {
524 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
525 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
526 N0.getOperand(0), N1);
527 AddToWorkList(OpNode.getNode());
528 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
532 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
533 if (isa<ConstantSDNode>(N0)) {
534 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
536 DAG.FoldConstantArithmetic(Opc, VT,
537 cast<ConstantSDNode>(N1.getOperand(1)),
538 cast<ConstantSDNode>(N0));
539 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
540 } else if (N1.hasOneUse()) {
541 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
542 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
543 N1.getOperand(0), N0);
544 AddToWorkList(OpNode.getNode());
545 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
552 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
554 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
556 DEBUG(dbgs() << "\nReplacing.1 ";
558 dbgs() << "\nWith: ";
559 To[0].getNode()->dump(&DAG);
560 dbgs() << " and " << NumTo-1 << " other values\n";
561 for (unsigned i = 0, e = NumTo; i != e; ++i)
562 assert((!To[i].getNode() ||
563 N->getValueType(i) == To[i].getValueType()) &&
564 "Cannot combine value to value of different type!"));
565 WorkListRemover DeadNodes(*this);
566 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
569 // Push the new nodes and any users onto the worklist
570 for (unsigned i = 0, e = NumTo; i != e; ++i) {
571 if (To[i].getNode()) {
572 AddToWorkList(To[i].getNode());
573 AddUsersToWorkList(To[i].getNode());
578 // Finally, if the node is now dead, remove it from the graph. The node
579 // may not be dead if the replacement process recursively simplified to
580 // something else needing this node.
581 if (N->use_empty()) {
582 // Nodes can be reintroduced into the worklist. Make sure we do not
583 // process a node that has been replaced.
584 removeFromWorkList(N);
586 // Finally, since the node is now dead, remove it from the graph.
589 return SDValue(N, 0);
593 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
594 // Replace all uses. If any nodes become isomorphic to other nodes and
595 // are deleted, make sure to remove them from our worklist.
596 WorkListRemover DeadNodes(*this);
597 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
599 // Push the new node and any (possibly new) users onto the worklist.
600 AddToWorkList(TLO.New.getNode());
601 AddUsersToWorkList(TLO.New.getNode());
603 // Finally, if the node is now dead, remove it from the graph. The node
604 // may not be dead if the replacement process recursively simplified to
605 // something else needing this node.
606 if (TLO.Old.getNode()->use_empty()) {
607 removeFromWorkList(TLO.Old.getNode());
609 // If the operands of this node are only used by the node, they will now
610 // be dead. Make sure to visit them first to delete dead nodes early.
611 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
612 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
613 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
615 DAG.DeleteNode(TLO.Old.getNode());
619 /// SimplifyDemandedBits - Check the specified integer node value to see if
620 /// it can be simplified or if things it uses can be simplified by bit
621 /// propagation. If so, return true.
622 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
623 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
624 APInt KnownZero, KnownOne;
625 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
629 AddToWorkList(Op.getNode());
631 // Replace the old value with the new one.
633 DEBUG(dbgs() << "\nReplacing.2 ";
634 TLO.Old.getNode()->dump(&DAG);
635 dbgs() << "\nWith: ";
636 TLO.New.getNode()->dump(&DAG);
639 CommitTargetLoweringOpt(TLO);
643 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
644 DebugLoc dl = Load->getDebugLoc();
645 EVT VT = Load->getValueType(0);
646 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
648 DEBUG(dbgs() << "\nReplacing.9 ";
650 dbgs() << "\nWith: ";
651 Trunc.getNode()->dump(&DAG);
653 WorkListRemover DeadNodes(*this);
654 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes);
655 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1),
657 removeFromWorkList(Load);
658 DAG.DeleteNode(Load);
659 AddToWorkList(Trunc.getNode());
662 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
664 DebugLoc dl = Op.getDebugLoc();
665 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
666 EVT MemVT = LD->getMemoryVT();
667 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
668 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD : ISD::EXTLOAD)
669 : LD->getExtensionType();
671 return DAG.getExtLoad(ExtType, dl, PVT,
672 LD->getChain(), LD->getBasePtr(),
673 LD->getSrcValue(), LD->getSrcValueOffset(),
674 MemVT, LD->isVolatile(),
675 LD->isNonTemporal(), LD->getAlignment());
678 unsigned Opc = Op.getOpcode();
681 case ISD::AssertSext:
682 return DAG.getNode(ISD::AssertSext, dl, PVT,
683 SExtPromoteOperand(Op.getOperand(0), PVT),
685 case ISD::AssertZext:
686 return DAG.getNode(ISD::AssertZext, dl, PVT,
687 ZExtPromoteOperand(Op.getOperand(0), PVT),
689 case ISD::Constant: {
691 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
692 return DAG.getNode(ExtOpc, dl, PVT, Op);
696 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
698 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
701 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
702 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
704 EVT OldVT = Op.getValueType();
705 DebugLoc dl = Op.getDebugLoc();
706 bool Replace = false;
707 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
708 if (NewOp.getNode() == 0)
710 AddToWorkList(NewOp.getNode());
713 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
714 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
715 DAG.getValueType(OldVT));
718 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
719 EVT OldVT = Op.getValueType();
720 DebugLoc dl = Op.getDebugLoc();
721 bool Replace = false;
722 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
723 if (NewOp.getNode() == 0)
725 AddToWorkList(NewOp.getNode());
728 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
729 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
732 /// PromoteIntBinOp - Promote the specified integer binary operation if the
733 /// target indicates it is beneficial. e.g. On x86, it's usually better to
734 /// promote i16 operations to i32 since i16 instructions are longer.
735 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
736 if (!LegalOperations)
739 EVT VT = Op.getValueType();
740 if (VT.isVector() || !VT.isInteger())
743 // If operation type is 'undesirable', e.g. i16 on x86, consider
745 unsigned Opc = Op.getOpcode();
746 if (TLI.isTypeDesirableForOp(Opc, VT))
750 // Consult target whether it is a good idea to promote this operation and
751 // what's the right type to promote it to.
752 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
753 assert(PVT != VT && "Don't know what type to promote to!");
755 bool Replace0 = false;
756 SDValue N0 = Op.getOperand(0);
757 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
758 if (NN0.getNode() == 0)
761 bool Replace1 = false;
762 SDValue N1 = Op.getOperand(1);
767 NN1 = PromoteOperand(N1, PVT, Replace1);
768 if (NN1.getNode() == 0)
772 AddToWorkList(NN0.getNode());
774 AddToWorkList(NN1.getNode());
777 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
779 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
781 DEBUG(dbgs() << "\nPromoting ";
782 Op.getNode()->dump(&DAG));
783 DebugLoc dl = Op.getDebugLoc();
784 return DAG.getNode(ISD::TRUNCATE, dl, VT,
785 DAG.getNode(Opc, dl, PVT, NN0, NN1));
790 /// PromoteIntShiftOp - Promote the specified integer shift operation if the
791 /// target indicates it is beneficial. e.g. On x86, it's usually better to
792 /// promote i16 operations to i32 since i16 instructions are longer.
793 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
794 if (!LegalOperations)
797 EVT VT = Op.getValueType();
798 if (VT.isVector() || !VT.isInteger())
801 // If operation type is 'undesirable', e.g. i16 on x86, consider
803 unsigned Opc = Op.getOpcode();
804 if (TLI.isTypeDesirableForOp(Opc, VT))
808 // Consult target whether it is a good idea to promote this operation and
809 // what's the right type to promote it to.
810 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
811 assert(PVT != VT && "Don't know what type to promote to!");
813 bool Replace = false;
814 SDValue N0 = Op.getOperand(0);
816 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
817 else if (Opc == ISD::SRL)
818 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
820 N0 = PromoteOperand(N0, PVT, Replace);
821 if (N0.getNode() == 0)
824 AddToWorkList(N0.getNode());
826 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
828 DEBUG(dbgs() << "\nPromoting ";
829 Op.getNode()->dump(&DAG));
830 DebugLoc dl = Op.getDebugLoc();
831 return DAG.getNode(ISD::TRUNCATE, dl, VT,
832 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
837 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
838 if (!LegalOperations)
841 EVT VT = Op.getValueType();
842 if (VT.isVector() || !VT.isInteger())
845 // If operation type is 'undesirable', e.g. i16 on x86, consider
847 unsigned Opc = Op.getOpcode();
848 if (TLI.isTypeDesirableForOp(Opc, VT))
852 // Consult target whether it is a good idea to promote this operation and
853 // what's the right type to promote it to.
854 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
855 assert(PVT != VT && "Don't know what type to promote to!");
856 // fold (aext (aext x)) -> (aext x)
857 // fold (aext (zext x)) -> (zext x)
858 // fold (aext (sext x)) -> (sext x)
859 DEBUG(dbgs() << "\nPromoting ";
860 Op.getNode()->dump(&DAG));
861 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0));
866 bool DAGCombiner::PromoteLoad(SDValue Op) {
867 if (!LegalOperations)
870 EVT VT = Op.getValueType();
871 if (VT.isVector() || !VT.isInteger())
874 // If operation type is 'undesirable', e.g. i16 on x86, consider
876 unsigned Opc = Op.getOpcode();
877 if (TLI.isTypeDesirableForOp(Opc, VT))
881 // Consult target whether it is a good idea to promote this operation and
882 // what's the right type to promote it to.
883 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
884 assert(PVT != VT && "Don't know what type to promote to!");
886 DebugLoc dl = Op.getDebugLoc();
887 SDNode *N = Op.getNode();
888 LoadSDNode *LD = cast<LoadSDNode>(N);
889 EVT MemVT = LD->getMemoryVT();
890 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
891 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD : ISD::EXTLOAD)
892 : LD->getExtensionType();
893 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
894 LD->getChain(), LD->getBasePtr(),
895 LD->getSrcValue(), LD->getSrcValueOffset(),
896 MemVT, LD->isVolatile(),
897 LD->isNonTemporal(), LD->getAlignment());
898 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
900 DEBUG(dbgs() << "\nPromoting ";
903 Result.getNode()->dump(&DAG);
905 WorkListRemover DeadNodes(*this);
906 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes);
907 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes);
908 removeFromWorkList(N);
910 AddToWorkList(Result.getNode());
917 //===----------------------------------------------------------------------===//
918 // Main DAG Combiner implementation
919 //===----------------------------------------------------------------------===//
921 void DAGCombiner::Run(CombineLevel AtLevel) {
922 // set the instance variables, so that the various visit routines may use it.
924 LegalOperations = Level >= NoIllegalOperations;
925 LegalTypes = Level >= NoIllegalTypes;
927 // Add all the dag nodes to the worklist.
928 WorkList.reserve(DAG.allnodes_size());
929 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
930 E = DAG.allnodes_end(); I != E; ++I)
931 WorkList.push_back(I);
933 // Create a dummy node (which is not added to allnodes), that adds a reference
934 // to the root node, preventing it from being deleted, and tracking any
935 // changes of the root.
936 HandleSDNode Dummy(DAG.getRoot());
938 // The root of the dag may dangle to deleted nodes until the dag combiner is
939 // done. Set it to null to avoid confusion.
940 DAG.setRoot(SDValue());
942 // while the worklist isn't empty, inspect the node on the end of it and
943 // try and combine it.
944 while (!WorkList.empty()) {
945 SDNode *N = WorkList.back();
948 // If N has no uses, it is dead. Make sure to revisit all N's operands once
949 // N is deleted from the DAG, since they too may now be dead or may have a
950 // reduced number of uses, allowing other xforms.
951 if (N->use_empty() && N != &Dummy) {
952 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
953 AddToWorkList(N->getOperand(i).getNode());
959 SDValue RV = combine(N);
961 if (RV.getNode() == 0)
966 // If we get back the same node we passed in, rather than a new node or
967 // zero, we know that the node must have defined multiple values and
968 // CombineTo was used. Since CombineTo takes care of the worklist
969 // mechanics for us, we have no work to do in this case.
970 if (RV.getNode() == N)
973 assert(N->getOpcode() != ISD::DELETED_NODE &&
974 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
975 "Node was deleted but visit returned new node!");
977 DEBUG(dbgs() << "\nReplacing.3 ";
979 dbgs() << "\nWith: ";
980 RV.getNode()->dump(&DAG);
982 WorkListRemover DeadNodes(*this);
983 if (N->getNumValues() == RV.getNode()->getNumValues())
984 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
986 assert(N->getValueType(0) == RV.getValueType() &&
987 N->getNumValues() == 1 && "Type mismatch");
989 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
992 // Push the new node and any users onto the worklist
993 AddToWorkList(RV.getNode());
994 AddUsersToWorkList(RV.getNode());
996 // Add any uses of the old node to the worklist in case this node is the
997 // last one that uses them. They may become dead after this node is
999 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1000 AddToWorkList(N->getOperand(i).getNode());
1002 // Finally, if the node is now dead, remove it from the graph. The node
1003 // may not be dead if the replacement process recursively simplified to
1004 // something else needing this node.
1005 if (N->use_empty()) {
1006 // Nodes can be reintroduced into the worklist. Make sure we do not
1007 // process a node that has been replaced.
1008 removeFromWorkList(N);
1010 // Finally, since the node is now dead, remove it from the graph.
1015 // If the root changed (e.g. it was a dead load, update the root).
1016 DAG.setRoot(Dummy.getValue());
1019 SDValue DAGCombiner::visit(SDNode *N) {
1020 switch (N->getOpcode()) {
1022 case ISD::TokenFactor: return visitTokenFactor(N);
1023 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1024 case ISD::ADD: return visitADD(N);
1025 case ISD::SUB: return visitSUB(N);
1026 case ISD::ADDC: return visitADDC(N);
1027 case ISD::ADDE: return visitADDE(N);
1028 case ISD::MUL: return visitMUL(N);
1029 case ISD::SDIV: return visitSDIV(N);
1030 case ISD::UDIV: return visitUDIV(N);
1031 case ISD::SREM: return visitSREM(N);
1032 case ISD::UREM: return visitUREM(N);
1033 case ISD::MULHU: return visitMULHU(N);
1034 case ISD::MULHS: return visitMULHS(N);
1035 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1036 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1037 case ISD::SDIVREM: return visitSDIVREM(N);
1038 case ISD::UDIVREM: return visitUDIVREM(N);
1039 case ISD::AND: return visitAND(N);
1040 case ISD::OR: return visitOR(N);
1041 case ISD::XOR: return visitXOR(N);
1042 case ISD::SHL: return visitSHL(N);
1043 case ISD::SRA: return visitSRA(N);
1044 case ISD::SRL: return visitSRL(N);
1045 case ISD::CTLZ: return visitCTLZ(N);
1046 case ISD::CTTZ: return visitCTTZ(N);
1047 case ISD::CTPOP: return visitCTPOP(N);
1048 case ISD::SELECT: return visitSELECT(N);
1049 case ISD::SELECT_CC: return visitSELECT_CC(N);
1050 case ISD::SETCC: return visitSETCC(N);
1051 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1052 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1053 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1054 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1055 case ISD::TRUNCATE: return visitTRUNCATE(N);
1056 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
1057 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1058 case ISD::FADD: return visitFADD(N);
1059 case ISD::FSUB: return visitFSUB(N);
1060 case ISD::FMUL: return visitFMUL(N);
1061 case ISD::FDIV: return visitFDIV(N);
1062 case ISD::FREM: return visitFREM(N);
1063 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1064 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1065 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1066 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1067 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1068 case ISD::FP_ROUND: return visitFP_ROUND(N);
1069 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1070 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1071 case ISD::FNEG: return visitFNEG(N);
1072 case ISD::FABS: return visitFABS(N);
1073 case ISD::BRCOND: return visitBRCOND(N);
1074 case ISD::BR_CC: return visitBR_CC(N);
1075 case ISD::LOAD: return visitLOAD(N);
1076 case ISD::STORE: return visitSTORE(N);
1077 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1078 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1079 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1080 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1081 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1086 SDValue DAGCombiner::combine(SDNode *N) {
1087 SDValue RV = visit(N);
1089 // If nothing happened, try a target-specific DAG combine.
1090 if (RV.getNode() == 0) {
1091 assert(N->getOpcode() != ISD::DELETED_NODE &&
1092 "Node was deleted but visit returned NULL!");
1094 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1095 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1097 // Expose the DAG combiner to the target combiner impls.
1098 TargetLowering::DAGCombinerInfo
1099 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
1101 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1105 // If nothing happened still, try promoting the operation.
1106 if (RV.getNode() == 0) {
1107 switch (N->getOpcode()) {
1115 RV = PromoteIntBinOp(SDValue(N, 0));
1120 RV = PromoteIntShiftOp(SDValue(N, 0));
1122 case ISD::SIGN_EXTEND:
1123 case ISD::ZERO_EXTEND:
1124 case ISD::ANY_EXTEND:
1125 RV = PromoteExtend(SDValue(N, 0));
1128 if (PromoteLoad(SDValue(N, 0)))
1134 // If N is a commutative binary node, try commuting it to enable more
1136 if (RV.getNode() == 0 &&
1137 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1138 N->getNumValues() == 1) {
1139 SDValue N0 = N->getOperand(0);
1140 SDValue N1 = N->getOperand(1);
1142 // Constant operands are canonicalized to RHS.
1143 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1144 SDValue Ops[] = { N1, N0 };
1145 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1148 return SDValue(CSENode, 0);
1155 /// getInputChainForNode - Given a node, return its input chain if it has one,
1156 /// otherwise return a null sd operand.
1157 static SDValue getInputChainForNode(SDNode *N) {
1158 if (unsigned NumOps = N->getNumOperands()) {
1159 if (N->getOperand(0).getValueType() == MVT::Other)
1160 return N->getOperand(0);
1161 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1162 return N->getOperand(NumOps-1);
1163 for (unsigned i = 1; i < NumOps-1; ++i)
1164 if (N->getOperand(i).getValueType() == MVT::Other)
1165 return N->getOperand(i);
1170 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1171 // If N has two operands, where one has an input chain equal to the other,
1172 // the 'other' chain is redundant.
1173 if (N->getNumOperands() == 2) {
1174 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1175 return N->getOperand(0);
1176 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1177 return N->getOperand(1);
1180 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1181 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1182 SmallPtrSet<SDNode*, 16> SeenOps;
1183 bool Changed = false; // If we should replace this token factor.
1185 // Start out with this token factor.
1188 // Iterate through token factors. The TFs grows when new token factors are
1190 for (unsigned i = 0; i < TFs.size(); ++i) {
1191 SDNode *TF = TFs[i];
1193 // Check each of the operands.
1194 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1195 SDValue Op = TF->getOperand(i);
1197 switch (Op.getOpcode()) {
1198 case ISD::EntryToken:
1199 // Entry tokens don't need to be added to the list. They are
1204 case ISD::TokenFactor:
1205 if (Op.hasOneUse() &&
1206 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1207 // Queue up for processing.
1208 TFs.push_back(Op.getNode());
1209 // Clean up in case the token factor is removed.
1210 AddToWorkList(Op.getNode());
1217 // Only add if it isn't already in the list.
1218 if (SeenOps.insert(Op.getNode()))
1229 // If we've change things around then replace token factor.
1232 // The entry token is the only possible outcome.
1233 Result = DAG.getEntryNode();
1235 // New and improved token factor.
1236 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
1237 MVT::Other, &Ops[0], Ops.size());
1240 // Don't add users to work list.
1241 return CombineTo(N, Result, false);
1247 /// MERGE_VALUES can always be eliminated.
1248 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1249 WorkListRemover DeadNodes(*this);
1250 // Replacing results may cause a different MERGE_VALUES to suddenly
1251 // be CSE'd with N, and carry its uses with it. Iterate until no
1252 // uses remain, to ensure that the node can be safely deleted.
1254 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1255 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
1257 } while (!N->use_empty());
1258 removeFromWorkList(N);
1260 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1264 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
1265 SelectionDAG &DAG) {
1266 EVT VT = N0.getValueType();
1267 SDValue N00 = N0.getOperand(0);
1268 SDValue N01 = N0.getOperand(1);
1269 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1271 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1272 isa<ConstantSDNode>(N00.getOperand(1))) {
1273 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1274 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1275 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1276 N00.getOperand(0), N01),
1277 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1278 N00.getOperand(1), N01));
1279 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1285 SDValue DAGCombiner::visitADD(SDNode *N) {
1286 SDValue N0 = N->getOperand(0);
1287 SDValue N1 = N->getOperand(1);
1288 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1289 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1290 EVT VT = N0.getValueType();
1293 if (VT.isVector()) {
1294 SDValue FoldedVOp = SimplifyVBinOp(N);
1295 if (FoldedVOp.getNode()) return FoldedVOp;
1298 // fold (add x, undef) -> undef
1299 if (N0.getOpcode() == ISD::UNDEF)
1301 if (N1.getOpcode() == ISD::UNDEF)
1303 // fold (add c1, c2) -> c1+c2
1305 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1306 // canonicalize constant to RHS
1308 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1309 // fold (add x, 0) -> x
1310 if (N1C && N1C->isNullValue())
1312 // fold (add Sym, c) -> Sym+c
1313 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1314 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1315 GA->getOpcode() == ISD::GlobalAddress)
1316 return DAG.getGlobalAddress(GA->getGlobal(), VT,
1318 (uint64_t)N1C->getSExtValue());
1319 // fold ((c1-A)+c2) -> (c1+c2)-A
1320 if (N1C && N0.getOpcode() == ISD::SUB)
1321 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1322 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1323 DAG.getConstant(N1C->getAPIntValue()+
1324 N0C->getAPIntValue(), VT),
1327 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1328 if (RADD.getNode() != 0)
1330 // fold ((0-A) + B) -> B-A
1331 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1332 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1333 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1334 // fold (A + (0-B)) -> A-B
1335 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1336 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1337 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1338 // fold (A+(B-A)) -> B
1339 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1340 return N1.getOperand(0);
1341 // fold ((B-A)+A) -> B
1342 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1343 return N0.getOperand(0);
1344 // fold (A+(B-(A+C))) to (B-C)
1345 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1346 N0 == N1.getOperand(1).getOperand(0))
1347 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1348 N1.getOperand(1).getOperand(1));
1349 // fold (A+(B-(C+A))) to (B-C)
1350 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1351 N0 == N1.getOperand(1).getOperand(1))
1352 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1353 N1.getOperand(1).getOperand(0));
1354 // fold (A+((B-A)+or-C)) to (B+or-C)
1355 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1356 N1.getOperand(0).getOpcode() == ISD::SUB &&
1357 N0 == N1.getOperand(0).getOperand(1))
1358 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1359 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1361 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1362 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1363 SDValue N00 = N0.getOperand(0);
1364 SDValue N01 = N0.getOperand(1);
1365 SDValue N10 = N1.getOperand(0);
1366 SDValue N11 = N1.getOperand(1);
1368 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1369 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1370 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1371 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1374 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1375 return SDValue(N, 0);
1377 // fold (a+b) -> (a|b) iff a and b share no bits.
1378 if (VT.isInteger() && !VT.isVector()) {
1379 APInt LHSZero, LHSOne;
1380 APInt RHSZero, RHSOne;
1381 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1382 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1384 if (LHSZero.getBoolValue()) {
1385 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1387 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1388 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1389 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1390 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1391 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1395 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1396 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1397 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1398 if (Result.getNode()) return Result;
1400 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1401 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1402 if (Result.getNode()) return Result;
1405 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1406 if (N1.getOpcode() == ISD::SHL &&
1407 N1.getOperand(0).getOpcode() == ISD::SUB)
1408 if (ConstantSDNode *C =
1409 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1410 if (C->getAPIntValue() == 0)
1411 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1412 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1413 N1.getOperand(0).getOperand(1),
1415 if (N0.getOpcode() == ISD::SHL &&
1416 N0.getOperand(0).getOpcode() == ISD::SUB)
1417 if (ConstantSDNode *C =
1418 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1419 if (C->getAPIntValue() == 0)
1420 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1421 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1422 N0.getOperand(0).getOperand(1),
1428 SDValue DAGCombiner::visitADDC(SDNode *N) {
1429 SDValue N0 = N->getOperand(0);
1430 SDValue N1 = N->getOperand(1);
1431 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1432 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1433 EVT VT = N0.getValueType();
1435 // If the flag result is dead, turn this into an ADD.
1436 if (N->hasNUsesOfValue(0, 1))
1437 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
1438 DAG.getNode(ISD::CARRY_FALSE,
1439 N->getDebugLoc(), MVT::Flag));
1441 // canonicalize constant to RHS.
1443 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1445 // fold (addc x, 0) -> x + no carry out
1446 if (N1C && N1C->isNullValue())
1447 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1448 N->getDebugLoc(), MVT::Flag));
1450 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1451 APInt LHSZero, LHSOne;
1452 APInt RHSZero, RHSOne;
1453 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1454 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1456 if (LHSZero.getBoolValue()) {
1457 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1459 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1460 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1461 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1462 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1463 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1464 DAG.getNode(ISD::CARRY_FALSE,
1465 N->getDebugLoc(), MVT::Flag));
1471 SDValue DAGCombiner::visitADDE(SDNode *N) {
1472 SDValue N0 = N->getOperand(0);
1473 SDValue N1 = N->getOperand(1);
1474 SDValue CarryIn = N->getOperand(2);
1475 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1476 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1478 // canonicalize constant to RHS
1480 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1483 // fold (adde x, y, false) -> (addc x, y)
1484 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1485 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1490 SDValue DAGCombiner::visitSUB(SDNode *N) {
1491 SDValue N0 = N->getOperand(0);
1492 SDValue N1 = N->getOperand(1);
1493 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1494 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1495 EVT VT = N0.getValueType();
1498 if (VT.isVector()) {
1499 SDValue FoldedVOp = SimplifyVBinOp(N);
1500 if (FoldedVOp.getNode()) return FoldedVOp;
1503 // fold (sub x, x) -> 0
1505 return DAG.getConstant(0, N->getValueType(0));
1506 // fold (sub c1, c2) -> c1-c2
1508 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1509 // fold (sub x, c) -> (add x, -c)
1511 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1512 DAG.getConstant(-N1C->getAPIntValue(), VT));
1513 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1514 if (N0C && N0C->isAllOnesValue())
1515 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1516 // fold (A+B)-A -> B
1517 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1518 return N0.getOperand(1);
1519 // fold (A+B)-B -> A
1520 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1521 return N0.getOperand(0);
1522 // fold ((A+(B+or-C))-B) -> A+or-C
1523 if (N0.getOpcode() == ISD::ADD &&
1524 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1525 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1526 N0.getOperand(1).getOperand(0) == N1)
1527 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1528 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1529 // fold ((A+(C+B))-B) -> A+C
1530 if (N0.getOpcode() == ISD::ADD &&
1531 N0.getOperand(1).getOpcode() == ISD::ADD &&
1532 N0.getOperand(1).getOperand(1) == N1)
1533 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1534 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1535 // fold ((A-(B-C))-C) -> A-B
1536 if (N0.getOpcode() == ISD::SUB &&
1537 N0.getOperand(1).getOpcode() == ISD::SUB &&
1538 N0.getOperand(1).getOperand(1) == N1)
1539 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1540 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1542 // If either operand of a sub is undef, the result is undef
1543 if (N0.getOpcode() == ISD::UNDEF)
1545 if (N1.getOpcode() == ISD::UNDEF)
1548 // If the relocation model supports it, consider symbol offsets.
1549 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1550 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1551 // fold (sub Sym, c) -> Sym-c
1552 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1553 return DAG.getGlobalAddress(GA->getGlobal(), VT,
1555 (uint64_t)N1C->getSExtValue());
1556 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1557 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1558 if (GA->getGlobal() == GB->getGlobal())
1559 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1566 SDValue DAGCombiner::visitMUL(SDNode *N) {
1567 SDValue N0 = N->getOperand(0);
1568 SDValue N1 = N->getOperand(1);
1569 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1570 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1571 EVT VT = N0.getValueType();
1574 if (VT.isVector()) {
1575 SDValue FoldedVOp = SimplifyVBinOp(N);
1576 if (FoldedVOp.getNode()) return FoldedVOp;
1579 // fold (mul x, undef) -> 0
1580 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1581 return DAG.getConstant(0, VT);
1582 // fold (mul c1, c2) -> c1*c2
1584 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1585 // canonicalize constant to RHS
1587 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1588 // fold (mul x, 0) -> 0
1589 if (N1C && N1C->isNullValue())
1591 // fold (mul x, -1) -> 0-x
1592 if (N1C && N1C->isAllOnesValue())
1593 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1594 DAG.getConstant(0, VT), N0);
1595 // fold (mul x, (1 << c)) -> x << c
1596 if (N1C && N1C->getAPIntValue().isPowerOf2())
1597 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1598 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1599 getShiftAmountTy()));
1600 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1601 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1602 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1603 // FIXME: If the input is something that is easily negated (e.g. a
1604 // single-use add), we should put the negate there.
1605 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1606 DAG.getConstant(0, VT),
1607 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1608 DAG.getConstant(Log2Val, getShiftAmountTy())));
1610 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1611 if (N1C && N0.getOpcode() == ISD::SHL &&
1612 isa<ConstantSDNode>(N0.getOperand(1))) {
1613 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1614 N1, N0.getOperand(1));
1615 AddToWorkList(C3.getNode());
1616 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1617 N0.getOperand(0), C3);
1620 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1623 SDValue Sh(0,0), Y(0,0);
1624 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1625 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1626 N0.getNode()->hasOneUse()) {
1628 } else if (N1.getOpcode() == ISD::SHL &&
1629 isa<ConstantSDNode>(N1.getOperand(1)) &&
1630 N1.getNode()->hasOneUse()) {
1635 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1636 Sh.getOperand(0), Y);
1637 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1638 Mul, Sh.getOperand(1));
1642 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1643 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1644 isa<ConstantSDNode>(N0.getOperand(1)))
1645 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1646 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1647 N0.getOperand(0), N1),
1648 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1649 N0.getOperand(1), N1));
1652 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1653 if (RMUL.getNode() != 0)
1659 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1660 SDValue N0 = N->getOperand(0);
1661 SDValue N1 = N->getOperand(1);
1662 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1663 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1664 EVT VT = N->getValueType(0);
1667 if (VT.isVector()) {
1668 SDValue FoldedVOp = SimplifyVBinOp(N);
1669 if (FoldedVOp.getNode()) return FoldedVOp;
1672 // fold (sdiv c1, c2) -> c1/c2
1673 if (N0C && N1C && !N1C->isNullValue())
1674 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1675 // fold (sdiv X, 1) -> X
1676 if (N1C && N1C->getSExtValue() == 1LL)
1678 // fold (sdiv X, -1) -> 0-X
1679 if (N1C && N1C->isAllOnesValue())
1680 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1681 DAG.getConstant(0, VT), N0);
1682 // If we know the sign bits of both operands are zero, strength reduce to a
1683 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1684 if (!VT.isVector()) {
1685 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1686 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1689 // fold (sdiv X, pow2) -> simple ops after legalize
1690 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
1691 (isPowerOf2_64(N1C->getSExtValue()) ||
1692 isPowerOf2_64(-N1C->getSExtValue()))) {
1693 // If dividing by powers of two is cheap, then don't perform the following
1695 if (TLI.isPow2DivCheap())
1698 int64_t pow2 = N1C->getSExtValue();
1699 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1700 unsigned lg2 = Log2_64(abs2);
1702 // Splat the sign bit into the register
1703 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1704 DAG.getConstant(VT.getSizeInBits()-1,
1705 getShiftAmountTy()));
1706 AddToWorkList(SGN.getNode());
1708 // Add (N0 < 0) ? abs2 - 1 : 0;
1709 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1710 DAG.getConstant(VT.getSizeInBits() - lg2,
1711 getShiftAmountTy()));
1712 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1713 AddToWorkList(SRL.getNode());
1714 AddToWorkList(ADD.getNode()); // Divide by pow2
1715 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1716 DAG.getConstant(lg2, getShiftAmountTy()));
1718 // If we're dividing by a positive value, we're done. Otherwise, we must
1719 // negate the result.
1723 AddToWorkList(SRA.getNode());
1724 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1725 DAG.getConstant(0, VT), SRA);
1728 // if integer divide is expensive and we satisfy the requirements, emit an
1729 // alternate sequence.
1730 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
1731 !TLI.isIntDivCheap()) {
1732 SDValue Op = BuildSDIV(N);
1733 if (Op.getNode()) return Op;
1737 if (N0.getOpcode() == ISD::UNDEF)
1738 return DAG.getConstant(0, VT);
1739 // X / undef -> undef
1740 if (N1.getOpcode() == ISD::UNDEF)
1746 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1747 SDValue N0 = N->getOperand(0);
1748 SDValue N1 = N->getOperand(1);
1749 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1750 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1751 EVT VT = N->getValueType(0);
1754 if (VT.isVector()) {
1755 SDValue FoldedVOp = SimplifyVBinOp(N);
1756 if (FoldedVOp.getNode()) return FoldedVOp;
1759 // fold (udiv c1, c2) -> c1/c2
1760 if (N0C && N1C && !N1C->isNullValue())
1761 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1762 // fold (udiv x, (1 << c)) -> x >>u c
1763 if (N1C && N1C->getAPIntValue().isPowerOf2())
1764 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1765 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1766 getShiftAmountTy()));
1767 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1768 if (N1.getOpcode() == ISD::SHL) {
1769 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1770 if (SHC->getAPIntValue().isPowerOf2()) {
1771 EVT ADDVT = N1.getOperand(1).getValueType();
1772 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1774 DAG.getConstant(SHC->getAPIntValue()
1777 AddToWorkList(Add.getNode());
1778 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1782 // fold (udiv x, c) -> alternate
1783 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1784 SDValue Op = BuildUDIV(N);
1785 if (Op.getNode()) return Op;
1789 if (N0.getOpcode() == ISD::UNDEF)
1790 return DAG.getConstant(0, VT);
1791 // X / undef -> undef
1792 if (N1.getOpcode() == ISD::UNDEF)
1798 SDValue DAGCombiner::visitSREM(SDNode *N) {
1799 SDValue N0 = N->getOperand(0);
1800 SDValue N1 = N->getOperand(1);
1801 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1802 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1803 EVT VT = N->getValueType(0);
1805 // fold (srem c1, c2) -> c1%c2
1806 if (N0C && N1C && !N1C->isNullValue())
1807 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1808 // If we know the sign bits of both operands are zero, strength reduce to a
1809 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1810 if (!VT.isVector()) {
1811 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1812 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1815 // If X/C can be simplified by the division-by-constant logic, lower
1816 // X%C to the equivalent of X-X/C*C.
1817 if (N1C && !N1C->isNullValue()) {
1818 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1819 AddToWorkList(Div.getNode());
1820 SDValue OptimizedDiv = combine(Div.getNode());
1821 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1822 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1824 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1825 AddToWorkList(Mul.getNode());
1831 if (N0.getOpcode() == ISD::UNDEF)
1832 return DAG.getConstant(0, VT);
1833 // X % undef -> undef
1834 if (N1.getOpcode() == ISD::UNDEF)
1840 SDValue DAGCombiner::visitUREM(SDNode *N) {
1841 SDValue N0 = N->getOperand(0);
1842 SDValue N1 = N->getOperand(1);
1843 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1844 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1845 EVT VT = N->getValueType(0);
1847 // fold (urem c1, c2) -> c1%c2
1848 if (N0C && N1C && !N1C->isNullValue())
1849 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
1850 // fold (urem x, pow2) -> (and x, pow2-1)
1851 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
1852 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
1853 DAG.getConstant(N1C->getAPIntValue()-1,VT));
1854 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1855 if (N1.getOpcode() == ISD::SHL) {
1856 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1857 if (SHC->getAPIntValue().isPowerOf2()) {
1859 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
1860 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
1862 AddToWorkList(Add.getNode());
1863 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
1868 // If X/C can be simplified by the division-by-constant logic, lower
1869 // X%C to the equivalent of X-X/C*C.
1870 if (N1C && !N1C->isNullValue()) {
1871 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
1872 AddToWorkList(Div.getNode());
1873 SDValue OptimizedDiv = combine(Div.getNode());
1874 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1875 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1877 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1878 AddToWorkList(Mul.getNode());
1884 if (N0.getOpcode() == ISD::UNDEF)
1885 return DAG.getConstant(0, VT);
1886 // X % undef -> undef
1887 if (N1.getOpcode() == ISD::UNDEF)
1893 SDValue DAGCombiner::visitMULHS(SDNode *N) {
1894 SDValue N0 = N->getOperand(0);
1895 SDValue N1 = N->getOperand(1);
1896 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1897 EVT VT = N->getValueType(0);
1899 // fold (mulhs x, 0) -> 0
1900 if (N1C && N1C->isNullValue())
1902 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1903 if (N1C && N1C->getAPIntValue() == 1)
1904 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
1905 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
1906 getShiftAmountTy()));
1907 // fold (mulhs x, undef) -> 0
1908 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1909 return DAG.getConstant(0, VT);
1914 SDValue DAGCombiner::visitMULHU(SDNode *N) {
1915 SDValue N0 = N->getOperand(0);
1916 SDValue N1 = N->getOperand(1);
1917 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1918 EVT VT = N->getValueType(0);
1920 // fold (mulhu x, 0) -> 0
1921 if (N1C && N1C->isNullValue())
1923 // fold (mulhu x, 1) -> 0
1924 if (N1C && N1C->getAPIntValue() == 1)
1925 return DAG.getConstant(0, N0.getValueType());
1926 // fold (mulhu x, undef) -> 0
1927 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1928 return DAG.getConstant(0, VT);
1933 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1934 /// compute two values. LoOp and HiOp give the opcodes for the two computations
1935 /// that are being performed. Return true if a simplification was made.
1937 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
1939 // If the high half is not needed, just compute the low half.
1940 bool HiExists = N->hasAnyUseOfValue(1);
1942 (!LegalOperations ||
1943 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1944 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1945 N->op_begin(), N->getNumOperands());
1946 return CombineTo(N, Res, Res);
1949 // If the low half is not needed, just compute the high half.
1950 bool LoExists = N->hasAnyUseOfValue(0);
1952 (!LegalOperations ||
1953 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
1954 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1955 N->op_begin(), N->getNumOperands());
1956 return CombineTo(N, Res, Res);
1959 // If both halves are used, return as it is.
1960 if (LoExists && HiExists)
1963 // If the two computed results can be simplified separately, separate them.
1965 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1966 N->op_begin(), N->getNumOperands());
1967 AddToWorkList(Lo.getNode());
1968 SDValue LoOpt = combine(Lo.getNode());
1969 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
1970 (!LegalOperations ||
1971 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
1972 return CombineTo(N, LoOpt, LoOpt);
1976 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1977 N->op_begin(), N->getNumOperands());
1978 AddToWorkList(Hi.getNode());
1979 SDValue HiOpt = combine(Hi.getNode());
1980 if (HiOpt.getNode() && HiOpt != Hi &&
1981 (!LegalOperations ||
1982 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
1983 return CombineTo(N, HiOpt, HiOpt);
1989 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
1990 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
1991 if (Res.getNode()) return Res;
1996 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
1997 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
1998 if (Res.getNode()) return Res;
2003 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2004 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2005 if (Res.getNode()) return Res;
2010 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2011 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2012 if (Res.getNode()) return Res;
2017 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2018 /// two operands of the same opcode, try to simplify it.
2019 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2020 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2021 EVT VT = N0.getValueType();
2022 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2024 // Bail early if none of these transforms apply.
2025 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2027 // For each of OP in AND/OR/XOR:
2028 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2029 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2030 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2031 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
2033 // do not sink logical op inside of a vector extend, since it may combine
2035 EVT Op0VT = N0.getOperand(0).getValueType();
2036 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2037 N0.getOpcode() == ISD::SIGN_EXTEND ||
2038 // Avoid infinite looping with PromoteIntBinOp.
2039 (N0.getOpcode() == ISD::ANY_EXTEND &&
2040 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2041 (N0.getOpcode() == ISD::TRUNCATE && TLI.isTypeLegal(Op0VT))) &&
2043 Op0VT == N1.getOperand(0).getValueType() &&
2044 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2045 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2046 N0.getOperand(0).getValueType(),
2047 N0.getOperand(0), N1.getOperand(0));
2048 AddToWorkList(ORNode.getNode());
2049 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
2052 // For each of OP in SHL/SRL/SRA/AND...
2053 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2054 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2055 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2056 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2057 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2058 N0.getOperand(1) == N1.getOperand(1)) {
2059 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2060 N0.getOperand(0).getValueType(),
2061 N0.getOperand(0), N1.getOperand(0));
2062 AddToWorkList(ORNode.getNode());
2063 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
2064 ORNode, N0.getOperand(1));
2070 SDValue DAGCombiner::visitAND(SDNode *N) {
2071 SDValue N0 = N->getOperand(0);
2072 SDValue N1 = N->getOperand(1);
2073 SDValue LL, LR, RL, RR, CC0, CC1;
2074 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2075 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2076 EVT VT = N1.getValueType();
2077 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2080 if (VT.isVector()) {
2081 SDValue FoldedVOp = SimplifyVBinOp(N);
2082 if (FoldedVOp.getNode()) return FoldedVOp;
2085 // fold (and x, undef) -> 0
2086 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2087 return DAG.getConstant(0, VT);
2088 // fold (and c1, c2) -> c1&c2
2090 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2091 // canonicalize constant to RHS
2093 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
2094 // fold (and x, -1) -> x
2095 if (N1C && N1C->isAllOnesValue())
2097 // if (and x, c) is known to be zero, return 0
2098 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2099 APInt::getAllOnesValue(BitWidth)))
2100 return DAG.getConstant(0, VT);
2102 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
2103 if (RAND.getNode() != 0)
2105 // fold (and (or x, C), D) -> D if (C & D) == D
2106 if (N1C && N0.getOpcode() == ISD::OR)
2107 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2108 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2110 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2111 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2112 SDValue N0Op0 = N0.getOperand(0);
2113 APInt Mask = ~N1C->getAPIntValue();
2114 Mask.trunc(N0Op0.getValueSizeInBits());
2115 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2116 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
2117 N0.getValueType(), N0Op0);
2119 // Replace uses of the AND with uses of the Zero extend node.
2122 // We actually want to replace all uses of the any_extend with the
2123 // zero_extend, to avoid duplicating things. This will later cause this
2124 // AND to be folded.
2125 CombineTo(N0.getNode(), Zext);
2126 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2129 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2130 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2131 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2132 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2134 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2135 LL.getValueType().isInteger()) {
2136 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2137 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2138 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2139 LR.getValueType(), LL, RL);
2140 AddToWorkList(ORNode.getNode());
2141 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2143 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2144 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2145 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
2146 LR.getValueType(), LL, RL);
2147 AddToWorkList(ANDNode.getNode());
2148 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2150 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2151 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2152 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2153 LR.getValueType(), LL, RL);
2154 AddToWorkList(ORNode.getNode());
2155 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2158 // canonicalize equivalent to ll == rl
2159 if (LL == RR && LR == RL) {
2160 Op1 = ISD::getSetCCSwappedOperands(Op1);
2163 if (LL == RL && LR == RR) {
2164 bool isInteger = LL.getValueType().isInteger();
2165 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2166 if (Result != ISD::SETCC_INVALID &&
2167 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2168 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2173 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2174 if (N0.getOpcode() == N1.getOpcode()) {
2175 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2176 if (Tmp.getNode()) return Tmp;
2179 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2180 // fold (and (sra)) -> (and (srl)) when possible.
2181 if (!VT.isVector() &&
2182 SimplifyDemandedBits(SDValue(N, 0)))
2183 return SDValue(N, 0);
2185 // fold (zext_inreg (extload x)) -> (zextload x)
2186 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2187 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2188 EVT MemVT = LN0->getMemoryVT();
2189 // If we zero all the possible extended bits, then we can turn this into
2190 // a zextload if we are running before legalize or the operation is legal.
2191 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2192 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2193 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2194 ((!LegalOperations && !LN0->isVolatile()) ||
2195 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2196 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2197 LN0->getChain(), LN0->getBasePtr(),
2199 LN0->getSrcValueOffset(), MemVT,
2200 LN0->isVolatile(), LN0->isNonTemporal(),
2201 LN0->getAlignment());
2203 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2204 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2207 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2208 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2210 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2211 EVT MemVT = LN0->getMemoryVT();
2212 // If we zero all the possible extended bits, then we can turn this into
2213 // a zextload if we are running before legalize or the operation is legal.
2214 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2215 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2216 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2217 ((!LegalOperations && !LN0->isVolatile()) ||
2218 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2219 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2221 LN0->getBasePtr(), LN0->getSrcValue(),
2222 LN0->getSrcValueOffset(), MemVT,
2223 LN0->isVolatile(), LN0->isNonTemporal(),
2224 LN0->getAlignment());
2226 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2227 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2231 // fold (and (load x), 255) -> (zextload x, i8)
2232 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2233 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2234 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2235 (N0.getOpcode() == ISD::ANY_EXTEND &&
2236 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2237 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2238 LoadSDNode *LN0 = HasAnyExt
2239 ? cast<LoadSDNode>(N0.getOperand(0))
2240 : cast<LoadSDNode>(N0);
2241 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2242 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2243 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2244 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2245 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2246 EVT LoadedVT = LN0->getMemoryVT();
2248 if (ExtVT == LoadedVT &&
2249 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2250 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2253 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2254 LN0->getChain(), LN0->getBasePtr(),
2255 LN0->getSrcValue(), LN0->getSrcValueOffset(),
2256 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2257 LN0->getAlignment());
2259 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2260 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2263 // Do not change the width of a volatile load.
2264 // Do not generate loads of non-round integer types since these can
2265 // be expensive (and would be wrong if the type is not byte sized).
2266 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2267 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2268 EVT PtrType = LN0->getOperand(1).getValueType();
2270 unsigned Alignment = LN0->getAlignment();
2271 SDValue NewPtr = LN0->getBasePtr();
2273 // For big endian targets, we need to add an offset to the pointer
2274 // to load the correct bytes. For little endian systems, we merely
2275 // need to read fewer bytes from the same pointer.
2276 if (TLI.isBigEndian()) {
2277 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2278 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2279 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2280 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2281 NewPtr, DAG.getConstant(PtrOff, PtrType));
2282 Alignment = MinAlign(Alignment, PtrOff);
2285 AddToWorkList(NewPtr.getNode());
2287 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2289 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2290 LN0->getChain(), NewPtr,
2291 LN0->getSrcValue(), LN0->getSrcValueOffset(),
2292 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2295 CombineTo(LN0, Load, Load.getValue(1));
2296 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2305 SDValue DAGCombiner::visitOR(SDNode *N) {
2306 SDValue N0 = N->getOperand(0);
2307 SDValue N1 = N->getOperand(1);
2308 SDValue LL, LR, RL, RR, CC0, CC1;
2309 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2310 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2311 EVT VT = N1.getValueType();
2314 if (VT.isVector()) {
2315 SDValue FoldedVOp = SimplifyVBinOp(N);
2316 if (FoldedVOp.getNode()) return FoldedVOp;
2319 // fold (or x, undef) -> -1
2320 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) {
2321 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
2322 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
2324 // fold (or c1, c2) -> c1|c2
2326 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
2327 // canonicalize constant to RHS
2329 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
2330 // fold (or x, 0) -> x
2331 if (N1C && N1C->isNullValue())
2333 // fold (or x, -1) -> -1
2334 if (N1C && N1C->isAllOnesValue())
2336 // fold (or x, c) -> c iff (x & ~c) == 0
2337 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
2340 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
2341 if (ROR.getNode() != 0)
2343 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
2344 // iff (c1 & c2) == 0.
2345 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
2346 isa<ConstantSDNode>(N0.getOperand(1))) {
2347 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
2348 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
2349 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
2350 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2351 N0.getOperand(0), N1),
2352 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
2354 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
2355 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2356 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2357 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2359 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2360 LL.getValueType().isInteger()) {
2361 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
2362 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
2363 if (cast<ConstantSDNode>(LR)->isNullValue() &&
2364 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
2365 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
2366 LR.getValueType(), LL, RL);
2367 AddToWorkList(ORNode.getNode());
2368 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2370 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
2371 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
2372 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2373 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
2374 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
2375 LR.getValueType(), LL, RL);
2376 AddToWorkList(ANDNode.getNode());
2377 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2380 // canonicalize equivalent to ll == rl
2381 if (LL == RR && LR == RL) {
2382 Op1 = ISD::getSetCCSwappedOperands(Op1);
2385 if (LL == RL && LR == RR) {
2386 bool isInteger = LL.getValueType().isInteger();
2387 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
2388 if (Result != ISD::SETCC_INVALID &&
2389 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2390 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2395 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
2396 if (N0.getOpcode() == N1.getOpcode()) {
2397 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2398 if (Tmp.getNode()) return Tmp;
2401 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
2402 if (N0.getOpcode() == ISD::AND &&
2403 N1.getOpcode() == ISD::AND &&
2404 N0.getOperand(1).getOpcode() == ISD::Constant &&
2405 N1.getOperand(1).getOpcode() == ISD::Constant &&
2406 // Don't increase # computations.
2407 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
2408 // We can only do this xform if we know that bits from X that are set in C2
2409 // but not in C1 are already zero. Likewise for Y.
2410 const APInt &LHSMask =
2411 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2412 const APInt &RHSMask =
2413 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
2415 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
2416 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
2417 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2418 N0.getOperand(0), N1.getOperand(0));
2419 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
2420 DAG.getConstant(LHSMask | RHSMask, VT));
2424 // See if this is some rotate idiom.
2425 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
2426 return SDValue(Rot, 0);
2431 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
2432 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
2433 if (Op.getOpcode() == ISD::AND) {
2434 if (isa<ConstantSDNode>(Op.getOperand(1))) {
2435 Mask = Op.getOperand(1);
2436 Op = Op.getOperand(0);
2442 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
2450 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
2451 // idioms for rotate, and if the target supports rotation instructions, generate
2453 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
2454 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
2455 EVT VT = LHS.getValueType();
2456 if (!TLI.isTypeLegal(VT)) return 0;
2458 // The target must have at least one rotate flavor.
2459 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
2460 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
2461 if (!HasROTL && !HasROTR) return 0;
2463 // Match "(X shl/srl V1) & V2" where V2 may not be present.
2464 SDValue LHSShift; // The shift.
2465 SDValue LHSMask; // AND value if any.
2466 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
2467 return 0; // Not part of a rotate.
2469 SDValue RHSShift; // The shift.
2470 SDValue RHSMask; // AND value if any.
2471 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
2472 return 0; // Not part of a rotate.
2474 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
2475 return 0; // Not shifting the same value.
2477 if (LHSShift.getOpcode() == RHSShift.getOpcode())
2478 return 0; // Shifts must disagree.
2480 // Canonicalize shl to left side in a shl/srl pair.
2481 if (RHSShift.getOpcode() == ISD::SHL) {
2482 std::swap(LHS, RHS);
2483 std::swap(LHSShift, RHSShift);
2484 std::swap(LHSMask , RHSMask );
2487 unsigned OpSizeInBits = VT.getSizeInBits();
2488 SDValue LHSShiftArg = LHSShift.getOperand(0);
2489 SDValue LHSShiftAmt = LHSShift.getOperand(1);
2490 SDValue RHSShiftAmt = RHSShift.getOperand(1);
2492 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
2493 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
2494 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
2495 RHSShiftAmt.getOpcode() == ISD::Constant) {
2496 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
2497 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
2498 if ((LShVal + RShVal) != OpSizeInBits)
2503 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
2505 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
2507 // If there is an AND of either shifted operand, apply it to the result.
2508 if (LHSMask.getNode() || RHSMask.getNode()) {
2509 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
2511 if (LHSMask.getNode()) {
2512 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
2513 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
2515 if (RHSMask.getNode()) {
2516 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
2517 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
2520 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
2523 return Rot.getNode();
2526 // If there is a mask here, and we have a variable shift, we can't be sure
2527 // that we're masking out the right stuff.
2528 if (LHSMask.getNode() || RHSMask.getNode())
2531 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
2532 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
2533 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
2534 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
2535 if (ConstantSDNode *SUBC =
2536 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
2537 if (SUBC->getAPIntValue() == OpSizeInBits) {
2539 return DAG.getNode(ISD::ROTL, DL, VT,
2540 LHSShiftArg, LHSShiftAmt).getNode();
2542 return DAG.getNode(ISD::ROTR, DL, VT,
2543 LHSShiftArg, RHSShiftAmt).getNode();
2548 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2549 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
2550 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
2551 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
2552 if (ConstantSDNode *SUBC =
2553 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
2554 if (SUBC->getAPIntValue() == OpSizeInBits) {
2556 return DAG.getNode(ISD::ROTR, DL, VT,
2557 LHSShiftArg, RHSShiftAmt).getNode();
2559 return DAG.getNode(ISD::ROTL, DL, VT,
2560 LHSShiftArg, LHSShiftAmt).getNode();
2565 // Look for sign/zext/any-extended or truncate cases:
2566 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2567 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2568 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2569 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
2570 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2571 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2572 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2573 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
2574 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
2575 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
2576 if (RExtOp0.getOpcode() == ISD::SUB &&
2577 RExtOp0.getOperand(1) == LExtOp0) {
2578 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2580 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2581 // (rotr x, (sub 32, y))
2582 if (ConstantSDNode *SUBC =
2583 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
2584 if (SUBC->getAPIntValue() == OpSizeInBits) {
2585 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
2587 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
2590 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2591 RExtOp0 == LExtOp0.getOperand(1)) {
2592 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2594 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2595 // (rotl x, (sub 32, y))
2596 if (ConstantSDNode *SUBC =
2597 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2598 if (SUBC->getAPIntValue() == OpSizeInBits) {
2599 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
2601 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
2610 SDValue DAGCombiner::visitXOR(SDNode *N) {
2611 SDValue N0 = N->getOperand(0);
2612 SDValue N1 = N->getOperand(1);
2613 SDValue LHS, RHS, CC;
2614 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2615 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2616 EVT VT = N0.getValueType();
2619 if (VT.isVector()) {
2620 SDValue FoldedVOp = SimplifyVBinOp(N);
2621 if (FoldedVOp.getNode()) return FoldedVOp;
2624 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
2625 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
2626 return DAG.getConstant(0, VT);
2627 // fold (xor x, undef) -> undef
2628 if (N0.getOpcode() == ISD::UNDEF)
2630 if (N1.getOpcode() == ISD::UNDEF)
2632 // fold (xor c1, c2) -> c1^c2
2634 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
2635 // canonicalize constant to RHS
2637 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
2638 // fold (xor x, 0) -> x
2639 if (N1C && N1C->isNullValue())
2642 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
2643 if (RXOR.getNode() != 0)
2646 // fold !(x cc y) -> (x !cc y)
2647 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2648 bool isInt = LHS.getValueType().isInteger();
2649 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2652 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
2653 switch (N0.getOpcode()) {
2655 llvm_unreachable("Unhandled SetCC Equivalent!");
2657 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
2658 case ISD::SELECT_CC:
2659 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
2660 N0.getOperand(3), NotCC);
2665 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2666 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2667 N0.getNode()->hasOneUse() &&
2668 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2669 SDValue V = N0.getOperand(0);
2670 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
2671 DAG.getConstant(1, V.getValueType()));
2672 AddToWorkList(V.getNode());
2673 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
2676 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
2677 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
2678 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2679 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2680 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2681 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2682 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2683 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2684 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2685 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2688 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
2689 if (N1C && N1C->isAllOnesValue() &&
2690 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2691 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2692 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2693 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2694 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2695 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2696 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2697 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2700 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
2701 if (N1C && N0.getOpcode() == ISD::XOR) {
2702 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2703 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2705 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
2706 DAG.getConstant(N1C->getAPIntValue() ^
2707 N00C->getAPIntValue(), VT));
2709 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
2710 DAG.getConstant(N1C->getAPIntValue() ^
2711 N01C->getAPIntValue(), VT));
2713 // fold (xor x, x) -> 0
2715 if (!VT.isVector()) {
2716 return DAG.getConstant(0, VT);
2717 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){
2718 // Produce a vector of zeros.
2719 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
2720 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
2721 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
2722 &Ops[0], Ops.size());
2726 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2727 if (N0.getOpcode() == N1.getOpcode()) {
2728 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2729 if (Tmp.getNode()) return Tmp;
2732 // Simplify the expression using non-local knowledge.
2733 if (!VT.isVector() &&
2734 SimplifyDemandedBits(SDValue(N, 0)))
2735 return SDValue(N, 0);
2740 /// visitShiftByConstant - Handle transforms common to the three shifts, when
2741 /// the shift amount is a constant.
2742 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
2743 SDNode *LHS = N->getOperand(0).getNode();
2744 if (!LHS->hasOneUse()) return SDValue();
2746 // We want to pull some binops through shifts, so that we have (and (shift))
2747 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
2748 // thing happens with address calculations, so it's important to canonicalize
2750 bool HighBitSet = false; // Can we transform this if the high bit is set?
2752 switch (LHS->getOpcode()) {
2753 default: return SDValue();
2756 HighBitSet = false; // We can only transform sra if the high bit is clear.
2759 HighBitSet = true; // We can only transform sra if the high bit is set.
2762 if (N->getOpcode() != ISD::SHL)
2763 return SDValue(); // only shl(add) not sr[al](add).
2764 HighBitSet = false; // We can only transform sra if the high bit is clear.
2768 // We require the RHS of the binop to be a constant as well.
2769 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
2770 if (!BinOpCst) return SDValue();
2772 // FIXME: disable this unless the input to the binop is a shift by a constant.
2773 // If it is not a shift, it pessimizes some common cases like:
2775 // void foo(int *X, int i) { X[i & 1235] = 1; }
2776 // int bar(int *X, int i) { return X[i & 255]; }
2777 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
2778 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
2779 BinOpLHSVal->getOpcode() != ISD::SRA &&
2780 BinOpLHSVal->getOpcode() != ISD::SRL) ||
2781 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
2784 EVT VT = N->getValueType(0);
2786 // If this is a signed shift right, and the high bit is modified by the
2787 // logical operation, do not perform the transformation. The highBitSet
2788 // boolean indicates the value of the high bit of the constant which would
2789 // cause it to be modified for this operation.
2790 if (N->getOpcode() == ISD::SRA) {
2791 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
2792 if (BinOpRHSSignSet != HighBitSet)
2796 // Fold the constants, shifting the binop RHS by the shift amount.
2797 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
2799 LHS->getOperand(1), N->getOperand(1));
2801 // Create the new shift.
2802 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(),
2803 VT, LHS->getOperand(0), N->getOperand(1));
2805 // Create the new binop.
2806 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
2809 SDValue DAGCombiner::visitSHL(SDNode *N) {
2810 SDValue N0 = N->getOperand(0);
2811 SDValue N1 = N->getOperand(1);
2812 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2813 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2814 EVT VT = N0.getValueType();
2815 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
2817 // fold (shl c1, c2) -> c1<<c2
2819 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
2820 // fold (shl 0, x) -> 0
2821 if (N0C && N0C->isNullValue())
2823 // fold (shl x, c >= size(x)) -> undef
2824 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2825 return DAG.getUNDEF(VT);
2826 // fold (shl x, 0) -> x
2827 if (N1C && N1C->isNullValue())
2829 // if (shl x, c) is known to be zero, return 0
2830 if (DAG.MaskedValueIsZero(SDValue(N, 0),
2831 APInt::getAllOnesValue(OpSizeInBits)))
2832 return DAG.getConstant(0, VT);
2833 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
2834 if (N1.getOpcode() == ISD::TRUNCATE &&
2835 N1.getOperand(0).getOpcode() == ISD::AND &&
2836 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2837 SDValue N101 = N1.getOperand(0).getOperand(1);
2838 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2839 EVT TruncVT = N1.getValueType();
2840 SDValue N100 = N1.getOperand(0).getOperand(0);
2841 APInt TruncC = N101C->getAPIntValue();
2842 TruncC.trunc(TruncVT.getSizeInBits());
2843 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
2844 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
2845 DAG.getNode(ISD::TRUNCATE,
2848 DAG.getConstant(TruncC, TruncVT)));
2852 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2853 return SDValue(N, 0);
2855 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
2856 if (N1C && N0.getOpcode() == ISD::SHL &&
2857 N0.getOperand(1).getOpcode() == ISD::Constant) {
2858 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2859 uint64_t c2 = N1C->getZExtValue();
2860 if (c1 + c2 > OpSizeInBits)
2861 return DAG.getConstant(0, VT);
2862 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
2863 DAG.getConstant(c1 + c2, N1.getValueType()));
2865 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or
2866 // (srl (and x, (shl -1, c1)), (sub c1, c2))
2867 if (N1C && N0.getOpcode() == ISD::SRL &&
2868 N0.getOperand(1).getOpcode() == ISD::Constant) {
2869 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2870 if (c1 < VT.getSizeInBits()) {
2871 uint64_t c2 = N1C->getZExtValue();
2872 SDValue HiBitsMask =
2873 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
2874 VT.getSizeInBits() - c1),
2876 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT,
2880 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask,
2881 DAG.getConstant(c2-c1, N1.getValueType()));
2883 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask,
2884 DAG.getConstant(c1-c2, N1.getValueType()));
2887 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
2888 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
2889 SDValue HiBitsMask =
2890 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
2891 VT.getSizeInBits() -
2892 N1C->getZExtValue()),
2894 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
2899 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
2900 if (NewSHL.getNode())
2907 SDValue DAGCombiner::visitSRA(SDNode *N) {
2908 SDValue N0 = N->getOperand(0);
2909 SDValue N1 = N->getOperand(1);
2910 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2911 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2912 EVT VT = N0.getValueType();
2913 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
2915 // fold (sra c1, c2) -> (sra c1, c2)
2917 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
2918 // fold (sra 0, x) -> 0
2919 if (N0C && N0C->isNullValue())
2921 // fold (sra -1, x) -> -1
2922 if (N0C && N0C->isAllOnesValue())
2924 // fold (sra x, (setge c, size(x))) -> undef
2925 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2926 return DAG.getUNDEF(VT);
2927 // fold (sra x, 0) -> x
2928 if (N1C && N1C->isNullValue())
2930 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2932 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2933 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
2934 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
2936 ExtVT = EVT::getVectorVT(*DAG.getContext(),
2937 ExtVT, VT.getVectorNumElements());
2938 if ((!LegalOperations ||
2939 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
2940 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
2941 N0.getOperand(0), DAG.getValueType(ExtVT));
2944 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
2945 if (N1C && N0.getOpcode() == ISD::SRA) {
2946 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2947 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
2948 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
2949 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
2950 DAG.getConstant(Sum, N1C->getValueType(0)));
2954 // fold (sra (shl X, m), (sub result_size, n))
2955 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
2956 // result_size - n != m.
2957 // If truncate is free for the target sext(shl) is likely to result in better
2959 if (N0.getOpcode() == ISD::SHL) {
2960 // Get the two constanst of the shifts, CN0 = m, CN = n.
2961 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2963 // Determine what the truncate's result bitsize and type would be.
2965 EVT::getIntegerVT(*DAG.getContext(), OpSizeInBits - N1C->getZExtValue());
2966 // Determine the residual right-shift amount.
2967 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
2969 // If the shift is not a no-op (in which case this should be just a sign
2970 // extend already), the truncated to type is legal, sign_extend is legal
2971 // on that type, and the truncate to that type is both legal and free,
2972 // perform the transform.
2973 if ((ShiftAmt > 0) &&
2974 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
2975 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
2976 TLI.isTruncateFree(VT, TruncVT)) {
2978 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy());
2979 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
2980 N0.getOperand(0), Amt);
2981 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
2983 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
2984 N->getValueType(0), Trunc);
2989 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
2990 if (N1.getOpcode() == ISD::TRUNCATE &&
2991 N1.getOperand(0).getOpcode() == ISD::AND &&
2992 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2993 SDValue N101 = N1.getOperand(0).getOperand(1);
2994 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2995 EVT TruncVT = N1.getValueType();
2996 SDValue N100 = N1.getOperand(0).getOperand(0);
2997 APInt TruncC = N101C->getAPIntValue();
2998 TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
2999 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
3000 DAG.getNode(ISD::AND, N->getDebugLoc(),
3002 DAG.getNode(ISD::TRUNCATE,
3005 DAG.getConstant(TruncC, TruncVT)));
3009 // Simplify, based on bits shifted out of the LHS.
3010 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3011 return SDValue(N, 0);
3014 // If the sign bit is known to be zero, switch this to a SRL.
3015 if (DAG.SignBitIsZero(N0))
3016 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3019 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
3020 if (NewSRA.getNode())
3027 SDValue DAGCombiner::visitSRL(SDNode *N) {
3028 SDValue N0 = N->getOperand(0);
3029 SDValue N1 = N->getOperand(1);
3030 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3031 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3032 EVT VT = N0.getValueType();
3033 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3035 // fold (srl c1, c2) -> c1 >>u c2
3037 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3038 // fold (srl 0, x) -> 0
3039 if (N0C && N0C->isNullValue())
3041 // fold (srl x, c >= size(x)) -> undef
3042 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3043 return DAG.getUNDEF(VT);
3044 // fold (srl x, 0) -> x
3045 if (N1C && N1C->isNullValue())
3047 // if (srl x, c) is known to be zero, return 0
3048 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3049 APInt::getAllOnesValue(OpSizeInBits)))
3050 return DAG.getConstant(0, VT);
3052 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3053 if (N1C && N0.getOpcode() == ISD::SRL &&
3054 N0.getOperand(1).getOpcode() == ISD::Constant) {
3055 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3056 uint64_t c2 = N1C->getZExtValue();
3057 if (c1 + c2 > OpSizeInBits)
3058 return DAG.getConstant(0, VT);
3059 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3060 DAG.getConstant(c1 + c2, N1.getValueType()));
3063 // fold (srl (shl x, c), c) -> (and x, cst2)
3064 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3065 N0.getValueSizeInBits() <= 64) {
3066 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3067 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3068 DAG.getConstant(~0ULL >> ShAmt, VT));
3072 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3073 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3074 // Shifting in all undef bits?
3075 EVT SmallVT = N0.getOperand(0).getValueType();
3076 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
3077 return DAG.getUNDEF(VT);
3079 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3080 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3081 N0.getOperand(0), N1);
3082 AddToWorkList(SmallShift.getNode());
3083 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
3087 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
3088 // bit, which is unmodified by sra.
3089 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
3090 if (N0.getOpcode() == ISD::SRA)
3091 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3094 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3095 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3096 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
3097 APInt KnownZero, KnownOne;
3098 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
3099 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
3101 // If any of the input bits are KnownOne, then the input couldn't be all
3102 // zeros, thus the result of the srl will always be zero.
3103 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
3105 // If all of the bits input the to ctlz node are known to be zero, then
3106 // the result of the ctlz is "32" and the result of the shift is one.
3107 APInt UnknownBits = ~KnownZero & Mask;
3108 if (UnknownBits == 0) return DAG.getConstant(1, VT);
3110 // Otherwise, check to see if there is exactly one bit input to the ctlz.
3111 if ((UnknownBits & (UnknownBits - 1)) == 0) {
3112 // Okay, we know that only that the single bit specified by UnknownBits
3113 // could be set on input to the CTLZ node. If this bit is set, the SRL
3114 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3115 // to an SRL/XOR pair, which is likely to simplify more.
3116 unsigned ShAmt = UnknownBits.countTrailingZeros();
3117 SDValue Op = N0.getOperand(0);
3120 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3121 DAG.getConstant(ShAmt, getShiftAmountTy()));
3122 AddToWorkList(Op.getNode());
3125 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3126 Op, DAG.getConstant(1, VT));
3130 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3131 if (N1.getOpcode() == ISD::TRUNCATE &&
3132 N1.getOperand(0).getOpcode() == ISD::AND &&
3133 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3134 SDValue N101 = N1.getOperand(0).getOperand(1);
3135 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3136 EVT TruncVT = N1.getValueType();
3137 SDValue N100 = N1.getOperand(0).getOperand(0);
3138 APInt TruncC = N101C->getAPIntValue();
3139 TruncC.trunc(TruncVT.getSizeInBits());
3140 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3141 DAG.getNode(ISD::AND, N->getDebugLoc(),
3143 DAG.getNode(ISD::TRUNCATE,
3146 DAG.getConstant(TruncC, TruncVT)));
3150 // fold operands of srl based on knowledge that the low bits are not
3152 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3153 return SDValue(N, 0);
3156 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
3157 if (NewSRL.getNode())
3161 // Here is a common situation. We want to optimize:
3164 // %b = and i32 %a, 2
3165 // %c = srl i32 %b, 1
3166 // brcond i32 %c ...
3172 // %c = setcc eq %b, 0
3175 // However when after the source operand of SRL is optimized into AND, the SRL
3176 // itself may not be optimized further. Look for it and add the BRCOND into
3178 if (N->hasOneUse()) {
3179 SDNode *Use = *N->use_begin();
3180 if (Use->getOpcode() == ISD::BRCOND)
3182 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
3183 // Also look pass the truncate.
3184 Use = *Use->use_begin();
3185 if (Use->getOpcode() == ISD::BRCOND)
3193 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
3194 SDValue N0 = N->getOperand(0);
3195 EVT VT = N->getValueType(0);
3197 // fold (ctlz c1) -> c2
3198 if (isa<ConstantSDNode>(N0))
3199 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
3203 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
3204 SDValue N0 = N->getOperand(0);
3205 EVT VT = N->getValueType(0);
3207 // fold (cttz c1) -> c2
3208 if (isa<ConstantSDNode>(N0))
3209 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
3213 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
3214 SDValue N0 = N->getOperand(0);
3215 EVT VT = N->getValueType(0);
3217 // fold (ctpop c1) -> c2
3218 if (isa<ConstantSDNode>(N0))
3219 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
3223 SDValue DAGCombiner::visitSELECT(SDNode *N) {
3224 SDValue N0 = N->getOperand(0);
3225 SDValue N1 = N->getOperand(1);
3226 SDValue N2 = N->getOperand(2);
3227 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3228 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3229 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
3230 EVT VT = N->getValueType(0);
3231 EVT VT0 = N0.getValueType();
3233 // fold (select C, X, X) -> X
3236 // fold (select true, X, Y) -> X
3237 if (N0C && !N0C->isNullValue())
3239 // fold (select false, X, Y) -> Y
3240 if (N0C && N0C->isNullValue())
3242 // fold (select C, 1, X) -> (or C, X)
3243 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
3244 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3245 // fold (select C, 0, 1) -> (xor C, 1)
3246 if (VT.isInteger() &&
3249 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
3250 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
3253 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
3254 N0, DAG.getConstant(1, VT0));
3255 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
3256 N0, DAG.getConstant(1, VT0));
3257 AddToWorkList(XORNode.getNode());
3259 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
3260 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
3262 // fold (select C, 0, X) -> (and (not C), X)
3263 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
3264 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3265 AddToWorkList(NOTNode.getNode());
3266 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
3268 // fold (select C, X, 1) -> (or (not C), X)
3269 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
3270 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3271 AddToWorkList(NOTNode.getNode());
3272 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
3274 // fold (select C, X, 0) -> (and C, X)
3275 if (VT == MVT::i1 && N2C && N2C->isNullValue())
3276 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3277 // fold (select X, X, Y) -> (or X, Y)
3278 // fold (select X, 1, Y) -> (or X, Y)
3279 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
3280 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3281 // fold (select X, Y, X) -> (and X, Y)
3282 // fold (select X, Y, 0) -> (and X, Y)
3283 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
3284 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3286 // If we can fold this based on the true/false value, do so.
3287 if (SimplifySelectOps(N, N1, N2))
3288 return SDValue(N, 0); // Don't revisit N.
3290 // fold selects based on a setcc into other things, such as min/max/abs
3291 if (N0.getOpcode() == ISD::SETCC) {
3293 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
3294 // having to say they don't support SELECT_CC on every type the DAG knows
3295 // about, since there is no way to mark an opcode illegal at all value types
3296 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
3297 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
3298 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
3299 N0.getOperand(0), N0.getOperand(1),
3300 N1, N2, N0.getOperand(2));
3301 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
3307 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
3308 SDValue N0 = N->getOperand(0);
3309 SDValue N1 = N->getOperand(1);
3310 SDValue N2 = N->getOperand(2);
3311 SDValue N3 = N->getOperand(3);
3312 SDValue N4 = N->getOperand(4);
3313 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
3315 // fold select_cc lhs, rhs, x, x, cc -> x
3319 // Determine if the condition we're dealing with is constant
3320 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
3321 N0, N1, CC, N->getDebugLoc(), false);
3322 if (SCC.getNode()) AddToWorkList(SCC.getNode());
3324 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
3325 if (!SCCC->isNullValue())
3326 return N2; // cond always true -> true val
3328 return N3; // cond always false -> false val
3331 // Fold to a simpler select_cc
3332 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
3333 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
3334 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
3337 // If we can fold this based on the true/false value, do so.
3338 if (SimplifySelectOps(N, N2, N3))
3339 return SDValue(N, 0); // Don't revisit N.
3341 // fold select_cc into other things, such as min/max/abs
3342 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
3345 SDValue DAGCombiner::visitSETCC(SDNode *N) {
3346 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
3347 cast<CondCodeSDNode>(N->getOperand(2))->get(),
3351 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
3352 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
3353 // transformation. Returns true if extension are possible and the above
3354 // mentioned transformation is profitable.
3355 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
3357 SmallVector<SDNode*, 4> &ExtendNodes,
3358 const TargetLowering &TLI) {
3359 bool HasCopyToRegUses = false;
3360 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
3361 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
3362 UE = N0.getNode()->use_end();
3367 if (UI.getUse().getResNo() != N0.getResNo())
3369 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
3370 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
3371 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
3372 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
3373 // Sign bits will be lost after a zext.
3376 for (unsigned i = 0; i != 2; ++i) {
3377 SDValue UseOp = User->getOperand(i);
3380 if (!isa<ConstantSDNode>(UseOp))
3385 ExtendNodes.push_back(User);
3388 // If truncates aren't free and there are users we can't
3389 // extend, it isn't worthwhile.
3392 // Remember if this value is live-out.
3393 if (User->getOpcode() == ISD::CopyToReg)
3394 HasCopyToRegUses = true;
3397 if (HasCopyToRegUses) {
3398 bool BothLiveOut = false;
3399 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3401 SDUse &Use = UI.getUse();
3402 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
3408 // Both unextended and extended values are live out. There had better be
3409 // good a reason for the transformation.
3410 return ExtendNodes.size();
3415 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
3416 SDValue N0 = N->getOperand(0);
3417 EVT VT = N->getValueType(0);
3419 // fold (sext c1) -> c1
3420 if (isa<ConstantSDNode>(N0))
3421 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
3423 // fold (sext (sext x)) -> (sext x)
3424 // fold (sext (aext x)) -> (sext x)
3425 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3426 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
3429 if (N0.getOpcode() == ISD::TRUNCATE) {
3430 // fold (sext (truncate (load x))) -> (sext (smaller load x))
3431 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
3432 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3433 if (NarrowLoad.getNode()) {
3434 SDNode* oye = N0.getNode()->getOperand(0).getNode();
3435 if (NarrowLoad.getNode() != N0.getNode()) {
3436 CombineTo(N0.getNode(), NarrowLoad);
3437 // CombineTo deleted the truncate, if needed, but not what's under it.
3440 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3443 // See if the value being truncated is already sign extended. If so, just
3444 // eliminate the trunc/sext pair.
3445 SDValue Op = N0.getOperand(0);
3446 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
3447 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
3448 unsigned DestBits = VT.getScalarType().getSizeInBits();
3449 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
3451 if (OpBits == DestBits) {
3452 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
3453 // bits, it is already ready.
3454 if (NumSignBits > DestBits-MidBits)
3456 } else if (OpBits < DestBits) {
3457 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
3458 // bits, just sext from i32.
3459 if (NumSignBits > OpBits-MidBits)
3460 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
3462 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
3463 // bits, just truncate to i32.
3464 if (NumSignBits > OpBits-MidBits)
3465 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3468 // fold (sext (truncate x)) -> (sextinreg x).
3469 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
3470 N0.getValueType())) {
3471 if (OpBits < DestBits)
3472 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
3473 else if (OpBits > DestBits)
3474 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
3475 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
3476 DAG.getValueType(N0.getValueType()));
3480 // fold (sext (load x)) -> (sext (truncate (sextload x)))
3481 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3482 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3483 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
3484 bool DoXform = true;
3485 SmallVector<SDNode*, 4> SetCCs;
3486 if (!N0.hasOneUse())
3487 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
3489 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3490 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3492 LN0->getBasePtr(), LN0->getSrcValue(),
3493 LN0->getSrcValueOffset(),
3495 LN0->isVolatile(), LN0->isNonTemporal(),
3496 LN0->getAlignment());
3497 CombineTo(N, ExtLoad);
3498 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3499 N0.getValueType(), ExtLoad);
3500 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3502 // Extend SetCC uses if necessary.
3503 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3504 SDNode *SetCC = SetCCs[i];
3505 SmallVector<SDValue, 4> Ops;
3507 for (unsigned j = 0; j != 2; ++j) {
3508 SDValue SOp = SetCC->getOperand(j);
3510 Ops.push_back(ExtLoad);
3512 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND,
3513 N->getDebugLoc(), VT, SOp));
3516 Ops.push_back(SetCC->getOperand(2));
3517 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3518 SetCC->getValueType(0),
3519 &Ops[0], Ops.size()));
3522 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3526 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
3527 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
3528 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3529 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3530 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3531 EVT MemVT = LN0->getMemoryVT();
3532 if ((!LegalOperations && !LN0->isVolatile()) ||
3533 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
3534 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3536 LN0->getBasePtr(), LN0->getSrcValue(),
3537 LN0->getSrcValueOffset(), MemVT,
3538 LN0->isVolatile(), LN0->isNonTemporal(),
3539 LN0->getAlignment());
3540 CombineTo(N, ExtLoad);
3541 CombineTo(N0.getNode(),
3542 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3543 N0.getValueType(), ExtLoad),
3544 ExtLoad.getValue(1));
3545 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3549 if (N0.getOpcode() == ISD::SETCC) {
3550 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
3551 // Only do this before legalize for now.
3552 if (VT.isVector() && !LegalOperations) {
3553 EVT N0VT = N0.getOperand(0).getValueType();
3554 // We know that the # elements of the results is the same as the
3555 // # elements of the compare (and the # elements of the compare result
3556 // for that matter). Check to see that they are the same size. If so,
3557 // we know that the element size of the sext'd result matches the
3558 // element size of the compare operands.
3559 if (VT.getSizeInBits() == N0VT.getSizeInBits())
3560 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
3562 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3563 // If the desired elements are smaller or larger than the source
3564 // elements we can use a matching integer vector type and then
3565 // truncate/sign extend
3567 EVT MatchingElementType =
3568 EVT::getIntegerVT(*DAG.getContext(),
3569 N0VT.getScalarType().getSizeInBits());
3570 EVT MatchingVectorType =
3571 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
3572 N0VT.getVectorNumElements());
3574 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
3576 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3577 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
3581 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
3582 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
3584 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
3586 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3587 NegOne, DAG.getConstant(0, VT),
3588 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3589 if (SCC.getNode()) return SCC;
3590 if (!LegalOperations ||
3591 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
3592 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
3593 DAG.getSetCC(N->getDebugLoc(),
3594 TLI.getSetCCResultType(VT),
3595 N0.getOperand(0), N0.getOperand(1),
3596 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
3597 NegOne, DAG.getConstant(0, VT));
3600 // fold (sext x) -> (zext x) if the sign bit is known zero.
3601 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
3602 DAG.SignBitIsZero(N0))
3603 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3608 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
3609 SDValue N0 = N->getOperand(0);
3610 EVT VT = N->getValueType(0);
3612 // fold (zext c1) -> c1
3613 if (isa<ConstantSDNode>(N0))
3614 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3615 // fold (zext (zext x)) -> (zext x)
3616 // fold (zext (aext x)) -> (zext x)
3617 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3618 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
3621 // fold (zext (truncate (load x))) -> (zext (smaller load x))
3622 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
3623 if (N0.getOpcode() == ISD::TRUNCATE) {
3624 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3625 if (NarrowLoad.getNode()) {
3626 SDNode* oye = N0.getNode()->getOperand(0).getNode();
3627 if (NarrowLoad.getNode() != N0.getNode()) {
3628 CombineTo(N0.getNode(), NarrowLoad);
3629 // CombineTo deleted the truncate, if needed, but not what's under it.
3632 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3636 // fold (zext (truncate x)) -> (and x, mask)
3637 if (N0.getOpcode() == ISD::TRUNCATE &&
3638 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT)) &&
3639 (!TLI.isTruncateFree(N0.getOperand(0).getValueType(),
3640 N0.getValueType()) ||
3641 !TLI.isZExtFree(N0.getValueType(), VT))) {
3642 SDValue Op = N0.getOperand(0);
3643 if (Op.getValueType().bitsLT(VT)) {
3644 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
3645 } else if (Op.getValueType().bitsGT(VT)) {
3646 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3648 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
3649 N0.getValueType().getScalarType());
3652 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
3653 // if either of the casts is not free.
3654 if (N0.getOpcode() == ISD::AND &&
3655 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3656 N0.getOperand(1).getOpcode() == ISD::Constant &&
3657 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3658 N0.getValueType()) ||
3659 !TLI.isZExtFree(N0.getValueType(), VT))) {
3660 SDValue X = N0.getOperand(0).getOperand(0);
3661 if (X.getValueType().bitsLT(VT)) {
3662 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
3663 } else if (X.getValueType().bitsGT(VT)) {
3664 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
3666 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3667 Mask.zext(VT.getSizeInBits());
3668 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3669 X, DAG.getConstant(Mask, VT));
3672 // fold (zext (load x)) -> (zext (truncate (zextload x)))
3673 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3674 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3675 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
3676 bool DoXform = true;
3677 SmallVector<SDNode*, 4> SetCCs;
3678 if (!N0.hasOneUse())
3679 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
3681 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3682 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3684 LN0->getBasePtr(), LN0->getSrcValue(),
3685 LN0->getSrcValueOffset(),
3687 LN0->isVolatile(), LN0->isNonTemporal(),
3688 LN0->getAlignment());
3689 CombineTo(N, ExtLoad);
3690 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3691 N0.getValueType(), ExtLoad);
3692 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3694 // Extend SetCC uses if necessary.
3695 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3696 SDNode *SetCC = SetCCs[i];
3697 SmallVector<SDValue, 4> Ops;
3699 for (unsigned j = 0; j != 2; ++j) {
3700 SDValue SOp = SetCC->getOperand(j);
3702 Ops.push_back(ExtLoad);
3704 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND,
3705 N->getDebugLoc(), VT, SOp));
3708 Ops.push_back(SetCC->getOperand(2));
3709 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3710 SetCC->getValueType(0),
3711 &Ops[0], Ops.size()));
3714 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3718 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
3719 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
3720 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3721 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3722 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3723 EVT MemVT = LN0->getMemoryVT();
3724 if ((!LegalOperations && !LN0->isVolatile()) ||
3725 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
3726 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3728 LN0->getBasePtr(), LN0->getSrcValue(),
3729 LN0->getSrcValueOffset(), MemVT,
3730 LN0->isVolatile(), LN0->isNonTemporal(),
3731 LN0->getAlignment());
3732 CombineTo(N, ExtLoad);
3733 CombineTo(N0.getNode(),
3734 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
3736 ExtLoad.getValue(1));
3737 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3741 if (N0.getOpcode() == ISD::SETCC) {
3742 if (!LegalOperations && VT.isVector()) {
3743 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
3744 // Only do this before legalize for now.
3745 EVT N0VT = N0.getOperand(0).getValueType();
3746 EVT EltVT = VT.getVectorElementType();
3747 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
3748 DAG.getConstant(1, EltVT));
3749 if (VT.getSizeInBits() == N0VT.getSizeInBits()) {
3750 // We know that the # elements of the results is the same as the
3751 // # elements of the compare (and the # elements of the compare result
3752 // for that matter). Check to see that they are the same size. If so,
3753 // we know that the element size of the sext'd result matches the
3754 // element size of the compare operands.
3755 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3756 DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
3758 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
3759 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
3760 &OneOps[0], OneOps.size()));
3762 // If the desired elements are smaller or larger than the source
3763 // elements we can use a matching integer vector type and then
3764 // truncate/sign extend
3765 EVT MatchingElementType =
3766 EVT::getIntegerVT(*DAG.getContext(),
3767 N0VT.getScalarType().getSizeInBits());
3768 EVT MatchingVectorType =
3769 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
3770 N0VT.getVectorNumElements());
3772 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
3774 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3775 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3776 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT),
3777 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
3778 &OneOps[0], OneOps.size()));
3782 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3784 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3785 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3786 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3787 if (SCC.getNode()) return SCC;
3790 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
3791 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
3792 isa<ConstantSDNode>(N0.getOperand(1)) &&
3793 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
3795 if (N0.getOpcode() == ISD::SHL) {
3796 // If the original shl may be shifting out bits, do not perform this
3798 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3799 unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() -
3800 N0.getOperand(0).getOperand(0).getValueType().getSizeInBits();
3801 if (ShAmt > KnownZeroBits)
3804 DebugLoc dl = N->getDebugLoc();
3805 return DAG.getNode(N0.getOpcode(), dl, VT,
3806 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)),
3807 DAG.getNode(ISD::ZERO_EXTEND, dl,
3808 N0.getOperand(1).getValueType(),
3815 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
3816 SDValue N0 = N->getOperand(0);
3817 EVT VT = N->getValueType(0);
3819 // fold (aext c1) -> c1
3820 if (isa<ConstantSDNode>(N0))
3821 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
3822 // fold (aext (aext x)) -> (aext x)
3823 // fold (aext (zext x)) -> (zext x)
3824 // fold (aext (sext x)) -> (sext x)
3825 if (N0.getOpcode() == ISD::ANY_EXTEND ||
3826 N0.getOpcode() == ISD::ZERO_EXTEND ||
3827 N0.getOpcode() == ISD::SIGN_EXTEND)
3828 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
3830 // fold (aext (truncate (load x))) -> (aext (smaller load x))
3831 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
3832 if (N0.getOpcode() == ISD::TRUNCATE) {
3833 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3834 if (NarrowLoad.getNode()) {
3835 SDNode* oye = N0.getNode()->getOperand(0).getNode();
3836 if (NarrowLoad.getNode() != N0.getNode()) {
3837 CombineTo(N0.getNode(), NarrowLoad);
3838 // CombineTo deleted the truncate, if needed, but not what's under it.
3841 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3845 // fold (aext (truncate x))
3846 if (N0.getOpcode() == ISD::TRUNCATE) {
3847 SDValue TruncOp = N0.getOperand(0);
3848 if (TruncOp.getValueType() == VT)
3849 return TruncOp; // x iff x size == zext size.
3850 if (TruncOp.getValueType().bitsGT(VT))
3851 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
3852 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
3855 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
3856 // if the trunc is not free.
3857 if (N0.getOpcode() == ISD::AND &&
3858 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3859 N0.getOperand(1).getOpcode() == ISD::Constant &&
3860 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3861 N0.getValueType())) {
3862 SDValue X = N0.getOperand(0).getOperand(0);
3863 if (X.getValueType().bitsLT(VT)) {
3864 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
3865 } else if (X.getValueType().bitsGT(VT)) {
3866 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
3868 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3869 Mask.zext(VT.getSizeInBits());
3870 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3871 X, DAG.getConstant(Mask, VT));
3874 // fold (aext (load x)) -> (aext (truncate (extload x)))
3875 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3876 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3877 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
3878 bool DoXform = true;
3879 SmallVector<SDNode*, 4> SetCCs;
3880 if (!N0.hasOneUse())
3881 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
3883 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3884 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
3886 LN0->getBasePtr(), LN0->getSrcValue(),
3887 LN0->getSrcValueOffset(),
3889 LN0->isVolatile(), LN0->isNonTemporal(),
3890 LN0->getAlignment());
3891 CombineTo(N, ExtLoad);
3892 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3893 N0.getValueType(), ExtLoad);
3894 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3896 // Extend SetCC uses if necessary.
3897 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3898 SDNode *SetCC = SetCCs[i];
3899 SmallVector<SDValue, 4> Ops;
3901 for (unsigned j = 0; j != 2; ++j) {
3902 SDValue SOp = SetCC->getOperand(j);
3904 Ops.push_back(ExtLoad);
3906 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND,
3907 N->getDebugLoc(), VT, SOp));
3910 Ops.push_back(SetCC->getOperand(2));
3911 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3912 SetCC->getValueType(0),
3913 &Ops[0], Ops.size()));
3916 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3920 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
3921 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
3922 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
3923 if (N0.getOpcode() == ISD::LOAD &&
3924 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3926 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3927 EVT MemVT = LN0->getMemoryVT();
3928 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
3929 VT, LN0->getChain(), LN0->getBasePtr(),
3931 LN0->getSrcValueOffset(), MemVT,
3932 LN0->isVolatile(), LN0->isNonTemporal(),
3933 LN0->getAlignment());
3934 CombineTo(N, ExtLoad);
3935 CombineTo(N0.getNode(),
3936 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3937 N0.getValueType(), ExtLoad),
3938 ExtLoad.getValue(1));
3939 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3942 if (N0.getOpcode() == ISD::SETCC) {
3943 // aext(setcc) -> sext_in_reg(vsetcc) for vectors.
3944 // Only do this before legalize for now.
3945 if (VT.isVector() && !LegalOperations) {
3946 EVT N0VT = N0.getOperand(0).getValueType();
3947 // We know that the # elements of the results is the same as the
3948 // # elements of the compare (and the # elements of the compare result
3949 // for that matter). Check to see that they are the same size. If so,
3950 // we know that the element size of the sext'd result matches the
3951 // element size of the compare operands.
3952 if (VT.getSizeInBits() == N0VT.getSizeInBits())
3953 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
3955 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3956 // If the desired elements are smaller or larger than the source
3957 // elements we can use a matching integer vector type and then
3958 // truncate/sign extend
3960 EVT MatchingElementType =
3961 EVT::getIntegerVT(*DAG.getContext(),
3962 N0VT.getScalarType().getSizeInBits());
3963 EVT MatchingVectorType =
3964 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
3965 N0VT.getVectorNumElements());
3967 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
3969 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3970 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
3974 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3976 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3977 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3978 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3986 /// GetDemandedBits - See if the specified operand can be simplified with the
3987 /// knowledge that only the bits specified by Mask are used. If so, return the
3988 /// simpler operand, otherwise return a null SDValue.
3989 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
3990 switch (V.getOpcode()) {
3994 // If the LHS or RHS don't contribute bits to the or, drop them.
3995 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
3996 return V.getOperand(1);
3997 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
3998 return V.getOperand(0);
4001 // Only look at single-use SRLs.
4002 if (!V.getNode()->hasOneUse())
4004 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
4005 // See if we can recursively simplify the LHS.
4006 unsigned Amt = RHSC->getZExtValue();
4008 // Watch out for shift count overflow though.
4009 if (Amt >= Mask.getBitWidth()) break;
4010 APInt NewMask = Mask << Amt;
4011 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
4012 if (SimplifyLHS.getNode())
4013 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
4014 SimplifyLHS, V.getOperand(1));
4020 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
4021 /// bits and then truncated to a narrower type and where N is a multiple
4022 /// of number of bits of the narrower type, transform it to a narrower load
4023 /// from address + N / num of bits of new type. If the result is to be
4024 /// extended, also fold the extension to form a extending load.
4025 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
4026 unsigned Opc = N->getOpcode();
4027 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
4028 SDValue N0 = N->getOperand(0);
4029 EVT VT = N->getValueType(0);
4032 // This transformation isn't valid for vector loads.
4036 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
4038 if (Opc == ISD::SIGN_EXTEND_INREG) {
4039 ExtType = ISD::SEXTLOAD;
4040 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4041 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT))
4045 unsigned EVTBits = ExtVT.getSizeInBits();
4047 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() && ExtVT.isRound()) {
4048 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4049 ShAmt = N01->getZExtValue();
4050 // Is the shift amount a multiple of size of VT?
4051 if ((ShAmt & (EVTBits-1)) == 0) {
4052 N0 = N0.getOperand(0);
4053 // Is the load width a multiple of size of VT?
4054 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
4060 // Do not generate loads of non-round integer types since these can
4061 // be expensive (and would be wrong if the type is not byte sized).
4062 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() &&
4063 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() >= EVTBits &&
4064 // Do not change the width of a volatile load.
4065 !cast<LoadSDNode>(N0)->isVolatile()) {
4066 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4067 EVT PtrType = N0.getOperand(1).getValueType();
4069 // For big endian targets, we need to adjust the offset to the pointer to
4070 // load the correct bytes.
4071 if (TLI.isBigEndian()) {
4072 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
4073 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
4074 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
4077 uint64_t PtrOff = ShAmt / 8;
4078 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
4079 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
4080 PtrType, LN0->getBasePtr(),
4081 DAG.getConstant(PtrOff, PtrType));
4082 AddToWorkList(NewPtr.getNode());
4084 SDValue Load = (ExtType == ISD::NON_EXTLOAD)
4085 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
4086 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
4087 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign)
4088 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr,
4089 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
4090 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
4093 // Replace the old load's chain with the new load's chain.
4094 WorkListRemover DeadNodes(*this);
4095 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
4098 // Return the new loaded value.
4105 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
4106 SDValue N0 = N->getOperand(0);
4107 SDValue N1 = N->getOperand(1);
4108 EVT VT = N->getValueType(0);
4109 EVT EVT = cast<VTSDNode>(N1)->getVT();
4110 unsigned VTBits = VT.getScalarType().getSizeInBits();
4111 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
4113 // fold (sext_in_reg c1) -> c1
4114 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
4115 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
4117 // If the input is already sign extended, just drop the extension.
4118 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
4121 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
4122 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
4123 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
4124 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
4125 N0.getOperand(0), N1);
4128 // fold (sext_in_reg (sext x)) -> (sext x)
4129 // fold (sext_in_reg (aext x)) -> (sext x)
4130 // if x is small enough.
4131 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
4132 SDValue N00 = N0.getOperand(0);
4133 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
4134 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
4135 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
4138 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
4139 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
4140 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
4142 // fold operands of sext_in_reg based on knowledge that the top bits are not
4144 if (SimplifyDemandedBits(SDValue(N, 0)))
4145 return SDValue(N, 0);
4147 // fold (sext_in_reg (load x)) -> (smaller sextload x)
4148 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
4149 SDValue NarrowLoad = ReduceLoadWidth(N);
4150 if (NarrowLoad.getNode())
4153 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
4154 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
4155 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
4156 if (N0.getOpcode() == ISD::SRL) {
4157 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
4158 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
4159 // We can turn this into an SRA iff the input to the SRL is already sign
4161 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
4162 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
4163 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
4164 N0.getOperand(0), N0.getOperand(1));
4168 // fold (sext_inreg (extload x)) -> (sextload x)
4169 if (ISD::isEXTLoad(N0.getNode()) &&
4170 ISD::isUNINDEXEDLoad(N0.getNode()) &&
4171 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4172 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4173 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
4174 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4175 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4177 LN0->getBasePtr(), LN0->getSrcValue(),
4178 LN0->getSrcValueOffset(), EVT,
4179 LN0->isVolatile(), LN0->isNonTemporal(),
4180 LN0->getAlignment());
4181 CombineTo(N, ExtLoad);
4182 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4183 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4185 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
4186 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4188 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4189 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4190 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
4191 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4192 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4194 LN0->getBasePtr(), LN0->getSrcValue(),
4195 LN0->getSrcValueOffset(), EVT,
4196 LN0->isVolatile(), LN0->isNonTemporal(),
4197 LN0->getAlignment());
4198 CombineTo(N, ExtLoad);
4199 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4200 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4205 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
4206 SDValue N0 = N->getOperand(0);
4207 EVT VT = N->getValueType(0);
4210 if (N0.getValueType() == N->getValueType(0))
4212 // fold (truncate c1) -> c1
4213 if (isa<ConstantSDNode>(N0))
4214 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
4215 // fold (truncate (truncate x)) -> (truncate x)
4216 if (N0.getOpcode() == ISD::TRUNCATE)
4217 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4218 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
4219 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
4220 N0.getOpcode() == ISD::SIGN_EXTEND ||
4221 N0.getOpcode() == ISD::ANY_EXTEND) {
4222 if (N0.getOperand(0).getValueType().bitsLT(VT))
4223 // if the source is smaller than the dest, we still need an extend
4224 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4226 else if (N0.getOperand(0).getValueType().bitsGT(VT))
4227 // if the source is larger than the dest, than we just need the truncate
4228 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4230 // if the source and dest are the same type, we can drop both the extend
4231 // and the truncate.
4232 return N0.getOperand(0);
4235 // See if we can simplify the input to this truncate through knowledge that
4236 // only the low bits are being used. For example "trunc (or (shl x, 8), y)"
4239 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
4240 VT.getSizeInBits()));
4241 if (Shorter.getNode())
4242 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
4244 // fold (truncate (load x)) -> (smaller load x)
4245 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
4246 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT))
4247 return ReduceLoadWidth(N);
4251 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
4252 SDValue Elt = N->getOperand(i);
4253 if (Elt.getOpcode() != ISD::MERGE_VALUES)
4254 return Elt.getNode();
4255 return Elt.getOperand(Elt.getResNo()).getNode();
4258 /// CombineConsecutiveLoads - build_pair (load, load) -> load
4259 /// if load locations are consecutive.
4260 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
4261 assert(N->getOpcode() == ISD::BUILD_PAIR);
4263 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
4264 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
4265 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse())
4267 EVT LD1VT = LD1->getValueType(0);
4269 if (ISD::isNON_EXTLoad(LD2) &&
4271 // If both are volatile this would reduce the number of volatile loads.
4272 // If one is volatile it might be ok, but play conservative and bail out.
4273 !LD1->isVolatile() &&
4274 !LD2->isVolatile() &&
4275 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
4276 unsigned Align = LD1->getAlignment();
4277 unsigned NewAlign = TLI.getTargetData()->
4278 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
4280 if (NewAlign <= Align &&
4281 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
4282 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
4283 LD1->getBasePtr(), LD1->getSrcValue(),
4284 LD1->getSrcValueOffset(), false, false, Align);
4290 SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
4291 SDValue N0 = N->getOperand(0);
4292 EVT VT = N->getValueType(0);
4294 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
4295 // Only do this before legalize, since afterward the target may be depending
4296 // on the bitconvert.
4297 // First check to see if this is all constant.
4299 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
4301 bool isSimple = true;
4302 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
4303 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
4304 N0.getOperand(i).getOpcode() != ISD::Constant &&
4305 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
4310 EVT DestEltVT = N->getValueType(0).getVectorElementType();
4311 assert(!DestEltVT.isVector() &&
4312 "Element type of vector ValueType must not be vector!");
4314 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT);
4317 // If the input is a constant, let getNode fold it.
4318 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
4319 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0);
4320 if (Res.getNode() != N) {
4321 if (!LegalOperations ||
4322 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
4325 // Folding it resulted in an illegal node, and it's too late to
4326 // do that. Clean up the old node and forego the transformation.
4327 // Ideally this won't happen very often, because instcombine
4328 // and the earlier dagcombine runs (where illegal nodes are
4329 // permitted) should have folded most of them already.
4330 DAG.DeleteNode(Res.getNode());
4334 // (conv (conv x, t1), t2) -> (conv x, t2)
4335 if (N0.getOpcode() == ISD::BIT_CONVERT)
4336 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT,
4339 // fold (conv (load x)) -> (load (conv*)x)
4340 // If the resultant load doesn't need a higher alignment than the original!
4341 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
4342 // Do not change the width of a volatile load.
4343 !cast<LoadSDNode>(N0)->isVolatile() &&
4344 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
4345 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4346 unsigned Align = TLI.getTargetData()->
4347 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
4348 unsigned OrigAlign = LN0->getAlignment();
4350 if (Align <= OrigAlign) {
4351 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
4353 LN0->getSrcValue(), LN0->getSrcValueOffset(),
4354 LN0->isVolatile(), LN0->isNonTemporal(),
4357 CombineTo(N0.getNode(),
4358 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
4359 N0.getValueType(), Load),
4365 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
4366 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
4367 // This often reduces constant pool loads.
4368 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
4369 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
4370 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT,
4372 AddToWorkList(NewConv.getNode());
4374 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
4375 if (N0.getOpcode() == ISD::FNEG)
4376 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
4377 NewConv, DAG.getConstant(SignBit, VT));
4378 assert(N0.getOpcode() == ISD::FABS);
4379 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4380 NewConv, DAG.getConstant(~SignBit, VT));
4383 // fold (bitconvert (fcopysign cst, x)) ->
4384 // (or (and (bitconvert x), sign), (and cst, (not sign)))
4385 // Note that we don't handle (copysign x, cst) because this can always be
4386 // folded to an fneg or fabs.
4387 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
4388 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
4389 VT.isInteger() && !VT.isVector()) {
4390 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
4391 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
4392 if (isTypeLegal(IntXVT)) {
4393 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
4394 IntXVT, N0.getOperand(1));
4395 AddToWorkList(X.getNode());
4397 // If X has a different width than the result/lhs, sext it or truncate it.
4398 unsigned VTWidth = VT.getSizeInBits();
4399 if (OrigXWidth < VTWidth) {
4400 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
4401 AddToWorkList(X.getNode());
4402 } else if (OrigXWidth > VTWidth) {
4403 // To get the sign bit in the right place, we have to shift it right
4404 // before truncating.
4405 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
4406 X.getValueType(), X,
4407 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
4408 AddToWorkList(X.getNode());
4409 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4410 AddToWorkList(X.getNode());
4413 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
4414 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
4415 X, DAG.getConstant(SignBit, VT));
4416 AddToWorkList(X.getNode());
4418 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
4419 VT, N0.getOperand(0));
4420 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
4421 Cst, DAG.getConstant(~SignBit, VT));
4422 AddToWorkList(Cst.getNode());
4424 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
4428 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
4429 if (N0.getOpcode() == ISD::BUILD_PAIR) {
4430 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
4431 if (CombineLD.getNode())
4438 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
4439 EVT VT = N->getValueType(0);
4440 return CombineConsecutiveLoads(N, VT);
4443 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
4444 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
4445 /// destination element value type.
4446 SDValue DAGCombiner::
4447 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
4448 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
4450 // If this is already the right type, we're done.
4451 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
4453 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
4454 unsigned DstBitSize = DstEltVT.getSizeInBits();
4456 // If this is a conversion of N elements of one type to N elements of another
4457 // type, convert each element. This handles FP<->INT cases.
4458 if (SrcBitSize == DstBitSize) {
4459 SmallVector<SDValue, 8> Ops;
4460 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
4461 SDValue Op = BV->getOperand(i);
4462 // If the vector element type is not legal, the BUILD_VECTOR operands
4463 // are promoted and implicitly truncated. Make that explicit here.
4464 if (Op.getValueType() != SrcEltVT)
4465 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
4466 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(),
4468 AddToWorkList(Ops.back().getNode());
4470 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
4471 BV->getValueType(0).getVectorNumElements());
4472 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4473 &Ops[0], Ops.size());
4476 // Otherwise, we're growing or shrinking the elements. To avoid having to
4477 // handle annoying details of growing/shrinking FP values, we convert them to
4479 if (SrcEltVT.isFloatingPoint()) {
4480 // Convert the input float vector to a int vector where the elements are the
4482 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
4483 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
4484 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
4488 // Now we know the input is an integer vector. If the output is a FP type,
4489 // convert to integer first, then to FP of the right size.
4490 if (DstEltVT.isFloatingPoint()) {
4491 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
4492 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
4493 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
4495 // Next, convert to FP elements of the same size.
4496 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
4499 // Okay, we know the src/dst types are both integers of differing types.
4500 // Handling growing first.
4501 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
4502 if (SrcBitSize < DstBitSize) {
4503 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
4505 SmallVector<SDValue, 8> Ops;
4506 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
4507 i += NumInputsPerOutput) {
4508 bool isLE = TLI.isLittleEndian();
4509 APInt NewBits = APInt(DstBitSize, 0);
4510 bool EltIsUndef = true;
4511 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
4512 // Shift the previously computed bits over.
4513 NewBits <<= SrcBitSize;
4514 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
4515 if (Op.getOpcode() == ISD::UNDEF) continue;
4518 NewBits |= APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).
4519 zextOrTrunc(SrcBitSize).zext(DstBitSize);
4523 Ops.push_back(DAG.getUNDEF(DstEltVT));
4525 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
4528 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
4529 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4530 &Ops[0], Ops.size());
4533 // Finally, this must be the case where we are shrinking elements: each input
4534 // turns into multiple outputs.
4535 bool isS2V = ISD::isScalarToVector(BV);
4536 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
4537 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
4538 NumOutputsPerInput*BV->getNumOperands());
4539 SmallVector<SDValue, 8> Ops;
4541 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
4542 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
4543 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
4544 Ops.push_back(DAG.getUNDEF(DstEltVT));
4548 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))->
4549 getAPIntValue()).zextOrTrunc(SrcBitSize);
4551 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
4552 APInt ThisVal = APInt(OpVal).trunc(DstBitSize);
4553 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
4554 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal)
4555 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
4556 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
4558 OpVal = OpVal.lshr(DstBitSize);
4561 // For big endian targets, swap the order of the pieces of each element.
4562 if (TLI.isBigEndian())
4563 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
4566 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4567 &Ops[0], Ops.size());
4570 SDValue DAGCombiner::visitFADD(SDNode *N) {
4571 SDValue N0 = N->getOperand(0);
4572 SDValue N1 = N->getOperand(1);
4573 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4574 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4575 EVT VT = N->getValueType(0);
4578 if (VT.isVector()) {
4579 SDValue FoldedVOp = SimplifyVBinOp(N);
4580 if (FoldedVOp.getNode()) return FoldedVOp;
4583 // fold (fadd c1, c2) -> (fadd c1, c2)
4584 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4585 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
4586 // canonicalize constant to RHS
4587 if (N0CFP && !N1CFP)
4588 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
4589 // fold (fadd A, 0) -> A
4590 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4592 // fold (fadd A, (fneg B)) -> (fsub A, B)
4593 if (isNegatibleForFree(N1, LegalOperations) == 2)
4594 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
4595 GetNegatedExpression(N1, DAG, LegalOperations));
4596 // fold (fadd (fneg A), B) -> (fsub B, A)
4597 if (isNegatibleForFree(N0, LegalOperations) == 2)
4598 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
4599 GetNegatedExpression(N0, DAG, LegalOperations));
4601 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
4602 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
4603 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4604 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
4605 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
4606 N0.getOperand(1), N1));
4611 SDValue DAGCombiner::visitFSUB(SDNode *N) {
4612 SDValue N0 = N->getOperand(0);
4613 SDValue N1 = N->getOperand(1);
4614 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4615 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4616 EVT VT = N->getValueType(0);
4619 if (VT.isVector()) {
4620 SDValue FoldedVOp = SimplifyVBinOp(N);
4621 if (FoldedVOp.getNode()) return FoldedVOp;
4624 // fold (fsub c1, c2) -> c1-c2
4625 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4626 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
4627 // fold (fsub A, 0) -> A
4628 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4630 // fold (fsub 0, B) -> -B
4631 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
4632 if (isNegatibleForFree(N1, LegalOperations))
4633 return GetNegatedExpression(N1, DAG, LegalOperations);
4634 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4635 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
4637 // fold (fsub A, (fneg B)) -> (fadd A, B)
4638 if (isNegatibleForFree(N1, LegalOperations))
4639 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
4640 GetNegatedExpression(N1, DAG, LegalOperations));
4645 SDValue DAGCombiner::visitFMUL(SDNode *N) {
4646 SDValue N0 = N->getOperand(0);
4647 SDValue N1 = N->getOperand(1);
4648 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4649 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4650 EVT VT = N->getValueType(0);
4653 if (VT.isVector()) {
4654 SDValue FoldedVOp = SimplifyVBinOp(N);
4655 if (FoldedVOp.getNode()) return FoldedVOp;
4658 // fold (fmul c1, c2) -> c1*c2
4659 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4660 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
4661 // canonicalize constant to RHS
4662 if (N0CFP && !N1CFP)
4663 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
4664 // fold (fmul A, 0) -> 0
4665 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4667 // fold (fmul A, 0) -> 0, vector edition.
4668 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode()))
4670 // fold (fmul X, 2.0) -> (fadd X, X)
4671 if (N1CFP && N1CFP->isExactlyValue(+2.0))
4672 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
4673 // fold (fmul X, -1.0) -> (fneg X)
4674 if (N1CFP && N1CFP->isExactlyValue(-1.0))
4675 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4676 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
4678 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
4679 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4680 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4681 // Both can be negated for free, check to see if at least one is cheaper
4683 if (LHSNeg == 2 || RHSNeg == 2)
4684 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4685 GetNegatedExpression(N0, DAG, LegalOperations),
4686 GetNegatedExpression(N1, DAG, LegalOperations));
4690 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
4691 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
4692 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4693 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
4694 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4695 N0.getOperand(1), N1));
4700 SDValue DAGCombiner::visitFDIV(SDNode *N) {
4701 SDValue N0 = N->getOperand(0);
4702 SDValue N1 = N->getOperand(1);
4703 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4704 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4705 EVT VT = N->getValueType(0);
4708 if (VT.isVector()) {
4709 SDValue FoldedVOp = SimplifyVBinOp(N);
4710 if (FoldedVOp.getNode()) return FoldedVOp;
4713 // fold (fdiv c1, c2) -> c1/c2
4714 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4715 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
4718 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
4719 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4720 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4721 // Both can be negated for free, check to see if at least one is cheaper
4723 if (LHSNeg == 2 || RHSNeg == 2)
4724 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
4725 GetNegatedExpression(N0, DAG, LegalOperations),
4726 GetNegatedExpression(N1, DAG, LegalOperations));
4733 SDValue DAGCombiner::visitFREM(SDNode *N) {
4734 SDValue N0 = N->getOperand(0);
4735 SDValue N1 = N->getOperand(1);
4736 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4737 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4738 EVT VT = N->getValueType(0);
4740 // fold (frem c1, c2) -> fmod(c1,c2)
4741 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4742 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
4747 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
4748 SDValue N0 = N->getOperand(0);
4749 SDValue N1 = N->getOperand(1);
4750 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4751 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4752 EVT VT = N->getValueType(0);
4754 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
4755 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
4758 const APFloat& V = N1CFP->getValueAPF();
4759 // copysign(x, c1) -> fabs(x) iff ispos(c1)
4760 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
4761 if (!V.isNegative()) {
4762 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
4763 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4765 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4766 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
4767 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
4771 // copysign(fabs(x), y) -> copysign(x, y)
4772 // copysign(fneg(x), y) -> copysign(x, y)
4773 // copysign(copysign(x,z), y) -> copysign(x, y)
4774 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
4775 N0.getOpcode() == ISD::FCOPYSIGN)
4776 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4777 N0.getOperand(0), N1);
4779 // copysign(x, abs(y)) -> abs(x)
4780 if (N1.getOpcode() == ISD::FABS)
4781 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4783 // copysign(x, copysign(y,z)) -> copysign(x, z)
4784 if (N1.getOpcode() == ISD::FCOPYSIGN)
4785 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4786 N0, N1.getOperand(1));
4788 // copysign(x, fp_extend(y)) -> copysign(x, y)
4789 // copysign(x, fp_round(y)) -> copysign(x, y)
4790 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
4791 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4792 N0, N1.getOperand(0));
4797 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
4798 SDValue N0 = N->getOperand(0);
4799 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4800 EVT VT = N->getValueType(0);
4801 EVT OpVT = N0.getValueType();
4803 // fold (sint_to_fp c1) -> c1fp
4804 if (N0C && OpVT != MVT::ppcf128)
4805 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4807 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
4808 // but UINT_TO_FP is legal on this target, try to convert.
4809 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
4810 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
4811 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
4812 if (DAG.SignBitIsZero(N0))
4813 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4819 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
4820 SDValue N0 = N->getOperand(0);
4821 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4822 EVT VT = N->getValueType(0);
4823 EVT OpVT = N0.getValueType();
4825 // fold (uint_to_fp c1) -> c1fp
4826 if (N0C && OpVT != MVT::ppcf128)
4827 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4829 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
4830 // but SINT_TO_FP is legal on this target, try to convert.
4831 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
4832 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
4833 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
4834 if (DAG.SignBitIsZero(N0))
4835 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4841 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
4842 SDValue N0 = N->getOperand(0);
4843 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4844 EVT VT = N->getValueType(0);
4846 // fold (fp_to_sint c1fp) -> c1
4848 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
4853 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
4854 SDValue N0 = N->getOperand(0);
4855 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4856 EVT VT = N->getValueType(0);
4858 // fold (fp_to_uint c1fp) -> c1
4859 if (N0CFP && VT != MVT::ppcf128)
4860 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
4865 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
4866 SDValue N0 = N->getOperand(0);
4867 SDValue N1 = N->getOperand(1);
4868 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4869 EVT VT = N->getValueType(0);
4871 // fold (fp_round c1fp) -> c1fp
4872 if (N0CFP && N0.getValueType() != MVT::ppcf128)
4873 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
4875 // fold (fp_round (fp_extend x)) -> x
4876 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
4877 return N0.getOperand(0);
4879 // fold (fp_round (fp_round x)) -> (fp_round x)
4880 if (N0.getOpcode() == ISD::FP_ROUND) {
4881 // This is a value preserving truncation if both round's are.
4882 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
4883 N0.getNode()->getConstantOperandVal(1) == 1;
4884 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
4885 DAG.getIntPtrConstant(IsTrunc));
4888 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
4889 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
4890 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
4891 N0.getOperand(0), N1);
4892 AddToWorkList(Tmp.getNode());
4893 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4894 Tmp, N0.getOperand(1));
4900 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
4901 SDValue N0 = N->getOperand(0);
4902 EVT VT = N->getValueType(0);
4903 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4904 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4906 // fold (fp_round_inreg c1fp) -> c1fp
4907 if (N0CFP && isTypeLegal(EVT)) {
4908 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
4909 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
4915 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
4916 SDValue N0 = N->getOperand(0);
4917 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4918 EVT VT = N->getValueType(0);
4920 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
4921 if (N->hasOneUse() &&
4922 N->use_begin()->getOpcode() == ISD::FP_ROUND)
4925 // fold (fp_extend c1fp) -> c1fp
4926 if (N0CFP && VT != MVT::ppcf128)
4927 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
4929 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
4931 if (N0.getOpcode() == ISD::FP_ROUND
4932 && N0.getNode()->getConstantOperandVal(1) == 1) {
4933 SDValue In = N0.getOperand(0);
4934 if (In.getValueType() == VT) return In;
4935 if (VT.bitsLT(In.getValueType()))
4936 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
4937 In, N0.getOperand(1));
4938 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
4941 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
4942 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
4943 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4944 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4945 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4946 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4948 LN0->getBasePtr(), LN0->getSrcValue(),
4949 LN0->getSrcValueOffset(),
4951 LN0->isVolatile(), LN0->isNonTemporal(),
4952 LN0->getAlignment());
4953 CombineTo(N, ExtLoad);
4954 CombineTo(N0.getNode(),
4955 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
4956 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
4957 ExtLoad.getValue(1));
4958 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4964 SDValue DAGCombiner::visitFNEG(SDNode *N) {
4965 SDValue N0 = N->getOperand(0);
4966 EVT VT = N->getValueType(0);
4968 if (isNegatibleForFree(N0, LegalOperations))
4969 return GetNegatedExpression(N0, DAG, LegalOperations);
4971 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
4972 // constant pool values.
4973 if (N0.getOpcode() == ISD::BIT_CONVERT &&
4975 N0.getNode()->hasOneUse() &&
4976 N0.getOperand(0).getValueType().isInteger()) {
4977 SDValue Int = N0.getOperand(0);
4978 EVT IntVT = Int.getValueType();
4979 if (IntVT.isInteger() && !IntVT.isVector()) {
4980 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
4981 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
4982 AddToWorkList(Int.getNode());
4983 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4991 SDValue DAGCombiner::visitFABS(SDNode *N) {
4992 SDValue N0 = N->getOperand(0);
4993 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4994 EVT VT = N->getValueType(0);
4996 // fold (fabs c1) -> fabs(c1)
4997 if (N0CFP && VT != MVT::ppcf128)
4998 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4999 // fold (fabs (fabs x)) -> (fabs x)
5000 if (N0.getOpcode() == ISD::FABS)
5001 return N->getOperand(0);
5002 // fold (fabs (fneg x)) -> (fabs x)
5003 // fold (fabs (fcopysign x, y)) -> (fabs x)
5004 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
5005 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
5007 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
5008 // constant pool values.
5009 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
5010 N0.getOperand(0).getValueType().isInteger() &&
5011 !N0.getOperand(0).getValueType().isVector()) {
5012 SDValue Int = N0.getOperand(0);
5013 EVT IntVT = Int.getValueType();
5014 if (IntVT.isInteger() && !IntVT.isVector()) {
5015 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
5016 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5017 AddToWorkList(Int.getNode());
5018 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
5019 N->getValueType(0), Int);
5026 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
5027 SDValue Chain = N->getOperand(0);
5028 SDValue N1 = N->getOperand(1);
5029 SDValue N2 = N->getOperand(2);
5031 // If N is a constant we could fold this into a fallthrough or unconditional
5032 // branch. However that doesn't happen very often in normal code, because
5033 // Instcombine/SimplifyCFG should have handled the available opportunities.
5034 // If we did this folding here, it would be necessary to update the
5035 // MachineBasicBlock CFG, which is awkward.
5037 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
5039 if (N1.getOpcode() == ISD::SETCC &&
5040 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
5041 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5042 Chain, N1.getOperand(2),
5043 N1.getOperand(0), N1.getOperand(1), N2);
5047 if (N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) {
5048 // Look past truncate.
5049 Trunc = N1.getNode();
5050 N1 = N1.getOperand(0);
5053 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) {
5054 // Match this pattern so that we can generate simpler code:
5057 // %b = and i32 %a, 2
5058 // %c = srl i32 %b, 1
5059 // brcond i32 %c ...
5064 // %b = and i32 %a, 2
5065 // %c = setcc eq %b, 0
5068 // This applies only when the AND constant value has one bit set and the
5069 // SRL constant is equal to the log2 of the AND constant. The back-end is
5070 // smart enough to convert the result into a TEST/JMP sequence.
5071 SDValue Op0 = N1.getOperand(0);
5072 SDValue Op1 = N1.getOperand(1);
5074 if (Op0.getOpcode() == ISD::AND &&
5075 Op1.getOpcode() == ISD::Constant) {
5076 SDValue AndOp1 = Op0.getOperand(1);
5078 if (AndOp1.getOpcode() == ISD::Constant) {
5079 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
5081 if (AndConst.isPowerOf2() &&
5082 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
5084 DAG.getSetCC(N->getDebugLoc(),
5085 TLI.getSetCCResultType(Op0.getValueType()),
5086 Op0, DAG.getConstant(0, Op0.getValueType()),
5089 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5090 MVT::Other, Chain, SetCC, N2);
5091 // Don't add the new BRCond into the worklist or else SimplifySelectCC
5092 // will convert it back to (X & C1) >> C2.
5093 CombineTo(N, NewBRCond, false);
5094 // Truncate is dead.
5096 removeFromWorkList(Trunc);
5097 DAG.DeleteNode(Trunc);
5099 // Replace the uses of SRL with SETCC
5100 WorkListRemover DeadNodes(*this);
5101 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
5102 removeFromWorkList(N1.getNode());
5103 DAG.DeleteNode(N1.getNode());
5104 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5110 // Transform br(xor(x, y)) -> br(x != y)
5111 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
5112 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
5113 SDNode *TheXor = N1.getNode();
5114 SDValue Op0 = TheXor->getOperand(0);
5115 SDValue Op1 = TheXor->getOperand(1);
5116 if (Op0.getOpcode() == Op1.getOpcode()) {
5117 // Avoid missing important xor optimizations.
5118 SDValue Tmp = visitXOR(TheXor);
5119 if (Tmp.getNode() && Tmp.getNode() != TheXor) {
5120 DEBUG(dbgs() << "\nReplacing.8 ";
5122 dbgs() << "\nWith: ";
5123 Tmp.getNode()->dump(&DAG);
5125 WorkListRemover DeadNodes(*this);
5126 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes);
5127 removeFromWorkList(TheXor);
5128 DAG.DeleteNode(TheXor);
5129 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5130 MVT::Other, Chain, Tmp, N2);
5134 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
5136 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
5137 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
5138 Op0.getOpcode() == ISD::XOR) {
5139 TheXor = Op0.getNode();
5143 SDValue NodeToReplace = Trunc ? SDValue(Trunc, 0) : N1;
5145 EVT SetCCVT = NodeToReplace.getValueType();
5147 SetCCVT = TLI.getSetCCResultType(SetCCVT);
5148 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
5151 Equal ? ISD::SETEQ : ISD::SETNE);
5152 // Replace the uses of XOR with SETCC
5153 WorkListRemover DeadNodes(*this);
5154 DAG.ReplaceAllUsesOfValueWith(NodeToReplace, SetCC, &DeadNodes);
5155 removeFromWorkList(NodeToReplace.getNode());
5156 DAG.DeleteNode(NodeToReplace.getNode());
5157 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5158 MVT::Other, Chain, SetCC, N2);
5165 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
5167 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
5168 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
5169 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
5171 // If N is a constant we could fold this into a fallthrough or unconditional
5172 // branch. However that doesn't happen very often in normal code, because
5173 // Instcombine/SimplifyCFG should have handled the available opportunities.
5174 // If we did this folding here, it would be necessary to update the
5175 // MachineBasicBlock CFG, which is awkward.
5177 // Use SimplifySetCC to simplify SETCC's.
5178 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
5179 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
5181 if (Simp.getNode()) AddToWorkList(Simp.getNode());
5183 // fold to a simpler setcc
5184 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
5185 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5186 N->getOperand(0), Simp.getOperand(2),
5187 Simp.getOperand(0), Simp.getOperand(1),
5193 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
5194 /// pre-indexed load / store when the base pointer is an add or subtract
5195 /// and it has other uses besides the load / store. After the
5196 /// transformation, the new indexed load / store has effectively folded
5197 /// the add / subtract in and all of its other uses are redirected to the
5198 /// new load / store.
5199 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
5200 if (!LegalOperations)
5206 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5207 if (LD->isIndexed())
5209 VT = LD->getMemoryVT();
5210 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
5211 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
5213 Ptr = LD->getBasePtr();
5214 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5215 if (ST->isIndexed())
5217 VT = ST->getMemoryVT();
5218 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
5219 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
5221 Ptr = ST->getBasePtr();
5227 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
5228 // out. There is no reason to make this a preinc/predec.
5229 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
5230 Ptr.getNode()->hasOneUse())
5233 // Ask the target to do addressing mode selection.
5236 ISD::MemIndexedMode AM = ISD::UNINDEXED;
5237 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
5239 // Don't create a indexed load / store with zero offset.
5240 if (isa<ConstantSDNode>(Offset) &&
5241 cast<ConstantSDNode>(Offset)->isNullValue())
5244 // Try turning it into a pre-indexed load / store except when:
5245 // 1) The new base ptr is a frame index.
5246 // 2) If N is a store and the new base ptr is either the same as or is a
5247 // predecessor of the value being stored.
5248 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
5249 // that would create a cycle.
5250 // 4) All uses are load / store ops that use it as old base ptr.
5252 // Check #1. Preinc'ing a frame index would require copying the stack pointer
5253 // (plus the implicit offset) to a register to preinc anyway.
5254 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
5259 SDValue Val = cast<StoreSDNode>(N)->getValue();
5260 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
5264 // Now check for #3 and #4.
5265 bool RealUse = false;
5266 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
5267 E = Ptr.getNode()->use_end(); I != E; ++I) {
5271 if (Use->isPredecessorOf(N))
5274 if (!((Use->getOpcode() == ISD::LOAD &&
5275 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
5276 (Use->getOpcode() == ISD::STORE &&
5277 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
5286 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
5287 BasePtr, Offset, AM);
5289 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
5290 BasePtr, Offset, AM);
5293 DEBUG(dbgs() << "\nReplacing.4 ";
5295 dbgs() << "\nWith: ";
5296 Result.getNode()->dump(&DAG);
5298 WorkListRemover DeadNodes(*this);
5300 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
5302 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
5305 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
5309 // Finally, since the node is now dead, remove it from the graph.
5312 // Replace the uses of Ptr with uses of the updated base value.
5313 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
5315 removeFromWorkList(Ptr.getNode());
5316 DAG.DeleteNode(Ptr.getNode());
5321 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
5322 /// add / sub of the base pointer node into a post-indexed load / store.
5323 /// The transformation folded the add / subtract into the new indexed
5324 /// load / store effectively and all of its uses are redirected to the
5325 /// new load / store.
5326 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
5327 if (!LegalOperations)
5333 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5334 if (LD->isIndexed())
5336 VT = LD->getMemoryVT();
5337 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
5338 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
5340 Ptr = LD->getBasePtr();
5341 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5342 if (ST->isIndexed())
5344 VT = ST->getMemoryVT();
5345 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
5346 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
5348 Ptr = ST->getBasePtr();
5354 if (Ptr.getNode()->hasOneUse())
5357 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
5358 E = Ptr.getNode()->use_end(); I != E; ++I) {
5361 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
5366 ISD::MemIndexedMode AM = ISD::UNINDEXED;
5367 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
5368 // Don't create a indexed load / store with zero offset.
5369 if (isa<ConstantSDNode>(Offset) &&
5370 cast<ConstantSDNode>(Offset)->isNullValue())
5373 // Try turning it into a post-indexed load / store except when
5374 // 1) All uses are load / store ops that use it as base ptr.
5375 // 2) Op must be independent of N, i.e. Op is neither a predecessor
5376 // nor a successor of N. Otherwise, if Op is folded that would
5379 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
5383 bool TryNext = false;
5384 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
5385 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
5387 if (Use == Ptr.getNode())
5390 // If all the uses are load / store addresses, then don't do the
5392 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
5393 bool RealUse = false;
5394 for (SDNode::use_iterator III = Use->use_begin(),
5395 EEE = Use->use_end(); III != EEE; ++III) {
5396 SDNode *UseUse = *III;
5397 if (!((UseUse->getOpcode() == ISD::LOAD &&
5398 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) ||
5399 (UseUse->getOpcode() == ISD::STORE &&
5400 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use)))
5415 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
5416 SDValue Result = isLoad
5417 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
5418 BasePtr, Offset, AM)
5419 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
5420 BasePtr, Offset, AM);
5423 DEBUG(dbgs() << "\nReplacing.5 ";
5425 dbgs() << "\nWith: ";
5426 Result.getNode()->dump(&DAG);
5428 WorkListRemover DeadNodes(*this);
5430 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
5432 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
5435 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
5439 // Finally, since the node is now dead, remove it from the graph.
5442 // Replace the uses of Use with uses of the updated base value.
5443 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
5444 Result.getValue(isLoad ? 1 : 0),
5446 removeFromWorkList(Op);
5456 SDValue DAGCombiner::visitLOAD(SDNode *N) {
5457 LoadSDNode *LD = cast<LoadSDNode>(N);
5458 SDValue Chain = LD->getChain();
5459 SDValue Ptr = LD->getBasePtr();
5461 // If load is not volatile and there are no uses of the loaded value (and
5462 // the updated indexed value in case of indexed loads), change uses of the
5463 // chain value into uses of the chain input (i.e. delete the dead load).
5464 if (!LD->isVolatile()) {
5465 if (N->getValueType(1) == MVT::Other) {
5467 if (N->hasNUsesOfValue(0, 0)) {
5468 // It's not safe to use the two value CombineTo variant here. e.g.
5469 // v1, chain2 = load chain1, loc
5470 // v2, chain3 = load chain2, loc
5472 // Now we replace use of chain2 with chain1. This makes the second load
5473 // isomorphic to the one we are deleting, and thus makes this load live.
5474 DEBUG(dbgs() << "\nReplacing.6 ";
5476 dbgs() << "\nWith chain: ";
5477 Chain.getNode()->dump(&DAG);
5479 WorkListRemover DeadNodes(*this);
5480 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
5482 if (N->use_empty()) {
5483 removeFromWorkList(N);
5487 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5491 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
5492 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
5493 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
5494 DEBUG(dbgs() << "\nReplacing.7 ";
5496 dbgs() << "\nWith: ";
5497 Undef.getNode()->dump(&DAG);
5498 dbgs() << " and 2 other values\n");
5499 WorkListRemover DeadNodes(*this);
5500 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
5501 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
5502 DAG.getUNDEF(N->getValueType(1)),
5504 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
5505 removeFromWorkList(N);
5507 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5512 // If this load is directly stored, replace the load value with the stored
5514 // TODO: Handle store large -> read small portion.
5515 // TODO: Handle TRUNCSTORE/LOADEXT
5516 if (LD->getExtensionType() == ISD::NON_EXTLOAD &&
5517 !LD->isVolatile()) {
5518 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
5519 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
5520 if (PrevST->getBasePtr() == Ptr &&
5521 PrevST->getValue().getValueType() == N->getValueType(0))
5522 return CombineTo(N, Chain.getOperand(1), Chain);
5526 // Try to infer better alignment information than the load already has.
5527 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
5528 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
5529 if (Align > LD->getAlignment())
5530 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
5531 LD->getValueType(0),
5532 Chain, Ptr, LD->getSrcValue(),
5533 LD->getSrcValueOffset(), LD->getMemoryVT(),
5534 LD->isVolatile(), LD->isNonTemporal(), Align);
5539 // Walk up chain skipping non-aliasing memory nodes.
5540 SDValue BetterChain = FindBetterChain(N, Chain);
5542 // If there is a better chain.
5543 if (Chain != BetterChain) {
5546 // Replace the chain to void dependency.
5547 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
5548 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
5550 LD->getSrcValue(), LD->getSrcValueOffset(),
5551 LD->isVolatile(), LD->isNonTemporal(),
5552 LD->getAlignment());
5554 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
5555 LD->getValueType(0),
5556 BetterChain, Ptr, LD->getSrcValue(),
5557 LD->getSrcValueOffset(),
5560 LD->isNonTemporal(),
5561 LD->getAlignment());
5564 // Create token factor to keep old chain connected.
5565 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
5566 MVT::Other, Chain, ReplLoad.getValue(1));
5568 // Make sure the new and old chains are cleaned up.
5569 AddToWorkList(Token.getNode());
5571 // Replace uses with load result and token factor. Don't add users
5573 return CombineTo(N, ReplLoad.getValue(0), Token, false);
5577 // Try transforming N to an indexed load.
5578 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
5579 return SDValue(N, 0);
5584 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
5585 /// load is having specific bytes cleared out. If so, return the byte size
5586 /// being masked out and the shift amount.
5587 static std::pair<unsigned, unsigned>
5588 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
5589 std::pair<unsigned, unsigned> Result(0, 0);
5591 // Check for the structure we're looking for.
5592 if (V->getOpcode() != ISD::AND ||
5593 !isa<ConstantSDNode>(V->getOperand(1)) ||
5594 !ISD::isNormalLoad(V->getOperand(0).getNode()))
5597 // Check the chain and pointer.
5598 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
5599 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
5601 // The store should be chained directly to the load or be an operand of a
5603 if (LD == Chain.getNode())
5605 else if (Chain->getOpcode() != ISD::TokenFactor)
5606 return Result; // Fail.
5609 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
5610 if (Chain->getOperand(i).getNode() == LD) {
5614 if (!isOk) return Result;
5617 // This only handles simple types.
5618 if (V.getValueType() != MVT::i16 &&
5619 V.getValueType() != MVT::i32 &&
5620 V.getValueType() != MVT::i64)
5623 // Check the constant mask. Invert it so that the bits being masked out are
5624 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
5625 // follow the sign bit for uniformity.
5626 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
5627 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask);
5628 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
5629 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask);
5630 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
5631 if (NotMaskLZ == 64) return Result; // All zero mask.
5633 // See if we have a continuous run of bits. If so, we have 0*1+0*
5634 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
5637 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
5638 if (V.getValueType() != MVT::i64 && NotMaskLZ)
5639 NotMaskLZ -= 64-V.getValueSizeInBits();
5641 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
5642 switch (MaskedBytes) {
5646 default: return Result; // All one mask, or 5-byte mask.
5649 // Verify that the first bit starts at a multiple of mask so that the access
5650 // is aligned the same as the access width.
5651 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
5653 Result.first = MaskedBytes;
5654 Result.second = NotMaskTZ/8;
5659 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
5660 /// provides a value as specified by MaskInfo. If so, replace the specified
5661 /// store with a narrower store of truncated IVal.
5663 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
5664 SDValue IVal, StoreSDNode *St,
5666 unsigned NumBytes = MaskInfo.first;
5667 unsigned ByteShift = MaskInfo.second;
5668 SelectionDAG &DAG = DC->getDAG();
5670 // Check to see if IVal is all zeros in the part being masked in by the 'or'
5671 // that uses this. If not, this is not a replacement.
5672 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
5673 ByteShift*8, (ByteShift+NumBytes)*8);
5674 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
5676 // Check that it is legal on the target to do this. It is legal if the new
5677 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
5679 MVT VT = MVT::getIntegerVT(NumBytes*8);
5680 if (!DC->isTypeLegal(VT))
5683 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
5684 // shifted by ByteShift and truncated down to NumBytes.
5686 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
5687 DAG.getConstant(ByteShift*8, DC->getShiftAmountTy()));
5689 // Figure out the offset for the store and the alignment of the access.
5691 unsigned NewAlign = St->getAlignment();
5693 if (DAG.getTargetLoweringInfo().isLittleEndian())
5694 StOffset = ByteShift;
5696 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
5698 SDValue Ptr = St->getBasePtr();
5700 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
5701 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
5702 NewAlign = MinAlign(NewAlign, StOffset);
5705 // Truncate down to the new size.
5706 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
5709 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr,
5710 St->getSrcValue(), St->getSrcValueOffset()+StOffset,
5711 false, false, NewAlign).getNode();
5715 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
5716 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
5717 /// of the loaded bits, try narrowing the load and store if it would end up
5718 /// being a win for performance or code size.
5719 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
5720 StoreSDNode *ST = cast<StoreSDNode>(N);
5721 if (ST->isVolatile())
5724 SDValue Chain = ST->getChain();
5725 SDValue Value = ST->getValue();
5726 SDValue Ptr = ST->getBasePtr();
5727 EVT VT = Value.getValueType();
5729 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
5732 unsigned Opc = Value.getOpcode();
5734 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
5735 // is a byte mask indicating a consecutive number of bytes, check to see if
5736 // Y is known to provide just those bytes. If so, we try to replace the
5737 // load + replace + store sequence with a single (narrower) store, which makes
5739 if (Opc == ISD::OR) {
5740 std::pair<unsigned, unsigned> MaskedLoad;
5741 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
5742 if (MaskedLoad.first)
5743 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
5744 Value.getOperand(1), ST,this))
5745 return SDValue(NewST, 0);
5747 // Or is commutative, so try swapping X and Y.
5748 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
5749 if (MaskedLoad.first)
5750 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
5751 Value.getOperand(0), ST,this))
5752 return SDValue(NewST, 0);
5755 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
5756 Value.getOperand(1).getOpcode() != ISD::Constant)
5759 SDValue N0 = Value.getOperand(0);
5760 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) {
5761 LoadSDNode *LD = cast<LoadSDNode>(N0);
5762 if (LD->getBasePtr() != Ptr)
5765 // Find the type to narrow it the load / op / store to.
5766 SDValue N1 = Value.getOperand(1);
5767 unsigned BitWidth = N1.getValueSizeInBits();
5768 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
5769 if (Opc == ISD::AND)
5770 Imm ^= APInt::getAllOnesValue(BitWidth);
5771 if (Imm == 0 || Imm.isAllOnesValue())
5773 unsigned ShAmt = Imm.countTrailingZeros();
5774 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
5775 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
5776 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
5777 while (NewBW < BitWidth &&
5778 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
5779 TLI.isNarrowingProfitable(VT, NewVT))) {
5780 NewBW = NextPowerOf2(NewBW);
5781 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
5783 if (NewBW >= BitWidth)
5786 // If the lsb changed does not start at the type bitwidth boundary,
5787 // start at the previous one.
5789 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
5790 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
5791 if ((Imm & Mask) == Imm) {
5792 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
5793 if (Opc == ISD::AND)
5794 NewImm ^= APInt::getAllOnesValue(NewBW);
5795 uint64_t PtrOff = ShAmt / 8;
5796 // For big endian targets, we need to adjust the offset to the pointer to
5797 // load the correct bytes.
5798 if (TLI.isBigEndian())
5799 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
5801 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
5802 const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
5803 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy))
5806 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
5807 Ptr.getValueType(), Ptr,
5808 DAG.getConstant(PtrOff, Ptr.getValueType()));
5809 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
5810 LD->getChain(), NewPtr,
5811 LD->getSrcValue(), LD->getSrcValueOffset(),
5812 LD->isVolatile(), LD->isNonTemporal(),
5814 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
5815 DAG.getConstant(NewImm, NewVT));
5816 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
5818 ST->getSrcValue(), ST->getSrcValueOffset(),
5819 false, false, NewAlign);
5821 AddToWorkList(NewPtr.getNode());
5822 AddToWorkList(NewLD.getNode());
5823 AddToWorkList(NewVal.getNode());
5824 WorkListRemover DeadNodes(*this);
5825 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1),
5835 SDValue DAGCombiner::visitSTORE(SDNode *N) {
5836 StoreSDNode *ST = cast<StoreSDNode>(N);
5837 SDValue Chain = ST->getChain();
5838 SDValue Value = ST->getValue();
5839 SDValue Ptr = ST->getBasePtr();
5841 // If this is a store of a bit convert, store the input value if the
5842 // resultant store does not need a higher alignment than the original.
5843 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
5844 ST->isUnindexed()) {
5845 unsigned OrigAlign = ST->getAlignment();
5846 EVT SVT = Value.getOperand(0).getValueType();
5847 unsigned Align = TLI.getTargetData()->
5848 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
5849 if (Align <= OrigAlign &&
5850 ((!LegalOperations && !ST->isVolatile()) ||
5851 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
5852 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
5853 Ptr, ST->getSrcValue(),
5854 ST->getSrcValueOffset(), ST->isVolatile(),
5855 ST->isNonTemporal(), OrigAlign);
5858 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
5859 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
5860 // NOTE: If the original store is volatile, this transform must not increase
5861 // the number of stores. For example, on x86-32 an f64 can be stored in one
5862 // processor operation but an i64 (which is not legal) requires two. So the
5863 // transform should not be done in this case.
5864 if (Value.getOpcode() != ISD::TargetConstantFP) {
5866 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
5867 default: llvm_unreachable("Unknown FP type");
5868 case MVT::f80: // We don't do this for these yet.
5873 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
5874 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
5875 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
5876 bitcastToAPInt().getZExtValue(), MVT::i32);
5877 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
5878 Ptr, ST->getSrcValue(),
5879 ST->getSrcValueOffset(), ST->isVolatile(),
5880 ST->isNonTemporal(), ST->getAlignment());
5884 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
5885 !ST->isVolatile()) ||
5886 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
5887 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
5888 getZExtValue(), MVT::i64);
5889 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
5890 Ptr, ST->getSrcValue(),
5891 ST->getSrcValueOffset(), ST->isVolatile(),
5892 ST->isNonTemporal(), ST->getAlignment());
5893 } else if (!ST->isVolatile() &&
5894 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
5895 // Many FP stores are not made apparent until after legalize, e.g. for
5896 // argument passing. Since this is so common, custom legalize the
5897 // 64-bit integer store into two 32-bit stores.
5898 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
5899 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
5900 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
5901 if (TLI.isBigEndian()) std::swap(Lo, Hi);
5903 int SVOffset = ST->getSrcValueOffset();
5904 unsigned Alignment = ST->getAlignment();
5905 bool isVolatile = ST->isVolatile();
5906 bool isNonTemporal = ST->isNonTemporal();
5908 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
5909 Ptr, ST->getSrcValue(),
5910 ST->getSrcValueOffset(),
5911 isVolatile, isNonTemporal,
5912 ST->getAlignment());
5913 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
5914 DAG.getConstant(4, Ptr.getValueType()));
5916 Alignment = MinAlign(Alignment, 4U);
5917 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
5918 Ptr, ST->getSrcValue(),
5919 SVOffset, isVolatile, isNonTemporal,
5921 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
5930 // Try to infer better alignment information than the store already has.
5931 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
5932 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
5933 if (Align > ST->getAlignment())
5934 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
5935 Ptr, ST->getSrcValue(),
5936 ST->getSrcValueOffset(), ST->getMemoryVT(),
5937 ST->isVolatile(), ST->isNonTemporal(), Align);
5942 // Walk up chain skipping non-aliasing memory nodes.
5943 SDValue BetterChain = FindBetterChain(N, Chain);
5945 // If there is a better chain.
5946 if (Chain != BetterChain) {
5949 // Replace the chain to avoid dependency.
5950 if (ST->isTruncatingStore()) {
5951 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
5952 ST->getSrcValue(),ST->getSrcValueOffset(),
5953 ST->getMemoryVT(), ST->isVolatile(),
5954 ST->isNonTemporal(), ST->getAlignment());
5956 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
5957 ST->getSrcValue(), ST->getSrcValueOffset(),
5958 ST->isVolatile(), ST->isNonTemporal(),
5959 ST->getAlignment());
5962 // Create token to keep both nodes around.
5963 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
5964 MVT::Other, Chain, ReplStore);
5966 // Make sure the new and old chains are cleaned up.
5967 AddToWorkList(Token.getNode());
5969 // Don't add users to work list.
5970 return CombineTo(N, Token, false);
5974 // Try transforming N to an indexed store.
5975 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
5976 return SDValue(N, 0);
5978 // FIXME: is there such a thing as a truncating indexed store?
5979 if (ST->isTruncatingStore() && ST->isUnindexed() &&
5980 Value.getValueType().isInteger()) {
5981 // See if we can simplify the input to this truncstore with knowledge that
5982 // only the low bits are being used. For example:
5983 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
5985 GetDemandedBits(Value,
5986 APInt::getLowBitsSet(Value.getValueSizeInBits(),
5987 ST->getMemoryVT().getSizeInBits()));
5988 AddToWorkList(Value.getNode());
5989 if (Shorter.getNode())
5990 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
5991 Ptr, ST->getSrcValue(),
5992 ST->getSrcValueOffset(), ST->getMemoryVT(),
5993 ST->isVolatile(), ST->isNonTemporal(),
5994 ST->getAlignment());
5996 // Otherwise, see if we can simplify the operation with
5997 // SimplifyDemandedBits, which only works if the value has a single use.
5998 if (SimplifyDemandedBits(Value,
5999 APInt::getLowBitsSet(
6000 Value.getValueType().getScalarType().getSizeInBits(),
6001 ST->getMemoryVT().getScalarType().getSizeInBits())))
6002 return SDValue(N, 0);
6005 // If this is a load followed by a store to the same location, then the store
6007 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
6008 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
6009 ST->isUnindexed() && !ST->isVolatile() &&
6010 // There can't be any side effects between the load and store, such as
6012 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
6013 // The store is dead, remove it.
6018 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
6019 // truncating store. We can do this even if this is already a truncstore.
6020 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
6021 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
6022 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
6023 ST->getMemoryVT())) {
6024 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
6025 Ptr, ST->getSrcValue(),
6026 ST->getSrcValueOffset(), ST->getMemoryVT(),
6027 ST->isVolatile(), ST->isNonTemporal(),
6028 ST->getAlignment());
6031 return ReduceLoadOpStoreWidth(N);
6034 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
6035 SDValue InVec = N->getOperand(0);
6036 SDValue InVal = N->getOperand(1);
6037 SDValue EltNo = N->getOperand(2);
6039 // If the inserted element is an UNDEF, just use the input vector.
6040 if (InVal.getOpcode() == ISD::UNDEF)
6043 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
6044 // vector with the inserted element.
6045 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
6046 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6047 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
6048 InVec.getNode()->op_end());
6049 if (Elt < Ops.size())
6051 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6052 InVec.getValueType(), &Ops[0], Ops.size());
6054 // If the invec is an UNDEF and if EltNo is a constant, create a new
6055 // BUILD_VECTOR with undef elements and the inserted element.
6056 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF &&
6057 isa<ConstantSDNode>(EltNo)) {
6058 EVT VT = InVec.getValueType();
6059 EVT EltVT = VT.getVectorElementType();
6060 unsigned NElts = VT.getVectorNumElements();
6061 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT));
6063 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6064 if (Elt < Ops.size())
6066 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6067 InVec.getValueType(), &Ops[0], Ops.size());
6072 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
6073 // (vextract (scalar_to_vector val, 0) -> val
6074 SDValue InVec = N->getOperand(0);
6076 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
6077 // Check if the result type doesn't match the inserted element type. A
6078 // SCALAR_TO_VECTOR may truncate the inserted element and the
6079 // EXTRACT_VECTOR_ELT may widen the extracted vector.
6080 EVT EltVT = InVec.getValueType().getVectorElementType();
6081 SDValue InOp = InVec.getOperand(0);
6082 EVT NVT = N->getValueType(0);
6083 if (InOp.getValueType() != NVT) {
6084 assert(InOp.getValueType().isInteger() && NVT.isInteger());
6085 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
6090 // Perform only after legalization to ensure build_vector / vector_shuffle
6091 // optimizations have already been done.
6092 if (!LegalOperations) return SDValue();
6094 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
6095 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
6096 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
6097 SDValue EltNo = N->getOperand(1);
6099 if (isa<ConstantSDNode>(EltNo)) {
6100 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6101 bool NewLoad = false;
6102 bool BCNumEltsChanged = false;
6103 EVT VT = InVec.getValueType();
6104 EVT ExtVT = VT.getVectorElementType();
6107 if (InVec.getOpcode() == ISD::BIT_CONVERT) {
6108 EVT BCVT = InVec.getOperand(0).getValueType();
6109 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
6111 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
6112 BCNumEltsChanged = true;
6113 InVec = InVec.getOperand(0);
6114 ExtVT = BCVT.getVectorElementType();
6118 LoadSDNode *LN0 = NULL;
6119 const ShuffleVectorSDNode *SVN = NULL;
6120 if (ISD::isNormalLoad(InVec.getNode())) {
6121 LN0 = cast<LoadSDNode>(InVec);
6122 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6123 InVec.getOperand(0).getValueType() == ExtVT &&
6124 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
6125 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
6126 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
6127 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
6129 // (load $addr+1*size)
6131 // If the bit convert changed the number of elements, it is unsafe
6132 // to examine the mask.
6133 if (BCNumEltsChanged)
6136 // Select the input vector, guarding against out of range extract vector.
6137 unsigned NumElems = VT.getVectorNumElements();
6138 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt);
6139 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
6141 if (InVec.getOpcode() == ISD::BIT_CONVERT)
6142 InVec = InVec.getOperand(0);
6143 if (ISD::isNormalLoad(InVec.getNode())) {
6144 LN0 = cast<LoadSDNode>(InVec);
6145 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
6149 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile())
6152 unsigned Align = LN0->getAlignment();
6154 // Check the resultant load doesn't need a higher alignment than the
6157 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
6159 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
6165 SDValue NewPtr = LN0->getBasePtr();
6167 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8;
6168 EVT PtrType = NewPtr.getValueType();
6169 if (TLI.isBigEndian())
6170 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
6171 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
6172 DAG.getConstant(PtrOff, PtrType));
6175 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
6176 LN0->getSrcValue(), LN0->getSrcValueOffset(),
6177 LN0->isVolatile(), LN0->isNonTemporal(), Align);
6183 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
6184 unsigned NumInScalars = N->getNumOperands();
6185 EVT VT = N->getValueType(0);
6187 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
6188 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
6189 // at most two distinct vectors, turn this into a shuffle node.
6190 SDValue VecIn1, VecIn2;
6191 for (unsigned i = 0; i != NumInScalars; ++i) {
6192 // Ignore undef inputs.
6193 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6195 // If this input is something other than a EXTRACT_VECTOR_ELT with a
6196 // constant index, bail out.
6197 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6198 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
6199 VecIn1 = VecIn2 = SDValue(0, 0);
6203 // If the input vector type disagrees with the result of the build_vector,
6204 // we can't make a shuffle.
6205 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
6206 if (ExtractedFromVec.getValueType() != VT) {
6207 VecIn1 = VecIn2 = SDValue(0, 0);
6211 // Otherwise, remember this. We allow up to two distinct input vectors.
6212 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
6215 if (VecIn1.getNode() == 0) {
6216 VecIn1 = ExtractedFromVec;
6217 } else if (VecIn2.getNode() == 0) {
6218 VecIn2 = ExtractedFromVec;
6221 VecIn1 = VecIn2 = SDValue(0, 0);
6226 // If everything is good, we can make a shuffle operation.
6227 if (VecIn1.getNode()) {
6228 SmallVector<int, 8> Mask;
6229 for (unsigned i = 0; i != NumInScalars; ++i) {
6230 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
6235 // If extracting from the first vector, just use the index directly.
6236 SDValue Extract = N->getOperand(i);
6237 SDValue ExtVal = Extract.getOperand(1);
6238 if (Extract.getOperand(0) == VecIn1) {
6239 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
6240 if (ExtIndex > VT.getVectorNumElements())
6243 Mask.push_back(ExtIndex);
6247 // Otherwise, use InIdx + VecSize
6248 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
6249 Mask.push_back(Idx+NumInScalars);
6252 // Add count and size info.
6253 if (!isTypeLegal(VT))
6256 // Return the new VECTOR_SHUFFLE node.
6259 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6260 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
6266 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
6267 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
6268 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
6269 // inputs come from at most two distinct vectors, turn this into a shuffle
6272 // If we only have one input vector, we don't need to do any concatenation.
6273 if (N->getNumOperands() == 1)
6274 return N->getOperand(0);
6279 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
6282 EVT VT = N->getValueType(0);
6283 unsigned NumElts = VT.getVectorNumElements();
6285 SDValue N0 = N->getOperand(0);
6287 assert(N0.getValueType().getVectorNumElements() == NumElts &&
6288 "Vector shuffle must be normalized in DAG");
6290 // FIXME: implement canonicalizations from DAG.getVectorShuffle()
6292 // If it is a splat, check if the argument vector is a build_vector with
6293 // all scalar elements the same.
6294 if (cast<ShuffleVectorSDNode>(N)->isSplat()) {
6295 SDNode *V = N0.getNode();
6297 // If this is a bit convert that changes the element type of the vector but
6298 // not the number of vector elements, look through it. Be careful not to
6299 // look though conversions that change things like v4f32 to v2f64.
6300 if (V->getOpcode() == ISD::BIT_CONVERT) {
6301 SDValue ConvInput = V->getOperand(0);
6302 if (ConvInput.getValueType().isVector() &&
6303 ConvInput.getValueType().getVectorNumElements() == NumElts)
6304 V = ConvInput.getNode();
6307 if (V->getOpcode() == ISD::BUILD_VECTOR) {
6308 unsigned NumElems = V->getNumOperands();
6309 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex();
6310 if (NumElems > BaseIdx) {
6312 bool AllSame = true;
6313 for (unsigned i = 0; i != NumElems; ++i) {
6314 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
6315 Base = V->getOperand(i);
6319 // Splat of <u, u, u, u>, return <u, u, u, u>
6320 if (!Base.getNode())
6322 for (unsigned i = 0; i != NumElems; ++i) {
6323 if (V->getOperand(i) != Base) {
6328 // Splat of <x, x, x, x>, return <x, x, x, x>
6337 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
6338 /// an AND to a vector_shuffle with the destination vector and a zero vector.
6339 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
6340 /// vector_shuffle V, Zero, <0, 4, 2, 4>
6341 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
6342 EVT VT = N->getValueType(0);
6343 DebugLoc dl = N->getDebugLoc();
6344 SDValue LHS = N->getOperand(0);
6345 SDValue RHS = N->getOperand(1);
6346 if (N->getOpcode() == ISD::AND) {
6347 if (RHS.getOpcode() == ISD::BIT_CONVERT)
6348 RHS = RHS.getOperand(0);
6349 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
6350 SmallVector<int, 8> Indices;
6351 unsigned NumElts = RHS.getNumOperands();
6352 for (unsigned i = 0; i != NumElts; ++i) {
6353 SDValue Elt = RHS.getOperand(i);
6354 if (!isa<ConstantSDNode>(Elt))
6356 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
6357 Indices.push_back(i);
6358 else if (cast<ConstantSDNode>(Elt)->isNullValue())
6359 Indices.push_back(NumElts);
6364 // Let's see if the target supports this vector_shuffle.
6365 EVT RVT = RHS.getValueType();
6366 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
6369 // Return the new VECTOR_SHUFFLE node.
6370 EVT EltVT = RVT.getVectorElementType();
6371 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
6372 DAG.getConstant(0, EltVT));
6373 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6374 RVT, &ZeroOps[0], ZeroOps.size());
6375 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS);
6376 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
6377 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf);
6384 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
6385 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
6386 // After legalize, the target may be depending on adds and other
6387 // binary ops to provide legal ways to construct constants or other
6388 // things. Simplifying them may result in a loss of legality.
6389 if (LegalOperations) return SDValue();
6391 EVT VT = N->getValueType(0);
6392 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!");
6394 EVT EltType = VT.getVectorElementType();
6395 SDValue LHS = N->getOperand(0);
6396 SDValue RHS = N->getOperand(1);
6397 SDValue Shuffle = XformToShuffleWithZero(N);
6398 if (Shuffle.getNode()) return Shuffle;
6400 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
6402 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
6403 RHS.getOpcode() == ISD::BUILD_VECTOR) {
6404 SmallVector<SDValue, 8> Ops;
6405 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
6406 SDValue LHSOp = LHS.getOperand(i);
6407 SDValue RHSOp = RHS.getOperand(i);
6408 // If these two elements can't be folded, bail out.
6409 if ((LHSOp.getOpcode() != ISD::UNDEF &&
6410 LHSOp.getOpcode() != ISD::Constant &&
6411 LHSOp.getOpcode() != ISD::ConstantFP) ||
6412 (RHSOp.getOpcode() != ISD::UNDEF &&
6413 RHSOp.getOpcode() != ISD::Constant &&
6414 RHSOp.getOpcode() != ISD::ConstantFP))
6417 // Can't fold divide by zero.
6418 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
6419 N->getOpcode() == ISD::FDIV) {
6420 if ((RHSOp.getOpcode() == ISD::Constant &&
6421 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
6422 (RHSOp.getOpcode() == ISD::ConstantFP &&
6423 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
6427 // If the vector element type is not legal, the BUILD_VECTOR operands
6428 // are promoted and implicitly truncated. Make that explicit here.
6429 if (LHSOp.getValueType() != EltType)
6430 LHSOp = DAG.getNode(ISD::TRUNCATE, LHS.getDebugLoc(), EltType, LHSOp);
6431 if (RHSOp.getValueType() != EltType)
6432 RHSOp = DAG.getNode(ISD::TRUNCATE, RHS.getDebugLoc(), EltType, RHSOp);
6434 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), EltType,
6436 if (FoldOp.getOpcode() != ISD::UNDEF &&
6437 FoldOp.getOpcode() != ISD::Constant &&
6438 FoldOp.getOpcode() != ISD::ConstantFP)
6440 Ops.push_back(FoldOp);
6441 AddToWorkList(FoldOp.getNode());
6444 if (Ops.size() == LHS.getNumOperands()) {
6445 EVT VT = LHS.getValueType();
6446 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
6447 &Ops[0], Ops.size());
6454 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
6455 SDValue N1, SDValue N2){
6456 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
6458 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
6459 cast<CondCodeSDNode>(N0.getOperand(2))->get());
6461 // If we got a simplified select_cc node back from SimplifySelectCC, then
6462 // break it down into a new SETCC node, and a new SELECT node, and then return
6463 // the SELECT node, since we were called with a SELECT node.
6464 if (SCC.getNode()) {
6465 // Check to see if we got a select_cc back (to turn into setcc/select).
6466 // Otherwise, just return whatever node we got back, like fabs.
6467 if (SCC.getOpcode() == ISD::SELECT_CC) {
6468 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
6470 SCC.getOperand(0), SCC.getOperand(1),
6472 AddToWorkList(SETCC.getNode());
6473 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
6474 SCC.getOperand(2), SCC.getOperand(3), SETCC);
6482 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
6483 /// are the two values being selected between, see if we can simplify the
6484 /// select. Callers of this should assume that TheSelect is deleted if this
6485 /// returns true. As such, they should return the appropriate thing (e.g. the
6486 /// node) back to the top-level of the DAG combiner loop to avoid it being
6488 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
6491 // If this is a select from two identical things, try to pull the operation
6492 // through the select.
6493 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
6494 // If this is a load and the token chain is identical, replace the select
6495 // of two loads with a load through a select of the address to load from.
6496 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
6497 // constants have been dropped into the constant pool.
6498 if (LHS.getOpcode() == ISD::LOAD &&
6499 // Do not let this transformation reduce the number of volatile loads.
6500 !cast<LoadSDNode>(LHS)->isVolatile() &&
6501 !cast<LoadSDNode>(RHS)->isVolatile() &&
6502 // Token chains must be identical.
6503 LHS.getOperand(0) == RHS.getOperand(0)) {
6504 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
6505 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
6507 // If this is an EXTLOAD, the VT's must match.
6508 if (LLD->getMemoryVT() == RLD->getMemoryVT()) {
6509 // FIXME: this discards src value information. This is
6510 // over-conservative. It would be beneficial to be able to remember
6511 // both potential memory locations. Since we are discarding
6512 // src value info, don't do the transformation if the memory
6513 // locations are not in the default address space.
6514 unsigned LLDAddrSpace = 0, RLDAddrSpace = 0;
6515 if (const Value *LLDVal = LLD->getMemOperand()->getValue()) {
6516 if (const PointerType *PT = dyn_cast<PointerType>(LLDVal->getType()))
6517 LLDAddrSpace = PT->getAddressSpace();
6519 if (const Value *RLDVal = RLD->getMemOperand()->getValue()) {
6520 if (const PointerType *PT = dyn_cast<PointerType>(RLDVal->getType()))
6521 RLDAddrSpace = PT->getAddressSpace();
6524 if (LLDAddrSpace == 0 && RLDAddrSpace == 0) {
6525 if (TheSelect->getOpcode() == ISD::SELECT) {
6526 // Check that the condition doesn't reach either load. If so, folding
6527 // this will induce a cycle into the DAG.
6528 if ((!LLD->hasAnyUseOfValue(1) ||
6529 !LLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) &&
6530 (!RLD->hasAnyUseOfValue(1) ||
6531 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()))) {
6532 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
6533 LLD->getBasePtr().getValueType(),
6534 TheSelect->getOperand(0), LLD->getBasePtr(),
6538 // Check that the condition doesn't reach either load. If so, folding
6539 // this will induce a cycle into the DAG.
6540 if ((!LLD->hasAnyUseOfValue(1) ||
6541 (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
6542 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()))) &&
6543 (!RLD->hasAnyUseOfValue(1) ||
6544 (!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
6545 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())))) {
6546 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
6547 LLD->getBasePtr().getValueType(),
6548 TheSelect->getOperand(0),
6549 TheSelect->getOperand(1),
6550 LLD->getBasePtr(), RLD->getBasePtr(),
6551 TheSelect->getOperand(4));
6556 if (Addr.getNode()) {
6558 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
6559 Load = DAG.getLoad(TheSelect->getValueType(0),
6560 TheSelect->getDebugLoc(),
6564 LLD->isNonTemporal(),
6565 LLD->getAlignment());
6567 Load = DAG.getExtLoad(LLD->getExtensionType(),
6568 TheSelect->getDebugLoc(),
6569 TheSelect->getValueType(0),
6570 LLD->getChain(), Addr, 0, 0,
6573 LLD->isNonTemporal(),
6574 LLD->getAlignment());
6577 // Users of the select now use the result of the load.
6578 CombineTo(TheSelect, Load);
6580 // Users of the old loads now use the new load's chain. We know the
6581 // old-load value is dead now.
6582 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
6583 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
6593 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
6594 /// where 'cond' is the comparison specified by CC.
6595 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
6596 SDValue N2, SDValue N3,
6597 ISD::CondCode CC, bool NotExtCompare) {
6598 // (x ? y : y) -> y.
6599 if (N2 == N3) return N2;
6601 EVT VT = N2.getValueType();
6602 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
6603 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
6604 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
6606 // Determine if the condition we're dealing with is constant
6607 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
6608 N0, N1, CC, DL, false);
6609 if (SCC.getNode()) AddToWorkList(SCC.getNode());
6610 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
6612 // fold select_cc true, x, y -> x
6613 if (SCCC && !SCCC->isNullValue())
6615 // fold select_cc false, x, y -> y
6616 if (SCCC && SCCC->isNullValue())
6619 // Check to see if we can simplify the select into an fabs node
6620 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
6621 // Allow either -0.0 or 0.0
6622 if (CFP->getValueAPF().isZero()) {
6623 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
6624 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
6625 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
6626 N2 == N3.getOperand(0))
6627 return DAG.getNode(ISD::FABS, DL, VT, N0);
6629 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
6630 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
6631 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
6632 N2.getOperand(0) == N3)
6633 return DAG.getNode(ISD::FABS, DL, VT, N3);
6637 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
6638 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
6639 // in it. This is a win when the constant is not otherwise available because
6640 // it replaces two constant pool loads with one. We only do this if the FP
6641 // type is known to be legal, because if it isn't, then we are before legalize
6642 // types an we want the other legalization to happen first (e.g. to avoid
6643 // messing with soft float) and if the ConstantFP is not legal, because if
6644 // it is legal, we may not need to store the FP constant in a constant pool.
6645 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
6646 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
6647 if (TLI.isTypeLegal(N2.getValueType()) &&
6648 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
6649 TargetLowering::Legal) &&
6650 // If both constants have multiple uses, then we won't need to do an
6651 // extra load, they are likely around in registers for other users.
6652 (TV->hasOneUse() || FV->hasOneUse())) {
6653 Constant *Elts[] = {
6654 const_cast<ConstantFP*>(FV->getConstantFPValue()),
6655 const_cast<ConstantFP*>(TV->getConstantFPValue())
6657 const Type *FPTy = Elts[0]->getType();
6658 const TargetData &TD = *TLI.getTargetData();
6660 // Create a ConstantArray of the two constants.
6661 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2);
6662 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
6663 TD.getPrefTypeAlignment(FPTy));
6664 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6666 // Get the offsets to the 0 and 1 element of the array so that we can
6667 // select between them.
6668 SDValue Zero = DAG.getIntPtrConstant(0);
6669 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
6670 SDValue One = DAG.getIntPtrConstant(EltSize);
6672 SDValue Cond = DAG.getSetCC(DL,
6673 TLI.getSetCCResultType(N0.getValueType()),
6675 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
6677 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
6679 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
6680 PseudoSourceValue::getConstantPool(), 0, false,
6686 // Check to see if we can perform the "gzip trick", transforming
6687 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
6688 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
6689 N0.getValueType().isInteger() &&
6690 N2.getValueType().isInteger() &&
6691 (N1C->isNullValue() || // (a < 0) ? b : 0
6692 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
6693 EVT XType = N0.getValueType();
6694 EVT AType = N2.getValueType();
6695 if (XType.bitsGE(AType)) {
6696 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
6697 // single-bit constant.
6698 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
6699 unsigned ShCtV = N2C->getAPIntValue().logBase2();
6700 ShCtV = XType.getSizeInBits()-ShCtV-1;
6701 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy());
6702 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
6704 AddToWorkList(Shift.getNode());
6706 if (XType.bitsGT(AType)) {
6707 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
6708 AddToWorkList(Shift.getNode());
6711 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
6714 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
6716 DAG.getConstant(XType.getSizeInBits()-1,
6717 getShiftAmountTy()));
6718 AddToWorkList(Shift.getNode());
6720 if (XType.bitsGT(AType)) {
6721 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
6722 AddToWorkList(Shift.getNode());
6725 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
6729 // fold select C, 16, 0 -> shl C, 4
6730 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
6731 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {
6733 // If the caller doesn't want us to simplify this into a zext of a compare,
6735 if (NotExtCompare && N2C->getAPIntValue() == 1)
6738 // Get a SetCC of the condition
6739 // FIXME: Should probably make sure that setcc is legal if we ever have a
6740 // target where it isn't.
6742 // cast from setcc result type to select result type
6744 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
6746 if (N2.getValueType().bitsLT(SCC.getValueType()))
6747 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
6749 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
6750 N2.getValueType(), SCC);
6752 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
6753 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
6754 N2.getValueType(), SCC);
6757 AddToWorkList(SCC.getNode());
6758 AddToWorkList(Temp.getNode());
6760 if (N2C->getAPIntValue() == 1)
6763 // shl setcc result by log2 n2c
6764 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
6765 DAG.getConstant(N2C->getAPIntValue().logBase2(),
6766 getShiftAmountTy()));
6769 // Check to see if this is the equivalent of setcc
6770 // FIXME: Turn all of these into setcc if setcc if setcc is legal
6771 // otherwise, go ahead with the folds.
6772 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
6773 EVT XType = N0.getValueType();
6774 if (!LegalOperations ||
6775 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
6776 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
6777 if (Res.getValueType() != VT)
6778 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
6782 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
6783 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
6784 (!LegalOperations ||
6785 TLI.isOperationLegal(ISD::CTLZ, XType))) {
6786 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
6787 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
6788 DAG.getConstant(Log2_32(XType.getSizeInBits()),
6789 getShiftAmountTy()));
6791 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
6792 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
6793 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
6794 XType, DAG.getConstant(0, XType), N0);
6795 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
6796 return DAG.getNode(ISD::SRL, DL, XType,
6797 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
6798 DAG.getConstant(XType.getSizeInBits()-1,
6799 getShiftAmountTy()));
6801 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
6802 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
6803 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
6804 DAG.getConstant(XType.getSizeInBits()-1,
6805 getShiftAmountTy()));
6806 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
6810 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
6811 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
6812 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
6813 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
6814 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) {
6815 EVT XType = N0.getValueType();
6816 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0,
6817 DAG.getConstant(XType.getSizeInBits()-1,
6818 getShiftAmountTy()));
6819 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType,
6821 AddToWorkList(Shift.getNode());
6822 AddToWorkList(Add.getNode());
6823 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
6825 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
6826 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
6827 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
6828 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
6829 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
6830 EVT XType = N0.getValueType();
6831 if (SubC->isNullValue() && XType.isInteger()) {
6832 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
6834 DAG.getConstant(XType.getSizeInBits()-1,
6835 getShiftAmountTy()));
6836 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
6838 AddToWorkList(Shift.getNode());
6839 AddToWorkList(Add.getNode());
6840 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
6848 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
6849 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
6850 SDValue N1, ISD::CondCode Cond,
6851 DebugLoc DL, bool foldBooleans) {
6852 TargetLowering::DAGCombinerInfo
6853 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
6854 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
6857 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
6858 /// return a DAG expression to select that will generate the same value by
6859 /// multiplying by a magic number. See:
6860 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
6861 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
6862 std::vector<SDNode*> Built;
6863 SDValue S = TLI.BuildSDIV(N, DAG, &Built);
6865 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
6871 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
6872 /// return a DAG expression to select that will generate the same value by
6873 /// multiplying by a magic number. See:
6874 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
6875 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
6876 std::vector<SDNode*> Built;
6877 SDValue S = TLI.BuildUDIV(N, DAG, &Built);
6879 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
6885 /// FindBaseOffset - Return true if base is a frame index, which is known not
6886 // to alias with anything but itself. Provides base object and offset as results.
6887 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
6888 const GlobalValue *&GV, void *&CV) {
6889 // Assume it is a primitive operation.
6890 Base = Ptr; Offset = 0; GV = 0; CV = 0;
6892 // If it's an adding a simple constant then integrate the offset.
6893 if (Base.getOpcode() == ISD::ADD) {
6894 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
6895 Base = Base.getOperand(0);
6896 Offset += C->getZExtValue();
6900 // Return the underlying GlobalValue, and update the Offset. Return false
6901 // for GlobalAddressSDNode since the same GlobalAddress may be represented
6902 // by multiple nodes with different offsets.
6903 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
6904 GV = G->getGlobal();
6905 Offset += G->getOffset();
6909 // Return the underlying Constant value, and update the Offset. Return false
6910 // for ConstantSDNodes since the same constant pool entry may be represented
6911 // by multiple nodes with different offsets.
6912 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
6913 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal()
6914 : (void *)C->getConstVal();
6915 Offset += C->getOffset();
6918 // If it's any of the following then it can't alias with anything but itself.
6919 return isa<FrameIndexSDNode>(Base);
6922 /// isAlias - Return true if there is any possibility that the two addresses
6924 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
6925 const Value *SrcValue1, int SrcValueOffset1,
6926 unsigned SrcValueAlign1,
6927 SDValue Ptr2, int64_t Size2,
6928 const Value *SrcValue2, int SrcValueOffset2,
6929 unsigned SrcValueAlign2) const {
6930 // If they are the same then they must be aliases.
6931 if (Ptr1 == Ptr2) return true;
6933 // Gather base node and offset information.
6934 SDValue Base1, Base2;
6935 int64_t Offset1, Offset2;
6936 const GlobalValue *GV1, *GV2;
6938 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
6939 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
6941 // If they have a same base address then check to see if they overlap.
6942 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
6943 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
6945 // If we know what the bases are, and they aren't identical, then we know they
6947 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
6950 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
6951 // compared to the size and offset of the access, we may be able to prove they
6952 // do not alias. This check is conservative for now to catch cases created by
6953 // splitting vector types.
6954 if ((SrcValueAlign1 == SrcValueAlign2) &&
6955 (SrcValueOffset1 != SrcValueOffset2) &&
6956 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
6957 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
6958 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
6960 // There is no overlap between these relatively aligned accesses of similar
6961 // size, return no alias.
6962 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
6966 if (CombinerGlobalAA) {
6967 // Use alias analysis information.
6968 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
6969 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
6970 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
6971 AliasAnalysis::AliasResult AAResult =
6972 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
6973 if (AAResult == AliasAnalysis::NoAlias)
6977 // Otherwise we have to assume they alias.
6981 /// FindAliasInfo - Extracts the relevant alias information from the memory
6982 /// node. Returns true if the operand was a load.
6983 bool DAGCombiner::FindAliasInfo(SDNode *N,
6984 SDValue &Ptr, int64_t &Size,
6985 const Value *&SrcValue,
6986 int &SrcValueOffset,
6987 unsigned &SrcValueAlign) const {
6988 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6989 Ptr = LD->getBasePtr();
6990 Size = LD->getMemoryVT().getSizeInBits() >> 3;
6991 SrcValue = LD->getSrcValue();
6992 SrcValueOffset = LD->getSrcValueOffset();
6993 SrcValueAlign = LD->getOriginalAlignment();
6995 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6996 Ptr = ST->getBasePtr();
6997 Size = ST->getMemoryVT().getSizeInBits() >> 3;
6998 SrcValue = ST->getSrcValue();
6999 SrcValueOffset = ST->getSrcValueOffset();
7000 SrcValueAlign = ST->getOriginalAlignment();
7002 llvm_unreachable("FindAliasInfo expected a memory operand");
7008 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
7009 /// looking for aliasing nodes and adding them to the Aliases vector.
7010 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
7011 SmallVector<SDValue, 8> &Aliases) {
7012 SmallVector<SDValue, 8> Chains; // List of chains to visit.
7013 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
7015 // Get alias information for node.
7018 const Value *SrcValue;
7020 unsigned SrcValueAlign;
7021 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
7025 Chains.push_back(OriginalChain);
7028 // Look at each chain and determine if it is an alias. If so, add it to the
7029 // aliases list. If not, then continue up the chain looking for the next
7031 while (!Chains.empty()) {
7032 SDValue Chain = Chains.back();
7035 // For TokenFactor nodes, look at each operand and only continue up the
7036 // chain until we find two aliases. If we've seen two aliases, assume we'll
7037 // find more and revert to original chain since the xform is unlikely to be
7040 // FIXME: The depth check could be made to return the last non-aliasing
7041 // chain we found before we hit a tokenfactor rather than the original
7043 if (Depth > 6 || Aliases.size() == 2) {
7045 Aliases.push_back(OriginalChain);
7049 // Don't bother if we've been before.
7050 if (!Visited.insert(Chain.getNode()))
7053 switch (Chain.getOpcode()) {
7054 case ISD::EntryToken:
7055 // Entry token is ideal chain operand, but handled in FindBetterChain.
7060 // Get alias information for Chain.
7063 const Value *OpSrcValue;
7064 int OpSrcValueOffset;
7065 unsigned OpSrcValueAlign;
7066 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
7067 OpSrcValue, OpSrcValueOffset,
7070 // If chain is alias then stop here.
7071 if (!(IsLoad && IsOpLoad) &&
7072 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
7073 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
7075 Aliases.push_back(Chain);
7077 // Look further up the chain.
7078 Chains.push_back(Chain.getOperand(0));
7084 case ISD::TokenFactor:
7085 // We have to check each of the operands of the token factor for "small"
7086 // token factors, so we queue them up. Adding the operands to the queue
7087 // (stack) in reverse order maintains the original order and increases the
7088 // likelihood that getNode will find a matching token factor (CSE.)
7089 if (Chain.getNumOperands() > 16) {
7090 Aliases.push_back(Chain);
7093 for (unsigned n = Chain.getNumOperands(); n;)
7094 Chains.push_back(Chain.getOperand(--n));
7099 // For all other instructions we will just have to take what we can get.
7100 Aliases.push_back(Chain);
7106 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
7107 /// for a better chain (aliasing node.)
7108 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
7109 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
7111 // Accumulate all the aliases to this node.
7112 GatherAllAliases(N, OldChain, Aliases);
7114 if (Aliases.size() == 0) {
7115 // If no operands then chain to entry token.
7116 return DAG.getEntryNode();
7117 } else if (Aliases.size() == 1) {
7118 // If a single operand then chain to it. We don't need to revisit it.
7122 // Construct a custom tailored token factor.
7123 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
7124 &Aliases[0], Aliases.size());
7127 // SelectionDAG::Combine - This is the entry point for the file.
7129 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
7130 CodeGenOpt::Level OptLevel) {
7131 /// run - This is the main entry point to this class.
7133 DAGCombiner(*this, AA, OptLevel).Run(Level);