1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: Should add a corresponding version of fold AND with
20 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which
23 // FIXME: select C, pow2, pow2 -> something smart
24 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
25 // FIXME: Dead stores -> nuke
26 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
27 // FIXME: mul (x, const) -> shifts + adds
28 // FIXME: undef values
29 // FIXME: make truncate see through SIGN_EXTEND and AND
30 // FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2)
31 // FIXME: verify that getNode can't return extends with an operand whose type
32 // is >= to that of the extend.
33 // FIXME: divide by zero is currently left unfolded. do we want to turn this
35 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
36 // FIXME: reassociate (X+C)+Y into (X+Y)+C if the inner expression has one use
38 //===----------------------------------------------------------------------===//
40 #define DEBUG_TYPE "dagcombine"
41 #include "llvm/ADT/Statistic.h"
42 #include "llvm/CodeGen/SelectionDAG.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Target/TargetLowering.h"
51 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined");
58 // Worklist of all of the nodes that need to be simplified.
59 std::vector<SDNode*> WorkList;
61 /// AddUsersToWorkList - When an instruction is simplified, add all users of
62 /// the instruction to the work lists because they might get more simplified
65 void AddUsersToWorkList(SDNode *N) {
66 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
68 WorkList.push_back(*UI);
71 /// removeFromWorkList - remove all instances of N from the worklist.
72 void removeFromWorkList(SDNode *N) {
73 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
77 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
79 DEBUG(std::cerr << "\nReplacing "; N->dump();
80 std::cerr << "\nWith: "; To[0].Val->dump();
81 std::cerr << " and " << To.size()-1 << " other values\n");
82 std::vector<SDNode*> NowDead;
83 DAG.ReplaceAllUsesWith(N, To, &NowDead);
85 // Push the new nodes and any users onto the worklist
86 for (unsigned i = 0, e = To.size(); i != e; ++i) {
87 WorkList.push_back(To[i].Val);
88 AddUsersToWorkList(To[i].Val);
91 // Nodes can end up on the worklist more than once. Make sure we do
92 // not process a node that has been replaced.
93 removeFromWorkList(N);
94 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
95 removeFromWorkList(NowDead[i]);
97 // Finally, since the node is now dead, remove it from the graph.
99 return SDOperand(N, 0);
102 SDOperand CombineTo(SDNode *N, SDOperand Res) {
103 std::vector<SDOperand> To;
105 return CombineTo(N, To);
108 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
109 std::vector<SDOperand> To;
112 return CombineTo(N, To);
115 /// visit - call the node-specific routine that knows how to fold each
116 /// particular type of node.
117 SDOperand visit(SDNode *N);
119 // Visitation implementation - Implement dag node combining for different
120 // node types. The semantics are as follows:
122 // SDOperand.Val == 0 - No change was made
123 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
124 // otherwise - N should be replaced by the returned Operand.
126 SDOperand visitTokenFactor(SDNode *N);
127 SDOperand visitADD(SDNode *N);
128 SDOperand visitSUB(SDNode *N);
129 SDOperand visitMUL(SDNode *N);
130 SDOperand visitSDIV(SDNode *N);
131 SDOperand visitUDIV(SDNode *N);
132 SDOperand visitSREM(SDNode *N);
133 SDOperand visitUREM(SDNode *N);
134 SDOperand visitMULHU(SDNode *N);
135 SDOperand visitMULHS(SDNode *N);
136 SDOperand visitAND(SDNode *N);
137 SDOperand visitOR(SDNode *N);
138 SDOperand visitXOR(SDNode *N);
139 SDOperand visitSHL(SDNode *N);
140 SDOperand visitSRA(SDNode *N);
141 SDOperand visitSRL(SDNode *N);
142 SDOperand visitCTLZ(SDNode *N);
143 SDOperand visitCTTZ(SDNode *N);
144 SDOperand visitCTPOP(SDNode *N);
145 SDOperand visitSELECT(SDNode *N);
146 SDOperand visitSELECT_CC(SDNode *N);
147 SDOperand visitSETCC(SDNode *N);
148 SDOperand visitADD_PARTS(SDNode *N);
149 SDOperand visitSUB_PARTS(SDNode *N);
150 SDOperand visitSIGN_EXTEND(SDNode *N);
151 SDOperand visitZERO_EXTEND(SDNode *N);
152 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
153 SDOperand visitTRUNCATE(SDNode *N);
155 SDOperand visitFADD(SDNode *N);
156 SDOperand visitFSUB(SDNode *N);
157 SDOperand visitFMUL(SDNode *N);
158 SDOperand visitFDIV(SDNode *N);
159 SDOperand visitFREM(SDNode *N);
160 SDOperand visitSINT_TO_FP(SDNode *N);
161 SDOperand visitUINT_TO_FP(SDNode *N);
162 SDOperand visitFP_TO_SINT(SDNode *N);
163 SDOperand visitFP_TO_UINT(SDNode *N);
164 SDOperand visitFP_ROUND(SDNode *N);
165 SDOperand visitFP_ROUND_INREG(SDNode *N);
166 SDOperand visitFP_EXTEND(SDNode *N);
167 SDOperand visitFNEG(SDNode *N);
168 SDOperand visitFABS(SDNode *N);
169 SDOperand visitBRCOND(SDNode *N);
170 SDOperand visitBRCONDTWOWAY(SDNode *N);
171 SDOperand visitBR_CC(SDNode *N);
172 SDOperand visitBRTWOWAY_CC(SDNode *N);
174 SDOperand visitLOAD(SDNode *N);
175 SDOperand visitSTORE(SDNode *N);
177 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
178 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
179 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
180 SDOperand N3, ISD::CondCode CC);
181 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
182 ISD::CondCode Cond, bool foldBooleans = true);
184 SDOperand BuildSDIV(SDNode *N);
185 SDOperand BuildUDIV(SDNode *N);
187 DAGCombiner(SelectionDAG &D)
188 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
190 /// Run - runs the dag combiner on all nodes in the work list
191 void Run(bool RunningAfterLegalize);
196 int64_t m; // magic number
197 int64_t s; // shift amount
201 uint64_t m; // magic number
202 int64_t a; // add indicator
203 int64_t s; // shift amount
206 /// magic - calculate the magic numbers required to codegen an integer sdiv as
207 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
209 static ms magic32(int32_t d) {
211 uint32_t ad, anc, delta, q1, r1, q2, r2, t;
212 const uint32_t two31 = 0x80000000U;
216 t = two31 + ((uint32_t)d >> 31);
217 anc = t - 1 - t%ad; // absolute value of nc
218 p = 31; // initialize p
219 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
220 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
221 q2 = two31/ad; // initialize q2 = 2p/abs(d)
222 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
225 q1 = 2*q1; // update q1 = 2p/abs(nc)
226 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
227 if (r1 >= anc) { // must be unsigned comparison
231 q2 = 2*q2; // update q2 = 2p/abs(d)
232 r2 = 2*r2; // update r2 = rem(2p/abs(d))
233 if (r2 >= ad) { // must be unsigned comparison
238 } while (q1 < delta || (q1 == delta && r1 == 0));
240 mag.m = (int32_t)(q2 + 1); // make sure to sign extend
241 if (d < 0) mag.m = -mag.m; // resulting magic number
242 mag.s = p - 32; // resulting shift
246 /// magicu - calculate the magic numbers required to codegen an integer udiv as
247 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
248 static mu magicu32(uint32_t d) {
250 uint32_t nc, delta, q1, r1, q2, r2;
252 magu.a = 0; // initialize "add" indicator
254 p = 31; // initialize p
255 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
256 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
257 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
258 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
261 if (r1 >= nc - r1 ) {
262 q1 = 2*q1 + 1; // update q1
263 r1 = 2*r1 - nc; // update r1
266 q1 = 2*q1; // update q1
267 r1 = 2*r1; // update r1
269 if (r2 + 1 >= d - r2) {
270 if (q2 >= 0x7FFFFFFF) magu.a = 1;
271 q2 = 2*q2 + 1; // update q2
272 r2 = 2*r2 + 1 - d; // update r2
275 if (q2 >= 0x80000000) magu.a = 1;
276 q2 = 2*q2; // update q2
277 r2 = 2*r2 + 1; // update r2
280 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
281 magu.m = q2 + 1; // resulting magic number
282 magu.s = p - 32; // resulting shift
286 /// magic - calculate the magic numbers required to codegen an integer sdiv as
287 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
289 static ms magic64(int64_t d) {
291 uint64_t ad, anc, delta, q1, r1, q2, r2, t;
292 const uint64_t two63 = 9223372036854775808ULL; // 2^63
296 t = two63 + ((uint64_t)d >> 63);
297 anc = t - 1 - t%ad; // absolute value of nc
298 p = 63; // initialize p
299 q1 = two63/anc; // initialize q1 = 2p/abs(nc)
300 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
301 q2 = two63/ad; // initialize q2 = 2p/abs(d)
302 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
305 q1 = 2*q1; // update q1 = 2p/abs(nc)
306 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
307 if (r1 >= anc) { // must be unsigned comparison
311 q2 = 2*q2; // update q2 = 2p/abs(d)
312 r2 = 2*r2; // update r2 = rem(2p/abs(d))
313 if (r2 >= ad) { // must be unsigned comparison
318 } while (q1 < delta || (q1 == delta && r1 == 0));
321 if (d < 0) mag.m = -mag.m; // resulting magic number
322 mag.s = p - 64; // resulting shift
326 /// magicu - calculate the magic numbers required to codegen an integer udiv as
327 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
328 static mu magicu64(uint64_t d)
331 uint64_t nc, delta, q1, r1, q2, r2;
333 magu.a = 0; // initialize "add" indicator
335 p = 63; // initialize p
336 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
337 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
338 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
339 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
342 if (r1 >= nc - r1 ) {
343 q1 = 2*q1 + 1; // update q1
344 r1 = 2*r1 - nc; // update r1
347 q1 = 2*q1; // update q1
348 r1 = 2*r1; // update r1
350 if (r2 + 1 >= d - r2) {
351 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
352 q2 = 2*q2 + 1; // update q2
353 r2 = 2*r2 + 1 - d; // update r2
356 if (q2 >= 0x8000000000000000ull) magu.a = 1;
357 q2 = 2*q2; // update q2
358 r2 = 2*r2 + 1; // update r2
361 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
362 magu.m = q2 + 1; // resulting magic number
363 magu.s = p - 64; // resulting shift
367 /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We use
368 /// this predicate to simplify operations downstream. Op and Mask are known to
369 /// be the same type.
370 static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
371 const TargetLowering &TLI) {
373 if (Mask == 0) return true;
375 // If we know the result of a setcc has the top bits zero, use this info.
376 switch (Op.getOpcode()) {
378 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
380 return ((Mask & 1) == 0) &&
381 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
383 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
384 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
385 case ISD::ZERO_EXTEND:
386 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
387 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI);
388 case ISD::AssertZext:
389 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
390 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
392 // If either of the operands has zero bits, the result will too.
393 if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) ||
394 MaskedValueIsZero(Op.getOperand(0), Mask, TLI))
396 // (X & C1) & C2 == 0 iff C1 & C2 == 0.
397 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
398 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
402 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
403 MaskedValueIsZero(Op.getOperand(1), Mask, TLI);
405 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) &&
406 MaskedValueIsZero(Op.getOperand(2), Mask, TLI);
408 return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) &&
409 MaskedValueIsZero(Op.getOperand(3), Mask, TLI);
411 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0
412 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
413 uint64_t NewVal = Mask << ShAmt->getValue();
414 SrcBits = MVT::getSizeInBits(Op.getValueType());
415 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
416 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
420 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0
421 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
422 uint64_t NewVal = Mask >> ShAmt->getValue();
423 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
427 // (add X, Y) & C == 0 iff (X&C)|(Y&C) == 0 and all bits are low bits.
428 if ((Mask&(Mask+1)) == 0) { // All low bits
429 if (MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
430 MaskedValueIsZero(Op.getOperand(1), Mask, TLI))
435 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
436 // We know that the top bits of C-X are clear if X contains less bits
437 // than C (i.e. no wrap-around can happen). For example, 20-X is
438 // positive if we can prove that X is >= 0 and < 16.
439 unsigned Bits = MVT::getSizeInBits(CLHS->getValueType(0));
440 if ((CLHS->getValue() & (1 << (Bits-1))) == 0) { // sign bit clear
441 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1);
442 uint64_t MaskV = (1ULL << (63-NLZ))-1;
443 if (MaskedValueIsZero(Op.getOperand(1), ~MaskV, TLI)) {
444 // High bits are clear this value is known to be >= C.
445 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue());
446 if ((Mask & ((1ULL << (64-NLZ2))-1)) == 0)
455 // Bit counting instructions can not set the high bits of the result
456 // register. The max number of bits sets depends on the input.
457 return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
463 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
464 // that selects between the values 1 and 0, making it equivalent to a setcc.
465 // Also, set the incoming LHS, RHS, and CC references to the appropriate
466 // nodes based on the type of node we are checking. This simplifies life a
467 // bit for the callers.
468 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
470 if (N.getOpcode() == ISD::SETCC) {
471 LHS = N.getOperand(0);
472 RHS = N.getOperand(1);
473 CC = N.getOperand(2);
476 if (N.getOpcode() == ISD::SELECT_CC &&
477 N.getOperand(2).getOpcode() == ISD::Constant &&
478 N.getOperand(3).getOpcode() == ISD::Constant &&
479 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
480 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
481 LHS = N.getOperand(0);
482 RHS = N.getOperand(1);
483 CC = N.getOperand(4);
489 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
490 // one use. If this is true, it allows the users to invert the operation for
491 // free when it is profitable to do so.
492 static bool isOneUseSetCC(SDOperand N) {
493 SDOperand N0, N1, N2;
494 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
499 // FIXME: This should probably go in the ISD class rather than being duplicated
501 static bool isCommutativeBinOp(unsigned Opcode) {
507 case ISD::XOR: return true;
508 default: return false; // FIXME: Need commutative info for user ops!
512 void DAGCombiner::Run(bool RunningAfterLegalize) {
513 // set the instance variable, so that the various visit routines may use it.
514 AfterLegalize = RunningAfterLegalize;
516 // Add all the dag nodes to the worklist.
517 WorkList.insert(WorkList.end(), DAG.allnodes_begin(), DAG.allnodes_end());
519 // Create a dummy node (which is not added to allnodes), that adds a reference
520 // to the root node, preventing it from being deleted, and tracking any
521 // changes of the root.
522 HandleSDNode Dummy(DAG.getRoot());
524 // while the worklist isn't empty, inspect the node on the end of it and
525 // try and combine it.
526 while (!WorkList.empty()) {
527 SDNode *N = WorkList.back();
530 // If N has no uses, it is dead. Make sure to revisit all N's operands once
531 // N is deleted from the DAG, since they too may now be dead or may have a
532 // reduced number of uses, allowing other xforms.
533 if (N->use_empty() && N != &Dummy) {
534 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
535 WorkList.push_back(N->getOperand(i).Val);
537 removeFromWorkList(N);
542 SDOperand RV = visit(N);
545 // If we get back the same node we passed in, rather than a new node or
546 // zero, we know that the node must have defined multiple values and
547 // CombineTo was used. Since CombineTo takes care of the worklist
548 // mechanics for us, we have no work to do in this case.
550 DEBUG(std::cerr << "\nReplacing "; N->dump();
551 std::cerr << "\nWith: "; RV.Val->dump();
553 std::vector<SDNode*> NowDead;
554 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead);
556 // Push the new node and any users onto the worklist
557 WorkList.push_back(RV.Val);
558 AddUsersToWorkList(RV.Val);
560 // Nodes can end up on the worklist more than once. Make sure we do
561 // not process a node that has been replaced.
562 removeFromWorkList(N);
563 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
564 removeFromWorkList(NowDead[i]);
566 // Finally, since the node is now dead, remove it from the graph.
572 // If the root changed (e.g. it was a dead load, update the root).
573 DAG.setRoot(Dummy.getValue());
576 SDOperand DAGCombiner::visit(SDNode *N) {
577 switch(N->getOpcode()) {
579 case ISD::TokenFactor: return visitTokenFactor(N);
580 case ISD::ADD: return visitADD(N);
581 case ISD::SUB: return visitSUB(N);
582 case ISD::MUL: return visitMUL(N);
583 case ISD::SDIV: return visitSDIV(N);
584 case ISD::UDIV: return visitUDIV(N);
585 case ISD::SREM: return visitSREM(N);
586 case ISD::UREM: return visitUREM(N);
587 case ISD::MULHU: return visitMULHU(N);
588 case ISD::MULHS: return visitMULHS(N);
589 case ISD::AND: return visitAND(N);
590 case ISD::OR: return visitOR(N);
591 case ISD::XOR: return visitXOR(N);
592 case ISD::SHL: return visitSHL(N);
593 case ISD::SRA: return visitSRA(N);
594 case ISD::SRL: return visitSRL(N);
595 case ISD::CTLZ: return visitCTLZ(N);
596 case ISD::CTTZ: return visitCTTZ(N);
597 case ISD::CTPOP: return visitCTPOP(N);
598 case ISD::SELECT: return visitSELECT(N);
599 case ISD::SELECT_CC: return visitSELECT_CC(N);
600 case ISD::SETCC: return visitSETCC(N);
601 case ISD::ADD_PARTS: return visitADD_PARTS(N);
602 case ISD::SUB_PARTS: return visitSUB_PARTS(N);
603 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
604 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
605 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
606 case ISD::TRUNCATE: return visitTRUNCATE(N);
607 case ISD::FADD: return visitFADD(N);
608 case ISD::FSUB: return visitFSUB(N);
609 case ISD::FMUL: return visitFMUL(N);
610 case ISD::FDIV: return visitFDIV(N);
611 case ISD::FREM: return visitFREM(N);
612 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
613 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
614 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
615 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
616 case ISD::FP_ROUND: return visitFP_ROUND(N);
617 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
618 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
619 case ISD::FNEG: return visitFNEG(N);
620 case ISD::FABS: return visitFABS(N);
621 case ISD::BRCOND: return visitBRCOND(N);
622 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N);
623 case ISD::BR_CC: return visitBR_CC(N);
624 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N);
625 case ISD::LOAD: return visitLOAD(N);
626 case ISD::STORE: return visitSTORE(N);
631 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
632 std::vector<SDOperand> Ops;
633 bool Changed = false;
635 // If the token factor has two operands and one is the entry token, replace
636 // the token factor with the other operand.
637 if (N->getNumOperands() == 2) {
638 if (N->getOperand(0).getOpcode() == ISD::EntryToken)
639 return N->getOperand(1);
640 if (N->getOperand(1).getOpcode() == ISD::EntryToken)
641 return N->getOperand(0);
644 // fold (tokenfactor (tokenfactor)) -> tokenfactor
645 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
646 SDOperand Op = N->getOperand(i);
647 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) {
649 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j)
650 Ops.push_back(Op.getOperand(j));
656 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
660 SDOperand DAGCombiner::visitADD(SDNode *N) {
661 SDOperand N0 = N->getOperand(0);
662 SDOperand N1 = N->getOperand(1);
663 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
664 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
665 MVT::ValueType VT = N0.getValueType();
667 // fold (add c1, c2) -> c1+c2
669 return DAG.getConstant(N0C->getValue() + N1C->getValue(), VT);
670 // canonicalize constant to RHS
672 return DAG.getNode(ISD::ADD, VT, N1, N0);
673 // fold (add x, 0) -> x
674 if (N1C && N1C->isNullValue())
676 // fold (add (add x, c1), c2) -> (add x, c1+c2)
677 if (N1C && N0.getOpcode() == ISD::ADD) {
678 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
679 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
681 return DAG.getNode(ISD::ADD, VT, N0.getOperand(1),
682 DAG.getConstant(N1C->getValue()+N00C->getValue(), VT));
684 return DAG.getNode(ISD::ADD, VT, N0.getOperand(0),
685 DAG.getConstant(N1C->getValue()+N01C->getValue(), VT));
687 // fold ((0-A) + B) -> B-A
688 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
689 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
690 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
691 // fold (A + (0-B)) -> A-B
692 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
693 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
694 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
695 // fold (A+(B-A)) -> B
696 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
697 return N1.getOperand(0);
701 SDOperand DAGCombiner::visitSUB(SDNode *N) {
702 SDOperand N0 = N->getOperand(0);
703 SDOperand N1 = N->getOperand(1);
704 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
705 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
707 // fold (sub x, x) -> 0
709 return DAG.getConstant(0, N->getValueType(0));
711 // fold (sub c1, c2) -> c1-c2
713 return DAG.getConstant(N0C->getValue() - N1C->getValue(),
715 // fold (sub x, c) -> (add x, -c)
717 return DAG.getNode(ISD::ADD, N0.getValueType(), N0,
718 DAG.getConstant(-N1C->getValue(), N0.getValueType()));
721 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
722 return N0.getOperand(1);
724 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
725 return N0.getOperand(0);
729 SDOperand DAGCombiner::visitMUL(SDNode *N) {
730 SDOperand N0 = N->getOperand(0);
731 SDOperand N1 = N->getOperand(1);
732 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
733 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
734 MVT::ValueType VT = N0.getValueType();
736 // fold (mul c1, c2) -> c1*c2
738 return DAG.getConstant(N0C->getValue() * N1C->getValue(),
740 // canonicalize constant to RHS
742 return DAG.getNode(ISD::MUL, VT, N1, N0);
743 // fold (mul x, 0) -> 0
744 if (N1C && N1C->isNullValue())
746 // fold (mul x, -1) -> 0-x
747 if (N1C && N1C->isAllOnesValue())
748 return DAG.getNode(ISD::SUB, N->getValueType(0),
749 DAG.getConstant(0, N->getValueType(0)), N0);
750 // fold (mul x, (1 << c)) -> x << c
751 if (N1C && isPowerOf2_64(N1C->getValue()))
752 return DAG.getNode(ISD::SHL, N->getValueType(0), N0,
753 DAG.getConstant(Log2_64(N1C->getValue()),
754 TLI.getShiftAmountTy()));
755 // fold (mul (mul x, c1), c2) -> (mul x, c1*c2)
756 if (N1C && N0.getOpcode() == ISD::MUL) {
757 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
758 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
760 return DAG.getNode(ISD::MUL, VT, N0.getOperand(1),
761 DAG.getConstant(N1C->getValue()*N00C->getValue(), VT));
763 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0),
764 DAG.getConstant(N1C->getValue()*N01C->getValue(), VT));
769 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
770 SDOperand N0 = N->getOperand(0);
771 SDOperand N1 = N->getOperand(1);
772 MVT::ValueType VT = N->getValueType(0);
773 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
774 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
776 // fold (sdiv c1, c2) -> c1/c2
777 if (N0C && N1C && !N1C->isNullValue())
778 return DAG.getConstant(N0C->getSignExtended() / N1C->getSignExtended(),
780 // If we know the sign bits of both operands are zero, strength reduce to a
781 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
782 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
783 if (MaskedValueIsZero(N1, SignBit, TLI) &&
784 MaskedValueIsZero(N0, SignBit, TLI))
785 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
786 // if integer divide is expensive and we satisfy the requirements, emit an
787 // alternate sequence.
788 // FIXME: This currently opts out powers of two, since targets can often be
789 // more clever in those cases. In an idea world, we would have some way to
791 if (N1C && !isPowerOf2_64(N1C->getSignExtended()) &&
792 (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
793 TLI.isOperationLegal(ISD::MULHS, VT) && TLI.isIntDivExpensive()) {
799 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
800 SDOperand N0 = N->getOperand(0);
801 SDOperand N1 = N->getOperand(1);
802 MVT::ValueType VT = N->getValueType(0);
803 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
804 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
806 // fold (udiv c1, c2) -> c1/c2
807 if (N0C && N1C && !N1C->isNullValue())
808 return DAG.getConstant(N0C->getValue() / N1C->getValue(),
810 // fold (udiv x, (1 << c)) -> x >>u c
811 if (N1C && isPowerOf2_64(N1C->getValue()))
812 return DAG.getNode(ISD::SRL, N->getValueType(0), N0,
813 DAG.getConstant(Log2_64(N1C->getValue()),
814 TLI.getShiftAmountTy()));
815 // fold (udiv x, c) -> alternate
816 if (N1C && N1C->getValue() && TLI.isOperationLegal(ISD::MULHU, VT) &&
817 TLI.isIntDivExpensive())
822 SDOperand DAGCombiner::visitSREM(SDNode *N) {
823 SDOperand N0 = N->getOperand(0);
824 SDOperand N1 = N->getOperand(1);
825 MVT::ValueType VT = N->getValueType(0);
826 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
827 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
829 // fold (srem c1, c2) -> c1%c2
830 if (N0C && N1C && !N1C->isNullValue())
831 return DAG.getConstant(N0C->getSignExtended() % N1C->getSignExtended(),
833 // If we know the sign bits of both operands are zero, strength reduce to a
834 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
835 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
836 if (MaskedValueIsZero(N1, SignBit, TLI) &&
837 MaskedValueIsZero(N0, SignBit, TLI))
838 return DAG.getNode(ISD::UREM, N1.getValueType(), N0, N1);
842 SDOperand DAGCombiner::visitUREM(SDNode *N) {
843 SDOperand N0 = N->getOperand(0);
844 SDOperand N1 = N->getOperand(1);
845 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
846 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
848 // fold (urem c1, c2) -> c1%c2
849 if (N0C && N1C && !N1C->isNullValue())
850 return DAG.getConstant(N0C->getValue() % N1C->getValue(),
852 // fold (urem x, pow2) -> (and x, pow2-1)
853 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
854 return DAG.getNode(ISD::AND, N0.getValueType(), N0,
855 DAG.getConstant(N1C->getValue()-1, N1.getValueType()));
859 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
860 SDOperand N0 = N->getOperand(0);
861 SDOperand N1 = N->getOperand(1);
862 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
864 // fold (mulhs x, 0) -> 0
865 if (N1C && N1C->isNullValue())
867 // fold (mulhs x, 1) -> (sra x, size(x)-1)
868 if (N1C && N1C->getValue() == 1)
869 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
870 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
871 TLI.getShiftAmountTy()));
875 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
876 SDOperand N0 = N->getOperand(0);
877 SDOperand N1 = N->getOperand(1);
878 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
880 // fold (mulhu x, 0) -> 0
881 if (N1C && N1C->isNullValue())
883 // fold (mulhu x, 1) -> 0
884 if (N1C && N1C->getValue() == 1)
885 return DAG.getConstant(0, N0.getValueType());
889 SDOperand DAGCombiner::visitAND(SDNode *N) {
890 SDOperand N0 = N->getOperand(0);
891 SDOperand N1 = N->getOperand(1);
892 SDOperand LL, LR, RL, RR, CC0, CC1;
893 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
894 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
895 MVT::ValueType VT = N1.getValueType();
896 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
898 // fold (and c1, c2) -> c1&c2
900 return DAG.getConstant(N0C->getValue() & N1C->getValue(), VT);
901 // canonicalize constant to RHS
903 return DAG.getNode(ISD::AND, VT, N1, N0);
904 // fold (and x, -1) -> x
905 if (N1C && N1C->isAllOnesValue())
907 // if (and x, c) is known to be zero, return 0
908 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
909 return DAG.getConstant(0, VT);
910 // fold (and x, c) -> x iff (x & ~c) == 0
911 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)),
914 // fold (and (and x, c1), c2) -> (and x, c1^c2)
915 if (N1C && N0.getOpcode() == ISD::AND) {
916 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
917 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
919 return DAG.getNode(ISD::AND, VT, N0.getOperand(1),
920 DAG.getConstant(N1C->getValue()&N00C->getValue(), VT));
922 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
923 DAG.getConstant(N1C->getValue()&N01C->getValue(), VT));
925 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
926 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
927 unsigned ExtendBits =
928 MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT());
929 if ((N1C->getValue() & (~0ULL << ExtendBits)) == 0)
930 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1);
932 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
933 if (N0.getOpcode() == ISD::OR && N1C)
934 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
935 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
937 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
938 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
939 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
940 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
942 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
943 MVT::isInteger(LL.getValueType())) {
944 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
945 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
946 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
947 WorkList.push_back(ORNode.Val);
948 return DAG.getSetCC(VT, ORNode, LR, Op1);
950 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
951 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
952 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
953 WorkList.push_back(ANDNode.Val);
954 return DAG.getSetCC(VT, ANDNode, LR, Op1);
956 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
957 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
958 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
959 WorkList.push_back(ORNode.Val);
960 return DAG.getSetCC(VT, ORNode, LR, Op1);
963 // canonicalize equivalent to ll == rl
964 if (LL == RR && LR == RL) {
965 Op1 = ISD::getSetCCSwappedOperands(Op1);
968 if (LL == RL && LR == RR) {
969 bool isInteger = MVT::isInteger(LL.getValueType());
970 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
971 if (Result != ISD::SETCC_INVALID)
972 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
975 // fold (and (zext x), (zext y)) -> (zext (and x, y))
976 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
977 N1.getOpcode() == ISD::ZERO_EXTEND &&
978 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
979 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
980 N0.getOperand(0), N1.getOperand(0));
981 WorkList.push_back(ANDNode.Val);
982 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode);
984 // fold (and (shl/srl x), (shl/srl y)) -> (shl/srl (and x, y))
985 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
986 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL)) &&
987 N0.getOperand(1) == N1.getOperand(1)) {
988 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
989 N0.getOperand(0), N1.getOperand(0));
990 WorkList.push_back(ANDNode.Val);
991 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
993 // fold (and (sra)) -> (and (srl)) when possible.
994 if (N0.getOpcode() == ISD::SRA && N0.Val->hasOneUse())
995 if (ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
996 // If the RHS of the AND has zeros where the sign bits of the SRA will
997 // land, turn the SRA into an SRL.
998 if (MaskedValueIsZero(N1, (~0ULL << (OpSizeInBits-N01C->getValue())) &
999 (~0ULL>>(64-OpSizeInBits)), TLI)) {
1000 WorkList.push_back(N);
1001 CombineTo(N0.Val, DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1007 // fold (zext_inreg (extload x)) -> (zextload x)
1008 if (N0.getOpcode() == ISD::EXTLOAD) {
1009 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1010 // If we zero all the possible extended bits, then we can turn this into
1011 // a zextload if we are running before legalize or the operation is legal.
1012 if (MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT), TLI) &&
1013 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1014 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1015 N0.getOperand(1), N0.getOperand(2),
1017 WorkList.push_back(N);
1018 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1022 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1023 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) {
1024 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1025 // If we zero all the possible extended bits, then we can turn this into
1026 // a zextload if we are running before legalize or the operation is legal.
1027 if (MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT), TLI) &&
1028 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1029 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1030 N0.getOperand(1), N0.getOperand(2),
1032 WorkList.push_back(N);
1033 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1040 SDOperand DAGCombiner::visitOR(SDNode *N) {
1041 SDOperand N0 = N->getOperand(0);
1042 SDOperand N1 = N->getOperand(1);
1043 SDOperand LL, LR, RL, RR, CC0, CC1;
1044 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1045 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1046 MVT::ValueType VT = N1.getValueType();
1047 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1049 // fold (or c1, c2) -> c1|c2
1051 return DAG.getConstant(N0C->getValue() | N1C->getValue(),
1052 N->getValueType(0));
1053 // canonicalize constant to RHS
1055 return DAG.getNode(ISD::OR, VT, N1, N0);
1056 // fold (or x, 0) -> x
1057 if (N1C && N1C->isNullValue())
1059 // fold (or x, -1) -> -1
1060 if (N1C && N1C->isAllOnesValue())
1062 // fold (or x, c) -> c iff (x & ~c) == 0
1063 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)),
1066 // fold (or (or x, c1), c2) -> (or x, c1|c2)
1067 if (N1C && N0.getOpcode() == ISD::OR) {
1068 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1069 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1071 return DAG.getNode(ISD::OR, VT, N0.getOperand(1),
1072 DAG.getConstant(N1C->getValue()|N00C->getValue(), VT));
1074 return DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1075 DAG.getConstant(N1C->getValue()|N01C->getValue(), VT));
1077 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1078 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1079 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1080 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1082 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1083 MVT::isInteger(LL.getValueType())) {
1084 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1085 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1086 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1087 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1088 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1089 WorkList.push_back(ORNode.Val);
1090 return DAG.getSetCC(VT, ORNode, LR, Op1);
1092 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1093 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1094 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1095 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1096 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1097 WorkList.push_back(ANDNode.Val);
1098 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1101 // canonicalize equivalent to ll == rl
1102 if (LL == RR && LR == RL) {
1103 Op1 = ISD::getSetCCSwappedOperands(Op1);
1106 if (LL == RL && LR == RR) {
1107 bool isInteger = MVT::isInteger(LL.getValueType());
1108 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1109 if (Result != ISD::SETCC_INVALID)
1110 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1113 // fold (or (zext x), (zext y)) -> (zext (or x, y))
1114 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1115 N1.getOpcode() == ISD::ZERO_EXTEND &&
1116 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1117 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
1118 N0.getOperand(0), N1.getOperand(0));
1119 WorkList.push_back(ORNode.Val);
1120 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode);
1125 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1126 SDOperand N0 = N->getOperand(0);
1127 SDOperand N1 = N->getOperand(1);
1128 SDOperand LHS, RHS, CC;
1129 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1130 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1131 MVT::ValueType VT = N0.getValueType();
1133 // fold (xor c1, c2) -> c1^c2
1135 return DAG.getConstant(N0C->getValue() ^ N1C->getValue(), VT);
1136 // canonicalize constant to RHS
1138 return DAG.getNode(ISD::XOR, VT, N1, N0);
1139 // fold (xor x, 0) -> x
1140 if (N1C && N1C->isNullValue())
1142 // fold !(x cc y) -> (x !cc y)
1143 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1144 bool isInt = MVT::isInteger(LHS.getValueType());
1145 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1147 if (N0.getOpcode() == ISD::SETCC)
1148 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1149 if (N0.getOpcode() == ISD::SELECT_CC)
1150 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1151 assert(0 && "Unhandled SetCC Equivalent!");
1154 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1155 if (N1C && N1C->getValue() == 1 &&
1156 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1157 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1158 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1159 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1160 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1161 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1162 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
1163 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1166 // fold !(x or y) -> (!x and !y) iff x or y are constants
1167 if (N1C && N1C->isAllOnesValue() &&
1168 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1169 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1170 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1171 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1172 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1173 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1174 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
1175 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1178 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1179 if (N1C && N0.getOpcode() == ISD::XOR) {
1180 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1181 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1183 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1184 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1186 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1187 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1189 // fold (xor x, x) -> 0
1191 return DAG.getConstant(0, VT);
1192 // fold (xor (zext x), (zext y)) -> (zext (xor x, y))
1193 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1194 N1.getOpcode() == ISD::ZERO_EXTEND &&
1195 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1196 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
1197 N0.getOperand(0), N1.getOperand(0));
1198 WorkList.push_back(XORNode.Val);
1199 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
1204 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1205 SDOperand N0 = N->getOperand(0);
1206 SDOperand N1 = N->getOperand(1);
1207 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1208 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1209 MVT::ValueType VT = N0.getValueType();
1210 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1212 // fold (shl c1, c2) -> c1<<c2
1214 return DAG.getConstant(N0C->getValue() << N1C->getValue(), VT);
1215 // fold (shl 0, x) -> 0
1216 if (N0C && N0C->isNullValue())
1218 // fold (shl x, c >= size(x)) -> undef
1219 if (N1C && N1C->getValue() >= OpSizeInBits)
1220 return DAG.getNode(ISD::UNDEF, VT);
1221 // fold (shl x, 0) -> x
1222 if (N1C && N1C->isNullValue())
1224 // if (shl x, c) is known to be zero, return 0
1225 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
1226 return DAG.getConstant(0, VT);
1227 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1228 if (N1C && N0.getOpcode() == ISD::SHL &&
1229 N0.getOperand(1).getOpcode() == ISD::Constant) {
1230 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1231 uint64_t c2 = N1C->getValue();
1232 if (c1 + c2 > OpSizeInBits)
1233 return DAG.getConstant(0, VT);
1234 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1235 DAG.getConstant(c1 + c2, N1.getValueType()));
1237 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1238 // (srl (and x, -1 << c1), c1-c2)
1239 if (N1C && N0.getOpcode() == ISD::SRL &&
1240 N0.getOperand(1).getOpcode() == ISD::Constant) {
1241 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1242 uint64_t c2 = N1C->getValue();
1243 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1244 DAG.getConstant(~0ULL << c1, VT));
1246 return DAG.getNode(ISD::SHL, VT, Mask,
1247 DAG.getConstant(c2-c1, N1.getValueType()));
1249 return DAG.getNode(ISD::SRL, VT, Mask,
1250 DAG.getConstant(c1-c2, N1.getValueType()));
1252 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1253 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1254 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1255 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1259 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1260 SDOperand N0 = N->getOperand(0);
1261 SDOperand N1 = N->getOperand(1);
1262 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1263 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1264 MVT::ValueType VT = N0.getValueType();
1265 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1267 // fold (sra c1, c2) -> c1>>c2
1269 return DAG.getConstant(N0C->getSignExtended() >> N1C->getValue(), VT);
1270 // fold (sra 0, x) -> 0
1271 if (N0C && N0C->isNullValue())
1273 // fold (sra -1, x) -> -1
1274 if (N0C && N0C->isAllOnesValue())
1276 // fold (sra x, c >= size(x)) -> undef
1277 if (N1C && N1C->getValue() >= OpSizeInBits)
1278 return DAG.getNode(ISD::UNDEF, VT);
1279 // fold (sra x, 0) -> x
1280 if (N1C && N1C->isNullValue())
1282 // If the sign bit is known to be zero, switch this to a SRL.
1283 if (MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)), TLI))
1284 return DAG.getNode(ISD::SRL, VT, N0, N1);
1288 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1289 SDOperand N0 = N->getOperand(0);
1290 SDOperand N1 = N->getOperand(1);
1291 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1292 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1293 MVT::ValueType VT = N0.getValueType();
1294 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1296 // fold (srl c1, c2) -> c1 >>u c2
1298 return DAG.getConstant(N0C->getValue() >> N1C->getValue(), VT);
1299 // fold (srl 0, x) -> 0
1300 if (N0C && N0C->isNullValue())
1302 // fold (srl x, c >= size(x)) -> undef
1303 if (N1C && N1C->getValue() >= OpSizeInBits)
1304 return DAG.getNode(ISD::UNDEF, VT);
1305 // fold (srl x, 0) -> x
1306 if (N1C && N1C->isNullValue())
1308 // if (srl x, c) is known to be zero, return 0
1309 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
1310 return DAG.getConstant(0, VT);
1311 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1312 if (N1C && N0.getOpcode() == ISD::SRL &&
1313 N0.getOperand(1).getOpcode() == ISD::Constant) {
1314 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1315 uint64_t c2 = N1C->getValue();
1316 if (c1 + c2 > OpSizeInBits)
1317 return DAG.getConstant(0, VT);
1318 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1319 DAG.getConstant(c1 + c2, N1.getValueType()));
1324 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1325 SDOperand N0 = N->getOperand(0);
1326 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1328 // fold (ctlz c1) -> c2
1330 return DAG.getConstant(CountLeadingZeros_64(N0C->getValue()),
1335 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1336 SDOperand N0 = N->getOperand(0);
1337 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1339 // fold (cttz c1) -> c2
1341 return DAG.getConstant(CountTrailingZeros_64(N0C->getValue()),
1346 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1347 SDOperand N0 = N->getOperand(0);
1348 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1350 // fold (ctpop c1) -> c2
1352 return DAG.getConstant(CountPopulation_64(N0C->getValue()),
1357 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1358 SDOperand N0 = N->getOperand(0);
1359 SDOperand N1 = N->getOperand(1);
1360 SDOperand N2 = N->getOperand(2);
1361 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1362 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1363 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1364 MVT::ValueType VT = N->getValueType(0);
1366 // fold select C, X, X -> X
1369 // fold select true, X, Y -> X
1370 if (N0C && !N0C->isNullValue())
1372 // fold select false, X, Y -> Y
1373 if (N0C && N0C->isNullValue())
1375 // fold select C, 1, X -> C | X
1376 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1377 return DAG.getNode(ISD::OR, VT, N0, N2);
1378 // fold select C, 0, X -> ~C & X
1379 // FIXME: this should check for C type == X type, not i1?
1380 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1381 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1382 WorkList.push_back(XORNode.Val);
1383 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1385 // fold select C, X, 1 -> ~C | X
1386 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1387 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1388 WorkList.push_back(XORNode.Val);
1389 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1391 // fold select C, X, 0 -> C & X
1392 // FIXME: this should check for C type == X type, not i1?
1393 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1394 return DAG.getNode(ISD::AND, VT, N0, N1);
1395 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1396 if (MVT::i1 == VT && N0 == N1)
1397 return DAG.getNode(ISD::OR, VT, N0, N2);
1398 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1399 if (MVT::i1 == VT && N0 == N2)
1400 return DAG.getNode(ISD::AND, VT, N0, N1);
1402 // If we can fold this based on the true/false value, do so.
1403 if (SimplifySelectOps(N, N1, N2))
1406 // fold selects based on a setcc into other things, such as min/max/abs
1407 if (N0.getOpcode() == ISD::SETCC)
1408 return SimplifySelect(N0, N1, N2);
1412 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1413 SDOperand N0 = N->getOperand(0);
1414 SDOperand N1 = N->getOperand(1);
1415 SDOperand N2 = N->getOperand(2);
1416 SDOperand N3 = N->getOperand(3);
1417 SDOperand N4 = N->getOperand(4);
1418 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1419 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1420 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1421 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1423 // Determine if the condition we're dealing with is constant
1424 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1425 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1427 // fold select_cc lhs, rhs, x, x, cc -> x
1431 // If we can fold this based on the true/false value, do so.
1432 if (SimplifySelectOps(N, N2, N3))
1435 // fold select_cc into other things, such as min/max/abs
1436 return SimplifySelectCC(N0, N1, N2, N3, CC);
1439 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1440 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1441 cast<CondCodeSDNode>(N->getOperand(2))->get());
1444 SDOperand DAGCombiner::visitADD_PARTS(SDNode *N) {
1445 SDOperand LHSLo = N->getOperand(0);
1446 SDOperand RHSLo = N->getOperand(2);
1447 MVT::ValueType VT = LHSLo.getValueType();
1449 // fold (a_Hi, 0) + (b_Hi, b_Lo) -> (b_Hi + a_Hi, b_Lo)
1450 if (MaskedValueIsZero(LHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) {
1451 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1),
1453 WorkList.push_back(Hi.Val);
1454 CombineTo(N, RHSLo, Hi);
1457 // fold (a_Hi, a_Lo) + (b_Hi, 0) -> (a_Hi + b_Hi, a_Lo)
1458 if (MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) {
1459 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1),
1461 WorkList.push_back(Hi.Val);
1462 CombineTo(N, LHSLo, Hi);
1468 SDOperand DAGCombiner::visitSUB_PARTS(SDNode *N) {
1469 SDOperand LHSLo = N->getOperand(0);
1470 SDOperand RHSLo = N->getOperand(2);
1471 MVT::ValueType VT = LHSLo.getValueType();
1473 // fold (a_Hi, a_Lo) - (b_Hi, 0) -> (a_Hi - b_Hi, a_Lo)
1474 if (MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) {
1475 SDOperand Hi = DAG.getNode(ISD::SUB, VT, N->getOperand(1),
1477 WorkList.push_back(Hi.Val);
1478 CombineTo(N, LHSLo, Hi);
1484 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1485 SDOperand N0 = N->getOperand(0);
1486 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1487 MVT::ValueType VT = N->getValueType(0);
1489 // fold (sext c1) -> c1
1491 return DAG.getConstant(N0C->getSignExtended(), VT);
1492 // fold (sext (sext x)) -> (sext x)
1493 if (N0.getOpcode() == ISD::SIGN_EXTEND)
1494 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1495 // fold (sext (sextload x)) -> (sextload x)
1496 if (N0.getOpcode() == ISD::SEXTLOAD && VT == N0.getValueType())
1498 // fold (sext (load x)) -> (sextload x)
1499 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
1500 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1501 N0.getOperand(1), N0.getOperand(2),
1503 WorkList.push_back(N);
1504 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1505 ExtLoad.getValue(1));
1511 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1512 SDOperand N0 = N->getOperand(0);
1513 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1514 MVT::ValueType VT = N->getValueType(0);
1516 // fold (zext c1) -> c1
1518 return DAG.getConstant(N0C->getValue(), VT);
1519 // fold (zext (zext x)) -> (zext x)
1520 if (N0.getOpcode() == ISD::ZERO_EXTEND)
1521 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1525 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1526 SDOperand N0 = N->getOperand(0);
1527 SDOperand N1 = N->getOperand(1);
1528 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1529 MVT::ValueType VT = N->getValueType(0);
1530 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
1531 unsigned EVTBits = MVT::getSizeInBits(EVT);
1533 // fold (sext_in_reg c1) -> c1
1535 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT);
1536 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate);
1538 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1
1539 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1540 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1543 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
1544 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1545 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
1546 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
1548 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x)
1549 if (N0.getOpcode() == ISD::AssertSext &&
1550 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1553 // fold (sext_in_reg (sextload x)) -> (sextload x)
1554 if (N0.getOpcode() == ISD::SEXTLOAD &&
1555 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) {
1558 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1
1559 if (N0.getOpcode() == ISD::SETCC &&
1560 TLI.getSetCCResultContents() ==
1561 TargetLowering::ZeroOrNegativeOneSetCCResult)
1563 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
1564 if (MaskedValueIsZero(N0, 1ULL << (EVTBits-1), TLI))
1565 return DAG.getNode(ISD::AND, N0.getValueType(), N0,
1566 DAG.getConstant(~0ULL >> (64-EVTBits), VT));
1567 // fold (sext_in_reg (srl x)) -> sra x
1568 if (N0.getOpcode() == ISD::SRL &&
1569 N0.getOperand(1).getOpcode() == ISD::Constant &&
1570 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) {
1571 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0),
1574 // fold (sext_inreg (extload x)) -> (sextload x)
1575 if (N0.getOpcode() == ISD::EXTLOAD &&
1576 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1577 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1578 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1579 N0.getOperand(1), N0.getOperand(2),
1581 WorkList.push_back(N);
1582 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1585 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
1586 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() &&
1587 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1588 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1589 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1590 N0.getOperand(1), N0.getOperand(2),
1592 WorkList.push_back(N);
1593 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1599 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
1600 SDOperand N0 = N->getOperand(0);
1601 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1602 MVT::ValueType VT = N->getValueType(0);
1605 if (N0.getValueType() == N->getValueType(0))
1607 // fold (truncate c1) -> c1
1609 return DAG.getConstant(N0C->getValue(), VT);
1610 // fold (truncate (truncate x)) -> (truncate x)
1611 if (N0.getOpcode() == ISD::TRUNCATE)
1612 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1613 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
1614 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){
1615 if (N0.getValueType() < VT)
1616 // if the source is smaller than the dest, we still need an extend
1617 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
1618 else if (N0.getValueType() > VT)
1619 // if the source is larger than the dest, than we just need the truncate
1620 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1622 // if the source and dest are the same type, we can drop both the extend
1624 return N0.getOperand(0);
1626 // fold (truncate (load x)) -> (smaller load x)
1627 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
1628 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
1629 "Cannot truncate to larger type!");
1630 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1631 // For big endian targets, we need to add an offset to the pointer to load
1632 // the correct bytes. For little endian systems, we merely need to read
1633 // fewer bytes from the same pointer.
1635 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
1636 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) :
1637 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1),
1638 DAG.getConstant(PtrOff, PtrType));
1639 WorkList.push_back(NewPtr.Val);
1640 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2));
1641 WorkList.push_back(N);
1642 CombineTo(N0.Val, Load, Load.getValue(1));
1648 SDOperand DAGCombiner::visitFADD(SDNode *N) {
1649 SDOperand N0 = N->getOperand(0);
1650 SDOperand N1 = N->getOperand(1);
1651 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1652 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1653 MVT::ValueType VT = N->getValueType(0);
1655 // fold (fadd c1, c2) -> c1+c2
1657 return DAG.getConstantFP(N0CFP->getValue() + N1CFP->getValue(), VT);
1658 // canonicalize constant to RHS
1659 if (N0CFP && !N1CFP)
1660 return DAG.getNode(ISD::FADD, VT, N1, N0);
1661 // fold (A + (-B)) -> A-B
1662 if (N1.getOpcode() == ISD::FNEG)
1663 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
1664 // fold ((-A) + B) -> B-A
1665 if (N0.getOpcode() == ISD::FNEG)
1666 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
1670 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
1671 SDOperand N0 = N->getOperand(0);
1672 SDOperand N1 = N->getOperand(1);
1673 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1674 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1675 MVT::ValueType VT = N->getValueType(0);
1677 // fold (fsub c1, c2) -> c1-c2
1679 return DAG.getConstantFP(N0CFP->getValue() - N1CFP->getValue(), VT);
1680 // fold (A-(-B)) -> A+B
1681 if (N1.getOpcode() == ISD::FNEG)
1682 return DAG.getNode(ISD::FADD, N0.getValueType(), N0, N1.getOperand(0));
1686 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
1687 SDOperand N0 = N->getOperand(0);
1688 SDOperand N1 = N->getOperand(1);
1689 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1690 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1691 MVT::ValueType VT = N->getValueType(0);
1693 // fold (fmul c1, c2) -> c1*c2
1695 return DAG.getConstantFP(N0CFP->getValue() * N1CFP->getValue(), VT);
1696 // canonicalize constant to RHS
1697 if (N0CFP && !N1CFP)
1698 return DAG.getNode(ISD::FMUL, VT, N1, N0);
1699 // fold (fmul X, 2.0) -> (fadd X, X)
1700 if (N1CFP && N1CFP->isExactlyValue(+2.0))
1701 return DAG.getNode(ISD::FADD, VT, N0, N0);
1705 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
1706 SDOperand N0 = N->getOperand(0);
1707 SDOperand N1 = N->getOperand(1);
1708 MVT::ValueType VT = N->getValueType(0);
1710 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
1711 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1712 // fold floating point (fdiv c1, c2)
1713 return DAG.getConstantFP(N0CFP->getValue() / N1CFP->getValue(), VT);
1718 SDOperand DAGCombiner::visitFREM(SDNode *N) {
1719 SDOperand N0 = N->getOperand(0);
1720 SDOperand N1 = N->getOperand(1);
1721 MVT::ValueType VT = N->getValueType(0);
1723 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
1724 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1725 // fold floating point (frem c1, c2) -> fmod(c1, c2)
1726 return DAG.getConstantFP(fmod(N0CFP->getValue(),N1CFP->getValue()), VT);
1732 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
1733 SDOperand N0 = N->getOperand(0);
1734 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1736 // fold (sint_to_fp c1) -> c1fp
1738 return DAG.getConstantFP(N0C->getSignExtended(), N->getValueType(0));
1742 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
1743 SDOperand N0 = N->getOperand(0);
1744 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1746 // fold (uint_to_fp c1) -> c1fp
1748 return DAG.getConstantFP(N0C->getValue(), N->getValueType(0));
1752 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
1753 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1755 // fold (fp_to_sint c1fp) -> c1
1757 return DAG.getConstant((int64_t)N0CFP->getValue(), N->getValueType(0));
1761 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
1762 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1764 // fold (fp_to_uint c1fp) -> c1
1766 return DAG.getConstant((uint64_t)N0CFP->getValue(), N->getValueType(0));
1770 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
1771 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1773 // fold (fp_round c1fp) -> c1fp
1775 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0));
1779 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
1780 SDOperand N0 = N->getOperand(0);
1781 MVT::ValueType VT = N->getValueType(0);
1782 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1783 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1785 // fold (fp_round_inreg c1fp) -> c1fp
1787 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
1788 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
1793 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
1794 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1796 // fold (fp_extend c1fp) -> c1fp
1798 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0));
1802 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
1803 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1804 // fold (neg c1) -> -c1
1806 return DAG.getConstantFP(-N0CFP->getValue(), N->getValueType(0));
1807 // fold (neg (sub x, y)) -> (sub y, x)
1808 if (N->getOperand(0).getOpcode() == ISD::SUB)
1809 return DAG.getNode(ISD::SUB, N->getValueType(0), N->getOperand(1),
1811 // fold (neg (neg x)) -> x
1812 if (N->getOperand(0).getOpcode() == ISD::FNEG)
1813 return N->getOperand(0).getOperand(0);
1817 SDOperand DAGCombiner::visitFABS(SDNode *N) {
1818 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1819 // fold (fabs c1) -> fabs(c1)
1821 return DAG.getConstantFP(fabs(N0CFP->getValue()), N->getValueType(0));
1822 // fold (fabs (fabs x)) -> (fabs x)
1823 if (N->getOperand(0).getOpcode() == ISD::FABS)
1824 return N->getOperand(0);
1825 // fold (fabs (fneg x)) -> (fabs x)
1826 if (N->getOperand(0).getOpcode() == ISD::FNEG)
1827 return DAG.getNode(ISD::FABS, N->getValueType(0),
1828 N->getOperand(0).getOperand(0));
1832 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
1833 SDOperand Chain = N->getOperand(0);
1834 SDOperand N1 = N->getOperand(1);
1835 SDOperand N2 = N->getOperand(2);
1836 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1838 // never taken branch, fold to chain
1839 if (N1C && N1C->isNullValue())
1841 // unconditional branch
1842 if (N1C && N1C->getValue() == 1)
1843 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
1847 SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) {
1848 SDOperand Chain = N->getOperand(0);
1849 SDOperand N1 = N->getOperand(1);
1850 SDOperand N2 = N->getOperand(2);
1851 SDOperand N3 = N->getOperand(3);
1852 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1854 // unconditional branch to true mbb
1855 if (N1C && N1C->getValue() == 1)
1856 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
1857 // unconditional branch to false mbb
1858 if (N1C && N1C->isNullValue())
1859 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3);
1863 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
1865 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
1866 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
1867 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
1869 // Use SimplifySetCC to simplify SETCC's.
1870 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
1871 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
1873 // fold br_cc true, dest -> br dest (unconditional branch)
1874 if (SCCC && SCCC->getValue())
1875 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
1877 // fold br_cc false, dest -> unconditional fall through
1878 if (SCCC && SCCC->isNullValue())
1879 return N->getOperand(0);
1880 // fold to a simpler setcc
1881 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
1882 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
1883 Simp.getOperand(2), Simp.getOperand(0),
1884 Simp.getOperand(1), N->getOperand(4));
1888 SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) {
1889 SDOperand Chain = N->getOperand(0);
1890 SDOperand CCN = N->getOperand(1);
1891 SDOperand LHS = N->getOperand(2);
1892 SDOperand RHS = N->getOperand(3);
1893 SDOperand N4 = N->getOperand(4);
1894 SDOperand N5 = N->getOperand(5);
1896 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS,
1897 cast<CondCodeSDNode>(CCN)->get(), false);
1898 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1900 // fold select_cc lhs, rhs, x, x, cc -> x
1902 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
1903 // fold select_cc true, x, y -> x
1904 if (SCCC && SCCC->getValue())
1905 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
1906 // fold select_cc false, x, y -> y
1907 if (SCCC && SCCC->isNullValue())
1908 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5);
1909 // fold to a simpler setcc
1910 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
1911 return DAG.getBR2Way_CC(Chain, SCC.getOperand(2), SCC.getOperand(0),
1912 SCC.getOperand(1), N4, N5);
1916 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
1917 SDOperand Chain = N->getOperand(0);
1918 SDOperand Ptr = N->getOperand(1);
1919 SDOperand SrcValue = N->getOperand(2);
1921 // If this load is directly stored, replace the load value with the stored
1923 // TODO: Handle store large -> read small portion.
1924 // TODO: Handle TRUNCSTORE/EXTLOAD
1925 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
1926 Chain.getOperand(1).getValueType() == N->getValueType(0))
1927 return CombineTo(N, Chain.getOperand(1), Chain);
1932 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
1933 SDOperand Chain = N->getOperand(0);
1934 SDOperand Value = N->getOperand(1);
1935 SDOperand Ptr = N->getOperand(2);
1936 SDOperand SrcValue = N->getOperand(3);
1938 // If this is a store that kills a previous store, remove the previous store.
1939 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
1940 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */) {
1941 // Create a new store of Value that replaces both stores.
1942 SDNode *PrevStore = Chain.Val;
1943 if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
1945 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other,
1946 PrevStore->getOperand(0), Value, Ptr,
1948 CombineTo(N, NewStore); // Nuke this store.
1949 CombineTo(PrevStore, NewStore); // Nuke the previous store.
1950 return SDOperand(N, 0);
1956 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
1957 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
1959 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
1960 cast<CondCodeSDNode>(N0.getOperand(2))->get());
1961 // If we got a simplified select_cc node back from SimplifySelectCC, then
1962 // break it down into a new SETCC node, and a new SELECT node, and then return
1963 // the SELECT node, since we were called with a SELECT node.
1965 // Check to see if we got a select_cc back (to turn into setcc/select).
1966 // Otherwise, just return whatever node we got back, like fabs.
1967 if (SCC.getOpcode() == ISD::SELECT_CC) {
1968 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
1969 SCC.getOperand(0), SCC.getOperand(1),
1971 WorkList.push_back(SETCC.Val);
1972 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
1973 SCC.getOperand(3), SETCC);
1980 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
1981 /// are the two values being selected between, see if we can simplify the
1984 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
1987 // If this is a select from two identical things, try to pull the operation
1988 // through the select.
1989 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
1991 std::cerr << "SELECT: ["; LHS.Val->dump();
1992 std::cerr << "] ["; RHS.Val->dump();
1996 // If this is a load and the token chain is identical, replace the select
1997 // of two loads with a load through a select of the address to load from.
1998 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
1999 // constants have been dropped into the constant pool.
2000 if ((LHS.getOpcode() == ISD::LOAD ||
2001 LHS.getOpcode() == ISD::EXTLOAD ||
2002 LHS.getOpcode() == ISD::ZEXTLOAD ||
2003 LHS.getOpcode() == ISD::SEXTLOAD) &&
2004 // Token chains must be identical.
2005 LHS.getOperand(0) == RHS.getOperand(0) &&
2006 // If this is an EXTLOAD, the VT's must match.
2007 (LHS.getOpcode() == ISD::LOAD ||
2008 LHS.getOperand(3) == RHS.getOperand(3))) {
2009 // FIXME: this conflates two src values, discarding one. This is not
2010 // the right thing to do, but nothing uses srcvalues now. When they do,
2011 // turn SrcValue into a list of locations.
2013 if (TheSelect->getOpcode() == ISD::SELECT)
2014 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(),
2015 TheSelect->getOperand(0), LHS.getOperand(1),
2018 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(),
2019 TheSelect->getOperand(0),
2020 TheSelect->getOperand(1),
2021 LHS.getOperand(1), RHS.getOperand(1),
2022 TheSelect->getOperand(4));
2025 if (LHS.getOpcode() == ISD::LOAD)
2026 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0),
2027 Addr, LHS.getOperand(2));
2029 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0),
2030 LHS.getOperand(0), Addr, LHS.getOperand(2),
2031 cast<VTSDNode>(LHS.getOperand(3))->getVT());
2032 // Users of the select now use the result of the load.
2033 CombineTo(TheSelect, Load);
2035 // Users of the old loads now use the new load's chain. We know the
2036 // old-load value is dead now.
2037 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
2038 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
2046 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
2047 SDOperand N2, SDOperand N3,
2050 MVT::ValueType VT = N2.getValueType();
2051 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
2052 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
2053 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
2054 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
2056 // Determine if the condition we're dealing with is constant
2057 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
2058 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
2060 // fold select_cc true, x, y -> x
2061 if (SCCC && SCCC->getValue())
2063 // fold select_cc false, x, y -> y
2064 if (SCCC && SCCC->getValue() == 0)
2067 // Check to see if we can simplify the select into an fabs node
2068 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
2069 // Allow either -0.0 or 0.0
2070 if (CFP->getValue() == 0.0) {
2071 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
2072 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
2073 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
2074 N2 == N3.getOperand(0))
2075 return DAG.getNode(ISD::FABS, VT, N0);
2077 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
2078 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
2079 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
2080 N2.getOperand(0) == N3)
2081 return DAG.getNode(ISD::FABS, VT, N3);
2085 // Check to see if we can perform the "gzip trick", transforming
2086 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
2087 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() &&
2088 MVT::isInteger(N0.getValueType()) &&
2089 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) {
2090 MVT::ValueType XType = N0.getValueType();
2091 MVT::ValueType AType = N2.getValueType();
2092 if (XType >= AType) {
2093 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
2094 // single-bit constant.
2095 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
2096 unsigned ShCtV = Log2_64(N2C->getValue());
2097 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
2098 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
2099 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
2100 WorkList.push_back(Shift.Val);
2101 if (XType > AType) {
2102 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
2103 WorkList.push_back(Shift.Val);
2105 return DAG.getNode(ISD::AND, AType, Shift, N2);
2107 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
2108 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2109 TLI.getShiftAmountTy()));
2110 WorkList.push_back(Shift.Val);
2111 if (XType > AType) {
2112 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
2113 WorkList.push_back(Shift.Val);
2115 return DAG.getNode(ISD::AND, AType, Shift, N2);
2119 // fold select C, 16, 0 -> shl C, 4
2120 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
2121 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
2122 // Get a SetCC of the condition
2123 // FIXME: Should probably make sure that setcc is legal if we ever have a
2124 // target where it isn't.
2125 SDOperand Temp, SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
2126 WorkList.push_back(SCC.Val);
2127 // cast from setcc result type to select result type
2129 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
2131 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
2132 WorkList.push_back(Temp.Val);
2133 // shl setcc result by log2 n2c
2134 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
2135 DAG.getConstant(Log2_64(N2C->getValue()),
2136 TLI.getShiftAmountTy()));
2139 // Check to see if this is the equivalent of setcc
2140 // FIXME: Turn all of these into setcc if setcc if setcc is legal
2141 // otherwise, go ahead with the folds.
2142 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
2143 MVT::ValueType XType = N0.getValueType();
2144 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
2145 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
2146 if (Res.getValueType() != VT)
2147 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
2151 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
2152 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
2153 TLI.isOperationLegal(ISD::CTLZ, XType)) {
2154 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
2155 return DAG.getNode(ISD::SRL, XType, Ctlz,
2156 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
2157 TLI.getShiftAmountTy()));
2159 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
2160 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
2161 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
2163 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
2164 DAG.getConstant(~0ULL, XType));
2165 return DAG.getNode(ISD::SRL, XType,
2166 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
2167 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2168 TLI.getShiftAmountTy()));
2170 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
2171 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
2172 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
2173 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2174 TLI.getShiftAmountTy()));
2175 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
2179 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
2180 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2181 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
2182 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
2183 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
2184 MVT::ValueType XType = N0.getValueType();
2185 if (SubC->isNullValue() && MVT::isInteger(XType)) {
2186 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
2187 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2188 TLI.getShiftAmountTy()));
2189 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
2190 WorkList.push_back(Shift.Val);
2191 WorkList.push_back(Add.Val);
2192 return DAG.getNode(ISD::XOR, XType, Add, Shift);
2200 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
2201 SDOperand N1, ISD::CondCode Cond,
2202 bool foldBooleans) {
2203 // These setcc operations always fold.
2207 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
2209 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
2212 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
2213 uint64_t C1 = N1C->getValue();
2214 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
2215 uint64_t C0 = N0C->getValue();
2217 // Sign extend the operands if required
2218 if (ISD::isSignedIntSetCC(Cond)) {
2219 C0 = N0C->getSignExtended();
2220 C1 = N1C->getSignExtended();
2224 default: assert(0 && "Unknown integer setcc!");
2225 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
2226 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
2227 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
2228 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
2229 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
2230 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
2231 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
2232 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
2233 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
2234 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
2237 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2238 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2239 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
2241 // If the comparison constant has bits in the upper part, the
2242 // zero-extended value could never match.
2243 if (C1 & (~0ULL << InSize)) {
2244 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
2248 case ISD::SETEQ: return DAG.getConstant(0, VT);
2251 case ISD::SETNE: return DAG.getConstant(1, VT);
2254 // True if the sign bit of C1 is set.
2255 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
2258 // True if the sign bit of C1 isn't set.
2259 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
2265 // Otherwise, we can perform the comparison with the low bits.
2273 return DAG.getSetCC(VT, N0.getOperand(0),
2274 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
2277 break; // todo, be more careful with signed comparisons
2279 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2280 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2281 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2282 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
2283 MVT::ValueType ExtDstTy = N0.getValueType();
2284 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
2286 // If the extended part has any inconsistent bits, it cannot ever
2287 // compare equal. In other words, they have to be all ones or all
2290 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
2291 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
2292 return DAG.getConstant(Cond == ISD::SETNE, VT);
2295 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
2296 if (Op0Ty == ExtSrcTy) {
2297 ZextOp = N0.getOperand(0);
2299 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
2300 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
2301 DAG.getConstant(Imm, Op0Ty));
2303 WorkList.push_back(ZextOp.Val);
2304 // Otherwise, make this a use of a zext.
2305 return DAG.getSetCC(VT, ZextOp,
2306 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
2311 uint64_t MinVal, MaxVal;
2312 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
2313 if (ISD::isSignedIntSetCC(Cond)) {
2314 MinVal = 1ULL << (OperandBitSize-1);
2315 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
2316 MaxVal = ~0ULL >> (65-OperandBitSize);
2321 MaxVal = ~0ULL >> (64-OperandBitSize);
2324 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2325 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2326 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2327 --C1; // X >= C0 --> X > (C0-1)
2328 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2329 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2332 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2333 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2334 ++C1; // X <= C0 --> X < (C0+1)
2335 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2336 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2339 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2340 return DAG.getConstant(0, VT); // X < MIN --> false
2342 // Canonicalize setgt X, Min --> setne X, Min
2343 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2344 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
2346 // If we have setult X, 1, turn it into seteq X, 0
2347 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2348 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
2350 // If we have setugt X, Max-1, turn it into seteq X, Max
2351 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2352 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
2355 // If we have "setcc X, C0", check to see if we can shrink the immediate
2358 // SETUGT X, SINTMAX -> SETLT X, 0
2359 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
2360 C1 == (~0ULL >> (65-OperandBitSize)))
2361 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
2364 // FIXME: Implement the rest of these.
2366 // Fold bit comparisons when we can.
2367 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2368 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
2369 if (ConstantSDNode *AndRHS =
2370 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2371 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2372 // Perform the xform if the AND RHS is a single bit.
2373 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
2374 return DAG.getNode(ISD::SRL, VT, N0,
2375 DAG.getConstant(Log2_64(AndRHS->getValue()),
2376 TLI.getShiftAmountTy()));
2378 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
2379 // (X & 8) == 8 --> (X & 8) >> 3
2380 // Perform the xform if C1 is a single bit.
2381 if ((C1 & (C1-1)) == 0) {
2382 return DAG.getNode(ISD::SRL, VT, N0,
2383 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
2388 } else if (isa<ConstantSDNode>(N0.Val)) {
2389 // Ensure that the constant occurs on the RHS.
2390 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2393 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
2394 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
2395 double C0 = N0C->getValue(), C1 = N1C->getValue();
2398 default: break; // FIXME: Implement the rest of these!
2399 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
2400 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
2401 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
2402 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
2403 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
2404 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
2407 // Ensure that the constant occurs on the RHS.
2408 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2412 // We can always fold X == Y for integer setcc's.
2413 if (MVT::isInteger(N0.getValueType()))
2414 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2415 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2416 if (UOF == 2) // FP operators that are undefined on NaNs.
2417 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2418 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2419 return DAG.getConstant(UOF, VT);
2420 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2421 // if it is not already.
2422 ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO;
2423 if (NewCond != Cond)
2424 return DAG.getSetCC(VT, N0, N1, NewCond);
2427 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2428 MVT::isInteger(N0.getValueType())) {
2429 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2430 N0.getOpcode() == ISD::XOR) {
2431 // Simplify (X+Y) == (X+Z) --> Y == Z
2432 if (N0.getOpcode() == N1.getOpcode()) {
2433 if (N0.getOperand(0) == N1.getOperand(0))
2434 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
2435 if (N0.getOperand(1) == N1.getOperand(1))
2436 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
2437 if (isCommutativeBinOp(N0.getOpcode())) {
2438 // If X op Y == Y op X, try other combinations.
2439 if (N0.getOperand(0) == N1.getOperand(1))
2440 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
2441 if (N0.getOperand(1) == N1.getOperand(0))
2442 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
2446 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. Common for condcodes.
2447 if (N0.getOpcode() == ISD::XOR)
2448 if (ConstantSDNode *XORC = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2449 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2450 // If we know that all of the inverted bits are zero, don't bother
2451 // performing the inversion.
2452 if (MaskedValueIsZero(N0.getOperand(0), ~XORC->getValue(), TLI))
2453 return DAG.getSetCC(VT, N0.getOperand(0),
2454 DAG.getConstant(XORC->getValue()^RHSC->getValue(),
2455 N0.getValueType()), Cond);
2458 // Simplify (X+Z) == X --> Z == 0
2459 if (N0.getOperand(0) == N1)
2460 return DAG.getSetCC(VT, N0.getOperand(1),
2461 DAG.getConstant(0, N0.getValueType()), Cond);
2462 if (N0.getOperand(1) == N1) {
2463 if (isCommutativeBinOp(N0.getOpcode()))
2464 return DAG.getSetCC(VT, N0.getOperand(0),
2465 DAG.getConstant(0, N0.getValueType()), Cond);
2467 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2468 // (Z-X) == X --> Z == X<<1
2469 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
2471 DAG.getConstant(1,TLI.getShiftAmountTy()));
2472 WorkList.push_back(SH.Val);
2473 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
2478 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2479 N1.getOpcode() == ISD::XOR) {
2480 // Simplify X == (X+Z) --> Z == 0
2481 if (N1.getOperand(0) == N0) {
2482 return DAG.getSetCC(VT, N1.getOperand(1),
2483 DAG.getConstant(0, N1.getValueType()), Cond);
2484 } else if (N1.getOperand(1) == N0) {
2485 if (isCommutativeBinOp(N1.getOpcode())) {
2486 return DAG.getSetCC(VT, N1.getOperand(0),
2487 DAG.getConstant(0, N1.getValueType()), Cond);
2489 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2490 // X == (Z-X) --> X<<1 == Z
2491 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
2492 DAG.getConstant(1,TLI.getShiftAmountTy()));
2493 WorkList.push_back(SH.Val);
2494 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
2500 // Fold away ALL boolean setcc's.
2502 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2504 default: assert(0 && "Unknown integer setcc!");
2505 case ISD::SETEQ: // X == Y -> (X^Y)^1
2506 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2507 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
2508 WorkList.push_back(Temp.Val);
2510 case ISD::SETNE: // X != Y --> (X^Y)
2511 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2513 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
2514 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
2515 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2516 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
2517 WorkList.push_back(Temp.Val);
2519 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
2520 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
2521 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2522 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
2523 WorkList.push_back(Temp.Val);
2525 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
2526 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
2527 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2528 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
2529 WorkList.push_back(Temp.Val);
2531 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
2532 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
2533 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2534 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
2537 if (VT != MVT::i1) {
2538 WorkList.push_back(N0.Val);
2539 // FIXME: If running after legalize, we probably can't do this.
2540 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2545 // Could not fold it.
2549 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2550 /// return a DAG expression to select that will generate the same value by
2551 /// multiplying by a magic number. See:
2552 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2553 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
2554 MVT::ValueType VT = N->getValueType(0);
2555 assert((VT == MVT::i32 || VT == MVT::i64) &&
2556 "BuildSDIV only operates on i32 or i64!");
2558 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
2559 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
2561 // Multiply the numerator (operand 0) by the magic value
2562 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
2563 DAG.getConstant(magics.m, VT));
2564 // If d > 0 and m < 0, add the numerator
2565 if (d > 0 && magics.m < 0) {
2566 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
2567 WorkList.push_back(Q.Val);
2569 // If d < 0 and m > 0, subtract the numerator.
2570 if (d < 0 && magics.m > 0) {
2571 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
2572 WorkList.push_back(Q.Val);
2574 // Shift right algebraic if shift value is nonzero
2576 Q = DAG.getNode(ISD::SRA, VT, Q,
2577 DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
2578 WorkList.push_back(Q.Val);
2580 // Extract the sign bit and add it to the quotient
2582 DAG.getNode(ISD::SRL, MVT::i32, Q,
2583 DAG.getConstant(MVT::getSizeInBits(VT)-1,
2584 TLI.getShiftAmountTy()));
2585 WorkList.push_back(T.Val);
2586 return DAG.getNode(ISD::ADD, VT, Q, T);
2589 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2590 /// return a DAG expression to select that will generate the same value by
2591 /// multiplying by a magic number. See:
2592 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2593 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
2594 MVT::ValueType VT = N->getValueType(0);
2595 assert((VT == MVT::i32 || VT == MVT::i64) &&
2596 "BuildUDIV only operates on i32 or i64!");
2598 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
2599 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
2601 // Multiply the numerator (operand 0) by the magic value
2602 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
2603 DAG.getConstant(magics.m, VT));
2604 WorkList.push_back(Q.Val);
2606 if (magics.a == 0) {
2607 return DAG.getNode(ISD::SRL, VT, Q,
2608 DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
2610 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
2611 WorkList.push_back(NPQ.Val);
2612 NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
2613 DAG.getConstant(1, TLI.getShiftAmountTy()));
2614 WorkList.push_back(NPQ.Val);
2615 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
2616 WorkList.push_back(NPQ.Val);
2617 return DAG.getNode(ISD::SRL, VT, NPQ,
2618 DAG.getConstant(magics.s-1, TLI.getShiftAmountTy()));
2622 // SelectionDAG::Combine - This is the entry point for the file.
2624 void SelectionDAG::Combine(bool RunningAfterLegalize) {
2625 /// run - This is the main entry point to this class.
2627 DAGCombiner(*this).Run(RunningAfterLegalize);