1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Analysis/AliasAnalysis.h"
27 #include "llvm/Target/TargetData.h"
28 #include "llvm/Target/TargetFrameInfo.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/ADT/SmallPtrSet.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
42 STATISTIC(NodesCombined , "Number of dag nodes combined");
43 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
44 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
45 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
49 CombinerAA("combiner-alias-analysis", cl::Hidden,
50 cl::desc("Turn on alias analysis during testing"));
53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
54 cl::desc("Include global information in alias analysis"));
56 //------------------------------ DAGCombiner ---------------------------------//
60 const TargetLowering &TLI;
62 CodeGenOpt::Level OptLevel;
66 // Worklist of all of the nodes that need to be simplified.
67 std::vector<SDNode*> WorkList;
69 // AA - Used for DAG load/store alias analysis.
72 /// AddUsersToWorkList - When an instruction is simplified, add all users of
73 /// the instruction to the work lists because they might get more simplified
76 void AddUsersToWorkList(SDNode *N) {
77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
82 /// visit - call the node-specific routine that knows how to fold each
83 /// particular type of node.
84 SDValue visit(SDNode *N);
87 /// AddToWorkList - Add to the work list making sure it's instance is at the
88 /// the back (next to be processed.)
89 void AddToWorkList(SDNode *N) {
90 removeFromWorkList(N);
91 WorkList.push_back(N);
94 /// removeFromWorkList - remove all instances of N from the worklist.
96 void removeFromWorkList(SDNode *N) {
97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
105 return CombineTo(N, &Res, 1, AddTo);
108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
110 SDValue To[] = { Res0, Res1 };
111 return CombineTo(N, To, 2, AddTo);
114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
118 /// SimplifyDemandedBits - Check the specified integer node value to see if
119 /// it can be simplified or if things it uses can be simplified by bit
120 /// propagation. If so, return true.
121 bool SimplifyDemandedBits(SDValue Op) {
122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
123 APInt Demanded = APInt::getAllOnesValue(BitWidth);
124 return SimplifyDemandedBits(Op, Demanded);
127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
129 bool CombineToPreIndexedLoadStore(SDNode *N);
130 bool CombineToPostIndexedLoadStore(SDNode *N);
132 SDValue PromoteIntBinOp(SDValue Op);
134 /// combine - call the node-specific routine that knows how to fold each
135 /// particular type of node. If that doesn't do anything, try the
136 /// target-specific DAG combines.
137 SDValue combine(SDNode *N);
139 // Visitation implementation - Implement dag node combining for different
140 // node types. The semantics are as follows:
142 // SDValue.getNode() == 0 - No change was made
143 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
144 // otherwise - N should be replaced by the returned Operand.
146 SDValue visitTokenFactor(SDNode *N);
147 SDValue visitMERGE_VALUES(SDNode *N);
148 SDValue visitADD(SDNode *N);
149 SDValue visitSUB(SDNode *N);
150 SDValue visitADDC(SDNode *N);
151 SDValue visitADDE(SDNode *N);
152 SDValue visitMUL(SDNode *N);
153 SDValue visitSDIV(SDNode *N);
154 SDValue visitUDIV(SDNode *N);
155 SDValue visitSREM(SDNode *N);
156 SDValue visitUREM(SDNode *N);
157 SDValue visitMULHU(SDNode *N);
158 SDValue visitMULHS(SDNode *N);
159 SDValue visitSMUL_LOHI(SDNode *N);
160 SDValue visitUMUL_LOHI(SDNode *N);
161 SDValue visitSDIVREM(SDNode *N);
162 SDValue visitUDIVREM(SDNode *N);
163 SDValue visitAND(SDNode *N);
164 SDValue visitOR(SDNode *N);
165 SDValue visitXOR(SDNode *N);
166 SDValue SimplifyVBinOp(SDNode *N);
167 SDValue visitSHL(SDNode *N);
168 SDValue visitSRA(SDNode *N);
169 SDValue visitSRL(SDNode *N);
170 SDValue visitCTLZ(SDNode *N);
171 SDValue visitCTTZ(SDNode *N);
172 SDValue visitCTPOP(SDNode *N);
173 SDValue visitSELECT(SDNode *N);
174 SDValue visitSELECT_CC(SDNode *N);
175 SDValue visitSETCC(SDNode *N);
176 SDValue visitSIGN_EXTEND(SDNode *N);
177 SDValue visitZERO_EXTEND(SDNode *N);
178 SDValue visitANY_EXTEND(SDNode *N);
179 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
180 SDValue visitTRUNCATE(SDNode *N);
181 SDValue visitBIT_CONVERT(SDNode *N);
182 SDValue visitBUILD_PAIR(SDNode *N);
183 SDValue visitFADD(SDNode *N);
184 SDValue visitFSUB(SDNode *N);
185 SDValue visitFMUL(SDNode *N);
186 SDValue visitFDIV(SDNode *N);
187 SDValue visitFREM(SDNode *N);
188 SDValue visitFCOPYSIGN(SDNode *N);
189 SDValue visitSINT_TO_FP(SDNode *N);
190 SDValue visitUINT_TO_FP(SDNode *N);
191 SDValue visitFP_TO_SINT(SDNode *N);
192 SDValue visitFP_TO_UINT(SDNode *N);
193 SDValue visitFP_ROUND(SDNode *N);
194 SDValue visitFP_ROUND_INREG(SDNode *N);
195 SDValue visitFP_EXTEND(SDNode *N);
196 SDValue visitFNEG(SDNode *N);
197 SDValue visitFABS(SDNode *N);
198 SDValue visitBRCOND(SDNode *N);
199 SDValue visitBR_CC(SDNode *N);
200 SDValue visitLOAD(SDNode *N);
201 SDValue visitSTORE(SDNode *N);
202 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
203 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
204 SDValue visitBUILD_VECTOR(SDNode *N);
205 SDValue visitCONCAT_VECTORS(SDNode *N);
206 SDValue visitVECTOR_SHUFFLE(SDNode *N);
208 SDValue XformToShuffleWithZero(SDNode *N);
209 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
211 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
213 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
214 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
215 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
216 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
217 SDValue N3, ISD::CondCode CC,
218 bool NotExtCompare = false);
219 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
220 DebugLoc DL, bool foldBooleans = true);
221 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
223 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
224 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT);
225 SDValue BuildSDIV(SDNode *N);
226 SDValue BuildUDIV(SDNode *N);
227 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
228 SDValue ReduceLoadWidth(SDNode *N);
229 SDValue ReduceLoadOpStoreWidth(SDNode *N);
231 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
233 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
234 /// looking for aliasing nodes and adding them to the Aliases vector.
235 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
236 SmallVector<SDValue, 8> &Aliases);
238 /// isAlias - Return true if there is any possibility that the two addresses
240 bool isAlias(SDValue Ptr1, int64_t Size1,
241 const Value *SrcValue1, int SrcValueOffset1,
242 unsigned SrcValueAlign1,
243 SDValue Ptr2, int64_t Size2,
244 const Value *SrcValue2, int SrcValueOffset2,
245 unsigned SrcValueAlign2) const;
247 /// FindAliasInfo - Extracts the relevant alias information from the memory
248 /// node. Returns true if the operand was a load.
249 bool FindAliasInfo(SDNode *N,
250 SDValue &Ptr, int64_t &Size,
251 const Value *&SrcValue, int &SrcValueOffset,
252 unsigned &SrcValueAlignment) const;
254 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
255 /// looking for a better chain (aliasing node.)
256 SDValue FindBetterChain(SDNode *N, SDValue Chain);
259 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
260 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted),
261 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
263 /// Run - runs the dag combiner on all nodes in the work list
264 void Run(CombineLevel AtLevel);
266 SelectionDAG &getDAG() const { return DAG; }
268 /// getShiftAmountTy - Returns a type large enough to hold any valid
269 /// shift amount - before type legalization these can be huge.
270 EVT getShiftAmountTy() {
271 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy();
274 /// isTypeLegal - This method returns true if we are running before type
275 /// legalization or if the specified VT is legal.
276 bool isTypeLegal(const EVT &VT) {
277 if (!LegalTypes) return true;
278 return TLI.isTypeLegal(VT);
285 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
286 /// nodes from the worklist.
287 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
290 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
292 virtual void NodeDeleted(SDNode *N, SDNode *E) {
293 DC.removeFromWorkList(N);
296 virtual void NodeUpdated(SDNode *N) {
302 //===----------------------------------------------------------------------===//
303 // TargetLowering::DAGCombinerInfo implementation
304 //===----------------------------------------------------------------------===//
306 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
307 ((DAGCombiner*)DC)->AddToWorkList(N);
310 SDValue TargetLowering::DAGCombinerInfo::
311 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
312 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
315 SDValue TargetLowering::DAGCombinerInfo::
316 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
317 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
321 SDValue TargetLowering::DAGCombinerInfo::
322 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
323 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
326 void TargetLowering::DAGCombinerInfo::
327 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
328 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
331 //===----------------------------------------------------------------------===//
333 //===----------------------------------------------------------------------===//
335 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
336 /// specified expression for the same cost as the expression itself, or 2 if we
337 /// can compute the negated form more cheaply than the expression itself.
338 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
339 unsigned Depth = 0) {
340 // No compile time optimizations on this type.
341 if (Op.getValueType() == MVT::ppcf128)
344 // fneg is removable even if it has multiple uses.
345 if (Op.getOpcode() == ISD::FNEG) return 2;
347 // Don't allow anything with multiple uses.
348 if (!Op.hasOneUse()) return 0;
350 // Don't recurse exponentially.
351 if (Depth > 6) return 0;
353 switch (Op.getOpcode()) {
354 default: return false;
355 case ISD::ConstantFP:
356 // Don't invert constant FP values after legalize. The negated constant
357 // isn't necessarily legal.
358 return LegalOperations ? 0 : 1;
360 // FIXME: determine better conditions for this xform.
361 if (!UnsafeFPMath) return 0;
363 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
364 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
366 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
367 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
369 // We can't turn -(A-B) into B-A when we honor signed zeros.
370 if (!UnsafeFPMath) return 0;
372 // fold (fneg (fsub A, B)) -> (fsub B, A)
377 if (HonorSignDependentRoundingFPMath()) return 0;
379 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
380 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
383 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
388 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1);
392 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
393 /// returns the newly negated expression.
394 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
395 bool LegalOperations, unsigned Depth = 0) {
396 // fneg is removable even if it has multiple uses.
397 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
399 // Don't allow anything with multiple uses.
400 assert(Op.hasOneUse() && "Unknown reuse!");
402 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
403 switch (Op.getOpcode()) {
404 default: llvm_unreachable("Unknown code");
405 case ISD::ConstantFP: {
406 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
408 return DAG.getConstantFP(V, Op.getValueType());
411 // FIXME: determine better conditions for this xform.
412 assert(UnsafeFPMath);
414 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
415 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
416 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
417 GetNegatedExpression(Op.getOperand(0), DAG,
418 LegalOperations, Depth+1),
420 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
421 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
422 GetNegatedExpression(Op.getOperand(1), DAG,
423 LegalOperations, Depth+1),
426 // We can't turn -(A-B) into B-A when we honor signed zeros.
427 assert(UnsafeFPMath);
429 // fold (fneg (fsub 0, B)) -> B
430 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
431 if (N0CFP->getValueAPF().isZero())
432 return Op.getOperand(1);
434 // fold (fneg (fsub A, B)) -> (fsub B, A)
435 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
436 Op.getOperand(1), Op.getOperand(0));
440 assert(!HonorSignDependentRoundingFPMath());
442 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
443 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
444 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
445 GetNegatedExpression(Op.getOperand(0), DAG,
446 LegalOperations, Depth+1),
449 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
450 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
452 GetNegatedExpression(Op.getOperand(1), DAG,
453 LegalOperations, Depth+1));
457 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
458 GetNegatedExpression(Op.getOperand(0), DAG,
459 LegalOperations, Depth+1));
461 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
462 GetNegatedExpression(Op.getOperand(0), DAG,
463 LegalOperations, Depth+1),
469 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
470 // that selects between the values 1 and 0, making it equivalent to a setcc.
471 // Also, set the incoming LHS, RHS, and CC references to the appropriate
472 // nodes based on the type of node we are checking. This simplifies life a
473 // bit for the callers.
474 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
476 if (N.getOpcode() == ISD::SETCC) {
477 LHS = N.getOperand(0);
478 RHS = N.getOperand(1);
479 CC = N.getOperand(2);
482 if (N.getOpcode() == ISD::SELECT_CC &&
483 N.getOperand(2).getOpcode() == ISD::Constant &&
484 N.getOperand(3).getOpcode() == ISD::Constant &&
485 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
486 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
487 LHS = N.getOperand(0);
488 RHS = N.getOperand(1);
489 CC = N.getOperand(4);
495 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
496 // one use. If this is true, it allows the users to invert the operation for
497 // free when it is profitable to do so.
498 static bool isOneUseSetCC(SDValue N) {
500 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
505 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
506 SDValue N0, SDValue N1) {
507 EVT VT = N0.getValueType();
508 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
509 if (isa<ConstantSDNode>(N1)) {
510 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
512 DAG.FoldConstantArithmetic(Opc, VT,
513 cast<ConstantSDNode>(N0.getOperand(1)),
514 cast<ConstantSDNode>(N1));
515 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
516 } else if (N0.hasOneUse()) {
517 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
518 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
519 N0.getOperand(0), N1);
520 AddToWorkList(OpNode.getNode());
521 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
525 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
526 if (isa<ConstantSDNode>(N0)) {
527 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
529 DAG.FoldConstantArithmetic(Opc, VT,
530 cast<ConstantSDNode>(N1.getOperand(1)),
531 cast<ConstantSDNode>(N0));
532 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
533 } else if (N1.hasOneUse()) {
534 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
535 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
536 N1.getOperand(0), N0);
537 AddToWorkList(OpNode.getNode());
538 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
545 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
547 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
549 DEBUG(dbgs() << "\nReplacing.1 ";
551 dbgs() << "\nWith: ";
552 To[0].getNode()->dump(&DAG);
553 dbgs() << " and " << NumTo-1 << " other values\n";
554 for (unsigned i = 0, e = NumTo; i != e; ++i)
555 assert((!To[i].getNode() ||
556 N->getValueType(i) == To[i].getValueType()) &&
557 "Cannot combine value to value of different type!"));
558 WorkListRemover DeadNodes(*this);
559 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
562 // Push the new nodes and any users onto the worklist
563 for (unsigned i = 0, e = NumTo; i != e; ++i) {
564 if (To[i].getNode()) {
565 AddToWorkList(To[i].getNode());
566 AddUsersToWorkList(To[i].getNode());
571 // Finally, if the node is now dead, remove it from the graph. The node
572 // may not be dead if the replacement process recursively simplified to
573 // something else needing this node.
574 if (N->use_empty()) {
575 // Nodes can be reintroduced into the worklist. Make sure we do not
576 // process a node that has been replaced.
577 removeFromWorkList(N);
579 // Finally, since the node is now dead, remove it from the graph.
582 return SDValue(N, 0);
586 DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &
588 // Replace all uses. If any nodes become isomorphic to other nodes and
589 // are deleted, make sure to remove them from our worklist.
590 WorkListRemover DeadNodes(*this);
591 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
593 // Push the new node and any (possibly new) users onto the worklist.
594 AddToWorkList(TLO.New.getNode());
595 AddUsersToWorkList(TLO.New.getNode());
597 // Finally, if the node is now dead, remove it from the graph. The node
598 // may not be dead if the replacement process recursively simplified to
599 // something else needing this node.
600 if (TLO.Old.getNode()->use_empty()) {
601 removeFromWorkList(TLO.Old.getNode());
603 // If the operands of this node are only used by the node, they will now
604 // be dead. Make sure to visit them first to delete dead nodes early.
605 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
606 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
607 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
609 DAG.DeleteNode(TLO.Old.getNode());
613 /// SimplifyDemandedBits - Check the specified integer node value to see if
614 /// it can be simplified or if things it uses can be simplified by bit
615 /// propagation. If so, return true.
616 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
617 TargetLowering::TargetLoweringOpt TLO(DAG);
618 APInt KnownZero, KnownOne;
619 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
623 AddToWorkList(Op.getNode());
625 // Replace the old value with the new one.
627 DEBUG(dbgs() << "\nReplacing.2 ";
628 TLO.Old.getNode()->dump(&DAG);
629 dbgs() << "\nWith: ";
630 TLO.New.getNode()->dump(&DAG);
633 CommitTargetLoweringOpt(TLO);
637 static SDValue PromoteOperand(SDValue Op, EVT PVT, SelectionDAG &DAG) {
638 unsigned Opc = ISD::ZERO_EXTEND;
639 if (Op.getOpcode() == ISD::Constant) {
640 // Zero extend things like i1, sign extend everything else. It shouldn't
641 // matter in theory which one we pick, but this tends to give better code?
642 // See DAGTypeLegalizer::PromoteIntRes_Constant.
643 if (Op.getValueType().isByteSized())
644 Opc = ISD::SIGN_EXTEND;
646 return DAG.getNode(Opc, Op.getDebugLoc(), PVT, Op);
649 /// PromoteIntBinOp - Promote the specified integer binary operation if the
650 /// target indicates it is beneficial. e.g. On x86, it's usually better to
651 /// promote i16 operations to i32 since i16 instructions are longer.
652 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
653 if (!LegalOperations)
656 EVT VT = Op.getValueType();
657 if (VT.isVector() || !VT.isInteger())
661 if (TLI.PerformDAGCombinePromotion(Op, PVT)) {
662 assert(PVT != VT && "Don't know what type to promote to!");
664 SDValue N0 = PromoteOperand(Op.getOperand(0), PVT, DAG);
665 AddToWorkList(N0.getNode());
667 SDValue N1 = PromoteOperand(Op.getOperand(1), PVT, DAG);
668 AddToWorkList(N1.getNode());
670 DebugLoc dl = Op.getDebugLoc();
671 return DAG.getNode(ISD::TRUNCATE, dl, VT,
672 DAG.getNode(Op.getOpcode(), dl, PVT, N0, N1));
677 //===----------------------------------------------------------------------===//
678 // Main DAG Combiner implementation
679 //===----------------------------------------------------------------------===//
681 void DAGCombiner::Run(CombineLevel AtLevel) {
682 // set the instance variables, so that the various visit routines may use it.
684 LegalOperations = Level >= NoIllegalOperations;
685 LegalTypes = Level >= NoIllegalTypes;
687 // Add all the dag nodes to the worklist.
688 WorkList.reserve(DAG.allnodes_size());
689 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
690 E = DAG.allnodes_end(); I != E; ++I)
691 WorkList.push_back(I);
693 // Create a dummy node (which is not added to allnodes), that adds a reference
694 // to the root node, preventing it from being deleted, and tracking any
695 // changes of the root.
696 HandleSDNode Dummy(DAG.getRoot());
698 // The root of the dag may dangle to deleted nodes until the dag combiner is
699 // done. Set it to null to avoid confusion.
700 DAG.setRoot(SDValue());
702 // while the worklist isn't empty, inspect the node on the end of it and
703 // try and combine it.
704 while (!WorkList.empty()) {
705 SDNode *N = WorkList.back();
708 // If N has no uses, it is dead. Make sure to revisit all N's operands once
709 // N is deleted from the DAG, since they too may now be dead or may have a
710 // reduced number of uses, allowing other xforms.
711 if (N->use_empty() && N != &Dummy) {
712 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
713 AddToWorkList(N->getOperand(i).getNode());
719 SDValue RV = combine(N);
721 if (RV.getNode() == 0)
726 // If we get back the same node we passed in, rather than a new node or
727 // zero, we know that the node must have defined multiple values and
728 // CombineTo was used. Since CombineTo takes care of the worklist
729 // mechanics for us, we have no work to do in this case.
730 if (RV.getNode() == N)
733 assert(N->getOpcode() != ISD::DELETED_NODE &&
734 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
735 "Node was deleted but visit returned new node!");
737 DEBUG(dbgs() << "\nReplacing.3 ";
739 dbgs() << "\nWith: ";
740 RV.getNode()->dump(&DAG);
742 WorkListRemover DeadNodes(*this);
743 if (N->getNumValues() == RV.getNode()->getNumValues())
744 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
746 assert(N->getValueType(0) == RV.getValueType() &&
747 N->getNumValues() == 1 && "Type mismatch");
749 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
752 // Push the new node and any users onto the worklist
753 AddToWorkList(RV.getNode());
754 AddUsersToWorkList(RV.getNode());
756 // Add any uses of the old node to the worklist in case this node is the
757 // last one that uses them. They may become dead after this node is
759 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
760 AddToWorkList(N->getOperand(i).getNode());
762 // Finally, if the node is now dead, remove it from the graph. The node
763 // may not be dead if the replacement process recursively simplified to
764 // something else needing this node.
765 if (N->use_empty()) {
766 // Nodes can be reintroduced into the worklist. Make sure we do not
767 // process a node that has been replaced.
768 removeFromWorkList(N);
770 // Finally, since the node is now dead, remove it from the graph.
775 // If the root changed (e.g. it was a dead load, update the root).
776 DAG.setRoot(Dummy.getValue());
779 SDValue DAGCombiner::visit(SDNode *N) {
780 switch(N->getOpcode()) {
782 case ISD::TokenFactor: return visitTokenFactor(N);
783 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
784 case ISD::ADD: return visitADD(N);
785 case ISD::SUB: return visitSUB(N);
786 case ISD::ADDC: return visitADDC(N);
787 case ISD::ADDE: return visitADDE(N);
788 case ISD::MUL: return visitMUL(N);
789 case ISD::SDIV: return visitSDIV(N);
790 case ISD::UDIV: return visitUDIV(N);
791 case ISD::SREM: return visitSREM(N);
792 case ISD::UREM: return visitUREM(N);
793 case ISD::MULHU: return visitMULHU(N);
794 case ISD::MULHS: return visitMULHS(N);
795 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
796 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
797 case ISD::SDIVREM: return visitSDIVREM(N);
798 case ISD::UDIVREM: return visitUDIVREM(N);
799 case ISD::AND: return visitAND(N);
800 case ISD::OR: return visitOR(N);
801 case ISD::XOR: return visitXOR(N);
802 case ISD::SHL: return visitSHL(N);
803 case ISD::SRA: return visitSRA(N);
804 case ISD::SRL: return visitSRL(N);
805 case ISD::CTLZ: return visitCTLZ(N);
806 case ISD::CTTZ: return visitCTTZ(N);
807 case ISD::CTPOP: return visitCTPOP(N);
808 case ISD::SELECT: return visitSELECT(N);
809 case ISD::SELECT_CC: return visitSELECT_CC(N);
810 case ISD::SETCC: return visitSETCC(N);
811 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
812 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
813 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
814 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
815 case ISD::TRUNCATE: return visitTRUNCATE(N);
816 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
817 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
818 case ISD::FADD: return visitFADD(N);
819 case ISD::FSUB: return visitFSUB(N);
820 case ISD::FMUL: return visitFMUL(N);
821 case ISD::FDIV: return visitFDIV(N);
822 case ISD::FREM: return visitFREM(N);
823 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
824 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
825 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
826 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
827 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
828 case ISD::FP_ROUND: return visitFP_ROUND(N);
829 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
830 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
831 case ISD::FNEG: return visitFNEG(N);
832 case ISD::FABS: return visitFABS(N);
833 case ISD::BRCOND: return visitBRCOND(N);
834 case ISD::BR_CC: return visitBR_CC(N);
835 case ISD::LOAD: return visitLOAD(N);
836 case ISD::STORE: return visitSTORE(N);
837 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
838 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
839 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
840 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
841 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
846 SDValue DAGCombiner::combine(SDNode *N) {
847 SDValue RV = visit(N);
849 // If nothing happened, try a target-specific DAG combine.
850 if (RV.getNode() == 0) {
851 assert(N->getOpcode() != ISD::DELETED_NODE &&
852 "Node was deleted but visit returned NULL!");
854 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
855 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
857 // Expose the DAG combiner to the target combiner impls.
858 TargetLowering::DAGCombinerInfo
859 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
861 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
865 // If N is a commutative binary node, try commuting it to enable more
867 if (RV.getNode() == 0 &&
868 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
869 N->getNumValues() == 1) {
870 SDValue N0 = N->getOperand(0);
871 SDValue N1 = N->getOperand(1);
873 // Constant operands are canonicalized to RHS.
874 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
875 SDValue Ops[] = { N1, N0 };
876 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
879 return SDValue(CSENode, 0);
886 /// getInputChainForNode - Given a node, return its input chain if it has one,
887 /// otherwise return a null sd operand.
888 static SDValue getInputChainForNode(SDNode *N) {
889 if (unsigned NumOps = N->getNumOperands()) {
890 if (N->getOperand(0).getValueType() == MVT::Other)
891 return N->getOperand(0);
892 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
893 return N->getOperand(NumOps-1);
894 for (unsigned i = 1; i < NumOps-1; ++i)
895 if (N->getOperand(i).getValueType() == MVT::Other)
896 return N->getOperand(i);
901 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
902 // If N has two operands, where one has an input chain equal to the other,
903 // the 'other' chain is redundant.
904 if (N->getNumOperands() == 2) {
905 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
906 return N->getOperand(0);
907 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
908 return N->getOperand(1);
911 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
912 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
913 SmallPtrSet<SDNode*, 16> SeenOps;
914 bool Changed = false; // If we should replace this token factor.
916 // Start out with this token factor.
919 // Iterate through token factors. The TFs grows when new token factors are
921 for (unsigned i = 0; i < TFs.size(); ++i) {
924 // Check each of the operands.
925 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
926 SDValue Op = TF->getOperand(i);
928 switch (Op.getOpcode()) {
929 case ISD::EntryToken:
930 // Entry tokens don't need to be added to the list. They are
935 case ISD::TokenFactor:
936 if (Op.hasOneUse() &&
937 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
938 // Queue up for processing.
939 TFs.push_back(Op.getNode());
940 // Clean up in case the token factor is removed.
941 AddToWorkList(Op.getNode());
948 // Only add if it isn't already in the list.
949 if (SeenOps.insert(Op.getNode()))
960 // If we've change things around then replace token factor.
963 // The entry token is the only possible outcome.
964 Result = DAG.getEntryNode();
966 // New and improved token factor.
967 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
968 MVT::Other, &Ops[0], Ops.size());
971 // Don't add users to work list.
972 return CombineTo(N, Result, false);
978 /// MERGE_VALUES can always be eliminated.
979 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
980 WorkListRemover DeadNodes(*this);
981 // Replacing results may cause a different MERGE_VALUES to suddenly
982 // be CSE'd with N, and carry its uses with it. Iterate until no
983 // uses remain, to ensure that the node can be safely deleted.
985 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
986 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
988 } while (!N->use_empty());
989 removeFromWorkList(N);
991 return SDValue(N, 0); // Return N so it doesn't get rechecked!
995 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
997 EVT VT = N0.getValueType();
998 SDValue N00 = N0.getOperand(0);
999 SDValue N01 = N0.getOperand(1);
1000 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1002 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1003 isa<ConstantSDNode>(N00.getOperand(1))) {
1004 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1005 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1006 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1007 N00.getOperand(0), N01),
1008 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1009 N00.getOperand(1), N01));
1010 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1016 SDValue DAGCombiner::visitADD(SDNode *N) {
1017 SDValue N0 = N->getOperand(0);
1018 SDValue N1 = N->getOperand(1);
1019 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1020 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1021 EVT VT = N0.getValueType();
1024 if (VT.isVector()) {
1025 SDValue FoldedVOp = SimplifyVBinOp(N);
1026 if (FoldedVOp.getNode()) return FoldedVOp;
1029 // fold (add x, undef) -> undef
1030 if (N0.getOpcode() == ISD::UNDEF)
1032 if (N1.getOpcode() == ISD::UNDEF)
1034 // fold (add c1, c2) -> c1+c2
1036 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1037 // canonicalize constant to RHS
1039 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1040 // fold (add x, 0) -> x
1041 if (N1C && N1C->isNullValue())
1043 // fold (add Sym, c) -> Sym+c
1044 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1045 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1046 GA->getOpcode() == ISD::GlobalAddress)
1047 return DAG.getGlobalAddress(GA->getGlobal(), VT,
1049 (uint64_t)N1C->getSExtValue());
1050 // fold ((c1-A)+c2) -> (c1+c2)-A
1051 if (N1C && N0.getOpcode() == ISD::SUB)
1052 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1053 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1054 DAG.getConstant(N1C->getAPIntValue()+
1055 N0C->getAPIntValue(), VT),
1058 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1059 if (RADD.getNode() != 0)
1061 // fold ((0-A) + B) -> B-A
1062 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1063 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1064 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1065 // fold (A + (0-B)) -> A-B
1066 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1067 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1068 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1069 // fold (A+(B-A)) -> B
1070 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1071 return N1.getOperand(0);
1072 // fold ((B-A)+A) -> B
1073 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1074 return N0.getOperand(0);
1075 // fold (A+(B-(A+C))) to (B-C)
1076 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1077 N0 == N1.getOperand(1).getOperand(0))
1078 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1079 N1.getOperand(1).getOperand(1));
1080 // fold (A+(B-(C+A))) to (B-C)
1081 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1082 N0 == N1.getOperand(1).getOperand(1))
1083 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1084 N1.getOperand(1).getOperand(0));
1085 // fold (A+((B-A)+or-C)) to (B+or-C)
1086 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1087 N1.getOperand(0).getOpcode() == ISD::SUB &&
1088 N0 == N1.getOperand(0).getOperand(1))
1089 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1090 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1092 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1093 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1094 SDValue N00 = N0.getOperand(0);
1095 SDValue N01 = N0.getOperand(1);
1096 SDValue N10 = N1.getOperand(0);
1097 SDValue N11 = N1.getOperand(1);
1099 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1100 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1101 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1102 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1105 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1106 return SDValue(N, 0);
1108 // fold (a+b) -> (a|b) iff a and b share no bits.
1109 if (VT.isInteger() && !VT.isVector()) {
1110 APInt LHSZero, LHSOne;
1111 APInt RHSZero, RHSOne;
1112 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1113 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1115 if (LHSZero.getBoolValue()) {
1116 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1118 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1119 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1120 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1121 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1122 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1126 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1127 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1128 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1129 if (Result.getNode()) return Result;
1131 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1132 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1133 if (Result.getNode()) return Result;
1136 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1137 if (N1.getOpcode() == ISD::SHL &&
1138 N1.getOperand(0).getOpcode() == ISD::SUB)
1139 if (ConstantSDNode *C =
1140 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1141 if (C->getAPIntValue() == 0)
1142 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1143 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1144 N1.getOperand(0).getOperand(1),
1146 if (N0.getOpcode() == ISD::SHL &&
1147 N0.getOperand(0).getOpcode() == ISD::SUB)
1148 if (ConstantSDNode *C =
1149 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1150 if (C->getAPIntValue() == 0)
1151 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1152 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1153 N0.getOperand(0).getOperand(1),
1156 return PromoteIntBinOp(SDValue(N, 0));
1159 SDValue DAGCombiner::visitADDC(SDNode *N) {
1160 SDValue N0 = N->getOperand(0);
1161 SDValue N1 = N->getOperand(1);
1162 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1163 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1164 EVT VT = N0.getValueType();
1166 // If the flag result is dead, turn this into an ADD.
1167 if (N->hasNUsesOfValue(0, 1))
1168 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
1169 DAG.getNode(ISD::CARRY_FALSE,
1170 N->getDebugLoc(), MVT::Flag));
1172 // canonicalize constant to RHS.
1174 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1176 // fold (addc x, 0) -> x + no carry out
1177 if (N1C && N1C->isNullValue())
1178 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1179 N->getDebugLoc(), MVT::Flag));
1181 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1182 APInt LHSZero, LHSOne;
1183 APInt RHSZero, RHSOne;
1184 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1185 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1187 if (LHSZero.getBoolValue()) {
1188 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1190 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1191 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1192 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1193 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1194 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1195 DAG.getNode(ISD::CARRY_FALSE,
1196 N->getDebugLoc(), MVT::Flag));
1202 SDValue DAGCombiner::visitADDE(SDNode *N) {
1203 SDValue N0 = N->getOperand(0);
1204 SDValue N1 = N->getOperand(1);
1205 SDValue CarryIn = N->getOperand(2);
1206 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1207 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1209 // canonicalize constant to RHS
1211 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1214 // fold (adde x, y, false) -> (addc x, y)
1215 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1216 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1221 SDValue DAGCombiner::visitSUB(SDNode *N) {
1222 SDValue N0 = N->getOperand(0);
1223 SDValue N1 = N->getOperand(1);
1224 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1225 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1226 EVT VT = N0.getValueType();
1229 if (VT.isVector()) {
1230 SDValue FoldedVOp = SimplifyVBinOp(N);
1231 if (FoldedVOp.getNode()) return FoldedVOp;
1234 // fold (sub x, x) -> 0
1236 return DAG.getConstant(0, N->getValueType(0));
1237 // fold (sub c1, c2) -> c1-c2
1239 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1240 // fold (sub x, c) -> (add x, -c)
1242 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1243 DAG.getConstant(-N1C->getAPIntValue(), VT));
1244 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1245 if (N0C && N0C->isAllOnesValue())
1246 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1247 // fold (A+B)-A -> B
1248 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1249 return N0.getOperand(1);
1250 // fold (A+B)-B -> A
1251 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1252 return N0.getOperand(0);
1253 // fold ((A+(B+or-C))-B) -> A+or-C
1254 if (N0.getOpcode() == ISD::ADD &&
1255 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1256 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1257 N0.getOperand(1).getOperand(0) == N1)
1258 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1259 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1260 // fold ((A+(C+B))-B) -> A+C
1261 if (N0.getOpcode() == ISD::ADD &&
1262 N0.getOperand(1).getOpcode() == ISD::ADD &&
1263 N0.getOperand(1).getOperand(1) == N1)
1264 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1265 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1266 // fold ((A-(B-C))-C) -> A-B
1267 if (N0.getOpcode() == ISD::SUB &&
1268 N0.getOperand(1).getOpcode() == ISD::SUB &&
1269 N0.getOperand(1).getOperand(1) == N1)
1270 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1271 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1273 // If either operand of a sub is undef, the result is undef
1274 if (N0.getOpcode() == ISD::UNDEF)
1276 if (N1.getOpcode() == ISD::UNDEF)
1279 // If the relocation model supports it, consider symbol offsets.
1280 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1281 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1282 // fold (sub Sym, c) -> Sym-c
1283 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1284 return DAG.getGlobalAddress(GA->getGlobal(), VT,
1286 (uint64_t)N1C->getSExtValue());
1287 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1288 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1289 if (GA->getGlobal() == GB->getGlobal())
1290 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1294 return PromoteIntBinOp(SDValue(N, 0));
1297 SDValue DAGCombiner::visitMUL(SDNode *N) {
1298 SDValue N0 = N->getOperand(0);
1299 SDValue N1 = N->getOperand(1);
1300 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1301 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1302 EVT VT = N0.getValueType();
1305 if (VT.isVector()) {
1306 SDValue FoldedVOp = SimplifyVBinOp(N);
1307 if (FoldedVOp.getNode()) return FoldedVOp;
1310 // fold (mul x, undef) -> 0
1311 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1312 return DAG.getConstant(0, VT);
1313 // fold (mul c1, c2) -> c1*c2
1315 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1316 // canonicalize constant to RHS
1318 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1319 // fold (mul x, 0) -> 0
1320 if (N1C && N1C->isNullValue())
1322 // fold (mul x, -1) -> 0-x
1323 if (N1C && N1C->isAllOnesValue())
1324 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1325 DAG.getConstant(0, VT), N0);
1326 // fold (mul x, (1 << c)) -> x << c
1327 if (N1C && N1C->getAPIntValue().isPowerOf2())
1328 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1329 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1330 getShiftAmountTy()));
1331 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1332 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1333 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1334 // FIXME: If the input is something that is easily negated (e.g. a
1335 // single-use add), we should put the negate there.
1336 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1337 DAG.getConstant(0, VT),
1338 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1339 DAG.getConstant(Log2Val, getShiftAmountTy())));
1341 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1342 if (N1C && N0.getOpcode() == ISD::SHL &&
1343 isa<ConstantSDNode>(N0.getOperand(1))) {
1344 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1345 N1, N0.getOperand(1));
1346 AddToWorkList(C3.getNode());
1347 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1348 N0.getOperand(0), C3);
1351 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1354 SDValue Sh(0,0), Y(0,0);
1355 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1356 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1357 N0.getNode()->hasOneUse()) {
1359 } else if (N1.getOpcode() == ISD::SHL &&
1360 isa<ConstantSDNode>(N1.getOperand(1)) &&
1361 N1.getNode()->hasOneUse()) {
1366 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1367 Sh.getOperand(0), Y);
1368 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1369 Mul, Sh.getOperand(1));
1373 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1374 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1375 isa<ConstantSDNode>(N0.getOperand(1)))
1376 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1377 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1378 N0.getOperand(0), N1),
1379 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1380 N0.getOperand(1), N1));
1383 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1384 if (RMUL.getNode() != 0)
1387 return PromoteIntBinOp(SDValue(N, 0));
1390 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1391 SDValue N0 = N->getOperand(0);
1392 SDValue N1 = N->getOperand(1);
1393 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1394 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1395 EVT VT = N->getValueType(0);
1398 if (VT.isVector()) {
1399 SDValue FoldedVOp = SimplifyVBinOp(N);
1400 if (FoldedVOp.getNode()) return FoldedVOp;
1403 // fold (sdiv c1, c2) -> c1/c2
1404 if (N0C && N1C && !N1C->isNullValue())
1405 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1406 // fold (sdiv X, 1) -> X
1407 if (N1C && N1C->getSExtValue() == 1LL)
1409 // fold (sdiv X, -1) -> 0-X
1410 if (N1C && N1C->isAllOnesValue())
1411 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1412 DAG.getConstant(0, VT), N0);
1413 // If we know the sign bits of both operands are zero, strength reduce to a
1414 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1415 if (!VT.isVector()) {
1416 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1417 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1420 // fold (sdiv X, pow2) -> simple ops after legalize
1421 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
1422 (isPowerOf2_64(N1C->getSExtValue()) ||
1423 isPowerOf2_64(-N1C->getSExtValue()))) {
1424 // If dividing by powers of two is cheap, then don't perform the following
1426 if (TLI.isPow2DivCheap())
1429 int64_t pow2 = N1C->getSExtValue();
1430 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1431 unsigned lg2 = Log2_64(abs2);
1433 // Splat the sign bit into the register
1434 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1435 DAG.getConstant(VT.getSizeInBits()-1,
1436 getShiftAmountTy()));
1437 AddToWorkList(SGN.getNode());
1439 // Add (N0 < 0) ? abs2 - 1 : 0;
1440 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1441 DAG.getConstant(VT.getSizeInBits() - lg2,
1442 getShiftAmountTy()));
1443 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1444 AddToWorkList(SRL.getNode());
1445 AddToWorkList(ADD.getNode()); // Divide by pow2
1446 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1447 DAG.getConstant(lg2, getShiftAmountTy()));
1449 // If we're dividing by a positive value, we're done. Otherwise, we must
1450 // negate the result.
1454 AddToWorkList(SRA.getNode());
1455 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1456 DAG.getConstant(0, VT), SRA);
1459 // if integer divide is expensive and we satisfy the requirements, emit an
1460 // alternate sequence.
1461 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
1462 !TLI.isIntDivCheap()) {
1463 SDValue Op = BuildSDIV(N);
1464 if (Op.getNode()) return Op;
1468 if (N0.getOpcode() == ISD::UNDEF)
1469 return DAG.getConstant(0, VT);
1470 // X / undef -> undef
1471 if (N1.getOpcode() == ISD::UNDEF)
1477 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1478 SDValue N0 = N->getOperand(0);
1479 SDValue N1 = N->getOperand(1);
1480 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1481 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1482 EVT VT = N->getValueType(0);
1485 if (VT.isVector()) {
1486 SDValue FoldedVOp = SimplifyVBinOp(N);
1487 if (FoldedVOp.getNode()) return FoldedVOp;
1490 // fold (udiv c1, c2) -> c1/c2
1491 if (N0C && N1C && !N1C->isNullValue())
1492 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1493 // fold (udiv x, (1 << c)) -> x >>u c
1494 if (N1C && N1C->getAPIntValue().isPowerOf2())
1495 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1496 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1497 getShiftAmountTy()));
1498 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1499 if (N1.getOpcode() == ISD::SHL) {
1500 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1501 if (SHC->getAPIntValue().isPowerOf2()) {
1502 EVT ADDVT = N1.getOperand(1).getValueType();
1503 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1505 DAG.getConstant(SHC->getAPIntValue()
1508 AddToWorkList(Add.getNode());
1509 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1513 // fold (udiv x, c) -> alternate
1514 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1515 SDValue Op = BuildUDIV(N);
1516 if (Op.getNode()) return Op;
1520 if (N0.getOpcode() == ISD::UNDEF)
1521 return DAG.getConstant(0, VT);
1522 // X / undef -> undef
1523 if (N1.getOpcode() == ISD::UNDEF)
1529 SDValue DAGCombiner::visitSREM(SDNode *N) {
1530 SDValue N0 = N->getOperand(0);
1531 SDValue N1 = N->getOperand(1);
1532 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1533 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1534 EVT VT = N->getValueType(0);
1536 // fold (srem c1, c2) -> c1%c2
1537 if (N0C && N1C && !N1C->isNullValue())
1538 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1539 // If we know the sign bits of both operands are zero, strength reduce to a
1540 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1541 if (!VT.isVector()) {
1542 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1543 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1546 // If X/C can be simplified by the division-by-constant logic, lower
1547 // X%C to the equivalent of X-X/C*C.
1548 if (N1C && !N1C->isNullValue()) {
1549 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1550 AddToWorkList(Div.getNode());
1551 SDValue OptimizedDiv = combine(Div.getNode());
1552 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1553 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1555 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1556 AddToWorkList(Mul.getNode());
1562 if (N0.getOpcode() == ISD::UNDEF)
1563 return DAG.getConstant(0, VT);
1564 // X % undef -> undef
1565 if (N1.getOpcode() == ISD::UNDEF)
1571 SDValue DAGCombiner::visitUREM(SDNode *N) {
1572 SDValue N0 = N->getOperand(0);
1573 SDValue N1 = N->getOperand(1);
1574 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1575 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1576 EVT VT = N->getValueType(0);
1578 // fold (urem c1, c2) -> c1%c2
1579 if (N0C && N1C && !N1C->isNullValue())
1580 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
1581 // fold (urem x, pow2) -> (and x, pow2-1)
1582 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
1583 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
1584 DAG.getConstant(N1C->getAPIntValue()-1,VT));
1585 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1586 if (N1.getOpcode() == ISD::SHL) {
1587 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1588 if (SHC->getAPIntValue().isPowerOf2()) {
1590 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
1591 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
1593 AddToWorkList(Add.getNode());
1594 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
1599 // If X/C can be simplified by the division-by-constant logic, lower
1600 // X%C to the equivalent of X-X/C*C.
1601 if (N1C && !N1C->isNullValue()) {
1602 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
1603 AddToWorkList(Div.getNode());
1604 SDValue OptimizedDiv = combine(Div.getNode());
1605 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1606 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1608 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1609 AddToWorkList(Mul.getNode());
1615 if (N0.getOpcode() == ISD::UNDEF)
1616 return DAG.getConstant(0, VT);
1617 // X % undef -> undef
1618 if (N1.getOpcode() == ISD::UNDEF)
1624 SDValue DAGCombiner::visitMULHS(SDNode *N) {
1625 SDValue N0 = N->getOperand(0);
1626 SDValue N1 = N->getOperand(1);
1627 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1628 EVT VT = N->getValueType(0);
1630 // fold (mulhs x, 0) -> 0
1631 if (N1C && N1C->isNullValue())
1633 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1634 if (N1C && N1C->getAPIntValue() == 1)
1635 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
1636 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
1637 getShiftAmountTy()));
1638 // fold (mulhs x, undef) -> 0
1639 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1640 return DAG.getConstant(0, VT);
1645 SDValue DAGCombiner::visitMULHU(SDNode *N) {
1646 SDValue N0 = N->getOperand(0);
1647 SDValue N1 = N->getOperand(1);
1648 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1649 EVT VT = N->getValueType(0);
1651 // fold (mulhu x, 0) -> 0
1652 if (N1C && N1C->isNullValue())
1654 // fold (mulhu x, 1) -> 0
1655 if (N1C && N1C->getAPIntValue() == 1)
1656 return DAG.getConstant(0, N0.getValueType());
1657 // fold (mulhu x, undef) -> 0
1658 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1659 return DAG.getConstant(0, VT);
1664 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1665 /// compute two values. LoOp and HiOp give the opcodes for the two computations
1666 /// that are being performed. Return true if a simplification was made.
1668 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
1670 // If the high half is not needed, just compute the low half.
1671 bool HiExists = N->hasAnyUseOfValue(1);
1673 (!LegalOperations ||
1674 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1675 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1676 N->op_begin(), N->getNumOperands());
1677 return CombineTo(N, Res, Res);
1680 // If the low half is not needed, just compute the high half.
1681 bool LoExists = N->hasAnyUseOfValue(0);
1683 (!LegalOperations ||
1684 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
1685 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1686 N->op_begin(), N->getNumOperands());
1687 return CombineTo(N, Res, Res);
1690 // If both halves are used, return as it is.
1691 if (LoExists && HiExists)
1694 // If the two computed results can be simplified separately, separate them.
1696 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1697 N->op_begin(), N->getNumOperands());
1698 AddToWorkList(Lo.getNode());
1699 SDValue LoOpt = combine(Lo.getNode());
1700 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
1701 (!LegalOperations ||
1702 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
1703 return CombineTo(N, LoOpt, LoOpt);
1707 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1708 N->op_begin(), N->getNumOperands());
1709 AddToWorkList(Hi.getNode());
1710 SDValue HiOpt = combine(Hi.getNode());
1711 if (HiOpt.getNode() && HiOpt != Hi &&
1712 (!LegalOperations ||
1713 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
1714 return CombineTo(N, HiOpt, HiOpt);
1720 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
1721 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
1722 if (Res.getNode()) return Res;
1727 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
1728 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
1729 if (Res.getNode()) return Res;
1734 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
1735 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
1736 if (Res.getNode()) return Res;
1741 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
1742 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
1743 if (Res.getNode()) return Res;
1748 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1749 /// two operands of the same opcode, try to simplify it.
1750 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1751 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1752 EVT VT = N0.getValueType();
1753 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1755 // Bail early if none of these transforms apply.
1756 if (N0.getNode()->getNumOperands() == 0) return SDValue();
1758 // For each of OP in AND/OR/XOR:
1759 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1760 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1761 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1762 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1764 // do not sink logical op inside of a vector extend, since it may combine
1766 EVT Op0VT = N0.getOperand(0).getValueType();
1767 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
1768 N0.getOpcode() == ISD::ANY_EXTEND ||
1769 N0.getOpcode() == ISD::SIGN_EXTEND ||
1770 (N0.getOpcode() == ISD::TRUNCATE && TLI.isTypeLegal(Op0VT))) &&
1772 Op0VT == N1.getOperand(0).getValueType() &&
1773 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
1774 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
1775 N0.getOperand(0).getValueType(),
1776 N0.getOperand(0), N1.getOperand(0));
1777 AddToWorkList(ORNode.getNode());
1778 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
1781 // For each of OP in SHL/SRL/SRA/AND...
1782 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1783 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1784 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1785 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1786 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1787 N0.getOperand(1) == N1.getOperand(1)) {
1788 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
1789 N0.getOperand(0).getValueType(),
1790 N0.getOperand(0), N1.getOperand(0));
1791 AddToWorkList(ORNode.getNode());
1792 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
1793 ORNode, N0.getOperand(1));
1799 SDValue DAGCombiner::visitAND(SDNode *N) {
1800 SDValue N0 = N->getOperand(0);
1801 SDValue N1 = N->getOperand(1);
1802 SDValue LL, LR, RL, RR, CC0, CC1;
1803 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1804 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1805 EVT VT = N1.getValueType();
1806 unsigned BitWidth = VT.getScalarType().getSizeInBits();
1809 if (VT.isVector()) {
1810 SDValue FoldedVOp = SimplifyVBinOp(N);
1811 if (FoldedVOp.getNode()) return FoldedVOp;
1814 // fold (and x, undef) -> 0
1815 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1816 return DAG.getConstant(0, VT);
1817 // fold (and c1, c2) -> c1&c2
1819 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
1820 // canonicalize constant to RHS
1822 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
1823 // fold (and x, -1) -> x
1824 if (N1C && N1C->isAllOnesValue())
1826 // if (and x, c) is known to be zero, return 0
1827 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
1828 APInt::getAllOnesValue(BitWidth)))
1829 return DAG.getConstant(0, VT);
1831 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
1832 if (RAND.getNode() != 0)
1834 // fold (and (or x, C), D) -> D if (C & D) == D
1835 if (N1C && N0.getOpcode() == ISD::OR)
1836 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1837 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
1839 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1840 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1841 SDValue N0Op0 = N0.getOperand(0);
1842 APInt Mask = ~N1C->getAPIntValue();
1843 Mask.trunc(N0Op0.getValueSizeInBits());
1844 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
1845 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
1846 N0.getValueType(), N0Op0);
1848 // Replace uses of the AND with uses of the Zero extend node.
1851 // We actually want to replace all uses of the any_extend with the
1852 // zero_extend, to avoid duplicating things. This will later cause this
1853 // AND to be folded.
1854 CombineTo(N0.getNode(), Zext);
1855 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1858 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1859 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1860 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1861 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1863 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1864 LL.getValueType().isInteger()) {
1865 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
1866 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
1867 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
1868 LR.getValueType(), LL, RL);
1869 AddToWorkList(ORNode.getNode());
1870 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
1872 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
1873 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1874 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
1875 LR.getValueType(), LL, RL);
1876 AddToWorkList(ANDNode.getNode());
1877 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
1879 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
1880 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1881 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
1882 LR.getValueType(), LL, RL);
1883 AddToWorkList(ORNode.getNode());
1884 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
1887 // canonicalize equivalent to ll == rl
1888 if (LL == RR && LR == RL) {
1889 Op1 = ISD::getSetCCSwappedOperands(Op1);
1892 if (LL == RL && LR == RR) {
1893 bool isInteger = LL.getValueType().isInteger();
1894 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1895 if (Result != ISD::SETCC_INVALID &&
1896 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
1897 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
1902 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
1903 if (N0.getOpcode() == N1.getOpcode()) {
1904 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1905 if (Tmp.getNode()) return Tmp;
1908 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1909 // fold (and (sra)) -> (and (srl)) when possible.
1910 if (!VT.isVector() &&
1911 SimplifyDemandedBits(SDValue(N, 0)))
1912 return SDValue(N, 0);
1914 // fold (zext_inreg (extload x)) -> (zextload x)
1915 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
1916 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1917 EVT MemVT = LN0->getMemoryVT();
1918 // If we zero all the possible extended bits, then we can turn this into
1919 // a zextload if we are running before legalize or the operation is legal.
1920 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
1921 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1922 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
1923 ((!LegalOperations && !LN0->isVolatile()) ||
1924 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
1925 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
1926 LN0->getChain(), LN0->getBasePtr(),
1928 LN0->getSrcValueOffset(), MemVT,
1929 LN0->isVolatile(), LN0->isNonTemporal(),
1930 LN0->getAlignment());
1932 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
1933 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1936 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1937 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
1939 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1940 EVT MemVT = LN0->getMemoryVT();
1941 // If we zero all the possible extended bits, then we can turn this into
1942 // a zextload if we are running before legalize or the operation is legal.
1943 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
1944 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1945 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
1946 ((!LegalOperations && !LN0->isVolatile()) ||
1947 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
1948 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
1950 LN0->getBasePtr(), LN0->getSrcValue(),
1951 LN0->getSrcValueOffset(), MemVT,
1952 LN0->isVolatile(), LN0->isNonTemporal(),
1953 LN0->getAlignment());
1955 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
1956 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1960 // fold (and (load x), 255) -> (zextload x, i8)
1961 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1962 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
1963 if (N1C && (N0.getOpcode() == ISD::LOAD ||
1964 (N0.getOpcode() == ISD::ANY_EXTEND &&
1965 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
1966 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
1967 LoadSDNode *LN0 = HasAnyExt
1968 ? cast<LoadSDNode>(N0.getOperand(0))
1969 : cast<LoadSDNode>(N0);
1970 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1971 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
1972 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
1973 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
1974 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
1975 EVT LoadedVT = LN0->getMemoryVT();
1977 if (ExtVT == LoadedVT &&
1978 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
1979 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
1982 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
1983 LN0->getChain(), LN0->getBasePtr(),
1984 LN0->getSrcValue(), LN0->getSrcValueOffset(),
1985 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
1986 LN0->getAlignment());
1988 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
1989 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1992 // Do not change the width of a volatile load.
1993 // Do not generate loads of non-round integer types since these can
1994 // be expensive (and would be wrong if the type is not byte sized).
1995 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
1996 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
1997 EVT PtrType = LN0->getOperand(1).getValueType();
1999 unsigned Alignment = LN0->getAlignment();
2000 SDValue NewPtr = LN0->getBasePtr();
2002 // For big endian targets, we need to add an offset to the pointer
2003 // to load the correct bytes. For little endian systems, we merely
2004 // need to read fewer bytes from the same pointer.
2005 if (TLI.isBigEndian()) {
2006 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2007 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2008 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2009 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2010 NewPtr, DAG.getConstant(PtrOff, PtrType));
2011 Alignment = MinAlign(Alignment, PtrOff);
2014 AddToWorkList(NewPtr.getNode());
2016 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2018 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2019 LN0->getChain(), NewPtr,
2020 LN0->getSrcValue(), LN0->getSrcValueOffset(),
2021 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2024 CombineTo(LN0, Load, Load.getValue(1));
2025 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2031 return PromoteIntBinOp(SDValue(N, 0));
2034 SDValue DAGCombiner::visitOR(SDNode *N) {
2035 SDValue N0 = N->getOperand(0);
2036 SDValue N1 = N->getOperand(1);
2037 SDValue LL, LR, RL, RR, CC0, CC1;
2038 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2039 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2040 EVT VT = N1.getValueType();
2043 if (VT.isVector()) {
2044 SDValue FoldedVOp = SimplifyVBinOp(N);
2045 if (FoldedVOp.getNode()) return FoldedVOp;
2048 // fold (or x, undef) -> -1
2049 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) {
2050 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
2051 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
2053 // fold (or c1, c2) -> c1|c2
2055 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
2056 // canonicalize constant to RHS
2058 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
2059 // fold (or x, 0) -> x
2060 if (N1C && N1C->isNullValue())
2062 // fold (or x, -1) -> -1
2063 if (N1C && N1C->isAllOnesValue())
2065 // fold (or x, c) -> c iff (x & ~c) == 0
2066 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
2069 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
2070 if (ROR.getNode() != 0)
2072 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
2073 // iff (c1 & c2) == 0.
2074 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
2075 isa<ConstantSDNode>(N0.getOperand(1))) {
2076 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
2077 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
2078 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
2079 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2080 N0.getOperand(0), N1),
2081 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
2083 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
2084 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2085 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2086 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2088 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2089 LL.getValueType().isInteger()) {
2090 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
2091 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
2092 if (cast<ConstantSDNode>(LR)->isNullValue() &&
2093 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
2094 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
2095 LR.getValueType(), LL, RL);
2096 AddToWorkList(ORNode.getNode());
2097 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2099 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
2100 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
2101 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2102 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
2103 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
2104 LR.getValueType(), LL, RL);
2105 AddToWorkList(ANDNode.getNode());
2106 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2109 // canonicalize equivalent to ll == rl
2110 if (LL == RR && LR == RL) {
2111 Op1 = ISD::getSetCCSwappedOperands(Op1);
2114 if (LL == RL && LR == RR) {
2115 bool isInteger = LL.getValueType().isInteger();
2116 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
2117 if (Result != ISD::SETCC_INVALID &&
2118 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2119 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2124 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
2125 if (N0.getOpcode() == N1.getOpcode()) {
2126 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2127 if (Tmp.getNode()) return Tmp;
2130 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
2131 if (N0.getOpcode() == ISD::AND &&
2132 N1.getOpcode() == ISD::AND &&
2133 N0.getOperand(1).getOpcode() == ISD::Constant &&
2134 N1.getOperand(1).getOpcode() == ISD::Constant &&
2135 // Don't increase # computations.
2136 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
2137 // We can only do this xform if we know that bits from X that are set in C2
2138 // but not in C1 are already zero. Likewise for Y.
2139 const APInt &LHSMask =
2140 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2141 const APInt &RHSMask =
2142 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
2144 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
2145 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
2146 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2147 N0.getOperand(0), N1.getOperand(0));
2148 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
2149 DAG.getConstant(LHSMask | RHSMask, VT));
2153 // See if this is some rotate idiom.
2154 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
2155 return SDValue(Rot, 0);
2157 return PromoteIntBinOp(SDValue(N, 0));
2160 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
2161 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
2162 if (Op.getOpcode() == ISD::AND) {
2163 if (isa<ConstantSDNode>(Op.getOperand(1))) {
2164 Mask = Op.getOperand(1);
2165 Op = Op.getOperand(0);
2171 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
2179 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
2180 // idioms for rotate, and if the target supports rotation instructions, generate
2182 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
2183 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
2184 EVT VT = LHS.getValueType();
2185 if (!TLI.isTypeLegal(VT)) return 0;
2187 // The target must have at least one rotate flavor.
2188 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
2189 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
2190 if (!HasROTL && !HasROTR) return 0;
2192 // Match "(X shl/srl V1) & V2" where V2 may not be present.
2193 SDValue LHSShift; // The shift.
2194 SDValue LHSMask; // AND value if any.
2195 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
2196 return 0; // Not part of a rotate.
2198 SDValue RHSShift; // The shift.
2199 SDValue RHSMask; // AND value if any.
2200 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
2201 return 0; // Not part of a rotate.
2203 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
2204 return 0; // Not shifting the same value.
2206 if (LHSShift.getOpcode() == RHSShift.getOpcode())
2207 return 0; // Shifts must disagree.
2209 // Canonicalize shl to left side in a shl/srl pair.
2210 if (RHSShift.getOpcode() == ISD::SHL) {
2211 std::swap(LHS, RHS);
2212 std::swap(LHSShift, RHSShift);
2213 std::swap(LHSMask , RHSMask );
2216 unsigned OpSizeInBits = VT.getSizeInBits();
2217 SDValue LHSShiftArg = LHSShift.getOperand(0);
2218 SDValue LHSShiftAmt = LHSShift.getOperand(1);
2219 SDValue RHSShiftAmt = RHSShift.getOperand(1);
2221 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
2222 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
2223 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
2224 RHSShiftAmt.getOpcode() == ISD::Constant) {
2225 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
2226 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
2227 if ((LShVal + RShVal) != OpSizeInBits)
2232 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
2234 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
2236 // If there is an AND of either shifted operand, apply it to the result.
2237 if (LHSMask.getNode() || RHSMask.getNode()) {
2238 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
2240 if (LHSMask.getNode()) {
2241 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
2242 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
2244 if (RHSMask.getNode()) {
2245 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
2246 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
2249 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
2252 return Rot.getNode();
2255 // If there is a mask here, and we have a variable shift, we can't be sure
2256 // that we're masking out the right stuff.
2257 if (LHSMask.getNode() || RHSMask.getNode())
2260 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
2261 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
2262 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
2263 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
2264 if (ConstantSDNode *SUBC =
2265 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
2266 if (SUBC->getAPIntValue() == OpSizeInBits) {
2268 return DAG.getNode(ISD::ROTL, DL, VT,
2269 LHSShiftArg, LHSShiftAmt).getNode();
2271 return DAG.getNode(ISD::ROTR, DL, VT,
2272 LHSShiftArg, RHSShiftAmt).getNode();
2277 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2278 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
2279 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
2280 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
2281 if (ConstantSDNode *SUBC =
2282 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
2283 if (SUBC->getAPIntValue() == OpSizeInBits) {
2285 return DAG.getNode(ISD::ROTR, DL, VT,
2286 LHSShiftArg, RHSShiftAmt).getNode();
2288 return DAG.getNode(ISD::ROTL, DL, VT,
2289 LHSShiftArg, LHSShiftAmt).getNode();
2294 // Look for sign/zext/any-extended or truncate cases:
2295 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2296 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2297 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2298 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
2299 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2300 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2301 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2302 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
2303 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
2304 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
2305 if (RExtOp0.getOpcode() == ISD::SUB &&
2306 RExtOp0.getOperand(1) == LExtOp0) {
2307 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2309 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2310 // (rotr x, (sub 32, y))
2311 if (ConstantSDNode *SUBC =
2312 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
2313 if (SUBC->getAPIntValue() == OpSizeInBits) {
2314 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
2316 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
2319 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2320 RExtOp0 == LExtOp0.getOperand(1)) {
2321 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2323 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2324 // (rotl x, (sub 32, y))
2325 if (ConstantSDNode *SUBC =
2326 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2327 if (SUBC->getAPIntValue() == OpSizeInBits) {
2328 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
2330 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
2339 SDValue DAGCombiner::visitXOR(SDNode *N) {
2340 SDValue N0 = N->getOperand(0);
2341 SDValue N1 = N->getOperand(1);
2342 SDValue LHS, RHS, CC;
2343 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2344 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2345 EVT VT = N0.getValueType();
2348 if (VT.isVector()) {
2349 SDValue FoldedVOp = SimplifyVBinOp(N);
2350 if (FoldedVOp.getNode()) return FoldedVOp;
2353 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
2354 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
2355 return DAG.getConstant(0, VT);
2356 // fold (xor x, undef) -> undef
2357 if (N0.getOpcode() == ISD::UNDEF)
2359 if (N1.getOpcode() == ISD::UNDEF)
2361 // fold (xor c1, c2) -> c1^c2
2363 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
2364 // canonicalize constant to RHS
2366 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
2367 // fold (xor x, 0) -> x
2368 if (N1C && N1C->isNullValue())
2371 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
2372 if (RXOR.getNode() != 0)
2375 // fold !(x cc y) -> (x !cc y)
2376 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2377 bool isInt = LHS.getValueType().isInteger();
2378 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2381 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
2382 switch (N0.getOpcode()) {
2384 llvm_unreachable("Unhandled SetCC Equivalent!");
2386 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
2387 case ISD::SELECT_CC:
2388 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
2389 N0.getOperand(3), NotCC);
2394 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2395 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2396 N0.getNode()->hasOneUse() &&
2397 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2398 SDValue V = N0.getOperand(0);
2399 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
2400 DAG.getConstant(1, V.getValueType()));
2401 AddToWorkList(V.getNode());
2402 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
2405 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
2406 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
2407 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2408 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2409 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2410 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2411 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2412 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2413 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2414 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2417 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
2418 if (N1C && N1C->isAllOnesValue() &&
2419 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2420 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2421 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2422 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2423 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2424 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2425 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2426 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2429 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
2430 if (N1C && N0.getOpcode() == ISD::XOR) {
2431 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2432 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2434 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
2435 DAG.getConstant(N1C->getAPIntValue() ^
2436 N00C->getAPIntValue(), VT));
2438 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
2439 DAG.getConstant(N1C->getAPIntValue() ^
2440 N01C->getAPIntValue(), VT));
2442 // fold (xor x, x) -> 0
2444 if (!VT.isVector()) {
2445 return DAG.getConstant(0, VT);
2446 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){
2447 // Produce a vector of zeros.
2448 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
2449 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
2450 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
2451 &Ops[0], Ops.size());
2455 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2456 if (N0.getOpcode() == N1.getOpcode()) {
2457 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2458 if (Tmp.getNode()) return Tmp;
2461 // Simplify the expression using non-local knowledge.
2462 if (!VT.isVector() &&
2463 SimplifyDemandedBits(SDValue(N, 0)))
2464 return SDValue(N, 0);
2466 return PromoteIntBinOp(SDValue(N, 0));
2469 /// visitShiftByConstant - Handle transforms common to the three shifts, when
2470 /// the shift amount is a constant.
2471 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
2472 SDNode *LHS = N->getOperand(0).getNode();
2473 if (!LHS->hasOneUse()) return SDValue();
2475 // We want to pull some binops through shifts, so that we have (and (shift))
2476 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
2477 // thing happens with address calculations, so it's important to canonicalize
2479 bool HighBitSet = false; // Can we transform this if the high bit is set?
2481 switch (LHS->getOpcode()) {
2482 default: return SDValue();
2485 HighBitSet = false; // We can only transform sra if the high bit is clear.
2488 HighBitSet = true; // We can only transform sra if the high bit is set.
2491 if (N->getOpcode() != ISD::SHL)
2492 return SDValue(); // only shl(add) not sr[al](add).
2493 HighBitSet = false; // We can only transform sra if the high bit is clear.
2497 // We require the RHS of the binop to be a constant as well.
2498 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
2499 if (!BinOpCst) return SDValue();
2501 // FIXME: disable this unless the input to the binop is a shift by a constant.
2502 // If it is not a shift, it pessimizes some common cases like:
2504 // void foo(int *X, int i) { X[i & 1235] = 1; }
2505 // int bar(int *X, int i) { return X[i & 255]; }
2506 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
2507 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
2508 BinOpLHSVal->getOpcode() != ISD::SRA &&
2509 BinOpLHSVal->getOpcode() != ISD::SRL) ||
2510 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
2513 EVT VT = N->getValueType(0);
2515 // If this is a signed shift right, and the high bit is modified by the
2516 // logical operation, do not perform the transformation. The highBitSet
2517 // boolean indicates the value of the high bit of the constant which would
2518 // cause it to be modified for this operation.
2519 if (N->getOpcode() == ISD::SRA) {
2520 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
2521 if (BinOpRHSSignSet != HighBitSet)
2525 // Fold the constants, shifting the binop RHS by the shift amount.
2526 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
2528 LHS->getOperand(1), N->getOperand(1));
2530 // Create the new shift.
2531 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(),
2532 VT, LHS->getOperand(0), N->getOperand(1));
2534 // Create the new binop.
2535 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
2538 SDValue DAGCombiner::visitSHL(SDNode *N) {
2539 SDValue N0 = N->getOperand(0);
2540 SDValue N1 = N->getOperand(1);
2541 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2542 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2543 EVT VT = N0.getValueType();
2544 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
2546 // fold (shl c1, c2) -> c1<<c2
2548 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
2549 // fold (shl 0, x) -> 0
2550 if (N0C && N0C->isNullValue())
2552 // fold (shl x, c >= size(x)) -> undef
2553 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2554 return DAG.getUNDEF(VT);
2555 // fold (shl x, 0) -> x
2556 if (N1C && N1C->isNullValue())
2558 // if (shl x, c) is known to be zero, return 0
2559 if (DAG.MaskedValueIsZero(SDValue(N, 0),
2560 APInt::getAllOnesValue(OpSizeInBits)))
2561 return DAG.getConstant(0, VT);
2562 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
2563 if (N1.getOpcode() == ISD::TRUNCATE &&
2564 N1.getOperand(0).getOpcode() == ISD::AND &&
2565 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2566 SDValue N101 = N1.getOperand(0).getOperand(1);
2567 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2568 EVT TruncVT = N1.getValueType();
2569 SDValue N100 = N1.getOperand(0).getOperand(0);
2570 APInt TruncC = N101C->getAPIntValue();
2571 TruncC.trunc(TruncVT.getSizeInBits());
2572 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
2573 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
2574 DAG.getNode(ISD::TRUNCATE,
2577 DAG.getConstant(TruncC, TruncVT)));
2581 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2582 return SDValue(N, 0);
2584 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
2585 if (N1C && N0.getOpcode() == ISD::SHL &&
2586 N0.getOperand(1).getOpcode() == ISD::Constant) {
2587 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2588 uint64_t c2 = N1C->getZExtValue();
2589 if (c1 + c2 > OpSizeInBits)
2590 return DAG.getConstant(0, VT);
2591 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
2592 DAG.getConstant(c1 + c2, N1.getValueType()));
2594 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or
2595 // (srl (and x, (shl -1, c1)), (sub c1, c2))
2596 if (N1C && N0.getOpcode() == ISD::SRL &&
2597 N0.getOperand(1).getOpcode() == ISD::Constant) {
2598 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2599 if (c1 < VT.getSizeInBits()) {
2600 uint64_t c2 = N1C->getZExtValue();
2601 SDValue HiBitsMask =
2602 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
2603 VT.getSizeInBits() - c1),
2605 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT,
2609 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask,
2610 DAG.getConstant(c2-c1, N1.getValueType()));
2612 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask,
2613 DAG.getConstant(c1-c2, N1.getValueType()));
2616 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
2617 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
2618 SDValue HiBitsMask =
2619 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
2620 VT.getSizeInBits() -
2621 N1C->getZExtValue()),
2623 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
2627 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2630 SDValue DAGCombiner::visitSRA(SDNode *N) {
2631 SDValue N0 = N->getOperand(0);
2632 SDValue N1 = N->getOperand(1);
2633 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2634 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2635 EVT VT = N0.getValueType();
2636 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
2638 // fold (sra c1, c2) -> (sra c1, c2)
2640 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
2641 // fold (sra 0, x) -> 0
2642 if (N0C && N0C->isNullValue())
2644 // fold (sra -1, x) -> -1
2645 if (N0C && N0C->isAllOnesValue())
2647 // fold (sra x, (setge c, size(x))) -> undef
2648 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2649 return DAG.getUNDEF(VT);
2650 // fold (sra x, 0) -> x
2651 if (N1C && N1C->isNullValue())
2653 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2655 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2656 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
2657 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
2659 ExtVT = EVT::getVectorVT(*DAG.getContext(),
2660 ExtVT, VT.getVectorNumElements());
2661 if ((!LegalOperations ||
2662 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
2663 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
2664 N0.getOperand(0), DAG.getValueType(ExtVT));
2667 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
2668 if (N1C && N0.getOpcode() == ISD::SRA) {
2669 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2670 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
2671 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
2672 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
2673 DAG.getConstant(Sum, N1C->getValueType(0)));
2677 // fold (sra (shl X, m), (sub result_size, n))
2678 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
2679 // result_size - n != m.
2680 // If truncate is free for the target sext(shl) is likely to result in better
2682 if (N0.getOpcode() == ISD::SHL) {
2683 // Get the two constanst of the shifts, CN0 = m, CN = n.
2684 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2686 // Determine what the truncate's result bitsize and type would be.
2688 EVT::getIntegerVT(*DAG.getContext(), OpSizeInBits - N1C->getZExtValue());
2689 // Determine the residual right-shift amount.
2690 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
2692 // If the shift is not a no-op (in which case this should be just a sign
2693 // extend already), the truncated to type is legal, sign_extend is legal
2694 // on that type, and the truncate to that type is both legal and free,
2695 // perform the transform.
2696 if ((ShiftAmt > 0) &&
2697 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
2698 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
2699 TLI.isTruncateFree(VT, TruncVT)) {
2701 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy());
2702 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
2703 N0.getOperand(0), Amt);
2704 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
2706 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
2707 N->getValueType(0), Trunc);
2712 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
2713 if (N1.getOpcode() == ISD::TRUNCATE &&
2714 N1.getOperand(0).getOpcode() == ISD::AND &&
2715 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2716 SDValue N101 = N1.getOperand(0).getOperand(1);
2717 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2718 EVT TruncVT = N1.getValueType();
2719 SDValue N100 = N1.getOperand(0).getOperand(0);
2720 APInt TruncC = N101C->getAPIntValue();
2721 TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
2722 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
2723 DAG.getNode(ISD::AND, N->getDebugLoc(),
2725 DAG.getNode(ISD::TRUNCATE,
2728 DAG.getConstant(TruncC, TruncVT)));
2732 // Simplify, based on bits shifted out of the LHS.
2733 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2734 return SDValue(N, 0);
2737 // If the sign bit is known to be zero, switch this to a SRL.
2738 if (DAG.SignBitIsZero(N0))
2739 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
2741 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2744 SDValue DAGCombiner::visitSRL(SDNode *N) {
2745 SDValue N0 = N->getOperand(0);
2746 SDValue N1 = N->getOperand(1);
2747 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2748 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2749 EVT VT = N0.getValueType();
2750 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
2752 // fold (srl c1, c2) -> c1 >>u c2
2754 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
2755 // fold (srl 0, x) -> 0
2756 if (N0C && N0C->isNullValue())
2758 // fold (srl x, c >= size(x)) -> undef
2759 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2760 return DAG.getUNDEF(VT);
2761 // fold (srl x, 0) -> x
2762 if (N1C && N1C->isNullValue())
2764 // if (srl x, c) is known to be zero, return 0
2765 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2766 APInt::getAllOnesValue(OpSizeInBits)))
2767 return DAG.getConstant(0, VT);
2769 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
2770 if (N1C && N0.getOpcode() == ISD::SRL &&
2771 N0.getOperand(1).getOpcode() == ISD::Constant) {
2772 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2773 uint64_t c2 = N1C->getZExtValue();
2774 if (c1 + c2 > OpSizeInBits)
2775 return DAG.getConstant(0, VT);
2776 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
2777 DAG.getConstant(c1 + c2, N1.getValueType()));
2780 // fold (srl (shl x, c), c) -> (and x, cst2)
2781 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
2782 N0.getValueSizeInBits() <= 64) {
2783 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
2784 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
2785 DAG.getConstant(~0ULL >> ShAmt, VT));
2789 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
2790 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2791 // Shifting in all undef bits?
2792 EVT SmallVT = N0.getOperand(0).getValueType();
2793 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
2794 return DAG.getUNDEF(VT);
2796 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
2797 N0.getOperand(0), N1);
2798 AddToWorkList(SmallShift.getNode());
2799 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
2802 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
2803 // bit, which is unmodified by sra.
2804 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
2805 if (N0.getOpcode() == ISD::SRA)
2806 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
2809 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
2810 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2811 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
2812 APInt KnownZero, KnownOne;
2813 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
2814 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
2816 // If any of the input bits are KnownOne, then the input couldn't be all
2817 // zeros, thus the result of the srl will always be zero.
2818 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
2820 // If all of the bits input the to ctlz node are known to be zero, then
2821 // the result of the ctlz is "32" and the result of the shift is one.
2822 APInt UnknownBits = ~KnownZero & Mask;
2823 if (UnknownBits == 0) return DAG.getConstant(1, VT);
2825 // Otherwise, check to see if there is exactly one bit input to the ctlz.
2826 if ((UnknownBits & (UnknownBits - 1)) == 0) {
2827 // Okay, we know that only that the single bit specified by UnknownBits
2828 // could be set on input to the CTLZ node. If this bit is set, the SRL
2829 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
2830 // to an SRL/XOR pair, which is likely to simplify more.
2831 unsigned ShAmt = UnknownBits.countTrailingZeros();
2832 SDValue Op = N0.getOperand(0);
2835 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
2836 DAG.getConstant(ShAmt, getShiftAmountTy()));
2837 AddToWorkList(Op.getNode());
2840 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
2841 Op, DAG.getConstant(1, VT));
2845 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
2846 if (N1.getOpcode() == ISD::TRUNCATE &&
2847 N1.getOperand(0).getOpcode() == ISD::AND &&
2848 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2849 SDValue N101 = N1.getOperand(0).getOperand(1);
2850 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2851 EVT TruncVT = N1.getValueType();
2852 SDValue N100 = N1.getOperand(0).getOperand(0);
2853 APInt TruncC = N101C->getAPIntValue();
2854 TruncC.trunc(TruncVT.getSizeInBits());
2855 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
2856 DAG.getNode(ISD::AND, N->getDebugLoc(),
2858 DAG.getNode(ISD::TRUNCATE,
2861 DAG.getConstant(TruncC, TruncVT)));
2865 // fold operands of srl based on knowledge that the low bits are not
2867 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2868 return SDValue(N, 0);
2871 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
2872 if (NewSRL.getNode())
2876 // Here is a common situation. We want to optimize:
2879 // %b = and i32 %a, 2
2880 // %c = srl i32 %b, 1
2881 // brcond i32 %c ...
2887 // %c = setcc eq %b, 0
2890 // However when after the source operand of SRL is optimized into AND, the SRL
2891 // itself may not be optimized further. Look for it and add the BRCOND into
2893 if (N->hasOneUse()) {
2894 SDNode *Use = *N->use_begin();
2895 if (Use->getOpcode() == ISD::BRCOND)
2897 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
2898 // Also look pass the truncate.
2899 Use = *Use->use_begin();
2900 if (Use->getOpcode() == ISD::BRCOND)
2908 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
2909 SDValue N0 = N->getOperand(0);
2910 EVT VT = N->getValueType(0);
2912 // fold (ctlz c1) -> c2
2913 if (isa<ConstantSDNode>(N0))
2914 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
2918 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
2919 SDValue N0 = N->getOperand(0);
2920 EVT VT = N->getValueType(0);
2922 // fold (cttz c1) -> c2
2923 if (isa<ConstantSDNode>(N0))
2924 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
2928 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
2929 SDValue N0 = N->getOperand(0);
2930 EVT VT = N->getValueType(0);
2932 // fold (ctpop c1) -> c2
2933 if (isa<ConstantSDNode>(N0))
2934 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
2938 SDValue DAGCombiner::visitSELECT(SDNode *N) {
2939 SDValue N0 = N->getOperand(0);
2940 SDValue N1 = N->getOperand(1);
2941 SDValue N2 = N->getOperand(2);
2942 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2943 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2944 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2945 EVT VT = N->getValueType(0);
2946 EVT VT0 = N0.getValueType();
2948 // fold (select C, X, X) -> X
2951 // fold (select true, X, Y) -> X
2952 if (N0C && !N0C->isNullValue())
2954 // fold (select false, X, Y) -> Y
2955 if (N0C && N0C->isNullValue())
2957 // fold (select C, 1, X) -> (or C, X)
2958 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
2959 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
2960 // fold (select C, 0, 1) -> (xor C, 1)
2961 if (VT.isInteger() &&
2964 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
2965 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
2968 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
2969 N0, DAG.getConstant(1, VT0));
2970 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
2971 N0, DAG.getConstant(1, VT0));
2972 AddToWorkList(XORNode.getNode());
2974 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
2975 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
2977 // fold (select C, 0, X) -> (and (not C), X)
2978 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
2979 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
2980 AddToWorkList(NOTNode.getNode());
2981 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
2983 // fold (select C, X, 1) -> (or (not C), X)
2984 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
2985 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
2986 AddToWorkList(NOTNode.getNode());
2987 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
2989 // fold (select C, X, 0) -> (and C, X)
2990 if (VT == MVT::i1 && N2C && N2C->isNullValue())
2991 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
2992 // fold (select X, X, Y) -> (or X, Y)
2993 // fold (select X, 1, Y) -> (or X, Y)
2994 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
2995 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
2996 // fold (select X, Y, X) -> (and X, Y)
2997 // fold (select X, Y, 0) -> (and X, Y)
2998 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
2999 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3001 // If we can fold this based on the true/false value, do so.
3002 if (SimplifySelectOps(N, N1, N2))
3003 return SDValue(N, 0); // Don't revisit N.
3005 // fold selects based on a setcc into other things, such as min/max/abs
3006 if (N0.getOpcode() == ISD::SETCC) {
3008 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
3009 // having to say they don't support SELECT_CC on every type the DAG knows
3010 // about, since there is no way to mark an opcode illegal at all value types
3011 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
3012 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
3013 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
3014 N0.getOperand(0), N0.getOperand(1),
3015 N1, N2, N0.getOperand(2));
3016 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
3022 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
3023 SDValue N0 = N->getOperand(0);
3024 SDValue N1 = N->getOperand(1);
3025 SDValue N2 = N->getOperand(2);
3026 SDValue N3 = N->getOperand(3);
3027 SDValue N4 = N->getOperand(4);
3028 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
3030 // fold select_cc lhs, rhs, x, x, cc -> x
3034 // Determine if the condition we're dealing with is constant
3035 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
3036 N0, N1, CC, N->getDebugLoc(), false);
3037 if (SCC.getNode()) AddToWorkList(SCC.getNode());
3039 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
3040 if (!SCCC->isNullValue())
3041 return N2; // cond always true -> true val
3043 return N3; // cond always false -> false val
3046 // Fold to a simpler select_cc
3047 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
3048 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
3049 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
3052 // If we can fold this based on the true/false value, do so.
3053 if (SimplifySelectOps(N, N2, N3))
3054 return SDValue(N, 0); // Don't revisit N.
3056 // fold select_cc into other things, such as min/max/abs
3057 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
3060 SDValue DAGCombiner::visitSETCC(SDNode *N) {
3061 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
3062 cast<CondCodeSDNode>(N->getOperand(2))->get(),
3066 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
3067 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
3068 // transformation. Returns true if extension are possible and the above
3069 // mentioned transformation is profitable.
3070 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
3072 SmallVector<SDNode*, 4> &ExtendNodes,
3073 const TargetLowering &TLI) {
3074 bool HasCopyToRegUses = false;
3075 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
3076 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
3077 UE = N0.getNode()->use_end();
3082 if (UI.getUse().getResNo() != N0.getResNo())
3084 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
3085 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
3086 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
3087 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
3088 // Sign bits will be lost after a zext.
3091 for (unsigned i = 0; i != 2; ++i) {
3092 SDValue UseOp = User->getOperand(i);
3095 if (!isa<ConstantSDNode>(UseOp))
3100 ExtendNodes.push_back(User);
3103 // If truncates aren't free and there are users we can't
3104 // extend, it isn't worthwhile.
3107 // Remember if this value is live-out.
3108 if (User->getOpcode() == ISD::CopyToReg)
3109 HasCopyToRegUses = true;
3112 if (HasCopyToRegUses) {
3113 bool BothLiveOut = false;
3114 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3116 SDUse &Use = UI.getUse();
3117 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
3123 // Both unextended and extended values are live out. There had better be
3124 // good a reason for the transformation.
3125 return ExtendNodes.size();
3130 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
3131 SDValue N0 = N->getOperand(0);
3132 EVT VT = N->getValueType(0);
3134 // fold (sext c1) -> c1
3135 if (isa<ConstantSDNode>(N0))
3136 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
3138 // fold (sext (sext x)) -> (sext x)
3139 // fold (sext (aext x)) -> (sext x)
3140 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3141 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
3144 if (N0.getOpcode() == ISD::TRUNCATE) {
3145 // fold (sext (truncate (load x))) -> (sext (smaller load x))
3146 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
3147 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3148 if (NarrowLoad.getNode()) {
3149 if (NarrowLoad.getNode() != N0.getNode())
3150 CombineTo(N0.getNode(), NarrowLoad);
3151 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3154 // See if the value being truncated is already sign extended. If so, just
3155 // eliminate the trunc/sext pair.
3156 SDValue Op = N0.getOperand(0);
3157 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
3158 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
3159 unsigned DestBits = VT.getScalarType().getSizeInBits();
3160 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
3162 if (OpBits == DestBits) {
3163 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
3164 // bits, it is already ready.
3165 if (NumSignBits > DestBits-MidBits)
3167 } else if (OpBits < DestBits) {
3168 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
3169 // bits, just sext from i32.
3170 if (NumSignBits > OpBits-MidBits)
3171 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
3173 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
3174 // bits, just truncate to i32.
3175 if (NumSignBits > OpBits-MidBits)
3176 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3179 // fold (sext (truncate x)) -> (sextinreg x).
3180 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
3181 N0.getValueType())) {
3182 if (OpBits < DestBits)
3183 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
3184 else if (OpBits > DestBits)
3185 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
3186 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
3187 DAG.getValueType(N0.getValueType()));
3191 // fold (sext (load x)) -> (sext (truncate (sextload x)))
3192 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3193 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3194 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
3195 bool DoXform = true;
3196 SmallVector<SDNode*, 4> SetCCs;
3197 if (!N0.hasOneUse())
3198 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
3200 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3201 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3203 LN0->getBasePtr(), LN0->getSrcValue(),
3204 LN0->getSrcValueOffset(),
3206 LN0->isVolatile(), LN0->isNonTemporal(),
3207 LN0->getAlignment());
3208 CombineTo(N, ExtLoad);
3209 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3210 N0.getValueType(), ExtLoad);
3211 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3213 // Extend SetCC uses if necessary.
3214 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3215 SDNode *SetCC = SetCCs[i];
3216 SmallVector<SDValue, 4> Ops;
3218 for (unsigned j = 0; j != 2; ++j) {
3219 SDValue SOp = SetCC->getOperand(j);
3221 Ops.push_back(ExtLoad);
3223 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND,
3224 N->getDebugLoc(), VT, SOp));
3227 Ops.push_back(SetCC->getOperand(2));
3228 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3229 SetCC->getValueType(0),
3230 &Ops[0], Ops.size()));
3233 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3237 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
3238 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
3239 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3240 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3241 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3242 EVT MemVT = LN0->getMemoryVT();
3243 if ((!LegalOperations && !LN0->isVolatile()) ||
3244 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
3245 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3247 LN0->getBasePtr(), LN0->getSrcValue(),
3248 LN0->getSrcValueOffset(), MemVT,
3249 LN0->isVolatile(), LN0->isNonTemporal(),
3250 LN0->getAlignment());
3251 CombineTo(N, ExtLoad);
3252 CombineTo(N0.getNode(),
3253 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3254 N0.getValueType(), ExtLoad),
3255 ExtLoad.getValue(1));
3256 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3260 if (N0.getOpcode() == ISD::SETCC) {
3261 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
3262 if (VT.isVector() &&
3263 // We know that the # elements of the results is the same as the
3264 // # elements of the compare (and the # elements of the compare result
3265 // for that matter). Check to see that they are the same size. If so,
3266 // we know that the element size of the sext'd result matches the
3267 // element size of the compare operands.
3268 VT.getSizeInBits() == N0.getOperand(0).getValueType().getSizeInBits() &&
3270 // Only do this before legalize for now.
3272 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
3274 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3277 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
3279 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
3281 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3282 NegOne, DAG.getConstant(0, VT),
3283 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3284 if (SCC.getNode()) return SCC;
3285 if (!LegalOperations ||
3286 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
3287 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
3288 DAG.getSetCC(N->getDebugLoc(),
3289 TLI.getSetCCResultType(VT),
3290 N0.getOperand(0), N0.getOperand(1),
3291 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
3292 NegOne, DAG.getConstant(0, VT));
3297 // fold (sext x) -> (zext x) if the sign bit is known zero.
3298 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
3299 DAG.SignBitIsZero(N0))
3300 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3305 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
3306 SDValue N0 = N->getOperand(0);
3307 EVT VT = N->getValueType(0);
3309 // fold (zext c1) -> c1
3310 if (isa<ConstantSDNode>(N0))
3311 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3312 // fold (zext (zext x)) -> (zext x)
3313 // fold (zext (aext x)) -> (zext x)
3314 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3315 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
3318 // fold (zext (truncate (load x))) -> (zext (smaller load x))
3319 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
3320 if (N0.getOpcode() == ISD::TRUNCATE) {
3321 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3322 if (NarrowLoad.getNode()) {
3323 if (NarrowLoad.getNode() != N0.getNode())
3324 CombineTo(N0.getNode(), NarrowLoad);
3325 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3329 // fold (zext (truncate x)) -> (and x, mask)
3330 if (N0.getOpcode() == ISD::TRUNCATE &&
3331 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT)) &&
3332 (!TLI.isTruncateFree(N0.getOperand(0).getValueType(),
3333 N0.getValueType()) ||
3334 !TLI.isZExtFree(N0.getValueType(), VT))) {
3335 SDValue Op = N0.getOperand(0);
3336 if (Op.getValueType().bitsLT(VT)) {
3337 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
3338 } else if (Op.getValueType().bitsGT(VT)) {
3339 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3341 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
3342 N0.getValueType().getScalarType());
3345 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
3346 // if either of the casts is not free.
3347 if (N0.getOpcode() == ISD::AND &&
3348 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3349 N0.getOperand(1).getOpcode() == ISD::Constant &&
3350 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3351 N0.getValueType()) ||
3352 !TLI.isZExtFree(N0.getValueType(), VT))) {
3353 SDValue X = N0.getOperand(0).getOperand(0);
3354 if (X.getValueType().bitsLT(VT)) {
3355 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
3356 } else if (X.getValueType().bitsGT(VT)) {
3357 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
3359 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3360 Mask.zext(VT.getSizeInBits());
3361 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3362 X, DAG.getConstant(Mask, VT));
3365 // fold (zext (load x)) -> (zext (truncate (zextload x)))
3366 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3367 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3368 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
3369 bool DoXform = true;
3370 SmallVector<SDNode*, 4> SetCCs;
3371 if (!N0.hasOneUse())
3372 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
3374 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3375 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3377 LN0->getBasePtr(), LN0->getSrcValue(),
3378 LN0->getSrcValueOffset(),
3380 LN0->isVolatile(), LN0->isNonTemporal(),
3381 LN0->getAlignment());
3382 CombineTo(N, ExtLoad);
3383 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3384 N0.getValueType(), ExtLoad);
3385 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3387 // Extend SetCC uses if necessary.
3388 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3389 SDNode *SetCC = SetCCs[i];
3390 SmallVector<SDValue, 4> Ops;
3392 for (unsigned j = 0; j != 2; ++j) {
3393 SDValue SOp = SetCC->getOperand(j);
3395 Ops.push_back(ExtLoad);
3397 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND,
3398 N->getDebugLoc(), VT, SOp));
3401 Ops.push_back(SetCC->getOperand(2));
3402 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3403 SetCC->getValueType(0),
3404 &Ops[0], Ops.size()));
3407 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3411 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
3412 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
3413 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3414 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3415 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3416 EVT MemVT = LN0->getMemoryVT();
3417 if ((!LegalOperations && !LN0->isVolatile()) ||
3418 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
3419 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3421 LN0->getBasePtr(), LN0->getSrcValue(),
3422 LN0->getSrcValueOffset(), MemVT,
3423 LN0->isVolatile(), LN0->isNonTemporal(),
3424 LN0->getAlignment());
3425 CombineTo(N, ExtLoad);
3426 CombineTo(N0.getNode(),
3427 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
3429 ExtLoad.getValue(1));
3430 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3434 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3435 if (N0.getOpcode() == ISD::SETCC) {
3437 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3438 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3439 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3440 if (SCC.getNode()) return SCC;
3443 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
3444 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
3445 isa<ConstantSDNode>(N0.getOperand(1)) &&
3446 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
3448 if (N0.getOpcode() == ISD::SHL) {
3449 // If the original shl may be shifting out bits, do not perform this
3451 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3452 unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() -
3453 N0.getOperand(0).getOperand(0).getValueType().getSizeInBits();
3454 if (ShAmt > KnownZeroBits)
3457 DebugLoc dl = N->getDebugLoc();
3458 return DAG.getNode(N0.getOpcode(), dl, VT,
3459 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)),
3460 DAG.getNode(ISD::ZERO_EXTEND, dl,
3461 N0.getOperand(1).getValueType(),
3468 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
3469 SDValue N0 = N->getOperand(0);
3470 EVT VT = N->getValueType(0);
3472 // fold (aext c1) -> c1
3473 if (isa<ConstantSDNode>(N0))
3474 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
3475 // fold (aext (aext x)) -> (aext x)
3476 // fold (aext (zext x)) -> (zext x)
3477 // fold (aext (sext x)) -> (sext x)
3478 if (N0.getOpcode() == ISD::ANY_EXTEND ||
3479 N0.getOpcode() == ISD::ZERO_EXTEND ||
3480 N0.getOpcode() == ISD::SIGN_EXTEND)
3481 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
3483 // fold (aext (truncate (load x))) -> (aext (smaller load x))
3484 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
3485 if (N0.getOpcode() == ISD::TRUNCATE) {
3486 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3487 if (NarrowLoad.getNode()) {
3488 if (NarrowLoad.getNode() != N0.getNode())
3489 CombineTo(N0.getNode(), NarrowLoad);
3490 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3494 // fold (aext (truncate x))
3495 if (N0.getOpcode() == ISD::TRUNCATE) {
3496 SDValue TruncOp = N0.getOperand(0);
3497 if (TruncOp.getValueType() == VT)
3498 return TruncOp; // x iff x size == zext size.
3499 if (TruncOp.getValueType().bitsGT(VT))
3500 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
3501 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
3504 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
3505 // if the trunc is not free.
3506 if (N0.getOpcode() == ISD::AND &&
3507 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3508 N0.getOperand(1).getOpcode() == ISD::Constant &&
3509 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3510 N0.getValueType())) {
3511 SDValue X = N0.getOperand(0).getOperand(0);
3512 if (X.getValueType().bitsLT(VT)) {
3513 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
3514 } else if (X.getValueType().bitsGT(VT)) {
3515 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
3517 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3518 Mask.zext(VT.getSizeInBits());
3519 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3520 X, DAG.getConstant(Mask, VT));
3523 // fold (aext (load x)) -> (aext (truncate (extload x)))
3524 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3525 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3526 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
3527 bool DoXform = true;
3528 SmallVector<SDNode*, 4> SetCCs;
3529 if (!N0.hasOneUse())
3530 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
3532 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3533 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
3535 LN0->getBasePtr(), LN0->getSrcValue(),
3536 LN0->getSrcValueOffset(),
3538 LN0->isVolatile(), LN0->isNonTemporal(),
3539 LN0->getAlignment());
3540 CombineTo(N, ExtLoad);
3541 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3542 N0.getValueType(), ExtLoad);
3543 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3545 // Extend SetCC uses if necessary.
3546 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3547 SDNode *SetCC = SetCCs[i];
3548 SmallVector<SDValue, 4> Ops;
3550 for (unsigned j = 0; j != 2; ++j) {
3551 SDValue SOp = SetCC->getOperand(j);
3553 Ops.push_back(ExtLoad);
3555 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND,
3556 N->getDebugLoc(), VT, SOp));
3559 Ops.push_back(SetCC->getOperand(2));
3560 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3561 SetCC->getValueType(0),
3562 &Ops[0], Ops.size()));
3565 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3569 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
3570 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
3571 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
3572 if (N0.getOpcode() == ISD::LOAD &&
3573 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3575 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3576 EVT MemVT = LN0->getMemoryVT();
3577 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
3578 VT, LN0->getChain(), LN0->getBasePtr(),
3580 LN0->getSrcValueOffset(), MemVT,
3581 LN0->isVolatile(), LN0->isNonTemporal(),
3582 LN0->getAlignment());
3583 CombineTo(N, ExtLoad);
3584 CombineTo(N0.getNode(),
3585 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3586 N0.getValueType(), ExtLoad),
3587 ExtLoad.getValue(1));
3588 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3591 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3592 if (N0.getOpcode() == ISD::SETCC) {
3594 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3595 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3596 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3604 /// GetDemandedBits - See if the specified operand can be simplified with the
3605 /// knowledge that only the bits specified by Mask are used. If so, return the
3606 /// simpler operand, otherwise return a null SDValue.
3607 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
3608 switch (V.getOpcode()) {
3612 // If the LHS or RHS don't contribute bits to the or, drop them.
3613 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
3614 return V.getOperand(1);
3615 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
3616 return V.getOperand(0);
3619 // Only look at single-use SRLs.
3620 if (!V.getNode()->hasOneUse())
3622 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
3623 // See if we can recursively simplify the LHS.
3624 unsigned Amt = RHSC->getZExtValue();
3626 // Watch out for shift count overflow though.
3627 if (Amt >= Mask.getBitWidth()) break;
3628 APInt NewMask = Mask << Amt;
3629 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
3630 if (SimplifyLHS.getNode())
3631 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
3632 SimplifyLHS, V.getOperand(1));
3638 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
3639 /// bits and then truncated to a narrower type and where N is a multiple
3640 /// of number of bits of the narrower type, transform it to a narrower load
3641 /// from address + N / num of bits of new type. If the result is to be
3642 /// extended, also fold the extension to form a extending load.
3643 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
3644 unsigned Opc = N->getOpcode();
3645 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
3646 SDValue N0 = N->getOperand(0);
3647 EVT VT = N->getValueType(0);
3650 // This transformation isn't valid for vector loads.
3654 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
3656 if (Opc == ISD::SIGN_EXTEND_INREG) {
3657 ExtType = ISD::SEXTLOAD;
3658 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3659 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT))
3663 unsigned EVTBits = ExtVT.getSizeInBits();
3665 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() && ExtVT.isRound()) {
3666 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3667 ShAmt = N01->getZExtValue();
3668 // Is the shift amount a multiple of size of VT?
3669 if ((ShAmt & (EVTBits-1)) == 0) {
3670 N0 = N0.getOperand(0);
3671 // Is the load width a multiple of size of VT?
3672 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
3678 // Do not generate loads of non-round integer types since these can
3679 // be expensive (and would be wrong if the type is not byte sized).
3680 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() &&
3681 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() >= EVTBits &&
3682 // Do not change the width of a volatile load.
3683 !cast<LoadSDNode>(N0)->isVolatile()) {
3684 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3685 EVT PtrType = N0.getOperand(1).getValueType();
3687 // For big endian targets, we need to adjust the offset to the pointer to
3688 // load the correct bytes.
3689 if (TLI.isBigEndian()) {
3690 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
3691 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
3692 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
3695 uint64_t PtrOff = ShAmt / 8;
3696 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
3697 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
3698 PtrType, LN0->getBasePtr(),
3699 DAG.getConstant(PtrOff, PtrType));
3700 AddToWorkList(NewPtr.getNode());
3702 SDValue Load = (ExtType == ISD::NON_EXTLOAD)
3703 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
3704 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
3705 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign)
3706 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr,
3707 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
3708 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
3711 // Replace the old load's chain with the new load's chain.
3712 WorkListRemover DeadNodes(*this);
3713 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
3716 // Return the new loaded value.
3723 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
3724 SDValue N0 = N->getOperand(0);
3725 SDValue N1 = N->getOperand(1);
3726 EVT VT = N->getValueType(0);
3727 EVT EVT = cast<VTSDNode>(N1)->getVT();
3728 unsigned VTBits = VT.getScalarType().getSizeInBits();
3729 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
3731 // fold (sext_in_reg c1) -> c1
3732 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
3733 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
3735 // If the input is already sign extended, just drop the extension.
3736 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
3739 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
3740 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3741 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
3742 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3743 N0.getOperand(0), N1);
3746 // fold (sext_in_reg (sext x)) -> (sext x)
3747 // fold (sext_in_reg (aext x)) -> (sext x)
3748 // if x is small enough.
3749 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
3750 SDValue N00 = N0.getOperand(0);
3751 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
3752 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
3753 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
3756 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
3757 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
3758 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
3760 // fold operands of sext_in_reg based on knowledge that the top bits are not
3762 if (SimplifyDemandedBits(SDValue(N, 0)))
3763 return SDValue(N, 0);
3765 // fold (sext_in_reg (load x)) -> (smaller sextload x)
3766 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
3767 SDValue NarrowLoad = ReduceLoadWidth(N);
3768 if (NarrowLoad.getNode())
3771 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
3772 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
3773 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
3774 if (N0.getOpcode() == ISD::SRL) {
3775 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
3776 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
3777 // We can turn this into an SRA iff the input to the SRL is already sign
3779 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
3780 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
3781 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
3782 N0.getOperand(0), N0.getOperand(1));
3786 // fold (sext_inreg (extload x)) -> (sextload x)
3787 if (ISD::isEXTLoad(N0.getNode()) &&
3788 ISD::isUNINDEXEDLoad(N0.getNode()) &&
3789 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3790 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3791 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
3792 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3793 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3795 LN0->getBasePtr(), LN0->getSrcValue(),
3796 LN0->getSrcValueOffset(), EVT,
3797 LN0->isVolatile(), LN0->isNonTemporal(),
3798 LN0->getAlignment());
3799 CombineTo(N, ExtLoad);
3800 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3801 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3803 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
3804 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3806 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3807 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3808 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
3809 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3810 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3812 LN0->getBasePtr(), LN0->getSrcValue(),
3813 LN0->getSrcValueOffset(), EVT,
3814 LN0->isVolatile(), LN0->isNonTemporal(),
3815 LN0->getAlignment());
3816 CombineTo(N, ExtLoad);
3817 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3818 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3823 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
3824 SDValue N0 = N->getOperand(0);
3825 EVT VT = N->getValueType(0);
3828 if (N0.getValueType() == N->getValueType(0))
3830 // fold (truncate c1) -> c1
3831 if (isa<ConstantSDNode>(N0))
3832 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
3833 // fold (truncate (truncate x)) -> (truncate x)
3834 if (N0.getOpcode() == ISD::TRUNCATE)
3835 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
3836 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
3837 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
3838 N0.getOpcode() == ISD::SIGN_EXTEND ||
3839 N0.getOpcode() == ISD::ANY_EXTEND) {
3840 if (N0.getOperand(0).getValueType().bitsLT(VT))
3841 // if the source is smaller than the dest, we still need an extend
3842 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
3844 else if (N0.getOperand(0).getValueType().bitsGT(VT))
3845 // if the source is larger than the dest, than we just need the truncate
3846 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
3848 // if the source and dest are the same type, we can drop both the extend
3849 // and the truncate.
3850 return N0.getOperand(0);
3853 // See if we can simplify the input to this truncate through knowledge that
3854 // only the low bits are being used. For example "trunc (or (shl x, 8), y)"
3857 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
3858 VT.getSizeInBits()));
3859 if (Shorter.getNode())
3860 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
3862 // fold (truncate (load x)) -> (smaller load x)
3863 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
3864 return ReduceLoadWidth(N);
3867 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
3868 SDValue Elt = N->getOperand(i);
3869 if (Elt.getOpcode() != ISD::MERGE_VALUES)
3870 return Elt.getNode();
3871 return Elt.getOperand(Elt.getResNo()).getNode();
3874 /// CombineConsecutiveLoads - build_pair (load, load) -> load
3875 /// if load locations are consecutive.
3876 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
3877 assert(N->getOpcode() == ISD::BUILD_PAIR);
3879 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
3880 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
3881 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse())
3883 EVT LD1VT = LD1->getValueType(0);
3885 if (ISD::isNON_EXTLoad(LD2) &&
3887 // If both are volatile this would reduce the number of volatile loads.
3888 // If one is volatile it might be ok, but play conservative and bail out.
3889 !LD1->isVolatile() &&
3890 !LD2->isVolatile() &&
3891 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
3892 unsigned Align = LD1->getAlignment();
3893 unsigned NewAlign = TLI.getTargetData()->
3894 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
3896 if (NewAlign <= Align &&
3897 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
3898 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
3899 LD1->getBasePtr(), LD1->getSrcValue(),
3900 LD1->getSrcValueOffset(), false, false, Align);
3906 SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
3907 SDValue N0 = N->getOperand(0);
3908 EVT VT = N->getValueType(0);
3910 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
3911 // Only do this before legalize, since afterward the target may be depending
3912 // on the bitconvert.
3913 // First check to see if this is all constant.
3915 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
3917 bool isSimple = true;
3918 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
3919 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
3920 N0.getOperand(i).getOpcode() != ISD::Constant &&
3921 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
3926 EVT DestEltVT = N->getValueType(0).getVectorElementType();
3927 assert(!DestEltVT.isVector() &&
3928 "Element type of vector ValueType must not be vector!");
3930 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT);
3933 // If the input is a constant, let getNode fold it.
3934 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
3935 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0);
3936 if (Res.getNode() != N) {
3937 if (!LegalOperations ||
3938 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
3941 // Folding it resulted in an illegal node, and it's too late to
3942 // do that. Clean up the old node and forego the transformation.
3943 // Ideally this won't happen very often, because instcombine
3944 // and the earlier dagcombine runs (where illegal nodes are
3945 // permitted) should have folded most of them already.
3946 DAG.DeleteNode(Res.getNode());
3950 // (conv (conv x, t1), t2) -> (conv x, t2)
3951 if (N0.getOpcode() == ISD::BIT_CONVERT)
3952 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT,
3955 // fold (conv (load x)) -> (load (conv*)x)
3956 // If the resultant load doesn't need a higher alignment than the original!
3957 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
3958 // Do not change the width of a volatile load.
3959 !cast<LoadSDNode>(N0)->isVolatile() &&
3960 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
3961 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3962 unsigned Align = TLI.getTargetData()->
3963 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
3964 unsigned OrigAlign = LN0->getAlignment();
3966 if (Align <= OrigAlign) {
3967 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
3969 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3970 LN0->isVolatile(), LN0->isNonTemporal(),
3973 CombineTo(N0.getNode(),
3974 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
3975 N0.getValueType(), Load),
3981 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
3982 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
3983 // This often reduces constant pool loads.
3984 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
3985 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
3986 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT,
3988 AddToWorkList(NewConv.getNode());
3990 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
3991 if (N0.getOpcode() == ISD::FNEG)
3992 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3993 NewConv, DAG.getConstant(SignBit, VT));
3994 assert(N0.getOpcode() == ISD::FABS);
3995 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3996 NewConv, DAG.getConstant(~SignBit, VT));
3999 // fold (bitconvert (fcopysign cst, x)) ->
4000 // (or (and (bitconvert x), sign), (and cst, (not sign)))
4001 // Note that we don't handle (copysign x, cst) because this can always be
4002 // folded to an fneg or fabs.
4003 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
4004 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
4005 VT.isInteger() && !VT.isVector()) {
4006 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
4007 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
4008 if (isTypeLegal(IntXVT)) {
4009 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
4010 IntXVT, N0.getOperand(1));
4011 AddToWorkList(X.getNode());
4013 // If X has a different width than the result/lhs, sext it or truncate it.
4014 unsigned VTWidth = VT.getSizeInBits();
4015 if (OrigXWidth < VTWidth) {
4016 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
4017 AddToWorkList(X.getNode());
4018 } else if (OrigXWidth > VTWidth) {
4019 // To get the sign bit in the right place, we have to shift it right
4020 // before truncating.
4021 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
4022 X.getValueType(), X,
4023 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
4024 AddToWorkList(X.getNode());
4025 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4026 AddToWorkList(X.getNode());
4029 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
4030 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
4031 X, DAG.getConstant(SignBit, VT));
4032 AddToWorkList(X.getNode());
4034 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
4035 VT, N0.getOperand(0));
4036 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
4037 Cst, DAG.getConstant(~SignBit, VT));
4038 AddToWorkList(Cst.getNode());
4040 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
4044 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
4045 if (N0.getOpcode() == ISD::BUILD_PAIR) {
4046 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
4047 if (CombineLD.getNode())
4054 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
4055 EVT VT = N->getValueType(0);
4056 return CombineConsecutiveLoads(N, VT);
4059 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
4060 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
4061 /// destination element value type.
4062 SDValue DAGCombiner::
4063 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
4064 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
4066 // If this is already the right type, we're done.
4067 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
4069 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
4070 unsigned DstBitSize = DstEltVT.getSizeInBits();
4072 // If this is a conversion of N elements of one type to N elements of another
4073 // type, convert each element. This handles FP<->INT cases.
4074 if (SrcBitSize == DstBitSize) {
4075 SmallVector<SDValue, 8> Ops;
4076 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
4077 SDValue Op = BV->getOperand(i);
4078 // If the vector element type is not legal, the BUILD_VECTOR operands
4079 // are promoted and implicitly truncated. Make that explicit here.
4080 if (Op.getValueType() != SrcEltVT)
4081 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
4082 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(),
4084 AddToWorkList(Ops.back().getNode());
4086 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
4087 BV->getValueType(0).getVectorNumElements());
4088 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4089 &Ops[0], Ops.size());
4092 // Otherwise, we're growing or shrinking the elements. To avoid having to
4093 // handle annoying details of growing/shrinking FP values, we convert them to
4095 if (SrcEltVT.isFloatingPoint()) {
4096 // Convert the input float vector to a int vector where the elements are the
4098 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
4099 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
4100 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
4104 // Now we know the input is an integer vector. If the output is a FP type,
4105 // convert to integer first, then to FP of the right size.
4106 if (DstEltVT.isFloatingPoint()) {
4107 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
4108 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
4109 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
4111 // Next, convert to FP elements of the same size.
4112 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
4115 // Okay, we know the src/dst types are both integers of differing types.
4116 // Handling growing first.
4117 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
4118 if (SrcBitSize < DstBitSize) {
4119 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
4121 SmallVector<SDValue, 8> Ops;
4122 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
4123 i += NumInputsPerOutput) {
4124 bool isLE = TLI.isLittleEndian();
4125 APInt NewBits = APInt(DstBitSize, 0);
4126 bool EltIsUndef = true;
4127 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
4128 // Shift the previously computed bits over.
4129 NewBits <<= SrcBitSize;
4130 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
4131 if (Op.getOpcode() == ISD::UNDEF) continue;
4134 NewBits |= APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).
4135 zextOrTrunc(SrcBitSize).zext(DstBitSize);
4139 Ops.push_back(DAG.getUNDEF(DstEltVT));
4141 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
4144 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
4145 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4146 &Ops[0], Ops.size());
4149 // Finally, this must be the case where we are shrinking elements: each input
4150 // turns into multiple outputs.
4151 bool isS2V = ISD::isScalarToVector(BV);
4152 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
4153 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
4154 NumOutputsPerInput*BV->getNumOperands());
4155 SmallVector<SDValue, 8> Ops;
4157 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
4158 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
4159 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
4160 Ops.push_back(DAG.getUNDEF(DstEltVT));
4164 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))->
4165 getAPIntValue()).zextOrTrunc(SrcBitSize);
4167 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
4168 APInt ThisVal = APInt(OpVal).trunc(DstBitSize);
4169 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
4170 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal)
4171 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
4172 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
4174 OpVal = OpVal.lshr(DstBitSize);
4177 // For big endian targets, swap the order of the pieces of each element.
4178 if (TLI.isBigEndian())
4179 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
4182 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4183 &Ops[0], Ops.size());
4186 SDValue DAGCombiner::visitFADD(SDNode *N) {
4187 SDValue N0 = N->getOperand(0);
4188 SDValue N1 = N->getOperand(1);
4189 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4190 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4191 EVT VT = N->getValueType(0);
4194 if (VT.isVector()) {
4195 SDValue FoldedVOp = SimplifyVBinOp(N);
4196 if (FoldedVOp.getNode()) return FoldedVOp;
4199 // fold (fadd c1, c2) -> (fadd c1, c2)
4200 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4201 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
4202 // canonicalize constant to RHS
4203 if (N0CFP && !N1CFP)
4204 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
4205 // fold (fadd A, 0) -> A
4206 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4208 // fold (fadd A, (fneg B)) -> (fsub A, B)
4209 if (isNegatibleForFree(N1, LegalOperations) == 2)
4210 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
4211 GetNegatedExpression(N1, DAG, LegalOperations));
4212 // fold (fadd (fneg A), B) -> (fsub B, A)
4213 if (isNegatibleForFree(N0, LegalOperations) == 2)
4214 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
4215 GetNegatedExpression(N0, DAG, LegalOperations));
4217 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
4218 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
4219 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4220 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
4221 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
4222 N0.getOperand(1), N1));
4227 SDValue DAGCombiner::visitFSUB(SDNode *N) {
4228 SDValue N0 = N->getOperand(0);
4229 SDValue N1 = N->getOperand(1);
4230 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4231 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4232 EVT VT = N->getValueType(0);
4235 if (VT.isVector()) {
4236 SDValue FoldedVOp = SimplifyVBinOp(N);
4237 if (FoldedVOp.getNode()) return FoldedVOp;
4240 // fold (fsub c1, c2) -> c1-c2
4241 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4242 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
4243 // fold (fsub A, 0) -> A
4244 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4246 // fold (fsub 0, B) -> -B
4247 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
4248 if (isNegatibleForFree(N1, LegalOperations))
4249 return GetNegatedExpression(N1, DAG, LegalOperations);
4250 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4251 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
4253 // fold (fsub A, (fneg B)) -> (fadd A, B)
4254 if (isNegatibleForFree(N1, LegalOperations))
4255 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
4256 GetNegatedExpression(N1, DAG, LegalOperations));
4261 SDValue DAGCombiner::visitFMUL(SDNode *N) {
4262 SDValue N0 = N->getOperand(0);
4263 SDValue N1 = N->getOperand(1);
4264 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4265 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4266 EVT VT = N->getValueType(0);
4269 if (VT.isVector()) {
4270 SDValue FoldedVOp = SimplifyVBinOp(N);
4271 if (FoldedVOp.getNode()) return FoldedVOp;
4274 // fold (fmul c1, c2) -> c1*c2
4275 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4276 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
4277 // canonicalize constant to RHS
4278 if (N0CFP && !N1CFP)
4279 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
4280 // fold (fmul A, 0) -> 0
4281 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4283 // fold (fmul A, 0) -> 0, vector edition.
4284 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode()))
4286 // fold (fmul X, 2.0) -> (fadd X, X)
4287 if (N1CFP && N1CFP->isExactlyValue(+2.0))
4288 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
4289 // fold (fmul X, -1.0) -> (fneg X)
4290 if (N1CFP && N1CFP->isExactlyValue(-1.0))
4291 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4292 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
4294 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
4295 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4296 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4297 // Both can be negated for free, check to see if at least one is cheaper
4299 if (LHSNeg == 2 || RHSNeg == 2)
4300 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4301 GetNegatedExpression(N0, DAG, LegalOperations),
4302 GetNegatedExpression(N1, DAG, LegalOperations));
4306 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
4307 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
4308 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4309 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
4310 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4311 N0.getOperand(1), N1));
4316 SDValue DAGCombiner::visitFDIV(SDNode *N) {
4317 SDValue N0 = N->getOperand(0);
4318 SDValue N1 = N->getOperand(1);
4319 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4320 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4321 EVT VT = N->getValueType(0);
4324 if (VT.isVector()) {
4325 SDValue FoldedVOp = SimplifyVBinOp(N);
4326 if (FoldedVOp.getNode()) return FoldedVOp;
4329 // fold (fdiv c1, c2) -> c1/c2
4330 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4331 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
4334 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
4335 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4336 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4337 // Both can be negated for free, check to see if at least one is cheaper
4339 if (LHSNeg == 2 || RHSNeg == 2)
4340 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
4341 GetNegatedExpression(N0, DAG, LegalOperations),
4342 GetNegatedExpression(N1, DAG, LegalOperations));
4349 SDValue DAGCombiner::visitFREM(SDNode *N) {
4350 SDValue N0 = N->getOperand(0);
4351 SDValue N1 = N->getOperand(1);
4352 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4353 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4354 EVT VT = N->getValueType(0);
4356 // fold (frem c1, c2) -> fmod(c1,c2)
4357 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4358 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
4363 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
4364 SDValue N0 = N->getOperand(0);
4365 SDValue N1 = N->getOperand(1);
4366 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4367 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4368 EVT VT = N->getValueType(0);
4370 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
4371 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
4374 const APFloat& V = N1CFP->getValueAPF();
4375 // copysign(x, c1) -> fabs(x) iff ispos(c1)
4376 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
4377 if (!V.isNegative()) {
4378 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
4379 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4381 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4382 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
4383 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
4387 // copysign(fabs(x), y) -> copysign(x, y)
4388 // copysign(fneg(x), y) -> copysign(x, y)
4389 // copysign(copysign(x,z), y) -> copysign(x, y)
4390 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
4391 N0.getOpcode() == ISD::FCOPYSIGN)
4392 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4393 N0.getOperand(0), N1);
4395 // copysign(x, abs(y)) -> abs(x)
4396 if (N1.getOpcode() == ISD::FABS)
4397 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4399 // copysign(x, copysign(y,z)) -> copysign(x, z)
4400 if (N1.getOpcode() == ISD::FCOPYSIGN)
4401 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4402 N0, N1.getOperand(1));
4404 // copysign(x, fp_extend(y)) -> copysign(x, y)
4405 // copysign(x, fp_round(y)) -> copysign(x, y)
4406 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
4407 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4408 N0, N1.getOperand(0));
4413 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
4414 SDValue N0 = N->getOperand(0);
4415 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4416 EVT VT = N->getValueType(0);
4417 EVT OpVT = N0.getValueType();
4419 // fold (sint_to_fp c1) -> c1fp
4420 if (N0C && OpVT != MVT::ppcf128)
4421 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4423 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
4424 // but UINT_TO_FP is legal on this target, try to convert.
4425 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
4426 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
4427 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
4428 if (DAG.SignBitIsZero(N0))
4429 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4435 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
4436 SDValue N0 = N->getOperand(0);
4437 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4438 EVT VT = N->getValueType(0);
4439 EVT OpVT = N0.getValueType();
4441 // fold (uint_to_fp c1) -> c1fp
4442 if (N0C && OpVT != MVT::ppcf128)
4443 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4445 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
4446 // but SINT_TO_FP is legal on this target, try to convert.
4447 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
4448 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
4449 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
4450 if (DAG.SignBitIsZero(N0))
4451 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4457 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
4458 SDValue N0 = N->getOperand(0);
4459 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4460 EVT VT = N->getValueType(0);
4462 // fold (fp_to_sint c1fp) -> c1
4464 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
4469 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
4470 SDValue N0 = N->getOperand(0);
4471 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4472 EVT VT = N->getValueType(0);
4474 // fold (fp_to_uint c1fp) -> c1
4475 if (N0CFP && VT != MVT::ppcf128)
4476 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
4481 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
4482 SDValue N0 = N->getOperand(0);
4483 SDValue N1 = N->getOperand(1);
4484 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4485 EVT VT = N->getValueType(0);
4487 // fold (fp_round c1fp) -> c1fp
4488 if (N0CFP && N0.getValueType() != MVT::ppcf128)
4489 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
4491 // fold (fp_round (fp_extend x)) -> x
4492 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
4493 return N0.getOperand(0);
4495 // fold (fp_round (fp_round x)) -> (fp_round x)
4496 if (N0.getOpcode() == ISD::FP_ROUND) {
4497 // This is a value preserving truncation if both round's are.
4498 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
4499 N0.getNode()->getConstantOperandVal(1) == 1;
4500 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
4501 DAG.getIntPtrConstant(IsTrunc));
4504 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
4505 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
4506 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
4507 N0.getOperand(0), N1);
4508 AddToWorkList(Tmp.getNode());
4509 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4510 Tmp, N0.getOperand(1));
4516 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
4517 SDValue N0 = N->getOperand(0);
4518 EVT VT = N->getValueType(0);
4519 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4520 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4522 // fold (fp_round_inreg c1fp) -> c1fp
4523 if (N0CFP && isTypeLegal(EVT)) {
4524 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
4525 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
4531 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
4532 SDValue N0 = N->getOperand(0);
4533 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4534 EVT VT = N->getValueType(0);
4536 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
4537 if (N->hasOneUse() &&
4538 N->use_begin()->getOpcode() == ISD::FP_ROUND)
4541 // fold (fp_extend c1fp) -> c1fp
4542 if (N0CFP && VT != MVT::ppcf128)
4543 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
4545 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
4547 if (N0.getOpcode() == ISD::FP_ROUND
4548 && N0.getNode()->getConstantOperandVal(1) == 1) {
4549 SDValue In = N0.getOperand(0);
4550 if (In.getValueType() == VT) return In;
4551 if (VT.bitsLT(In.getValueType()))
4552 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
4553 In, N0.getOperand(1));
4554 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
4557 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
4558 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
4559 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4560 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4561 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4562 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4564 LN0->getBasePtr(), LN0->getSrcValue(),
4565 LN0->getSrcValueOffset(),
4567 LN0->isVolatile(), LN0->isNonTemporal(),
4568 LN0->getAlignment());
4569 CombineTo(N, ExtLoad);
4570 CombineTo(N0.getNode(),
4571 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
4572 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
4573 ExtLoad.getValue(1));
4574 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4580 SDValue DAGCombiner::visitFNEG(SDNode *N) {
4581 SDValue N0 = N->getOperand(0);
4582 EVT VT = N->getValueType(0);
4584 if (isNegatibleForFree(N0, LegalOperations))
4585 return GetNegatedExpression(N0, DAG, LegalOperations);
4587 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
4588 // constant pool values.
4589 if (N0.getOpcode() == ISD::BIT_CONVERT &&
4591 N0.getNode()->hasOneUse() &&
4592 N0.getOperand(0).getValueType().isInteger()) {
4593 SDValue Int = N0.getOperand(0);
4594 EVT IntVT = Int.getValueType();
4595 if (IntVT.isInteger() && !IntVT.isVector()) {
4596 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
4597 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
4598 AddToWorkList(Int.getNode());
4599 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4607 SDValue DAGCombiner::visitFABS(SDNode *N) {
4608 SDValue N0 = N->getOperand(0);
4609 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4610 EVT VT = N->getValueType(0);
4612 // fold (fabs c1) -> fabs(c1)
4613 if (N0CFP && VT != MVT::ppcf128)
4614 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4615 // fold (fabs (fabs x)) -> (fabs x)
4616 if (N0.getOpcode() == ISD::FABS)
4617 return N->getOperand(0);
4618 // fold (fabs (fneg x)) -> (fabs x)
4619 // fold (fabs (fcopysign x, y)) -> (fabs x)
4620 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
4621 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
4623 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
4624 // constant pool values.
4625 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
4626 N0.getOperand(0).getValueType().isInteger() &&
4627 !N0.getOperand(0).getValueType().isVector()) {
4628 SDValue Int = N0.getOperand(0);
4629 EVT IntVT = Int.getValueType();
4630 if (IntVT.isInteger() && !IntVT.isVector()) {
4631 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
4632 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
4633 AddToWorkList(Int.getNode());
4634 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4635 N->getValueType(0), Int);
4642 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
4643 SDValue Chain = N->getOperand(0);
4644 SDValue N1 = N->getOperand(1);
4645 SDValue N2 = N->getOperand(2);
4647 // If N is a constant we could fold this into a fallthrough or unconditional
4648 // branch. However that doesn't happen very often in normal code, because
4649 // Instcombine/SimplifyCFG should have handled the available opportunities.
4650 // If we did this folding here, it would be necessary to update the
4651 // MachineBasicBlock CFG, which is awkward.
4653 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
4655 if (N1.getOpcode() == ISD::SETCC &&
4656 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
4657 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
4658 Chain, N1.getOperand(2),
4659 N1.getOperand(0), N1.getOperand(1), N2);
4663 if (N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) {
4664 // Look past truncate.
4665 Trunc = N1.getNode();
4666 N1 = N1.getOperand(0);
4669 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) {
4670 // Match this pattern so that we can generate simpler code:
4673 // %b = and i32 %a, 2
4674 // %c = srl i32 %b, 1
4675 // brcond i32 %c ...
4680 // %b = and i32 %a, 2
4681 // %c = setcc eq %b, 0
4684 // This applies only when the AND constant value has one bit set and the
4685 // SRL constant is equal to the log2 of the AND constant. The back-end is
4686 // smart enough to convert the result into a TEST/JMP sequence.
4687 SDValue Op0 = N1.getOperand(0);
4688 SDValue Op1 = N1.getOperand(1);
4690 if (Op0.getOpcode() == ISD::AND &&
4691 Op1.getOpcode() == ISD::Constant) {
4692 SDValue AndOp1 = Op0.getOperand(1);
4694 if (AndOp1.getOpcode() == ISD::Constant) {
4695 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
4697 if (AndConst.isPowerOf2() &&
4698 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
4700 DAG.getSetCC(N->getDebugLoc(),
4701 TLI.getSetCCResultType(Op0.getValueType()),
4702 Op0, DAG.getConstant(0, Op0.getValueType()),
4705 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
4706 MVT::Other, Chain, SetCC, N2);
4707 // Don't add the new BRCond into the worklist or else SimplifySelectCC
4708 // will convert it back to (X & C1) >> C2.
4709 CombineTo(N, NewBRCond, false);
4710 // Truncate is dead.
4712 removeFromWorkList(Trunc);
4713 DAG.DeleteNode(Trunc);
4715 // Replace the uses of SRL with SETCC
4716 WorkListRemover DeadNodes(*this);
4717 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
4718 removeFromWorkList(N1.getNode());
4719 DAG.DeleteNode(N1.getNode());
4720 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4726 // Transform br(xor(x, y)) -> br(x != y)
4727 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
4728 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
4729 SDNode *TheXor = N1.getNode();
4730 SDValue Op0 = TheXor->getOperand(0);
4731 SDValue Op1 = TheXor->getOperand(1);
4732 if (Op0.getOpcode() == Op1.getOpcode()) {
4733 // Avoid missing important xor optimizations.
4734 SDValue Tmp = visitXOR(TheXor);
4735 if (Tmp.getNode()) {
4736 DEBUG(dbgs() << "\nReplacing.8 ";
4738 dbgs() << "\nWith: ";
4739 Tmp.getNode()->dump(&DAG);
4741 WorkListRemover DeadNodes(*this);
4742 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes);
4743 removeFromWorkList(TheXor);
4744 DAG.DeleteNode(TheXor);
4745 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
4746 MVT::Other, Chain, Tmp, N2);
4750 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
4752 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
4753 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
4754 Op0.getOpcode() == ISD::XOR) {
4755 TheXor = Op0.getNode();
4759 SDValue NodeToReplace = Trunc ? SDValue(Trunc, 0) : N1;
4761 EVT SetCCVT = NodeToReplace.getValueType();
4763 SetCCVT = TLI.getSetCCResultType(SetCCVT);
4764 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
4767 Equal ? ISD::SETEQ : ISD::SETNE);
4768 // Replace the uses of XOR with SETCC
4769 WorkListRemover DeadNodes(*this);
4770 DAG.ReplaceAllUsesOfValueWith(NodeToReplace, SetCC, &DeadNodes);
4771 removeFromWorkList(NodeToReplace.getNode());
4772 DAG.DeleteNode(NodeToReplace.getNode());
4773 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
4774 MVT::Other, Chain, SetCC, N2);
4781 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
4783 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
4784 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
4785 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
4787 // If N is a constant we could fold this into a fallthrough or unconditional
4788 // branch. However that doesn't happen very often in normal code, because
4789 // Instcombine/SimplifyCFG should have handled the available opportunities.
4790 // If we did this folding here, it would be necessary to update the
4791 // MachineBasicBlock CFG, which is awkward.
4793 // Use SimplifySetCC to simplify SETCC's.
4794 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
4795 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
4797 if (Simp.getNode()) AddToWorkList(Simp.getNode());
4799 // fold to a simpler setcc
4800 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
4801 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
4802 N->getOperand(0), Simp.getOperand(2),
4803 Simp.getOperand(0), Simp.getOperand(1),
4809 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
4810 /// pre-indexed load / store when the base pointer is an add or subtract
4811 /// and it has other uses besides the load / store. After the
4812 /// transformation, the new indexed load / store has effectively folded
4813 /// the add / subtract in and all of its other uses are redirected to the
4814 /// new load / store.
4815 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
4816 if (!LegalOperations)
4822 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4823 if (LD->isIndexed())
4825 VT = LD->getMemoryVT();
4826 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
4827 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
4829 Ptr = LD->getBasePtr();
4830 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4831 if (ST->isIndexed())
4833 VT = ST->getMemoryVT();
4834 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
4835 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
4837 Ptr = ST->getBasePtr();
4843 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
4844 // out. There is no reason to make this a preinc/predec.
4845 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
4846 Ptr.getNode()->hasOneUse())
4849 // Ask the target to do addressing mode selection.
4852 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4853 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
4855 // Don't create a indexed load / store with zero offset.
4856 if (isa<ConstantSDNode>(Offset) &&
4857 cast<ConstantSDNode>(Offset)->isNullValue())
4860 // Try turning it into a pre-indexed load / store except when:
4861 // 1) The new base ptr is a frame index.
4862 // 2) If N is a store and the new base ptr is either the same as or is a
4863 // predecessor of the value being stored.
4864 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
4865 // that would create a cycle.
4866 // 4) All uses are load / store ops that use it as old base ptr.
4868 // Check #1. Preinc'ing a frame index would require copying the stack pointer
4869 // (plus the implicit offset) to a register to preinc anyway.
4870 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
4875 SDValue Val = cast<StoreSDNode>(N)->getValue();
4876 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
4880 // Now check for #3 and #4.
4881 bool RealUse = false;
4882 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
4883 E = Ptr.getNode()->use_end(); I != E; ++I) {
4887 if (Use->isPredecessorOf(N))
4890 if (!((Use->getOpcode() == ISD::LOAD &&
4891 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
4892 (Use->getOpcode() == ISD::STORE &&
4893 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
4902 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
4903 BasePtr, Offset, AM);
4905 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
4906 BasePtr, Offset, AM);
4909 DEBUG(dbgs() << "\nReplacing.4 ";
4911 dbgs() << "\nWith: ";
4912 Result.getNode()->dump(&DAG);
4914 WorkListRemover DeadNodes(*this);
4916 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
4918 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
4921 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
4925 // Finally, since the node is now dead, remove it from the graph.
4928 // Replace the uses of Ptr with uses of the updated base value.
4929 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
4931 removeFromWorkList(Ptr.getNode());
4932 DAG.DeleteNode(Ptr.getNode());
4937 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
4938 /// add / sub of the base pointer node into a post-indexed load / store.
4939 /// The transformation folded the add / subtract into the new indexed
4940 /// load / store effectively and all of its uses are redirected to the
4941 /// new load / store.
4942 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
4943 if (!LegalOperations)
4949 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4950 if (LD->isIndexed())
4952 VT = LD->getMemoryVT();
4953 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
4954 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
4956 Ptr = LD->getBasePtr();
4957 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4958 if (ST->isIndexed())
4960 VT = ST->getMemoryVT();
4961 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
4962 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
4964 Ptr = ST->getBasePtr();
4970 if (Ptr.getNode()->hasOneUse())
4973 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
4974 E = Ptr.getNode()->use_end(); I != E; ++I) {
4977 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
4982 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4983 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
4984 if (Ptr == Offset && Op->getOpcode() == ISD::ADD)
4985 std::swap(BasePtr, Offset);
4988 // Don't create a indexed load / store with zero offset.
4989 if (isa<ConstantSDNode>(Offset) &&
4990 cast<ConstantSDNode>(Offset)->isNullValue())
4993 // Try turning it into a post-indexed load / store except when
4994 // 1) All uses are load / store ops that use it as base ptr.
4995 // 2) Op must be independent of N, i.e. Op is neither a predecessor
4996 // nor a successor of N. Otherwise, if Op is folded that would
4999 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
5003 bool TryNext = false;
5004 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
5005 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
5007 if (Use == Ptr.getNode())
5010 // If all the uses are load / store addresses, then don't do the
5012 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
5013 bool RealUse = false;
5014 for (SDNode::use_iterator III = Use->use_begin(),
5015 EEE = Use->use_end(); III != EEE; ++III) {
5016 SDNode *UseUse = *III;
5017 if (!((UseUse->getOpcode() == ISD::LOAD &&
5018 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) ||
5019 (UseUse->getOpcode() == ISD::STORE &&
5020 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use)))
5035 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
5036 SDValue Result = isLoad
5037 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
5038 BasePtr, Offset, AM)
5039 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
5040 BasePtr, Offset, AM);
5043 DEBUG(dbgs() << "\nReplacing.5 ";
5045 dbgs() << "\nWith: ";
5046 Result.getNode()->dump(&DAG);
5048 WorkListRemover DeadNodes(*this);
5050 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
5052 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
5055 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
5059 // Finally, since the node is now dead, remove it from the graph.
5062 // Replace the uses of Use with uses of the updated base value.
5063 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
5064 Result.getValue(isLoad ? 1 : 0),
5066 removeFromWorkList(Op);
5076 SDValue DAGCombiner::visitLOAD(SDNode *N) {
5077 LoadSDNode *LD = cast<LoadSDNode>(N);
5078 SDValue Chain = LD->getChain();
5079 SDValue Ptr = LD->getBasePtr();
5081 // If load is not volatile and there are no uses of the loaded value (and
5082 // the updated indexed value in case of indexed loads), change uses of the
5083 // chain value into uses of the chain input (i.e. delete the dead load).
5084 if (!LD->isVolatile()) {
5085 if (N->getValueType(1) == MVT::Other) {
5087 if (N->hasNUsesOfValue(0, 0)) {
5088 // It's not safe to use the two value CombineTo variant here. e.g.
5089 // v1, chain2 = load chain1, loc
5090 // v2, chain3 = load chain2, loc
5092 // Now we replace use of chain2 with chain1. This makes the second load
5093 // isomorphic to the one we are deleting, and thus makes this load live.
5094 DEBUG(dbgs() << "\nReplacing.6 ";
5096 dbgs() << "\nWith chain: ";
5097 Chain.getNode()->dump(&DAG);
5099 WorkListRemover DeadNodes(*this);
5100 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
5102 if (N->use_empty()) {
5103 removeFromWorkList(N);
5107 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5111 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
5112 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
5113 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
5114 DEBUG(dbgs() << "\nReplacing.7 ";
5116 dbgs() << "\nWith: ";
5117 Undef.getNode()->dump(&DAG);
5118 dbgs() << " and 2 other values\n");
5119 WorkListRemover DeadNodes(*this);
5120 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
5121 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
5122 DAG.getUNDEF(N->getValueType(1)),
5124 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
5125 removeFromWorkList(N);
5127 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5132 // If this load is directly stored, replace the load value with the stored
5134 // TODO: Handle store large -> read small portion.
5135 // TODO: Handle TRUNCSTORE/LOADEXT
5136 if (LD->getExtensionType() == ISD::NON_EXTLOAD &&
5137 !LD->isVolatile()) {
5138 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
5139 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
5140 if (PrevST->getBasePtr() == Ptr &&
5141 PrevST->getValue().getValueType() == N->getValueType(0))
5142 return CombineTo(N, Chain.getOperand(1), Chain);
5146 // Try to infer better alignment information than the load already has.
5147 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
5148 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
5149 if (Align > LD->getAlignment())
5150 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
5151 LD->getValueType(0),
5152 Chain, Ptr, LD->getSrcValue(),
5153 LD->getSrcValueOffset(), LD->getMemoryVT(),
5154 LD->isVolatile(), LD->isNonTemporal(), Align);
5159 // Walk up chain skipping non-aliasing memory nodes.
5160 SDValue BetterChain = FindBetterChain(N, Chain);
5162 // If there is a better chain.
5163 if (Chain != BetterChain) {
5166 // Replace the chain to void dependency.
5167 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
5168 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
5170 LD->getSrcValue(), LD->getSrcValueOffset(),
5171 LD->isVolatile(), LD->isNonTemporal(),
5172 LD->getAlignment());
5174 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
5175 LD->getValueType(0),
5176 BetterChain, Ptr, LD->getSrcValue(),
5177 LD->getSrcValueOffset(),
5180 LD->isNonTemporal(),
5181 LD->getAlignment());
5184 // Create token factor to keep old chain connected.
5185 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
5186 MVT::Other, Chain, ReplLoad.getValue(1));
5188 // Make sure the new and old chains are cleaned up.
5189 AddToWorkList(Token.getNode());
5191 // Replace uses with load result and token factor. Don't add users
5193 return CombineTo(N, ReplLoad.getValue(0), Token, false);
5197 // Try transforming N to an indexed load.
5198 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
5199 return SDValue(N, 0);
5204 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
5205 /// load is having specific bytes cleared out. If so, return the byte size
5206 /// being masked out and the shift amount.
5207 static std::pair<unsigned, unsigned>
5208 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
5209 std::pair<unsigned, unsigned> Result(0, 0);
5211 // Check for the structure we're looking for.
5212 if (V->getOpcode() != ISD::AND ||
5213 !isa<ConstantSDNode>(V->getOperand(1)) ||
5214 !ISD::isNormalLoad(V->getOperand(0).getNode()))
5217 // Check the chain and pointer.
5218 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
5219 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
5221 // The store should be chained directly to the load or be an operand of a
5223 if (LD == Chain.getNode())
5225 else if (Chain->getOpcode() != ISD::TokenFactor)
5226 return Result; // Fail.
5229 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
5230 if (Chain->getOperand(i).getNode() == LD) {
5234 if (!isOk) return Result;
5237 // This only handles simple types.
5238 if (V.getValueType() != MVT::i16 &&
5239 V.getValueType() != MVT::i32 &&
5240 V.getValueType() != MVT::i64)
5243 // Check the constant mask. Invert it so that the bits being masked out are
5244 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
5245 // follow the sign bit for uniformity.
5246 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
5247 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask);
5248 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
5249 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask);
5250 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
5251 if (NotMaskLZ == 64) return Result; // All zero mask.
5253 // See if we have a continuous run of bits. If so, we have 0*1+0*
5254 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
5257 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
5258 if (V.getValueType() != MVT::i64 && NotMaskLZ)
5259 NotMaskLZ -= 64-V.getValueSizeInBits();
5261 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
5262 switch (MaskedBytes) {
5266 default: return Result; // All one mask, or 5-byte mask.
5269 // Verify that the first bit starts at a multiple of mask so that the access
5270 // is aligned the same as the access width.
5271 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
5273 Result.first = MaskedBytes;
5274 Result.second = NotMaskTZ/8;
5279 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
5280 /// provides a value as specified by MaskInfo. If so, replace the specified
5281 /// store with a narrower store of truncated IVal.
5283 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
5284 SDValue IVal, StoreSDNode *St,
5286 unsigned NumBytes = MaskInfo.first;
5287 unsigned ByteShift = MaskInfo.second;
5288 SelectionDAG &DAG = DC->getDAG();
5290 // Check to see if IVal is all zeros in the part being masked in by the 'or'
5291 // that uses this. If not, this is not a replacement.
5292 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
5293 ByteShift*8, (ByteShift+NumBytes)*8);
5294 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
5296 // Check that it is legal on the target to do this. It is legal if the new
5297 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
5299 MVT VT = MVT::getIntegerVT(NumBytes*8);
5300 if (!DC->isTypeLegal(VT))
5303 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
5304 // shifted by ByteShift and truncated down to NumBytes.
5306 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
5307 DAG.getConstant(ByteShift*8, DC->getShiftAmountTy()));
5309 // Figure out the offset for the store and the alignment of the access.
5311 unsigned NewAlign = St->getAlignment();
5313 if (DAG.getTargetLoweringInfo().isLittleEndian())
5314 StOffset = ByteShift;
5316 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
5318 SDValue Ptr = St->getBasePtr();
5320 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
5321 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
5322 NewAlign = MinAlign(NewAlign, StOffset);
5325 // Truncate down to the new size.
5326 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
5329 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr,
5330 St->getSrcValue(), St->getSrcValueOffset()+StOffset,
5331 false, false, NewAlign).getNode();
5335 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
5336 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
5337 /// of the loaded bits, try narrowing the load and store if it would end up
5338 /// being a win for performance or code size.
5339 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
5340 StoreSDNode *ST = cast<StoreSDNode>(N);
5341 if (ST->isVolatile())
5344 SDValue Chain = ST->getChain();
5345 SDValue Value = ST->getValue();
5346 SDValue Ptr = ST->getBasePtr();
5347 EVT VT = Value.getValueType();
5349 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
5352 unsigned Opc = Value.getOpcode();
5354 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
5355 // is a byte mask indicating a consecutive number of bytes, check to see if
5356 // Y is known to provide just those bytes. If so, we try to replace the
5357 // load + replace + store sequence with a single (narrower) store, which makes
5359 if (Opc == ISD::OR) {
5360 std::pair<unsigned, unsigned> MaskedLoad;
5361 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
5362 if (MaskedLoad.first)
5363 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
5364 Value.getOperand(1), ST,this))
5365 return SDValue(NewST, 0);
5367 // Or is commutative, so try swapping X and Y.
5368 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
5369 if (MaskedLoad.first)
5370 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
5371 Value.getOperand(0), ST,this))
5372 return SDValue(NewST, 0);
5375 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
5376 Value.getOperand(1).getOpcode() != ISD::Constant)
5379 SDValue N0 = Value.getOperand(0);
5380 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) {
5381 LoadSDNode *LD = cast<LoadSDNode>(N0);
5382 if (LD->getBasePtr() != Ptr)
5385 // Find the type to narrow it the load / op / store to.
5386 SDValue N1 = Value.getOperand(1);
5387 unsigned BitWidth = N1.getValueSizeInBits();
5388 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
5389 if (Opc == ISD::AND)
5390 Imm ^= APInt::getAllOnesValue(BitWidth);
5391 if (Imm == 0 || Imm.isAllOnesValue())
5393 unsigned ShAmt = Imm.countTrailingZeros();
5394 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
5395 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
5396 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
5397 while (NewBW < BitWidth &&
5398 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
5399 TLI.isNarrowingProfitable(VT, NewVT))) {
5400 NewBW = NextPowerOf2(NewBW);
5401 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
5403 if (NewBW >= BitWidth)
5406 // If the lsb changed does not start at the type bitwidth boundary,
5407 // start at the previous one.
5409 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
5410 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
5411 if ((Imm & Mask) == Imm) {
5412 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
5413 if (Opc == ISD::AND)
5414 NewImm ^= APInt::getAllOnesValue(NewBW);
5415 uint64_t PtrOff = ShAmt / 8;
5416 // For big endian targets, we need to adjust the offset to the pointer to
5417 // load the correct bytes.
5418 if (TLI.isBigEndian())
5419 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
5421 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
5422 const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
5423 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy))
5426 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
5427 Ptr.getValueType(), Ptr,
5428 DAG.getConstant(PtrOff, Ptr.getValueType()));
5429 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
5430 LD->getChain(), NewPtr,
5431 LD->getSrcValue(), LD->getSrcValueOffset(),
5432 LD->isVolatile(), LD->isNonTemporal(),
5434 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
5435 DAG.getConstant(NewImm, NewVT));
5436 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
5438 ST->getSrcValue(), ST->getSrcValueOffset(),
5439 false, false, NewAlign);
5441 AddToWorkList(NewPtr.getNode());
5442 AddToWorkList(NewLD.getNode());
5443 AddToWorkList(NewVal.getNode());
5444 WorkListRemover DeadNodes(*this);
5445 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1),
5455 SDValue DAGCombiner::visitSTORE(SDNode *N) {
5456 StoreSDNode *ST = cast<StoreSDNode>(N);
5457 SDValue Chain = ST->getChain();
5458 SDValue Value = ST->getValue();
5459 SDValue Ptr = ST->getBasePtr();
5461 // If this is a store of a bit convert, store the input value if the
5462 // resultant store does not need a higher alignment than the original.
5463 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
5464 ST->isUnindexed()) {
5465 unsigned OrigAlign = ST->getAlignment();
5466 EVT SVT = Value.getOperand(0).getValueType();
5467 unsigned Align = TLI.getTargetData()->
5468 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
5469 if (Align <= OrigAlign &&
5470 ((!LegalOperations && !ST->isVolatile()) ||
5471 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
5472 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
5473 Ptr, ST->getSrcValue(),
5474 ST->getSrcValueOffset(), ST->isVolatile(),
5475 ST->isNonTemporal(), OrigAlign);
5478 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
5479 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
5480 // NOTE: If the original store is volatile, this transform must not increase
5481 // the number of stores. For example, on x86-32 an f64 can be stored in one
5482 // processor operation but an i64 (which is not legal) requires two. So the
5483 // transform should not be done in this case.
5484 if (Value.getOpcode() != ISD::TargetConstantFP) {
5486 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
5487 default: llvm_unreachable("Unknown FP type");
5488 case MVT::f80: // We don't do this for these yet.
5493 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
5494 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
5495 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
5496 bitcastToAPInt().getZExtValue(), MVT::i32);
5497 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
5498 Ptr, ST->getSrcValue(),
5499 ST->getSrcValueOffset(), ST->isVolatile(),
5500 ST->isNonTemporal(), ST->getAlignment());
5504 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
5505 !ST->isVolatile()) ||
5506 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
5507 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
5508 getZExtValue(), MVT::i64);
5509 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
5510 Ptr, ST->getSrcValue(),
5511 ST->getSrcValueOffset(), ST->isVolatile(),
5512 ST->isNonTemporal(), ST->getAlignment());
5513 } else if (!ST->isVolatile() &&
5514 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
5515 // Many FP stores are not made apparent until after legalize, e.g. for
5516 // argument passing. Since this is so common, custom legalize the
5517 // 64-bit integer store into two 32-bit stores.
5518 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
5519 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
5520 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
5521 if (TLI.isBigEndian()) std::swap(Lo, Hi);
5523 int SVOffset = ST->getSrcValueOffset();
5524 unsigned Alignment = ST->getAlignment();
5525 bool isVolatile = ST->isVolatile();
5526 bool isNonTemporal = ST->isNonTemporal();
5528 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
5529 Ptr, ST->getSrcValue(),
5530 ST->getSrcValueOffset(),
5531 isVolatile, isNonTemporal,
5532 ST->getAlignment());
5533 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
5534 DAG.getConstant(4, Ptr.getValueType()));
5536 Alignment = MinAlign(Alignment, 4U);
5537 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
5538 Ptr, ST->getSrcValue(),
5539 SVOffset, isVolatile, isNonTemporal,
5541 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
5550 // Try to infer better alignment information than the store already has.
5551 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
5552 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
5553 if (Align > ST->getAlignment())
5554 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
5555 Ptr, ST->getSrcValue(),
5556 ST->getSrcValueOffset(), ST->getMemoryVT(),
5557 ST->isVolatile(), ST->isNonTemporal(), Align);
5562 // Walk up chain skipping non-aliasing memory nodes.
5563 SDValue BetterChain = FindBetterChain(N, Chain);
5565 // If there is a better chain.
5566 if (Chain != BetterChain) {
5569 // Replace the chain to avoid dependency.
5570 if (ST->isTruncatingStore()) {
5571 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
5572 ST->getSrcValue(),ST->getSrcValueOffset(),
5573 ST->getMemoryVT(), ST->isVolatile(),
5574 ST->isNonTemporal(), ST->getAlignment());
5576 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
5577 ST->getSrcValue(), ST->getSrcValueOffset(),
5578 ST->isVolatile(), ST->isNonTemporal(),
5579 ST->getAlignment());
5582 // Create token to keep both nodes around.
5583 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
5584 MVT::Other, Chain, ReplStore);
5586 // Make sure the new and old chains are cleaned up.
5587 AddToWorkList(Token.getNode());
5589 // Don't add users to work list.
5590 return CombineTo(N, Token, false);
5594 // Try transforming N to an indexed store.
5595 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
5596 return SDValue(N, 0);
5598 // FIXME: is there such a thing as a truncating indexed store?
5599 if (ST->isTruncatingStore() && ST->isUnindexed() &&
5600 Value.getValueType().isInteger()) {
5601 // See if we can simplify the input to this truncstore with knowledge that
5602 // only the low bits are being used. For example:
5603 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
5605 GetDemandedBits(Value,
5606 APInt::getLowBitsSet(Value.getValueSizeInBits(),
5607 ST->getMemoryVT().getSizeInBits()));
5608 AddToWorkList(Value.getNode());
5609 if (Shorter.getNode())
5610 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
5611 Ptr, ST->getSrcValue(),
5612 ST->getSrcValueOffset(), ST->getMemoryVT(),
5613 ST->isVolatile(), ST->isNonTemporal(),
5614 ST->getAlignment());
5616 // Otherwise, see if we can simplify the operation with
5617 // SimplifyDemandedBits, which only works if the value has a single use.
5618 if (SimplifyDemandedBits(Value,
5619 APInt::getLowBitsSet(
5620 Value.getValueType().getScalarType().getSizeInBits(),
5621 ST->getMemoryVT().getScalarType().getSizeInBits())))
5622 return SDValue(N, 0);
5625 // If this is a load followed by a store to the same location, then the store
5627 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
5628 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
5629 ST->isUnindexed() && !ST->isVolatile() &&
5630 // There can't be any side effects between the load and store, such as
5632 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
5633 // The store is dead, remove it.
5638 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
5639 // truncating store. We can do this even if this is already a truncstore.
5640 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
5641 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
5642 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
5643 ST->getMemoryVT())) {
5644 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
5645 Ptr, ST->getSrcValue(),
5646 ST->getSrcValueOffset(), ST->getMemoryVT(),
5647 ST->isVolatile(), ST->isNonTemporal(),
5648 ST->getAlignment());
5651 return ReduceLoadOpStoreWidth(N);
5654 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
5655 SDValue InVec = N->getOperand(0);
5656 SDValue InVal = N->getOperand(1);
5657 SDValue EltNo = N->getOperand(2);
5659 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
5660 // vector with the inserted element.
5661 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
5662 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5663 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
5664 InVec.getNode()->op_end());
5665 if (Elt < Ops.size())
5667 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5668 InVec.getValueType(), &Ops[0], Ops.size());
5670 // If the invec is an UNDEF and if EltNo is a constant, create a new
5671 // BUILD_VECTOR with undef elements and the inserted element.
5672 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF &&
5673 isa<ConstantSDNode>(EltNo)) {
5674 EVT VT = InVec.getValueType();
5675 EVT EltVT = VT.getVectorElementType();
5676 unsigned NElts = VT.getVectorNumElements();
5677 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT));
5679 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5680 if (Elt < Ops.size())
5682 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5683 InVec.getValueType(), &Ops[0], Ops.size());
5688 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
5689 // (vextract (scalar_to_vector val, 0) -> val
5690 SDValue InVec = N->getOperand(0);
5692 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5693 // Check if the result type doesn't match the inserted element type. A
5694 // SCALAR_TO_VECTOR may truncate the inserted element and the
5695 // EXTRACT_VECTOR_ELT may widen the extracted vector.
5696 EVT EltVT = InVec.getValueType().getVectorElementType();
5697 SDValue InOp = InVec.getOperand(0);
5698 EVT NVT = N->getValueType(0);
5699 if (InOp.getValueType() != NVT) {
5700 assert(InOp.getValueType().isInteger() && NVT.isInteger());
5701 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
5706 // Perform only after legalization to ensure build_vector / vector_shuffle
5707 // optimizations have already been done.
5708 if (!LegalOperations) return SDValue();
5710 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
5711 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
5712 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
5713 SDValue EltNo = N->getOperand(1);
5715 if (isa<ConstantSDNode>(EltNo)) {
5716 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5717 bool NewLoad = false;
5718 bool BCNumEltsChanged = false;
5719 EVT VT = InVec.getValueType();
5720 EVT ExtVT = VT.getVectorElementType();
5723 if (InVec.getOpcode() == ISD::BIT_CONVERT) {
5724 EVT BCVT = InVec.getOperand(0).getValueType();
5725 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
5727 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
5728 BCNumEltsChanged = true;
5729 InVec = InVec.getOperand(0);
5730 ExtVT = BCVT.getVectorElementType();
5734 LoadSDNode *LN0 = NULL;
5735 const ShuffleVectorSDNode *SVN = NULL;
5736 if (ISD::isNormalLoad(InVec.getNode())) {
5737 LN0 = cast<LoadSDNode>(InVec);
5738 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5739 InVec.getOperand(0).getValueType() == ExtVT &&
5740 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
5741 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
5742 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
5743 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
5745 // (load $addr+1*size)
5747 // If the bit convert changed the number of elements, it is unsafe
5748 // to examine the mask.
5749 if (BCNumEltsChanged)
5752 // Select the input vector, guarding against out of range extract vector.
5753 unsigned NumElems = VT.getVectorNumElements();
5754 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt);
5755 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
5757 if (InVec.getOpcode() == ISD::BIT_CONVERT)
5758 InVec = InVec.getOperand(0);
5759 if (ISD::isNormalLoad(InVec.getNode())) {
5760 LN0 = cast<LoadSDNode>(InVec);
5761 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
5765 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile())
5768 unsigned Align = LN0->getAlignment();
5770 // Check the resultant load doesn't need a higher alignment than the
5773 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
5775 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
5781 SDValue NewPtr = LN0->getBasePtr();
5783 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8;
5784 EVT PtrType = NewPtr.getValueType();
5785 if (TLI.isBigEndian())
5786 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
5787 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
5788 DAG.getConstant(PtrOff, PtrType));
5791 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
5792 LN0->getSrcValue(), LN0->getSrcValueOffset(),
5793 LN0->isVolatile(), LN0->isNonTemporal(), Align);
5799 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
5800 unsigned NumInScalars = N->getNumOperands();
5801 EVT VT = N->getValueType(0);
5803 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
5804 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
5805 // at most two distinct vectors, turn this into a shuffle node.
5806 SDValue VecIn1, VecIn2;
5807 for (unsigned i = 0; i != NumInScalars; ++i) {
5808 // Ignore undef inputs.
5809 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5811 // If this input is something other than a EXTRACT_VECTOR_ELT with a
5812 // constant index, bail out.
5813 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5814 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
5815 VecIn1 = VecIn2 = SDValue(0, 0);
5819 // If the input vector type disagrees with the result of the build_vector,
5820 // we can't make a shuffle.
5821 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
5822 if (ExtractedFromVec.getValueType() != VT) {
5823 VecIn1 = VecIn2 = SDValue(0, 0);
5827 // Otherwise, remember this. We allow up to two distinct input vectors.
5828 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
5831 if (VecIn1.getNode() == 0) {
5832 VecIn1 = ExtractedFromVec;
5833 } else if (VecIn2.getNode() == 0) {
5834 VecIn2 = ExtractedFromVec;
5837 VecIn1 = VecIn2 = SDValue(0, 0);
5842 // If everything is good, we can make a shuffle operation.
5843 if (VecIn1.getNode()) {
5844 SmallVector<int, 8> Mask;
5845 for (unsigned i = 0; i != NumInScalars; ++i) {
5846 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
5851 // If extracting from the first vector, just use the index directly.
5852 SDValue Extract = N->getOperand(i);
5853 SDValue ExtVal = Extract.getOperand(1);
5854 if (Extract.getOperand(0) == VecIn1) {
5855 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
5856 if (ExtIndex > VT.getVectorNumElements())
5859 Mask.push_back(ExtIndex);
5863 // Otherwise, use InIdx + VecSize
5864 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
5865 Mask.push_back(Idx+NumInScalars);
5868 // Add count and size info.
5869 if (!isTypeLegal(VT))
5872 // Return the new VECTOR_SHUFFLE node.
5875 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5876 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
5882 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
5883 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
5884 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
5885 // inputs come from at most two distinct vectors, turn this into a shuffle
5888 // If we only have one input vector, we don't need to do any concatenation.
5889 if (N->getNumOperands() == 1)
5890 return N->getOperand(0);
5895 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
5898 EVT VT = N->getValueType(0);
5899 unsigned NumElts = VT.getVectorNumElements();
5901 SDValue N0 = N->getOperand(0);
5903 assert(N0.getValueType().getVectorNumElements() == NumElts &&
5904 "Vector shuffle must be normalized in DAG");
5906 // FIXME: implement canonicalizations from DAG.getVectorShuffle()
5908 // If it is a splat, check if the argument vector is a build_vector with
5909 // all scalar elements the same.
5910 if (cast<ShuffleVectorSDNode>(N)->isSplat()) {
5911 SDNode *V = N0.getNode();
5914 // If this is a bit convert that changes the element type of the vector but
5915 // not the number of vector elements, look through it. Be careful not to
5916 // look though conversions that change things like v4f32 to v2f64.
5917 if (V->getOpcode() == ISD::BIT_CONVERT) {
5918 SDValue ConvInput = V->getOperand(0);
5919 if (ConvInput.getValueType().isVector() &&
5920 ConvInput.getValueType().getVectorNumElements() == NumElts)
5921 V = ConvInput.getNode();
5924 if (V->getOpcode() == ISD::BUILD_VECTOR) {
5925 unsigned NumElems = V->getNumOperands();
5926 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex();
5927 if (NumElems > BaseIdx) {
5929 bool AllSame = true;
5930 for (unsigned i = 0; i != NumElems; ++i) {
5931 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
5932 Base = V->getOperand(i);
5936 // Splat of <u, u, u, u>, return <u, u, u, u>
5937 if (!Base.getNode())
5939 for (unsigned i = 0; i != NumElems; ++i) {
5940 if (V->getOperand(i) != Base) {
5945 // Splat of <x, x, x, x>, return <x, x, x, x>
5954 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
5955 /// an AND to a vector_shuffle with the destination vector and a zero vector.
5956 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
5957 /// vector_shuffle V, Zero, <0, 4, 2, 4>
5958 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
5959 EVT VT = N->getValueType(0);
5960 DebugLoc dl = N->getDebugLoc();
5961 SDValue LHS = N->getOperand(0);
5962 SDValue RHS = N->getOperand(1);
5963 if (N->getOpcode() == ISD::AND) {
5964 if (RHS.getOpcode() == ISD::BIT_CONVERT)
5965 RHS = RHS.getOperand(0);
5966 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
5967 SmallVector<int, 8> Indices;
5968 unsigned NumElts = RHS.getNumOperands();
5969 for (unsigned i = 0; i != NumElts; ++i) {
5970 SDValue Elt = RHS.getOperand(i);
5971 if (!isa<ConstantSDNode>(Elt))
5973 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
5974 Indices.push_back(i);
5975 else if (cast<ConstantSDNode>(Elt)->isNullValue())
5976 Indices.push_back(NumElts);
5981 // Let's see if the target supports this vector_shuffle.
5982 EVT RVT = RHS.getValueType();
5983 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
5986 // Return the new VECTOR_SHUFFLE node.
5987 EVT EltVT = RVT.getVectorElementType();
5988 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
5989 DAG.getConstant(0, EltVT));
5990 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5991 RVT, &ZeroOps[0], ZeroOps.size());
5992 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS);
5993 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
5994 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf);
6001 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
6002 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
6003 // After legalize, the target may be depending on adds and other
6004 // binary ops to provide legal ways to construct constants or other
6005 // things. Simplifying them may result in a loss of legality.
6006 if (LegalOperations) return SDValue();
6008 EVT VT = N->getValueType(0);
6009 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!");
6011 EVT EltType = VT.getVectorElementType();
6012 SDValue LHS = N->getOperand(0);
6013 SDValue RHS = N->getOperand(1);
6014 SDValue Shuffle = XformToShuffleWithZero(N);
6015 if (Shuffle.getNode()) return Shuffle;
6017 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
6019 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
6020 RHS.getOpcode() == ISD::BUILD_VECTOR) {
6021 SmallVector<SDValue, 8> Ops;
6022 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
6023 SDValue LHSOp = LHS.getOperand(i);
6024 SDValue RHSOp = RHS.getOperand(i);
6025 // If these two elements can't be folded, bail out.
6026 if ((LHSOp.getOpcode() != ISD::UNDEF &&
6027 LHSOp.getOpcode() != ISD::Constant &&
6028 LHSOp.getOpcode() != ISD::ConstantFP) ||
6029 (RHSOp.getOpcode() != ISD::UNDEF &&
6030 RHSOp.getOpcode() != ISD::Constant &&
6031 RHSOp.getOpcode() != ISD::ConstantFP))
6034 // Can't fold divide by zero.
6035 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
6036 N->getOpcode() == ISD::FDIV) {
6037 if ((RHSOp.getOpcode() == ISD::Constant &&
6038 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
6039 (RHSOp.getOpcode() == ISD::ConstantFP &&
6040 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
6044 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(),
6045 EltType, LHSOp, RHSOp));
6046 AddToWorkList(Ops.back().getNode());
6047 assert((Ops.back().getOpcode() == ISD::UNDEF ||
6048 Ops.back().getOpcode() == ISD::Constant ||
6049 Ops.back().getOpcode() == ISD::ConstantFP) &&
6050 "Scalar binop didn't fold!");
6053 if (Ops.size() == LHS.getNumOperands()) {
6054 EVT VT = LHS.getValueType();
6055 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
6056 &Ops[0], Ops.size());
6063 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
6064 SDValue N1, SDValue N2){
6065 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
6067 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
6068 cast<CondCodeSDNode>(N0.getOperand(2))->get());
6070 // If we got a simplified select_cc node back from SimplifySelectCC, then
6071 // break it down into a new SETCC node, and a new SELECT node, and then return
6072 // the SELECT node, since we were called with a SELECT node.
6073 if (SCC.getNode()) {
6074 // Check to see if we got a select_cc back (to turn into setcc/select).
6075 // Otherwise, just return whatever node we got back, like fabs.
6076 if (SCC.getOpcode() == ISD::SELECT_CC) {
6077 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
6079 SCC.getOperand(0), SCC.getOperand(1),
6081 AddToWorkList(SETCC.getNode());
6082 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
6083 SCC.getOperand(2), SCC.getOperand(3), SETCC);
6091 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
6092 /// are the two values being selected between, see if we can simplify the
6093 /// select. Callers of this should assume that TheSelect is deleted if this
6094 /// returns true. As such, they should return the appropriate thing (e.g. the
6095 /// node) back to the top-level of the DAG combiner loop to avoid it being
6097 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
6100 // If this is a select from two identical things, try to pull the operation
6101 // through the select.
6102 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
6103 // If this is a load and the token chain is identical, replace the select
6104 // of two loads with a load through a select of the address to load from.
6105 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
6106 // constants have been dropped into the constant pool.
6107 if (LHS.getOpcode() == ISD::LOAD &&
6108 // Do not let this transformation reduce the number of volatile loads.
6109 !cast<LoadSDNode>(LHS)->isVolatile() &&
6110 !cast<LoadSDNode>(RHS)->isVolatile() &&
6111 // Token chains must be identical.
6112 LHS.getOperand(0) == RHS.getOperand(0)) {
6113 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
6114 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
6116 // If this is an EXTLOAD, the VT's must match.
6117 if (LLD->getMemoryVT() == RLD->getMemoryVT()) {
6118 // FIXME: this discards src value information. This is
6119 // over-conservative. It would be beneficial to be able to remember
6120 // both potential memory locations. Since we are discarding
6121 // src value info, don't do the transformation if the memory
6122 // locations are not in the default address space.
6123 unsigned LLDAddrSpace = 0, RLDAddrSpace = 0;
6124 if (const Value *LLDVal = LLD->getMemOperand()->getValue()) {
6125 if (const PointerType *PT = dyn_cast<PointerType>(LLDVal->getType()))
6126 LLDAddrSpace = PT->getAddressSpace();
6128 if (const Value *RLDVal = RLD->getMemOperand()->getValue()) {
6129 if (const PointerType *PT = dyn_cast<PointerType>(RLDVal->getType()))
6130 RLDAddrSpace = PT->getAddressSpace();
6133 if (LLDAddrSpace == 0 && RLDAddrSpace == 0) {
6134 if (TheSelect->getOpcode() == ISD::SELECT) {
6135 // Check that the condition doesn't reach either load. If so, folding
6136 // this will induce a cycle into the DAG.
6137 if ((!LLD->hasAnyUseOfValue(1) ||
6138 !LLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) &&
6139 (!RLD->hasAnyUseOfValue(1) ||
6140 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()))) {
6141 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
6142 LLD->getBasePtr().getValueType(),
6143 TheSelect->getOperand(0), LLD->getBasePtr(),
6147 // Check that the condition doesn't reach either load. If so, folding
6148 // this will induce a cycle into the DAG.
6149 if ((!LLD->hasAnyUseOfValue(1) ||
6150 (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
6151 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()))) &&
6152 (!RLD->hasAnyUseOfValue(1) ||
6153 (!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
6154 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())))) {
6155 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
6156 LLD->getBasePtr().getValueType(),
6157 TheSelect->getOperand(0),
6158 TheSelect->getOperand(1),
6159 LLD->getBasePtr(), RLD->getBasePtr(),
6160 TheSelect->getOperand(4));
6165 if (Addr.getNode()) {
6167 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
6168 Load = DAG.getLoad(TheSelect->getValueType(0),
6169 TheSelect->getDebugLoc(),
6173 LLD->isNonTemporal(),
6174 LLD->getAlignment());
6176 Load = DAG.getExtLoad(LLD->getExtensionType(),
6177 TheSelect->getDebugLoc(),
6178 TheSelect->getValueType(0),
6179 LLD->getChain(), Addr, 0, 0,
6182 LLD->isNonTemporal(),
6183 LLD->getAlignment());
6186 // Users of the select now use the result of the load.
6187 CombineTo(TheSelect, Load);
6189 // Users of the old loads now use the new load's chain. We know the
6190 // old-load value is dead now.
6191 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
6192 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
6202 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
6203 /// where 'cond' is the comparison specified by CC.
6204 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
6205 SDValue N2, SDValue N3,
6206 ISD::CondCode CC, bool NotExtCompare) {
6207 // (x ? y : y) -> y.
6208 if (N2 == N3) return N2;
6210 EVT VT = N2.getValueType();
6211 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
6212 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
6213 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
6215 // Determine if the condition we're dealing with is constant
6216 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
6217 N0, N1, CC, DL, false);
6218 if (SCC.getNode()) AddToWorkList(SCC.getNode());
6219 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
6221 // fold select_cc true, x, y -> x
6222 if (SCCC && !SCCC->isNullValue())
6224 // fold select_cc false, x, y -> y
6225 if (SCCC && SCCC->isNullValue())
6228 // Check to see if we can simplify the select into an fabs node
6229 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
6230 // Allow either -0.0 or 0.0
6231 if (CFP->getValueAPF().isZero()) {
6232 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
6233 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
6234 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
6235 N2 == N3.getOperand(0))
6236 return DAG.getNode(ISD::FABS, DL, VT, N0);
6238 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
6239 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
6240 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
6241 N2.getOperand(0) == N3)
6242 return DAG.getNode(ISD::FABS, DL, VT, N3);
6246 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
6247 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
6248 // in it. This is a win when the constant is not otherwise available because
6249 // it replaces two constant pool loads with one. We only do this if the FP
6250 // type is known to be legal, because if it isn't, then we are before legalize
6251 // types an we want the other legalization to happen first (e.g. to avoid
6252 // messing with soft float) and if the ConstantFP is not legal, because if
6253 // it is legal, we may not need to store the FP constant in a constant pool.
6254 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
6255 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
6256 if (TLI.isTypeLegal(N2.getValueType()) &&
6257 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
6258 TargetLowering::Legal) &&
6259 // If both constants have multiple uses, then we won't need to do an
6260 // extra load, they are likely around in registers for other users.
6261 (TV->hasOneUse() || FV->hasOneUse())) {
6262 Constant *Elts[] = {
6263 const_cast<ConstantFP*>(FV->getConstantFPValue()),
6264 const_cast<ConstantFP*>(TV->getConstantFPValue())
6266 const Type *FPTy = Elts[0]->getType();
6267 const TargetData &TD = *TLI.getTargetData();
6269 // Create a ConstantArray of the two constants.
6270 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2);
6271 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
6272 TD.getPrefTypeAlignment(FPTy));
6273 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6275 // Get the offsets to the 0 and 1 element of the array so that we can
6276 // select between them.
6277 SDValue Zero = DAG.getIntPtrConstant(0);
6278 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
6279 SDValue One = DAG.getIntPtrConstant(EltSize);
6281 SDValue Cond = DAG.getSetCC(DL,
6282 TLI.getSetCCResultType(N0.getValueType()),
6284 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
6286 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
6288 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
6289 PseudoSourceValue::getConstantPool(), 0, false,
6295 // Check to see if we can perform the "gzip trick", transforming
6296 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
6297 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
6298 N0.getValueType().isInteger() &&
6299 N2.getValueType().isInteger() &&
6300 (N1C->isNullValue() || // (a < 0) ? b : 0
6301 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
6302 EVT XType = N0.getValueType();
6303 EVT AType = N2.getValueType();
6304 if (XType.bitsGE(AType)) {
6305 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
6306 // single-bit constant.
6307 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
6308 unsigned ShCtV = N2C->getAPIntValue().logBase2();
6309 ShCtV = XType.getSizeInBits()-ShCtV-1;
6310 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy());
6311 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
6313 AddToWorkList(Shift.getNode());
6315 if (XType.bitsGT(AType)) {
6316 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
6317 AddToWorkList(Shift.getNode());
6320 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
6323 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
6325 DAG.getConstant(XType.getSizeInBits()-1,
6326 getShiftAmountTy()));
6327 AddToWorkList(Shift.getNode());
6329 if (XType.bitsGT(AType)) {
6330 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
6331 AddToWorkList(Shift.getNode());
6334 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
6338 // fold select C, 16, 0 -> shl C, 4
6339 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
6340 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {
6342 // If the caller doesn't want us to simplify this into a zext of a compare,
6344 if (NotExtCompare && N2C->getAPIntValue() == 1)
6347 // Get a SetCC of the condition
6348 // FIXME: Should probably make sure that setcc is legal if we ever have a
6349 // target where it isn't.
6351 // cast from setcc result type to select result type
6353 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
6355 if (N2.getValueType().bitsLT(SCC.getValueType()))
6356 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
6358 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
6359 N2.getValueType(), SCC);
6361 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
6362 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
6363 N2.getValueType(), SCC);
6366 AddToWorkList(SCC.getNode());
6367 AddToWorkList(Temp.getNode());
6369 if (N2C->getAPIntValue() == 1)
6372 // shl setcc result by log2 n2c
6373 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
6374 DAG.getConstant(N2C->getAPIntValue().logBase2(),
6375 getShiftAmountTy()));
6378 // Check to see if this is the equivalent of setcc
6379 // FIXME: Turn all of these into setcc if setcc if setcc is legal
6380 // otherwise, go ahead with the folds.
6381 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
6382 EVT XType = N0.getValueType();
6383 if (!LegalOperations ||
6384 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
6385 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
6386 if (Res.getValueType() != VT)
6387 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
6391 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
6392 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
6393 (!LegalOperations ||
6394 TLI.isOperationLegal(ISD::CTLZ, XType))) {
6395 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
6396 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
6397 DAG.getConstant(Log2_32(XType.getSizeInBits()),
6398 getShiftAmountTy()));
6400 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
6401 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
6402 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
6403 XType, DAG.getConstant(0, XType), N0);
6404 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
6405 return DAG.getNode(ISD::SRL, DL, XType,
6406 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
6407 DAG.getConstant(XType.getSizeInBits()-1,
6408 getShiftAmountTy()));
6410 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
6411 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
6412 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
6413 DAG.getConstant(XType.getSizeInBits()-1,
6414 getShiftAmountTy()));
6415 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
6419 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
6420 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
6421 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
6422 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
6423 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) {
6424 EVT XType = N0.getValueType();
6425 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0,
6426 DAG.getConstant(XType.getSizeInBits()-1,
6427 getShiftAmountTy()));
6428 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType,
6430 AddToWorkList(Shift.getNode());
6431 AddToWorkList(Add.getNode());
6432 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
6434 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
6435 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
6436 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
6437 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
6438 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
6439 EVT XType = N0.getValueType();
6440 if (SubC->isNullValue() && XType.isInteger()) {
6441 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
6443 DAG.getConstant(XType.getSizeInBits()-1,
6444 getShiftAmountTy()));
6445 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
6447 AddToWorkList(Shift.getNode());
6448 AddToWorkList(Add.getNode());
6449 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
6457 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
6458 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
6459 SDValue N1, ISD::CondCode Cond,
6460 DebugLoc DL, bool foldBooleans) {
6461 TargetLowering::DAGCombinerInfo
6462 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
6463 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
6466 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
6467 /// return a DAG expression to select that will generate the same value by
6468 /// multiplying by a magic number. See:
6469 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
6470 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
6471 std::vector<SDNode*> Built;
6472 SDValue S = TLI.BuildSDIV(N, DAG, &Built);
6474 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
6480 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
6481 /// return a DAG expression to select that will generate the same value by
6482 /// multiplying by a magic number. See:
6483 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
6484 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
6485 std::vector<SDNode*> Built;
6486 SDValue S = TLI.BuildUDIV(N, DAG, &Built);
6488 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
6494 /// FindBaseOffset - Return true if base is a frame index, which is known not
6495 // to alias with anything but itself. Provides base object and offset as results.
6496 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
6497 const GlobalValue *&GV, void *&CV) {
6498 // Assume it is a primitive operation.
6499 Base = Ptr; Offset = 0; GV = 0; CV = 0;
6501 // If it's an adding a simple constant then integrate the offset.
6502 if (Base.getOpcode() == ISD::ADD) {
6503 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
6504 Base = Base.getOperand(0);
6505 Offset += C->getZExtValue();
6509 // Return the underlying GlobalValue, and update the Offset. Return false
6510 // for GlobalAddressSDNode since the same GlobalAddress may be represented
6511 // by multiple nodes with different offsets.
6512 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
6513 GV = G->getGlobal();
6514 Offset += G->getOffset();
6518 // Return the underlying Constant value, and update the Offset. Return false
6519 // for ConstantSDNodes since the same constant pool entry may be represented
6520 // by multiple nodes with different offsets.
6521 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
6522 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal()
6523 : (void *)C->getConstVal();
6524 Offset += C->getOffset();
6527 // If it's any of the following then it can't alias with anything but itself.
6528 return isa<FrameIndexSDNode>(Base);
6531 /// isAlias - Return true if there is any possibility that the two addresses
6533 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
6534 const Value *SrcValue1, int SrcValueOffset1,
6535 unsigned SrcValueAlign1,
6536 SDValue Ptr2, int64_t Size2,
6537 const Value *SrcValue2, int SrcValueOffset2,
6538 unsigned SrcValueAlign2) const {
6539 // If they are the same then they must be aliases.
6540 if (Ptr1 == Ptr2) return true;
6542 // Gather base node and offset information.
6543 SDValue Base1, Base2;
6544 int64_t Offset1, Offset2;
6545 const GlobalValue *GV1, *GV2;
6547 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
6548 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
6550 // If they have a same base address then check to see if they overlap.
6551 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
6552 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
6554 // If we know what the bases are, and they aren't identical, then we know they
6556 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
6559 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
6560 // compared to the size and offset of the access, we may be able to prove they
6561 // do not alias. This check is conservative for now to catch cases created by
6562 // splitting vector types.
6563 if ((SrcValueAlign1 == SrcValueAlign2) &&
6564 (SrcValueOffset1 != SrcValueOffset2) &&
6565 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
6566 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
6567 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
6569 // There is no overlap between these relatively aligned accesses of similar
6570 // size, return no alias.
6571 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
6575 if (CombinerGlobalAA) {
6576 // Use alias analysis information.
6577 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
6578 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
6579 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
6580 AliasAnalysis::AliasResult AAResult =
6581 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
6582 if (AAResult == AliasAnalysis::NoAlias)
6586 // Otherwise we have to assume they alias.
6590 /// FindAliasInfo - Extracts the relevant alias information from the memory
6591 /// node. Returns true if the operand was a load.
6592 bool DAGCombiner::FindAliasInfo(SDNode *N,
6593 SDValue &Ptr, int64_t &Size,
6594 const Value *&SrcValue,
6595 int &SrcValueOffset,
6596 unsigned &SrcValueAlign) const {
6597 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6598 Ptr = LD->getBasePtr();
6599 Size = LD->getMemoryVT().getSizeInBits() >> 3;
6600 SrcValue = LD->getSrcValue();
6601 SrcValueOffset = LD->getSrcValueOffset();
6602 SrcValueAlign = LD->getOriginalAlignment();
6604 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6605 Ptr = ST->getBasePtr();
6606 Size = ST->getMemoryVT().getSizeInBits() >> 3;
6607 SrcValue = ST->getSrcValue();
6608 SrcValueOffset = ST->getSrcValueOffset();
6609 SrcValueAlign = ST->getOriginalAlignment();
6611 llvm_unreachable("FindAliasInfo expected a memory operand");
6617 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
6618 /// looking for aliasing nodes and adding them to the Aliases vector.
6619 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
6620 SmallVector<SDValue, 8> &Aliases) {
6621 SmallVector<SDValue, 8> Chains; // List of chains to visit.
6622 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
6624 // Get alias information for node.
6627 const Value *SrcValue;
6629 unsigned SrcValueAlign;
6630 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
6634 Chains.push_back(OriginalChain);
6637 // Look at each chain and determine if it is an alias. If so, add it to the
6638 // aliases list. If not, then continue up the chain looking for the next
6640 while (!Chains.empty()) {
6641 SDValue Chain = Chains.back();
6644 // For TokenFactor nodes, look at each operand and only continue up the
6645 // chain until we find two aliases. If we've seen two aliases, assume we'll
6646 // find more and revert to original chain since the xform is unlikely to be
6649 // FIXME: The depth check could be made to return the last non-aliasing
6650 // chain we found before we hit a tokenfactor rather than the original
6652 if (Depth > 6 || Aliases.size() == 2) {
6654 Aliases.push_back(OriginalChain);
6658 // Don't bother if we've been before.
6659 if (!Visited.insert(Chain.getNode()))
6662 switch (Chain.getOpcode()) {
6663 case ISD::EntryToken:
6664 // Entry token is ideal chain operand, but handled in FindBetterChain.
6669 // Get alias information for Chain.
6672 const Value *OpSrcValue;
6673 int OpSrcValueOffset;
6674 unsigned OpSrcValueAlign;
6675 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
6676 OpSrcValue, OpSrcValueOffset,
6679 // If chain is alias then stop here.
6680 if (!(IsLoad && IsOpLoad) &&
6681 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
6682 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
6684 Aliases.push_back(Chain);
6686 // Look further up the chain.
6687 Chains.push_back(Chain.getOperand(0));
6693 case ISD::TokenFactor:
6694 // We have to check each of the operands of the token factor for "small"
6695 // token factors, so we queue them up. Adding the operands to the queue
6696 // (stack) in reverse order maintains the original order and increases the
6697 // likelihood that getNode will find a matching token factor (CSE.)
6698 if (Chain.getNumOperands() > 16) {
6699 Aliases.push_back(Chain);
6702 for (unsigned n = Chain.getNumOperands(); n;)
6703 Chains.push_back(Chain.getOperand(--n));
6708 // For all other instructions we will just have to take what we can get.
6709 Aliases.push_back(Chain);
6715 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
6716 /// for a better chain (aliasing node.)
6717 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
6718 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
6720 // Accumulate all the aliases to this node.
6721 GatherAllAliases(N, OldChain, Aliases);
6723 if (Aliases.size() == 0) {
6724 // If no operands then chain to entry token.
6725 return DAG.getEntryNode();
6726 } else if (Aliases.size() == 1) {
6727 // If a single operand then chain to it. We don't need to revisit it.
6731 // Construct a custom tailored token factor.
6732 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
6733 &Aliases[0], Aliases.size());
6736 // SelectionDAG::Combine - This is the entry point for the file.
6738 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
6739 CodeGenOpt::Level OptLevel) {
6740 /// run - This is the main entry point to this class.
6742 DAGCombiner(*this, AA, OptLevel).Run(Level);