1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: Should add a corresponding version of fold AND with
20 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which
23 // FIXME: select C, pow2, pow2 -> something smart
24 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
25 // FIXME: Dead stores -> nuke
26 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
27 // FIXME: mul (x, const) -> shifts + adds
28 // FIXME: undef values
29 // FIXME: make truncate see through SIGN_EXTEND and AND
30 // FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2)
31 // FIXME: verify that getNode can't return extends with an operand whose type
32 // is >= to that of the extend.
33 // FIXME: divide by zero is currently left unfolded. do we want to turn this
35 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
37 //===----------------------------------------------------------------------===//
39 #define DEBUG_TYPE "dagcombine"
40 #include "llvm/ADT/Statistic.h"
41 #include "llvm/CodeGen/SelectionDAG.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/MathExtras.h"
44 #include "llvm/Target/TargetLowering.h"
51 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined");
58 // Worklist of all of the nodes that need to be simplified.
59 std::vector<SDNode*> WorkList;
61 /// AddUsersToWorkList - When an instruction is simplified, add all users of
62 /// the instruction to the work lists because they might get more simplified
65 void AddUsersToWorkList(SDNode *N) {
66 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
68 WorkList.push_back(*UI);
71 /// removeFromWorkList - remove all instances of N from the worklist.
72 void removeFromWorkList(SDNode *N) {
73 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
77 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
79 DEBUG(std::cerr << "\nReplacing "; N->dump();
80 std::cerr << "\nWith: "; To[0].Val->dump();
81 std::cerr << " and " << To.size()-1 << " other values\n");
82 std::vector<SDNode*> NowDead;
83 DAG.ReplaceAllUsesWith(N, To, &NowDead);
85 // Push the new nodes and any users onto the worklist
86 for (unsigned i = 0, e = To.size(); i != e; ++i) {
87 WorkList.push_back(To[i].Val);
88 AddUsersToWorkList(To[i].Val);
91 // Nodes can end up on the worklist more than once. Make sure we do
92 // not process a node that has been replaced.
93 removeFromWorkList(N);
94 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
95 removeFromWorkList(NowDead[i]);
97 // Finally, since the node is now dead, remove it from the graph.
99 return SDOperand(N, 0);
102 /// SimplifyDemandedBits - Check the specified integer node value to see if
103 /// it can be simplified or if things is uses can be simplified by bit
104 /// propagation. If so, return true.
105 bool SimplifyDemandedBits(SDOperand Op) {
106 TargetLowering::TargetLoweringOpt TLO(DAG);
107 uint64_t KnownZero, KnownOne;
108 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
109 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
113 WorkList.push_back(Op.Val);
115 // Replace the old value with the new one.
117 DEBUG(std::cerr << "\nReplacing "; TLO.Old.Val->dump();
118 std::cerr << "\nWith: "; TLO.New.Val->dump());
120 std::vector<SDNode*> NowDead;
121 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
123 // Push the new node and any (possibly new) users onto the worklist.
124 WorkList.push_back(TLO.New.Val);
125 AddUsersToWorkList(TLO.New.Val);
127 // Nodes can end up on the worklist more than once. Make sure we do
128 // not process a node that has been replaced.
129 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
130 removeFromWorkList(NowDead[i]);
132 // Finally, if the node is now dead, remove it from the graph. The node
133 // may not be dead if the replacement process recursively simplified to
134 // something else needing this node.
135 if (TLO.Old.Val->use_empty()) {
136 removeFromWorkList(TLO.Old.Val);
137 DAG.DeleteNode(TLO.Old.Val);
142 SDOperand CombineTo(SDNode *N, SDOperand Res) {
143 std::vector<SDOperand> To;
145 return CombineTo(N, To);
148 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
149 std::vector<SDOperand> To;
152 return CombineTo(N, To);
155 /// visit - call the node-specific routine that knows how to fold each
156 /// particular type of node.
157 SDOperand visit(SDNode *N);
159 // Visitation implementation - Implement dag node combining for different
160 // node types. The semantics are as follows:
162 // SDOperand.Val == 0 - No change was made
163 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
164 // otherwise - N should be replaced by the returned Operand.
166 SDOperand visitTokenFactor(SDNode *N);
167 SDOperand visitADD(SDNode *N);
168 SDOperand visitSUB(SDNode *N);
169 SDOperand visitMUL(SDNode *N);
170 SDOperand visitSDIV(SDNode *N);
171 SDOperand visitUDIV(SDNode *N);
172 SDOperand visitSREM(SDNode *N);
173 SDOperand visitUREM(SDNode *N);
174 SDOperand visitMULHU(SDNode *N);
175 SDOperand visitMULHS(SDNode *N);
176 SDOperand visitAND(SDNode *N);
177 SDOperand visitOR(SDNode *N);
178 SDOperand visitXOR(SDNode *N);
179 SDOperand visitSHL(SDNode *N);
180 SDOperand visitSRA(SDNode *N);
181 SDOperand visitSRL(SDNode *N);
182 SDOperand visitCTLZ(SDNode *N);
183 SDOperand visitCTTZ(SDNode *N);
184 SDOperand visitCTPOP(SDNode *N);
185 SDOperand visitSELECT(SDNode *N);
186 SDOperand visitSELECT_CC(SDNode *N);
187 SDOperand visitSETCC(SDNode *N);
188 SDOperand visitSIGN_EXTEND(SDNode *N);
189 SDOperand visitZERO_EXTEND(SDNode *N);
190 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
191 SDOperand visitTRUNCATE(SDNode *N);
192 SDOperand visitBIT_CONVERT(SDNode *N);
193 SDOperand visitFADD(SDNode *N);
194 SDOperand visitFSUB(SDNode *N);
195 SDOperand visitFMUL(SDNode *N);
196 SDOperand visitFDIV(SDNode *N);
197 SDOperand visitFREM(SDNode *N);
198 SDOperand visitSINT_TO_FP(SDNode *N);
199 SDOperand visitUINT_TO_FP(SDNode *N);
200 SDOperand visitFP_TO_SINT(SDNode *N);
201 SDOperand visitFP_TO_UINT(SDNode *N);
202 SDOperand visitFP_ROUND(SDNode *N);
203 SDOperand visitFP_ROUND_INREG(SDNode *N);
204 SDOperand visitFP_EXTEND(SDNode *N);
205 SDOperand visitFNEG(SDNode *N);
206 SDOperand visitFABS(SDNode *N);
207 SDOperand visitBRCOND(SDNode *N);
208 SDOperand visitBRCONDTWOWAY(SDNode *N);
209 SDOperand visitBR_CC(SDNode *N);
210 SDOperand visitBRTWOWAY_CC(SDNode *N);
211 SDOperand visitLOAD(SDNode *N);
212 SDOperand visitSTORE(SDNode *N);
214 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
216 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
217 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
218 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
219 SDOperand N3, ISD::CondCode CC);
220 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
221 ISD::CondCode Cond, bool foldBooleans = true);
223 SDOperand BuildSDIV(SDNode *N);
224 SDOperand BuildUDIV(SDNode *N);
226 DAGCombiner(SelectionDAG &D)
227 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
229 /// Run - runs the dag combiner on all nodes in the work list
230 void Run(bool RunningAfterLegalize);
235 int64_t m; // magic number
236 int64_t s; // shift amount
240 uint64_t m; // magic number
241 int64_t a; // add indicator
242 int64_t s; // shift amount
245 /// magic - calculate the magic numbers required to codegen an integer sdiv as
246 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
248 static ms magic32(int32_t d) {
250 uint32_t ad, anc, delta, q1, r1, q2, r2, t;
251 const uint32_t two31 = 0x80000000U;
255 t = two31 + ((uint32_t)d >> 31);
256 anc = t - 1 - t%ad; // absolute value of nc
257 p = 31; // initialize p
258 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
259 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
260 q2 = two31/ad; // initialize q2 = 2p/abs(d)
261 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
264 q1 = 2*q1; // update q1 = 2p/abs(nc)
265 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
266 if (r1 >= anc) { // must be unsigned comparison
270 q2 = 2*q2; // update q2 = 2p/abs(d)
271 r2 = 2*r2; // update r2 = rem(2p/abs(d))
272 if (r2 >= ad) { // must be unsigned comparison
277 } while (q1 < delta || (q1 == delta && r1 == 0));
279 mag.m = (int32_t)(q2 + 1); // make sure to sign extend
280 if (d < 0) mag.m = -mag.m; // resulting magic number
281 mag.s = p - 32; // resulting shift
285 /// magicu - calculate the magic numbers required to codegen an integer udiv as
286 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
287 static mu magicu32(uint32_t d) {
289 uint32_t nc, delta, q1, r1, q2, r2;
291 magu.a = 0; // initialize "add" indicator
293 p = 31; // initialize p
294 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
295 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
296 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
297 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
300 if (r1 >= nc - r1 ) {
301 q1 = 2*q1 + 1; // update q1
302 r1 = 2*r1 - nc; // update r1
305 q1 = 2*q1; // update q1
306 r1 = 2*r1; // update r1
308 if (r2 + 1 >= d - r2) {
309 if (q2 >= 0x7FFFFFFF) magu.a = 1;
310 q2 = 2*q2 + 1; // update q2
311 r2 = 2*r2 + 1 - d; // update r2
314 if (q2 >= 0x80000000) magu.a = 1;
315 q2 = 2*q2; // update q2
316 r2 = 2*r2 + 1; // update r2
319 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
320 magu.m = q2 + 1; // resulting magic number
321 magu.s = p - 32; // resulting shift
325 /// magic - calculate the magic numbers required to codegen an integer sdiv as
326 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
328 static ms magic64(int64_t d) {
330 uint64_t ad, anc, delta, q1, r1, q2, r2, t;
331 const uint64_t two63 = 9223372036854775808ULL; // 2^63
334 ad = d >= 0 ? d : -d;
335 t = two63 + ((uint64_t)d >> 63);
336 anc = t - 1 - t%ad; // absolute value of nc
337 p = 63; // initialize p
338 q1 = two63/anc; // initialize q1 = 2p/abs(nc)
339 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
340 q2 = two63/ad; // initialize q2 = 2p/abs(d)
341 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
344 q1 = 2*q1; // update q1 = 2p/abs(nc)
345 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
346 if (r1 >= anc) { // must be unsigned comparison
350 q2 = 2*q2; // update q2 = 2p/abs(d)
351 r2 = 2*r2; // update r2 = rem(2p/abs(d))
352 if (r2 >= ad) { // must be unsigned comparison
357 } while (q1 < delta || (q1 == delta && r1 == 0));
360 if (d < 0) mag.m = -mag.m; // resulting magic number
361 mag.s = p - 64; // resulting shift
365 /// magicu - calculate the magic numbers required to codegen an integer udiv as
366 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
367 static mu magicu64(uint64_t d)
370 uint64_t nc, delta, q1, r1, q2, r2;
372 magu.a = 0; // initialize "add" indicator
374 p = 63; // initialize p
375 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
376 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
377 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
378 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
381 if (r1 >= nc - r1 ) {
382 q1 = 2*q1 + 1; // update q1
383 r1 = 2*r1 - nc; // update r1
386 q1 = 2*q1; // update q1
387 r1 = 2*r1; // update r1
389 if (r2 + 1 >= d - r2) {
390 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
391 q2 = 2*q2 + 1; // update q2
392 r2 = 2*r2 + 1 - d; // update r2
395 if (q2 >= 0x8000000000000000ull) magu.a = 1;
396 q2 = 2*q2; // update q2
397 r2 = 2*r2 + 1; // update r2
400 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
401 magu.m = q2 + 1; // resulting magic number
402 magu.s = p - 64; // resulting shift
406 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
407 // that selects between the values 1 and 0, making it equivalent to a setcc.
408 // Also, set the incoming LHS, RHS, and CC references to the appropriate
409 // nodes based on the type of node we are checking. This simplifies life a
410 // bit for the callers.
411 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
413 if (N.getOpcode() == ISD::SETCC) {
414 LHS = N.getOperand(0);
415 RHS = N.getOperand(1);
416 CC = N.getOperand(2);
419 if (N.getOpcode() == ISD::SELECT_CC &&
420 N.getOperand(2).getOpcode() == ISD::Constant &&
421 N.getOperand(3).getOpcode() == ISD::Constant &&
422 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
423 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
424 LHS = N.getOperand(0);
425 RHS = N.getOperand(1);
426 CC = N.getOperand(4);
432 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
433 // one use. If this is true, it allows the users to invert the operation for
434 // free when it is profitable to do so.
435 static bool isOneUseSetCC(SDOperand N) {
436 SDOperand N0, N1, N2;
437 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
442 // FIXME: This should probably go in the ISD class rather than being duplicated
444 static bool isCommutativeBinOp(unsigned Opcode) {
450 case ISD::XOR: return true;
451 default: return false; // FIXME: Need commutative info for user ops!
455 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
456 MVT::ValueType VT = N0.getValueType();
457 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
458 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
459 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
460 if (isa<ConstantSDNode>(N1)) {
461 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
462 WorkList.push_back(OpNode.Val);
463 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
464 } else if (N0.hasOneUse()) {
465 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
466 WorkList.push_back(OpNode.Val);
467 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
470 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
471 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
472 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
473 if (isa<ConstantSDNode>(N0)) {
474 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
475 WorkList.push_back(OpNode.Val);
476 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
477 } else if (N1.hasOneUse()) {
478 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
479 WorkList.push_back(OpNode.Val);
480 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
486 void DAGCombiner::Run(bool RunningAfterLegalize) {
487 // set the instance variable, so that the various visit routines may use it.
488 AfterLegalize = RunningAfterLegalize;
490 // Add all the dag nodes to the worklist.
491 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
492 E = DAG.allnodes_end(); I != E; ++I)
493 WorkList.push_back(I);
495 // Create a dummy node (which is not added to allnodes), that adds a reference
496 // to the root node, preventing it from being deleted, and tracking any
497 // changes of the root.
498 HandleSDNode Dummy(DAG.getRoot());
500 // while the worklist isn't empty, inspect the node on the end of it and
501 // try and combine it.
502 while (!WorkList.empty()) {
503 SDNode *N = WorkList.back();
506 // If N has no uses, it is dead. Make sure to revisit all N's operands once
507 // N is deleted from the DAG, since they too may now be dead or may have a
508 // reduced number of uses, allowing other xforms.
509 if (N->use_empty() && N != &Dummy) {
510 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
511 WorkList.push_back(N->getOperand(i).Val);
513 removeFromWorkList(N);
518 SDOperand RV = visit(N);
521 // If we get back the same node we passed in, rather than a new node or
522 // zero, we know that the node must have defined multiple values and
523 // CombineTo was used. Since CombineTo takes care of the worklist
524 // mechanics for us, we have no work to do in this case.
526 DEBUG(std::cerr << "\nReplacing "; N->dump();
527 std::cerr << "\nWith: "; RV.Val->dump();
529 std::vector<SDNode*> NowDead;
530 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead);
532 // Push the new node and any users onto the worklist
533 WorkList.push_back(RV.Val);
534 AddUsersToWorkList(RV.Val);
536 // Nodes can end up on the worklist more than once. Make sure we do
537 // not process a node that has been replaced.
538 removeFromWorkList(N);
539 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
540 removeFromWorkList(NowDead[i]);
542 // Finally, since the node is now dead, remove it from the graph.
548 // If the root changed (e.g. it was a dead load, update the root).
549 DAG.setRoot(Dummy.getValue());
552 SDOperand DAGCombiner::visit(SDNode *N) {
553 switch(N->getOpcode()) {
555 case ISD::TokenFactor: return visitTokenFactor(N);
556 case ISD::ADD: return visitADD(N);
557 case ISD::SUB: return visitSUB(N);
558 case ISD::MUL: return visitMUL(N);
559 case ISD::SDIV: return visitSDIV(N);
560 case ISD::UDIV: return visitUDIV(N);
561 case ISD::SREM: return visitSREM(N);
562 case ISD::UREM: return visitUREM(N);
563 case ISD::MULHU: return visitMULHU(N);
564 case ISD::MULHS: return visitMULHS(N);
565 case ISD::AND: return visitAND(N);
566 case ISD::OR: return visitOR(N);
567 case ISD::XOR: return visitXOR(N);
568 case ISD::SHL: return visitSHL(N);
569 case ISD::SRA: return visitSRA(N);
570 case ISD::SRL: return visitSRL(N);
571 case ISD::CTLZ: return visitCTLZ(N);
572 case ISD::CTTZ: return visitCTTZ(N);
573 case ISD::CTPOP: return visitCTPOP(N);
574 case ISD::SELECT: return visitSELECT(N);
575 case ISD::SELECT_CC: return visitSELECT_CC(N);
576 case ISD::SETCC: return visitSETCC(N);
577 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
578 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
579 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
580 case ISD::TRUNCATE: return visitTRUNCATE(N);
581 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
582 case ISD::FADD: return visitFADD(N);
583 case ISD::FSUB: return visitFSUB(N);
584 case ISD::FMUL: return visitFMUL(N);
585 case ISD::FDIV: return visitFDIV(N);
586 case ISD::FREM: return visitFREM(N);
587 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
588 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
589 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
590 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
591 case ISD::FP_ROUND: return visitFP_ROUND(N);
592 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
593 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
594 case ISD::FNEG: return visitFNEG(N);
595 case ISD::FABS: return visitFABS(N);
596 case ISD::BRCOND: return visitBRCOND(N);
597 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N);
598 case ISD::BR_CC: return visitBR_CC(N);
599 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N);
600 case ISD::LOAD: return visitLOAD(N);
601 case ISD::STORE: return visitSTORE(N);
606 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
607 std::vector<SDOperand> Ops;
608 bool Changed = false;
610 // If the token factor has two operands and one is the entry token, replace
611 // the token factor with the other operand.
612 if (N->getNumOperands() == 2) {
613 if (N->getOperand(0).getOpcode() == ISD::EntryToken)
614 return N->getOperand(1);
615 if (N->getOperand(1).getOpcode() == ISD::EntryToken)
616 return N->getOperand(0);
619 // fold (tokenfactor (tokenfactor)) -> tokenfactor
620 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
621 SDOperand Op = N->getOperand(i);
622 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) {
624 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j)
625 Ops.push_back(Op.getOperand(j));
631 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
635 SDOperand DAGCombiner::visitADD(SDNode *N) {
636 SDOperand N0 = N->getOperand(0);
637 SDOperand N1 = N->getOperand(1);
638 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
639 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
640 MVT::ValueType VT = N0.getValueType();
642 // fold (add c1, c2) -> c1+c2
644 return DAG.getNode(ISD::ADD, VT, N0, N1);
645 // canonicalize constant to RHS
647 return DAG.getNode(ISD::ADD, VT, N1, N0);
648 // fold (add x, 0) -> x
649 if (N1C && N1C->isNullValue())
651 // fold ((c1-A)+c2) -> (c1+c2)-A
652 if (N1C && N0.getOpcode() == ISD::SUB)
653 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
654 return DAG.getNode(ISD::SUB, VT,
655 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
658 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
661 // fold ((0-A) + B) -> B-A
662 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
663 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
664 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
665 // fold (A + (0-B)) -> A-B
666 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
667 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
668 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
669 // fold (A+(B-A)) -> B
670 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
671 return N1.getOperand(0);
673 if (SimplifyDemandedBits(SDOperand(N, 0)))
678 SDOperand DAGCombiner::visitSUB(SDNode *N) {
679 SDOperand N0 = N->getOperand(0);
680 SDOperand N1 = N->getOperand(1);
681 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
682 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
683 MVT::ValueType VT = N0.getValueType();
685 // fold (sub x, x) -> 0
687 return DAG.getConstant(0, N->getValueType(0));
688 // fold (sub c1, c2) -> c1-c2
690 return DAG.getNode(ISD::SUB, VT, N0, N1);
691 // fold (sub x, c) -> (add x, -c)
693 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
695 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
696 return N0.getOperand(1);
698 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
699 return N0.getOperand(0);
703 SDOperand DAGCombiner::visitMUL(SDNode *N) {
704 SDOperand N0 = N->getOperand(0);
705 SDOperand N1 = N->getOperand(1);
706 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
707 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
708 MVT::ValueType VT = N0.getValueType();
710 // fold (mul c1, c2) -> c1*c2
712 return DAG.getNode(ISD::MUL, VT, N0, N1);
713 // canonicalize constant to RHS
715 return DAG.getNode(ISD::MUL, VT, N1, N0);
716 // fold (mul x, 0) -> 0
717 if (N1C && N1C->isNullValue())
719 // fold (mul x, -1) -> 0-x
720 if (N1C && N1C->isAllOnesValue())
721 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
722 // fold (mul x, (1 << c)) -> x << c
723 if (N1C && isPowerOf2_64(N1C->getValue()))
724 return DAG.getNode(ISD::SHL, VT, N0,
725 DAG.getConstant(Log2_64(N1C->getValue()),
726 TLI.getShiftAmountTy()));
727 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
728 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
729 // FIXME: If the input is something that is easily negated (e.g. a
730 // single-use add), we should put the negate there.
731 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
732 DAG.getNode(ISD::SHL, VT, N0,
733 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
734 TLI.getShiftAmountTy())));
737 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
743 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
744 SDOperand N0 = N->getOperand(0);
745 SDOperand N1 = N->getOperand(1);
746 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
747 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
748 MVT::ValueType VT = N->getValueType(0);
750 // fold (sdiv c1, c2) -> c1/c2
751 if (N0C && N1C && !N1C->isNullValue())
752 return DAG.getNode(ISD::SDIV, VT, N0, N1);
753 // fold (sdiv X, 1) -> X
754 if (N1C && N1C->getSignExtended() == 1LL)
756 // fold (sdiv X, -1) -> 0-X
757 if (N1C && N1C->isAllOnesValue())
758 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
759 // If we know the sign bits of both operands are zero, strength reduce to a
760 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
761 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
762 if (TLI.MaskedValueIsZero(N1, SignBit) &&
763 TLI.MaskedValueIsZero(N0, SignBit))
764 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
765 // fold (sdiv X, pow2) -> simple ops after legalize
766 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
767 (isPowerOf2_64(N1C->getSignExtended()) ||
768 isPowerOf2_64(-N1C->getSignExtended()))) {
769 // If dividing by powers of two is cheap, then don't perform the following
771 if (TLI.isPow2DivCheap())
773 int64_t pow2 = N1C->getSignExtended();
774 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
775 unsigned lg2 = Log2_64(abs2);
776 // Splat the sign bit into the register
777 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
778 DAG.getConstant(MVT::getSizeInBits(VT)-1,
779 TLI.getShiftAmountTy()));
780 WorkList.push_back(SGN.Val);
781 // Add (N0 < 0) ? abs2 - 1 : 0;
782 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
783 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
784 TLI.getShiftAmountTy()));
785 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
786 WorkList.push_back(SRL.Val);
787 WorkList.push_back(ADD.Val); // Divide by pow2
788 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
789 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
790 // If we're dividing by a positive value, we're done. Otherwise, we must
791 // negate the result.
794 WorkList.push_back(SRA.Val);
795 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
797 // if integer divide is expensive and we satisfy the requirements, emit an
798 // alternate sequence.
799 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
800 !TLI.isIntDivCheap()) {
801 SDOperand Op = BuildSDIV(N);
802 if (Op.Val) return Op;
807 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
808 SDOperand N0 = N->getOperand(0);
809 SDOperand N1 = N->getOperand(1);
810 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
811 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
812 MVT::ValueType VT = N->getValueType(0);
814 // fold (udiv c1, c2) -> c1/c2
815 if (N0C && N1C && !N1C->isNullValue())
816 return DAG.getNode(ISD::UDIV, VT, N0, N1);
817 // fold (udiv x, (1 << c)) -> x >>u c
818 if (N1C && isPowerOf2_64(N1C->getValue()))
819 return DAG.getNode(ISD::SRL, VT, N0,
820 DAG.getConstant(Log2_64(N1C->getValue()),
821 TLI.getShiftAmountTy()));
822 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
823 if (N1.getOpcode() == ISD::SHL) {
824 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
825 if (isPowerOf2_64(SHC->getValue())) {
826 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
827 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
828 DAG.getConstant(Log2_64(SHC->getValue()),
830 WorkList.push_back(Add.Val);
831 return DAG.getNode(ISD::SRL, VT, N0, Add);
835 // fold (udiv x, c) -> alternate
836 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
837 SDOperand Op = BuildUDIV(N);
838 if (Op.Val) return Op;
843 SDOperand DAGCombiner::visitSREM(SDNode *N) {
844 SDOperand N0 = N->getOperand(0);
845 SDOperand N1 = N->getOperand(1);
846 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
847 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
848 MVT::ValueType VT = N->getValueType(0);
850 // fold (srem c1, c2) -> c1%c2
851 if (N0C && N1C && !N1C->isNullValue())
852 return DAG.getNode(ISD::SREM, VT, N0, N1);
853 // If we know the sign bits of both operands are zero, strength reduce to a
854 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
855 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
856 if (TLI.MaskedValueIsZero(N1, SignBit) &&
857 TLI.MaskedValueIsZero(N0, SignBit))
858 return DAG.getNode(ISD::UREM, VT, N0, N1);
862 SDOperand DAGCombiner::visitUREM(SDNode *N) {
863 SDOperand N0 = N->getOperand(0);
864 SDOperand N1 = N->getOperand(1);
865 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
866 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
867 MVT::ValueType VT = N->getValueType(0);
869 // fold (urem c1, c2) -> c1%c2
870 if (N0C && N1C && !N1C->isNullValue())
871 return DAG.getNode(ISD::UREM, VT, N0, N1);
872 // fold (urem x, pow2) -> (and x, pow2-1)
873 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
874 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
875 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
876 if (N1.getOpcode() == ISD::SHL) {
877 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
878 if (isPowerOf2_64(SHC->getValue())) {
879 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
880 WorkList.push_back(Add.Val);
881 return DAG.getNode(ISD::AND, VT, N0, Add);
888 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
889 SDOperand N0 = N->getOperand(0);
890 SDOperand N1 = N->getOperand(1);
891 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
893 // fold (mulhs x, 0) -> 0
894 if (N1C && N1C->isNullValue())
896 // fold (mulhs x, 1) -> (sra x, size(x)-1)
897 if (N1C && N1C->getValue() == 1)
898 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
899 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
900 TLI.getShiftAmountTy()));
904 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
905 SDOperand N0 = N->getOperand(0);
906 SDOperand N1 = N->getOperand(1);
907 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
909 // fold (mulhu x, 0) -> 0
910 if (N1C && N1C->isNullValue())
912 // fold (mulhu x, 1) -> 0
913 if (N1C && N1C->getValue() == 1)
914 return DAG.getConstant(0, N0.getValueType());
918 SDOperand DAGCombiner::visitAND(SDNode *N) {
919 SDOperand N0 = N->getOperand(0);
920 SDOperand N1 = N->getOperand(1);
921 SDOperand LL, LR, RL, RR, CC0, CC1;
922 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
923 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
924 MVT::ValueType VT = N1.getValueType();
925 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
927 // fold (and c1, c2) -> c1&c2
929 return DAG.getNode(ISD::AND, VT, N0, N1);
930 // canonicalize constant to RHS
932 return DAG.getNode(ISD::AND, VT, N1, N0);
933 // fold (and x, -1) -> x
934 if (N1C && N1C->isAllOnesValue())
936 // if (and x, c) is known to be zero, return 0
937 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
938 return DAG.getConstant(0, VT);
940 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
943 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
944 if (N1C && N0.getOpcode() == ISD::OR)
945 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
946 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
948 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
949 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
950 unsigned InBits = MVT::getSizeInBits(N0.getOperand(0).getValueType());
951 if (TLI.MaskedValueIsZero(N0.getOperand(0),
952 ~N1C->getValue() & ((1ULL << InBits)-1))) {
953 // We actually want to replace all uses of the any_extend with the
954 // zero_extend, to avoid duplicating things. This will later cause this
956 CombineTo(N0.Val, DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
961 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
962 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
963 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
964 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
966 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
967 MVT::isInteger(LL.getValueType())) {
968 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
969 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
970 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
971 WorkList.push_back(ORNode.Val);
972 return DAG.getSetCC(VT, ORNode, LR, Op1);
974 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
975 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
976 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
977 WorkList.push_back(ANDNode.Val);
978 return DAG.getSetCC(VT, ANDNode, LR, Op1);
980 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
981 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
982 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
983 WorkList.push_back(ORNode.Val);
984 return DAG.getSetCC(VT, ORNode, LR, Op1);
987 // canonicalize equivalent to ll == rl
988 if (LL == RR && LR == RL) {
989 Op1 = ISD::getSetCCSwappedOperands(Op1);
992 if (LL == RL && LR == RR) {
993 bool isInteger = MVT::isInteger(LL.getValueType());
994 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
995 if (Result != ISD::SETCC_INVALID)
996 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
999 // fold (and (zext x), (zext y)) -> (zext (and x, y))
1000 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1001 N1.getOpcode() == ISD::ZERO_EXTEND &&
1002 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1003 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
1004 N0.getOperand(0), N1.getOperand(0));
1005 WorkList.push_back(ANDNode.Val);
1006 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode);
1008 // fold (and (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (and x, y))
1009 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
1010 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
1011 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
1012 N0.getOperand(1) == N1.getOperand(1)) {
1013 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
1014 N0.getOperand(0), N1.getOperand(0));
1015 WorkList.push_back(ANDNode.Val);
1016 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
1018 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1019 // fold (and (sra)) -> (and (srl)) when possible.
1020 if (SimplifyDemandedBits(SDOperand(N, 0)))
1022 // fold (zext_inreg (extload x)) -> (zextload x)
1023 if (N0.getOpcode() == ISD::EXTLOAD) {
1024 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1025 // If we zero all the possible extended bits, then we can turn this into
1026 // a zextload if we are running before legalize or the operation is legal.
1027 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1028 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1029 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1030 N0.getOperand(1), N0.getOperand(2),
1032 WorkList.push_back(N);
1033 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1037 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1038 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) {
1039 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1040 // If we zero all the possible extended bits, then we can turn this into
1041 // a zextload if we are running before legalize or the operation is legal.
1042 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1043 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1044 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1045 N0.getOperand(1), N0.getOperand(2),
1047 WorkList.push_back(N);
1048 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1055 SDOperand DAGCombiner::visitOR(SDNode *N) {
1056 SDOperand N0 = N->getOperand(0);
1057 SDOperand N1 = N->getOperand(1);
1058 SDOperand LL, LR, RL, RR, CC0, CC1;
1059 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1060 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1061 MVT::ValueType VT = N1.getValueType();
1062 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1064 // fold (or c1, c2) -> c1|c2
1066 return DAG.getNode(ISD::OR, VT, N0, N1);
1067 // canonicalize constant to RHS
1069 return DAG.getNode(ISD::OR, VT, N1, N0);
1070 // fold (or x, 0) -> x
1071 if (N1C && N1C->isNullValue())
1073 // fold (or x, -1) -> -1
1074 if (N1C && N1C->isAllOnesValue())
1076 // fold (or x, c) -> c iff (x & ~c) == 0
1078 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1081 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1084 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1085 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1086 isa<ConstantSDNode>(N0.getOperand(1))) {
1087 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1088 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1090 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1092 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1093 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1094 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1095 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1097 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1098 MVT::isInteger(LL.getValueType())) {
1099 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1100 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1101 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1102 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1103 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1104 WorkList.push_back(ORNode.Val);
1105 return DAG.getSetCC(VT, ORNode, LR, Op1);
1107 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1108 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1109 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1110 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1111 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1112 WorkList.push_back(ANDNode.Val);
1113 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1116 // canonicalize equivalent to ll == rl
1117 if (LL == RR && LR == RL) {
1118 Op1 = ISD::getSetCCSwappedOperands(Op1);
1121 if (LL == RL && LR == RR) {
1122 bool isInteger = MVT::isInteger(LL.getValueType());
1123 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1124 if (Result != ISD::SETCC_INVALID)
1125 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1128 // fold (or (zext x), (zext y)) -> (zext (or x, y))
1129 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1130 N1.getOpcode() == ISD::ZERO_EXTEND &&
1131 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1132 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
1133 N0.getOperand(0), N1.getOperand(0));
1134 WorkList.push_back(ORNode.Val);
1135 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode);
1137 // fold (or (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (or x, y))
1138 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
1139 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
1140 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
1141 N0.getOperand(1) == N1.getOperand(1)) {
1142 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
1143 N0.getOperand(0), N1.getOperand(0));
1144 WorkList.push_back(ORNode.Val);
1145 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1147 // canonicalize shl to left side in a shl/srl pair, to match rotate
1148 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
1150 // check for rotl, rotr
1151 if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL &&
1152 N0.getOperand(0) == N1.getOperand(0) &&
1153 TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) {
1154 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1155 if (N0.getOperand(1).getOpcode() == ISD::Constant &&
1156 N1.getOperand(1).getOpcode() == ISD::Constant) {
1157 uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1158 uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1159 if ((c1val + c2val) == OpSizeInBits)
1160 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
1162 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1163 if (N1.getOperand(1).getOpcode() == ISD::SUB &&
1164 N0.getOperand(1) == N1.getOperand(1).getOperand(1))
1165 if (ConstantSDNode *SUBC =
1166 dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0)))
1167 if (SUBC->getValue() == OpSizeInBits)
1168 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
1169 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1170 if (N0.getOperand(1).getOpcode() == ISD::SUB &&
1171 N1.getOperand(1) == N0.getOperand(1).getOperand(1))
1172 if (ConstantSDNode *SUBC =
1173 dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0)))
1174 if (SUBC->getValue() == OpSizeInBits) {
1175 if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT))
1176 return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0),
1179 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0),
1186 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1187 SDOperand N0 = N->getOperand(0);
1188 SDOperand N1 = N->getOperand(1);
1189 SDOperand LHS, RHS, CC;
1190 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1191 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1192 MVT::ValueType VT = N0.getValueType();
1194 // fold (xor c1, c2) -> c1^c2
1196 return DAG.getNode(ISD::XOR, VT, N0, N1);
1197 // canonicalize constant to RHS
1199 return DAG.getNode(ISD::XOR, VT, N1, N0);
1200 // fold (xor x, 0) -> x
1201 if (N1C && N1C->isNullValue())
1204 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1207 // fold !(x cc y) -> (x !cc y)
1208 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1209 bool isInt = MVT::isInteger(LHS.getValueType());
1210 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1212 if (N0.getOpcode() == ISD::SETCC)
1213 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1214 if (N0.getOpcode() == ISD::SELECT_CC)
1215 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1216 assert(0 && "Unhandled SetCC Equivalent!");
1219 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1220 if (N1C && N1C->getValue() == 1 &&
1221 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1222 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1223 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1224 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1225 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1226 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1227 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
1228 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1231 // fold !(x or y) -> (!x and !y) iff x or y are constants
1232 if (N1C && N1C->isAllOnesValue() &&
1233 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1234 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1235 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1236 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1237 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1238 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1239 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
1240 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1243 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1244 if (N1C && N0.getOpcode() == ISD::XOR) {
1245 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1246 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1248 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1249 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1251 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1252 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1254 // fold (xor x, x) -> 0
1256 return DAG.getConstant(0, VT);
1257 // fold (xor (zext x), (zext y)) -> (zext (xor x, y))
1258 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1259 N1.getOpcode() == ISD::ZERO_EXTEND &&
1260 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1261 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
1262 N0.getOperand(0), N1.getOperand(0));
1263 WorkList.push_back(XORNode.Val);
1264 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
1266 // fold (xor (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (xor x, y))
1267 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
1268 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
1269 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
1270 N0.getOperand(1) == N1.getOperand(1)) {
1271 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
1272 N0.getOperand(0), N1.getOperand(0));
1273 WorkList.push_back(XORNode.Val);
1274 return DAG.getNode(N0.getOpcode(), VT, XORNode, N0.getOperand(1));
1279 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1280 SDOperand N0 = N->getOperand(0);
1281 SDOperand N1 = N->getOperand(1);
1282 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1283 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1284 MVT::ValueType VT = N0.getValueType();
1285 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1287 // fold (shl c1, c2) -> c1<<c2
1289 return DAG.getNode(ISD::SHL, VT, N0, N1);
1290 // fold (shl 0, x) -> 0
1291 if (N0C && N0C->isNullValue())
1293 // fold (shl x, c >= size(x)) -> undef
1294 if (N1C && N1C->getValue() >= OpSizeInBits)
1295 return DAG.getNode(ISD::UNDEF, VT);
1296 // fold (shl x, 0) -> x
1297 if (N1C && N1C->isNullValue())
1299 // if (shl x, c) is known to be zero, return 0
1300 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1301 return DAG.getConstant(0, VT);
1302 if (SimplifyDemandedBits(SDOperand(N, 0)))
1304 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1305 if (N1C && N0.getOpcode() == ISD::SHL &&
1306 N0.getOperand(1).getOpcode() == ISD::Constant) {
1307 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1308 uint64_t c2 = N1C->getValue();
1309 if (c1 + c2 > OpSizeInBits)
1310 return DAG.getConstant(0, VT);
1311 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1312 DAG.getConstant(c1 + c2, N1.getValueType()));
1314 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1315 // (srl (and x, -1 << c1), c1-c2)
1316 if (N1C && N0.getOpcode() == ISD::SRL &&
1317 N0.getOperand(1).getOpcode() == ISD::Constant) {
1318 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1319 uint64_t c2 = N1C->getValue();
1320 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1321 DAG.getConstant(~0ULL << c1, VT));
1323 return DAG.getNode(ISD::SHL, VT, Mask,
1324 DAG.getConstant(c2-c1, N1.getValueType()));
1326 return DAG.getNode(ISD::SRL, VT, Mask,
1327 DAG.getConstant(c1-c2, N1.getValueType()));
1329 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1330 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1331 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1332 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1336 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1337 SDOperand N0 = N->getOperand(0);
1338 SDOperand N1 = N->getOperand(1);
1339 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1340 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1341 MVT::ValueType VT = N0.getValueType();
1343 // fold (sra c1, c2) -> c1>>c2
1345 return DAG.getNode(ISD::SRA, VT, N0, N1);
1346 // fold (sra 0, x) -> 0
1347 if (N0C && N0C->isNullValue())
1349 // fold (sra -1, x) -> -1
1350 if (N0C && N0C->isAllOnesValue())
1352 // fold (sra x, c >= size(x)) -> undef
1353 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
1354 return DAG.getNode(ISD::UNDEF, VT);
1355 // fold (sra x, 0) -> x
1356 if (N1C && N1C->isNullValue())
1358 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
1360 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
1361 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
1364 default: EVT = MVT::Other; break;
1365 case 1: EVT = MVT::i1; break;
1366 case 8: EVT = MVT::i8; break;
1367 case 16: EVT = MVT::i16; break;
1368 case 32: EVT = MVT::i32; break;
1370 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
1371 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1372 DAG.getValueType(EVT));
1374 // If the sign bit is known to be zero, switch this to a SRL.
1375 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
1376 return DAG.getNode(ISD::SRL, VT, N0, N1);
1380 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1381 SDOperand N0 = N->getOperand(0);
1382 SDOperand N1 = N->getOperand(1);
1383 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1384 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1385 MVT::ValueType VT = N0.getValueType();
1386 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1388 // fold (srl c1, c2) -> c1 >>u c2
1390 return DAG.getNode(ISD::SRL, VT, N0, N1);
1391 // fold (srl 0, x) -> 0
1392 if (N0C && N0C->isNullValue())
1394 // fold (srl x, c >= size(x)) -> undef
1395 if (N1C && N1C->getValue() >= OpSizeInBits)
1396 return DAG.getNode(ISD::UNDEF, VT);
1397 // fold (srl x, 0) -> x
1398 if (N1C && N1C->isNullValue())
1400 // if (srl x, c) is known to be zero, return 0
1401 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1402 return DAG.getConstant(0, VT);
1403 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1404 if (N1C && N0.getOpcode() == ISD::SRL &&
1405 N0.getOperand(1).getOpcode() == ISD::Constant) {
1406 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1407 uint64_t c2 = N1C->getValue();
1408 if (c1 + c2 > OpSizeInBits)
1409 return DAG.getConstant(0, VT);
1410 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1411 DAG.getConstant(c1 + c2, N1.getValueType()));
1416 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1417 SDOperand N0 = N->getOperand(0);
1418 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1419 MVT::ValueType VT = N->getValueType(0);
1421 // fold (ctlz c1) -> c2
1423 return DAG.getNode(ISD::CTLZ, VT, N0);
1427 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1428 SDOperand N0 = N->getOperand(0);
1429 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1430 MVT::ValueType VT = N->getValueType(0);
1432 // fold (cttz c1) -> c2
1434 return DAG.getNode(ISD::CTTZ, VT, N0);
1438 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1439 SDOperand N0 = N->getOperand(0);
1440 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1441 MVT::ValueType VT = N->getValueType(0);
1443 // fold (ctpop c1) -> c2
1445 return DAG.getNode(ISD::CTPOP, VT, N0);
1449 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1450 SDOperand N0 = N->getOperand(0);
1451 SDOperand N1 = N->getOperand(1);
1452 SDOperand N2 = N->getOperand(2);
1453 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1454 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1455 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1456 MVT::ValueType VT = N->getValueType(0);
1458 // fold select C, X, X -> X
1461 // fold select true, X, Y -> X
1462 if (N0C && !N0C->isNullValue())
1464 // fold select false, X, Y -> Y
1465 if (N0C && N0C->isNullValue())
1467 // fold select C, 1, X -> C | X
1468 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1469 return DAG.getNode(ISD::OR, VT, N0, N2);
1470 // fold select C, 0, X -> ~C & X
1471 // FIXME: this should check for C type == X type, not i1?
1472 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1473 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1474 WorkList.push_back(XORNode.Val);
1475 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1477 // fold select C, X, 1 -> ~C | X
1478 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1479 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1480 WorkList.push_back(XORNode.Val);
1481 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1483 // fold select C, X, 0 -> C & X
1484 // FIXME: this should check for C type == X type, not i1?
1485 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1486 return DAG.getNode(ISD::AND, VT, N0, N1);
1487 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1488 if (MVT::i1 == VT && N0 == N1)
1489 return DAG.getNode(ISD::OR, VT, N0, N2);
1490 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1491 if (MVT::i1 == VT && N0 == N2)
1492 return DAG.getNode(ISD::AND, VT, N0, N1);
1493 // If we can fold this based on the true/false value, do so.
1494 if (SimplifySelectOps(N, N1, N2))
1496 // fold selects based on a setcc into other things, such as min/max/abs
1497 if (N0.getOpcode() == ISD::SETCC)
1499 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1500 // having to say they don't support SELECT_CC on every type the DAG knows
1501 // about, since there is no way to mark an opcode illegal at all value types
1502 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1503 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1504 N1, N2, N0.getOperand(2));
1506 return SimplifySelect(N0, N1, N2);
1510 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1511 SDOperand N0 = N->getOperand(0);
1512 SDOperand N1 = N->getOperand(1);
1513 SDOperand N2 = N->getOperand(2);
1514 SDOperand N3 = N->getOperand(3);
1515 SDOperand N4 = N->getOperand(4);
1516 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1517 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1518 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1519 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1521 // Determine if the condition we're dealing with is constant
1522 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1523 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1525 // fold select_cc lhs, rhs, x, x, cc -> x
1529 // If we can fold this based on the true/false value, do so.
1530 if (SimplifySelectOps(N, N2, N3))
1533 // fold select_cc into other things, such as min/max/abs
1534 return SimplifySelectCC(N0, N1, N2, N3, CC);
1537 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1538 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1539 cast<CondCodeSDNode>(N->getOperand(2))->get());
1542 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1543 SDOperand N0 = N->getOperand(0);
1544 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1545 MVT::ValueType VT = N->getValueType(0);
1547 // fold (sext c1) -> c1
1549 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
1550 // fold (sext (sext x)) -> (sext x)
1551 if (N0.getOpcode() == ISD::SIGN_EXTEND)
1552 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1553 // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size.
1554 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
1556 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType())))
1557 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1558 DAG.getValueType(N0.getValueType()));
1559 // fold (sext (load x)) -> (sext (truncate (sextload x)))
1560 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1561 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){
1562 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1563 N0.getOperand(1), N0.getOperand(2),
1565 CombineTo(N, ExtLoad);
1566 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1567 ExtLoad.getValue(1));
1571 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
1572 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
1573 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
1575 SDOperand ExtLoad = DAG.getNode(ISD::SEXTLOAD, VT, N0.getOperand(0),
1576 N0.getOperand(1), N0.getOperand(2),
1578 CombineTo(N, ExtLoad);
1579 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1580 ExtLoad.getValue(1));
1587 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1588 SDOperand N0 = N->getOperand(0);
1589 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1590 MVT::ValueType VT = N->getValueType(0);
1592 // fold (zext c1) -> c1
1594 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1595 // fold (zext (zext x)) -> (zext x)
1596 if (N0.getOpcode() == ISD::ZERO_EXTEND)
1597 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1598 // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size.
1599 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
1600 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType())))
1601 return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType());
1602 // fold (zext (load x)) -> (zext (truncate (zextload x)))
1603 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1604 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){
1605 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1606 N0.getOperand(1), N0.getOperand(2),
1608 CombineTo(N, ExtLoad);
1609 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1610 ExtLoad.getValue(1));
1614 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
1615 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
1616 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
1618 SDOperand ExtLoad = DAG.getNode(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1619 N0.getOperand(1), N0.getOperand(2),
1621 CombineTo(N, ExtLoad);
1622 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1623 ExtLoad.getValue(1));
1629 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1630 SDOperand N0 = N->getOperand(0);
1631 SDOperand N1 = N->getOperand(1);
1632 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1633 MVT::ValueType VT = N->getValueType(0);
1634 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
1635 unsigned EVTBits = MVT::getSizeInBits(EVT);
1637 // fold (sext_in_reg c1) -> c1
1639 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT);
1640 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate);
1642 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1
1643 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1644 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1647 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
1648 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1649 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
1650 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
1652 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x)
1653 if (N0.getOpcode() == ISD::AssertSext &&
1654 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1657 // fold (sext_in_reg (sextload x)) -> (sextload x)
1658 if (N0.getOpcode() == ISD::SEXTLOAD &&
1659 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) {
1662 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1
1663 if (N0.getOpcode() == ISD::SETCC &&
1664 TLI.getSetCCResultContents() ==
1665 TargetLowering::ZeroOrNegativeOneSetCCResult)
1667 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
1668 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
1669 return DAG.getZeroExtendInReg(N0, EVT);
1670 // fold (sext_in_reg (srl x)) -> sra x
1671 if (N0.getOpcode() == ISD::SRL &&
1672 N0.getOperand(1).getOpcode() == ISD::Constant &&
1673 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) {
1674 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0),
1677 // fold (sext_inreg (extload x)) -> (sextload x)
1678 if (N0.getOpcode() == ISD::EXTLOAD &&
1679 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1680 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1681 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1682 N0.getOperand(1), N0.getOperand(2),
1684 CombineTo(N, ExtLoad);
1685 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1688 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
1689 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() &&
1690 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1691 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1692 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1693 N0.getOperand(1), N0.getOperand(2),
1695 CombineTo(N, ExtLoad);
1696 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1702 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
1703 SDOperand N0 = N->getOperand(0);
1704 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1705 MVT::ValueType VT = N->getValueType(0);
1708 if (N0.getValueType() == N->getValueType(0))
1710 // fold (truncate c1) -> c1
1712 return DAG.getNode(ISD::TRUNCATE, VT, N0);
1713 // fold (truncate (truncate x)) -> (truncate x)
1714 if (N0.getOpcode() == ISD::TRUNCATE)
1715 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1716 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
1717 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){
1718 if (N0.getValueType() < VT)
1719 // if the source is smaller than the dest, we still need an extend
1720 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
1721 else if (N0.getValueType() > VT)
1722 // if the source is larger than the dest, than we just need the truncate
1723 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1725 // if the source and dest are the same type, we can drop both the extend
1727 return N0.getOperand(0);
1729 // fold (truncate (load x)) -> (smaller load x)
1730 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
1731 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
1732 "Cannot truncate to larger type!");
1733 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1734 // For big endian targets, we need to add an offset to the pointer to load
1735 // the correct bytes. For little endian systems, we merely need to read
1736 // fewer bytes from the same pointer.
1738 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
1739 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) :
1740 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1),
1741 DAG.getConstant(PtrOff, PtrType));
1742 WorkList.push_back(NewPtr.Val);
1743 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2));
1744 WorkList.push_back(N);
1745 CombineTo(N0.Val, Load, Load.getValue(1));
1751 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
1752 SDOperand N0 = N->getOperand(0);
1753 MVT::ValueType VT = N->getValueType(0);
1755 // If the input is a constant, let getNode() fold it.
1756 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
1757 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
1758 if (Res.Val != N) return Res;
1761 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
1762 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
1764 // fold (conv (load x)) -> (load (conv*)x)
1765 // FIXME: These xforms need to know that the resultant load doesn't need a
1766 // higher alignment than the original!
1767 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
1768 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1),
1770 WorkList.push_back(N);
1771 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
1779 SDOperand DAGCombiner::visitFADD(SDNode *N) {
1780 SDOperand N0 = N->getOperand(0);
1781 SDOperand N1 = N->getOperand(1);
1782 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1783 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1784 MVT::ValueType VT = N->getValueType(0);
1786 // fold (fadd c1, c2) -> c1+c2
1788 return DAG.getNode(ISD::FADD, VT, N0, N1);
1789 // canonicalize constant to RHS
1790 if (N0CFP && !N1CFP)
1791 return DAG.getNode(ISD::FADD, VT, N1, N0);
1792 // fold (A + (-B)) -> A-B
1793 if (N1.getOpcode() == ISD::FNEG)
1794 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
1795 // fold ((-A) + B) -> B-A
1796 if (N0.getOpcode() == ISD::FNEG)
1797 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
1801 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
1802 SDOperand N0 = N->getOperand(0);
1803 SDOperand N1 = N->getOperand(1);
1804 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1805 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1806 MVT::ValueType VT = N->getValueType(0);
1808 // fold (fsub c1, c2) -> c1-c2
1810 return DAG.getNode(ISD::FSUB, VT, N0, N1);
1811 // fold (A-(-B)) -> A+B
1812 if (N1.getOpcode() == ISD::FNEG)
1813 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
1817 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
1818 SDOperand N0 = N->getOperand(0);
1819 SDOperand N1 = N->getOperand(1);
1820 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1821 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1822 MVT::ValueType VT = N->getValueType(0);
1824 // fold (fmul c1, c2) -> c1*c2
1826 return DAG.getNode(ISD::FMUL, VT, N0, N1);
1827 // canonicalize constant to RHS
1828 if (N0CFP && !N1CFP)
1829 return DAG.getNode(ISD::FMUL, VT, N1, N0);
1830 // fold (fmul X, 2.0) -> (fadd X, X)
1831 if (N1CFP && N1CFP->isExactlyValue(+2.0))
1832 return DAG.getNode(ISD::FADD, VT, N0, N0);
1836 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
1837 SDOperand N0 = N->getOperand(0);
1838 SDOperand N1 = N->getOperand(1);
1839 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1840 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1841 MVT::ValueType VT = N->getValueType(0);
1843 // fold (fdiv c1, c2) -> c1/c2
1845 return DAG.getNode(ISD::FDIV, VT, N0, N1);
1849 SDOperand DAGCombiner::visitFREM(SDNode *N) {
1850 SDOperand N0 = N->getOperand(0);
1851 SDOperand N1 = N->getOperand(1);
1852 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1853 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1854 MVT::ValueType VT = N->getValueType(0);
1856 // fold (frem c1, c2) -> fmod(c1,c2)
1858 return DAG.getNode(ISD::FREM, VT, N0, N1);
1863 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
1864 SDOperand N0 = N->getOperand(0);
1865 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1866 MVT::ValueType VT = N->getValueType(0);
1868 // fold (sint_to_fp c1) -> c1fp
1870 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
1874 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
1875 SDOperand N0 = N->getOperand(0);
1876 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1877 MVT::ValueType VT = N->getValueType(0);
1879 // fold (uint_to_fp c1) -> c1fp
1881 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
1885 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
1886 SDOperand N0 = N->getOperand(0);
1887 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1888 MVT::ValueType VT = N->getValueType(0);
1890 // fold (fp_to_sint c1fp) -> c1
1892 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
1896 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
1897 SDOperand N0 = N->getOperand(0);
1898 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1899 MVT::ValueType VT = N->getValueType(0);
1901 // fold (fp_to_uint c1fp) -> c1
1903 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
1907 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
1908 SDOperand N0 = N->getOperand(0);
1909 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1910 MVT::ValueType VT = N->getValueType(0);
1912 // fold (fp_round c1fp) -> c1fp
1914 return DAG.getNode(ISD::FP_ROUND, VT, N0);
1918 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
1919 SDOperand N0 = N->getOperand(0);
1920 MVT::ValueType VT = N->getValueType(0);
1921 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1922 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1924 // fold (fp_round_inreg c1fp) -> c1fp
1926 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
1927 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
1932 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
1933 SDOperand N0 = N->getOperand(0);
1934 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1935 MVT::ValueType VT = N->getValueType(0);
1937 // fold (fp_extend c1fp) -> c1fp
1939 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
1943 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
1944 SDOperand N0 = N->getOperand(0);
1945 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1946 MVT::ValueType VT = N->getValueType(0);
1948 // fold (fneg c1) -> -c1
1950 return DAG.getNode(ISD::FNEG, VT, N0);
1951 // fold (fneg (sub x, y)) -> (sub y, x)
1952 if (N->getOperand(0).getOpcode() == ISD::SUB)
1953 return DAG.getNode(ISD::SUB, VT, N->getOperand(1), N->getOperand(0));
1954 // fold (fneg (fneg x)) -> x
1955 if (N->getOperand(0).getOpcode() == ISD::FNEG)
1956 return N->getOperand(0).getOperand(0);
1960 SDOperand DAGCombiner::visitFABS(SDNode *N) {
1961 SDOperand N0 = N->getOperand(0);
1962 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1963 MVT::ValueType VT = N->getValueType(0);
1965 // fold (fabs c1) -> fabs(c1)
1967 return DAG.getNode(ISD::FABS, VT, N0);
1968 // fold (fabs (fabs x)) -> (fabs x)
1969 if (N->getOperand(0).getOpcode() == ISD::FABS)
1970 return N->getOperand(0);
1971 // fold (fabs (fneg x)) -> (fabs x)
1972 if (N->getOperand(0).getOpcode() == ISD::FNEG)
1973 return DAG.getNode(ISD::FABS, VT, N->getOperand(0).getOperand(0));
1977 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
1978 SDOperand Chain = N->getOperand(0);
1979 SDOperand N1 = N->getOperand(1);
1980 SDOperand N2 = N->getOperand(2);
1981 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1983 // never taken branch, fold to chain
1984 if (N1C && N1C->isNullValue())
1986 // unconditional branch
1987 if (N1C && N1C->getValue() == 1)
1988 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
1989 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
1991 if (N1.getOpcode() == ISD::SETCC &&
1992 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
1993 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
1994 N1.getOperand(0), N1.getOperand(1), N2);
1999 SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) {
2000 SDOperand Chain = N->getOperand(0);
2001 SDOperand N1 = N->getOperand(1);
2002 SDOperand N2 = N->getOperand(2);
2003 SDOperand N3 = N->getOperand(3);
2004 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2006 // unconditional branch to true mbb
2007 if (N1C && N1C->getValue() == 1)
2008 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2009 // unconditional branch to false mbb
2010 if (N1C && N1C->isNullValue())
2011 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3);
2012 // fold a brcondtwoway with a setcc condition into a BRTWOWAY_CC node if
2013 // BRTWOWAY_CC is legal on the target.
2014 if (N1.getOpcode() == ISD::SETCC &&
2015 TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) {
2016 std::vector<SDOperand> Ops;
2017 Ops.push_back(Chain);
2018 Ops.push_back(N1.getOperand(2));
2019 Ops.push_back(N1.getOperand(0));
2020 Ops.push_back(N1.getOperand(1));
2023 return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops);
2028 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
2030 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
2031 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2032 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2034 // Use SimplifySetCC to simplify SETCC's.
2035 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2036 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2038 // fold br_cc true, dest -> br dest (unconditional branch)
2039 if (SCCC && SCCC->getValue())
2040 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2042 // fold br_cc false, dest -> unconditional fall through
2043 if (SCCC && SCCC->isNullValue())
2044 return N->getOperand(0);
2045 // fold to a simpler setcc
2046 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2047 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2048 Simp.getOperand(2), Simp.getOperand(0),
2049 Simp.getOperand(1), N->getOperand(4));
2053 SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) {
2054 SDOperand Chain = N->getOperand(0);
2055 SDOperand CCN = N->getOperand(1);
2056 SDOperand LHS = N->getOperand(2);
2057 SDOperand RHS = N->getOperand(3);
2058 SDOperand N4 = N->getOperand(4);
2059 SDOperand N5 = N->getOperand(5);
2061 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS,
2062 cast<CondCodeSDNode>(CCN)->get(), false);
2063 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
2065 // fold select_cc lhs, rhs, x, x, cc -> x
2067 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
2068 // fold select_cc true, x, y -> x
2069 if (SCCC && SCCC->getValue())
2070 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
2071 // fold select_cc false, x, y -> y
2072 if (SCCC && SCCC->isNullValue())
2073 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5);
2074 // fold to a simpler setcc
2075 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) {
2076 std::vector<SDOperand> Ops;
2077 Ops.push_back(Chain);
2078 Ops.push_back(SCC.getOperand(2));
2079 Ops.push_back(SCC.getOperand(0));
2080 Ops.push_back(SCC.getOperand(1));
2083 return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops);
2088 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
2089 SDOperand Chain = N->getOperand(0);
2090 SDOperand Ptr = N->getOperand(1);
2091 SDOperand SrcValue = N->getOperand(2);
2093 // If this load is directly stored, replace the load value with the stored
2095 // TODO: Handle store large -> read small portion.
2096 // TODO: Handle TRUNCSTORE/EXTLOAD
2097 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2098 Chain.getOperand(1).getValueType() == N->getValueType(0))
2099 return CombineTo(N, Chain.getOperand(1), Chain);
2104 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
2105 SDOperand Chain = N->getOperand(0);
2106 SDOperand Value = N->getOperand(1);
2107 SDOperand Ptr = N->getOperand(2);
2108 SDOperand SrcValue = N->getOperand(3);
2110 // If this is a store that kills a previous store, remove the previous store.
2111 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2112 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ &&
2113 // Make sure that these stores are the same value type:
2114 // FIXME: we really care that the second store is >= size of the first.
2115 Value.getValueType() == Chain.getOperand(1).getValueType()) {
2116 // Create a new store of Value that replaces both stores.
2117 SDNode *PrevStore = Chain.Val;
2118 if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
2120 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other,
2121 PrevStore->getOperand(0), Value, Ptr,
2123 CombineTo(N, NewStore); // Nuke this store.
2124 CombineTo(PrevStore, NewStore); // Nuke the previous store.
2125 return SDOperand(N, 0);
2128 // If this is a store of a bit convert, store the input value.
2129 // FIXME: This needs to know that the resultant store does not need a
2130 // higher alignment than the original.
2131 if (0 && Value.getOpcode() == ISD::BIT_CONVERT)
2132 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0),
2138 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
2139 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
2141 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
2142 cast<CondCodeSDNode>(N0.getOperand(2))->get());
2143 // If we got a simplified select_cc node back from SimplifySelectCC, then
2144 // break it down into a new SETCC node, and a new SELECT node, and then return
2145 // the SELECT node, since we were called with a SELECT node.
2147 // Check to see if we got a select_cc back (to turn into setcc/select).
2148 // Otherwise, just return whatever node we got back, like fabs.
2149 if (SCC.getOpcode() == ISD::SELECT_CC) {
2150 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
2151 SCC.getOperand(0), SCC.getOperand(1),
2153 WorkList.push_back(SETCC.Val);
2154 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
2155 SCC.getOperand(3), SETCC);
2162 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
2163 /// are the two values being selected between, see if we can simplify the
2166 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
2169 // If this is a select from two identical things, try to pull the operation
2170 // through the select.
2171 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
2173 std::cerr << "SELECT: ["; LHS.Val->dump();
2174 std::cerr << "] ["; RHS.Val->dump();
2178 // If this is a load and the token chain is identical, replace the select
2179 // of two loads with a load through a select of the address to load from.
2180 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
2181 // constants have been dropped into the constant pool.
2182 if ((LHS.getOpcode() == ISD::LOAD ||
2183 LHS.getOpcode() == ISD::EXTLOAD ||
2184 LHS.getOpcode() == ISD::ZEXTLOAD ||
2185 LHS.getOpcode() == ISD::SEXTLOAD) &&
2186 // Token chains must be identical.
2187 LHS.getOperand(0) == RHS.getOperand(0) &&
2188 // If this is an EXTLOAD, the VT's must match.
2189 (LHS.getOpcode() == ISD::LOAD ||
2190 LHS.getOperand(3) == RHS.getOperand(3))) {
2191 // FIXME: this conflates two src values, discarding one. This is not
2192 // the right thing to do, but nothing uses srcvalues now. When they do,
2193 // turn SrcValue into a list of locations.
2195 if (TheSelect->getOpcode() == ISD::SELECT)
2196 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(),
2197 TheSelect->getOperand(0), LHS.getOperand(1),
2200 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(),
2201 TheSelect->getOperand(0),
2202 TheSelect->getOperand(1),
2203 LHS.getOperand(1), RHS.getOperand(1),
2204 TheSelect->getOperand(4));
2207 if (LHS.getOpcode() == ISD::LOAD)
2208 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0),
2209 Addr, LHS.getOperand(2));
2211 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0),
2212 LHS.getOperand(0), Addr, LHS.getOperand(2),
2213 cast<VTSDNode>(LHS.getOperand(3))->getVT());
2214 // Users of the select now use the result of the load.
2215 CombineTo(TheSelect, Load);
2217 // Users of the old loads now use the new load's chain. We know the
2218 // old-load value is dead now.
2219 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
2220 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
2228 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
2229 SDOperand N2, SDOperand N3,
2232 MVT::ValueType VT = N2.getValueType();
2233 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
2234 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
2235 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
2236 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
2238 // Determine if the condition we're dealing with is constant
2239 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
2240 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
2242 // fold select_cc true, x, y -> x
2243 if (SCCC && SCCC->getValue())
2245 // fold select_cc false, x, y -> y
2246 if (SCCC && SCCC->getValue() == 0)
2249 // Check to see if we can simplify the select into an fabs node
2250 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
2251 // Allow either -0.0 or 0.0
2252 if (CFP->getValue() == 0.0) {
2253 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
2254 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
2255 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
2256 N2 == N3.getOperand(0))
2257 return DAG.getNode(ISD::FABS, VT, N0);
2259 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
2260 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
2261 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
2262 N2.getOperand(0) == N3)
2263 return DAG.getNode(ISD::FABS, VT, N3);
2267 // Check to see if we can perform the "gzip trick", transforming
2268 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
2269 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() &&
2270 MVT::isInteger(N0.getValueType()) &&
2271 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) {
2272 MVT::ValueType XType = N0.getValueType();
2273 MVT::ValueType AType = N2.getValueType();
2274 if (XType >= AType) {
2275 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
2276 // single-bit constant.
2277 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
2278 unsigned ShCtV = Log2_64(N2C->getValue());
2279 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
2280 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
2281 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
2282 WorkList.push_back(Shift.Val);
2283 if (XType > AType) {
2284 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
2285 WorkList.push_back(Shift.Val);
2287 return DAG.getNode(ISD::AND, AType, Shift, N2);
2289 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
2290 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2291 TLI.getShiftAmountTy()));
2292 WorkList.push_back(Shift.Val);
2293 if (XType > AType) {
2294 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
2295 WorkList.push_back(Shift.Val);
2297 return DAG.getNode(ISD::AND, AType, Shift, N2);
2301 // fold select C, 16, 0 -> shl C, 4
2302 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
2303 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
2304 // Get a SetCC of the condition
2305 // FIXME: Should probably make sure that setcc is legal if we ever have a
2306 // target where it isn't.
2307 SDOperand Temp, SCC;
2308 // cast from setcc result type to select result type
2309 if (AfterLegalize) {
2310 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
2311 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
2313 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
2314 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
2316 WorkList.push_back(SCC.Val);
2317 WorkList.push_back(Temp.Val);
2318 // shl setcc result by log2 n2c
2319 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
2320 DAG.getConstant(Log2_64(N2C->getValue()),
2321 TLI.getShiftAmountTy()));
2324 // Check to see if this is the equivalent of setcc
2325 // FIXME: Turn all of these into setcc if setcc if setcc is legal
2326 // otherwise, go ahead with the folds.
2327 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
2328 MVT::ValueType XType = N0.getValueType();
2329 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
2330 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
2331 if (Res.getValueType() != VT)
2332 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
2336 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
2337 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
2338 TLI.isOperationLegal(ISD::CTLZ, XType)) {
2339 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
2340 return DAG.getNode(ISD::SRL, XType, Ctlz,
2341 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
2342 TLI.getShiftAmountTy()));
2344 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
2345 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
2346 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
2348 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
2349 DAG.getConstant(~0ULL, XType));
2350 return DAG.getNode(ISD::SRL, XType,
2351 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
2352 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2353 TLI.getShiftAmountTy()));
2355 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
2356 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
2357 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
2358 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2359 TLI.getShiftAmountTy()));
2360 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
2364 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
2365 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2366 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
2367 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
2368 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
2369 MVT::ValueType XType = N0.getValueType();
2370 if (SubC->isNullValue() && MVT::isInteger(XType)) {
2371 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
2372 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2373 TLI.getShiftAmountTy()));
2374 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
2375 WorkList.push_back(Shift.Val);
2376 WorkList.push_back(Add.Val);
2377 return DAG.getNode(ISD::XOR, XType, Add, Shift);
2385 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
2386 SDOperand N1, ISD::CondCode Cond,
2387 bool foldBooleans) {
2388 // These setcc operations always fold.
2392 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
2394 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
2397 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
2398 uint64_t C1 = N1C->getValue();
2399 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
2400 uint64_t C0 = N0C->getValue();
2402 // Sign extend the operands if required
2403 if (ISD::isSignedIntSetCC(Cond)) {
2404 C0 = N0C->getSignExtended();
2405 C1 = N1C->getSignExtended();
2409 default: assert(0 && "Unknown integer setcc!");
2410 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
2411 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
2412 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
2413 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
2414 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
2415 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
2416 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
2417 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
2418 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
2419 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
2422 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2423 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2424 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
2426 // If the comparison constant has bits in the upper part, the
2427 // zero-extended value could never match.
2428 if (C1 & (~0ULL << InSize)) {
2429 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
2433 case ISD::SETEQ: return DAG.getConstant(0, VT);
2436 case ISD::SETNE: return DAG.getConstant(1, VT);
2439 // True if the sign bit of C1 is set.
2440 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
2443 // True if the sign bit of C1 isn't set.
2444 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
2450 // Otherwise, we can perform the comparison with the low bits.
2458 return DAG.getSetCC(VT, N0.getOperand(0),
2459 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
2462 break; // todo, be more careful with signed comparisons
2464 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2465 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2466 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2467 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
2468 MVT::ValueType ExtDstTy = N0.getValueType();
2469 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
2471 // If the extended part has any inconsistent bits, it cannot ever
2472 // compare equal. In other words, they have to be all ones or all
2475 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
2476 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
2477 return DAG.getConstant(Cond == ISD::SETNE, VT);
2480 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
2481 if (Op0Ty == ExtSrcTy) {
2482 ZextOp = N0.getOperand(0);
2484 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
2485 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
2486 DAG.getConstant(Imm, Op0Ty));
2488 WorkList.push_back(ZextOp.Val);
2489 // Otherwise, make this a use of a zext.
2490 return DAG.getSetCC(VT, ZextOp,
2491 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
2494 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
2495 (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2496 (N0.getOpcode() == ISD::XOR ||
2497 (N0.getOpcode() == ISD::AND &&
2498 N0.getOperand(0).getOpcode() == ISD::XOR &&
2499 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2500 isa<ConstantSDNode>(N0.getOperand(1)) &&
2501 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
2502 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can
2503 // only do this if the top bits are known zero.
2504 if (TLI.MaskedValueIsZero(N1,
2505 MVT::getIntVTBitMask(N0.getValueType())-1)) {
2506 // Okay, get the un-inverted input value.
2508 if (N0.getOpcode() == ISD::XOR)
2509 Val = N0.getOperand(0);
2511 assert(N0.getOpcode() == ISD::AND &&
2512 N0.getOperand(0).getOpcode() == ISD::XOR);
2513 // ((X^1)&1)^1 -> X & 1
2514 Val = DAG.getNode(ISD::AND, N0.getValueType(),
2515 N0.getOperand(0).getOperand(0), N0.getOperand(1));
2517 return DAG.getSetCC(VT, Val, N1,
2518 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2522 uint64_t MinVal, MaxVal;
2523 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
2524 if (ISD::isSignedIntSetCC(Cond)) {
2525 MinVal = 1ULL << (OperandBitSize-1);
2526 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
2527 MaxVal = ~0ULL >> (65-OperandBitSize);
2532 MaxVal = ~0ULL >> (64-OperandBitSize);
2535 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2536 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2537 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2538 --C1; // X >= C0 --> X > (C0-1)
2539 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2540 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2543 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2544 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2545 ++C1; // X <= C0 --> X < (C0+1)
2546 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2547 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2550 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2551 return DAG.getConstant(0, VT); // X < MIN --> false
2553 // Canonicalize setgt X, Min --> setne X, Min
2554 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2555 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
2556 // Canonicalize setlt X, Max --> setne X, Max
2557 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2558 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
2560 // If we have setult X, 1, turn it into seteq X, 0
2561 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2562 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
2564 // If we have setugt X, Max-1, turn it into seteq X, Max
2565 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2566 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
2569 // If we have "setcc X, C0", check to see if we can shrink the immediate
2572 // SETUGT X, SINTMAX -> SETLT X, 0
2573 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
2574 C1 == (~0ULL >> (65-OperandBitSize)))
2575 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
2578 // FIXME: Implement the rest of these.
2580 // Fold bit comparisons when we can.
2581 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2582 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
2583 if (ConstantSDNode *AndRHS =
2584 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2585 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2586 // Perform the xform if the AND RHS is a single bit.
2587 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
2588 return DAG.getNode(ISD::SRL, VT, N0,
2589 DAG.getConstant(Log2_64(AndRHS->getValue()),
2590 TLI.getShiftAmountTy()));
2592 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
2593 // (X & 8) == 8 --> (X & 8) >> 3
2594 // Perform the xform if C1 is a single bit.
2595 if ((C1 & (C1-1)) == 0) {
2596 return DAG.getNode(ISD::SRL, VT, N0,
2597 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
2602 } else if (isa<ConstantSDNode>(N0.Val)) {
2603 // Ensure that the constant occurs on the RHS.
2604 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2607 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
2608 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
2609 double C0 = N0C->getValue(), C1 = N1C->getValue();
2612 default: break; // FIXME: Implement the rest of these!
2613 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
2614 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
2615 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
2616 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
2617 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
2618 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
2621 // Ensure that the constant occurs on the RHS.
2622 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2626 // We can always fold X == Y for integer setcc's.
2627 if (MVT::isInteger(N0.getValueType()))
2628 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2629 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2630 if (UOF == 2) // FP operators that are undefined on NaNs.
2631 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2632 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2633 return DAG.getConstant(UOF, VT);
2634 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2635 // if it is not already.
2636 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2637 if (NewCond != Cond)
2638 return DAG.getSetCC(VT, N0, N1, NewCond);
2641 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2642 MVT::isInteger(N0.getValueType())) {
2643 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2644 N0.getOpcode() == ISD::XOR) {
2645 // Simplify (X+Y) == (X+Z) --> Y == Z
2646 if (N0.getOpcode() == N1.getOpcode()) {
2647 if (N0.getOperand(0) == N1.getOperand(0))
2648 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
2649 if (N0.getOperand(1) == N1.getOperand(1))
2650 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
2651 if (isCommutativeBinOp(N0.getOpcode())) {
2652 // If X op Y == Y op X, try other combinations.
2653 if (N0.getOperand(0) == N1.getOperand(1))
2654 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
2655 if (N0.getOperand(1) == N1.getOperand(0))
2656 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
2660 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2661 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2662 // Turn (X+C1) == C2 --> X == C2-C1
2663 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
2664 return DAG.getSetCC(VT, N0.getOperand(0),
2665 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
2666 N0.getValueType()), Cond);
2669 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2670 if (N0.getOpcode() == ISD::XOR)
2671 // If we know that all of the inverted bits are zero, don't bother
2672 // performing the inversion.
2673 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
2674 return DAG.getSetCC(VT, N0.getOperand(0),
2675 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
2676 N0.getValueType()), Cond);
2679 // Turn (C1-X) == C2 --> X == C1-C2
2680 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2681 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
2682 return DAG.getSetCC(VT, N0.getOperand(1),
2683 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
2684 N0.getValueType()), Cond);
2689 // Simplify (X+Z) == X --> Z == 0
2690 if (N0.getOperand(0) == N1)
2691 return DAG.getSetCC(VT, N0.getOperand(1),
2692 DAG.getConstant(0, N0.getValueType()), Cond);
2693 if (N0.getOperand(1) == N1) {
2694 if (isCommutativeBinOp(N0.getOpcode()))
2695 return DAG.getSetCC(VT, N0.getOperand(0),
2696 DAG.getConstant(0, N0.getValueType()), Cond);
2698 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2699 // (Z-X) == X --> Z == X<<1
2700 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
2702 DAG.getConstant(1,TLI.getShiftAmountTy()));
2703 WorkList.push_back(SH.Val);
2704 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
2709 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2710 N1.getOpcode() == ISD::XOR) {
2711 // Simplify X == (X+Z) --> Z == 0
2712 if (N1.getOperand(0) == N0) {
2713 return DAG.getSetCC(VT, N1.getOperand(1),
2714 DAG.getConstant(0, N1.getValueType()), Cond);
2715 } else if (N1.getOperand(1) == N0) {
2716 if (isCommutativeBinOp(N1.getOpcode())) {
2717 return DAG.getSetCC(VT, N1.getOperand(0),
2718 DAG.getConstant(0, N1.getValueType()), Cond);
2720 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2721 // X == (Z-X) --> X<<1 == Z
2722 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
2723 DAG.getConstant(1,TLI.getShiftAmountTy()));
2724 WorkList.push_back(SH.Val);
2725 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
2731 // Fold away ALL boolean setcc's.
2733 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2735 default: assert(0 && "Unknown integer setcc!");
2736 case ISD::SETEQ: // X == Y -> (X^Y)^1
2737 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2738 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
2739 WorkList.push_back(Temp.Val);
2741 case ISD::SETNE: // X != Y --> (X^Y)
2742 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2744 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
2745 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
2746 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2747 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
2748 WorkList.push_back(Temp.Val);
2750 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
2751 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
2752 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2753 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
2754 WorkList.push_back(Temp.Val);
2756 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
2757 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
2758 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2759 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
2760 WorkList.push_back(Temp.Val);
2762 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
2763 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
2764 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2765 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
2768 if (VT != MVT::i1) {
2769 WorkList.push_back(N0.Val);
2770 // FIXME: If running after legalize, we probably can't do this.
2771 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2776 // Could not fold it.
2780 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2781 /// return a DAG expression to select that will generate the same value by
2782 /// multiplying by a magic number. See:
2783 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2784 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
2785 MVT::ValueType VT = N->getValueType(0);
2787 // Check to see if we can do this.
2788 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
2789 return SDOperand(); // BuildSDIV only operates on i32 or i64
2790 if (!TLI.isOperationLegal(ISD::MULHS, VT))
2791 return SDOperand(); // Make sure the target supports MULHS.
2793 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
2794 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
2796 // Multiply the numerator (operand 0) by the magic value
2797 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
2798 DAG.getConstant(magics.m, VT));
2799 // If d > 0 and m < 0, add the numerator
2800 if (d > 0 && magics.m < 0) {
2801 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
2802 WorkList.push_back(Q.Val);
2804 // If d < 0 and m > 0, subtract the numerator.
2805 if (d < 0 && magics.m > 0) {
2806 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
2807 WorkList.push_back(Q.Val);
2809 // Shift right algebraic if shift value is nonzero
2811 Q = DAG.getNode(ISD::SRA, VT, Q,
2812 DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
2813 WorkList.push_back(Q.Val);
2815 // Extract the sign bit and add it to the quotient
2817 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1,
2818 TLI.getShiftAmountTy()));
2819 WorkList.push_back(T.Val);
2820 return DAG.getNode(ISD::ADD, VT, Q, T);
2823 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2824 /// return a DAG expression to select that will generate the same value by
2825 /// multiplying by a magic number. See:
2826 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2827 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
2828 MVT::ValueType VT = N->getValueType(0);
2830 // Check to see if we can do this.
2831 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
2832 return SDOperand(); // BuildUDIV only operates on i32 or i64
2833 if (!TLI.isOperationLegal(ISD::MULHU, VT))
2834 return SDOperand(); // Make sure the target supports MULHU.
2836 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
2837 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
2839 // Multiply the numerator (operand 0) by the magic value
2840 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
2841 DAG.getConstant(magics.m, VT));
2842 WorkList.push_back(Q.Val);
2844 if (magics.a == 0) {
2845 return DAG.getNode(ISD::SRL, VT, Q,
2846 DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
2848 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
2849 WorkList.push_back(NPQ.Val);
2850 NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
2851 DAG.getConstant(1, TLI.getShiftAmountTy()));
2852 WorkList.push_back(NPQ.Val);
2853 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
2854 WorkList.push_back(NPQ.Val);
2855 return DAG.getNode(ISD::SRL, VT, NPQ,
2856 DAG.getConstant(magics.s-1, TLI.getShiftAmountTy()));
2860 // SelectionDAG::Combine - This is the entry point for the file.
2862 void SelectionDAG::Combine(bool RunningAfterLegalize) {
2863 /// run - This is the main entry point to this class.
2865 DAGCombiner(*this).Run(RunningAfterLegalize);