1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: Should add a corresponding version of fold AND with
20 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which
23 // FIXME: select C, pow2, pow2 -> something smart
24 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
25 // FIXME: Dead stores -> nuke
26 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
27 // FIXME: mul (x, const) -> shifts + adds
28 // FIXME: undef values
29 // FIXME: make truncate see through SIGN_EXTEND and AND
30 // FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2)
31 // FIXME: verify that getNode can't return extends with an operand whose type
32 // is >= to that of the extend.
33 // FIXME: divide by zero is currently left unfolded. do we want to turn this
35 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
36 // FIXME: reassociate (X+C)+Y into (X+Y)+C if the inner expression has one use
38 //===----------------------------------------------------------------------===//
40 #define DEBUG_TYPE "dagcombine"
41 #include "llvm/ADT/Statistic.h"
42 #include "llvm/CodeGen/SelectionDAG.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Target/TargetLowering.h"
51 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined");
58 // Worklist of all of the nodes that need to be simplified.
59 std::vector<SDNode*> WorkList;
61 /// AddUsersToWorkList - When an instruction is simplified, add all users of
62 /// the instruction to the work lists because they might get more simplified
65 void AddUsersToWorkList(SDNode *N) {
66 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
68 WorkList.push_back(*UI);
71 /// removeFromWorkList - remove all instances of N from the worklist.
72 void removeFromWorkList(SDNode *N) {
73 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
77 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
79 DEBUG(std::cerr << "\nReplacing "; N->dump();
80 std::cerr << "\nWith: "; To[0].Val->dump();
81 std::cerr << " and " << To.size()-1 << " other values\n");
82 std::vector<SDNode*> NowDead;
83 DAG.ReplaceAllUsesWith(N, To, &NowDead);
85 // Push the new nodes and any users onto the worklist
86 for (unsigned i = 0, e = To.size(); i != e; ++i) {
87 WorkList.push_back(To[i].Val);
88 AddUsersToWorkList(To[i].Val);
91 // Nodes can end up on the worklist more than once. Make sure we do
92 // not process a node that has been replaced.
93 removeFromWorkList(N);
94 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
95 removeFromWorkList(NowDead[i]);
97 // Finally, since the node is now dead, remove it from the graph.
99 return SDOperand(N, 0);
102 SDOperand CombineTo(SDNode *N, SDOperand Res) {
103 std::vector<SDOperand> To;
105 return CombineTo(N, To);
108 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
109 std::vector<SDOperand> To;
112 return CombineTo(N, To);
115 /// visit - call the node-specific routine that knows how to fold each
116 /// particular type of node.
117 SDOperand visit(SDNode *N);
119 // Visitation implementation - Implement dag node combining for different
120 // node types. The semantics are as follows:
122 // SDOperand.Val == 0 - No change was made
123 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
124 // otherwise - N should be replaced by the returned Operand.
126 SDOperand visitTokenFactor(SDNode *N);
127 SDOperand visitADD(SDNode *N);
128 SDOperand visitSUB(SDNode *N);
129 SDOperand visitMUL(SDNode *N);
130 SDOperand visitSDIV(SDNode *N);
131 SDOperand visitUDIV(SDNode *N);
132 SDOperand visitSREM(SDNode *N);
133 SDOperand visitUREM(SDNode *N);
134 SDOperand visitMULHU(SDNode *N);
135 SDOperand visitMULHS(SDNode *N);
136 SDOperand visitAND(SDNode *N);
137 SDOperand visitOR(SDNode *N);
138 SDOperand visitXOR(SDNode *N);
139 SDOperand visitSHL(SDNode *N);
140 SDOperand visitSRA(SDNode *N);
141 SDOperand visitSRL(SDNode *N);
142 SDOperand visitCTLZ(SDNode *N);
143 SDOperand visitCTTZ(SDNode *N);
144 SDOperand visitCTPOP(SDNode *N);
145 SDOperand visitSELECT(SDNode *N);
146 SDOperand visitSELECT_CC(SDNode *N);
147 SDOperand visitSETCC(SDNode *N);
148 SDOperand visitADD_PARTS(SDNode *N);
149 SDOperand visitSUB_PARTS(SDNode *N);
150 SDOperand visitSIGN_EXTEND(SDNode *N);
151 SDOperand visitZERO_EXTEND(SDNode *N);
152 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
153 SDOperand visitTRUNCATE(SDNode *N);
155 SDOperand visitFADD(SDNode *N);
156 SDOperand visitFSUB(SDNode *N);
157 SDOperand visitFMUL(SDNode *N);
158 SDOperand visitFDIV(SDNode *N);
159 SDOperand visitFREM(SDNode *N);
160 SDOperand visitSINT_TO_FP(SDNode *N);
161 SDOperand visitUINT_TO_FP(SDNode *N);
162 SDOperand visitFP_TO_SINT(SDNode *N);
163 SDOperand visitFP_TO_UINT(SDNode *N);
164 SDOperand visitFP_ROUND(SDNode *N);
165 SDOperand visitFP_ROUND_INREG(SDNode *N);
166 SDOperand visitFP_EXTEND(SDNode *N);
167 SDOperand visitFNEG(SDNode *N);
168 SDOperand visitFABS(SDNode *N);
169 SDOperand visitBRCOND(SDNode *N);
170 SDOperand visitBRCONDTWOWAY(SDNode *N);
171 SDOperand visitBR_CC(SDNode *N);
172 SDOperand visitBRTWOWAY_CC(SDNode *N);
174 SDOperand visitLOAD(SDNode *N);
175 SDOperand visitSTORE(SDNode *N);
177 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
178 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
179 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
180 SDOperand N3, ISD::CondCode CC);
181 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
182 ISD::CondCode Cond, bool foldBooleans = true);
184 DAGCombiner(SelectionDAG &D)
185 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
187 /// Run - runs the dag combiner on all nodes in the work list
188 void Run(bool RunningAfterLegalize);
192 /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We use
193 /// this predicate to simplify operations downstream. Op and Mask are known to
194 /// be the same type.
195 static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
196 const TargetLowering &TLI) {
198 if (Mask == 0) return true;
200 // If we know the result of a setcc has the top bits zero, use this info.
201 switch (Op.getOpcode()) {
203 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
205 return ((Mask & 1) == 0) &&
206 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
208 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
209 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
210 case ISD::ZERO_EXTEND:
211 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
212 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI);
213 case ISD::AssertZext:
214 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
215 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
217 // If either of the operands has zero bits, the result will too.
218 if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) ||
219 MaskedValueIsZero(Op.getOperand(0), Mask, TLI))
221 // (X & C1) & C2 == 0 iff C1 & C2 == 0.
222 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
223 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
227 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
228 MaskedValueIsZero(Op.getOperand(1), Mask, TLI);
230 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) &&
231 MaskedValueIsZero(Op.getOperand(2), Mask, TLI);
233 return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) &&
234 MaskedValueIsZero(Op.getOperand(3), Mask, TLI);
236 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0
237 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
238 uint64_t NewVal = Mask << ShAmt->getValue();
239 SrcBits = MVT::getSizeInBits(Op.getValueType());
240 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
241 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
245 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0
246 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
247 uint64_t NewVal = Mask >> ShAmt->getValue();
248 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
252 // (add X, Y) & C == 0 iff (X&C)|(Y&C) == 0 and all bits are low bits.
253 if ((Mask&(Mask+1)) == 0) { // All low bits
254 if (MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
255 MaskedValueIsZero(Op.getOperand(1), Mask, TLI))
260 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
261 // We know that the top bits of C-X are clear if X contains less bits
262 // than C (i.e. no wrap-around can happen). For example, 20-X is
263 // positive if we can prove that X is >= 0 and < 16.
264 unsigned Bits = MVT::getSizeInBits(CLHS->getValueType(0));
265 if ((CLHS->getValue() & (1 << (Bits-1))) == 0) { // sign bit clear
266 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1);
267 uint64_t MaskV = (1ULL << (63-NLZ))-1;
268 if (MaskedValueIsZero(Op.getOperand(1), ~MaskV, TLI)) {
269 // High bits are clear this value is known to be >= C.
270 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue());
271 if ((Mask & ((1ULL << (64-NLZ2))-1)) == 0)
280 // Bit counting instructions can not set the high bits of the result
281 // register. The max number of bits sets depends on the input.
282 return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
288 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
289 // that selects between the values 1 and 0, making it equivalent to a setcc.
290 // Also, set the incoming LHS, RHS, and CC references to the appropriate
291 // nodes based on the type of node we are checking. This simplifies life a
292 // bit for the callers.
293 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
295 if (N.getOpcode() == ISD::SETCC) {
296 LHS = N.getOperand(0);
297 RHS = N.getOperand(1);
298 CC = N.getOperand(2);
301 if (N.getOpcode() == ISD::SELECT_CC &&
302 N.getOperand(2).getOpcode() == ISD::Constant &&
303 N.getOperand(3).getOpcode() == ISD::Constant &&
304 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
305 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
306 LHS = N.getOperand(0);
307 RHS = N.getOperand(1);
308 CC = N.getOperand(4);
314 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
315 // one use. If this is true, it allows the users to invert the operation for
316 // free when it is profitable to do so.
317 static bool isOneUseSetCC(SDOperand N) {
318 SDOperand N0, N1, N2;
319 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
324 // FIXME: This should probably go in the ISD class rather than being duplicated
326 static bool isCommutativeBinOp(unsigned Opcode) {
332 case ISD::XOR: return true;
333 default: return false; // FIXME: Need commutative info for user ops!
337 void DAGCombiner::Run(bool RunningAfterLegalize) {
338 // set the instance variable, so that the various visit routines may use it.
339 AfterLegalize = RunningAfterLegalize;
341 // Add all the dag nodes to the worklist.
342 WorkList.insert(WorkList.end(), DAG.allnodes_begin(), DAG.allnodes_end());
344 // Create a dummy node (which is not added to allnodes), that adds a reference
345 // to the root node, preventing it from being deleted, and tracking any
346 // changes of the root.
347 HandleSDNode Dummy(DAG.getRoot());
349 // while the worklist isn't empty, inspect the node on the end of it and
350 // try and combine it.
351 while (!WorkList.empty()) {
352 SDNode *N = WorkList.back();
355 // If N has no uses, it is dead. Make sure to revisit all N's operands once
356 // N is deleted from the DAG, since they too may now be dead or may have a
357 // reduced number of uses, allowing other xforms.
358 if (N->use_empty() && N != &Dummy) {
359 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
360 WorkList.push_back(N->getOperand(i).Val);
362 removeFromWorkList(N);
367 SDOperand RV = visit(N);
370 // If we get back the same node we passed in, rather than a new node or
371 // zero, we know that the node must have defined multiple values and
372 // CombineTo was used. Since CombineTo takes care of the worklist
373 // mechanics for us, we have no work to do in this case.
375 DEBUG(std::cerr << "\nReplacing "; N->dump();
376 std::cerr << "\nWith: "; RV.Val->dump();
378 std::vector<SDNode*> NowDead;
379 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead);
381 // Push the new node and any users onto the worklist
382 WorkList.push_back(RV.Val);
383 AddUsersToWorkList(RV.Val);
385 // Nodes can end up on the worklist more than once. Make sure we do
386 // not process a node that has been replaced.
387 removeFromWorkList(N);
388 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
389 removeFromWorkList(NowDead[i]);
391 // Finally, since the node is now dead, remove it from the graph.
397 // If the root changed (e.g. it was a dead load, update the root).
398 DAG.setRoot(Dummy.getValue());
401 SDOperand DAGCombiner::visit(SDNode *N) {
402 switch(N->getOpcode()) {
404 case ISD::TokenFactor: return visitTokenFactor(N);
405 case ISD::ADD: return visitADD(N);
406 case ISD::SUB: return visitSUB(N);
407 case ISD::MUL: return visitMUL(N);
408 case ISD::SDIV: return visitSDIV(N);
409 case ISD::UDIV: return visitUDIV(N);
410 case ISD::SREM: return visitSREM(N);
411 case ISD::UREM: return visitUREM(N);
412 case ISD::MULHU: return visitMULHU(N);
413 case ISD::MULHS: return visitMULHS(N);
414 case ISD::AND: return visitAND(N);
415 case ISD::OR: return visitOR(N);
416 case ISD::XOR: return visitXOR(N);
417 case ISD::SHL: return visitSHL(N);
418 case ISD::SRA: return visitSRA(N);
419 case ISD::SRL: return visitSRL(N);
420 case ISD::CTLZ: return visitCTLZ(N);
421 case ISD::CTTZ: return visitCTTZ(N);
422 case ISD::CTPOP: return visitCTPOP(N);
423 case ISD::SELECT: return visitSELECT(N);
424 case ISD::SELECT_CC: return visitSELECT_CC(N);
425 case ISD::SETCC: return visitSETCC(N);
426 case ISD::ADD_PARTS: return visitADD_PARTS(N);
427 case ISD::SUB_PARTS: return visitSUB_PARTS(N);
428 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
429 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
430 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
431 case ISD::TRUNCATE: return visitTRUNCATE(N);
432 case ISD::FADD: return visitFADD(N);
433 case ISD::FSUB: return visitFSUB(N);
434 case ISD::FMUL: return visitFMUL(N);
435 case ISD::FDIV: return visitFDIV(N);
436 case ISD::FREM: return visitFREM(N);
437 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
438 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
439 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
440 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
441 case ISD::FP_ROUND: return visitFP_ROUND(N);
442 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
443 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
444 case ISD::FNEG: return visitFNEG(N);
445 case ISD::FABS: return visitFABS(N);
446 case ISD::BRCOND: return visitBRCOND(N);
447 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N);
448 case ISD::BR_CC: return visitBR_CC(N);
449 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N);
450 case ISD::LOAD: return visitLOAD(N);
451 case ISD::STORE: return visitSTORE(N);
456 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
457 std::vector<SDOperand> Ops;
458 bool Changed = false;
460 // If the token factor has two operands and one is the entry token, replace
461 // the token factor with the other operand.
462 if (N->getNumOperands() == 2) {
463 if (N->getOperand(0).getOpcode() == ISD::EntryToken)
464 return N->getOperand(1);
465 if (N->getOperand(1).getOpcode() == ISD::EntryToken)
466 return N->getOperand(0);
469 // fold (tokenfactor (tokenfactor)) -> tokenfactor
470 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
471 SDOperand Op = N->getOperand(i);
472 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) {
474 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j)
475 Ops.push_back(Op.getOperand(j));
481 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
485 SDOperand DAGCombiner::visitADD(SDNode *N) {
486 SDOperand N0 = N->getOperand(0);
487 SDOperand N1 = N->getOperand(1);
488 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
489 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
490 MVT::ValueType VT = N0.getValueType();
492 // fold (add c1, c2) -> c1+c2
494 return DAG.getConstant(N0C->getValue() + N1C->getValue(), VT);
495 // canonicalize constant to RHS
497 return DAG.getNode(ISD::ADD, VT, N1, N0);
498 // fold (add x, 0) -> x
499 if (N1C && N1C->isNullValue())
501 // fold (add (add x, c1), c2) -> (add x, c1+c2)
502 if (N1C && N0.getOpcode() == ISD::ADD) {
503 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
504 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
506 return DAG.getNode(ISD::ADD, VT, N0.getOperand(1),
507 DAG.getConstant(N1C->getValue()+N00C->getValue(), VT));
509 return DAG.getNode(ISD::ADD, VT, N0.getOperand(0),
510 DAG.getConstant(N1C->getValue()+N01C->getValue(), VT));
512 // fold ((0-A) + B) -> B-A
513 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
514 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
515 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
516 // fold (A + (0-B)) -> A-B
517 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
518 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
519 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
520 // fold (A+(B-A)) -> B
521 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
522 return N1.getOperand(0);
526 SDOperand DAGCombiner::visitSUB(SDNode *N) {
527 SDOperand N0 = N->getOperand(0);
528 SDOperand N1 = N->getOperand(1);
529 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
530 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
532 // fold (sub x, x) -> 0
534 return DAG.getConstant(0, N->getValueType(0));
536 // fold (sub c1, c2) -> c1-c2
538 return DAG.getConstant(N0C->getValue() - N1C->getValue(),
540 // fold (sub x, c) -> (add x, -c)
542 return DAG.getNode(ISD::ADD, N0.getValueType(), N0,
543 DAG.getConstant(-N1C->getValue(), N0.getValueType()));
546 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
547 return N0.getOperand(1);
549 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
550 return N0.getOperand(0);
554 SDOperand DAGCombiner::visitMUL(SDNode *N) {
555 SDOperand N0 = N->getOperand(0);
556 SDOperand N1 = N->getOperand(1);
557 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
558 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
559 MVT::ValueType VT = N0.getValueType();
561 // fold (mul c1, c2) -> c1*c2
563 return DAG.getConstant(N0C->getValue() * N1C->getValue(),
565 // canonicalize constant to RHS
567 return DAG.getNode(ISD::MUL, VT, N1, N0);
568 // fold (mul x, 0) -> 0
569 if (N1C && N1C->isNullValue())
571 // fold (mul x, -1) -> 0-x
572 if (N1C && N1C->isAllOnesValue())
573 return DAG.getNode(ISD::SUB, N->getValueType(0),
574 DAG.getConstant(0, N->getValueType(0)), N0);
575 // fold (mul x, (1 << c)) -> x << c
576 if (N1C && isPowerOf2_64(N1C->getValue()))
577 return DAG.getNode(ISD::SHL, N->getValueType(0), N0,
578 DAG.getConstant(Log2_64(N1C->getValue()),
579 TLI.getShiftAmountTy()));
580 // fold (mul (mul x, c1), c2) -> (mul x, c1*c2)
581 if (N1C && N0.getOpcode() == ISD::MUL) {
582 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
583 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
585 return DAG.getNode(ISD::MUL, VT, N0.getOperand(1),
586 DAG.getConstant(N1C->getValue()*N00C->getValue(), VT));
588 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0),
589 DAG.getConstant(N1C->getValue()*N01C->getValue(), VT));
594 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
595 SDOperand N0 = N->getOperand(0);
596 SDOperand N1 = N->getOperand(1);
597 MVT::ValueType VT = N->getValueType(0);
598 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
599 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
601 // fold (sdiv c1, c2) -> c1/c2
602 if (N0C && N1C && !N1C->isNullValue())
603 return DAG.getConstant(N0C->getSignExtended() / N1C->getSignExtended(),
605 // If we know the sign bits of both operands are zero, strength reduce to a
606 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
607 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
608 if (MaskedValueIsZero(N1, SignBit, TLI) &&
609 MaskedValueIsZero(N0, SignBit, TLI))
610 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
614 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
615 SDOperand N0 = N->getOperand(0);
616 SDOperand N1 = N->getOperand(1);
617 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
618 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
620 // fold (udiv c1, c2) -> c1/c2
621 if (N0C && N1C && !N1C->isNullValue())
622 return DAG.getConstant(N0C->getValue() / N1C->getValue(),
624 // fold (udiv x, (1 << c)) -> x >>u c
625 if (N1C && isPowerOf2_64(N1C->getValue()))
626 return DAG.getNode(ISD::SRL, N->getValueType(0), N0,
627 DAG.getConstant(Log2_64(N1C->getValue()),
628 TLI.getShiftAmountTy()));
632 SDOperand DAGCombiner::visitSREM(SDNode *N) {
633 SDOperand N0 = N->getOperand(0);
634 SDOperand N1 = N->getOperand(1);
635 MVT::ValueType VT = N->getValueType(0);
636 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
637 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
639 // fold (srem c1, c2) -> c1%c2
640 if (N0C && N1C && !N1C->isNullValue())
641 return DAG.getConstant(N0C->getSignExtended() % N1C->getSignExtended(),
643 // If we know the sign bits of both operands are zero, strength reduce to a
644 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
645 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
646 if (MaskedValueIsZero(N1, SignBit, TLI) &&
647 MaskedValueIsZero(N0, SignBit, TLI))
648 return DAG.getNode(ISD::UREM, N1.getValueType(), N0, N1);
652 SDOperand DAGCombiner::visitUREM(SDNode *N) {
653 SDOperand N0 = N->getOperand(0);
654 SDOperand N1 = N->getOperand(1);
655 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
656 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
658 // fold (urem c1, c2) -> c1%c2
659 if (N0C && N1C && !N1C->isNullValue())
660 return DAG.getConstant(N0C->getValue() % N1C->getValue(),
662 // fold (urem x, pow2) -> (and x, pow2-1)
663 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
664 return DAG.getNode(ISD::AND, N0.getValueType(), N0,
665 DAG.getConstant(N1C->getValue()-1, N1.getValueType()));
669 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
670 SDOperand N0 = N->getOperand(0);
671 SDOperand N1 = N->getOperand(1);
672 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
674 // fold (mulhs x, 0) -> 0
675 if (N1C && N1C->isNullValue())
677 // fold (mulhs x, 1) -> (sra x, size(x)-1)
678 if (N1C && N1C->getValue() == 1)
679 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
680 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
681 TLI.getShiftAmountTy()));
685 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
686 SDOperand N0 = N->getOperand(0);
687 SDOperand N1 = N->getOperand(1);
688 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
690 // fold (mulhu x, 0) -> 0
691 if (N1C && N1C->isNullValue())
693 // fold (mulhu x, 1) -> 0
694 if (N1C && N1C->getValue() == 1)
695 return DAG.getConstant(0, N0.getValueType());
699 SDOperand DAGCombiner::visitAND(SDNode *N) {
700 SDOperand N0 = N->getOperand(0);
701 SDOperand N1 = N->getOperand(1);
702 SDOperand LL, LR, RL, RR, CC0, CC1;
703 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
704 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
705 MVT::ValueType VT = N1.getValueType();
706 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
708 // fold (and c1, c2) -> c1&c2
710 return DAG.getConstant(N0C->getValue() & N1C->getValue(), VT);
711 // canonicalize constant to RHS
713 return DAG.getNode(ISD::AND, VT, N1, N0);
714 // fold (and x, -1) -> x
715 if (N1C && N1C->isAllOnesValue())
717 // if (and x, c) is known to be zero, return 0
718 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
719 return DAG.getConstant(0, VT);
720 // fold (and x, c) -> x iff (x & ~c) == 0
721 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)),
724 // fold (and (and x, c1), c2) -> (and x, c1^c2)
725 if (N1C && N0.getOpcode() == ISD::AND) {
726 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
727 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
729 return DAG.getNode(ISD::AND, VT, N0.getOperand(1),
730 DAG.getConstant(N1C->getValue()&N00C->getValue(), VT));
732 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
733 DAG.getConstant(N1C->getValue()&N01C->getValue(), VT));
735 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
736 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
737 unsigned ExtendBits =
738 MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT());
739 if ((N1C->getValue() & (~0ULL << ExtendBits)) == 0)
740 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1);
742 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
743 if (N0.getOpcode() == ISD::OR && N1C)
744 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
745 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
747 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
748 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
749 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
750 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
752 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
753 MVT::isInteger(LL.getValueType())) {
754 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
755 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
756 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
757 WorkList.push_back(ORNode.Val);
758 return DAG.getSetCC(VT, ORNode, LR, Op1);
760 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
761 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
762 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
763 WorkList.push_back(ANDNode.Val);
764 return DAG.getSetCC(VT, ANDNode, LR, Op1);
766 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
767 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
768 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
769 WorkList.push_back(ORNode.Val);
770 return DAG.getSetCC(VT, ORNode, LR, Op1);
773 // canonicalize equivalent to ll == rl
774 if (LL == RR && LR == RL) {
775 Op1 = ISD::getSetCCSwappedOperands(Op1);
778 if (LL == RL && LR == RR) {
779 bool isInteger = MVT::isInteger(LL.getValueType());
780 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
781 if (Result != ISD::SETCC_INVALID)
782 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
785 // fold (and (zext x), (zext y)) -> (zext (and x, y))
786 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
787 N1.getOpcode() == ISD::ZERO_EXTEND &&
788 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
789 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
790 N0.getOperand(0), N1.getOperand(0));
791 WorkList.push_back(ANDNode.Val);
792 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode);
794 // fold (and (shl/srl x), (shl/srl y)) -> (shl/srl (and x, y))
795 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
796 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL)) &&
797 N0.getOperand(1) == N1.getOperand(1)) {
798 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
799 N0.getOperand(0), N1.getOperand(0));
800 WorkList.push_back(ANDNode.Val);
801 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
803 // fold (and (sra)) -> (and (srl)) when possible.
804 if (N0.getOpcode() == ISD::SRA && N0.Val->hasOneUse())
805 if (ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
806 // If the RHS of the AND has zeros where the sign bits of the SRA will
807 // land, turn the SRA into an SRL.
808 if (MaskedValueIsZero(N1, (~0ULL << (OpSizeInBits-N01C->getValue())) &
809 (~0ULL>>(64-OpSizeInBits)), TLI)) {
810 WorkList.push_back(N);
811 CombineTo(N0.Val, DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
817 // fold (zext_inreg (extload x)) -> (zextload x)
818 if (N0.getOpcode() == ISD::EXTLOAD) {
819 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
820 // If we zero all the possible extended bits, then we can turn this into
821 // a zextload if we are running before legalize or the operation is legal.
822 if (MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT), TLI) &&
823 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
824 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
825 N0.getOperand(1), N0.getOperand(2),
827 WorkList.push_back(N);
828 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
832 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
833 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) {
834 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
835 // If we zero all the possible extended bits, then we can turn this into
836 // a zextload if we are running before legalize or the operation is legal.
837 if (MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT), TLI) &&
838 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
839 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
840 N0.getOperand(1), N0.getOperand(2),
842 WorkList.push_back(N);
843 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
850 SDOperand DAGCombiner::visitOR(SDNode *N) {
851 SDOperand N0 = N->getOperand(0);
852 SDOperand N1 = N->getOperand(1);
853 SDOperand LL, LR, RL, RR, CC0, CC1;
854 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
855 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
856 MVT::ValueType VT = N1.getValueType();
857 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
859 // fold (or c1, c2) -> c1|c2
861 return DAG.getConstant(N0C->getValue() | N1C->getValue(),
863 // canonicalize constant to RHS
865 return DAG.getNode(ISD::OR, VT, N1, N0);
866 // fold (or x, 0) -> x
867 if (N1C && N1C->isNullValue())
869 // fold (or x, -1) -> -1
870 if (N1C && N1C->isAllOnesValue())
872 // fold (or x, c) -> c iff (x & ~c) == 0
873 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)),
876 // fold (or (or x, c1), c2) -> (or x, c1|c2)
877 if (N1C && N0.getOpcode() == ISD::OR) {
878 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
879 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
881 return DAG.getNode(ISD::OR, VT, N0.getOperand(1),
882 DAG.getConstant(N1C->getValue()|N00C->getValue(), VT));
884 return DAG.getNode(ISD::OR, VT, N0.getOperand(0),
885 DAG.getConstant(N1C->getValue()|N01C->getValue(), VT));
887 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
888 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
889 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
890 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
892 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
893 MVT::isInteger(LL.getValueType())) {
894 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
895 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
896 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
897 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
898 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
899 WorkList.push_back(ORNode.Val);
900 return DAG.getSetCC(VT, ORNode, LR, Op1);
902 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
903 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
904 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
905 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
906 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
907 WorkList.push_back(ANDNode.Val);
908 return DAG.getSetCC(VT, ANDNode, LR, Op1);
911 // canonicalize equivalent to ll == rl
912 if (LL == RR && LR == RL) {
913 Op1 = ISD::getSetCCSwappedOperands(Op1);
916 if (LL == RL && LR == RR) {
917 bool isInteger = MVT::isInteger(LL.getValueType());
918 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
919 if (Result != ISD::SETCC_INVALID)
920 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
923 // fold (or (zext x), (zext y)) -> (zext (or x, y))
924 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
925 N1.getOpcode() == ISD::ZERO_EXTEND &&
926 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
927 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
928 N0.getOperand(0), N1.getOperand(0));
929 WorkList.push_back(ORNode.Val);
930 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode);
935 SDOperand DAGCombiner::visitXOR(SDNode *N) {
936 SDOperand N0 = N->getOperand(0);
937 SDOperand N1 = N->getOperand(1);
938 SDOperand LHS, RHS, CC;
939 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
940 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
941 MVT::ValueType VT = N0.getValueType();
943 // fold (xor c1, c2) -> c1^c2
945 return DAG.getConstant(N0C->getValue() ^ N1C->getValue(), VT);
946 // canonicalize constant to RHS
948 return DAG.getNode(ISD::XOR, VT, N1, N0);
949 // fold (xor x, 0) -> x
950 if (N1C && N1C->isNullValue())
952 // fold !(x cc y) -> (x !cc y)
953 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
954 bool isInt = MVT::isInteger(LHS.getValueType());
955 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
957 if (N0.getOpcode() == ISD::SETCC)
958 return DAG.getSetCC(VT, LHS, RHS, NotCC);
959 if (N0.getOpcode() == ISD::SELECT_CC)
960 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
961 assert(0 && "Unhandled SetCC Equivalent!");
964 // fold !(x or y) -> (!x and !y) iff x or y are setcc
965 if (N1C && N1C->getValue() == 1 &&
966 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
967 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
968 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
969 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
970 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
971 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
972 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
973 return DAG.getNode(NewOpcode, VT, LHS, RHS);
976 // fold !(x or y) -> (!x and !y) iff x or y are constants
977 if (N1C && N1C->isAllOnesValue() &&
978 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
979 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
980 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
981 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
982 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
983 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
984 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
985 return DAG.getNode(NewOpcode, VT, LHS, RHS);
988 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
989 if (N1C && N0.getOpcode() == ISD::XOR) {
990 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
991 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
993 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
994 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
996 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
997 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
999 // fold (xor x, x) -> 0
1001 return DAG.getConstant(0, VT);
1002 // fold (xor (zext x), (zext y)) -> (zext (xor x, y))
1003 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1004 N1.getOpcode() == ISD::ZERO_EXTEND &&
1005 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1006 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
1007 N0.getOperand(0), N1.getOperand(0));
1008 WorkList.push_back(XORNode.Val);
1009 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
1014 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1015 SDOperand N0 = N->getOperand(0);
1016 SDOperand N1 = N->getOperand(1);
1017 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1018 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1019 MVT::ValueType VT = N0.getValueType();
1020 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1022 // fold (shl c1, c2) -> c1<<c2
1024 return DAG.getConstant(N0C->getValue() << N1C->getValue(), VT);
1025 // fold (shl 0, x) -> 0
1026 if (N0C && N0C->isNullValue())
1028 // fold (shl x, c >= size(x)) -> undef
1029 if (N1C && N1C->getValue() >= OpSizeInBits)
1030 return DAG.getNode(ISD::UNDEF, VT);
1031 // fold (shl x, 0) -> x
1032 if (N1C && N1C->isNullValue())
1034 // if (shl x, c) is known to be zero, return 0
1035 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
1036 return DAG.getConstant(0, VT);
1037 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1038 if (N1C && N0.getOpcode() == ISD::SHL &&
1039 N0.getOperand(1).getOpcode() == ISD::Constant) {
1040 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1041 uint64_t c2 = N1C->getValue();
1042 if (c1 + c2 > OpSizeInBits)
1043 return DAG.getConstant(0, VT);
1044 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1045 DAG.getConstant(c1 + c2, N1.getValueType()));
1047 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1048 // (srl (and x, -1 << c1), c1-c2)
1049 if (N1C && N0.getOpcode() == ISD::SRL &&
1050 N0.getOperand(1).getOpcode() == ISD::Constant) {
1051 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1052 uint64_t c2 = N1C->getValue();
1053 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1054 DAG.getConstant(~0ULL << c1, VT));
1056 return DAG.getNode(ISD::SHL, VT, Mask,
1057 DAG.getConstant(c2-c1, N1.getValueType()));
1059 return DAG.getNode(ISD::SRL, VT, Mask,
1060 DAG.getConstant(c1-c2, N1.getValueType()));
1062 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1063 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1064 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1065 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1069 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1070 SDOperand N0 = N->getOperand(0);
1071 SDOperand N1 = N->getOperand(1);
1072 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1073 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1074 MVT::ValueType VT = N0.getValueType();
1075 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1077 // fold (sra c1, c2) -> c1>>c2
1079 return DAG.getConstant(N0C->getSignExtended() >> N1C->getValue(), VT);
1080 // fold (sra 0, x) -> 0
1081 if (N0C && N0C->isNullValue())
1083 // fold (sra -1, x) -> -1
1084 if (N0C && N0C->isAllOnesValue())
1086 // fold (sra x, c >= size(x)) -> undef
1087 if (N1C && N1C->getValue() >= OpSizeInBits)
1088 return DAG.getNode(ISD::UNDEF, VT);
1089 // fold (sra x, 0) -> x
1090 if (N1C && N1C->isNullValue())
1092 // If the sign bit is known to be zero, switch this to a SRL.
1093 if (MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)), TLI))
1094 return DAG.getNode(ISD::SRL, VT, N0, N1);
1098 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1099 SDOperand N0 = N->getOperand(0);
1100 SDOperand N1 = N->getOperand(1);
1101 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1102 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1103 MVT::ValueType VT = N0.getValueType();
1104 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1106 // fold (srl c1, c2) -> c1 >>u c2
1108 return DAG.getConstant(N0C->getValue() >> N1C->getValue(), VT);
1109 // fold (srl 0, x) -> 0
1110 if (N0C && N0C->isNullValue())
1112 // fold (srl x, c >= size(x)) -> undef
1113 if (N1C && N1C->getValue() >= OpSizeInBits)
1114 return DAG.getNode(ISD::UNDEF, VT);
1115 // fold (srl x, 0) -> x
1116 if (N1C && N1C->isNullValue())
1118 // if (srl x, c) is known to be zero, return 0
1119 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
1120 return DAG.getConstant(0, VT);
1121 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1122 if (N1C && N0.getOpcode() == ISD::SRL &&
1123 N0.getOperand(1).getOpcode() == ISD::Constant) {
1124 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1125 uint64_t c2 = N1C->getValue();
1126 if (c1 + c2 > OpSizeInBits)
1127 return DAG.getConstant(0, VT);
1128 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1129 DAG.getConstant(c1 + c2, N1.getValueType()));
1134 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1135 SDOperand N0 = N->getOperand(0);
1136 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1138 // fold (ctlz c1) -> c2
1140 return DAG.getConstant(CountLeadingZeros_64(N0C->getValue()),
1145 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1146 SDOperand N0 = N->getOperand(0);
1147 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1149 // fold (cttz c1) -> c2
1151 return DAG.getConstant(CountTrailingZeros_64(N0C->getValue()),
1156 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1157 SDOperand N0 = N->getOperand(0);
1158 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1160 // fold (ctpop c1) -> c2
1162 return DAG.getConstant(CountPopulation_64(N0C->getValue()),
1167 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1168 SDOperand N0 = N->getOperand(0);
1169 SDOperand N1 = N->getOperand(1);
1170 SDOperand N2 = N->getOperand(2);
1171 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1172 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1173 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1174 MVT::ValueType VT = N->getValueType(0);
1176 // fold select C, X, X -> X
1179 // fold select true, X, Y -> X
1180 if (N0C && !N0C->isNullValue())
1182 // fold select false, X, Y -> Y
1183 if (N0C && N0C->isNullValue())
1185 // fold select C, 1, X -> C | X
1186 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1187 return DAG.getNode(ISD::OR, VT, N0, N2);
1188 // fold select C, 0, X -> ~C & X
1189 // FIXME: this should check for C type == X type, not i1?
1190 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1191 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1192 WorkList.push_back(XORNode.Val);
1193 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1195 // fold select C, X, 1 -> ~C | X
1196 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1197 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1198 WorkList.push_back(XORNode.Val);
1199 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1201 // fold select C, X, 0 -> C & X
1202 // FIXME: this should check for C type == X type, not i1?
1203 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1204 return DAG.getNode(ISD::AND, VT, N0, N1);
1205 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1206 if (MVT::i1 == VT && N0 == N1)
1207 return DAG.getNode(ISD::OR, VT, N0, N2);
1208 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1209 if (MVT::i1 == VT && N0 == N2)
1210 return DAG.getNode(ISD::AND, VT, N0, N1);
1212 // If we can fold this based on the true/false value, do so.
1213 if (SimplifySelectOps(N, N1, N2))
1216 // fold selects based on a setcc into other things, such as min/max/abs
1217 if (N0.getOpcode() == ISD::SETCC)
1218 return SimplifySelect(N0, N1, N2);
1222 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1223 SDOperand N0 = N->getOperand(0);
1224 SDOperand N1 = N->getOperand(1);
1225 SDOperand N2 = N->getOperand(2);
1226 SDOperand N3 = N->getOperand(3);
1227 SDOperand N4 = N->getOperand(4);
1228 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1229 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1230 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1231 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1233 // Determine if the condition we're dealing with is constant
1234 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1235 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1237 // fold select_cc lhs, rhs, x, x, cc -> x
1241 // If we can fold this based on the true/false value, do so.
1242 if (SimplifySelectOps(N, N2, N3))
1245 // fold select_cc into other things, such as min/max/abs
1246 return SimplifySelectCC(N0, N1, N2, N3, CC);
1249 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1250 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1251 cast<CondCodeSDNode>(N->getOperand(2))->get());
1254 SDOperand DAGCombiner::visitADD_PARTS(SDNode *N) {
1255 SDOperand LHSLo = N->getOperand(0);
1256 SDOperand RHSLo = N->getOperand(2);
1257 MVT::ValueType VT = LHSLo.getValueType();
1259 // fold (a_Hi, 0) + (b_Hi, b_Lo) -> (b_Hi + a_Hi, b_Lo)
1260 if (MaskedValueIsZero(LHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) {
1261 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1),
1263 WorkList.push_back(Hi.Val);
1264 CombineTo(N, RHSLo, Hi);
1267 // fold (a_Hi, a_Lo) + (b_Hi, 0) -> (a_Hi + b_Hi, a_Lo)
1268 if (MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) {
1269 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1),
1271 WorkList.push_back(Hi.Val);
1272 CombineTo(N, LHSLo, Hi);
1278 SDOperand DAGCombiner::visitSUB_PARTS(SDNode *N) {
1279 SDOperand LHSLo = N->getOperand(0);
1280 SDOperand RHSLo = N->getOperand(2);
1281 MVT::ValueType VT = LHSLo.getValueType();
1283 // fold (a_Hi, a_Lo) - (b_Hi, 0) -> (a_Hi - b_Hi, a_Lo)
1284 if (MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) {
1285 SDOperand Hi = DAG.getNode(ISD::SUB, VT, N->getOperand(1),
1287 WorkList.push_back(Hi.Val);
1288 CombineTo(N, LHSLo, Hi);
1294 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1295 SDOperand N0 = N->getOperand(0);
1296 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1297 MVT::ValueType VT = N->getValueType(0);
1299 // fold (sext c1) -> c1
1301 return DAG.getConstant(N0C->getSignExtended(), VT);
1302 // fold (sext (sext x)) -> (sext x)
1303 if (N0.getOpcode() == ISD::SIGN_EXTEND)
1304 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1305 // fold (sext (sextload x)) -> (sextload x)
1306 if (N0.getOpcode() == ISD::SEXTLOAD && VT == N0.getValueType())
1308 // fold (sext (load x)) -> (sextload x)
1309 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
1310 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1311 N0.getOperand(1), N0.getOperand(2),
1313 WorkList.push_back(N);
1314 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1315 ExtLoad.getValue(1));
1321 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1322 SDOperand N0 = N->getOperand(0);
1323 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1324 MVT::ValueType VT = N->getValueType(0);
1326 // fold (zext c1) -> c1
1328 return DAG.getConstant(N0C->getValue(), VT);
1329 // fold (zext (zext x)) -> (zext x)
1330 if (N0.getOpcode() == ISD::ZERO_EXTEND)
1331 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1335 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1336 SDOperand N0 = N->getOperand(0);
1337 SDOperand N1 = N->getOperand(1);
1338 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1339 MVT::ValueType VT = N->getValueType(0);
1340 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
1341 unsigned EVTBits = MVT::getSizeInBits(EVT);
1343 // fold (sext_in_reg c1) -> c1
1345 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT);
1346 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate);
1348 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1
1349 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1350 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1353 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
1354 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1355 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
1356 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
1358 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x)
1359 if (N0.getOpcode() == ISD::AssertSext &&
1360 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1363 // fold (sext_in_reg (sextload x)) -> (sextload x)
1364 if (N0.getOpcode() == ISD::SEXTLOAD &&
1365 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) {
1368 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1
1369 if (N0.getOpcode() == ISD::SETCC &&
1370 TLI.getSetCCResultContents() ==
1371 TargetLowering::ZeroOrNegativeOneSetCCResult)
1373 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
1374 if (MaskedValueIsZero(N0, 1ULL << (EVTBits-1), TLI))
1375 return DAG.getNode(ISD::AND, N0.getValueType(), N0,
1376 DAG.getConstant(~0ULL >> (64-EVTBits), VT));
1377 // fold (sext_in_reg (srl x)) -> sra x
1378 if (N0.getOpcode() == ISD::SRL &&
1379 N0.getOperand(1).getOpcode() == ISD::Constant &&
1380 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) {
1381 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0),
1384 // fold (sext_inreg (extload x)) -> (sextload x)
1385 if (N0.getOpcode() == ISD::EXTLOAD &&
1386 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1387 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1388 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1389 N0.getOperand(1), N0.getOperand(2),
1391 WorkList.push_back(N);
1392 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1395 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
1396 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() &&
1397 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1398 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1399 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1400 N0.getOperand(1), N0.getOperand(2),
1402 WorkList.push_back(N);
1403 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1409 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
1410 SDOperand N0 = N->getOperand(0);
1411 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1412 MVT::ValueType VT = N->getValueType(0);
1415 if (N0.getValueType() == N->getValueType(0))
1417 // fold (truncate c1) -> c1
1419 return DAG.getConstant(N0C->getValue(), VT);
1420 // fold (truncate (truncate x)) -> (truncate x)
1421 if (N0.getOpcode() == ISD::TRUNCATE)
1422 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1423 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
1424 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){
1425 if (N0.getValueType() < VT)
1426 // if the source is smaller than the dest, we still need an extend
1427 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
1428 else if (N0.getValueType() > VT)
1429 // if the source is larger than the dest, than we just need the truncate
1430 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1432 // if the source and dest are the same type, we can drop both the extend
1434 return N0.getOperand(0);
1436 // fold (truncate (load x)) -> (smaller load x)
1437 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
1438 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
1439 "Cannot truncate to larger type!");
1440 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1441 // For big endian targets, we need to add an offset to the pointer to load
1442 // the correct bytes. For little endian systems, we merely need to read
1443 // fewer bytes from the same pointer.
1445 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
1446 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) :
1447 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1),
1448 DAG.getConstant(PtrOff, PtrType));
1449 WorkList.push_back(NewPtr.Val);
1450 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2));
1451 WorkList.push_back(N);
1452 CombineTo(N0.Val, Load, Load.getValue(1));
1458 SDOperand DAGCombiner::visitFADD(SDNode *N) {
1459 SDOperand N0 = N->getOperand(0);
1460 SDOperand N1 = N->getOperand(1);
1461 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1462 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1463 MVT::ValueType VT = N->getValueType(0);
1465 // fold (fadd c1, c2) -> c1+c2
1467 return DAG.getConstantFP(N0CFP->getValue() + N1CFP->getValue(), VT);
1468 // canonicalize constant to RHS
1469 if (N0CFP && !N1CFP)
1470 return DAG.getNode(ISD::FADD, VT, N1, N0);
1471 // fold (A + (-B)) -> A-B
1472 if (N1.getOpcode() == ISD::FNEG)
1473 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
1474 // fold ((-A) + B) -> B-A
1475 if (N0.getOpcode() == ISD::FNEG)
1476 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
1480 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
1481 SDOperand N0 = N->getOperand(0);
1482 SDOperand N1 = N->getOperand(1);
1483 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1484 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1485 MVT::ValueType VT = N->getValueType(0);
1487 // fold (fsub c1, c2) -> c1-c2
1489 return DAG.getConstantFP(N0CFP->getValue() - N1CFP->getValue(), VT);
1490 // fold (A-(-B)) -> A+B
1491 if (N1.getOpcode() == ISD::FNEG)
1492 return DAG.getNode(ISD::FADD, N0.getValueType(), N0, N1.getOperand(0));
1496 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
1497 SDOperand N0 = N->getOperand(0);
1498 SDOperand N1 = N->getOperand(1);
1499 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1500 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1501 MVT::ValueType VT = N->getValueType(0);
1503 // fold (fmul c1, c2) -> c1*c2
1505 return DAG.getConstantFP(N0CFP->getValue() * N1CFP->getValue(), VT);
1506 // canonicalize constant to RHS
1507 if (N0CFP && !N1CFP)
1508 return DAG.getNode(ISD::FMUL, VT, N1, N0);
1509 // fold (fmul X, 2.0) -> (fadd X, X)
1510 if (N1CFP && N1CFP->isExactlyValue(+2.0))
1511 return DAG.getNode(ISD::FADD, VT, N0, N0);
1515 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
1516 SDOperand N0 = N->getOperand(0);
1517 SDOperand N1 = N->getOperand(1);
1518 MVT::ValueType VT = N->getValueType(0);
1520 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
1521 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1522 // fold floating point (fdiv c1, c2)
1523 return DAG.getConstantFP(N0CFP->getValue() / N1CFP->getValue(), VT);
1528 SDOperand DAGCombiner::visitFREM(SDNode *N) {
1529 SDOperand N0 = N->getOperand(0);
1530 SDOperand N1 = N->getOperand(1);
1531 MVT::ValueType VT = N->getValueType(0);
1533 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
1534 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1535 // fold floating point (frem c1, c2) -> fmod(c1, c2)
1536 return DAG.getConstantFP(fmod(N0CFP->getValue(),N1CFP->getValue()), VT);
1542 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
1543 SDOperand N0 = N->getOperand(0);
1544 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1546 // fold (sint_to_fp c1) -> c1fp
1548 return DAG.getConstantFP(N0C->getSignExtended(), N->getValueType(0));
1552 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
1553 SDOperand N0 = N->getOperand(0);
1554 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1556 // fold (uint_to_fp c1) -> c1fp
1558 return DAG.getConstantFP(N0C->getValue(), N->getValueType(0));
1562 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
1563 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1565 // fold (fp_to_sint c1fp) -> c1
1567 return DAG.getConstant((int64_t)N0CFP->getValue(), N->getValueType(0));
1571 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
1572 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1574 // fold (fp_to_uint c1fp) -> c1
1576 return DAG.getConstant((uint64_t)N0CFP->getValue(), N->getValueType(0));
1580 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
1581 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1583 // fold (fp_round c1fp) -> c1fp
1585 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0));
1589 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
1590 SDOperand N0 = N->getOperand(0);
1591 MVT::ValueType VT = N->getValueType(0);
1592 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1593 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1595 // fold (fp_round_inreg c1fp) -> c1fp
1597 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
1598 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
1603 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
1604 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1606 // fold (fp_extend c1fp) -> c1fp
1608 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0));
1612 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
1613 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1614 // fold (neg c1) -> -c1
1616 return DAG.getConstantFP(-N0CFP->getValue(), N->getValueType(0));
1617 // fold (neg (sub x, y)) -> (sub y, x)
1618 if (N->getOperand(0).getOpcode() == ISD::SUB)
1619 return DAG.getNode(ISD::SUB, N->getValueType(0), N->getOperand(1),
1621 // fold (neg (neg x)) -> x
1622 if (N->getOperand(0).getOpcode() == ISD::FNEG)
1623 return N->getOperand(0).getOperand(0);
1627 SDOperand DAGCombiner::visitFABS(SDNode *N) {
1628 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1629 // fold (fabs c1) -> fabs(c1)
1631 return DAG.getConstantFP(fabs(N0CFP->getValue()), N->getValueType(0));
1632 // fold (fabs (fabs x)) -> (fabs x)
1633 if (N->getOperand(0).getOpcode() == ISD::FABS)
1634 return N->getOperand(0);
1635 // fold (fabs (fneg x)) -> (fabs x)
1636 if (N->getOperand(0).getOpcode() == ISD::FNEG)
1637 return DAG.getNode(ISD::FABS, N->getValueType(0),
1638 N->getOperand(0).getOperand(0));
1642 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
1643 SDOperand Chain = N->getOperand(0);
1644 SDOperand N1 = N->getOperand(1);
1645 SDOperand N2 = N->getOperand(2);
1646 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1648 // never taken branch, fold to chain
1649 if (N1C && N1C->isNullValue())
1651 // unconditional branch
1652 if (N1C && N1C->getValue() == 1)
1653 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
1657 SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) {
1658 SDOperand Chain = N->getOperand(0);
1659 SDOperand N1 = N->getOperand(1);
1660 SDOperand N2 = N->getOperand(2);
1661 SDOperand N3 = N->getOperand(3);
1662 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1664 // unconditional branch to true mbb
1665 if (N1C && N1C->getValue() == 1)
1666 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
1667 // unconditional branch to false mbb
1668 if (N1C && N1C->isNullValue())
1669 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3);
1673 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
1675 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
1676 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
1677 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
1679 // Use SimplifySetCC to simplify SETCC's.
1680 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
1681 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
1683 // fold br_cc true, dest -> br dest (unconditional branch)
1684 if (SCCC && SCCC->getValue())
1685 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
1687 // fold br_cc false, dest -> unconditional fall through
1688 if (SCCC && SCCC->isNullValue())
1689 return N->getOperand(0);
1690 // fold to a simpler setcc
1691 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
1692 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
1693 Simp.getOperand(2), Simp.getOperand(0),
1694 Simp.getOperand(1), N->getOperand(4));
1698 SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) {
1699 SDOperand Chain = N->getOperand(0);
1700 SDOperand CCN = N->getOperand(1);
1701 SDOperand LHS = N->getOperand(2);
1702 SDOperand RHS = N->getOperand(3);
1703 SDOperand N4 = N->getOperand(4);
1704 SDOperand N5 = N->getOperand(5);
1706 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS,
1707 cast<CondCodeSDNode>(CCN)->get(), false);
1708 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1710 // fold select_cc lhs, rhs, x, x, cc -> x
1712 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
1713 // fold select_cc true, x, y -> x
1714 if (SCCC && SCCC->getValue())
1715 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
1716 // fold select_cc false, x, y -> y
1717 if (SCCC && SCCC->isNullValue())
1718 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5);
1719 // fold to a simpler setcc
1720 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
1721 return DAG.getBR2Way_CC(Chain, SCC.getOperand(2), SCC.getOperand(0),
1722 SCC.getOperand(1), N4, N5);
1726 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
1727 SDOperand Chain = N->getOperand(0);
1728 SDOperand Ptr = N->getOperand(1);
1729 SDOperand SrcValue = N->getOperand(2);
1731 // If this load is directly stored, replace the load value with the stored
1733 // TODO: Handle store large -> read small portion.
1734 // TODO: Handle TRUNCSTORE/EXTLOAD
1735 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
1736 Chain.getOperand(1).getValueType() == N->getValueType(0))
1737 return CombineTo(N, Chain.getOperand(1), Chain);
1742 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
1743 SDOperand Chain = N->getOperand(0);
1744 SDOperand Value = N->getOperand(1);
1745 SDOperand Ptr = N->getOperand(2);
1746 SDOperand SrcValue = N->getOperand(3);
1748 // If this is a store that kills a previous store, remove the previous store.
1749 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
1750 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */) {
1751 // Create a new store of Value that replaces both stores.
1752 SDNode *PrevStore = Chain.Val;
1753 if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
1755 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other,
1756 PrevStore->getOperand(0), Value, Ptr,
1758 CombineTo(N, NewStore); // Nuke this store.
1759 CombineTo(PrevStore, NewStore); // Nuke the previous store.
1760 return SDOperand(N, 0);
1766 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
1767 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
1769 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
1770 cast<CondCodeSDNode>(N0.getOperand(2))->get());
1771 // If we got a simplified select_cc node back from SimplifySelectCC, then
1772 // break it down into a new SETCC node, and a new SELECT node, and then return
1773 // the SELECT node, since we were called with a SELECT node.
1775 // Check to see if we got a select_cc back (to turn into setcc/select).
1776 // Otherwise, just return whatever node we got back, like fabs.
1777 if (SCC.getOpcode() == ISD::SELECT_CC) {
1778 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
1779 SCC.getOperand(0), SCC.getOperand(1),
1781 WorkList.push_back(SETCC.Val);
1782 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
1783 SCC.getOperand(3), SETCC);
1790 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
1791 /// are the two values being selected between, see if we can simplify the
1794 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
1797 // If this is a select from two identical things, try to pull the operation
1798 // through the select.
1799 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
1801 std::cerr << "SELECT: ["; LHS.Val->dump();
1802 std::cerr << "] ["; RHS.Val->dump();
1806 // If this is a load and the token chain is identical, replace the select
1807 // of two loads with a load through a select of the address to load from.
1808 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
1809 // constants have been dropped into the constant pool.
1810 if ((LHS.getOpcode() == ISD::LOAD ||
1811 LHS.getOpcode() == ISD::EXTLOAD ||
1812 LHS.getOpcode() == ISD::ZEXTLOAD ||
1813 LHS.getOpcode() == ISD::SEXTLOAD) &&
1814 // Token chains must be identical.
1815 LHS.getOperand(0) == RHS.getOperand(0) &&
1816 // If this is an EXTLOAD, the VT's must match.
1817 (LHS.getOpcode() == ISD::LOAD ||
1818 LHS.getOperand(3) == RHS.getOperand(3))) {
1819 // FIXME: this conflates two src values, discarding one. This is not
1820 // the right thing to do, but nothing uses srcvalues now. When they do,
1821 // turn SrcValue into a list of locations.
1823 if (TheSelect->getOpcode() == ISD::SELECT)
1824 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(),
1825 TheSelect->getOperand(0), LHS.getOperand(1),
1828 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(),
1829 TheSelect->getOperand(0),
1830 TheSelect->getOperand(1),
1831 LHS.getOperand(1), RHS.getOperand(1),
1832 TheSelect->getOperand(4));
1835 if (LHS.getOpcode() == ISD::LOAD)
1836 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0),
1837 Addr, LHS.getOperand(2));
1839 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0),
1840 LHS.getOperand(0), Addr, LHS.getOperand(2),
1841 cast<VTSDNode>(LHS.getOperand(3))->getVT());
1842 // Users of the select now use the result of the load.
1843 CombineTo(TheSelect, Load);
1845 // Users of the old loads now use the new load's chain. We know the
1846 // old-load value is dead now.
1847 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
1848 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
1856 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
1857 SDOperand N2, SDOperand N3,
1860 MVT::ValueType VT = N2.getValueType();
1861 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1862 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1863 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
1864 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
1866 // Determine if the condition we're dealing with is constant
1867 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1868 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1870 // fold select_cc true, x, y -> x
1871 if (SCCC && SCCC->getValue())
1873 // fold select_cc false, x, y -> y
1874 if (SCCC && SCCC->getValue() == 0)
1877 // Check to see if we can simplify the select into an fabs node
1878 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1879 // Allow either -0.0 or 0.0
1880 if (CFP->getValue() == 0.0) {
1881 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
1882 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
1883 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
1884 N2 == N3.getOperand(0))
1885 return DAG.getNode(ISD::FABS, VT, N0);
1887 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
1888 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
1889 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
1890 N2.getOperand(0) == N3)
1891 return DAG.getNode(ISD::FABS, VT, N3);
1895 // Check to see if we can perform the "gzip trick", transforming
1896 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
1897 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() &&
1898 MVT::isInteger(N0.getValueType()) &&
1899 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) {
1900 MVT::ValueType XType = N0.getValueType();
1901 MVT::ValueType AType = N2.getValueType();
1902 if (XType >= AType) {
1903 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
1904 // single-bit constant.
1905 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
1906 unsigned ShCtV = Log2_64(N2C->getValue());
1907 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
1908 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
1909 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
1910 WorkList.push_back(Shift.Val);
1911 if (XType > AType) {
1912 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
1913 WorkList.push_back(Shift.Val);
1915 return DAG.getNode(ISD::AND, AType, Shift, N2);
1917 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
1918 DAG.getConstant(MVT::getSizeInBits(XType)-1,
1919 TLI.getShiftAmountTy()));
1920 WorkList.push_back(Shift.Val);
1921 if (XType > AType) {
1922 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
1923 WorkList.push_back(Shift.Val);
1925 return DAG.getNode(ISD::AND, AType, Shift, N2);
1929 // fold select C, 16, 0 -> shl C, 4
1930 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
1931 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
1932 // Get a SetCC of the condition
1933 // FIXME: Should probably make sure that setcc is legal if we ever have a
1934 // target where it isn't.
1935 SDOperand Temp, SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
1936 WorkList.push_back(SCC.Val);
1937 // cast from setcc result type to select result type
1939 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
1941 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
1942 WorkList.push_back(Temp.Val);
1943 // shl setcc result by log2 n2c
1944 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
1945 DAG.getConstant(Log2_64(N2C->getValue()),
1946 TLI.getShiftAmountTy()));
1949 // Check to see if this is the equivalent of setcc
1950 // FIXME: Turn all of these into setcc if setcc if setcc is legal
1951 // otherwise, go ahead with the folds.
1952 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
1953 MVT::ValueType XType = N0.getValueType();
1954 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
1955 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
1956 if (Res.getValueType() != VT)
1957 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
1961 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
1962 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
1963 TLI.isOperationLegal(ISD::CTLZ, XType)) {
1964 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
1965 return DAG.getNode(ISD::SRL, XType, Ctlz,
1966 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
1967 TLI.getShiftAmountTy()));
1969 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
1970 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
1971 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
1973 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
1974 DAG.getConstant(~0ULL, XType));
1975 return DAG.getNode(ISD::SRL, XType,
1976 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
1977 DAG.getConstant(MVT::getSizeInBits(XType)-1,
1978 TLI.getShiftAmountTy()));
1980 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
1981 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
1982 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
1983 DAG.getConstant(MVT::getSizeInBits(XType)-1,
1984 TLI.getShiftAmountTy()));
1985 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
1989 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
1990 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
1991 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
1992 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
1993 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
1994 MVT::ValueType XType = N0.getValueType();
1995 if (SubC->isNullValue() && MVT::isInteger(XType)) {
1996 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
1997 DAG.getConstant(MVT::getSizeInBits(XType)-1,
1998 TLI.getShiftAmountTy()));
1999 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
2000 WorkList.push_back(Shift.Val);
2001 WorkList.push_back(Add.Val);
2002 return DAG.getNode(ISD::XOR, XType, Add, Shift);
2010 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
2011 SDOperand N1, ISD::CondCode Cond,
2012 bool foldBooleans) {
2013 // These setcc operations always fold.
2017 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
2019 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
2022 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
2023 uint64_t C1 = N1C->getValue();
2024 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
2025 uint64_t C0 = N0C->getValue();
2027 // Sign extend the operands if required
2028 if (ISD::isSignedIntSetCC(Cond)) {
2029 C0 = N0C->getSignExtended();
2030 C1 = N1C->getSignExtended();
2034 default: assert(0 && "Unknown integer setcc!");
2035 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
2036 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
2037 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
2038 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
2039 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
2040 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
2041 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
2042 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
2043 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
2044 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
2047 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2048 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2049 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
2051 // If the comparison constant has bits in the upper part, the
2052 // zero-extended value could never match.
2053 if (C1 & (~0ULL << InSize)) {
2054 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
2058 case ISD::SETEQ: return DAG.getConstant(0, VT);
2061 case ISD::SETNE: return DAG.getConstant(1, VT);
2064 // True if the sign bit of C1 is set.
2065 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
2068 // True if the sign bit of C1 isn't set.
2069 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
2075 // Otherwise, we can perform the comparison with the low bits.
2083 return DAG.getSetCC(VT, N0.getOperand(0),
2084 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
2087 break; // todo, be more careful with signed comparisons
2089 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2090 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2091 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2092 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
2093 MVT::ValueType ExtDstTy = N0.getValueType();
2094 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
2096 // If the extended part has any inconsistent bits, it cannot ever
2097 // compare equal. In other words, they have to be all ones or all
2100 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
2101 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
2102 return DAG.getConstant(Cond == ISD::SETNE, VT);
2105 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
2106 if (Op0Ty == ExtSrcTy) {
2107 ZextOp = N0.getOperand(0);
2109 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
2110 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
2111 DAG.getConstant(Imm, Op0Ty));
2113 WorkList.push_back(ZextOp.Val);
2114 // Otherwise, make this a use of a zext.
2115 return DAG.getSetCC(VT, ZextOp,
2116 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
2121 uint64_t MinVal, MaxVal;
2122 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
2123 if (ISD::isSignedIntSetCC(Cond)) {
2124 MinVal = 1ULL << (OperandBitSize-1);
2125 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
2126 MaxVal = ~0ULL >> (65-OperandBitSize);
2131 MaxVal = ~0ULL >> (64-OperandBitSize);
2134 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2135 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2136 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2137 --C1; // X >= C0 --> X > (C0-1)
2138 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2139 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2142 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2143 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2144 ++C1; // X <= C0 --> X < (C0+1)
2145 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2146 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2149 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2150 return DAG.getConstant(0, VT); // X < MIN --> false
2152 // Canonicalize setgt X, Min --> setne X, Min
2153 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2154 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
2156 // If we have setult X, 1, turn it into seteq X, 0
2157 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2158 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
2160 // If we have setugt X, Max-1, turn it into seteq X, Max
2161 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2162 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
2165 // If we have "setcc X, C0", check to see if we can shrink the immediate
2168 // SETUGT X, SINTMAX -> SETLT X, 0
2169 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
2170 C1 == (~0ULL >> (65-OperandBitSize)))
2171 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
2174 // FIXME: Implement the rest of these.
2176 // Fold bit comparisons when we can.
2177 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2178 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
2179 if (ConstantSDNode *AndRHS =
2180 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2181 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2182 // Perform the xform if the AND RHS is a single bit.
2183 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
2184 return DAG.getNode(ISD::SRL, VT, N0,
2185 DAG.getConstant(Log2_64(AndRHS->getValue()),
2186 TLI.getShiftAmountTy()));
2188 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
2189 // (X & 8) == 8 --> (X & 8) >> 3
2190 // Perform the xform if C1 is a single bit.
2191 if ((C1 & (C1-1)) == 0) {
2192 return DAG.getNode(ISD::SRL, VT, N0,
2193 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
2198 } else if (isa<ConstantSDNode>(N0.Val)) {
2199 // Ensure that the constant occurs on the RHS.
2200 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2203 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
2204 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
2205 double C0 = N0C->getValue(), C1 = N1C->getValue();
2208 default: break; // FIXME: Implement the rest of these!
2209 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
2210 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
2211 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
2212 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
2213 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
2214 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
2217 // Ensure that the constant occurs on the RHS.
2218 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2222 // We can always fold X == Y for integer setcc's.
2223 if (MVT::isInteger(N0.getValueType()))
2224 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2225 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2226 if (UOF == 2) // FP operators that are undefined on NaNs.
2227 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2228 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2229 return DAG.getConstant(UOF, VT);
2230 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2231 // if it is not already.
2232 ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO;
2233 if (NewCond != Cond)
2234 return DAG.getSetCC(VT, N0, N1, NewCond);
2237 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2238 MVT::isInteger(N0.getValueType())) {
2239 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2240 N0.getOpcode() == ISD::XOR) {
2241 // Simplify (X+Y) == (X+Z) --> Y == Z
2242 if (N0.getOpcode() == N1.getOpcode()) {
2243 if (N0.getOperand(0) == N1.getOperand(0))
2244 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
2245 if (N0.getOperand(1) == N1.getOperand(1))
2246 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
2247 if (isCommutativeBinOp(N0.getOpcode())) {
2248 // If X op Y == Y op X, try other combinations.
2249 if (N0.getOperand(0) == N1.getOperand(1))
2250 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
2251 if (N0.getOperand(1) == N1.getOperand(0))
2252 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
2256 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. Common for condcodes.
2257 if (N0.getOpcode() == ISD::XOR)
2258 if (ConstantSDNode *XORC = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2259 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2260 // If we know that all of the inverted bits are zero, don't bother
2261 // performing the inversion.
2262 if (MaskedValueIsZero(N0.getOperand(0), ~XORC->getValue(), TLI))
2263 return DAG.getSetCC(VT, N0.getOperand(0),
2264 DAG.getConstant(XORC->getValue()^RHSC->getValue(),
2265 N0.getValueType()), Cond);
2268 // Simplify (X+Z) == X --> Z == 0
2269 if (N0.getOperand(0) == N1)
2270 return DAG.getSetCC(VT, N0.getOperand(1),
2271 DAG.getConstant(0, N0.getValueType()), Cond);
2272 if (N0.getOperand(1) == N1) {
2273 if (isCommutativeBinOp(N0.getOpcode()))
2274 return DAG.getSetCC(VT, N0.getOperand(0),
2275 DAG.getConstant(0, N0.getValueType()), Cond);
2277 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2278 // (Z-X) == X --> Z == X<<1
2279 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
2281 DAG.getConstant(1,TLI.getShiftAmountTy()));
2282 WorkList.push_back(SH.Val);
2283 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
2288 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2289 N1.getOpcode() == ISD::XOR) {
2290 // Simplify X == (X+Z) --> Z == 0
2291 if (N1.getOperand(0) == N0) {
2292 return DAG.getSetCC(VT, N1.getOperand(1),
2293 DAG.getConstant(0, N1.getValueType()), Cond);
2294 } else if (N1.getOperand(1) == N0) {
2295 if (isCommutativeBinOp(N1.getOpcode())) {
2296 return DAG.getSetCC(VT, N1.getOperand(0),
2297 DAG.getConstant(0, N1.getValueType()), Cond);
2299 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2300 // X == (Z-X) --> X<<1 == Z
2301 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
2302 DAG.getConstant(1,TLI.getShiftAmountTy()));
2303 WorkList.push_back(SH.Val);
2304 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
2310 // Fold away ALL boolean setcc's.
2312 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2314 default: assert(0 && "Unknown integer setcc!");
2315 case ISD::SETEQ: // X == Y -> (X^Y)^1
2316 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2317 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
2318 WorkList.push_back(Temp.Val);
2320 case ISD::SETNE: // X != Y --> (X^Y)
2321 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2323 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
2324 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
2325 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2326 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
2327 WorkList.push_back(Temp.Val);
2329 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
2330 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
2331 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2332 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
2333 WorkList.push_back(Temp.Val);
2335 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
2336 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
2337 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2338 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
2339 WorkList.push_back(Temp.Val);
2341 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
2342 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
2343 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2344 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
2347 if (VT != MVT::i1) {
2348 WorkList.push_back(N0.Val);
2349 // FIXME: If running after legalize, we probably can't do this.
2350 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2355 // Could not fold it.
2359 // SelectionDAG::Combine - This is the entry point for the file.
2361 void SelectionDAG::Combine(bool RunningAfterLegalize) {
2362 /// run - This is the main entry point to this class.
2364 DAGCombiner(*this).Run(RunningAfterLegalize);