1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/ADT/SmallPtrSet.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
41 STATISTIC(NodesCombined , "Number of dag nodes combined");
42 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
43 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
44 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
45 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
49 CombinerAA("combiner-alias-analysis", cl::Hidden,
50 cl::desc("Turn on alias analysis during testing"));
53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
54 cl::desc("Include global information in alias analysis"));
56 //------------------------------ DAGCombiner ---------------------------------//
60 const TargetLowering &TLI;
62 CodeGenOpt::Level OptLevel;
66 // Worklist of all of the nodes that need to be simplified.
68 // This has the semantics that when adding to the worklist,
69 // the item added must be next to be processed. It should
70 // also only appear once. The naive approach to this takes
73 // To reduce the insert/remove time to logarithmic, we use
74 // a set and a vector to maintain our worklist.
76 // The set contains the items on the worklist, but does not
77 // maintain the order they should be visited.
79 // The vector maintains the order nodes should be visited, but may
80 // contain duplicate or removed nodes. When choosing a node to
81 // visit, we pop off the order stack until we find an item that is
82 // also in the contents set. All operations are O(log N).
83 SmallPtrSet<SDNode*, 64> WorkListContents;
84 SmallVector<SDNode*, 64> WorkListOrder;
86 // AA - Used for DAG load/store alias analysis.
89 /// AddUsersToWorkList - When an instruction is simplified, add all users of
90 /// the instruction to the work lists because they might get more simplified
93 void AddUsersToWorkList(SDNode *N) {
94 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
99 /// visit - call the node-specific routine that knows how to fold each
100 /// particular type of node.
101 SDValue visit(SDNode *N);
104 /// AddToWorkList - Add to the work list making sure its instance is at the
105 /// back (next to be processed.)
106 void AddToWorkList(SDNode *N) {
107 WorkListContents.insert(N);
108 WorkListOrder.push_back(N);
111 /// removeFromWorkList - remove all instances of N from the worklist.
113 void removeFromWorkList(SDNode *N) {
114 WorkListContents.erase(N);
117 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
120 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
121 return CombineTo(N, &Res, 1, AddTo);
124 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
126 SDValue To[] = { Res0, Res1 };
127 return CombineTo(N, To, 2, AddTo);
130 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
134 /// SimplifyDemandedBits - Check the specified integer node value to see if
135 /// it can be simplified or if things it uses can be simplified by bit
136 /// propagation. If so, return true.
137 bool SimplifyDemandedBits(SDValue Op) {
138 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
139 APInt Demanded = APInt::getAllOnesValue(BitWidth);
140 return SimplifyDemandedBits(Op, Demanded);
143 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
145 bool CombineToPreIndexedLoadStore(SDNode *N);
146 bool CombineToPostIndexedLoadStore(SDNode *N);
148 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
149 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
150 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
151 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
152 SDValue PromoteIntBinOp(SDValue Op);
153 SDValue PromoteIntShiftOp(SDValue Op);
154 SDValue PromoteExtend(SDValue Op);
155 bool PromoteLoad(SDValue Op);
157 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
158 SDValue Trunc, SDValue ExtLoad, SDLoc DL,
159 ISD::NodeType ExtType);
161 /// combine - call the node-specific routine that knows how to fold each
162 /// particular type of node. If that doesn't do anything, try the
163 /// target-specific DAG combines.
164 SDValue combine(SDNode *N);
166 // Visitation implementation - Implement dag node combining for different
167 // node types. The semantics are as follows:
169 // SDValue.getNode() == 0 - No change was made
170 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
171 // otherwise - N should be replaced by the returned Operand.
173 SDValue visitTokenFactor(SDNode *N);
174 SDValue visitMERGE_VALUES(SDNode *N);
175 SDValue visitADD(SDNode *N);
176 SDValue visitSUB(SDNode *N);
177 SDValue visitADDC(SDNode *N);
178 SDValue visitSUBC(SDNode *N);
179 SDValue visitADDE(SDNode *N);
180 SDValue visitSUBE(SDNode *N);
181 SDValue visitMUL(SDNode *N);
182 SDValue visitSDIV(SDNode *N);
183 SDValue visitUDIV(SDNode *N);
184 SDValue visitSREM(SDNode *N);
185 SDValue visitUREM(SDNode *N);
186 SDValue visitMULHU(SDNode *N);
187 SDValue visitMULHS(SDNode *N);
188 SDValue visitSMUL_LOHI(SDNode *N);
189 SDValue visitUMUL_LOHI(SDNode *N);
190 SDValue visitSMULO(SDNode *N);
191 SDValue visitUMULO(SDNode *N);
192 SDValue visitSDIVREM(SDNode *N);
193 SDValue visitUDIVREM(SDNode *N);
194 SDValue visitAND(SDNode *N);
195 SDValue visitOR(SDNode *N);
196 SDValue visitXOR(SDNode *N);
197 SDValue SimplifyVBinOp(SDNode *N);
198 SDValue SimplifyVUnaryOp(SDNode *N);
199 SDValue visitSHL(SDNode *N);
200 SDValue visitSRA(SDNode *N);
201 SDValue visitSRL(SDNode *N);
202 SDValue visitCTLZ(SDNode *N);
203 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
204 SDValue visitCTTZ(SDNode *N);
205 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
206 SDValue visitCTPOP(SDNode *N);
207 SDValue visitSELECT(SDNode *N);
208 SDValue visitVSELECT(SDNode *N);
209 SDValue visitSELECT_CC(SDNode *N);
210 SDValue visitSETCC(SDNode *N);
211 SDValue visitSIGN_EXTEND(SDNode *N);
212 SDValue visitZERO_EXTEND(SDNode *N);
213 SDValue visitANY_EXTEND(SDNode *N);
214 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
215 SDValue visitTRUNCATE(SDNode *N);
216 SDValue visitBITCAST(SDNode *N);
217 SDValue visitBUILD_PAIR(SDNode *N);
218 SDValue visitFADD(SDNode *N);
219 SDValue visitFSUB(SDNode *N);
220 SDValue visitFMUL(SDNode *N);
221 SDValue visitFMA(SDNode *N);
222 SDValue visitFDIV(SDNode *N);
223 SDValue visitFREM(SDNode *N);
224 SDValue visitFCOPYSIGN(SDNode *N);
225 SDValue visitSINT_TO_FP(SDNode *N);
226 SDValue visitUINT_TO_FP(SDNode *N);
227 SDValue visitFP_TO_SINT(SDNode *N);
228 SDValue visitFP_TO_UINT(SDNode *N);
229 SDValue visitFP_ROUND(SDNode *N);
230 SDValue visitFP_ROUND_INREG(SDNode *N);
231 SDValue visitFP_EXTEND(SDNode *N);
232 SDValue visitFNEG(SDNode *N);
233 SDValue visitFABS(SDNode *N);
234 SDValue visitFCEIL(SDNode *N);
235 SDValue visitFTRUNC(SDNode *N);
236 SDValue visitFFLOOR(SDNode *N);
237 SDValue visitBRCOND(SDNode *N);
238 SDValue visitBR_CC(SDNode *N);
239 SDValue visitLOAD(SDNode *N);
240 SDValue visitSTORE(SDNode *N);
241 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
242 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
243 SDValue visitBUILD_VECTOR(SDNode *N);
244 SDValue visitCONCAT_VECTORS(SDNode *N);
245 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
246 SDValue visitVECTOR_SHUFFLE(SDNode *N);
248 SDValue XformToShuffleWithZero(SDNode *N);
249 SDValue ReassociateOps(unsigned Opc, SDLoc DL, SDValue LHS, SDValue RHS);
251 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
253 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
254 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
255 SDValue SimplifySelect(SDLoc DL, SDValue N0, SDValue N1, SDValue N2);
256 SDValue SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1, SDValue N2,
257 SDValue N3, ISD::CondCode CC,
258 bool NotExtCompare = false);
259 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
260 SDLoc DL, bool foldBooleans = true);
261 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
263 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
264 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
265 SDValue BuildSDIV(SDNode *N);
266 SDValue BuildUDIV(SDNode *N);
267 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
268 bool DemandHighBits = true);
269 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
270 SDNode *MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL);
271 SDValue ReduceLoadWidth(SDNode *N);
272 SDValue ReduceLoadOpStoreWidth(SDNode *N);
273 SDValue TransformFPLoadStorePair(SDNode *N);
274 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N);
275 SDValue reduceBuildVecConvertToConvertBuildVec(SDNode *N);
277 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
279 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
280 /// looking for aliasing nodes and adding them to the Aliases vector.
281 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
282 SmallVector<SDValue, 8> &Aliases);
284 /// isAlias - Return true if there is any possibility that the two addresses
286 bool isAlias(SDValue Ptr1, int64_t Size1,
287 const Value *SrcValue1, int SrcValueOffset1,
288 unsigned SrcValueAlign1,
289 const MDNode *TBAAInfo1,
290 SDValue Ptr2, int64_t Size2,
291 const Value *SrcValue2, int SrcValueOffset2,
292 unsigned SrcValueAlign2,
293 const MDNode *TBAAInfo2) const;
295 /// isAlias - Return true if there is any possibility that the two addresses
297 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1);
299 /// FindAliasInfo - Extracts the relevant alias information from the memory
300 /// node. Returns true if the operand was a load.
301 bool FindAliasInfo(SDNode *N,
302 SDValue &Ptr, int64_t &Size,
303 const Value *&SrcValue, int &SrcValueOffset,
304 unsigned &SrcValueAlignment,
305 const MDNode *&TBAAInfo) const;
307 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
308 /// looking for a better chain (aliasing node.)
309 SDValue FindBetterChain(SDNode *N, SDValue Chain);
311 /// Merge consecutive store operations into a wide store.
312 /// This optimization uses wide integers or vectors when possible.
313 /// \return True if some memory operations were changed.
314 bool MergeConsecutiveStores(StoreSDNode *N);
317 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
318 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
319 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
321 /// Run - runs the dag combiner on all nodes in the work list
322 void Run(CombineLevel AtLevel);
324 SelectionDAG &getDAG() const { return DAG; }
326 /// getShiftAmountTy - Returns a type large enough to hold any valid
327 /// shift amount - before type legalization these can be huge.
328 EVT getShiftAmountTy(EVT LHSTy) {
329 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy();
332 /// isTypeLegal - This method returns true if we are running before type
333 /// legalization or if the specified VT is legal.
334 bool isTypeLegal(const EVT &VT) {
335 if (!LegalTypes) return true;
336 return TLI.isTypeLegal(VT);
339 /// getSetCCResultType - Convenience wrapper around
340 /// TargetLowering::getSetCCResultType
341 EVT getSetCCResultType(EVT VT) const {
342 return TLI.getSetCCResultType(*DAG.getContext(), VT);
349 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
350 /// nodes from the worklist.
351 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
354 explicit WorkListRemover(DAGCombiner &dc)
355 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
357 virtual void NodeDeleted(SDNode *N, SDNode *E) {
358 DC.removeFromWorkList(N);
363 //===----------------------------------------------------------------------===//
364 // TargetLowering::DAGCombinerInfo implementation
365 //===----------------------------------------------------------------------===//
367 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
368 ((DAGCombiner*)DC)->AddToWorkList(N);
371 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
372 ((DAGCombiner*)DC)->removeFromWorkList(N);
375 SDValue TargetLowering::DAGCombinerInfo::
376 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
377 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
380 SDValue TargetLowering::DAGCombinerInfo::
381 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
382 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
386 SDValue TargetLowering::DAGCombinerInfo::
387 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
388 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
391 void TargetLowering::DAGCombinerInfo::
392 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
393 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
396 //===----------------------------------------------------------------------===//
398 //===----------------------------------------------------------------------===//
400 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
401 /// specified expression for the same cost as the expression itself, or 2 if we
402 /// can compute the negated form more cheaply than the expression itself.
403 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
404 const TargetLowering &TLI,
405 const TargetOptions *Options,
406 unsigned Depth = 0) {
407 // fneg is removable even if it has multiple uses.
408 if (Op.getOpcode() == ISD::FNEG) return 2;
410 // Don't allow anything with multiple uses.
411 if (!Op.hasOneUse()) return 0;
413 // Don't recurse exponentially.
414 if (Depth > 6) return 0;
416 switch (Op.getOpcode()) {
417 default: return false;
418 case ISD::ConstantFP:
419 // Don't invert constant FP values after legalize. The negated constant
420 // isn't necessarily legal.
421 return LegalOperations ? 0 : 1;
423 // FIXME: determine better conditions for this xform.
424 if (!Options->UnsafeFPMath) return 0;
426 // After operation legalization, it might not be legal to create new FSUBs.
427 if (LegalOperations &&
428 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
431 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
432 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
435 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
436 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
439 // We can't turn -(A-B) into B-A when we honor signed zeros.
440 if (!Options->UnsafeFPMath) return 0;
442 // fold (fneg (fsub A, B)) -> (fsub B, A)
447 if (Options->HonorSignDependentRoundingFPMath()) return 0;
449 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
450 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
454 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
460 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
465 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
466 /// returns the newly negated expression.
467 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
468 bool LegalOperations, unsigned Depth = 0) {
469 // fneg is removable even if it has multiple uses.
470 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
472 // Don't allow anything with multiple uses.
473 assert(Op.hasOneUse() && "Unknown reuse!");
475 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
476 switch (Op.getOpcode()) {
477 default: llvm_unreachable("Unknown code");
478 case ISD::ConstantFP: {
479 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
481 return DAG.getConstantFP(V, Op.getValueType());
484 // FIXME: determine better conditions for this xform.
485 assert(DAG.getTarget().Options.UnsafeFPMath);
487 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
488 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
489 DAG.getTargetLoweringInfo(),
490 &DAG.getTarget().Options, Depth+1))
491 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
492 GetNegatedExpression(Op.getOperand(0), DAG,
493 LegalOperations, Depth+1),
495 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
496 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
497 GetNegatedExpression(Op.getOperand(1), DAG,
498 LegalOperations, Depth+1),
501 // We can't turn -(A-B) into B-A when we honor signed zeros.
502 assert(DAG.getTarget().Options.UnsafeFPMath);
504 // fold (fneg (fsub 0, B)) -> B
505 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
506 if (N0CFP->getValueAPF().isZero())
507 return Op.getOperand(1);
509 // fold (fneg (fsub A, B)) -> (fsub B, A)
510 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
511 Op.getOperand(1), Op.getOperand(0));
515 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath());
517 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
518 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
519 DAG.getTargetLoweringInfo(),
520 &DAG.getTarget().Options, Depth+1))
521 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
522 GetNegatedExpression(Op.getOperand(0), DAG,
523 LegalOperations, Depth+1),
526 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
527 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
529 GetNegatedExpression(Op.getOperand(1), DAG,
530 LegalOperations, Depth+1));
534 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
535 GetNegatedExpression(Op.getOperand(0), DAG,
536 LegalOperations, Depth+1));
538 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(),
539 GetNegatedExpression(Op.getOperand(0), DAG,
540 LegalOperations, Depth+1),
546 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
547 // that selects between the values 1 and 0, making it equivalent to a setcc.
548 // Also, set the incoming LHS, RHS, and CC references to the appropriate
549 // nodes based on the type of node we are checking. This simplifies life a
550 // bit for the callers.
551 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
553 if (N.getOpcode() == ISD::SETCC) {
554 LHS = N.getOperand(0);
555 RHS = N.getOperand(1);
556 CC = N.getOperand(2);
559 if (N.getOpcode() == ISD::SELECT_CC &&
560 N.getOperand(2).getOpcode() == ISD::Constant &&
561 N.getOperand(3).getOpcode() == ISD::Constant &&
562 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
563 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
564 LHS = N.getOperand(0);
565 RHS = N.getOperand(1);
566 CC = N.getOperand(4);
572 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
573 // one use. If this is true, it allows the users to invert the operation for
574 // free when it is profitable to do so.
575 static bool isOneUseSetCC(SDValue N) {
577 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
582 SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDLoc DL,
583 SDValue N0, SDValue N1) {
584 EVT VT = N0.getValueType();
585 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
586 if (isa<ConstantSDNode>(N1)) {
587 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
589 DAG.FoldConstantArithmetic(Opc, VT,
590 cast<ConstantSDNode>(N0.getOperand(1)),
591 cast<ConstantSDNode>(N1));
592 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
594 if (N0.hasOneUse()) {
595 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
596 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT,
597 N0.getOperand(0), N1);
598 AddToWorkList(OpNode.getNode());
599 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
603 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
604 if (isa<ConstantSDNode>(N0)) {
605 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
607 DAG.FoldConstantArithmetic(Opc, VT,
608 cast<ConstantSDNode>(N1.getOperand(1)),
609 cast<ConstantSDNode>(N0));
610 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
612 if (N1.hasOneUse()) {
613 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
614 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT,
615 N1.getOperand(0), N0);
616 AddToWorkList(OpNode.getNode());
617 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
624 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
626 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
628 DEBUG(dbgs() << "\nReplacing.1 ";
630 dbgs() << "\nWith: ";
631 To[0].getNode()->dump(&DAG);
632 dbgs() << " and " << NumTo-1 << " other values\n";
633 for (unsigned i = 0, e = NumTo; i != e; ++i)
634 assert((!To[i].getNode() ||
635 N->getValueType(i) == To[i].getValueType()) &&
636 "Cannot combine value to value of different type!"));
637 WorkListRemover DeadNodes(*this);
638 DAG.ReplaceAllUsesWith(N, To);
640 // Push the new nodes and any users onto the worklist
641 for (unsigned i = 0, e = NumTo; i != e; ++i) {
642 if (To[i].getNode()) {
643 AddToWorkList(To[i].getNode());
644 AddUsersToWorkList(To[i].getNode());
649 // Finally, if the node is now dead, remove it from the graph. The node
650 // may not be dead if the replacement process recursively simplified to
651 // something else needing this node.
652 if (N->use_empty()) {
653 // Nodes can be reintroduced into the worklist. Make sure we do not
654 // process a node that has been replaced.
655 removeFromWorkList(N);
657 // Finally, since the node is now dead, remove it from the graph.
660 return SDValue(N, 0);
664 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
665 // Replace all uses. If any nodes become isomorphic to other nodes and
666 // are deleted, make sure to remove them from our worklist.
667 WorkListRemover DeadNodes(*this);
668 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
670 // Push the new node and any (possibly new) users onto the worklist.
671 AddToWorkList(TLO.New.getNode());
672 AddUsersToWorkList(TLO.New.getNode());
674 // Finally, if the node is now dead, remove it from the graph. The node
675 // may not be dead if the replacement process recursively simplified to
676 // something else needing this node.
677 if (TLO.Old.getNode()->use_empty()) {
678 removeFromWorkList(TLO.Old.getNode());
680 // If the operands of this node are only used by the node, they will now
681 // be dead. Make sure to visit them first to delete dead nodes early.
682 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
683 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
684 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
686 DAG.DeleteNode(TLO.Old.getNode());
690 /// SimplifyDemandedBits - Check the specified integer node value to see if
691 /// it can be simplified or if things it uses can be simplified by bit
692 /// propagation. If so, return true.
693 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
694 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
695 APInt KnownZero, KnownOne;
696 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
700 AddToWorkList(Op.getNode());
702 // Replace the old value with the new one.
704 DEBUG(dbgs() << "\nReplacing.2 ";
705 TLO.Old.getNode()->dump(&DAG);
706 dbgs() << "\nWith: ";
707 TLO.New.getNode()->dump(&DAG);
710 CommitTargetLoweringOpt(TLO);
714 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
716 EVT VT = Load->getValueType(0);
717 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
719 DEBUG(dbgs() << "\nReplacing.9 ";
721 dbgs() << "\nWith: ";
722 Trunc.getNode()->dump(&DAG);
724 WorkListRemover DeadNodes(*this);
725 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
726 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
727 removeFromWorkList(Load);
728 DAG.DeleteNode(Load);
729 AddToWorkList(Trunc.getNode());
732 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
735 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
736 EVT MemVT = LD->getMemoryVT();
737 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
738 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
740 : LD->getExtensionType();
742 return DAG.getExtLoad(ExtType, dl, PVT,
743 LD->getChain(), LD->getBasePtr(),
744 LD->getPointerInfo(),
745 MemVT, LD->isVolatile(),
746 LD->isNonTemporal(), LD->getAlignment());
749 unsigned Opc = Op.getOpcode();
752 case ISD::AssertSext:
753 return DAG.getNode(ISD::AssertSext, dl, PVT,
754 SExtPromoteOperand(Op.getOperand(0), PVT),
756 case ISD::AssertZext:
757 return DAG.getNode(ISD::AssertZext, dl, PVT,
758 ZExtPromoteOperand(Op.getOperand(0), PVT),
760 case ISD::Constant: {
762 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
763 return DAG.getNode(ExtOpc, dl, PVT, Op);
767 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
769 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
772 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
773 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
775 EVT OldVT = Op.getValueType();
777 bool Replace = false;
778 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
779 if (NewOp.getNode() == 0)
781 AddToWorkList(NewOp.getNode());
784 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
785 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
786 DAG.getValueType(OldVT));
789 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
790 EVT OldVT = Op.getValueType();
792 bool Replace = false;
793 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
794 if (NewOp.getNode() == 0)
796 AddToWorkList(NewOp.getNode());
799 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
800 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
803 /// PromoteIntBinOp - Promote the specified integer binary operation if the
804 /// target indicates it is beneficial. e.g. On x86, it's usually better to
805 /// promote i16 operations to i32 since i16 instructions are longer.
806 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
807 if (!LegalOperations)
810 EVT VT = Op.getValueType();
811 if (VT.isVector() || !VT.isInteger())
814 // If operation type is 'undesirable', e.g. i16 on x86, consider
816 unsigned Opc = Op.getOpcode();
817 if (TLI.isTypeDesirableForOp(Opc, VT))
821 // Consult target whether it is a good idea to promote this operation and
822 // what's the right type to promote it to.
823 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
824 assert(PVT != VT && "Don't know what type to promote to!");
826 bool Replace0 = false;
827 SDValue N0 = Op.getOperand(0);
828 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
829 if (NN0.getNode() == 0)
832 bool Replace1 = false;
833 SDValue N1 = Op.getOperand(1);
838 NN1 = PromoteOperand(N1, PVT, Replace1);
839 if (NN1.getNode() == 0)
843 AddToWorkList(NN0.getNode());
845 AddToWorkList(NN1.getNode());
848 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
850 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
852 DEBUG(dbgs() << "\nPromoting ";
853 Op.getNode()->dump(&DAG));
855 return DAG.getNode(ISD::TRUNCATE, dl, VT,
856 DAG.getNode(Opc, dl, PVT, NN0, NN1));
861 /// PromoteIntShiftOp - Promote the specified integer shift operation if the
862 /// target indicates it is beneficial. e.g. On x86, it's usually better to
863 /// promote i16 operations to i32 since i16 instructions are longer.
864 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
865 if (!LegalOperations)
868 EVT VT = Op.getValueType();
869 if (VT.isVector() || !VT.isInteger())
872 // If operation type is 'undesirable', e.g. i16 on x86, consider
874 unsigned Opc = Op.getOpcode();
875 if (TLI.isTypeDesirableForOp(Opc, VT))
879 // Consult target whether it is a good idea to promote this operation and
880 // what's the right type to promote it to.
881 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
882 assert(PVT != VT && "Don't know what type to promote to!");
884 bool Replace = false;
885 SDValue N0 = Op.getOperand(0);
887 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
888 else if (Opc == ISD::SRL)
889 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
891 N0 = PromoteOperand(N0, PVT, Replace);
892 if (N0.getNode() == 0)
895 AddToWorkList(N0.getNode());
897 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
899 DEBUG(dbgs() << "\nPromoting ";
900 Op.getNode()->dump(&DAG));
902 return DAG.getNode(ISD::TRUNCATE, dl, VT,
903 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
908 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
909 if (!LegalOperations)
912 EVT VT = Op.getValueType();
913 if (VT.isVector() || !VT.isInteger())
916 // If operation type is 'undesirable', e.g. i16 on x86, consider
918 unsigned Opc = Op.getOpcode();
919 if (TLI.isTypeDesirableForOp(Opc, VT))
923 // Consult target whether it is a good idea to promote this operation and
924 // what's the right type to promote it to.
925 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
926 assert(PVT != VT && "Don't know what type to promote to!");
927 // fold (aext (aext x)) -> (aext x)
928 // fold (aext (zext x)) -> (zext x)
929 // fold (aext (sext x)) -> (sext x)
930 DEBUG(dbgs() << "\nPromoting ";
931 Op.getNode()->dump(&DAG));
932 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0));
937 bool DAGCombiner::PromoteLoad(SDValue Op) {
938 if (!LegalOperations)
941 EVT VT = Op.getValueType();
942 if (VT.isVector() || !VT.isInteger())
945 // If operation type is 'undesirable', e.g. i16 on x86, consider
947 unsigned Opc = Op.getOpcode();
948 if (TLI.isTypeDesirableForOp(Opc, VT))
952 // Consult target whether it is a good idea to promote this operation and
953 // what's the right type to promote it to.
954 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
955 assert(PVT != VT && "Don't know what type to promote to!");
958 SDNode *N = Op.getNode();
959 LoadSDNode *LD = cast<LoadSDNode>(N);
960 EVT MemVT = LD->getMemoryVT();
961 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
962 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
964 : LD->getExtensionType();
965 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
966 LD->getChain(), LD->getBasePtr(),
967 LD->getPointerInfo(),
968 MemVT, LD->isVolatile(),
969 LD->isNonTemporal(), LD->getAlignment());
970 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
972 DEBUG(dbgs() << "\nPromoting ";
975 Result.getNode()->dump(&DAG);
977 WorkListRemover DeadNodes(*this);
978 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
979 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
980 removeFromWorkList(N);
982 AddToWorkList(Result.getNode());
989 //===----------------------------------------------------------------------===//
990 // Main DAG Combiner implementation
991 //===----------------------------------------------------------------------===//
993 void DAGCombiner::Run(CombineLevel AtLevel) {
994 // set the instance variables, so that the various visit routines may use it.
996 LegalOperations = Level >= AfterLegalizeVectorOps;
997 LegalTypes = Level >= AfterLegalizeTypes;
999 // Add all the dag nodes to the worklist.
1000 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
1001 E = DAG.allnodes_end(); I != E; ++I)
1004 // Create a dummy node (which is not added to allnodes), that adds a reference
1005 // to the root node, preventing it from being deleted, and tracking any
1006 // changes of the root.
1007 HandleSDNode Dummy(DAG.getRoot());
1009 // The root of the dag may dangle to deleted nodes until the dag combiner is
1010 // done. Set it to null to avoid confusion.
1011 DAG.setRoot(SDValue());
1013 // while the worklist isn't empty, find a node and
1014 // try and combine it.
1015 while (!WorkListContents.empty()) {
1017 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates.
1018 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the
1019 // worklist *should* contain, and check the node we want to visit is should
1020 // actually be visited.
1022 N = WorkListOrder.pop_back_val();
1023 } while (!WorkListContents.erase(N));
1025 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1026 // N is deleted from the DAG, since they too may now be dead or may have a
1027 // reduced number of uses, allowing other xforms.
1028 if (N->use_empty() && N != &Dummy) {
1029 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1030 AddToWorkList(N->getOperand(i).getNode());
1036 SDValue RV = combine(N);
1038 if (RV.getNode() == 0)
1043 // If we get back the same node we passed in, rather than a new node or
1044 // zero, we know that the node must have defined multiple values and
1045 // CombineTo was used. Since CombineTo takes care of the worklist
1046 // mechanics for us, we have no work to do in this case.
1047 if (RV.getNode() == N)
1050 assert(N->getOpcode() != ISD::DELETED_NODE &&
1051 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1052 "Node was deleted but visit returned new node!");
1054 DEBUG(dbgs() << "\nReplacing.3 ";
1056 dbgs() << "\nWith: ";
1057 RV.getNode()->dump(&DAG);
1060 // Transfer debug value.
1061 DAG.TransferDbgValues(SDValue(N, 0), RV);
1062 WorkListRemover DeadNodes(*this);
1063 if (N->getNumValues() == RV.getNode()->getNumValues())
1064 DAG.ReplaceAllUsesWith(N, RV.getNode());
1066 assert(N->getValueType(0) == RV.getValueType() &&
1067 N->getNumValues() == 1 && "Type mismatch");
1069 DAG.ReplaceAllUsesWith(N, &OpV);
1072 // Push the new node and any users onto the worklist
1073 AddToWorkList(RV.getNode());
1074 AddUsersToWorkList(RV.getNode());
1076 // Add any uses of the old node to the worklist in case this node is the
1077 // last one that uses them. They may become dead after this node is
1079 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1080 AddToWorkList(N->getOperand(i).getNode());
1082 // Finally, if the node is now dead, remove it from the graph. The node
1083 // may not be dead if the replacement process recursively simplified to
1084 // something else needing this node.
1085 if (N->use_empty()) {
1086 // Nodes can be reintroduced into the worklist. Make sure we do not
1087 // process a node that has been replaced.
1088 removeFromWorkList(N);
1090 // Finally, since the node is now dead, remove it from the graph.
1095 // If the root changed (e.g. it was a dead load, update the root).
1096 DAG.setRoot(Dummy.getValue());
1097 DAG.RemoveDeadNodes();
1100 SDValue DAGCombiner::visit(SDNode *N) {
1101 switch (N->getOpcode()) {
1103 case ISD::TokenFactor: return visitTokenFactor(N);
1104 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1105 case ISD::ADD: return visitADD(N);
1106 case ISD::SUB: return visitSUB(N);
1107 case ISD::ADDC: return visitADDC(N);
1108 case ISD::SUBC: return visitSUBC(N);
1109 case ISD::ADDE: return visitADDE(N);
1110 case ISD::SUBE: return visitSUBE(N);
1111 case ISD::MUL: return visitMUL(N);
1112 case ISD::SDIV: return visitSDIV(N);
1113 case ISD::UDIV: return visitUDIV(N);
1114 case ISD::SREM: return visitSREM(N);
1115 case ISD::UREM: return visitUREM(N);
1116 case ISD::MULHU: return visitMULHU(N);
1117 case ISD::MULHS: return visitMULHS(N);
1118 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1119 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1120 case ISD::SMULO: return visitSMULO(N);
1121 case ISD::UMULO: return visitUMULO(N);
1122 case ISD::SDIVREM: return visitSDIVREM(N);
1123 case ISD::UDIVREM: return visitUDIVREM(N);
1124 case ISD::AND: return visitAND(N);
1125 case ISD::OR: return visitOR(N);
1126 case ISD::XOR: return visitXOR(N);
1127 case ISD::SHL: return visitSHL(N);
1128 case ISD::SRA: return visitSRA(N);
1129 case ISD::SRL: return visitSRL(N);
1130 case ISD::CTLZ: return visitCTLZ(N);
1131 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1132 case ISD::CTTZ: return visitCTTZ(N);
1133 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1134 case ISD::CTPOP: return visitCTPOP(N);
1135 case ISD::SELECT: return visitSELECT(N);
1136 case ISD::VSELECT: return visitVSELECT(N);
1137 case ISD::SELECT_CC: return visitSELECT_CC(N);
1138 case ISD::SETCC: return visitSETCC(N);
1139 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1140 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1141 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1142 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1143 case ISD::TRUNCATE: return visitTRUNCATE(N);
1144 case ISD::BITCAST: return visitBITCAST(N);
1145 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1146 case ISD::FADD: return visitFADD(N);
1147 case ISD::FSUB: return visitFSUB(N);
1148 case ISD::FMUL: return visitFMUL(N);
1149 case ISD::FMA: return visitFMA(N);
1150 case ISD::FDIV: return visitFDIV(N);
1151 case ISD::FREM: return visitFREM(N);
1152 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1153 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1154 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1155 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1156 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1157 case ISD::FP_ROUND: return visitFP_ROUND(N);
1158 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1159 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1160 case ISD::FNEG: return visitFNEG(N);
1161 case ISD::FABS: return visitFABS(N);
1162 case ISD::FFLOOR: return visitFFLOOR(N);
1163 case ISD::FCEIL: return visitFCEIL(N);
1164 case ISD::FTRUNC: return visitFTRUNC(N);
1165 case ISD::BRCOND: return visitBRCOND(N);
1166 case ISD::BR_CC: return visitBR_CC(N);
1167 case ISD::LOAD: return visitLOAD(N);
1168 case ISD::STORE: return visitSTORE(N);
1169 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1170 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1171 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1172 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1173 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1174 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1179 SDValue DAGCombiner::combine(SDNode *N) {
1180 SDValue RV = visit(N);
1182 // If nothing happened, try a target-specific DAG combine.
1183 if (RV.getNode() == 0) {
1184 assert(N->getOpcode() != ISD::DELETED_NODE &&
1185 "Node was deleted but visit returned NULL!");
1187 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1188 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1190 // Expose the DAG combiner to the target combiner impls.
1191 TargetLowering::DAGCombinerInfo
1192 DagCombineInfo(DAG, Level, false, this);
1194 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1198 // If nothing happened still, try promoting the operation.
1199 if (RV.getNode() == 0) {
1200 switch (N->getOpcode()) {
1208 RV = PromoteIntBinOp(SDValue(N, 0));
1213 RV = PromoteIntShiftOp(SDValue(N, 0));
1215 case ISD::SIGN_EXTEND:
1216 case ISD::ZERO_EXTEND:
1217 case ISD::ANY_EXTEND:
1218 RV = PromoteExtend(SDValue(N, 0));
1221 if (PromoteLoad(SDValue(N, 0)))
1227 // If N is a commutative binary node, try commuting it to enable more
1229 if (RV.getNode() == 0 &&
1230 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1231 N->getNumValues() == 1) {
1232 SDValue N0 = N->getOperand(0);
1233 SDValue N1 = N->getOperand(1);
1235 // Constant operands are canonicalized to RHS.
1236 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1237 SDValue Ops[] = { N1, N0 };
1238 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1241 return SDValue(CSENode, 0);
1248 /// getInputChainForNode - Given a node, return its input chain if it has one,
1249 /// otherwise return a null sd operand.
1250 static SDValue getInputChainForNode(SDNode *N) {
1251 if (unsigned NumOps = N->getNumOperands()) {
1252 if (N->getOperand(0).getValueType() == MVT::Other)
1253 return N->getOperand(0);
1254 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1255 return N->getOperand(NumOps-1);
1256 for (unsigned i = 1; i < NumOps-1; ++i)
1257 if (N->getOperand(i).getValueType() == MVT::Other)
1258 return N->getOperand(i);
1263 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1264 // If N has two operands, where one has an input chain equal to the other,
1265 // the 'other' chain is redundant.
1266 if (N->getNumOperands() == 2) {
1267 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1268 return N->getOperand(0);
1269 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1270 return N->getOperand(1);
1273 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1274 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1275 SmallPtrSet<SDNode*, 16> SeenOps;
1276 bool Changed = false; // If we should replace this token factor.
1278 // Start out with this token factor.
1281 // Iterate through token factors. The TFs grows when new token factors are
1283 for (unsigned i = 0; i < TFs.size(); ++i) {
1284 SDNode *TF = TFs[i];
1286 // Check each of the operands.
1287 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1288 SDValue Op = TF->getOperand(i);
1290 switch (Op.getOpcode()) {
1291 case ISD::EntryToken:
1292 // Entry tokens don't need to be added to the list. They are
1297 case ISD::TokenFactor:
1298 if (Op.hasOneUse() &&
1299 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1300 // Queue up for processing.
1301 TFs.push_back(Op.getNode());
1302 // Clean up in case the token factor is removed.
1303 AddToWorkList(Op.getNode());
1310 // Only add if it isn't already in the list.
1311 if (SeenOps.insert(Op.getNode()))
1322 // If we've change things around then replace token factor.
1325 // The entry token is the only possible outcome.
1326 Result = DAG.getEntryNode();
1328 // New and improved token factor.
1329 Result = DAG.getNode(ISD::TokenFactor, SDLoc(N),
1330 MVT::Other, &Ops[0], Ops.size());
1333 // Don't add users to work list.
1334 return CombineTo(N, Result, false);
1340 /// MERGE_VALUES can always be eliminated.
1341 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1342 WorkListRemover DeadNodes(*this);
1343 // Replacing results may cause a different MERGE_VALUES to suddenly
1344 // be CSE'd with N, and carry its uses with it. Iterate until no
1345 // uses remain, to ensure that the node can be safely deleted.
1346 // First add the users of this node to the work list so that they
1347 // can be tried again once they have new operands.
1348 AddUsersToWorkList(N);
1350 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1351 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i));
1352 } while (!N->use_empty());
1353 removeFromWorkList(N);
1355 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1359 SDValue combineShlAddConstant(SDLoc DL, SDValue N0, SDValue N1,
1360 SelectionDAG &DAG) {
1361 EVT VT = N0.getValueType();
1362 SDValue N00 = N0.getOperand(0);
1363 SDValue N01 = N0.getOperand(1);
1364 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1366 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1367 isa<ConstantSDNode>(N00.getOperand(1))) {
1368 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1369 N0 = DAG.getNode(ISD::ADD, SDLoc(N0), VT,
1370 DAG.getNode(ISD::SHL, SDLoc(N00), VT,
1371 N00.getOperand(0), N01),
1372 DAG.getNode(ISD::SHL, SDLoc(N01), VT,
1373 N00.getOperand(1), N01));
1374 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1380 SDValue DAGCombiner::visitADD(SDNode *N) {
1381 SDValue N0 = N->getOperand(0);
1382 SDValue N1 = N->getOperand(1);
1383 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1384 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1385 EVT VT = N0.getValueType();
1388 if (VT.isVector()) {
1389 SDValue FoldedVOp = SimplifyVBinOp(N);
1390 if (FoldedVOp.getNode()) return FoldedVOp;
1392 // fold (add x, 0) -> x, vector edition
1393 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1395 if (ISD::isBuildVectorAllZeros(N0.getNode()))
1399 // fold (add x, undef) -> undef
1400 if (N0.getOpcode() == ISD::UNDEF)
1402 if (N1.getOpcode() == ISD::UNDEF)
1404 // fold (add c1, c2) -> c1+c2
1406 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1407 // canonicalize constant to RHS
1409 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N1, N0);
1410 // fold (add x, 0) -> x
1411 if (N1C && N1C->isNullValue())
1413 // fold (add Sym, c) -> Sym+c
1414 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1415 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1416 GA->getOpcode() == ISD::GlobalAddress)
1417 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
1419 (uint64_t)N1C->getSExtValue());
1420 // fold ((c1-A)+c2) -> (c1+c2)-A
1421 if (N1C && N0.getOpcode() == ISD::SUB)
1422 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1423 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1424 DAG.getConstant(N1C->getAPIntValue()+
1425 N0C->getAPIntValue(), VT),
1428 SDValue RADD = ReassociateOps(ISD::ADD, SDLoc(N), N0, N1);
1429 if (RADD.getNode() != 0)
1431 // fold ((0-A) + B) -> B-A
1432 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1433 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1434 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1, N0.getOperand(1));
1435 // fold (A + (0-B)) -> A-B
1436 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1437 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1438 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1.getOperand(1));
1439 // fold (A+(B-A)) -> B
1440 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1441 return N1.getOperand(0);
1442 // fold ((B-A)+A) -> B
1443 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1444 return N0.getOperand(0);
1445 // fold (A+(B-(A+C))) to (B-C)
1446 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1447 N0 == N1.getOperand(1).getOperand(0))
1448 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
1449 N1.getOperand(1).getOperand(1));
1450 // fold (A+(B-(C+A))) to (B-C)
1451 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1452 N0 == N1.getOperand(1).getOperand(1))
1453 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
1454 N1.getOperand(1).getOperand(0));
1455 // fold (A+((B-A)+or-C)) to (B+or-C)
1456 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1457 N1.getOperand(0).getOpcode() == ISD::SUB &&
1458 N0 == N1.getOperand(0).getOperand(1))
1459 return DAG.getNode(N1.getOpcode(), SDLoc(N), VT,
1460 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1462 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1463 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1464 SDValue N00 = N0.getOperand(0);
1465 SDValue N01 = N0.getOperand(1);
1466 SDValue N10 = N1.getOperand(0);
1467 SDValue N11 = N1.getOperand(1);
1469 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1470 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1471 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10),
1472 DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11));
1475 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1476 return SDValue(N, 0);
1478 // fold (a+b) -> (a|b) iff a and b share no bits.
1479 if (VT.isInteger() && !VT.isVector()) {
1480 APInt LHSZero, LHSOne;
1481 APInt RHSZero, RHSOne;
1482 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne);
1484 if (LHSZero.getBoolValue()) {
1485 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne);
1487 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1488 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1489 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1490 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1);
1494 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1495 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1496 SDValue Result = combineShlAddConstant(SDLoc(N), N0, N1, DAG);
1497 if (Result.getNode()) return Result;
1499 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1500 SDValue Result = combineShlAddConstant(SDLoc(N), N1, N0, DAG);
1501 if (Result.getNode()) return Result;
1504 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1505 if (N1.getOpcode() == ISD::SHL &&
1506 N1.getOperand(0).getOpcode() == ISD::SUB)
1507 if (ConstantSDNode *C =
1508 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1509 if (C->getAPIntValue() == 0)
1510 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0,
1511 DAG.getNode(ISD::SHL, SDLoc(N), VT,
1512 N1.getOperand(0).getOperand(1),
1514 if (N0.getOpcode() == ISD::SHL &&
1515 N0.getOperand(0).getOpcode() == ISD::SUB)
1516 if (ConstantSDNode *C =
1517 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1518 if (C->getAPIntValue() == 0)
1519 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1,
1520 DAG.getNode(ISD::SHL, SDLoc(N), VT,
1521 N0.getOperand(0).getOperand(1),
1524 if (N1.getOpcode() == ISD::AND) {
1525 SDValue AndOp0 = N1.getOperand(0);
1526 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1527 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1528 unsigned DestBits = VT.getScalarType().getSizeInBits();
1530 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1531 // and similar xforms where the inner op is either ~0 or 0.
1532 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1534 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1538 // add (sext i1), X -> sub X, (zext i1)
1539 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1540 N0.getOperand(0).getValueType() == MVT::i1 &&
1541 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1543 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1544 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1550 SDValue DAGCombiner::visitADDC(SDNode *N) {
1551 SDValue N0 = N->getOperand(0);
1552 SDValue N1 = N->getOperand(1);
1553 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1554 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1555 EVT VT = N0.getValueType();
1557 // If the flag result is dead, turn this into an ADD.
1558 if (!N->hasAnyUseOfValue(1))
1559 return CombineTo(N, DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N1),
1560 DAG.getNode(ISD::CARRY_FALSE,
1561 SDLoc(N), MVT::Glue));
1563 // canonicalize constant to RHS.
1565 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N1, N0);
1567 // fold (addc x, 0) -> x + no carry out
1568 if (N1C && N1C->isNullValue())
1569 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1570 SDLoc(N), MVT::Glue));
1572 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1573 APInt LHSZero, LHSOne;
1574 APInt RHSZero, RHSOne;
1575 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne);
1577 if (LHSZero.getBoolValue()) {
1578 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne);
1580 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1581 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1582 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1583 return CombineTo(N, DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1),
1584 DAG.getNode(ISD::CARRY_FALSE,
1585 SDLoc(N), MVT::Glue));
1591 SDValue DAGCombiner::visitADDE(SDNode *N) {
1592 SDValue N0 = N->getOperand(0);
1593 SDValue N1 = N->getOperand(1);
1594 SDValue CarryIn = N->getOperand(2);
1595 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1596 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1598 // canonicalize constant to RHS
1600 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
1603 // fold (adde x, y, false) -> (addc x, y)
1604 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1605 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
1610 // Since it may not be valid to emit a fold to zero for vector initializers
1611 // check if we can before folding.
1612 static SDValue tryFoldToZero(SDLoc DL, const TargetLowering &TLI, EVT VT,
1613 SelectionDAG &DAG, bool LegalOperations) {
1614 if (!VT.isVector()) {
1615 return DAG.getConstant(0, VT);
1617 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1618 // Produce a vector of zeros.
1619 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
1620 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
1621 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
1622 &Ops[0], Ops.size());
1627 SDValue DAGCombiner::visitSUB(SDNode *N) {
1628 SDValue N0 = N->getOperand(0);
1629 SDValue N1 = N->getOperand(1);
1630 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1631 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1632 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 :
1633 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1634 EVT VT = N0.getValueType();
1637 if (VT.isVector()) {
1638 SDValue FoldedVOp = SimplifyVBinOp(N);
1639 if (FoldedVOp.getNode()) return FoldedVOp;
1641 // fold (sub x, 0) -> x, vector edition
1642 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1646 // fold (sub x, x) -> 0
1647 // FIXME: Refactor this and xor and other similar operations together.
1649 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations);
1650 // fold (sub c1, c2) -> c1-c2
1652 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1653 // fold (sub x, c) -> (add x, -c)
1655 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0,
1656 DAG.getConstant(-N1C->getAPIntValue(), VT));
1657 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1658 if (N0C && N0C->isAllOnesValue())
1659 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
1660 // fold A-(A-B) -> B
1661 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1662 return N1.getOperand(1);
1663 // fold (A+B)-A -> B
1664 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1665 return N0.getOperand(1);
1666 // fold (A+B)-B -> A
1667 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1668 return N0.getOperand(0);
1669 // fold C2-(A+C1) -> (C2-C1)-A
1670 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1671 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(),
1673 return DAG.getNode(ISD::SUB, SDLoc(N), VT, NewC,
1676 // fold ((A+(B+or-C))-B) -> A+or-C
1677 if (N0.getOpcode() == ISD::ADD &&
1678 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1679 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1680 N0.getOperand(1).getOperand(0) == N1)
1681 return DAG.getNode(N0.getOperand(1).getOpcode(), SDLoc(N), VT,
1682 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1683 // fold ((A+(C+B))-B) -> A+C
1684 if (N0.getOpcode() == ISD::ADD &&
1685 N0.getOperand(1).getOpcode() == ISD::ADD &&
1686 N0.getOperand(1).getOperand(1) == N1)
1687 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
1688 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1689 // fold ((A-(B-C))-C) -> A-B
1690 if (N0.getOpcode() == ISD::SUB &&
1691 N0.getOperand(1).getOpcode() == ISD::SUB &&
1692 N0.getOperand(1).getOperand(1) == N1)
1693 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1694 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1696 // If either operand of a sub is undef, the result is undef
1697 if (N0.getOpcode() == ISD::UNDEF)
1699 if (N1.getOpcode() == ISD::UNDEF)
1702 // If the relocation model supports it, consider symbol offsets.
1703 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1704 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1705 // fold (sub Sym, c) -> Sym-c
1706 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1707 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
1709 (uint64_t)N1C->getSExtValue());
1710 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1711 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1712 if (GA->getGlobal() == GB->getGlobal())
1713 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1720 SDValue DAGCombiner::visitSUBC(SDNode *N) {
1721 SDValue N0 = N->getOperand(0);
1722 SDValue N1 = N->getOperand(1);
1723 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1724 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1725 EVT VT = N0.getValueType();
1727 // If the flag result is dead, turn this into an SUB.
1728 if (!N->hasAnyUseOfValue(1))
1729 return CombineTo(N, DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1),
1730 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1733 // fold (subc x, x) -> 0 + no borrow
1735 return CombineTo(N, DAG.getConstant(0, VT),
1736 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1739 // fold (subc x, 0) -> x + no borrow
1740 if (N1C && N1C->isNullValue())
1741 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1744 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
1745 if (N0C && N0C->isAllOnesValue())
1746 return CombineTo(N, DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0),
1747 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1753 SDValue DAGCombiner::visitSUBE(SDNode *N) {
1754 SDValue N0 = N->getOperand(0);
1755 SDValue N1 = N->getOperand(1);
1756 SDValue CarryIn = N->getOperand(2);
1758 // fold (sube x, y, false) -> (subc x, y)
1759 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1760 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);
1765 SDValue DAGCombiner::visitMUL(SDNode *N) {
1766 SDValue N0 = N->getOperand(0);
1767 SDValue N1 = N->getOperand(1);
1768 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1769 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1770 EVT VT = N0.getValueType();
1773 if (VT.isVector()) {
1774 SDValue FoldedVOp = SimplifyVBinOp(N);
1775 if (FoldedVOp.getNode()) return FoldedVOp;
1778 // fold (mul x, undef) -> 0
1779 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1780 return DAG.getConstant(0, VT);
1781 // fold (mul c1, c2) -> c1*c2
1783 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1784 // canonicalize constant to RHS
1786 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
1787 // fold (mul x, 0) -> 0
1788 if (N1C && N1C->isNullValue())
1790 // fold (mul x, -1) -> 0-x
1791 if (N1C && N1C->isAllOnesValue())
1792 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1793 DAG.getConstant(0, VT), N0);
1794 // fold (mul x, (1 << c)) -> x << c
1795 if (N1C && N1C->getAPIntValue().isPowerOf2())
1796 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
1797 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1798 getShiftAmountTy(N0.getValueType())));
1799 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1800 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1801 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1802 // FIXME: If the input is something that is easily negated (e.g. a
1803 // single-use add), we should put the negate there.
1804 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1805 DAG.getConstant(0, VT),
1806 DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
1807 DAG.getConstant(Log2Val,
1808 getShiftAmountTy(N0.getValueType()))));
1810 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1811 if (N1C && N0.getOpcode() == ISD::SHL &&
1812 isa<ConstantSDNode>(N0.getOperand(1))) {
1813 SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT,
1814 N1, N0.getOperand(1));
1815 AddToWorkList(C3.getNode());
1816 return DAG.getNode(ISD::MUL, SDLoc(N), VT,
1817 N0.getOperand(0), C3);
1820 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1823 SDValue Sh(0,0), Y(0,0);
1824 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1825 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1826 N0.getNode()->hasOneUse()) {
1828 } else if (N1.getOpcode() == ISD::SHL &&
1829 isa<ConstantSDNode>(N1.getOperand(1)) &&
1830 N1.getNode()->hasOneUse()) {
1835 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
1836 Sh.getOperand(0), Y);
1837 return DAG.getNode(ISD::SHL, SDLoc(N), VT,
1838 Mul, Sh.getOperand(1));
1842 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1843 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1844 isa<ConstantSDNode>(N0.getOperand(1)))
1845 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
1846 DAG.getNode(ISD::MUL, SDLoc(N0), VT,
1847 N0.getOperand(0), N1),
1848 DAG.getNode(ISD::MUL, SDLoc(N1), VT,
1849 N0.getOperand(1), N1));
1852 SDValue RMUL = ReassociateOps(ISD::MUL, SDLoc(N), N0, N1);
1853 if (RMUL.getNode() != 0)
1859 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1860 SDValue N0 = N->getOperand(0);
1861 SDValue N1 = N->getOperand(1);
1862 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1863 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1864 EVT VT = N->getValueType(0);
1867 if (VT.isVector()) {
1868 SDValue FoldedVOp = SimplifyVBinOp(N);
1869 if (FoldedVOp.getNode()) return FoldedVOp;
1872 // fold (sdiv c1, c2) -> c1/c2
1873 if (N0C && N1C && !N1C->isNullValue())
1874 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1875 // fold (sdiv X, 1) -> X
1876 if (N1C && N1C->getAPIntValue() == 1LL)
1878 // fold (sdiv X, -1) -> 0-X
1879 if (N1C && N1C->isAllOnesValue())
1880 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1881 DAG.getConstant(0, VT), N0);
1882 // If we know the sign bits of both operands are zero, strength reduce to a
1883 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1884 if (!VT.isVector()) {
1885 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1886 return DAG.getNode(ISD::UDIV, SDLoc(N), N1.getValueType(),
1889 // fold (sdiv X, pow2) -> simple ops after legalize
1890 if (N1C && !N1C->isNullValue() &&
1891 (N1C->getAPIntValue().isPowerOf2() ||
1892 (-N1C->getAPIntValue()).isPowerOf2())) {
1893 // If dividing by powers of two is cheap, then don't perform the following
1895 if (TLI.isPow2DivCheap())
1898 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
1900 // Splat the sign bit into the register
1901 SDValue SGN = DAG.getNode(ISD::SRA, SDLoc(N), VT, N0,
1902 DAG.getConstant(VT.getSizeInBits()-1,
1903 getShiftAmountTy(N0.getValueType())));
1904 AddToWorkList(SGN.getNode());
1906 // Add (N0 < 0) ? abs2 - 1 : 0;
1907 SDValue SRL = DAG.getNode(ISD::SRL, SDLoc(N), VT, SGN,
1908 DAG.getConstant(VT.getSizeInBits() - lg2,
1909 getShiftAmountTy(SGN.getValueType())));
1910 SDValue ADD = DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, SRL);
1911 AddToWorkList(SRL.getNode());
1912 AddToWorkList(ADD.getNode()); // Divide by pow2
1913 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), VT, ADD,
1914 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
1916 // If we're dividing by a positive value, we're done. Otherwise, we must
1917 // negate the result.
1918 if (N1C->getAPIntValue().isNonNegative())
1921 AddToWorkList(SRA.getNode());
1922 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1923 DAG.getConstant(0, VT), SRA);
1926 // if integer divide is expensive and we satisfy the requirements, emit an
1927 // alternate sequence.
1928 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1929 SDValue Op = BuildSDIV(N);
1930 if (Op.getNode()) return Op;
1934 if (N0.getOpcode() == ISD::UNDEF)
1935 return DAG.getConstant(0, VT);
1936 // X / undef -> undef
1937 if (N1.getOpcode() == ISD::UNDEF)
1943 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1944 SDValue N0 = N->getOperand(0);
1945 SDValue N1 = N->getOperand(1);
1946 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1947 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1948 EVT VT = N->getValueType(0);
1951 if (VT.isVector()) {
1952 SDValue FoldedVOp = SimplifyVBinOp(N);
1953 if (FoldedVOp.getNode()) return FoldedVOp;
1956 // fold (udiv c1, c2) -> c1/c2
1957 if (N0C && N1C && !N1C->isNullValue())
1958 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1959 // fold (udiv x, (1 << c)) -> x >>u c
1960 if (N1C && N1C->getAPIntValue().isPowerOf2())
1961 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0,
1962 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1963 getShiftAmountTy(N0.getValueType())));
1964 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1965 if (N1.getOpcode() == ISD::SHL) {
1966 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1967 if (SHC->getAPIntValue().isPowerOf2()) {
1968 EVT ADDVT = N1.getOperand(1).getValueType();
1969 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N), ADDVT,
1971 DAG.getConstant(SHC->getAPIntValue()
1974 AddToWorkList(Add.getNode());
1975 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, Add);
1979 // fold (udiv x, c) -> alternate
1980 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1981 SDValue Op = BuildUDIV(N);
1982 if (Op.getNode()) return Op;
1986 if (N0.getOpcode() == ISD::UNDEF)
1987 return DAG.getConstant(0, VT);
1988 // X / undef -> undef
1989 if (N1.getOpcode() == ISD::UNDEF)
1995 SDValue DAGCombiner::visitSREM(SDNode *N) {
1996 SDValue N0 = N->getOperand(0);
1997 SDValue N1 = N->getOperand(1);
1998 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1999 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2000 EVT VT = N->getValueType(0);
2002 // fold (srem c1, c2) -> c1%c2
2003 if (N0C && N1C && !N1C->isNullValue())
2004 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
2005 // If we know the sign bits of both operands are zero, strength reduce to a
2006 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
2007 if (!VT.isVector()) {
2008 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2009 return DAG.getNode(ISD::UREM, SDLoc(N), VT, N0, N1);
2012 // If X/C can be simplified by the division-by-constant logic, lower
2013 // X%C to the equivalent of X-X/C*C.
2014 if (N1C && !N1C->isNullValue()) {
2015 SDValue Div = DAG.getNode(ISD::SDIV, SDLoc(N), VT, N0, N1);
2016 AddToWorkList(Div.getNode());
2017 SDValue OptimizedDiv = combine(Div.getNode());
2018 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2019 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2021 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2022 AddToWorkList(Mul.getNode());
2028 if (N0.getOpcode() == ISD::UNDEF)
2029 return DAG.getConstant(0, VT);
2030 // X % undef -> undef
2031 if (N1.getOpcode() == ISD::UNDEF)
2037 SDValue DAGCombiner::visitUREM(SDNode *N) {
2038 SDValue N0 = N->getOperand(0);
2039 SDValue N1 = N->getOperand(1);
2040 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2041 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2042 EVT VT = N->getValueType(0);
2044 // fold (urem c1, c2) -> c1%c2
2045 if (N0C && N1C && !N1C->isNullValue())
2046 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
2047 // fold (urem x, pow2) -> (and x, pow2-1)
2048 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
2049 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0,
2050 DAG.getConstant(N1C->getAPIntValue()-1,VT));
2051 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
2052 if (N1.getOpcode() == ISD::SHL) {
2053 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2054 if (SHC->getAPIntValue().isPowerOf2()) {
2056 DAG.getNode(ISD::ADD, SDLoc(N), VT, N1,
2057 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
2059 AddToWorkList(Add.getNode());
2060 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, Add);
2065 // If X/C can be simplified by the division-by-constant logic, lower
2066 // X%C to the equivalent of X-X/C*C.
2067 if (N1C && !N1C->isNullValue()) {
2068 SDValue Div = DAG.getNode(ISD::UDIV, SDLoc(N), VT, N0, N1);
2069 AddToWorkList(Div.getNode());
2070 SDValue OptimizedDiv = combine(Div.getNode());
2071 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2072 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2074 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2075 AddToWorkList(Mul.getNode());
2081 if (N0.getOpcode() == ISD::UNDEF)
2082 return DAG.getConstant(0, VT);
2083 // X % undef -> undef
2084 if (N1.getOpcode() == ISD::UNDEF)
2090 SDValue DAGCombiner::visitMULHS(SDNode *N) {
2091 SDValue N0 = N->getOperand(0);
2092 SDValue N1 = N->getOperand(1);
2093 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2094 EVT VT = N->getValueType(0);
2097 // fold (mulhs x, 0) -> 0
2098 if (N1C && N1C->isNullValue())
2100 // fold (mulhs x, 1) -> (sra x, size(x)-1)
2101 if (N1C && N1C->getAPIntValue() == 1)
2102 return DAG.getNode(ISD::SRA, SDLoc(N), N0.getValueType(), N0,
2103 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2104 getShiftAmountTy(N0.getValueType())));
2105 // fold (mulhs x, undef) -> 0
2106 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2107 return DAG.getConstant(0, VT);
2109 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2111 if (VT.isSimple() && !VT.isVector()) {
2112 MVT Simple = VT.getSimpleVT();
2113 unsigned SimpleSize = Simple.getSizeInBits();
2114 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2115 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2116 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2117 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2118 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2119 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2120 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2121 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2128 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2129 SDValue N0 = N->getOperand(0);
2130 SDValue N1 = N->getOperand(1);
2131 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2132 EVT VT = N->getValueType(0);
2135 // fold (mulhu x, 0) -> 0
2136 if (N1C && N1C->isNullValue())
2138 // fold (mulhu x, 1) -> 0
2139 if (N1C && N1C->getAPIntValue() == 1)
2140 return DAG.getConstant(0, N0.getValueType());
2141 // fold (mulhu x, undef) -> 0
2142 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2143 return DAG.getConstant(0, VT);
2145 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2147 if (VT.isSimple() && !VT.isVector()) {
2148 MVT Simple = VT.getSimpleVT();
2149 unsigned SimpleSize = Simple.getSizeInBits();
2150 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2151 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2152 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2153 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2154 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2155 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2156 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2157 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2164 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
2165 /// compute two values. LoOp and HiOp give the opcodes for the two computations
2166 /// that are being performed. Return true if a simplification was made.
2168 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2170 // If the high half is not needed, just compute the low half.
2171 bool HiExists = N->hasAnyUseOfValue(1);
2173 (!LegalOperations ||
2174 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
2175 SDValue Res = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0),
2176 N->op_begin(), N->getNumOperands());
2177 return CombineTo(N, Res, Res);
2180 // If the low half is not needed, just compute the high half.
2181 bool LoExists = N->hasAnyUseOfValue(0);
2183 (!LegalOperations ||
2184 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2185 SDValue Res = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1),
2186 N->op_begin(), N->getNumOperands());
2187 return CombineTo(N, Res, Res);
2190 // If both halves are used, return as it is.
2191 if (LoExists && HiExists)
2194 // If the two computed results can be simplified separately, separate them.
2196 SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0),
2197 N->op_begin(), N->getNumOperands());
2198 AddToWorkList(Lo.getNode());
2199 SDValue LoOpt = combine(Lo.getNode());
2200 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2201 (!LegalOperations ||
2202 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2203 return CombineTo(N, LoOpt, LoOpt);
2207 SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1),
2208 N->op_begin(), N->getNumOperands());
2209 AddToWorkList(Hi.getNode());
2210 SDValue HiOpt = combine(Hi.getNode());
2211 if (HiOpt.getNode() && HiOpt != Hi &&
2212 (!LegalOperations ||
2213 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2214 return CombineTo(N, HiOpt, HiOpt);
2220 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2221 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2222 if (Res.getNode()) return Res;
2224 EVT VT = N->getValueType(0);
2227 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2229 if (VT.isSimple() && !VT.isVector()) {
2230 MVT Simple = VT.getSimpleVT();
2231 unsigned SimpleSize = Simple.getSizeInBits();
2232 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2233 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2234 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2235 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2236 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2237 // Compute the high part as N1.
2238 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2239 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2240 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2241 // Compute the low part as N0.
2242 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2243 return CombineTo(N, Lo, Hi);
2250 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2251 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2252 if (Res.getNode()) return Res;
2254 EVT VT = N->getValueType(0);
2257 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2259 if (VT.isSimple() && !VT.isVector()) {
2260 MVT Simple = VT.getSimpleVT();
2261 unsigned SimpleSize = Simple.getSizeInBits();
2262 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2263 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2264 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2265 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2266 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2267 // Compute the high part as N1.
2268 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2269 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2270 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2271 // Compute the low part as N0.
2272 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2273 return CombineTo(N, Lo, Hi);
2280 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2281 // (smulo x, 2) -> (saddo x, x)
2282 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2283 if (C2->getAPIntValue() == 2)
2284 return DAG.getNode(ISD::SADDO, SDLoc(N), N->getVTList(),
2285 N->getOperand(0), N->getOperand(0));
2290 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2291 // (umulo x, 2) -> (uaddo x, x)
2292 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2293 if (C2->getAPIntValue() == 2)
2294 return DAG.getNode(ISD::UADDO, SDLoc(N), N->getVTList(),
2295 N->getOperand(0), N->getOperand(0));
2300 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2301 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2302 if (Res.getNode()) return Res;
2307 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2308 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2309 if (Res.getNode()) return Res;
2314 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2315 /// two operands of the same opcode, try to simplify it.
2316 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2317 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2318 EVT VT = N0.getValueType();
2319 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2321 // Bail early if none of these transforms apply.
2322 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2324 // For each of OP in AND/OR/XOR:
2325 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2326 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2327 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2328 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2330 // do not sink logical op inside of a vector extend, since it may combine
2332 EVT Op0VT = N0.getOperand(0).getValueType();
2333 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2334 N0.getOpcode() == ISD::SIGN_EXTEND ||
2335 // Avoid infinite looping with PromoteIntBinOp.
2336 (N0.getOpcode() == ISD::ANY_EXTEND &&
2337 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2338 (N0.getOpcode() == ISD::TRUNCATE &&
2339 (!TLI.isZExtFree(VT, Op0VT) ||
2340 !TLI.isTruncateFree(Op0VT, VT)) &&
2341 TLI.isTypeLegal(Op0VT))) &&
2343 Op0VT == N1.getOperand(0).getValueType() &&
2344 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2345 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2346 N0.getOperand(0).getValueType(),
2347 N0.getOperand(0), N1.getOperand(0));
2348 AddToWorkList(ORNode.getNode());
2349 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, ORNode);
2352 // For each of OP in SHL/SRL/SRA/AND...
2353 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2354 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2355 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2356 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2357 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2358 N0.getOperand(1) == N1.getOperand(1)) {
2359 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2360 N0.getOperand(0).getValueType(),
2361 N0.getOperand(0), N1.getOperand(0));
2362 AddToWorkList(ORNode.getNode());
2363 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
2364 ORNode, N0.getOperand(1));
2367 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
2368 // Only perform this optimization after type legalization and before
2369 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
2370 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
2371 // we don't want to undo this promotion.
2372 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
2374 if ((N0.getOpcode() == ISD::BITCAST ||
2375 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) &&
2376 Level == AfterLegalizeTypes) {
2377 SDValue In0 = N0.getOperand(0);
2378 SDValue In1 = N1.getOperand(0);
2379 EVT In0Ty = In0.getValueType();
2380 EVT In1Ty = In1.getValueType();
2382 // If both incoming values are integers, and the original types are the
2384 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) {
2385 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1);
2386 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op);
2387 AddToWorkList(Op.getNode());
2392 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
2393 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
2394 // If both shuffles use the same mask, and both shuffle within a single
2395 // vector, then it is worthwhile to move the swizzle after the operation.
2396 // The type-legalizer generates this pattern when loading illegal
2397 // vector types from memory. In many cases this allows additional shuffle
2399 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
2400 N0.getOperand(1).getOpcode() == ISD::UNDEF &&
2401 N1.getOperand(1).getOpcode() == ISD::UNDEF) {
2402 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
2403 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
2405 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() &&
2406 "Inputs to shuffles are not the same type");
2408 unsigned NumElts = VT.getVectorNumElements();
2410 // Check that both shuffles use the same mask. The masks are known to be of
2411 // the same length because the result vector type is the same.
2412 bool SameMask = true;
2413 for (unsigned i = 0; i != NumElts; ++i) {
2414 int Idx0 = SVN0->getMaskElt(i);
2415 int Idx1 = SVN1->getMaskElt(i);
2423 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
2424 N0.getOperand(0), N1.getOperand(0));
2425 AddToWorkList(Op.getNode());
2426 return DAG.getVectorShuffle(VT, SDLoc(N), Op,
2427 DAG.getUNDEF(VT), &SVN0->getMask()[0]);
2434 SDValue DAGCombiner::visitAND(SDNode *N) {
2435 SDValue N0 = N->getOperand(0);
2436 SDValue N1 = N->getOperand(1);
2437 SDValue LL, LR, RL, RR, CC0, CC1;
2438 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2439 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2440 EVT VT = N1.getValueType();
2441 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2444 if (VT.isVector()) {
2445 SDValue FoldedVOp = SimplifyVBinOp(N);
2446 if (FoldedVOp.getNode()) return FoldedVOp;
2448 // fold (and x, 0) -> 0, vector edition
2449 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2451 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2454 // fold (and x, -1) -> x, vector edition
2455 if (ISD::isBuildVectorAllOnes(N0.getNode()))
2457 if (ISD::isBuildVectorAllOnes(N1.getNode()))
2461 // fold (and x, undef) -> 0
2462 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2463 return DAG.getConstant(0, VT);
2464 // fold (and c1, c2) -> c1&c2
2466 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2467 // canonicalize constant to RHS
2469 return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
2470 // fold (and x, -1) -> x
2471 if (N1C && N1C->isAllOnesValue())
2473 // if (and x, c) is known to be zero, return 0
2474 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2475 APInt::getAllOnesValue(BitWidth)))
2476 return DAG.getConstant(0, VT);
2478 SDValue RAND = ReassociateOps(ISD::AND, SDLoc(N), N0, N1);
2479 if (RAND.getNode() != 0)
2481 // fold (and (or x, C), D) -> D if (C & D) == D
2482 if (N1C && N0.getOpcode() == ISD::OR)
2483 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2484 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2486 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2487 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2488 SDValue N0Op0 = N0.getOperand(0);
2489 APInt Mask = ~N1C->getAPIntValue();
2490 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2491 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2492 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
2493 N0.getValueType(), N0Op0);
2495 // Replace uses of the AND with uses of the Zero extend node.
2498 // We actually want to replace all uses of the any_extend with the
2499 // zero_extend, to avoid duplicating things. This will later cause this
2500 // AND to be folded.
2501 CombineTo(N0.getNode(), Zext);
2502 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2505 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
2506 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
2507 // already be zero by virtue of the width of the base type of the load.
2509 // the 'X' node here can either be nothing or an extract_vector_elt to catch
2511 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
2512 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
2513 N0.getOpcode() == ISD::LOAD) {
2514 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
2515 N0 : N0.getOperand(0) );
2517 // Get the constant (if applicable) the zero'th operand is being ANDed with.
2518 // This can be a pure constant or a vector splat, in which case we treat the
2519 // vector as a scalar and use the splat value.
2520 APInt Constant = APInt::getNullValue(1);
2521 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
2522 Constant = C->getAPIntValue();
2523 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
2524 APInt SplatValue, SplatUndef;
2525 unsigned SplatBitSize;
2527 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
2528 SplatBitSize, HasAnyUndefs);
2530 // Undef bits can contribute to a possible optimisation if set, so
2532 SplatValue |= SplatUndef;
2534 // The splat value may be something like "0x00FFFFFF", which means 0 for
2535 // the first vector value and FF for the rest, repeating. We need a mask
2536 // that will apply equally to all members of the vector, so AND all the
2537 // lanes of the constant together.
2538 EVT VT = Vector->getValueType(0);
2539 unsigned BitWidth = VT.getVectorElementType().getSizeInBits();
2541 // If the splat value has been compressed to a bitlength lower
2542 // than the size of the vector lane, we need to re-expand it to
2544 if (BitWidth > SplatBitSize)
2545 for (SplatValue = SplatValue.zextOrTrunc(BitWidth);
2546 SplatBitSize < BitWidth;
2547 SplatBitSize = SplatBitSize * 2)
2548 SplatValue |= SplatValue.shl(SplatBitSize);
2550 Constant = APInt::getAllOnesValue(BitWidth);
2551 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i)
2552 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
2556 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
2557 // actually legal and isn't going to get expanded, else this is a false
2559 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
2560 Load->getMemoryVT());
2562 // Resize the constant to the same size as the original memory access before
2563 // extension. If it is still the AllOnesValue then this AND is completely
2566 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits());
2569 switch (Load->getExtensionType()) {
2570 default: B = false; break;
2571 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
2573 case ISD::NON_EXTLOAD: B = true; break;
2576 if (B && Constant.isAllOnesValue()) {
2577 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
2578 // preserve semantics once we get rid of the AND.
2579 SDValue NewLoad(Load, 0);
2580 if (Load->getExtensionType() == ISD::EXTLOAD) {
2581 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
2582 Load->getValueType(0), SDLoc(Load),
2583 Load->getChain(), Load->getBasePtr(),
2584 Load->getOffset(), Load->getMemoryVT(),
2585 Load->getMemOperand());
2586 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
2587 if (Load->getNumValues() == 3) {
2588 // PRE/POST_INC loads have 3 values.
2589 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
2590 NewLoad.getValue(2) };
2591 CombineTo(Load, To, 3, true);
2593 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
2597 // Fold the AND away, taking care not to fold to the old load node if we
2599 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
2601 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2604 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2605 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2606 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2607 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2609 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2610 LL.getValueType().isInteger()) {
2611 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2612 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2613 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2614 LR.getValueType(), LL, RL);
2615 AddToWorkList(ORNode.getNode());
2616 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
2618 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2619 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2620 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(N0),
2621 LR.getValueType(), LL, RL);
2622 AddToWorkList(ANDNode.getNode());
2623 return DAG.getSetCC(SDLoc(N), VT, ANDNode, LR, Op1);
2625 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2626 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2627 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2628 LR.getValueType(), LL, RL);
2629 AddToWorkList(ORNode.getNode());
2630 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
2633 // canonicalize equivalent to ll == rl
2634 if (LL == RR && LR == RL) {
2635 Op1 = ISD::getSetCCSwappedOperands(Op1);
2638 if (LL == RL && LR == RR) {
2639 bool isInteger = LL.getValueType().isInteger();
2640 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2641 if (Result != ISD::SETCC_INVALID &&
2642 (!LegalOperations ||
2643 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
2644 TLI.isOperationLegal(ISD::SETCC,
2645 getSetCCResultType(N0.getSimpleValueType())))))
2646 return DAG.getSetCC(SDLoc(N), N0.getValueType(),
2651 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2652 if (N0.getOpcode() == N1.getOpcode()) {
2653 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2654 if (Tmp.getNode()) return Tmp;
2657 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2658 // fold (and (sra)) -> (and (srl)) when possible.
2659 if (!VT.isVector() &&
2660 SimplifyDemandedBits(SDValue(N, 0)))
2661 return SDValue(N, 0);
2663 // fold (zext_inreg (extload x)) -> (zextload x)
2664 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2665 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2666 EVT MemVT = LN0->getMemoryVT();
2667 // If we zero all the possible extended bits, then we can turn this into
2668 // a zextload if we are running before legalize or the operation is legal.
2669 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2670 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2671 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2672 ((!LegalOperations && !LN0->isVolatile()) ||
2673 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2674 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
2675 LN0->getChain(), LN0->getBasePtr(),
2676 LN0->getPointerInfo(), MemVT,
2677 LN0->isVolatile(), LN0->isNonTemporal(),
2678 LN0->getAlignment());
2680 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2681 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2684 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2685 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2687 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2688 EVT MemVT = LN0->getMemoryVT();
2689 // If we zero all the possible extended bits, then we can turn this into
2690 // a zextload if we are running before legalize or the operation is legal.
2691 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2692 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2693 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2694 ((!LegalOperations && !LN0->isVolatile()) ||
2695 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2696 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
2698 LN0->getBasePtr(), LN0->getPointerInfo(),
2700 LN0->isVolatile(), LN0->isNonTemporal(),
2701 LN0->getAlignment());
2703 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2704 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2708 // fold (and (load x), 255) -> (zextload x, i8)
2709 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2710 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2711 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2712 (N0.getOpcode() == ISD::ANY_EXTEND &&
2713 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2714 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2715 LoadSDNode *LN0 = HasAnyExt
2716 ? cast<LoadSDNode>(N0.getOperand(0))
2717 : cast<LoadSDNode>(N0);
2718 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2719 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2720 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2721 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2722 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2723 EVT LoadedVT = LN0->getMemoryVT();
2725 if (ExtVT == LoadedVT &&
2726 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2727 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2730 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
2731 LN0->getChain(), LN0->getBasePtr(),
2732 LN0->getPointerInfo(),
2733 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2734 LN0->getAlignment());
2736 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2737 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2740 // Do not change the width of a volatile load.
2741 // Do not generate loads of non-round integer types since these can
2742 // be expensive (and would be wrong if the type is not byte sized).
2743 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2744 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2745 EVT PtrType = LN0->getOperand(1).getValueType();
2747 unsigned Alignment = LN0->getAlignment();
2748 SDValue NewPtr = LN0->getBasePtr();
2750 // For big endian targets, we need to add an offset to the pointer
2751 // to load the correct bytes. For little endian systems, we merely
2752 // need to read fewer bytes from the same pointer.
2753 if (TLI.isBigEndian()) {
2754 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2755 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2756 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2757 NewPtr = DAG.getNode(ISD::ADD, SDLoc(LN0), PtrType,
2758 NewPtr, DAG.getConstant(PtrOff, PtrType));
2759 Alignment = MinAlign(Alignment, PtrOff);
2762 AddToWorkList(NewPtr.getNode());
2764 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2766 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
2767 LN0->getChain(), NewPtr,
2768 LN0->getPointerInfo(),
2769 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2772 CombineTo(LN0, Load, Load.getValue(1));
2773 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2779 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
2780 VT.getSizeInBits() <= 64) {
2781 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2782 APInt ADDC = ADDI->getAPIntValue();
2783 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2784 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
2785 // immediate for an add, but it is legal if its top c2 bits are set,
2786 // transform the ADD so the immediate doesn't need to be materialized
2788 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
2789 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
2790 SRLI->getZExtValue());
2791 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
2793 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2795 DAG.getNode(ISD::ADD, SDLoc(N0), VT,
2796 N0.getOperand(0), DAG.getConstant(ADDC, VT));
2797 CombineTo(N0.getNode(), NewAdd);
2798 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2809 /// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16
2811 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
2812 bool DemandHighBits) {
2813 if (!LegalOperations)
2816 EVT VT = N->getValueType(0);
2817 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
2819 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2822 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
2823 bool LookPassAnd0 = false;
2824 bool LookPassAnd1 = false;
2825 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2827 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
2829 if (N0.getOpcode() == ISD::AND) {
2830 if (!N0.getNode()->hasOneUse())
2832 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2833 if (!N01C || N01C->getZExtValue() != 0xFF00)
2835 N0 = N0.getOperand(0);
2836 LookPassAnd0 = true;
2839 if (N1.getOpcode() == ISD::AND) {
2840 if (!N1.getNode()->hasOneUse())
2842 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2843 if (!N11C || N11C->getZExtValue() != 0xFF)
2845 N1 = N1.getOperand(0);
2846 LookPassAnd1 = true;
2849 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2851 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2853 if (!N0.getNode()->hasOneUse() ||
2854 !N1.getNode()->hasOneUse())
2857 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2858 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2861 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
2864 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
2865 SDValue N00 = N0->getOperand(0);
2866 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
2867 if (!N00.getNode()->hasOneUse())
2869 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
2870 if (!N001C || N001C->getZExtValue() != 0xFF)
2872 N00 = N00.getOperand(0);
2873 LookPassAnd0 = true;
2876 SDValue N10 = N1->getOperand(0);
2877 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
2878 if (!N10.getNode()->hasOneUse())
2880 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
2881 if (!N101C || N101C->getZExtValue() != 0xFF00)
2883 N10 = N10.getOperand(0);
2884 LookPassAnd1 = true;
2890 // Make sure everything beyond the low halfword is zero since the SRL 16
2891 // will clear the top bits.
2892 unsigned OpSizeInBits = VT.getSizeInBits();
2893 if (DemandHighBits && OpSizeInBits > 16 &&
2894 (!LookPassAnd0 || !LookPassAnd1) &&
2895 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16)))
2898 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00);
2899 if (OpSizeInBits > 16)
2900 Res = DAG.getNode(ISD::SRL, SDLoc(N), VT, Res,
2901 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT)));
2905 /// isBSwapHWordElement - Return true if the specified node is an element
2906 /// that makes up a 32-bit packed halfword byteswap. i.e.
2907 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2908 static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) {
2909 if (!N.getNode()->hasOneUse())
2912 unsigned Opc = N.getOpcode();
2913 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
2916 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2921 switch (N1C->getZExtValue()) {
2924 case 0xFF: Num = 0; break;
2925 case 0xFF00: Num = 1; break;
2926 case 0xFF0000: Num = 2; break;
2927 case 0xFF000000: Num = 3; break;
2930 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
2931 SDValue N0 = N.getOperand(0);
2932 if (Opc == ISD::AND) {
2933 if (Num == 0 || Num == 2) {
2935 // (x >> 8) & 0xff0000
2936 if (N0.getOpcode() != ISD::SRL)
2938 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2939 if (!C || C->getZExtValue() != 8)
2942 // (x << 8) & 0xff00
2943 // (x << 8) & 0xff000000
2944 if (N0.getOpcode() != ISD::SHL)
2946 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2947 if (!C || C->getZExtValue() != 8)
2950 } else if (Opc == ISD::SHL) {
2952 // (x & 0xff0000) << 8
2953 if (Num != 0 && Num != 2)
2955 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2956 if (!C || C->getZExtValue() != 8)
2958 } else { // Opc == ISD::SRL
2959 // (x & 0xff00) >> 8
2960 // (x & 0xff000000) >> 8
2961 if (Num != 1 && Num != 3)
2963 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2964 if (!C || C->getZExtValue() != 8)
2971 Parts[Num] = N0.getOperand(0).getNode();
2975 /// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is
2976 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2977 /// => (rotl (bswap x), 16)
2978 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
2979 if (!LegalOperations)
2982 EVT VT = N->getValueType(0);
2985 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2988 SmallVector<SDNode*,4> Parts(4, (SDNode*)0);
2990 // (or (or (and), (and)), (or (and), (and)))
2991 // (or (or (or (and), (and)), (and)), (and))
2992 if (N0.getOpcode() != ISD::OR)
2994 SDValue N00 = N0.getOperand(0);
2995 SDValue N01 = N0.getOperand(1);
2997 if (N1.getOpcode() == ISD::OR &&
2998 N00.getNumOperands() == 2 && N01.getNumOperands() == 2) {
2999 // (or (or (and), (and)), (or (and), (and)))
3000 SDValue N000 = N00.getOperand(0);
3001 if (!isBSwapHWordElement(N000, Parts))
3004 SDValue N001 = N00.getOperand(1);
3005 if (!isBSwapHWordElement(N001, Parts))
3007 SDValue N010 = N01.getOperand(0);
3008 if (!isBSwapHWordElement(N010, Parts))
3010 SDValue N011 = N01.getOperand(1);
3011 if (!isBSwapHWordElement(N011, Parts))
3014 // (or (or (or (and), (and)), (and)), (and))
3015 if (!isBSwapHWordElement(N1, Parts))
3017 if (!isBSwapHWordElement(N01, Parts))
3019 if (N00.getOpcode() != ISD::OR)
3021 SDValue N000 = N00.getOperand(0);
3022 if (!isBSwapHWordElement(N000, Parts))
3024 SDValue N001 = N00.getOperand(1);
3025 if (!isBSwapHWordElement(N001, Parts))
3029 // Make sure the parts are all coming from the same node.
3030 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
3033 SDValue BSwap = DAG.getNode(ISD::BSWAP, SDLoc(N), VT,
3034 SDValue(Parts[0],0));
3036 // Result of the bswap should be rotated by 16. If it's not legal, than
3037 // do (x << 16) | (x >> 16).
3038 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT));
3039 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
3040 return DAG.getNode(ISD::ROTL, SDLoc(N), VT, BSwap, ShAmt);
3041 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
3042 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, BSwap, ShAmt);
3043 return DAG.getNode(ISD::OR, SDLoc(N), VT,
3044 DAG.getNode(ISD::SHL, SDLoc(N), VT, BSwap, ShAmt),
3045 DAG.getNode(ISD::SRL, SDLoc(N), VT, BSwap, ShAmt));
3048 SDValue DAGCombiner::visitOR(SDNode *N) {
3049 SDValue N0 = N->getOperand(0);
3050 SDValue N1 = N->getOperand(1);
3051 SDValue LL, LR, RL, RR, CC0, CC1;
3052 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3053 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3054 EVT VT = N1.getValueType();
3057 if (VT.isVector()) {
3058 SDValue FoldedVOp = SimplifyVBinOp(N);
3059 if (FoldedVOp.getNode()) return FoldedVOp;
3061 // fold (or x, 0) -> x, vector edition
3062 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3064 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3067 // fold (or x, -1) -> -1, vector edition
3068 if (ISD::isBuildVectorAllOnes(N0.getNode()))
3070 if (ISD::isBuildVectorAllOnes(N1.getNode()))
3074 // fold (or x, undef) -> -1
3075 if (!LegalOperations &&
3076 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
3077 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
3078 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
3080 // fold (or c1, c2) -> c1|c2
3082 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
3083 // canonicalize constant to RHS
3085 return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0);
3086 // fold (or x, 0) -> x
3087 if (N1C && N1C->isNullValue())
3089 // fold (or x, -1) -> -1
3090 if (N1C && N1C->isAllOnesValue())
3092 // fold (or x, c) -> c iff (x & ~c) == 0
3093 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
3096 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
3097 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
3098 if (BSwap.getNode() != 0)
3100 BSwap = MatchBSwapHWordLow(N, N0, N1);
3101 if (BSwap.getNode() != 0)
3105 SDValue ROR = ReassociateOps(ISD::OR, SDLoc(N), N0, N1);
3106 if (ROR.getNode() != 0)
3108 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
3109 // iff (c1 & c2) == 0.
3110 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3111 isa<ConstantSDNode>(N0.getOperand(1))) {
3112 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
3113 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
3114 return DAG.getNode(ISD::AND, SDLoc(N), VT,
3115 DAG.getNode(ISD::OR, SDLoc(N0), VT,
3116 N0.getOperand(0), N1),
3117 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
3119 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
3120 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
3121 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
3122 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
3124 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
3125 LL.getValueType().isInteger()) {
3126 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
3127 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
3128 if (cast<ConstantSDNode>(LR)->isNullValue() &&
3129 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
3130 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(LR),
3131 LR.getValueType(), LL, RL);
3132 AddToWorkList(ORNode.getNode());
3133 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
3135 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
3136 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
3137 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
3138 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
3139 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(LR),
3140 LR.getValueType(), LL, RL);
3141 AddToWorkList(ANDNode.getNode());
3142 return DAG.getSetCC(SDLoc(N), VT, ANDNode, LR, Op1);
3145 // canonicalize equivalent to ll == rl
3146 if (LL == RR && LR == RL) {
3147 Op1 = ISD::getSetCCSwappedOperands(Op1);
3150 if (LL == RL && LR == RR) {
3151 bool isInteger = LL.getValueType().isInteger();
3152 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
3153 if (Result != ISD::SETCC_INVALID &&
3154 (!LegalOperations ||
3155 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
3156 TLI.isOperationLegal(ISD::SETCC,
3157 getSetCCResultType(N0.getValueType())))))
3158 return DAG.getSetCC(SDLoc(N), N0.getValueType(),
3163 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
3164 if (N0.getOpcode() == N1.getOpcode()) {
3165 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3166 if (Tmp.getNode()) return Tmp;
3169 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
3170 if (N0.getOpcode() == ISD::AND &&
3171 N1.getOpcode() == ISD::AND &&
3172 N0.getOperand(1).getOpcode() == ISD::Constant &&
3173 N1.getOperand(1).getOpcode() == ISD::Constant &&
3174 // Don't increase # computations.
3175 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3176 // We can only do this xform if we know that bits from X that are set in C2
3177 // but not in C1 are already zero. Likewise for Y.
3178 const APInt &LHSMask =
3179 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3180 const APInt &RHSMask =
3181 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
3183 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
3184 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
3185 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
3186 N0.getOperand(0), N1.getOperand(0));
3187 return DAG.getNode(ISD::AND, SDLoc(N), VT, X,
3188 DAG.getConstant(LHSMask | RHSMask, VT));
3192 // See if this is some rotate idiom.
3193 if (SDNode *Rot = MatchRotate(N0, N1, SDLoc(N)))
3194 return SDValue(Rot, 0);
3196 // Simplify the operands using demanded-bits information.
3197 if (!VT.isVector() &&
3198 SimplifyDemandedBits(SDValue(N, 0)))
3199 return SDValue(N, 0);
3204 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
3205 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
3206 if (Op.getOpcode() == ISD::AND) {
3207 if (isa<ConstantSDNode>(Op.getOperand(1))) {
3208 Mask = Op.getOperand(1);
3209 Op = Op.getOperand(0);
3215 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3223 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
3224 // idioms for rotate, and if the target supports rotation instructions, generate
3226 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL) {
3227 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
3228 EVT VT = LHS.getValueType();
3229 if (!TLI.isTypeLegal(VT)) return 0;
3231 // The target must have at least one rotate flavor.
3232 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
3233 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
3234 if (!HasROTL && !HasROTR) return 0;
3236 // Match "(X shl/srl V1) & V2" where V2 may not be present.
3237 SDValue LHSShift; // The shift.
3238 SDValue LHSMask; // AND value if any.
3239 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
3240 return 0; // Not part of a rotate.
3242 SDValue RHSShift; // The shift.
3243 SDValue RHSMask; // AND value if any.
3244 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
3245 return 0; // Not part of a rotate.
3247 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
3248 return 0; // Not shifting the same value.
3250 if (LHSShift.getOpcode() == RHSShift.getOpcode())
3251 return 0; // Shifts must disagree.
3253 // Canonicalize shl to left side in a shl/srl pair.
3254 if (RHSShift.getOpcode() == ISD::SHL) {
3255 std::swap(LHS, RHS);
3256 std::swap(LHSShift, RHSShift);
3257 std::swap(LHSMask , RHSMask );
3260 unsigned OpSizeInBits = VT.getSizeInBits();
3261 SDValue LHSShiftArg = LHSShift.getOperand(0);
3262 SDValue LHSShiftAmt = LHSShift.getOperand(1);
3263 SDValue RHSShiftAmt = RHSShift.getOperand(1);
3265 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
3266 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
3267 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
3268 RHSShiftAmt.getOpcode() == ISD::Constant) {
3269 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
3270 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
3271 if ((LShVal + RShVal) != OpSizeInBits)
3274 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3275 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt);
3277 // If there is an AND of either shifted operand, apply it to the result.
3278 if (LHSMask.getNode() || RHSMask.getNode()) {
3279 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
3281 if (LHSMask.getNode()) {
3282 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
3283 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
3285 if (RHSMask.getNode()) {
3286 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
3287 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
3290 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
3293 return Rot.getNode();
3296 // If there is a mask here, and we have a variable shift, we can't be sure
3297 // that we're masking out the right stuff.
3298 if (LHSMask.getNode() || RHSMask.getNode())
3301 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
3302 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
3303 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
3304 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
3305 if (ConstantSDNode *SUBC =
3306 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
3307 if (SUBC->getAPIntValue() == OpSizeInBits) {
3308 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg,
3309 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
3314 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
3315 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
3316 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
3317 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
3318 if (ConstantSDNode *SUBC =
3319 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
3320 if (SUBC->getAPIntValue() == OpSizeInBits) {
3321 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, LHSShiftArg,
3322 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
3327 // Look for sign/zext/any-extended or truncate cases:
3328 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3329 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3330 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3331 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3332 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3333 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3334 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3335 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3336 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
3337 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
3338 if (RExtOp0.getOpcode() == ISD::SUB &&
3339 RExtOp0.getOperand(1) == LExtOp0) {
3340 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3342 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3343 // (rotr x, (sub 32, y))
3344 if (ConstantSDNode *SUBC =
3345 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
3346 if (SUBC->getAPIntValue() == OpSizeInBits) {
3347 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3349 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
3352 } else if (LExtOp0.getOpcode() == ISD::SUB &&
3353 RExtOp0 == LExtOp0.getOperand(1)) {
3354 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3356 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3357 // (rotl x, (sub 32, y))
3358 if (ConstantSDNode *SUBC =
3359 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
3360 if (SUBC->getAPIntValue() == OpSizeInBits) {
3361 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
3363 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
3372 SDValue DAGCombiner::visitXOR(SDNode *N) {
3373 SDValue N0 = N->getOperand(0);
3374 SDValue N1 = N->getOperand(1);
3375 SDValue LHS, RHS, CC;
3376 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3377 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3378 EVT VT = N0.getValueType();
3381 if (VT.isVector()) {
3382 SDValue FoldedVOp = SimplifyVBinOp(N);
3383 if (FoldedVOp.getNode()) return FoldedVOp;
3385 // fold (xor x, 0) -> x, vector edition
3386 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3388 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3392 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3393 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3394 return DAG.getConstant(0, VT);
3395 // fold (xor x, undef) -> undef
3396 if (N0.getOpcode() == ISD::UNDEF)
3398 if (N1.getOpcode() == ISD::UNDEF)
3400 // fold (xor c1, c2) -> c1^c2
3402 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3403 // canonicalize constant to RHS
3405 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
3406 // fold (xor x, 0) -> x
3407 if (N1C && N1C->isNullValue())
3410 SDValue RXOR = ReassociateOps(ISD::XOR, SDLoc(N), N0, N1);
3411 if (RXOR.getNode() != 0)
3414 // fold !(x cc y) -> (x !cc y)
3415 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3416 bool isInt = LHS.getValueType().isInteger();
3417 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3420 if (!LegalOperations ||
3421 TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) {
3422 switch (N0.getOpcode()) {
3424 llvm_unreachable("Unhandled SetCC Equivalent!");
3426 return DAG.getSetCC(SDLoc(N), VT, LHS, RHS, NotCC);
3427 case ISD::SELECT_CC:
3428 return DAG.getSelectCC(SDLoc(N), LHS, RHS, N0.getOperand(2),
3429 N0.getOperand(3), NotCC);
3434 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
3435 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3436 N0.getNode()->hasOneUse() &&
3437 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3438 SDValue V = N0.getOperand(0);
3439 V = DAG.getNode(ISD::XOR, SDLoc(N0), V.getValueType(), V,
3440 DAG.getConstant(1, V.getValueType()));
3441 AddToWorkList(V.getNode());
3442 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, V);
3445 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
3446 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
3447 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3448 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3449 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
3450 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3451 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
3452 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
3453 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3454 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
3457 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
3458 if (N1C && N1C->isAllOnesValue() &&
3459 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3460 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3461 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
3462 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3463 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
3464 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
3465 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3466 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
3469 // fold (xor (and x, y), y) -> (and (not x), y)
3470 if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3471 N0->getOperand(1) == N1) {
3472 SDValue X = N0->getOperand(0);
3473 SDValue NotX = DAG.getNOT(SDLoc(X), X, VT);
3474 AddToWorkList(NotX.getNode());
3475 return DAG.getNode(ISD::AND, SDLoc(N), VT, NotX, N1);
3477 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
3478 if (N1C && N0.getOpcode() == ISD::XOR) {
3479 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3480 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3482 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N0.getOperand(1),
3483 DAG.getConstant(N1C->getAPIntValue() ^
3484 N00C->getAPIntValue(), VT));
3486 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N0.getOperand(0),
3487 DAG.getConstant(N1C->getAPIntValue() ^
3488 N01C->getAPIntValue(), VT));
3490 // fold (xor x, x) -> 0
3492 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations);
3494 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
3495 if (N0.getOpcode() == N1.getOpcode()) {
3496 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3497 if (Tmp.getNode()) return Tmp;
3500 // Simplify the expression using non-local knowledge.
3501 if (!VT.isVector() &&
3502 SimplifyDemandedBits(SDValue(N, 0)))
3503 return SDValue(N, 0);
3508 /// visitShiftByConstant - Handle transforms common to the three shifts, when
3509 /// the shift amount is a constant.
3510 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
3511 SDNode *LHS = N->getOperand(0).getNode();
3512 if (!LHS->hasOneUse()) return SDValue();
3514 // We want to pull some binops through shifts, so that we have (and (shift))
3515 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
3516 // thing happens with address calculations, so it's important to canonicalize
3518 bool HighBitSet = false; // Can we transform this if the high bit is set?
3520 switch (LHS->getOpcode()) {
3521 default: return SDValue();
3524 HighBitSet = false; // We can only transform sra if the high bit is clear.
3527 HighBitSet = true; // We can only transform sra if the high bit is set.
3530 if (N->getOpcode() != ISD::SHL)
3531 return SDValue(); // only shl(add) not sr[al](add).
3532 HighBitSet = false; // We can only transform sra if the high bit is clear.
3536 // We require the RHS of the binop to be a constant as well.
3537 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
3538 if (!BinOpCst) return SDValue();
3540 // FIXME: disable this unless the input to the binop is a shift by a constant.
3541 // If it is not a shift, it pessimizes some common cases like:
3543 // void foo(int *X, int i) { X[i & 1235] = 1; }
3544 // int bar(int *X, int i) { return X[i & 255]; }
3545 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
3546 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
3547 BinOpLHSVal->getOpcode() != ISD::SRA &&
3548 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3549 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
3552 EVT VT = N->getValueType(0);
3554 // If this is a signed shift right, and the high bit is modified by the
3555 // logical operation, do not perform the transformation. The highBitSet
3556 // boolean indicates the value of the high bit of the constant which would
3557 // cause it to be modified for this operation.
3558 if (N->getOpcode() == ISD::SRA) {
3559 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
3560 if (BinOpRHSSignSet != HighBitSet)
3564 // Fold the constants, shifting the binop RHS by the shift amount.
3565 SDValue NewRHS = DAG.getNode(N->getOpcode(), SDLoc(LHS->getOperand(1)),
3567 LHS->getOperand(1), N->getOperand(1));
3569 // Create the new shift.
3570 SDValue NewShift = DAG.getNode(N->getOpcode(),
3571 SDLoc(LHS->getOperand(0)),
3572 VT, LHS->getOperand(0), N->getOperand(1));
3574 // Create the new binop.
3575 return DAG.getNode(LHS->getOpcode(), SDLoc(N), VT, NewShift, NewRHS);
3578 SDValue DAGCombiner::visitSHL(SDNode *N) {
3579 SDValue N0 = N->getOperand(0);
3580 SDValue N1 = N->getOperand(1);
3581 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3582 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3583 EVT VT = N0.getValueType();
3584 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3586 // fold (shl c1, c2) -> c1<<c2
3588 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
3589 // fold (shl 0, x) -> 0
3590 if (N0C && N0C->isNullValue())
3592 // fold (shl x, c >= size(x)) -> undef
3593 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3594 return DAG.getUNDEF(VT);
3595 // fold (shl x, 0) -> x
3596 if (N1C && N1C->isNullValue())
3598 // fold (shl undef, x) -> 0
3599 if (N0.getOpcode() == ISD::UNDEF)
3600 return DAG.getConstant(0, VT);
3601 // if (shl x, c) is known to be zero, return 0
3602 if (DAG.MaskedValueIsZero(SDValue(N, 0),
3603 APInt::getAllOnesValue(OpSizeInBits)))
3604 return DAG.getConstant(0, VT);
3605 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
3606 if (N1.getOpcode() == ISD::TRUNCATE &&
3607 N1.getOperand(0).getOpcode() == ISD::AND &&
3608 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3609 SDValue N101 = N1.getOperand(0).getOperand(1);
3610 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3611 EVT TruncVT = N1.getValueType();
3612 SDValue N100 = N1.getOperand(0).getOperand(0);
3613 APInt TruncC = N101C->getAPIntValue();
3614 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3615 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
3616 DAG.getNode(ISD::AND, SDLoc(N), TruncVT,
3617 DAG.getNode(ISD::TRUNCATE,
3620 DAG.getConstant(TruncC, TruncVT)));
3624 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3625 return SDValue(N, 0);
3627 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
3628 if (N1C && N0.getOpcode() == ISD::SHL &&
3629 N0.getOperand(1).getOpcode() == ISD::Constant) {
3630 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3631 uint64_t c2 = N1C->getZExtValue();
3632 if (c1 + c2 >= OpSizeInBits)
3633 return DAG.getConstant(0, VT);
3634 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0),
3635 DAG.getConstant(c1 + c2, N1.getValueType()));
3638 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
3639 // For this to be valid, the second form must not preserve any of the bits
3640 // that are shifted out by the inner shift in the first form. This means
3641 // the outer shift size must be >= the number of bits added by the ext.
3642 // As a corollary, we don't care what kind of ext it is.
3643 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
3644 N0.getOpcode() == ISD::ANY_EXTEND ||
3645 N0.getOpcode() == ISD::SIGN_EXTEND) &&
3646 N0.getOperand(0).getOpcode() == ISD::SHL &&
3647 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3649 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3650 uint64_t c2 = N1C->getZExtValue();
3651 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3652 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3653 if (c2 >= OpSizeInBits - InnerShiftSize) {
3654 if (c1 + c2 >= OpSizeInBits)
3655 return DAG.getConstant(0, VT);
3656 return DAG.getNode(ISD::SHL, SDLoc(N0), VT,
3657 DAG.getNode(N0.getOpcode(), SDLoc(N0), VT,
3658 N0.getOperand(0)->getOperand(0)),
3659 DAG.getConstant(c1 + c2, N1.getValueType()));
3663 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
3664 // (and (srl x, (sub c1, c2), MASK)
3665 // Only fold this if the inner shift has no other uses -- if it does, folding
3666 // this will increase the total number of instructions.
3667 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() &&
3668 N0.getOperand(1).getOpcode() == ISD::Constant) {
3669 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3670 if (c1 < VT.getSizeInBits()) {
3671 uint64_t c2 = N1C->getZExtValue();
3672 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
3673 VT.getSizeInBits() - c1);
3676 Mask = Mask.shl(c2-c1);
3677 Shift = DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0),
3678 DAG.getConstant(c2-c1, N1.getValueType()));
3680 Mask = Mask.lshr(c1-c2);
3681 Shift = DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0),
3682 DAG.getConstant(c1-c2, N1.getValueType()));
3684 return DAG.getNode(ISD::AND, SDLoc(N0), VT, Shift,
3685 DAG.getConstant(Mask, VT));
3688 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
3689 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
3690 SDValue HiBitsMask =
3691 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
3692 VT.getSizeInBits() -
3693 N1C->getZExtValue()),
3695 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0),
3700 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
3701 if (NewSHL.getNode())
3708 SDValue DAGCombiner::visitSRA(SDNode *N) {
3709 SDValue N0 = N->getOperand(0);
3710 SDValue N1 = N->getOperand(1);
3711 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3712 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3713 EVT VT = N0.getValueType();
3714 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3716 // fold (sra c1, c2) -> (sra c1, c2)
3718 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
3719 // fold (sra 0, x) -> 0
3720 if (N0C && N0C->isNullValue())
3722 // fold (sra -1, x) -> -1
3723 if (N0C && N0C->isAllOnesValue())
3725 // fold (sra x, (setge c, size(x))) -> undef
3726 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3727 return DAG.getUNDEF(VT);
3728 // fold (sra x, 0) -> x
3729 if (N1C && N1C->isNullValue())
3731 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
3733 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
3734 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
3735 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
3737 ExtVT = EVT::getVectorVT(*DAG.getContext(),
3738 ExtVT, VT.getVectorNumElements());
3739 if ((!LegalOperations ||
3740 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
3741 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
3742 N0.getOperand(0), DAG.getValueType(ExtVT));
3745 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
3746 if (N1C && N0.getOpcode() == ISD::SRA) {
3747 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3748 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
3749 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
3750 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0.getOperand(0),
3751 DAG.getConstant(Sum, N1C->getValueType(0)));
3755 // fold (sra (shl X, m), (sub result_size, n))
3756 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
3757 // result_size - n != m.
3758 // If truncate is free for the target sext(shl) is likely to result in better
3760 if (N0.getOpcode() == ISD::SHL) {
3761 // Get the two constanst of the shifts, CN0 = m, CN = n.
3762 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3764 // Determine what the truncate's result bitsize and type would be.
3766 EVT::getIntegerVT(*DAG.getContext(),
3767 OpSizeInBits - N1C->getZExtValue());
3768 // Determine the residual right-shift amount.
3769 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
3771 // If the shift is not a no-op (in which case this should be just a sign
3772 // extend already), the truncated to type is legal, sign_extend is legal
3773 // on that type, and the truncate to that type is both legal and free,
3774 // perform the transform.
3775 if ((ShiftAmt > 0) &&
3776 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
3777 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
3778 TLI.isTruncateFree(VT, TruncVT)) {
3780 SDValue Amt = DAG.getConstant(ShiftAmt,
3781 getShiftAmountTy(N0.getOperand(0).getValueType()));
3782 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0), VT,
3783 N0.getOperand(0), Amt);
3784 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), TruncVT,
3786 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N),
3787 N->getValueType(0), Trunc);
3792 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
3793 if (N1.getOpcode() == ISD::TRUNCATE &&
3794 N1.getOperand(0).getOpcode() == ISD::AND &&
3795 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3796 SDValue N101 = N1.getOperand(0).getOperand(1);
3797 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3798 EVT TruncVT = N1.getValueType();
3799 SDValue N100 = N1.getOperand(0).getOperand(0);
3800 APInt TruncC = N101C->getAPIntValue();
3801 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
3802 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0,
3803 DAG.getNode(ISD::AND, SDLoc(N),
3805 DAG.getNode(ISD::TRUNCATE,
3808 DAG.getConstant(TruncC, TruncVT)));
3812 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2))
3813 // if c1 is equal to the number of bits the trunc removes
3814 if (N0.getOpcode() == ISD::TRUNCATE &&
3815 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3816 N0.getOperand(0).getOpcode() == ISD::SRA) &&
3817 N0.getOperand(0).hasOneUse() &&
3818 N0.getOperand(0).getOperand(1).hasOneUse() &&
3819 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) {
3820 EVT LargeVT = N0.getOperand(0).getValueType();
3821 ConstantSDNode *LargeShiftAmt =
3822 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1));
3824 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits ==
3825 LargeShiftAmt->getZExtValue()) {
3827 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(),
3828 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType()));
3829 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), LargeVT,
3830 N0.getOperand(0).getOperand(0), Amt);
3831 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, SRA);
3835 // Simplify, based on bits shifted out of the LHS.
3836 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3837 return SDValue(N, 0);
3840 // If the sign bit is known to be zero, switch this to a SRL.
3841 if (DAG.SignBitIsZero(N0))
3842 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1);
3845 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
3846 if (NewSRA.getNode())
3853 SDValue DAGCombiner::visitSRL(SDNode *N) {
3854 SDValue N0 = N->getOperand(0);
3855 SDValue N1 = N->getOperand(1);
3856 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3857 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3858 EVT VT = N0.getValueType();
3859 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3861 // fold (srl c1, c2) -> c1 >>u c2
3863 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3864 // fold (srl 0, x) -> 0
3865 if (N0C && N0C->isNullValue())
3867 // fold (srl x, c >= size(x)) -> undef
3868 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3869 return DAG.getUNDEF(VT);
3870 // fold (srl x, 0) -> x
3871 if (N1C && N1C->isNullValue())
3873 // if (srl x, c) is known to be zero, return 0
3874 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3875 APInt::getAllOnesValue(OpSizeInBits)))
3876 return DAG.getConstant(0, VT);
3878 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3879 if (N1C && N0.getOpcode() == ISD::SRL &&
3880 N0.getOperand(1).getOpcode() == ISD::Constant) {
3881 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3882 uint64_t c2 = N1C->getZExtValue();
3883 if (c1 + c2 >= OpSizeInBits)
3884 return DAG.getConstant(0, VT);
3885 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0),
3886 DAG.getConstant(c1 + c2, N1.getValueType()));
3889 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
3890 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
3891 N0.getOperand(0).getOpcode() == ISD::SRL &&
3892 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3894 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3895 uint64_t c2 = N1C->getZExtValue();
3896 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3897 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
3898 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3899 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
3900 if (c1 + OpSizeInBits == InnerShiftSize) {
3901 if (c1 + c2 >= InnerShiftSize)
3902 return DAG.getConstant(0, VT);
3903 return DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT,
3904 DAG.getNode(ISD::SRL, SDLoc(N0), InnerShiftVT,
3905 N0.getOperand(0)->getOperand(0),
3906 DAG.getConstant(c1 + c2, ShiftCountVT)));
3910 // fold (srl (shl x, c), c) -> (and x, cst2)
3911 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3912 N0.getValueSizeInBits() <= 64) {
3913 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3914 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0),
3915 DAG.getConstant(~0ULL >> ShAmt, VT));
3919 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3920 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3921 // Shifting in all undef bits?
3922 EVT SmallVT = N0.getOperand(0).getValueType();
3923 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
3924 return DAG.getUNDEF(VT);
3926 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3927 uint64_t ShiftAmt = N1C->getZExtValue();
3928 SDValue SmallShift = DAG.getNode(ISD::SRL, SDLoc(N0), SmallVT,
3930 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));
3931 AddToWorkList(SmallShift.getNode());
3932 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, SmallShift);
3936 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
3937 // bit, which is unmodified by sra.
3938 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
3939 if (N0.getOpcode() == ISD::SRA)
3940 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1);
3943 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3944 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3945 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
3946 APInt KnownZero, KnownOne;
3947 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne);
3949 // If any of the input bits are KnownOne, then the input couldn't be all
3950 // zeros, thus the result of the srl will always be zero.
3951 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
3953 // If all of the bits input the to ctlz node are known to be zero, then
3954 // the result of the ctlz is "32" and the result of the shift is one.
3955 APInt UnknownBits = ~KnownZero;
3956 if (UnknownBits == 0) return DAG.getConstant(1, VT);
3958 // Otherwise, check to see if there is exactly one bit input to the ctlz.
3959 if ((UnknownBits & (UnknownBits - 1)) == 0) {
3960 // Okay, we know that only that the single bit specified by UnknownBits
3961 // could be set on input to the CTLZ node. If this bit is set, the SRL
3962 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3963 // to an SRL/XOR pair, which is likely to simplify more.
3964 unsigned ShAmt = UnknownBits.countTrailingZeros();
3965 SDValue Op = N0.getOperand(0);
3968 Op = DAG.getNode(ISD::SRL, SDLoc(N0), VT, Op,
3969 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType())));
3970 AddToWorkList(Op.getNode());
3973 return DAG.getNode(ISD::XOR, SDLoc(N), VT,
3974 Op, DAG.getConstant(1, VT));
3978 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3979 if (N1.getOpcode() == ISD::TRUNCATE &&
3980 N1.getOperand(0).getOpcode() == ISD::AND &&
3981 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3982 SDValue N101 = N1.getOperand(0).getOperand(1);
3983 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3984 EVT TruncVT = N1.getValueType();
3985 SDValue N100 = N1.getOperand(0).getOperand(0);
3986 APInt TruncC = N101C->getAPIntValue();
3987 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3988 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0,
3989 DAG.getNode(ISD::AND, SDLoc(N),
3991 DAG.getNode(ISD::TRUNCATE,
3994 DAG.getConstant(TruncC, TruncVT)));
3998 // fold operands of srl based on knowledge that the low bits are not
4000 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4001 return SDValue(N, 0);
4004 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
4005 if (NewSRL.getNode())
4009 // Attempt to convert a srl of a load into a narrower zero-extending load.
4010 SDValue NarrowLoad = ReduceLoadWidth(N);
4011 if (NarrowLoad.getNode())
4014 // Here is a common situation. We want to optimize:
4017 // %b = and i32 %a, 2
4018 // %c = srl i32 %b, 1
4019 // brcond i32 %c ...
4025 // %c = setcc eq %b, 0
4028 // However when after the source operand of SRL is optimized into AND, the SRL
4029 // itself may not be optimized further. Look for it and add the BRCOND into
4031 if (N->hasOneUse()) {
4032 SDNode *Use = *N->use_begin();
4033 if (Use->getOpcode() == ISD::BRCOND)
4035 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
4036 // Also look pass the truncate.
4037 Use = *Use->use_begin();
4038 if (Use->getOpcode() == ISD::BRCOND)
4046 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
4047 SDValue N0 = N->getOperand(0);
4048 EVT VT = N->getValueType(0);
4050 // fold (ctlz c1) -> c2
4051 if (isa<ConstantSDNode>(N0))
4052 return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0);
4056 SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) {
4057 SDValue N0 = N->getOperand(0);
4058 EVT VT = N->getValueType(0);
4060 // fold (ctlz_zero_undef c1) -> c2
4061 if (isa<ConstantSDNode>(N0))
4062 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4066 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
4067 SDValue N0 = N->getOperand(0);
4068 EVT VT = N->getValueType(0);
4070 // fold (cttz c1) -> c2
4071 if (isa<ConstantSDNode>(N0))
4072 return DAG.getNode(ISD::CTTZ, SDLoc(N), VT, N0);
4076 SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) {
4077 SDValue N0 = N->getOperand(0);
4078 EVT VT = N->getValueType(0);
4080 // fold (cttz_zero_undef c1) -> c2
4081 if (isa<ConstantSDNode>(N0))
4082 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4086 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
4087 SDValue N0 = N->getOperand(0);
4088 EVT VT = N->getValueType(0);
4090 // fold (ctpop c1) -> c2
4091 if (isa<ConstantSDNode>(N0))
4092 return DAG.getNode(ISD::CTPOP, SDLoc(N), VT, N0);
4096 SDValue DAGCombiner::visitSELECT(SDNode *N) {
4097 SDValue N0 = N->getOperand(0);
4098 SDValue N1 = N->getOperand(1);
4099 SDValue N2 = N->getOperand(2);
4100 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4101 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4102 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
4103 EVT VT = N->getValueType(0);
4104 EVT VT0 = N0.getValueType();
4106 // fold (select C, X, X) -> X
4109 // fold (select true, X, Y) -> X
4110 if (N0C && !N0C->isNullValue())
4112 // fold (select false, X, Y) -> Y
4113 if (N0C && N0C->isNullValue())
4115 // fold (select C, 1, X) -> (or C, X)
4116 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
4117 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
4118 // fold (select C, 0, 1) -> (xor C, 1)
4119 if (VT.isInteger() &&
4122 TLI.getBooleanContents(false) ==
4123 TargetLowering::ZeroOrOneBooleanContent)) &&
4124 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
4127 return DAG.getNode(ISD::XOR, SDLoc(N), VT0,
4128 N0, DAG.getConstant(1, VT0));
4129 XORNode = DAG.getNode(ISD::XOR, SDLoc(N0), VT0,
4130 N0, DAG.getConstant(1, VT0));
4131 AddToWorkList(XORNode.getNode());
4133 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, XORNode);
4134 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, XORNode);
4136 // fold (select C, 0, X) -> (and (not C), X)
4137 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
4138 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
4139 AddToWorkList(NOTNode.getNode());
4140 return DAG.getNode(ISD::AND, SDLoc(N), VT, NOTNode, N2);
4142 // fold (select C, X, 1) -> (or (not C), X)
4143 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
4144 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
4145 AddToWorkList(NOTNode.getNode());
4146 return DAG.getNode(ISD::OR, SDLoc(N), VT, NOTNode, N1);
4148 // fold (select C, X, 0) -> (and C, X)
4149 if (VT == MVT::i1 && N2C && N2C->isNullValue())
4150 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
4151 // fold (select X, X, Y) -> (or X, Y)
4152 // fold (select X, 1, Y) -> (or X, Y)
4153 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
4154 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
4155 // fold (select X, Y, X) -> (and X, Y)
4156 // fold (select X, Y, 0) -> (and X, Y)
4157 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
4158 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
4160 // If we can fold this based on the true/false value, do so.
4161 if (SimplifySelectOps(N, N1, N2))
4162 return SDValue(N, 0); // Don't revisit N.
4164 // fold selects based on a setcc into other things, such as min/max/abs
4165 if (N0.getOpcode() == ISD::SETCC) {
4167 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
4168 // having to say they don't support SELECT_CC on every type the DAG knows
4169 // about, since there is no way to mark an opcode illegal at all value types
4170 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
4171 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
4172 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT,
4173 N0.getOperand(0), N0.getOperand(1),
4174 N1, N2, N0.getOperand(2));
4175 return SimplifySelect(SDLoc(N), N0, N1, N2);
4181 SDValue DAGCombiner::visitVSELECT(SDNode *N) {
4182 SDValue N0 = N->getOperand(0);
4183 SDValue N1 = N->getOperand(1);
4184 SDValue N2 = N->getOperand(2);
4187 // Canonicalize integer abs.
4188 // vselect (setg[te] X, 0), X, -X ->
4189 // vselect (setgt X, -1), X, -X ->
4190 // vselect (setl[te] X, 0), -X, X ->
4191 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4192 if (N0.getOpcode() == ISD::SETCC) {
4193 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
4194 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
4196 bool RHSIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
4198 if (((RHSIsAllZeros && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
4199 (ISD::isBuildVectorAllOnes(RHS.getNode()) && CC == ISD::SETGT)) &&
4200 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1))
4201 isAbs = ISD::isBuildVectorAllZeros(N2.getOperand(0).getNode());
4202 else if ((RHSIsAllZeros && (CC == ISD::SETLT || CC == ISD::SETLE)) &&
4203 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1))
4204 isAbs = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode());
4207 EVT VT = LHS.getValueType();
4208 SDValue Shift = DAG.getNode(
4209 ISD::SRA, DL, VT, LHS,
4210 DAG.getConstant(VT.getScalarType().getSizeInBits() - 1, VT));
4211 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, LHS, Shift);
4212 AddToWorkList(Shift.getNode());
4213 AddToWorkList(Add.getNode());
4214 return DAG.getNode(ISD::XOR, DL, VT, Add, Shift);
4221 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
4222 SDValue N0 = N->getOperand(0);
4223 SDValue N1 = N->getOperand(1);
4224 SDValue N2 = N->getOperand(2);
4225 SDValue N3 = N->getOperand(3);
4226 SDValue N4 = N->getOperand(4);
4227 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
4229 // fold select_cc lhs, rhs, x, x, cc -> x
4233 // Determine if the condition we're dealing with is constant
4234 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
4235 N0, N1, CC, SDLoc(N), false);
4236 if (SCC.getNode()) {
4237 AddToWorkList(SCC.getNode());
4239 if (ConstantSDNode *SCCC = dyn_cast<ConstantSDNode>(SCC.getNode())) {
4240 if (!SCCC->isNullValue())
4241 return N2; // cond always true -> true val
4243 return N3; // cond always false -> false val
4246 // Fold to a simpler select_cc
4247 if (SCC.getOpcode() == ISD::SETCC)
4248 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N2.getValueType(),
4249 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
4253 // If we can fold this based on the true/false value, do so.
4254 if (SimplifySelectOps(N, N2, N3))
4255 return SDValue(N, 0); // Don't revisit N.
4257 // fold select_cc into other things, such as min/max/abs
4258 return SimplifySelectCC(SDLoc(N), N0, N1, N2, N3, CC);
4261 SDValue DAGCombiner::visitSETCC(SDNode *N) {
4262 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
4263 cast<CondCodeSDNode>(N->getOperand(2))->get(),
4267 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
4268 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
4269 // transformation. Returns true if extension are possible and the above
4270 // mentioned transformation is profitable.
4271 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
4273 SmallVector<SDNode*, 4> &ExtendNodes,
4274 const TargetLowering &TLI) {
4275 bool HasCopyToRegUses = false;
4276 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
4277 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
4278 UE = N0.getNode()->use_end();
4283 if (UI.getUse().getResNo() != N0.getResNo())
4285 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
4286 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
4287 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
4288 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
4289 // Sign bits will be lost after a zext.
4292 for (unsigned i = 0; i != 2; ++i) {
4293 SDValue UseOp = User->getOperand(i);
4296 if (!isa<ConstantSDNode>(UseOp))
4301 ExtendNodes.push_back(User);
4304 // If truncates aren't free and there are users we can't
4305 // extend, it isn't worthwhile.
4308 // Remember if this value is live-out.
4309 if (User->getOpcode() == ISD::CopyToReg)
4310 HasCopyToRegUses = true;
4313 if (HasCopyToRegUses) {
4314 bool BothLiveOut = false;
4315 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
4317 SDUse &Use = UI.getUse();
4318 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
4324 // Both unextended and extended values are live out. There had better be
4325 // a good reason for the transformation.
4326 return ExtendNodes.size();
4331 void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
4332 SDValue Trunc, SDValue ExtLoad, SDLoc DL,
4333 ISD::NodeType ExtType) {
4334 // Extend SetCC uses if necessary.
4335 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
4336 SDNode *SetCC = SetCCs[i];
4337 SmallVector<SDValue, 4> Ops;
4339 for (unsigned j = 0; j != 2; ++j) {
4340 SDValue SOp = SetCC->getOperand(j);
4342 Ops.push_back(ExtLoad);
4344 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
4347 Ops.push_back(SetCC->getOperand(2));
4348 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0),
4349 &Ops[0], Ops.size()));
4353 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
4354 SDValue N0 = N->getOperand(0);
4355 EVT VT = N->getValueType(0);
4357 // fold (sext c1) -> c1
4358 if (isa<ConstantSDNode>(N0))
4359 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N0);
4361 // fold (sext (sext x)) -> (sext x)
4362 // fold (sext (aext x)) -> (sext x)
4363 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4364 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT,
4367 if (N0.getOpcode() == ISD::TRUNCATE) {
4368 // fold (sext (truncate (load x))) -> (sext (smaller load x))
4369 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
4370 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4371 if (NarrowLoad.getNode()) {
4372 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4373 if (NarrowLoad.getNode() != N0.getNode()) {
4374 CombineTo(N0.getNode(), NarrowLoad);
4375 // CombineTo deleted the truncate, if needed, but not what's under it.
4378 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4381 // See if the value being truncated is already sign extended. If so, just
4382 // eliminate the trunc/sext pair.
4383 SDValue Op = N0.getOperand(0);
4384 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
4385 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
4386 unsigned DestBits = VT.getScalarType().getSizeInBits();
4387 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
4389 if (OpBits == DestBits) {
4390 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
4391 // bits, it is already ready.
4392 if (NumSignBits > DestBits-MidBits)
4394 } else if (OpBits < DestBits) {
4395 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
4396 // bits, just sext from i32.
4397 if (NumSignBits > OpBits-MidBits)
4398 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, Op);
4400 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
4401 // bits, just truncate to i32.
4402 if (NumSignBits > OpBits-MidBits)
4403 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
4406 // fold (sext (truncate x)) -> (sextinreg x).
4407 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
4408 N0.getValueType())) {
4409 if (OpBits < DestBits)
4410 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N0), VT, Op);
4411 else if (OpBits > DestBits)
4412 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT, Op);
4413 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, Op,
4414 DAG.getValueType(N0.getValueType()));
4418 // fold (sext (load x)) -> (sext (truncate (sextload x)))
4419 // None of the supported targets knows how to perform load and sign extend
4420 // on vectors in one instruction. We only perform this transformation on
4422 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4423 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4424 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
4425 bool DoXform = true;
4426 SmallVector<SDNode*, 4> SetCCs;
4427 if (!N0.hasOneUse())
4428 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
4430 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4431 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
4433 LN0->getBasePtr(), LN0->getPointerInfo(),
4435 LN0->isVolatile(), LN0->isNonTemporal(),
4436 LN0->getAlignment());
4437 CombineTo(N, ExtLoad);
4438 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
4439 N0.getValueType(), ExtLoad);
4440 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4441 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
4443 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4447 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
4448 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
4449 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4450 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4451 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4452 EVT MemVT = LN0->getMemoryVT();
4453 if ((!LegalOperations && !LN0->isVolatile()) ||
4454 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
4455 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
4457 LN0->getBasePtr(), LN0->getPointerInfo(),
4459 LN0->isVolatile(), LN0->isNonTemporal(),
4460 LN0->getAlignment());
4461 CombineTo(N, ExtLoad);
4462 CombineTo(N0.getNode(),
4463 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
4464 N0.getValueType(), ExtLoad),
4465 ExtLoad.getValue(1));
4466 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4470 // fold (sext (and/or/xor (load x), cst)) ->
4471 // (and/or/xor (sextload x), (sext cst))
4472 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4473 N0.getOpcode() == ISD::XOR) &&
4474 isa<LoadSDNode>(N0.getOperand(0)) &&
4475 N0.getOperand(1).getOpcode() == ISD::Constant &&
4476 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
4477 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4478 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4479 if (LN0->getExtensionType() != ISD::ZEXTLOAD) {
4480 bool DoXform = true;
4481 SmallVector<SDNode*, 4> SetCCs;
4482 if (!N0.hasOneUse())
4483 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
4486 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(LN0), VT,
4487 LN0->getChain(), LN0->getBasePtr(),
4488 LN0->getPointerInfo(),
4491 LN0->isNonTemporal(),
4492 LN0->getAlignment());
4493 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4494 Mask = Mask.sext(VT.getSizeInBits());
4495 SDValue And = DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
4496 ExtLoad, DAG.getConstant(Mask, VT));
4497 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4498 SDLoc(N0.getOperand(0)),
4499 N0.getOperand(0).getValueType(), ExtLoad);
4501 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4502 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
4504 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4509 if (N0.getOpcode() == ISD::SETCC) {
4510 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
4511 // Only do this before legalize for now.
4512 if (VT.isVector() && !LegalOperations &&
4513 TLI.getBooleanContents(true) ==
4514 TargetLowering::ZeroOrNegativeOneBooleanContent) {
4515 EVT N0VT = N0.getOperand(0).getValueType();
4516 // On some architectures (such as SSE/NEON/etc) the SETCC result type is
4517 // of the same size as the compared operands. Only optimize sext(setcc())
4518 // if this is the case.
4519 EVT SVT = getSetCCResultType(N0VT);
4521 // We know that the # elements of the results is the same as the
4522 // # elements of the compare (and the # elements of the compare result
4523 // for that matter). Check to see that they are the same size. If so,
4524 // we know that the element size of the sext'd result matches the
4525 // element size of the compare operands.
4526 if (VT.getSizeInBits() == SVT.getSizeInBits())
4527 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
4529 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4531 // If the desired elements are smaller or larger than the source
4532 // elements we can use a matching integer vector type and then
4533 // truncate/sign extend
4534 EVT MatchingVectorType = N0VT.changeVectorElementTypeToInteger();
4535 if (SVT == MatchingVectorType) {
4536 SDValue VsetCC = DAG.getSetCC(SDLoc(N), MatchingVectorType,
4537 N0.getOperand(0), N0.getOperand(1),
4538 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4539 return DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT);
4543 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
4544 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
4546 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
4548 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
4549 NegOne, DAG.getConstant(0, VT),
4550 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4551 if (SCC.getNode()) return SCC;
4552 if (!VT.isVector() &&
4553 (!LegalOperations ||
4554 TLI.isOperationLegal(ISD::SETCC, getSetCCResultType(VT)))) {
4555 return DAG.getSelect(SDLoc(N), VT,
4556 DAG.getSetCC(SDLoc(N),
4557 getSetCCResultType(VT),
4558 N0.getOperand(0), N0.getOperand(1),
4559 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4560 NegOne, DAG.getConstant(0, VT));
4564 // fold (sext x) -> (zext x) if the sign bit is known zero.
4565 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
4566 DAG.SignBitIsZero(N0))
4567 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0);
4572 // isTruncateOf - If N is a truncate of some other value, return true, record
4573 // the value being truncated in Op and which of Op's bits are zero in KnownZero.
4574 // This function computes KnownZero to avoid a duplicated call to
4575 // ComputeMaskedBits in the caller.
4576 static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
4579 if (N->getOpcode() == ISD::TRUNCATE) {
4580 Op = N->getOperand(0);
4581 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne);
4585 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 ||
4586 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE)
4589 SDValue Op0 = N->getOperand(0);
4590 SDValue Op1 = N->getOperand(1);
4591 assert(Op0.getValueType() == Op1.getValueType());
4593 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0);
4594 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1);
4595 if (COp0 && COp0->isNullValue())
4597 else if (COp1 && COp1->isNullValue())
4602 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne);
4604 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue())
4610 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
4611 SDValue N0 = N->getOperand(0);
4612 EVT VT = N->getValueType(0);
4614 // fold (zext c1) -> c1
4615 if (isa<ConstantSDNode>(N0))
4616 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0);
4617 // fold (zext (zext x)) -> (zext x)
4618 // fold (zext (aext x)) -> (zext x)
4619 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4620 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT,
4623 // fold (zext (truncate x)) -> (zext x) or
4624 // (zext (truncate x)) -> (truncate x)
4625 // This is valid when the truncated bits of x are already zero.
4626 // FIXME: We should extend this to work for vectors too.
4629 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) {
4630 APInt TruncatedBits =
4631 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ?
4632 APInt(Op.getValueSizeInBits(), 0) :
4633 APInt::getBitsSet(Op.getValueSizeInBits(),
4634 N0.getValueSizeInBits(),
4635 std::min(Op.getValueSizeInBits(),
4636 VT.getSizeInBits()));
4637 if (TruncatedBits == (KnownZero & TruncatedBits)) {
4638 if (VT.bitsGT(Op.getValueType()))
4639 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, Op);
4640 if (VT.bitsLT(Op.getValueType()))
4641 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
4647 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4648 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
4649 if (N0.getOpcode() == ISD::TRUNCATE) {
4650 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4651 if (NarrowLoad.getNode()) {
4652 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4653 if (NarrowLoad.getNode() != N0.getNode()) {
4654 CombineTo(N0.getNode(), NarrowLoad);
4655 // CombineTo deleted the truncate, if needed, but not what's under it.
4658 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4662 // fold (zext (truncate x)) -> (and x, mask)
4663 if (N0.getOpcode() == ISD::TRUNCATE &&
4664 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
4666 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4667 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
4668 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4669 if (NarrowLoad.getNode()) {
4670 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4671 if (NarrowLoad.getNode() != N0.getNode()) {
4672 CombineTo(N0.getNode(), NarrowLoad);
4673 // CombineTo deleted the truncate, if needed, but not what's under it.
4676 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4679 SDValue Op = N0.getOperand(0);
4680 if (Op.getValueType().bitsLT(VT)) {
4681 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, Op);
4682 AddToWorkList(Op.getNode());
4683 } else if (Op.getValueType().bitsGT(VT)) {
4684 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
4685 AddToWorkList(Op.getNode());
4687 return DAG.getZeroExtendInReg(Op, SDLoc(N),
4688 N0.getValueType().getScalarType());
4691 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
4692 // if either of the casts is not free.
4693 if (N0.getOpcode() == ISD::AND &&
4694 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4695 N0.getOperand(1).getOpcode() == ISD::Constant &&
4696 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4697 N0.getValueType()) ||
4698 !TLI.isZExtFree(N0.getValueType(), VT))) {
4699 SDValue X = N0.getOperand(0).getOperand(0);
4700 if (X.getValueType().bitsLT(VT)) {
4701 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(X), VT, X);
4702 } else if (X.getValueType().bitsGT(VT)) {
4703 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);
4705 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4706 Mask = Mask.zext(VT.getSizeInBits());
4707 return DAG.getNode(ISD::AND, SDLoc(N), VT,
4708 X, DAG.getConstant(Mask, VT));
4711 // fold (zext (load x)) -> (zext (truncate (zextload x)))
4712 // None of the supported targets knows how to perform load and vector_zext
4713 // on vectors in one instruction. We only perform this transformation on
4715 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4716 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4717 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
4718 bool DoXform = true;
4719 SmallVector<SDNode*, 4> SetCCs;
4720 if (!N0.hasOneUse())
4721 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
4723 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4724 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
4726 LN0->getBasePtr(), LN0->getPointerInfo(),
4728 LN0->isVolatile(), LN0->isNonTemporal(),
4729 LN0->getAlignment());
4730 CombineTo(N, ExtLoad);
4731 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
4732 N0.getValueType(), ExtLoad);
4733 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4735 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
4737 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4741 // fold (zext (and/or/xor (load x), cst)) ->
4742 // (and/or/xor (zextload x), (zext cst))
4743 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4744 N0.getOpcode() == ISD::XOR) &&
4745 isa<LoadSDNode>(N0.getOperand(0)) &&
4746 N0.getOperand(1).getOpcode() == ISD::Constant &&
4747 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
4748 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4749 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4750 if (LN0->getExtensionType() != ISD::SEXTLOAD) {
4751 bool DoXform = true;
4752 SmallVector<SDNode*, 4> SetCCs;
4753 if (!N0.hasOneUse())
4754 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
4757 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), VT,
4758 LN0->getChain(), LN0->getBasePtr(),
4759 LN0->getPointerInfo(),
4762 LN0->isNonTemporal(),
4763 LN0->getAlignment());
4764 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4765 Mask = Mask.zext(VT.getSizeInBits());
4766 SDValue And = DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
4767 ExtLoad, DAG.getConstant(Mask, VT));
4768 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4769 SDLoc(N0.getOperand(0)),
4770 N0.getOperand(0).getValueType(), ExtLoad);
4772 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4773 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
4775 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4780 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
4781 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
4782 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4783 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4784 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4785 EVT MemVT = LN0->getMemoryVT();
4786 if ((!LegalOperations && !LN0->isVolatile()) ||
4787 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
4788 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
4790 LN0->getBasePtr(), LN0->getPointerInfo(),
4792 LN0->isVolatile(), LN0->isNonTemporal(),
4793 LN0->getAlignment());
4794 CombineTo(N, ExtLoad);
4795 CombineTo(N0.getNode(),
4796 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(),
4798 ExtLoad.getValue(1));
4799 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4803 if (N0.getOpcode() == ISD::SETCC) {
4804 if (!LegalOperations && VT.isVector()) {
4805 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
4806 // Only do this before legalize for now.
4807 EVT N0VT = N0.getOperand(0).getValueType();
4808 EVT EltVT = VT.getVectorElementType();
4809 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
4810 DAG.getConstant(1, EltVT));
4811 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4812 // We know that the # elements of the results is the same as the
4813 // # elements of the compare (and the # elements of the compare result
4814 // for that matter). Check to see that they are the same size. If so,
4815 // we know that the element size of the sext'd result matches the
4816 // element size of the compare operands.
4817 return DAG.getNode(ISD::AND, SDLoc(N), VT,
4818 DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
4820 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4821 DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT,
4822 &OneOps[0], OneOps.size()));
4824 // If the desired elements are smaller or larger than the source
4825 // elements we can use a matching integer vector type and then
4826 // truncate/sign extend
4827 EVT MatchingElementType =
4828 EVT::getIntegerVT(*DAG.getContext(),
4829 N0VT.getScalarType().getSizeInBits());
4830 EVT MatchingVectorType =
4831 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4832 N0VT.getVectorNumElements());
4834 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0),
4836 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4837 return DAG.getNode(ISD::AND, SDLoc(N), VT,
4838 DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT),
4839 DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT,
4840 &OneOps[0], OneOps.size()));
4843 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4845 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
4846 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4847 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4848 if (SCC.getNode()) return SCC;
4851 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
4852 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
4853 isa<ConstantSDNode>(N0.getOperand(1)) &&
4854 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
4856 SDValue ShAmt = N0.getOperand(1);
4857 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
4858 if (N0.getOpcode() == ISD::SHL) {
4859 SDValue InnerZExt = N0.getOperand(0);
4860 // If the original shl may be shifting out bits, do not perform this
4862 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
4863 InnerZExt.getOperand(0).getValueType().getSizeInBits();
4864 if (ShAmtVal > KnownZeroBits)
4870 // Ensure that the shift amount is wide enough for the shifted value.
4871 if (VT.getSizeInBits() >= 256)
4872 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
4874 return DAG.getNode(N0.getOpcode(), DL, VT,
4875 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
4882 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
4883 SDValue N0 = N->getOperand(0);
4884 EVT VT = N->getValueType(0);
4886 // fold (aext c1) -> c1
4887 if (isa<ConstantSDNode>(N0))
4888 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, N0);
4889 // fold (aext (aext x)) -> (aext x)
4890 // fold (aext (zext x)) -> (zext x)
4891 // fold (aext (sext x)) -> (sext x)
4892 if (N0.getOpcode() == ISD::ANY_EXTEND ||
4893 N0.getOpcode() == ISD::ZERO_EXTEND ||
4894 N0.getOpcode() == ISD::SIGN_EXTEND)
4895 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0));
4897 // fold (aext (truncate (load x))) -> (aext (smaller load x))
4898 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
4899 if (N0.getOpcode() == ISD::TRUNCATE) {
4900 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4901 if (NarrowLoad.getNode()) {
4902 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4903 if (NarrowLoad.getNode() != N0.getNode()) {
4904 CombineTo(N0.getNode(), NarrowLoad);
4905 // CombineTo deleted the truncate, if needed, but not what's under it.
4908 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4912 // fold (aext (truncate x))
4913 if (N0.getOpcode() == ISD::TRUNCATE) {
4914 SDValue TruncOp = N0.getOperand(0);
4915 if (TruncOp.getValueType() == VT)
4916 return TruncOp; // x iff x size == zext size.
4917 if (TruncOp.getValueType().bitsGT(VT))
4918 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, TruncOp);
4919 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, TruncOp);
4922 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
4923 // if the trunc is not free.
4924 if (N0.getOpcode() == ISD::AND &&
4925 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4926 N0.getOperand(1).getOpcode() == ISD::Constant &&
4927 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4928 N0.getValueType())) {
4929 SDValue X = N0.getOperand(0).getOperand(0);
4930 if (X.getValueType().bitsLT(VT)) {
4931 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, X);
4932 } else if (X.getValueType().bitsGT(VT)) {
4933 X = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, X);
4935 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4936 Mask = Mask.zext(VT.getSizeInBits());
4937 return DAG.getNode(ISD::AND, SDLoc(N), VT,
4938 X, DAG.getConstant(Mask, VT));
4941 // fold (aext (load x)) -> (aext (truncate (extload x)))
4942 // None of the supported targets knows how to perform load and any_ext
4943 // on vectors in one instruction. We only perform this transformation on
4945 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4946 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4947 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4948 bool DoXform = true;
4949 SmallVector<SDNode*, 4> SetCCs;
4950 if (!N0.hasOneUse())
4951 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
4953 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4954 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
4956 LN0->getBasePtr(), LN0->getPointerInfo(),
4958 LN0->isVolatile(), LN0->isNonTemporal(),
4959 LN0->getAlignment());
4960 CombineTo(N, ExtLoad);
4961 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
4962 N0.getValueType(), ExtLoad);
4963 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4964 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
4966 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4970 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
4971 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
4972 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
4973 if (N0.getOpcode() == ISD::LOAD &&
4974 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4976 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4977 EVT MemVT = LN0->getMemoryVT();
4978 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), SDLoc(N),
4979 VT, LN0->getChain(), LN0->getBasePtr(),
4980 LN0->getPointerInfo(), MemVT,
4981 LN0->isVolatile(), LN0->isNonTemporal(),
4982 LN0->getAlignment());
4983 CombineTo(N, ExtLoad);
4984 CombineTo(N0.getNode(),
4985 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
4986 N0.getValueType(), ExtLoad),
4987 ExtLoad.getValue(1));
4988 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4991 if (N0.getOpcode() == ISD::SETCC) {
4992 // aext(setcc) -> sext_in_reg(vsetcc) for vectors.
4993 // Only do this before legalize for now.
4994 if (VT.isVector() && !LegalOperations) {
4995 EVT N0VT = N0.getOperand(0).getValueType();
4996 // We know that the # elements of the results is the same as the
4997 // # elements of the compare (and the # elements of the compare result
4998 // for that matter). Check to see that they are the same size. If so,
4999 // we know that the element size of the sext'd result matches the
5000 // element size of the compare operands.
5001 if (VT.getSizeInBits() == N0VT.getSizeInBits())
5002 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
5004 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5005 // If the desired elements are smaller or larger than the source
5006 // elements we can use a matching integer vector type and then
5007 // truncate/sign extend
5009 EVT MatchingElementType =
5010 EVT::getIntegerVT(*DAG.getContext(),
5011 N0VT.getScalarType().getSizeInBits());
5012 EVT MatchingVectorType =
5013 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
5014 N0VT.getVectorNumElements());
5016 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0),
5018 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5019 return DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT);
5023 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
5025 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
5026 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
5027 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
5035 /// GetDemandedBits - See if the specified operand can be simplified with the
5036 /// knowledge that only the bits specified by Mask are used. If so, return the
5037 /// simpler operand, otherwise return a null SDValue.
5038 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
5039 switch (V.getOpcode()) {
5041 case ISD::Constant: {
5042 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode());
5043 assert(CV != 0 && "Const value should be ConstSDNode.");
5044 const APInt &CVal = CV->getAPIntValue();
5045 APInt NewVal = CVal & Mask;
5046 if (NewVal != CVal) {
5047 return DAG.getConstant(NewVal, V.getValueType());
5053 // If the LHS or RHS don't contribute bits to the or, drop them.
5054 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
5055 return V.getOperand(1);
5056 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
5057 return V.getOperand(0);
5060 // Only look at single-use SRLs.
5061 if (!V.getNode()->hasOneUse())
5063 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
5064 // See if we can recursively simplify the LHS.
5065 unsigned Amt = RHSC->getZExtValue();
5067 // Watch out for shift count overflow though.
5068 if (Amt >= Mask.getBitWidth()) break;
5069 APInt NewMask = Mask << Amt;
5070 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
5071 if (SimplifyLHS.getNode())
5072 return DAG.getNode(ISD::SRL, SDLoc(V), V.getValueType(),
5073 SimplifyLHS, V.getOperand(1));
5079 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
5080 /// bits and then truncated to a narrower type and where N is a multiple
5081 /// of number of bits of the narrower type, transform it to a narrower load
5082 /// from address + N / num of bits of new type. If the result is to be
5083 /// extended, also fold the extension to form a extending load.
5084 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
5085 unsigned Opc = N->getOpcode();
5087 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
5088 SDValue N0 = N->getOperand(0);
5089 EVT VT = N->getValueType(0);
5092 // This transformation isn't valid for vector loads.
5096 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
5098 if (Opc == ISD::SIGN_EXTEND_INREG) {
5099 ExtType = ISD::SEXTLOAD;
5100 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
5101 } else if (Opc == ISD::SRL) {
5102 // Another special-case: SRL is basically zero-extending a narrower value.
5103 ExtType = ISD::ZEXTLOAD;
5105 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5106 if (!N01) return SDValue();
5107 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
5108 VT.getSizeInBits() - N01->getZExtValue());
5110 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
5113 unsigned EVTBits = ExtVT.getSizeInBits();
5115 // Do not generate loads of non-round integer types since these can
5116 // be expensive (and would be wrong if the type is not byte sized).
5117 if (!ExtVT.isRound())
5121 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
5122 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5123 ShAmt = N01->getZExtValue();
5124 // Is the shift amount a multiple of size of VT?
5125 if ((ShAmt & (EVTBits-1)) == 0) {
5126 N0 = N0.getOperand(0);
5127 // Is the load width a multiple of size of VT?
5128 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
5132 // At this point, we must have a load or else we can't do the transform.
5133 if (!isa<LoadSDNode>(N0)) return SDValue();
5135 // Because a SRL must be assumed to *need* to zero-extend the high bits
5136 // (as opposed to anyext the high bits), we can't combine the zextload
5137 // lowering of SRL and an sextload.
5138 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD)
5141 // If the shift amount is larger than the input type then we're not
5142 // accessing any of the loaded bytes. If the load was a zextload/extload
5143 // then the result of the shift+trunc is zero/undef (handled elsewhere).
5144 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
5149 // If the load is shifted left (and the result isn't shifted back right),
5150 // we can fold the truncate through the shift.
5151 unsigned ShLeftAmt = 0;
5152 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
5153 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
5154 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5155 ShLeftAmt = N01->getZExtValue();
5156 N0 = N0.getOperand(0);
5160 // If we haven't found a load, we can't narrow it. Don't transform one with
5161 // multiple uses, this would require adding a new load.
5162 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse())
5165 // Don't change the width of a volatile load.
5166 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5167 if (LN0->isVolatile())
5170 // Verify that we are actually reducing a load width here.
5171 if (LN0->getMemoryVT().getSizeInBits() < EVTBits)
5174 // For the transform to be legal, the load must produce only two values
5175 // (the value loaded and the chain). Don't transform a pre-increment
5176 // load, for example, which produces an extra value. Otherwise the
5177 // transformation is not equivalent, and the downstream logic to replace
5178 // uses gets things wrong.
5179 if (LN0->getNumValues() > 2)
5182 EVT PtrType = N0.getOperand(1).getValueType();
5184 if (PtrType == MVT::Untyped || PtrType.isExtended())
5185 // It's not possible to generate a constant of extended or untyped type.
5188 // For big endian targets, we need to adjust the offset to the pointer to
5189 // load the correct bytes.
5190 if (TLI.isBigEndian()) {
5191 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
5192 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
5193 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
5196 uint64_t PtrOff = ShAmt / 8;
5197 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
5198 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LN0),
5199 PtrType, LN0->getBasePtr(),
5200 DAG.getConstant(PtrOff, PtrType));
5201 AddToWorkList(NewPtr.getNode());
5204 if (ExtType == ISD::NON_EXTLOAD)
5205 Load = DAG.getLoad(VT, SDLoc(N0), LN0->getChain(), NewPtr,
5206 LN0->getPointerInfo().getWithOffset(PtrOff),
5207 LN0->isVolatile(), LN0->isNonTemporal(),
5208 LN0->isInvariant(), NewAlign);
5210 Load = DAG.getExtLoad(ExtType, SDLoc(N0), VT, LN0->getChain(),NewPtr,
5211 LN0->getPointerInfo().getWithOffset(PtrOff),
5212 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
5215 // Replace the old load's chain with the new load's chain.
5216 WorkListRemover DeadNodes(*this);
5217 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
5219 // Shift the result left, if we've swallowed a left shift.
5220 SDValue Result = Load;
5221 if (ShLeftAmt != 0) {
5222 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
5223 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
5225 // If the shift amount is as large as the result size (but, presumably,
5226 // no larger than the source) then the useful bits of the result are
5227 // zero; we can't simply return the shortened shift, because the result
5228 // of that operation is undefined.
5229 if (ShLeftAmt >= VT.getSizeInBits())
5230 Result = DAG.getConstant(0, VT);
5232 Result = DAG.getNode(ISD::SHL, SDLoc(N0), VT,
5233 Result, DAG.getConstant(ShLeftAmt, ShImmTy));
5236 // Return the new loaded value.
5240 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
5241 SDValue N0 = N->getOperand(0);
5242 SDValue N1 = N->getOperand(1);
5243 EVT VT = N->getValueType(0);
5244 EVT EVT = cast<VTSDNode>(N1)->getVT();
5245 unsigned VTBits = VT.getScalarType().getSizeInBits();
5246 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
5248 // fold (sext_in_reg c1) -> c1
5249 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
5250 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, N0, N1);
5252 // If the input is already sign extended, just drop the extension.
5253 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
5256 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
5257 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
5258 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
5259 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
5260 N0.getOperand(0), N1);
5263 // fold (sext_in_reg (sext x)) -> (sext x)
5264 // fold (sext_in_reg (aext x)) -> (sext x)
5265 // if x is small enough.
5266 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
5267 SDValue N00 = N0.getOperand(0);
5268 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
5269 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
5270 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00, N1);
5273 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
5274 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
5275 return DAG.getZeroExtendInReg(N0, SDLoc(N), EVT);
5277 // fold operands of sext_in_reg based on knowledge that the top bits are not
5279 if (SimplifyDemandedBits(SDValue(N, 0)))
5280 return SDValue(N, 0);
5282 // fold (sext_in_reg (load x)) -> (smaller sextload x)
5283 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
5284 SDValue NarrowLoad = ReduceLoadWidth(N);
5285 if (NarrowLoad.getNode())
5288 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
5289 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
5290 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
5291 if (N0.getOpcode() == ISD::SRL) {
5292 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
5293 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
5294 // We can turn this into an SRA iff the input to the SRL is already sign
5296 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
5297 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
5298 return DAG.getNode(ISD::SRA, SDLoc(N), VT,
5299 N0.getOperand(0), N0.getOperand(1));
5303 // fold (sext_inreg (extload x)) -> (sextload x)
5304 if (ISD::isEXTLoad(N0.getNode()) &&
5305 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5306 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5307 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5308 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5309 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5310 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5312 LN0->getBasePtr(), LN0->getPointerInfo(),
5314 LN0->isVolatile(), LN0->isNonTemporal(),
5315 LN0->getAlignment());
5316 CombineTo(N, ExtLoad);
5317 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5318 AddToWorkList(ExtLoad.getNode());
5319 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5321 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
5322 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5324 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5325 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5326 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5327 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5328 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5330 LN0->getBasePtr(), LN0->getPointerInfo(),
5332 LN0->isVolatile(), LN0->isNonTemporal(),
5333 LN0->getAlignment());
5334 CombineTo(N, ExtLoad);
5335 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5336 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5339 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
5340 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
5341 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
5342 N0.getOperand(1), false);
5343 if (BSwap.getNode() != 0)
5344 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
5351 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
5352 SDValue N0 = N->getOperand(0);
5353 EVT VT = N->getValueType(0);
5354 bool isLE = TLI.isLittleEndian();
5357 if (N0.getValueType() == N->getValueType(0))
5359 // fold (truncate c1) -> c1
5360 if (isa<ConstantSDNode>(N0))
5361 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0);
5362 // fold (truncate (truncate x)) -> (truncate x)
5363 if (N0.getOpcode() == ISD::TRUNCATE)
5364 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
5365 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
5366 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
5367 N0.getOpcode() == ISD::SIGN_EXTEND ||
5368 N0.getOpcode() == ISD::ANY_EXTEND) {
5369 if (N0.getOperand(0).getValueType().bitsLT(VT))
5370 // if the source is smaller than the dest, we still need an extend
5371 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
5373 if (N0.getOperand(0).getValueType().bitsGT(VT))
5374 // if the source is larger than the dest, than we just need the truncate
5375 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
5376 // if the source and dest are the same type, we can drop both the extend
5377 // and the truncate.
5378 return N0.getOperand(0);
5381 // Fold extract-and-trunc into a narrow extract. For example:
5382 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
5383 // i32 y = TRUNCATE(i64 x)
5385 // v16i8 b = BITCAST (v2i64 val)
5386 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8)
5388 // Note: We only run this optimization after type legalization (which often
5389 // creates this pattern) and before operation legalization after which
5390 // we need to be more careful about the vector instructions that we generate.
5391 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5392 LegalTypes && !LegalOperations && N0->hasOneUse()) {
5394 EVT VecTy = N0.getOperand(0).getValueType();
5395 EVT ExTy = N0.getValueType();
5396 EVT TrTy = N->getValueType(0);
5398 unsigned NumElem = VecTy.getVectorNumElements();
5399 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits();
5401 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem);
5402 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size");
5404 SDValue EltNo = N0->getOperand(1);
5405 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
5406 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5407 EVT IndexTy = N0->getOperand(1).getValueType();
5408 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
5410 SDValue V = DAG.getNode(ISD::BITCAST, SDLoc(N),
5411 NVT, N0.getOperand(0));
5413 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
5415 DAG.getConstant(Index, IndexTy));
5419 // Fold a series of buildvector, bitcast, and truncate if possible.
5421 // (2xi32 trunc (bitcast ((4xi32)buildvector x, x, y, y) 2xi64)) to
5422 // (2xi32 (buildvector x, y)).
5423 if (Level == AfterLegalizeVectorOps && VT.isVector() &&
5424 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
5425 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
5426 N0.getOperand(0).hasOneUse()) {
5428 SDValue BuildVect = N0.getOperand(0);
5429 EVT BuildVectEltTy = BuildVect.getValueType().getVectorElementType();
5430 EVT TruncVecEltTy = VT.getVectorElementType();
5432 // Check that the element types match.
5433 if (BuildVectEltTy == TruncVecEltTy) {
5434 // Now we only need to compute the offset of the truncated elements.
5435 unsigned BuildVecNumElts = BuildVect.getNumOperands();
5436 unsigned TruncVecNumElts = VT.getVectorNumElements();
5437 unsigned TruncEltOffset = BuildVecNumElts / TruncVecNumElts;
5439 assert((BuildVecNumElts % TruncVecNumElts) == 0 &&
5440 "Invalid number of elements");
5442 SmallVector<SDValue, 8> Opnds;
5443 for (unsigned i = 0, e = BuildVecNumElts; i != e; i += TruncEltOffset)
5444 Opnds.push_back(BuildVect.getOperand(i));
5446 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, &Opnds[0],
5451 // See if we can simplify the input to this truncate through knowledge that
5452 // only the low bits are being used.
5453 // For example "trunc (or (shl x, 8), y)" // -> trunc y
5454 // Currently we only perform this optimization on scalars because vectors
5455 // may have different active low bits.
5456 if (!VT.isVector()) {
5458 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
5459 VT.getSizeInBits()));
5460 if (Shorter.getNode())
5461 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Shorter);
5463 // fold (truncate (load x)) -> (smaller load x)
5464 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
5465 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
5466 SDValue Reduced = ReduceLoadWidth(N);
5467 if (Reduced.getNode())
5470 // fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)),
5471 // where ... are all 'undef'.
5472 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) {
5473 SmallVector<EVT, 8> VTs;
5476 unsigned NumDefs = 0;
5478 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
5479 SDValue X = N0.getOperand(i);
5480 if (X.getOpcode() != ISD::UNDEF) {
5485 // Stop if more than one members are non-undef.
5488 VTs.push_back(EVT::getVectorVT(*DAG.getContext(),
5489 VT.getVectorElementType(),
5490 X.getValueType().getVectorNumElements()));
5494 return DAG.getUNDEF(VT);
5497 assert(V.getNode() && "The single defined operand is empty!");
5498 SmallVector<SDValue, 8> Opnds;
5499 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
5501 Opnds.push_back(DAG.getUNDEF(VTs[i]));
5504 SDValue NV = DAG.getNode(ISD::TRUNCATE, SDLoc(V), VTs[i], V);
5505 AddToWorkList(NV.getNode());
5506 Opnds.push_back(NV);
5508 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
5509 &Opnds[0], Opnds.size());
5513 // Simplify the operands using demanded-bits information.
5514 if (!VT.isVector() &&
5515 SimplifyDemandedBits(SDValue(N, 0)))
5516 return SDValue(N, 0);
5521 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
5522 SDValue Elt = N->getOperand(i);
5523 if (Elt.getOpcode() != ISD::MERGE_VALUES)
5524 return Elt.getNode();
5525 return Elt.getOperand(Elt.getResNo()).getNode();
5528 /// CombineConsecutiveLoads - build_pair (load, load) -> load
5529 /// if load locations are consecutive.
5530 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
5531 assert(N->getOpcode() == ISD::BUILD_PAIR);
5533 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
5534 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
5535 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
5536 LD1->getPointerInfo().getAddrSpace() !=
5537 LD2->getPointerInfo().getAddrSpace())
5539 EVT LD1VT = LD1->getValueType(0);
5541 if (ISD::isNON_EXTLoad(LD2) &&
5543 // If both are volatile this would reduce the number of volatile loads.
5544 // If one is volatile it might be ok, but play conservative and bail out.
5545 !LD1->isVolatile() &&
5546 !LD2->isVolatile() &&
5547 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
5548 unsigned Align = LD1->getAlignment();
5549 unsigned NewAlign = TLI.getDataLayout()->
5550 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5552 if (NewAlign <= Align &&
5553 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
5554 return DAG.getLoad(VT, SDLoc(N), LD1->getChain(),
5555 LD1->getBasePtr(), LD1->getPointerInfo(),
5556 false, false, false, Align);
5562 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
5563 SDValue N0 = N->getOperand(0);
5564 EVT VT = N->getValueType(0);
5566 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
5567 // Only do this before legalize, since afterward the target may be depending
5568 // on the bitconvert.
5569 // First check to see if this is all constant.
5571 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
5573 bool isSimple = true;
5574 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
5575 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
5576 N0.getOperand(i).getOpcode() != ISD::Constant &&
5577 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
5582 EVT DestEltVT = N->getValueType(0).getVectorElementType();
5583 assert(!DestEltVT.isVector() &&
5584 "Element type of vector ValueType must not be vector!");
5586 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
5589 // If the input is a constant, let getNode fold it.
5590 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
5591 SDValue Res = DAG.getNode(ISD::BITCAST, SDLoc(N), VT, N0);
5592 if (Res.getNode() != N) {
5593 if (!LegalOperations ||
5594 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
5597 // Folding it resulted in an illegal node, and it's too late to
5598 // do that. Clean up the old node and forego the transformation.
5599 // Ideally this won't happen very often, because instcombine
5600 // and the earlier dagcombine runs (where illegal nodes are
5601 // permitted) should have folded most of them already.
5602 DAG.DeleteNode(Res.getNode());
5606 // (conv (conv x, t1), t2) -> (conv x, t2)
5607 if (N0.getOpcode() == ISD::BITCAST)
5608 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT,
5611 // fold (conv (load x)) -> (load (conv*)x)
5612 // If the resultant load doesn't need a higher alignment than the original!
5613 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
5614 // Do not change the width of a volatile load.
5615 !cast<LoadSDNode>(N0)->isVolatile() &&
5616 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
5617 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5618 unsigned Align = TLI.getDataLayout()->
5619 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5620 unsigned OrigAlign = LN0->getAlignment();
5622 if (Align <= OrigAlign) {
5623 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(),
5624 LN0->getBasePtr(), LN0->getPointerInfo(),
5625 LN0->isVolatile(), LN0->isNonTemporal(),
5626 LN0->isInvariant(), OrigAlign);
5628 CombineTo(N0.getNode(),
5629 DAG.getNode(ISD::BITCAST, SDLoc(N0),
5630 N0.getValueType(), Load),
5636 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
5637 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
5638 // This often reduces constant pool loads.
5639 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) ||
5640 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) &&
5641 N0.getNode()->hasOneUse() && VT.isInteger() &&
5642 !VT.isVector() && !N0.getValueType().isVector()) {
5643 SDValue NewConv = DAG.getNode(ISD::BITCAST, SDLoc(N0), VT,
5645 AddToWorkList(NewConv.getNode());
5647 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5648 if (N0.getOpcode() == ISD::FNEG)
5649 return DAG.getNode(ISD::XOR, SDLoc(N), VT,
5650 NewConv, DAG.getConstant(SignBit, VT));
5651 assert(N0.getOpcode() == ISD::FABS);
5652 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5653 NewConv, DAG.getConstant(~SignBit, VT));
5656 // fold (bitconvert (fcopysign cst, x)) ->
5657 // (or (and (bitconvert x), sign), (and cst, (not sign)))
5658 // Note that we don't handle (copysign x, cst) because this can always be
5659 // folded to an fneg or fabs.
5660 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
5661 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
5662 VT.isInteger() && !VT.isVector()) {
5663 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
5664 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
5665 if (isTypeLegal(IntXVT)) {
5666 SDValue X = DAG.getNode(ISD::BITCAST, SDLoc(N0),
5667 IntXVT, N0.getOperand(1));
5668 AddToWorkList(X.getNode());
5670 // If X has a different width than the result/lhs, sext it or truncate it.
5671 unsigned VTWidth = VT.getSizeInBits();
5672 if (OrigXWidth < VTWidth) {
5673 X = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, X);
5674 AddToWorkList(X.getNode());
5675 } else if (OrigXWidth > VTWidth) {
5676 // To get the sign bit in the right place, we have to shift it right
5677 // before truncating.
5678 X = DAG.getNode(ISD::SRL, SDLoc(X),
5679 X.getValueType(), X,
5680 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
5681 AddToWorkList(X.getNode());
5682 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);
5683 AddToWorkList(X.getNode());
5686 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5687 X = DAG.getNode(ISD::AND, SDLoc(X), VT,
5688 X, DAG.getConstant(SignBit, VT));
5689 AddToWorkList(X.getNode());
5691 SDValue Cst = DAG.getNode(ISD::BITCAST, SDLoc(N0),
5692 VT, N0.getOperand(0));
5693 Cst = DAG.getNode(ISD::AND, SDLoc(Cst), VT,
5694 Cst, DAG.getConstant(~SignBit, VT));
5695 AddToWorkList(Cst.getNode());
5697 return DAG.getNode(ISD::OR, SDLoc(N), VT, X, Cst);
5701 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
5702 if (N0.getOpcode() == ISD::BUILD_PAIR) {
5703 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
5704 if (CombineLD.getNode())
5711 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
5712 EVT VT = N->getValueType(0);
5713 return CombineConsecutiveLoads(N, VT);
5716 /// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector
5717 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
5718 /// destination element value type.
5719 SDValue DAGCombiner::
5720 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
5721 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
5723 // If this is already the right type, we're done.
5724 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
5726 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
5727 unsigned DstBitSize = DstEltVT.getSizeInBits();
5729 // If this is a conversion of N elements of one type to N elements of another
5730 // type, convert each element. This handles FP<->INT cases.
5731 if (SrcBitSize == DstBitSize) {
5732 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5733 BV->getValueType(0).getVectorNumElements());
5735 // Due to the FP element handling below calling this routine recursively,
5736 // we can end up with a scalar-to-vector node here.
5737 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
5738 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(BV), VT,
5739 DAG.getNode(ISD::BITCAST, SDLoc(BV),
5740 DstEltVT, BV->getOperand(0)));
5742 SmallVector<SDValue, 8> Ops;
5743 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5744 SDValue Op = BV->getOperand(i);
5745 // If the vector element type is not legal, the BUILD_VECTOR operands
5746 // are promoted and implicitly truncated. Make that explicit here.
5747 if (Op.getValueType() != SrcEltVT)
5748 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(BV), SrcEltVT, Op);
5749 Ops.push_back(DAG.getNode(ISD::BITCAST, SDLoc(BV),
5751 AddToWorkList(Ops.back().getNode());
5753 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT,
5754 &Ops[0], Ops.size());
5757 // Otherwise, we're growing or shrinking the elements. To avoid having to
5758 // handle annoying details of growing/shrinking FP values, we convert them to
5760 if (SrcEltVT.isFloatingPoint()) {
5761 // Convert the input float vector to a int vector where the elements are the
5763 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
5764 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
5765 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
5769 // Now we know the input is an integer vector. If the output is a FP type,
5770 // convert to integer first, then to FP of the right size.
5771 if (DstEltVT.isFloatingPoint()) {
5772 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
5773 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
5774 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
5776 // Next, convert to FP elements of the same size.
5777 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
5780 // Okay, we know the src/dst types are both integers of differing types.
5781 // Handling growing first.
5782 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
5783 if (SrcBitSize < DstBitSize) {
5784 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
5786 SmallVector<SDValue, 8> Ops;
5787 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
5788 i += NumInputsPerOutput) {
5789 bool isLE = TLI.isLittleEndian();
5790 APInt NewBits = APInt(DstBitSize, 0);
5791 bool EltIsUndef = true;
5792 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
5793 // Shift the previously computed bits over.
5794 NewBits <<= SrcBitSize;
5795 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
5796 if (Op.getOpcode() == ISD::UNDEF) continue;
5799 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
5800 zextOrTrunc(SrcBitSize).zext(DstBitSize);
5804 Ops.push_back(DAG.getUNDEF(DstEltVT));
5806 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
5809 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
5810 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT,
5811 &Ops[0], Ops.size());
5814 // Finally, this must be the case where we are shrinking elements: each input
5815 // turns into multiple outputs.
5816 bool isS2V = ISD::isScalarToVector(BV);
5817 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
5818 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5819 NumOutputsPerInput*BV->getNumOperands());
5820 SmallVector<SDValue, 8> Ops;
5822 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5823 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
5824 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
5825 Ops.push_back(DAG.getUNDEF(DstEltVT));
5829 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
5830 getAPIntValue().zextOrTrunc(SrcBitSize);
5832 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
5833 APInt ThisVal = OpVal.trunc(DstBitSize);
5834 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
5835 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
5836 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
5837 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(BV), VT,
5839 OpVal = OpVal.lshr(DstBitSize);
5842 // For big endian targets, swap the order of the pieces of each element.
5843 if (TLI.isBigEndian())
5844 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
5847 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT,
5848 &Ops[0], Ops.size());
5851 SDValue DAGCombiner::visitFADD(SDNode *N) {
5852 SDValue N0 = N->getOperand(0);
5853 SDValue N1 = N->getOperand(1);
5854 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5855 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5856 EVT VT = N->getValueType(0);
5859 if (VT.isVector()) {
5860 SDValue FoldedVOp = SimplifyVBinOp(N);
5861 if (FoldedVOp.getNode()) return FoldedVOp;
5864 // fold (fadd c1, c2) -> c1 + c2
5866 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N1);
5867 // canonicalize constant to RHS
5868 if (N0CFP && !N1CFP)
5869 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N0);
5870 // fold (fadd A, 0) -> A
5871 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5872 N1CFP->getValueAPF().isZero())
5874 // fold (fadd A, (fneg B)) -> (fsub A, B)
5875 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5876 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
5877 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0,
5878 GetNegatedExpression(N1, DAG, LegalOperations));
5879 // fold (fadd (fneg A), B) -> (fsub B, A)
5880 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5881 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
5882 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N1,
5883 GetNegatedExpression(N0, DAG, LegalOperations));
5885 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
5886 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5887 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
5888 isa<ConstantFPSDNode>(N0.getOperand(1)))
5889 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0.getOperand(0),
5890 DAG.getNode(ISD::FADD, SDLoc(N), VT,
5891 N0.getOperand(1), N1));
5893 // No FP constant should be created after legalization as Instruction
5894 // Selection pass has hard time in dealing with FP constant.
5896 // We don't need test this condition for transformation like following, as
5897 // the DAG being transformed implies it is legal to take FP constant as
5900 // (fadd (fmul c, x), x) -> (fmul c+1, x)
5902 bool AllowNewFpConst = (Level < AfterLegalizeDAG);
5904 // If allow, fold (fadd (fneg x), x) -> 0.0
5905 if (AllowNewFpConst && DAG.getTarget().Options.UnsafeFPMath &&
5906 N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) {
5907 return DAG.getConstantFP(0.0, VT);
5910 // If allow, fold (fadd x, (fneg x)) -> 0.0
5911 if (AllowNewFpConst && DAG.getTarget().Options.UnsafeFPMath &&
5912 N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0) {
5913 return DAG.getConstantFP(0.0, VT);
5916 // In unsafe math mode, we can fold chains of FADD's of the same value
5917 // into multiplications. This transform is not safe in general because
5918 // we are reducing the number of rounding steps.
5919 if (DAG.getTarget().Options.UnsafeFPMath &&
5920 TLI.isOperationLegalOrCustom(ISD::FMUL, VT) &&
5922 if (N0.getOpcode() == ISD::FMUL) {
5923 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
5924 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
5926 // (fadd (fmul c, x), x) -> (fmul x, c+1)
5927 if (CFP00 && !CFP01 && N0.getOperand(1) == N1) {
5928 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
5930 DAG.getConstantFP(1.0, VT));
5931 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
5935 // (fadd (fmul x, c), x) -> (fmul x, c+1)
5936 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) {
5937 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
5939 DAG.getConstantFP(1.0, VT));
5940 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
5944 // (fadd (fmul c, x), (fadd x, x)) -> (fmul x, c+2)
5945 if (CFP00 && !CFP01 && N1.getOpcode() == ISD::FADD &&
5946 N1.getOperand(0) == N1.getOperand(1) &&
5947 N0.getOperand(1) == N1.getOperand(0)) {
5948 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
5950 DAG.getConstantFP(2.0, VT));
5951 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
5952 N0.getOperand(1), NewCFP);
5955 // (fadd (fmul x, c), (fadd x, x)) -> (fmul x, c+2)
5956 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD &&
5957 N1.getOperand(0) == N1.getOperand(1) &&
5958 N0.getOperand(0) == N1.getOperand(0)) {
5959 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
5961 DAG.getConstantFP(2.0, VT));
5962 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
5963 N0.getOperand(0), NewCFP);
5967 if (N1.getOpcode() == ISD::FMUL) {
5968 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
5969 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1));
5971 // (fadd x, (fmul c, x)) -> (fmul x, c+1)
5972 if (CFP10 && !CFP11 && N1.getOperand(1) == N0) {
5973 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
5975 DAG.getConstantFP(1.0, VT));
5976 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
5980 // (fadd x, (fmul x, c)) -> (fmul x, c+1)
5981 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) {
5982 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
5984 DAG.getConstantFP(1.0, VT));
5985 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
5990 // (fadd (fadd x, x), (fmul c, x)) -> (fmul x, c+2)
5991 if (CFP10 && !CFP11 && N0.getOpcode() == ISD::FADD &&
5992 N0.getOperand(0) == N0.getOperand(1) &&
5993 N1.getOperand(1) == N0.getOperand(0)) {
5994 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
5996 DAG.getConstantFP(2.0, VT));
5997 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
5998 N1.getOperand(1), NewCFP);
6001 // (fadd (fadd x, x), (fmul x, c)) -> (fmul x, c+2)
6002 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD &&
6003 N0.getOperand(0) == N0.getOperand(1) &&
6004 N1.getOperand(0) == N0.getOperand(0)) {
6005 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6007 DAG.getConstantFP(2.0, VT));
6008 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6009 N1.getOperand(0), NewCFP);
6013 if (N0.getOpcode() == ISD::FADD && AllowNewFpConst) {
6014 ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
6015 // (fadd (fadd x, x), x) -> (fmul x, 3.0)
6016 if (!CFP && N0.getOperand(0) == N0.getOperand(1) &&
6017 (N0.getOperand(0) == N1)) {
6018 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6019 N1, DAG.getConstantFP(3.0, VT));
6023 if (N1.getOpcode() == ISD::FADD && AllowNewFpConst) {
6024 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
6025 // (fadd x, (fadd x, x)) -> (fmul x, 3.0)
6026 if (!CFP10 && N1.getOperand(0) == N1.getOperand(1) &&
6027 N1.getOperand(0) == N0) {
6028 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6029 N0, DAG.getConstantFP(3.0, VT));
6033 // (fadd (fadd x, x), (fadd x, x)) -> (fmul x, 4.0)
6034 if (AllowNewFpConst &&
6035 N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
6036 N0.getOperand(0) == N0.getOperand(1) &&
6037 N1.getOperand(0) == N1.getOperand(1) &&
6038 N0.getOperand(0) == N1.getOperand(0)) {
6039 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6041 DAG.getConstantFP(4.0, VT));
6045 // FADD -> FMA combines:
6046 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast ||
6047 DAG.getTarget().Options.UnsafeFPMath) &&
6048 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) &&
6049 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) {
6051 // fold (fadd (fmul x, y), z) -> (fma x, y, z)
6052 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) {
6053 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6054 N0.getOperand(0), N0.getOperand(1), N1);
6057 // fold (fadd x, (fmul y, z)) -> (fma y, z, x)
6058 // Note: Commutes FADD operands.
6059 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) {
6060 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6061 N1.getOperand(0), N1.getOperand(1), N0);
6068 SDValue DAGCombiner::visitFSUB(SDNode *N) {
6069 SDValue N0 = N->getOperand(0);
6070 SDValue N1 = N->getOperand(1);
6071 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6072 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6073 EVT VT = N->getValueType(0);
6077 if (VT.isVector()) {
6078 SDValue FoldedVOp = SimplifyVBinOp(N);
6079 if (FoldedVOp.getNode()) return FoldedVOp;
6082 // fold (fsub c1, c2) -> c1-c2
6084 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0, N1);
6085 // fold (fsub A, 0) -> A
6086 if (DAG.getTarget().Options.UnsafeFPMath &&
6087 N1CFP && N1CFP->getValueAPF().isZero())
6089 // fold (fsub 0, B) -> -B
6090 if (DAG.getTarget().Options.UnsafeFPMath &&
6091 N0CFP && N0CFP->getValueAPF().isZero()) {
6092 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options))
6093 return GetNegatedExpression(N1, DAG, LegalOperations);
6094 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6095 return DAG.getNode(ISD::FNEG, dl, VT, N1);
6097 // fold (fsub A, (fneg B)) -> (fadd A, B)
6098 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options))
6099 return DAG.getNode(ISD::FADD, dl, VT, N0,
6100 GetNegatedExpression(N1, DAG, LegalOperations));
6102 // If 'unsafe math' is enabled, fold
6103 // (fsub x, x) -> 0.0 &
6104 // (fsub x, (fadd x, y)) -> (fneg y) &
6105 // (fsub x, (fadd y, x)) -> (fneg y)
6106 if (DAG.getTarget().Options.UnsafeFPMath) {
6108 return DAG.getConstantFP(0.0f, VT);
6110 if (N1.getOpcode() == ISD::FADD) {
6111 SDValue N10 = N1->getOperand(0);
6112 SDValue N11 = N1->getOperand(1);
6114 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI,
6115 &DAG.getTarget().Options))
6116 return GetNegatedExpression(N11, DAG, LegalOperations);
6117 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI,
6118 &DAG.getTarget().Options))
6119 return GetNegatedExpression(N10, DAG, LegalOperations);
6123 // FSUB -> FMA combines:
6124 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast ||
6125 DAG.getTarget().Options.UnsafeFPMath) &&
6126 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) &&
6127 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) {
6129 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
6130 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) {
6131 return DAG.getNode(ISD::FMA, dl, VT,
6132 N0.getOperand(0), N0.getOperand(1),
6133 DAG.getNode(ISD::FNEG, dl, VT, N1));
6136 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
6137 // Note: Commutes FSUB operands.
6138 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) {
6139 return DAG.getNode(ISD::FMA, dl, VT,
6140 DAG.getNode(ISD::FNEG, dl, VT,
6142 N1.getOperand(1), N0);
6145 // fold (fsub (-(fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
6146 if (N0.getOpcode() == ISD::FNEG &&
6147 N0.getOperand(0).getOpcode() == ISD::FMUL &&
6148 N0->hasOneUse() && N0.getOperand(0).hasOneUse()) {
6149 SDValue N00 = N0.getOperand(0).getOperand(0);
6150 SDValue N01 = N0.getOperand(0).getOperand(1);
6151 return DAG.getNode(ISD::FMA, dl, VT,
6152 DAG.getNode(ISD::FNEG, dl, VT, N00), N01,
6153 DAG.getNode(ISD::FNEG, dl, VT, N1));
6160 SDValue DAGCombiner::visitFMUL(SDNode *N) {
6161 SDValue N0 = N->getOperand(0);
6162 SDValue N1 = N->getOperand(1);
6163 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6164 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6165 EVT VT = N->getValueType(0);
6166 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6169 if (VT.isVector()) {
6170 SDValue FoldedVOp = SimplifyVBinOp(N);
6171 if (FoldedVOp.getNode()) return FoldedVOp;
6174 // fold (fmul c1, c2) -> c1*c2
6176 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0, N1);
6177 // canonicalize constant to RHS
6178 if (N0CFP && !N1CFP)
6179 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N1, N0);
6180 // fold (fmul A, 0) -> 0
6181 if (DAG.getTarget().Options.UnsafeFPMath &&
6182 N1CFP && N1CFP->getValueAPF().isZero())
6184 // fold (fmul A, 0) -> 0, vector edition.
6185 if (DAG.getTarget().Options.UnsafeFPMath &&
6186 ISD::isBuildVectorAllZeros(N1.getNode()))
6188 // fold (fmul A, 1.0) -> A
6189 if (N1CFP && N1CFP->isExactlyValue(1.0))
6191 // fold (fmul X, 2.0) -> (fadd X, X)
6192 if (N1CFP && N1CFP->isExactlyValue(+2.0))
6193 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N0);
6194 // fold (fmul X, -1.0) -> (fneg X)
6195 if (N1CFP && N1CFP->isExactlyValue(-1.0))
6196 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6197 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0);
6199 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
6200 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
6201 &DAG.getTarget().Options)) {
6202 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI,
6203 &DAG.getTarget().Options)) {
6204 // Both can be negated for free, check to see if at least one is cheaper
6206 if (LHSNeg == 2 || RHSNeg == 2)
6207 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6208 GetNegatedExpression(N0, DAG, LegalOperations),
6209 GetNegatedExpression(N1, DAG, LegalOperations));
6213 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
6214 if (DAG.getTarget().Options.UnsafeFPMath &&
6215 N1CFP && N0.getOpcode() == ISD::FMUL &&
6216 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
6217 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0.getOperand(0),
6218 DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6219 N0.getOperand(1), N1));
6224 SDValue DAGCombiner::visitFMA(SDNode *N) {
6225 SDValue N0 = N->getOperand(0);
6226 SDValue N1 = N->getOperand(1);
6227 SDValue N2 = N->getOperand(2);
6228 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6229 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6230 EVT VT = N->getValueType(0);
6233 if (DAG.getTarget().Options.UnsafeFPMath) {
6234 if (N0CFP && N0CFP->isZero())
6236 if (N1CFP && N1CFP->isZero())
6239 if (N0CFP && N0CFP->isExactlyValue(1.0))
6240 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N2);
6241 if (N1CFP && N1CFP->isExactlyValue(1.0))
6242 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N2);
6244 // Canonicalize (fma c, x, y) -> (fma x, c, y)
6245 if (N0CFP && !N1CFP)
6246 return DAG.getNode(ISD::FMA, SDLoc(N), VT, N1, N0, N2);
6248 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2)
6249 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
6250 N2.getOpcode() == ISD::FMUL &&
6251 N0 == N2.getOperand(0) &&
6252 N2.getOperand(1).getOpcode() == ISD::ConstantFP) {
6253 return DAG.getNode(ISD::FMUL, dl, VT, N0,
6254 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1)));
6258 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y)
6259 if (DAG.getTarget().Options.UnsafeFPMath &&
6260 N0.getOpcode() == ISD::FMUL && N1CFP &&
6261 N0.getOperand(1).getOpcode() == ISD::ConstantFP) {
6262 return DAG.getNode(ISD::FMA, dl, VT,
6264 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)),
6268 // (fma x, 1, y) -> (fadd x, y)
6269 // (fma x, -1, y) -> (fadd (fneg x), y)
6271 if (N1CFP->isExactlyValue(1.0))
6272 return DAG.getNode(ISD::FADD, dl, VT, N0, N2);
6274 if (N1CFP->isExactlyValue(-1.0) &&
6275 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) {
6276 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0);
6277 AddToWorkList(RHSNeg.getNode());
6278 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg);
6282 // (fma x, c, x) -> (fmul x, (c+1))
6283 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && N0 == N2) {
6284 return DAG.getNode(ISD::FMUL, dl, VT,
6286 DAG.getNode(ISD::FADD, dl, VT,
6287 N1, DAG.getConstantFP(1.0, VT)));
6290 // (fma x, c, (fneg x)) -> (fmul x, (c-1))
6291 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
6292 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) {
6293 return DAG.getNode(ISD::FMUL, dl, VT,
6295 DAG.getNode(ISD::FADD, dl, VT,
6296 N1, DAG.getConstantFP(-1.0, VT)));
6303 SDValue DAGCombiner::visitFDIV(SDNode *N) {
6304 SDValue N0 = N->getOperand(0);
6305 SDValue N1 = N->getOperand(1);
6306 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6307 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6308 EVT VT = N->getValueType(0);
6309 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6312 if (VT.isVector()) {
6313 SDValue FoldedVOp = SimplifyVBinOp(N);
6314 if (FoldedVOp.getNode()) return FoldedVOp;
6317 // fold (fdiv c1, c2) -> c1/c2
6319 return DAG.getNode(ISD::FDIV, SDLoc(N), VT, N0, N1);
6321 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable.
6322 if (N1CFP && DAG.getTarget().Options.UnsafeFPMath) {
6323 // Compute the reciprocal 1.0 / c2.
6324 APFloat N1APF = N1CFP->getValueAPF();
6325 APFloat Recip(N1APF.getSemantics(), 1); // 1.0
6326 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven);
6327 // Only do the transform if the reciprocal is a legal fp immediate that
6328 // isn't too nasty (eg NaN, denormal, ...).
6329 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty
6330 (!LegalOperations ||
6331 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM
6332 // backend)... we should handle this gracefully after Legalize.
6333 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) ||
6334 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) ||
6335 TLI.isFPImmLegal(Recip, VT)))
6336 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0,
6337 DAG.getConstantFP(Recip, VT));
6340 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
6341 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
6342 &DAG.getTarget().Options)) {
6343 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI,
6344 &DAG.getTarget().Options)) {
6345 // Both can be negated for free, check to see if at least one is cheaper
6347 if (LHSNeg == 2 || RHSNeg == 2)
6348 return DAG.getNode(ISD::FDIV, SDLoc(N), VT,
6349 GetNegatedExpression(N0, DAG, LegalOperations),
6350 GetNegatedExpression(N1, DAG, LegalOperations));
6357 SDValue DAGCombiner::visitFREM(SDNode *N) {
6358 SDValue N0 = N->getOperand(0);
6359 SDValue N1 = N->getOperand(1);
6360 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6361 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6362 EVT VT = N->getValueType(0);
6364 // fold (frem c1, c2) -> fmod(c1,c2)
6366 return DAG.getNode(ISD::FREM, SDLoc(N), VT, N0, N1);
6371 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
6372 SDValue N0 = N->getOperand(0);
6373 SDValue N1 = N->getOperand(1);
6374 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6375 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6376 EVT VT = N->getValueType(0);
6378 if (N0CFP && N1CFP) // Constant fold
6379 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1);
6382 const APFloat& V = N1CFP->getValueAPF();
6383 // copysign(x, c1) -> fabs(x) iff ispos(c1)
6384 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
6385 if (!V.isNegative()) {
6386 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
6387 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
6389 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6390 return DAG.getNode(ISD::FNEG, SDLoc(N), VT,
6391 DAG.getNode(ISD::FABS, SDLoc(N0), VT, N0));
6395 // copysign(fabs(x), y) -> copysign(x, y)
6396 // copysign(fneg(x), y) -> copysign(x, y)
6397 // copysign(copysign(x,z), y) -> copysign(x, y)
6398 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
6399 N0.getOpcode() == ISD::FCOPYSIGN)
6400 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
6401 N0.getOperand(0), N1);
6403 // copysign(x, abs(y)) -> abs(x)
6404 if (N1.getOpcode() == ISD::FABS)
6405 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
6407 // copysign(x, copysign(y,z)) -> copysign(x, z)
6408 if (N1.getOpcode() == ISD::FCOPYSIGN)
6409 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
6410 N0, N1.getOperand(1));
6412 // copysign(x, fp_extend(y)) -> copysign(x, y)
6413 // copysign(x, fp_round(y)) -> copysign(x, y)
6414 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
6415 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
6416 N0, N1.getOperand(0));
6421 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
6422 SDValue N0 = N->getOperand(0);
6423 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
6424 EVT VT = N->getValueType(0);
6425 EVT OpVT = N0.getValueType();
6427 // fold (sint_to_fp c1) -> c1fp
6429 // ...but only if the target supports immediate floating-point values
6430 (!LegalOperations ||
6431 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
6432 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
6434 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
6435 // but UINT_TO_FP is legal on this target, try to convert.
6436 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
6437 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
6438 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
6439 if (DAG.SignBitIsZero(N0))
6440 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
6443 // The next optimizations are desireable only if SELECT_CC can be lowered.
6444 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
6445 // having to say they don't support SELECT_CC on every type the DAG knows
6446 // about, since there is no way to mark an opcode illegal at all value types
6447 // (See also visitSELECT)
6448 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) {
6449 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
6450 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
6452 (!LegalOperations ||
6453 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6455 { N0.getOperand(0), N0.getOperand(1),
6456 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT),
6458 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops, 5);
6461 // fold (sint_to_fp (zext (setcc x, y, cc))) ->
6462 // (select_cc x, y, 1.0, 0.0,, cc)
6463 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
6464 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
6465 (!LegalOperations ||
6466 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6468 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1),
6469 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT),
6470 N0.getOperand(0).getOperand(2) };
6471 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops, 5);
6478 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
6479 SDValue N0 = N->getOperand(0);
6480 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
6481 EVT VT = N->getValueType(0);
6482 EVT OpVT = N0.getValueType();
6484 // fold (uint_to_fp c1) -> c1fp
6486 // ...but only if the target supports immediate floating-point values
6487 (!LegalOperations ||
6488 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
6489 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
6491 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
6492 // but SINT_TO_FP is legal on this target, try to convert.
6493 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
6494 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
6495 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
6496 if (DAG.SignBitIsZero(N0))
6497 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
6500 // The next optimizations are desireable only if SELECT_CC can be lowered.
6501 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
6502 // having to say they don't support SELECT_CC on every type the DAG knows
6503 // about, since there is no way to mark an opcode illegal at all value types
6504 // (See also visitSELECT)
6505 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) {
6506 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
6508 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
6509 (!LegalOperations ||
6510 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6512 { N0.getOperand(0), N0.getOperand(1),
6513 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT),
6515 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops, 5);
6522 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
6523 SDValue N0 = N->getOperand(0);
6524 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6525 EVT VT = N->getValueType(0);
6527 // fold (fp_to_sint c1fp) -> c1
6529 return DAG.getNode(ISD::FP_TO_SINT, SDLoc(N), VT, N0);
6534 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
6535 SDValue N0 = N->getOperand(0);
6536 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6537 EVT VT = N->getValueType(0);
6539 // fold (fp_to_uint c1fp) -> c1
6541 return DAG.getNode(ISD::FP_TO_UINT, SDLoc(N), VT, N0);
6546 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
6547 SDValue N0 = N->getOperand(0);
6548 SDValue N1 = N->getOperand(1);
6549 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6550 EVT VT = N->getValueType(0);
6552 // fold (fp_round c1fp) -> c1fp
6554 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0, N1);
6556 // fold (fp_round (fp_extend x)) -> x
6557 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
6558 return N0.getOperand(0);
6560 // fold (fp_round (fp_round x)) -> (fp_round x)
6561 if (N0.getOpcode() == ISD::FP_ROUND) {
6562 // This is a value preserving truncation if both round's are.
6563 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
6564 N0.getNode()->getConstantOperandVal(1) == 1;
6565 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0.getOperand(0),
6566 DAG.getIntPtrConstant(IsTrunc));
6569 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
6570 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
6571 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, SDLoc(N0), VT,
6572 N0.getOperand(0), N1);
6573 AddToWorkList(Tmp.getNode());
6574 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
6575 Tmp, N0.getOperand(1));
6581 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
6582 SDValue N0 = N->getOperand(0);
6583 EVT VT = N->getValueType(0);
6584 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
6585 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6587 // fold (fp_round_inreg c1fp) -> c1fp
6588 if (N0CFP && isTypeLegal(EVT)) {
6589 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
6590 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Round);
6596 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
6597 SDValue N0 = N->getOperand(0);
6598 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6599 EVT VT = N->getValueType(0);
6601 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
6602 if (N->hasOneUse() &&
6603 N->use_begin()->getOpcode() == ISD::FP_ROUND)
6606 // fold (fp_extend c1fp) -> c1fp
6608 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, N0);
6610 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
6612 if (N0.getOpcode() == ISD::FP_ROUND
6613 && N0.getNode()->getConstantOperandVal(1) == 1) {
6614 SDValue In = N0.getOperand(0);
6615 if (In.getValueType() == VT) return In;
6616 if (VT.bitsLT(In.getValueType()))
6617 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT,
6618 In, N0.getOperand(1));
6619 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, In);
6622 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
6623 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
6624 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6625 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
6626 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6627 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
6629 LN0->getBasePtr(), LN0->getPointerInfo(),
6631 LN0->isVolatile(), LN0->isNonTemporal(),
6632 LN0->getAlignment());
6633 CombineTo(N, ExtLoad);
6634 CombineTo(N0.getNode(),
6635 DAG.getNode(ISD::FP_ROUND, SDLoc(N0),
6636 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
6637 ExtLoad.getValue(1));
6638 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6644 SDValue DAGCombiner::visitFNEG(SDNode *N) {
6645 SDValue N0 = N->getOperand(0);
6646 EVT VT = N->getValueType(0);
6648 if (VT.isVector()) {
6649 SDValue FoldedVOp = SimplifyVUnaryOp(N);
6650 if (FoldedVOp.getNode()) return FoldedVOp;
6653 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(),
6654 &DAG.getTarget().Options))
6655 return GetNegatedExpression(N0, DAG, LegalOperations);
6657 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
6658 // constant pool values.
6659 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST &&
6661 N0.getNode()->hasOneUse() &&
6662 N0.getOperand(0).getValueType().isInteger()) {
6663 SDValue Int = N0.getOperand(0);
6664 EVT IntVT = Int.getValueType();
6665 if (IntVT.isInteger() && !IntVT.isVector()) {
6666 Int = DAG.getNode(ISD::XOR, SDLoc(N0), IntVT, Int,
6667 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
6668 AddToWorkList(Int.getNode());
6669 return DAG.getNode(ISD::BITCAST, SDLoc(N),
6674 // (fneg (fmul c, x)) -> (fmul -c, x)
6675 if (N0.getOpcode() == ISD::FMUL) {
6676 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
6678 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6680 DAG.getNode(ISD::FNEG, SDLoc(N), VT,
6688 SDValue DAGCombiner::visitFCEIL(SDNode *N) {
6689 SDValue N0 = N->getOperand(0);
6690 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6691 EVT VT = N->getValueType(0);
6693 // fold (fceil c1) -> fceil(c1)
6695 return DAG.getNode(ISD::FCEIL, SDLoc(N), VT, N0);
6700 SDValue DAGCombiner::visitFTRUNC(SDNode *N) {
6701 SDValue N0 = N->getOperand(0);
6702 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6703 EVT VT = N->getValueType(0);
6705 // fold (ftrunc c1) -> ftrunc(c1)
6707 return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0);
6712 SDValue DAGCombiner::visitFFLOOR(SDNode *N) {
6713 SDValue N0 = N->getOperand(0);
6714 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6715 EVT VT = N->getValueType(0);
6717 // fold (ffloor c1) -> ffloor(c1)
6719 return DAG.getNode(ISD::FFLOOR, SDLoc(N), VT, N0);
6724 SDValue DAGCombiner::visitFABS(SDNode *N) {
6725 SDValue N0 = N->getOperand(0);
6726 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6727 EVT VT = N->getValueType(0);
6729 if (VT.isVector()) {
6730 SDValue FoldedVOp = SimplifyVUnaryOp(N);
6731 if (FoldedVOp.getNode()) return FoldedVOp;
6734 // fold (fabs c1) -> fabs(c1)
6736 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
6737 // fold (fabs (fabs x)) -> (fabs x)
6738 if (N0.getOpcode() == ISD::FABS)
6739 return N->getOperand(0);
6740 // fold (fabs (fneg x)) -> (fabs x)
6741 // fold (fabs (fcopysign x, y)) -> (fabs x)
6742 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
6743 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0.getOperand(0));
6745 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
6746 // constant pool values.
6747 if (!TLI.isFAbsFree(VT) &&
6748 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
6749 N0.getOperand(0).getValueType().isInteger() &&
6750 !N0.getOperand(0).getValueType().isVector()) {
6751 SDValue Int = N0.getOperand(0);
6752 EVT IntVT = Int.getValueType();
6753 if (IntVT.isInteger() && !IntVT.isVector()) {
6754 Int = DAG.getNode(ISD::AND, SDLoc(N0), IntVT, Int,
6755 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
6756 AddToWorkList(Int.getNode());
6757 return DAG.getNode(ISD::BITCAST, SDLoc(N),
6758 N->getValueType(0), Int);
6765 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
6766 SDValue Chain = N->getOperand(0);
6767 SDValue N1 = N->getOperand(1);
6768 SDValue N2 = N->getOperand(2);
6770 // If N is a constant we could fold this into a fallthrough or unconditional
6771 // branch. However that doesn't happen very often in normal code, because
6772 // Instcombine/SimplifyCFG should have handled the available opportunities.
6773 // If we did this folding here, it would be necessary to update the
6774 // MachineBasicBlock CFG, which is awkward.
6776 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
6778 if (N1.getOpcode() == ISD::SETCC &&
6779 TLI.isOperationLegalOrCustom(ISD::BR_CC,
6780 N1.getOperand(0).getValueType())) {
6781 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
6782 Chain, N1.getOperand(2),
6783 N1.getOperand(0), N1.getOperand(1), N2);
6786 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
6787 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
6788 (N1.getOperand(0).hasOneUse() &&
6789 N1.getOperand(0).getOpcode() == ISD::SRL))) {
6791 if (N1.getOpcode() == ISD::TRUNCATE) {
6792 // Look pass the truncate.
6793 Trunc = N1.getNode();
6794 N1 = N1.getOperand(0);
6797 // Match this pattern so that we can generate simpler code:
6800 // %b = and i32 %a, 2
6801 // %c = srl i32 %b, 1
6802 // brcond i32 %c ...
6807 // %b = and i32 %a, 2
6808 // %c = setcc eq %b, 0
6811 // This applies only when the AND constant value has one bit set and the
6812 // SRL constant is equal to the log2 of the AND constant. The back-end is
6813 // smart enough to convert the result into a TEST/JMP sequence.
6814 SDValue Op0 = N1.getOperand(0);
6815 SDValue Op1 = N1.getOperand(1);
6817 if (Op0.getOpcode() == ISD::AND &&
6818 Op1.getOpcode() == ISD::Constant) {
6819 SDValue AndOp1 = Op0.getOperand(1);
6821 if (AndOp1.getOpcode() == ISD::Constant) {
6822 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
6824 if (AndConst.isPowerOf2() &&
6825 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
6827 DAG.getSetCC(SDLoc(N),
6828 getSetCCResultType(Op0.getValueType()),
6829 Op0, DAG.getConstant(0, Op0.getValueType()),
6832 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, SDLoc(N),
6833 MVT::Other, Chain, SetCC, N2);
6834 // Don't add the new BRCond into the worklist or else SimplifySelectCC
6835 // will convert it back to (X & C1) >> C2.
6836 CombineTo(N, NewBRCond, false);
6837 // Truncate is dead.
6839 removeFromWorkList(Trunc);
6840 DAG.DeleteNode(Trunc);
6842 // Replace the uses of SRL with SETCC
6843 WorkListRemover DeadNodes(*this);
6844 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
6845 removeFromWorkList(N1.getNode());
6846 DAG.DeleteNode(N1.getNode());
6847 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6853 // Restore N1 if the above transformation doesn't match.
6854 N1 = N->getOperand(1);
6857 // Transform br(xor(x, y)) -> br(x != y)
6858 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
6859 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
6860 SDNode *TheXor = N1.getNode();
6861 SDValue Op0 = TheXor->getOperand(0);
6862 SDValue Op1 = TheXor->getOperand(1);
6863 if (Op0.getOpcode() == Op1.getOpcode()) {
6864 // Avoid missing important xor optimizations.
6865 SDValue Tmp = visitXOR(TheXor);
6866 if (Tmp.getNode()) {
6867 if (Tmp.getNode() != TheXor) {
6868 DEBUG(dbgs() << "\nReplacing.8 ";
6870 dbgs() << "\nWith: ";
6871 Tmp.getNode()->dump(&DAG);
6873 WorkListRemover DeadNodes(*this);
6874 DAG.ReplaceAllUsesOfValueWith(N1, Tmp);
6875 removeFromWorkList(TheXor);
6876 DAG.DeleteNode(TheXor);
6877 return DAG.getNode(ISD::BRCOND, SDLoc(N),
6878 MVT::Other, Chain, Tmp, N2);
6881 // visitXOR has changed XOR's operands or replaced the XOR completely,
6883 return SDValue(N, 0);
6887 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
6889 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
6890 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
6891 Op0.getOpcode() == ISD::XOR) {
6892 TheXor = Op0.getNode();
6896 EVT SetCCVT = N1.getValueType();
6898 SetCCVT = getSetCCResultType(SetCCVT);
6899 SDValue SetCC = DAG.getSetCC(SDLoc(TheXor),
6902 Equal ? ISD::SETEQ : ISD::SETNE);
6903 // Replace the uses of XOR with SETCC
6904 WorkListRemover DeadNodes(*this);
6905 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
6906 removeFromWorkList(N1.getNode());
6907 DAG.DeleteNode(N1.getNode());
6908 return DAG.getNode(ISD::BRCOND, SDLoc(N),
6909 MVT::Other, Chain, SetCC, N2);
6916 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
6918 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
6919 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
6920 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
6922 // If N is a constant we could fold this into a fallthrough or unconditional
6923 // branch. However that doesn't happen very often in normal code, because
6924 // Instcombine/SimplifyCFG should have handled the available opportunities.
6925 // If we did this folding here, it would be necessary to update the
6926 // MachineBasicBlock CFG, which is awkward.
6928 // Use SimplifySetCC to simplify SETCC's.
6929 SDValue Simp = SimplifySetCC(getSetCCResultType(CondLHS.getValueType()),
6930 CondLHS, CondRHS, CC->get(), SDLoc(N),
6932 if (Simp.getNode()) AddToWorkList(Simp.getNode());
6934 // fold to a simpler setcc
6935 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
6936 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
6937 N->getOperand(0), Simp.getOperand(2),
6938 Simp.getOperand(0), Simp.getOperand(1),
6944 /// canFoldInAddressingMode - Return true if 'Use' is a load or a store that
6945 /// uses N as its base pointer and that N may be folded in the load / store
6946 /// addressing mode.
6947 static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
6949 const TargetLowering &TLI) {
6951 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) {
6952 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
6954 VT = Use->getValueType(0);
6955 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) {
6956 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
6958 VT = ST->getValue().getValueType();
6962 TargetLowering::AddrMode AM;
6963 if (N->getOpcode() == ISD::ADD) {
6964 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
6967 AM.BaseOffs = Offset->getSExtValue();
6971 } else if (N->getOpcode() == ISD::SUB) {
6972 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
6975 AM.BaseOffs = -Offset->getSExtValue();
6982 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext()));
6985 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
6986 /// pre-indexed load / store when the base pointer is an add or subtract
6987 /// and it has other uses besides the load / store. After the
6988 /// transformation, the new indexed load / store has effectively folded
6989 /// the add / subtract in and all of its other uses are redirected to the
6990 /// new load / store.
6991 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
6992 if (Level < AfterLegalizeDAG)
6998 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6999 if (LD->isIndexed())
7001 VT = LD->getMemoryVT();
7002 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
7003 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
7005 Ptr = LD->getBasePtr();
7006 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7007 if (ST->isIndexed())
7009 VT = ST->getMemoryVT();
7010 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
7011 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
7013 Ptr = ST->getBasePtr();
7019 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
7020 // out. There is no reason to make this a preinc/predec.
7021 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
7022 Ptr.getNode()->hasOneUse())
7025 // Ask the target to do addressing mode selection.
7028 ISD::MemIndexedMode AM = ISD::UNINDEXED;
7029 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
7032 // Backends without true r+i pre-indexed forms may need to pass a
7033 // constant base with a variable offset so that constant coercion
7034 // will work with the patterns in canonical form.
7035 bool Swapped = false;
7036 if (isa<ConstantSDNode>(BasePtr)) {
7037 std::swap(BasePtr, Offset);
7041 // Don't create a indexed load / store with zero offset.
7042 if (isa<ConstantSDNode>(Offset) &&
7043 cast<ConstantSDNode>(Offset)->isNullValue())
7046 // Try turning it into a pre-indexed load / store except when:
7047 // 1) The new base ptr is a frame index.
7048 // 2) If N is a store and the new base ptr is either the same as or is a
7049 // predecessor of the value being stored.
7050 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
7051 // that would create a cycle.
7052 // 4) All uses are load / store ops that use it as old base ptr.
7054 // Check #1. Preinc'ing a frame index would require copying the stack pointer
7055 // (plus the implicit offset) to a register to preinc anyway.
7056 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
7061 SDValue Val = cast<StoreSDNode>(N)->getValue();
7062 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
7066 // If the offset is a constant, there may be other adds of constants that
7067 // can be folded with this one. We should do this to avoid having to keep
7068 // a copy of the original base pointer.
7069 SmallVector<SDNode *, 16> OtherUses;
7070 if (isa<ConstantSDNode>(Offset))
7071 for (SDNode::use_iterator I = BasePtr.getNode()->use_begin(),
7072 E = BasePtr.getNode()->use_end(); I != E; ++I) {
7074 if (Use == Ptr.getNode())
7077 if (Use->isPredecessorOf(N))
7080 if (Use->getOpcode() != ISD::ADD && Use->getOpcode() != ISD::SUB) {
7085 SDValue Op0 = Use->getOperand(0), Op1 = Use->getOperand(1);
7086 if (Op1.getNode() == BasePtr.getNode())
7087 std::swap(Op0, Op1);
7088 assert(Op0.getNode() == BasePtr.getNode() &&
7089 "Use of ADD/SUB but not an operand");
7091 if (!isa<ConstantSDNode>(Op1)) {
7096 // FIXME: In some cases, we can be smarter about this.
7097 if (Op1.getValueType() != Offset.getValueType()) {
7102 OtherUses.push_back(Use);
7106 std::swap(BasePtr, Offset);
7108 // Now check for #3 and #4.
7109 bool RealUse = false;
7111 // Caches for hasPredecessorHelper
7112 SmallPtrSet<const SDNode *, 32> Visited;
7113 SmallVector<const SDNode *, 16> Worklist;
7115 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
7116 E = Ptr.getNode()->use_end(); I != E; ++I) {
7120 if (N->hasPredecessorHelper(Use, Visited, Worklist))
7123 // If Ptr may be folded in addressing mode of other use, then it's
7124 // not profitable to do this transformation.
7125 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI))
7134 Result = DAG.getIndexedLoad(SDValue(N,0), SDLoc(N),
7135 BasePtr, Offset, AM);
7137 Result = DAG.getIndexedStore(SDValue(N,0), SDLoc(N),
7138 BasePtr, Offset, AM);
7141 DEBUG(dbgs() << "\nReplacing.4 ";
7143 dbgs() << "\nWith: ";
7144 Result.getNode()->dump(&DAG);
7146 WorkListRemover DeadNodes(*this);
7148 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
7149 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
7151 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
7154 // Finally, since the node is now dead, remove it from the graph.
7158 std::swap(BasePtr, Offset);
7160 // Replace other uses of BasePtr that can be updated to use Ptr
7161 for (unsigned i = 0, e = OtherUses.size(); i != e; ++i) {
7162 unsigned OffsetIdx = 1;
7163 if (OtherUses[i]->getOperand(OffsetIdx).getNode() == BasePtr.getNode())
7165 assert(OtherUses[i]->getOperand(!OffsetIdx).getNode() ==
7166 BasePtr.getNode() && "Expected BasePtr operand");
7168 // We need to replace ptr0 in the following expression:
7169 // x0 * offset0 + y0 * ptr0 = t0
7171 // x1 * offset1 + y1 * ptr0 = t1 (the indexed load/store)
7173 // where x0, x1, y0 and y1 in {-1, 1} are given by the types of the
7174 // indexed load/store and the expresion that needs to be re-written.
7176 // Therefore, we have:
7177 // t0 = (x0 * offset0 - x1 * y0 * y1 *offset1) + (y0 * y1) * t1
7179 ConstantSDNode *CN =
7180 cast<ConstantSDNode>(OtherUses[i]->getOperand(OffsetIdx));
7182 APInt Offset0 = CN->getAPIntValue();
7183 APInt Offset1 = cast<ConstantSDNode>(Offset)->getAPIntValue();
7185 X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1;
7186 Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1;
7187 X1 = (AM == ISD::PRE_DEC && !Swapped) ? -1 : 1;
7188 Y1 = (AM == ISD::PRE_DEC && Swapped) ? -1 : 1;
7190 unsigned Opcode = (Y0 * Y1 < 0) ? ISD::SUB : ISD::ADD;
7192 APInt CNV = Offset0;
7193 if (X0 < 0) CNV = -CNV;
7194 if (X1 * Y0 * Y1 < 0) CNV = CNV + Offset1;
7195 else CNV = CNV - Offset1;
7197 // We can now generate the new expression.
7198 SDValue NewOp1 = DAG.getConstant(CNV, CN->getValueType(0));
7199 SDValue NewOp2 = Result.getValue(isLoad ? 1 : 0);
7201 SDValue NewUse = DAG.getNode(Opcode,
7202 SDLoc(OtherUses[i]),
7203 OtherUses[i]->getValueType(0), NewOp1, NewOp2);
7204 DAG.ReplaceAllUsesOfValueWith(SDValue(OtherUses[i], 0), NewUse);
7205 removeFromWorkList(OtherUses[i]);
7206 DAG.DeleteNode(OtherUses[i]);
7209 // Replace the uses of Ptr with uses of the updated base value.
7210 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0));
7211 removeFromWorkList(Ptr.getNode());
7212 DAG.DeleteNode(Ptr.getNode());
7217 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
7218 /// add / sub of the base pointer node into a post-indexed load / store.
7219 /// The transformation folded the add / subtract into the new indexed
7220 /// load / store effectively and all of its uses are redirected to the
7221 /// new load / store.
7222 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
7223 if (Level < AfterLegalizeDAG)
7229 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7230 if (LD->isIndexed())
7232 VT = LD->getMemoryVT();
7233 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
7234 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
7236 Ptr = LD->getBasePtr();
7237 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7238 if (ST->isIndexed())
7240 VT = ST->getMemoryVT();
7241 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
7242 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
7244 Ptr = ST->getBasePtr();
7250 if (Ptr.getNode()->hasOneUse())
7253 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
7254 E = Ptr.getNode()->use_end(); I != E; ++I) {
7257 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
7262 ISD::MemIndexedMode AM = ISD::UNINDEXED;
7263 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
7264 // Don't create a indexed load / store with zero offset.
7265 if (isa<ConstantSDNode>(Offset) &&
7266 cast<ConstantSDNode>(Offset)->isNullValue())
7269 // Try turning it into a post-indexed load / store except when
7270 // 1) All uses are load / store ops that use it as base ptr (and
7271 // it may be folded as addressing mmode).
7272 // 2) Op must be independent of N, i.e. Op is neither a predecessor
7273 // nor a successor of N. Otherwise, if Op is folded that would
7276 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
7280 bool TryNext = false;
7281 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
7282 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
7284 if (Use == Ptr.getNode())
7287 // If all the uses are load / store addresses, then don't do the
7289 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
7290 bool RealUse = false;
7291 for (SDNode::use_iterator III = Use->use_begin(),
7292 EEE = Use->use_end(); III != EEE; ++III) {
7293 SDNode *UseUse = *III;
7294 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI))
7309 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
7310 SDValue Result = isLoad
7311 ? DAG.getIndexedLoad(SDValue(N,0), SDLoc(N),
7312 BasePtr, Offset, AM)
7313 : DAG.getIndexedStore(SDValue(N,0), SDLoc(N),
7314 BasePtr, Offset, AM);
7317 DEBUG(dbgs() << "\nReplacing.5 ";
7319 dbgs() << "\nWith: ";
7320 Result.getNode()->dump(&DAG);
7322 WorkListRemover DeadNodes(*this);
7324 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
7325 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
7327 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
7330 // Finally, since the node is now dead, remove it from the graph.
7333 // Replace the uses of Use with uses of the updated base value.
7334 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
7335 Result.getValue(isLoad ? 1 : 0));
7336 removeFromWorkList(Op);
7346 SDValue DAGCombiner::visitLOAD(SDNode *N) {
7347 LoadSDNode *LD = cast<LoadSDNode>(N);
7348 SDValue Chain = LD->getChain();
7349 SDValue Ptr = LD->getBasePtr();
7351 // If load is not volatile and there are no uses of the loaded value (and
7352 // the updated indexed value in case of indexed loads), change uses of the
7353 // chain value into uses of the chain input (i.e. delete the dead load).
7354 if (!LD->isVolatile()) {
7355 if (N->getValueType(1) == MVT::Other) {
7357 if (!N->hasAnyUseOfValue(0)) {
7358 // It's not safe to use the two value CombineTo variant here. e.g.
7359 // v1, chain2 = load chain1, loc
7360 // v2, chain3 = load chain2, loc
7362 // Now we replace use of chain2 with chain1. This makes the second load
7363 // isomorphic to the one we are deleting, and thus makes this load live.
7364 DEBUG(dbgs() << "\nReplacing.6 ";
7366 dbgs() << "\nWith chain: ";
7367 Chain.getNode()->dump(&DAG);
7369 WorkListRemover DeadNodes(*this);
7370 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
7372 if (N->use_empty()) {
7373 removeFromWorkList(N);
7377 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7381 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
7382 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) {
7383 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
7384 DEBUG(dbgs() << "\nReplacing.7 ";
7386 dbgs() << "\nWith: ";
7387 Undef.getNode()->dump(&DAG);
7388 dbgs() << " and 2 other values\n");
7389 WorkListRemover DeadNodes(*this);
7390 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef);
7391 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
7392 DAG.getUNDEF(N->getValueType(1)));
7393 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain);
7394 removeFromWorkList(N);
7396 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7401 // If this load is directly stored, replace the load value with the stored
7403 // TODO: Handle store large -> read small portion.
7404 // TODO: Handle TRUNCSTORE/LOADEXT
7405 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
7406 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
7407 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
7408 if (PrevST->getBasePtr() == Ptr &&
7409 PrevST->getValue().getValueType() == N->getValueType(0))
7410 return CombineTo(N, Chain.getOperand(1), Chain);
7414 // Try to infer better alignment information than the load already has.
7415 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
7416 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
7417 if (Align > LD->getMemOperand()->getBaseAlignment()) {
7419 DAG.getExtLoad(LD->getExtensionType(), SDLoc(N),
7420 LD->getValueType(0),
7421 Chain, Ptr, LD->getPointerInfo(),
7423 LD->isVolatile(), LD->isNonTemporal(), Align);
7424 return CombineTo(N, NewLoad, SDValue(NewLoad.getNode(), 1), true);
7430 // Walk up chain skipping non-aliasing memory nodes.
7431 SDValue BetterChain = FindBetterChain(N, Chain);
7433 // If there is a better chain.
7434 if (Chain != BetterChain) {
7437 // Replace the chain to void dependency.
7438 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
7439 ReplLoad = DAG.getLoad(N->getValueType(0), SDLoc(LD),
7440 BetterChain, Ptr, LD->getPointerInfo(),
7441 LD->isVolatile(), LD->isNonTemporal(),
7442 LD->isInvariant(), LD->getAlignment());
7444 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD),
7445 LD->getValueType(0),
7446 BetterChain, Ptr, LD->getPointerInfo(),
7449 LD->isNonTemporal(),
7450 LD->getAlignment());
7453 // Create token factor to keep old chain connected.
7454 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N),
7455 MVT::Other, Chain, ReplLoad.getValue(1));
7457 // Make sure the new and old chains are cleaned up.
7458 AddToWorkList(Token.getNode());
7460 // Replace uses with load result and token factor. Don't add users
7462 return CombineTo(N, ReplLoad.getValue(0), Token, false);
7466 // Try transforming N to an indexed load.
7467 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
7468 return SDValue(N, 0);
7473 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
7474 /// load is having specific bytes cleared out. If so, return the byte size
7475 /// being masked out and the shift amount.
7476 static std::pair<unsigned, unsigned>
7477 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
7478 std::pair<unsigned, unsigned> Result(0, 0);
7480 // Check for the structure we're looking for.
7481 if (V->getOpcode() != ISD::AND ||
7482 !isa<ConstantSDNode>(V->getOperand(1)) ||
7483 !ISD::isNormalLoad(V->getOperand(0).getNode()))
7486 // Check the chain and pointer.
7487 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
7488 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
7490 // The store should be chained directly to the load or be an operand of a
7492 if (LD == Chain.getNode())
7494 else if (Chain->getOpcode() != ISD::TokenFactor)
7495 return Result; // Fail.
7498 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
7499 if (Chain->getOperand(i).getNode() == LD) {
7503 if (!isOk) return Result;
7506 // This only handles simple types.
7507 if (V.getValueType() != MVT::i16 &&
7508 V.getValueType() != MVT::i32 &&
7509 V.getValueType() != MVT::i64)
7512 // Check the constant mask. Invert it so that the bits being masked out are
7513 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
7514 // follow the sign bit for uniformity.
7515 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
7516 unsigned NotMaskLZ = countLeadingZeros(NotMask);
7517 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
7518 unsigned NotMaskTZ = countTrailingZeros(NotMask);
7519 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
7520 if (NotMaskLZ == 64) return Result; // All zero mask.
7522 // See if we have a continuous run of bits. If so, we have 0*1+0*
7523 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
7526 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
7527 if (V.getValueType() != MVT::i64 && NotMaskLZ)
7528 NotMaskLZ -= 64-V.getValueSizeInBits();
7530 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
7531 switch (MaskedBytes) {
7535 default: return Result; // All one mask, or 5-byte mask.
7538 // Verify that the first bit starts at a multiple of mask so that the access
7539 // is aligned the same as the access width.
7540 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
7542 Result.first = MaskedBytes;
7543 Result.second = NotMaskTZ/8;
7548 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
7549 /// provides a value as specified by MaskInfo. If so, replace the specified
7550 /// store with a narrower store of truncated IVal.
7552 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
7553 SDValue IVal, StoreSDNode *St,
7555 unsigned NumBytes = MaskInfo.first;
7556 unsigned ByteShift = MaskInfo.second;
7557 SelectionDAG &DAG = DC->getDAG();
7559 // Check to see if IVal is all zeros in the part being masked in by the 'or'
7560 // that uses this. If not, this is not a replacement.
7561 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
7562 ByteShift*8, (ByteShift+NumBytes)*8);
7563 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
7565 // Check that it is legal on the target to do this. It is legal if the new
7566 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
7568 MVT VT = MVT::getIntegerVT(NumBytes*8);
7569 if (!DC->isTypeLegal(VT))
7572 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
7573 // shifted by ByteShift and truncated down to NumBytes.
7575 IVal = DAG.getNode(ISD::SRL, SDLoc(IVal), IVal.getValueType(), IVal,
7576 DAG.getConstant(ByteShift*8,
7577 DC->getShiftAmountTy(IVal.getValueType())));
7579 // Figure out the offset for the store and the alignment of the access.
7581 unsigned NewAlign = St->getAlignment();
7583 if (DAG.getTargetLoweringInfo().isLittleEndian())
7584 StOffset = ByteShift;
7586 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
7588 SDValue Ptr = St->getBasePtr();
7590 Ptr = DAG.getNode(ISD::ADD, SDLoc(IVal), Ptr.getValueType(),
7591 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
7592 NewAlign = MinAlign(NewAlign, StOffset);
7595 // Truncate down to the new size.
7596 IVal = DAG.getNode(ISD::TRUNCATE, SDLoc(IVal), VT, IVal);
7599 return DAG.getStore(St->getChain(), SDLoc(St), IVal, Ptr,
7600 St->getPointerInfo().getWithOffset(StOffset),
7601 false, false, NewAlign).getNode();
7605 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
7606 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
7607 /// of the loaded bits, try narrowing the load and store if it would end up
7608 /// being a win for performance or code size.
7609 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
7610 StoreSDNode *ST = cast<StoreSDNode>(N);
7611 if (ST->isVolatile())
7614 SDValue Chain = ST->getChain();
7615 SDValue Value = ST->getValue();
7616 SDValue Ptr = ST->getBasePtr();
7617 EVT VT = Value.getValueType();
7619 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
7622 unsigned Opc = Value.getOpcode();
7624 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
7625 // is a byte mask indicating a consecutive number of bytes, check to see if
7626 // Y is known to provide just those bytes. If so, we try to replace the
7627 // load + replace + store sequence with a single (narrower) store, which makes
7629 if (Opc == ISD::OR) {
7630 std::pair<unsigned, unsigned> MaskedLoad;
7631 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
7632 if (MaskedLoad.first)
7633 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
7634 Value.getOperand(1), ST,this))
7635 return SDValue(NewST, 0);
7637 // Or is commutative, so try swapping X and Y.
7638 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
7639 if (MaskedLoad.first)
7640 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
7641 Value.getOperand(0), ST,this))
7642 return SDValue(NewST, 0);
7645 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
7646 Value.getOperand(1).getOpcode() != ISD::Constant)
7649 SDValue N0 = Value.getOperand(0);
7650 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7651 Chain == SDValue(N0.getNode(), 1)) {
7652 LoadSDNode *LD = cast<LoadSDNode>(N0);
7653 if (LD->getBasePtr() != Ptr ||
7654 LD->getPointerInfo().getAddrSpace() !=
7655 ST->getPointerInfo().getAddrSpace())
7658 // Find the type to narrow it the load / op / store to.
7659 SDValue N1 = Value.getOperand(1);
7660 unsigned BitWidth = N1.getValueSizeInBits();
7661 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
7662 if (Opc == ISD::AND)
7663 Imm ^= APInt::getAllOnesValue(BitWidth);
7664 if (Imm == 0 || Imm.isAllOnesValue())
7666 unsigned ShAmt = Imm.countTrailingZeros();
7667 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
7668 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
7669 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
7670 while (NewBW < BitWidth &&
7671 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
7672 TLI.isNarrowingProfitable(VT, NewVT))) {
7673 NewBW = NextPowerOf2(NewBW);
7674 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
7676 if (NewBW >= BitWidth)
7679 // If the lsb changed does not start at the type bitwidth boundary,
7680 // start at the previous one.
7682 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
7683 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt,
7684 std::min(BitWidth, ShAmt + NewBW));
7685 if ((Imm & Mask) == Imm) {
7686 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
7687 if (Opc == ISD::AND)
7688 NewImm ^= APInt::getAllOnesValue(NewBW);
7689 uint64_t PtrOff = ShAmt / 8;
7690 // For big endian targets, we need to adjust the offset to the pointer to
7691 // load the correct bytes.
7692 if (TLI.isBigEndian())
7693 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
7695 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
7696 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
7697 if (NewAlign < TLI.getDataLayout()->getABITypeAlignment(NewVTTy))
7700 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LD),
7701 Ptr.getValueType(), Ptr,
7702 DAG.getConstant(PtrOff, Ptr.getValueType()));
7703 SDValue NewLD = DAG.getLoad(NewVT, SDLoc(N0),
7704 LD->getChain(), NewPtr,
7705 LD->getPointerInfo().getWithOffset(PtrOff),
7706 LD->isVolatile(), LD->isNonTemporal(),
7707 LD->isInvariant(), NewAlign);
7708 SDValue NewVal = DAG.getNode(Opc, SDLoc(Value), NewVT, NewLD,
7709 DAG.getConstant(NewImm, NewVT));
7710 SDValue NewST = DAG.getStore(Chain, SDLoc(N),
7712 ST->getPointerInfo().getWithOffset(PtrOff),
7713 false, false, NewAlign);
7715 AddToWorkList(NewPtr.getNode());
7716 AddToWorkList(NewLD.getNode());
7717 AddToWorkList(NewVal.getNode());
7718 WorkListRemover DeadNodes(*this);
7719 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1));
7728 /// TransformFPLoadStorePair - For a given floating point load / store pair,
7729 /// if the load value isn't used by any other operations, then consider
7730 /// transforming the pair to integer load / store operations if the target
7731 /// deems the transformation profitable.
7732 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
7733 StoreSDNode *ST = cast<StoreSDNode>(N);
7734 SDValue Chain = ST->getChain();
7735 SDValue Value = ST->getValue();
7736 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
7737 Value.hasOneUse() &&
7738 Chain == SDValue(Value.getNode(), 1)) {
7739 LoadSDNode *LD = cast<LoadSDNode>(Value);
7740 EVT VT = LD->getMemoryVT();
7741 if (!VT.isFloatingPoint() ||
7742 VT != ST->getMemoryVT() ||
7743 LD->isNonTemporal() ||
7744 ST->isNonTemporal() ||
7745 LD->getPointerInfo().getAddrSpace() != 0 ||
7746 ST->getPointerInfo().getAddrSpace() != 0)
7749 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
7750 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
7751 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
7752 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
7753 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
7756 unsigned LDAlign = LD->getAlignment();
7757 unsigned STAlign = ST->getAlignment();
7758 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
7759 unsigned ABIAlign = TLI.getDataLayout()->getABITypeAlignment(IntVTTy);
7760 if (LDAlign < ABIAlign || STAlign < ABIAlign)
7763 SDValue NewLD = DAG.getLoad(IntVT, SDLoc(Value),
7764 LD->getChain(), LD->getBasePtr(),
7765 LD->getPointerInfo(),
7766 false, false, false, LDAlign);
7768 SDValue NewST = DAG.getStore(NewLD.getValue(1), SDLoc(N),
7769 NewLD, ST->getBasePtr(),
7770 ST->getPointerInfo(),
7771 false, false, STAlign);
7773 AddToWorkList(NewLD.getNode());
7774 AddToWorkList(NewST.getNode());
7775 WorkListRemover DeadNodes(*this);
7776 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1));
7784 /// Helper struct to parse and store a memory address as base + index + offset.
7785 /// We ignore sign extensions when it is safe to do so.
7786 /// The following two expressions are not equivalent. To differentiate we need
7787 /// to store whether there was a sign extension involved in the index
7789 /// (load (i64 add (i64 copyfromreg %c)
7790 /// (i64 signextend (add (i8 load %index)
7794 /// (load (i64 add (i64 copyfromreg %c)
7795 /// (i64 signextend (i32 add (i32 signextend (i8 load %index))
7797 struct BaseIndexOffset {
7801 bool IsIndexSignExt;
7803 BaseIndexOffset() : Offset(0), IsIndexSignExt(false) {}
7805 BaseIndexOffset(SDValue Base, SDValue Index, int64_t Offset,
7806 bool IsIndexSignExt) :
7807 Base(Base), Index(Index), Offset(Offset), IsIndexSignExt(IsIndexSignExt) {}
7809 bool equalBaseIndex(const BaseIndexOffset &Other) {
7810 return Other.Base == Base && Other.Index == Index &&
7811 Other.IsIndexSignExt == IsIndexSignExt;
7814 /// Parses tree in Ptr for base, index, offset addresses.
7815 static BaseIndexOffset match(SDValue Ptr) {
7816 bool IsIndexSignExt = false;
7818 // Just Base or possibly anything else.
7819 if (Ptr->getOpcode() != ISD::ADD)
7820 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
7823 if (isa<ConstantSDNode>(Ptr->getOperand(1))) {
7824 int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue();
7825 return BaseIndexOffset(Ptr->getOperand(0), SDValue(), Offset,
7829 // Look at Base + Index + Offset cases.
7830 SDValue Base = Ptr->getOperand(0);
7831 SDValue IndexOffset = Ptr->getOperand(1);
7833 // Skip signextends.
7834 if (IndexOffset->getOpcode() == ISD::SIGN_EXTEND) {
7835 IndexOffset = IndexOffset->getOperand(0);
7836 IsIndexSignExt = true;
7839 // Either the case of Base + Index (no offset) or something else.
7840 if (IndexOffset->getOpcode() != ISD::ADD)
7841 return BaseIndexOffset(Base, IndexOffset, 0, IsIndexSignExt);
7843 // Now we have the case of Base + Index + offset.
7844 SDValue Index = IndexOffset->getOperand(0);
7845 SDValue Offset = IndexOffset->getOperand(1);
7847 if (!isa<ConstantSDNode>(Offset))
7848 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
7850 // Ignore signextends.
7851 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
7852 Index = Index->getOperand(0);
7853 IsIndexSignExt = true;
7854 } else IsIndexSignExt = false;
7856 int64_t Off = cast<ConstantSDNode>(Offset)->getSExtValue();
7857 return BaseIndexOffset(Base, Index, Off, IsIndexSignExt);
7861 /// Holds a pointer to an LSBaseSDNode as well as information on where it
7862 /// is located in a sequence of memory operations connected by a chain.
7864 MemOpLink (LSBaseSDNode *N, int64_t Offset, unsigned Seq):
7865 MemNode(N), OffsetFromBase(Offset), SequenceNum(Seq) { }
7866 // Ptr to the mem node.
7867 LSBaseSDNode *MemNode;
7868 // Offset from the base ptr.
7869 int64_t OffsetFromBase;
7870 // What is the sequence number of this mem node.
7871 // Lowest mem operand in the DAG starts at zero.
7872 unsigned SequenceNum;
7875 /// Sorts store nodes in a link according to their offset from a shared
7877 struct ConsecutiveMemoryChainSorter {
7878 bool operator()(MemOpLink LHS, MemOpLink RHS) {
7879 return LHS.OffsetFromBase < RHS.OffsetFromBase;
7883 bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
7884 EVT MemVT = St->getMemoryVT();
7885 int64_t ElementSizeBytes = MemVT.getSizeInBits()/8;
7886 bool NoVectors = DAG.getMachineFunction().getFunction()->getAttributes().
7887 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
7889 // Don't merge vectors into wider inputs.
7890 if (MemVT.isVector() || !MemVT.isSimple())
7893 // Perform an early exit check. Do not bother looking at stored values that
7894 // are not constants or loads.
7895 SDValue StoredVal = St->getValue();
7896 bool IsLoadSrc = isa<LoadSDNode>(StoredVal);
7897 if (!isa<ConstantSDNode>(StoredVal) && !isa<ConstantFPSDNode>(StoredVal) &&
7901 // Only look at ends of store sequences.
7902 SDValue Chain = SDValue(St, 1);
7903 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE)
7906 // This holds the base pointer, index, and the offset in bytes from the base
7908 BaseIndexOffset BasePtr = BaseIndexOffset::match(St->getBasePtr());
7910 // We must have a base and an offset.
7911 if (!BasePtr.Base.getNode())
7914 // Do not handle stores to undef base pointers.
7915 if (BasePtr.Base.getOpcode() == ISD::UNDEF)
7918 // Save the LoadSDNodes that we find in the chain.
7919 // We need to make sure that these nodes do not interfere with
7920 // any of the store nodes.
7921 SmallVector<LSBaseSDNode*, 8> AliasLoadNodes;
7923 // Save the StoreSDNodes that we find in the chain.
7924 SmallVector<MemOpLink, 8> StoreNodes;
7926 // Walk up the chain and look for nodes with offsets from the same
7927 // base pointer. Stop when reaching an instruction with a different kind
7928 // or instruction which has a different base pointer.
7930 StoreSDNode *Index = St;
7932 // If the chain has more than one use, then we can't reorder the mem ops.
7933 if (Index != St && !SDValue(Index, 1)->hasOneUse())
7936 // Find the base pointer and offset for this memory node.
7937 BaseIndexOffset Ptr = BaseIndexOffset::match(Index->getBasePtr());
7939 // Check that the base pointer is the same as the original one.
7940 if (!Ptr.equalBaseIndex(BasePtr))
7943 // Check that the alignment is the same.
7944 if (Index->getAlignment() != St->getAlignment())
7947 // The memory operands must not be volatile.
7948 if (Index->isVolatile() || Index->isIndexed())
7952 if (StoreSDNode *St = dyn_cast<StoreSDNode>(Index))
7953 if (St->isTruncatingStore())
7956 // The stored memory type must be the same.
7957 if (Index->getMemoryVT() != MemVT)
7960 // We do not allow unaligned stores because we want to prevent overriding
7962 if (Index->getAlignment()*8 != MemVT.getSizeInBits())
7965 // We found a potential memory operand to merge.
7966 StoreNodes.push_back(MemOpLink(Index, Ptr.Offset, Seq++));
7968 // Find the next memory operand in the chain. If the next operand in the
7969 // chain is a store then move up and continue the scan with the next
7970 // memory operand. If the next operand is a load save it and use alias
7971 // information to check if it interferes with anything.
7972 SDNode *NextInChain = Index->getChain().getNode();
7974 if (StoreSDNode *STn = dyn_cast<StoreSDNode>(NextInChain)) {
7975 // We found a store node. Use it for the next iteration.
7978 } else if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(NextInChain)) {
7979 // Save the load node for later. Continue the scan.
7980 AliasLoadNodes.push_back(Ldn);
7981 NextInChain = Ldn->getChain().getNode();
7990 // Check if there is anything to merge.
7991 if (StoreNodes.size() < 2)
7994 // Sort the memory operands according to their distance from the base pointer.
7995 std::sort(StoreNodes.begin(), StoreNodes.end(),
7996 ConsecutiveMemoryChainSorter());
7998 // Scan the memory operations on the chain and find the first non-consecutive
7999 // store memory address.
8000 unsigned LastConsecutiveStore = 0;
8001 int64_t StartAddress = StoreNodes[0].OffsetFromBase;
8002 for (unsigned i = 0, e = StoreNodes.size(); i < e; ++i) {
8004 // Check that the addresses are consecutive starting from the second
8005 // element in the list of stores.
8007 int64_t CurrAddress = StoreNodes[i].OffsetFromBase;
8008 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
8013 // Check if this store interferes with any of the loads that we found.
8014 for (unsigned ld = 0, lde = AliasLoadNodes.size(); ld < lde; ++ld)
8015 if (isAlias(AliasLoadNodes[ld], StoreNodes[i].MemNode)) {
8019 // We found a load that alias with this store. Stop the sequence.
8023 // Mark this node as useful.
8024 LastConsecutiveStore = i;
8027 // The node with the lowest store address.
8028 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;
8030 // Store the constants into memory as one consecutive store.
8032 unsigned LastLegalType = 0;
8033 unsigned LastLegalVectorType = 0;
8034 bool NonZero = false;
8035 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
8036 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
8037 SDValue StoredVal = St->getValue();
8039 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(StoredVal)) {
8040 NonZero |= !C->isNullValue();
8041 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) {
8042 NonZero |= !C->getConstantFPValue()->isNullValue();
8048 // Find a legal type for the constant store.
8049 unsigned StoreBW = (i+1) * ElementSizeBytes * 8;
8050 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
8051 if (TLI.isTypeLegal(StoreTy))
8052 LastLegalType = i+1;
8053 // Or check whether a truncstore is legal.
8054 else if (TLI.getTypeAction(*DAG.getContext(), StoreTy) ==
8055 TargetLowering::TypePromoteInteger) {
8056 EVT LegalizedStoredValueTy =
8057 TLI.getTypeToTransformTo(*DAG.getContext(), StoredVal.getValueType());
8058 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy))
8059 LastLegalType = i+1;
8062 // Find a legal type for the vector store.
8063 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
8064 if (TLI.isTypeLegal(Ty))
8065 LastLegalVectorType = i + 1;
8068 // We only use vectors if the constant is known to be zero and the
8069 // function is not marked with the noimplicitfloat attribute.
8070 if (NonZero || NoVectors)
8071 LastLegalVectorType = 0;
8073 // Check if we found a legal integer type to store.
8074 if (LastLegalType == 0 && LastLegalVectorType == 0)
8077 bool UseVector = (LastLegalVectorType > LastLegalType) && !NoVectors;
8078 unsigned NumElem = UseVector ? LastLegalVectorType : LastLegalType;
8080 // Make sure we have something to merge.
8084 unsigned EarliestNodeUsed = 0;
8085 for (unsigned i=0; i < NumElem; ++i) {
8086 // Find a chain for the new wide-store operand. Notice that some
8087 // of the store nodes that we found may not be selected for inclusion
8088 // in the wide store. The chain we use needs to be the chain of the
8089 // earliest store node which is *used* and replaced by the wide store.
8090 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum)
8091 EarliestNodeUsed = i;
8094 // The earliest Node in the DAG.
8095 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode;
8096 SDLoc DL(StoreNodes[0].MemNode);
8100 // Find a legal type for the vector store.
8101 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
8102 assert(TLI.isTypeLegal(Ty) && "Illegal vector store");
8103 StoredVal = DAG.getConstant(0, Ty);
8105 unsigned StoreBW = NumElem * ElementSizeBytes * 8;
8106 APInt StoreInt(StoreBW, 0);
8108 // Construct a single integer constant which is made of the smaller
8110 bool IsLE = TLI.isLittleEndian();
8111 for (unsigned i = 0; i < NumElem ; ++i) {
8112 unsigned Idx = IsLE ?(NumElem - 1 - i) : i;
8113 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[Idx].MemNode);
8114 SDValue Val = St->getValue();
8115 StoreInt<<=ElementSizeBytes*8;
8116 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val)) {
8117 StoreInt|=C->getAPIntValue().zext(StoreBW);
8118 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) {
8119 StoreInt|= C->getValueAPF().bitcastToAPInt().zext(StoreBW);
8121 assert(false && "Invalid constant element type");
8125 // Create the new Load and Store operations.
8126 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
8127 StoredVal = DAG.getConstant(StoreInt, StoreTy);
8130 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), DL, StoredVal,
8131 FirstInChain->getBasePtr(),
8132 FirstInChain->getPointerInfo(),
8134 FirstInChain->getAlignment());
8136 // Replace the first store with the new store
8137 CombineTo(EarliestOp, NewStore);
8138 // Erase all other stores.
8139 for (unsigned i = 0; i < NumElem ; ++i) {
8140 if (StoreNodes[i].MemNode == EarliestOp)
8142 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
8143 // ReplaceAllUsesWith will replace all uses that existed when it was
8144 // called, but graph optimizations may cause new ones to appear. For
8145 // example, the case in pr14333 looks like
8147 // St's chain -> St -> another store -> X
8149 // And the only difference from St to the other store is the chain.
8150 // When we change it's chain to be St's chain they become identical,
8151 // get CSEed and the net result is that X is now a use of St.
8152 // Since we know that St is redundant, just iterate.
8153 while (!St->use_empty())
8154 DAG.ReplaceAllUsesWith(SDValue(St, 0), St->getChain());
8155 removeFromWorkList(St);
8162 // Below we handle the case of multiple consecutive stores that
8163 // come from multiple consecutive loads. We merge them into a single
8164 // wide load and a single wide store.
8166 // Look for load nodes which are used by the stored values.
8167 SmallVector<MemOpLink, 8> LoadNodes;
8169 // Find acceptable loads. Loads need to have the same chain (token factor),
8170 // must not be zext, volatile, indexed, and they must be consecutive.
8171 BaseIndexOffset LdBasePtr;
8172 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
8173 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
8174 LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue());
8177 // Loads must only have one use.
8178 if (!Ld->hasNUsesOfValue(1, 0))
8181 // Check that the alignment is the same as the stores.
8182 if (Ld->getAlignment() != St->getAlignment())
8185 // The memory operands must not be volatile.
8186 if (Ld->isVolatile() || Ld->isIndexed())
8189 // We do not accept ext loads.
8190 if (Ld->getExtensionType() != ISD::NON_EXTLOAD)
8193 // The stored memory type must be the same.
8194 if (Ld->getMemoryVT() != MemVT)
8197 BaseIndexOffset LdPtr = BaseIndexOffset::match(Ld->getBasePtr());
8198 // If this is not the first ptr that we check.
8199 if (LdBasePtr.Base.getNode()) {
8200 // The base ptr must be the same.
8201 if (!LdPtr.equalBaseIndex(LdBasePtr))
8204 // Check that all other base pointers are the same as this one.
8208 // We found a potential memory operand to merge.
8209 LoadNodes.push_back(MemOpLink(Ld, LdPtr.Offset, 0));
8212 if (LoadNodes.size() < 2)
8215 // Scan the memory operations on the chain and find the first non-consecutive
8216 // load memory address. These variables hold the index in the store node
8218 unsigned LastConsecutiveLoad = 0;
8219 // This variable refers to the size and not index in the array.
8220 unsigned LastLegalVectorType = 0;
8221 unsigned LastLegalIntegerType = 0;
8222 StartAddress = LoadNodes[0].OffsetFromBase;
8223 SDValue FirstChain = LoadNodes[0].MemNode->getChain();
8224 for (unsigned i = 1; i < LoadNodes.size(); ++i) {
8225 // All loads much share the same chain.
8226 if (LoadNodes[i].MemNode->getChain() != FirstChain)
8229 int64_t CurrAddress = LoadNodes[i].OffsetFromBase;
8230 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
8232 LastConsecutiveLoad = i;
8234 // Find a legal type for the vector store.
8235 EVT StoreTy = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
8236 if (TLI.isTypeLegal(StoreTy))
8237 LastLegalVectorType = i + 1;
8239 // Find a legal type for the integer store.
8240 unsigned StoreBW = (i+1) * ElementSizeBytes * 8;
8241 StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
8242 if (TLI.isTypeLegal(StoreTy))
8243 LastLegalIntegerType = i + 1;
8244 // Or check whether a truncstore and extload is legal.
8245 else if (TLI.getTypeAction(*DAG.getContext(), StoreTy) ==
8246 TargetLowering::TypePromoteInteger) {
8247 EVT LegalizedStoredValueTy =
8248 TLI.getTypeToTransformTo(*DAG.getContext(), StoreTy);
8249 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy) &&
8250 TLI.isLoadExtLegal(ISD::ZEXTLOAD, StoreTy) &&
8251 TLI.isLoadExtLegal(ISD::SEXTLOAD, StoreTy) &&
8252 TLI.isLoadExtLegal(ISD::EXTLOAD, StoreTy))
8253 LastLegalIntegerType = i+1;
8257 // Only use vector types if the vector type is larger than the integer type.
8258 // If they are the same, use integers.
8259 bool UseVectorTy = LastLegalVectorType > LastLegalIntegerType && !NoVectors;
8260 unsigned LastLegalType = std::max(LastLegalVectorType, LastLegalIntegerType);
8262 // We add +1 here because the LastXXX variables refer to location while
8263 // the NumElem refers to array/index size.
8264 unsigned NumElem = std::min(LastConsecutiveStore, LastConsecutiveLoad) + 1;
8265 NumElem = std::min(LastLegalType, NumElem);
8270 // The earliest Node in the DAG.
8271 unsigned EarliestNodeUsed = 0;
8272 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode;
8273 for (unsigned i=1; i<NumElem; ++i) {
8274 // Find a chain for the new wide-store operand. Notice that some
8275 // of the store nodes that we found may not be selected for inclusion
8276 // in the wide store. The chain we use needs to be the chain of the
8277 // earliest store node which is *used* and replaced by the wide store.
8278 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum)
8279 EarliestNodeUsed = i;
8282 // Find if it is better to use vectors or integers to load and store
8286 JointMemOpVT = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
8288 unsigned StoreBW = NumElem * ElementSizeBytes * 8;
8289 JointMemOpVT = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
8292 SDLoc LoadDL(LoadNodes[0].MemNode);
8293 SDLoc StoreDL(StoreNodes[0].MemNode);
8295 LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode);
8296 SDValue NewLoad = DAG.getLoad(JointMemOpVT, LoadDL,
8297 FirstLoad->getChain(),
8298 FirstLoad->getBasePtr(),
8299 FirstLoad->getPointerInfo(),
8300 false, false, false,
8301 FirstLoad->getAlignment());
8303 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), StoreDL, NewLoad,
8304 FirstInChain->getBasePtr(),
8305 FirstInChain->getPointerInfo(), false, false,
8306 FirstInChain->getAlignment());
8308 // Replace one of the loads with the new load.
8309 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[0].MemNode);
8310 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1),
8311 SDValue(NewLoad.getNode(), 1));
8313 // Remove the rest of the load chains.
8314 for (unsigned i = 1; i < NumElem ; ++i) {
8315 // Replace all chain users of the old load nodes with the chain of the new
8317 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[i].MemNode);
8318 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Ld->getChain());
8321 // Replace the first store with the new store.
8322 CombineTo(EarliestOp, NewStore);
8323 // Erase all other stores.
8324 for (unsigned i = 0; i < NumElem ; ++i) {
8325 // Remove all Store nodes.
8326 if (StoreNodes[i].MemNode == EarliestOp)
8328 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
8329 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain());
8330 removeFromWorkList(St);
8337 SDValue DAGCombiner::visitSTORE(SDNode *N) {
8338 StoreSDNode *ST = cast<StoreSDNode>(N);
8339 SDValue Chain = ST->getChain();
8340 SDValue Value = ST->getValue();
8341 SDValue Ptr = ST->getBasePtr();
8343 // If this is a store of a bit convert, store the input value if the
8344 // resultant store does not need a higher alignment than the original.
8345 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
8346 ST->isUnindexed()) {
8347 unsigned OrigAlign = ST->getAlignment();
8348 EVT SVT = Value.getOperand(0).getValueType();
8349 unsigned Align = TLI.getDataLayout()->
8350 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
8351 if (Align <= OrigAlign &&
8352 ((!LegalOperations && !ST->isVolatile()) ||
8353 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
8354 return DAG.getStore(Chain, SDLoc(N), Value.getOperand(0),
8355 Ptr, ST->getPointerInfo(), ST->isVolatile(),
8356 ST->isNonTemporal(), OrigAlign);
8359 // Turn 'store undef, Ptr' -> nothing.
8360 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
8363 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
8364 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
8365 // NOTE: If the original store is volatile, this transform must not increase
8366 // the number of stores. For example, on x86-32 an f64 can be stored in one
8367 // processor operation but an i64 (which is not legal) requires two. So the
8368 // transform should not be done in this case.
8369 if (Value.getOpcode() != ISD::TargetConstantFP) {
8371 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
8372 default: llvm_unreachable("Unknown FP type");
8373 case MVT::f16: // We don't do this for these yet.
8379 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
8380 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
8381 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
8382 bitcastToAPInt().getZExtValue(), MVT::i32);
8383 return DAG.getStore(Chain, SDLoc(N), Tmp,
8384 Ptr, ST->getPointerInfo(), ST->isVolatile(),
8385 ST->isNonTemporal(), ST->getAlignment());
8389 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
8390 !ST->isVolatile()) ||
8391 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
8392 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
8393 getZExtValue(), MVT::i64);
8394 return DAG.getStore(Chain, SDLoc(N), Tmp,
8395 Ptr, ST->getPointerInfo(), ST->isVolatile(),
8396 ST->isNonTemporal(), ST->getAlignment());
8399 if (!ST->isVolatile() &&
8400 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
8401 // Many FP stores are not made apparent until after legalize, e.g. for
8402 // argument passing. Since this is so common, custom legalize the
8403 // 64-bit integer store into two 32-bit stores.
8404 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
8405 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
8406 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
8407 if (TLI.isBigEndian()) std::swap(Lo, Hi);
8409 unsigned Alignment = ST->getAlignment();
8410 bool isVolatile = ST->isVolatile();
8411 bool isNonTemporal = ST->isNonTemporal();
8413 SDValue St0 = DAG.getStore(Chain, SDLoc(ST), Lo,
8414 Ptr, ST->getPointerInfo(),
8415 isVolatile, isNonTemporal,
8416 ST->getAlignment());
8417 Ptr = DAG.getNode(ISD::ADD, SDLoc(N), Ptr.getValueType(), Ptr,
8418 DAG.getConstant(4, Ptr.getValueType()));
8419 Alignment = MinAlign(Alignment, 4U);
8420 SDValue St1 = DAG.getStore(Chain, SDLoc(ST), Hi,
8421 Ptr, ST->getPointerInfo().getWithOffset(4),
8422 isVolatile, isNonTemporal,
8424 return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other,
8433 // Try to infer better alignment information than the store already has.
8434 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
8435 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
8436 if (Align > ST->getAlignment())
8437 return DAG.getTruncStore(Chain, SDLoc(N), Value,
8438 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
8439 ST->isVolatile(), ST->isNonTemporal(), Align);
8443 // Try transforming a pair floating point load / store ops to integer
8444 // load / store ops.
8445 SDValue NewST = TransformFPLoadStorePair(N);
8446 if (NewST.getNode())
8450 // Walk up chain skipping non-aliasing memory nodes.
8451 SDValue BetterChain = FindBetterChain(N, Chain);
8453 // If there is a better chain.
8454 if (Chain != BetterChain) {
8457 // Replace the chain to avoid dependency.
8458 if (ST->isTruncatingStore()) {
8459 ReplStore = DAG.getTruncStore(BetterChain, SDLoc(N), Value, Ptr,
8460 ST->getPointerInfo(),
8461 ST->getMemoryVT(), ST->isVolatile(),
8462 ST->isNonTemporal(), ST->getAlignment());
8464 ReplStore = DAG.getStore(BetterChain, SDLoc(N), Value, Ptr,
8465 ST->getPointerInfo(),
8466 ST->isVolatile(), ST->isNonTemporal(),
8467 ST->getAlignment());
8470 // Create token to keep both nodes around.
8471 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N),
8472 MVT::Other, Chain, ReplStore);
8474 // Make sure the new and old chains are cleaned up.
8475 AddToWorkList(Token.getNode());
8477 // Don't add users to work list.
8478 return CombineTo(N, Token, false);
8482 // Try transforming N to an indexed store.
8483 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
8484 return SDValue(N, 0);
8486 // FIXME: is there such a thing as a truncating indexed store?
8487 if (ST->isTruncatingStore() && ST->isUnindexed() &&
8488 Value.getValueType().isInteger()) {
8489 // See if we can simplify the input to this truncstore with knowledge that
8490 // only the low bits are being used. For example:
8491 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
8493 GetDemandedBits(Value,
8494 APInt::getLowBitsSet(
8495 Value.getValueType().getScalarType().getSizeInBits(),
8496 ST->getMemoryVT().getScalarType().getSizeInBits()));
8497 AddToWorkList(Value.getNode());
8498 if (Shorter.getNode())
8499 return DAG.getTruncStore(Chain, SDLoc(N), Shorter,
8500 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
8501 ST->isVolatile(), ST->isNonTemporal(),
8502 ST->getAlignment());
8504 // Otherwise, see if we can simplify the operation with
8505 // SimplifyDemandedBits, which only works if the value has a single use.
8506 if (SimplifyDemandedBits(Value,
8507 APInt::getLowBitsSet(
8508 Value.getValueType().getScalarType().getSizeInBits(),
8509 ST->getMemoryVT().getScalarType().getSizeInBits())))
8510 return SDValue(N, 0);
8513 // If this is a load followed by a store to the same location, then the store
8515 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
8516 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
8517 ST->isUnindexed() && !ST->isVolatile() &&
8518 // There can't be any side effects between the load and store, such as
8520 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
8521 // The store is dead, remove it.
8526 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
8527 // truncating store. We can do this even if this is already a truncstore.
8528 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
8529 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
8530 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
8531 ST->getMemoryVT())) {
8532 return DAG.getTruncStore(Chain, SDLoc(N), Value.getOperand(0),
8533 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
8534 ST->isVolatile(), ST->isNonTemporal(),
8535 ST->getAlignment());
8538 // Only perform this optimization before the types are legal, because we
8539 // don't want to perform this optimization on every DAGCombine invocation.
8541 bool EverChanged = false;
8544 // There can be multiple store sequences on the same chain.
8545 // Keep trying to merge store sequences until we are unable to do so
8546 // or until we merge the last store on the chain.
8547 bool Changed = MergeConsecutiveStores(ST);
8548 EverChanged |= Changed;
8549 if (!Changed) break;
8550 } while (ST->getOpcode() != ISD::DELETED_NODE);
8553 return SDValue(N, 0);
8556 return ReduceLoadOpStoreWidth(N);
8559 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
8560 SDValue InVec = N->getOperand(0);
8561 SDValue InVal = N->getOperand(1);
8562 SDValue EltNo = N->getOperand(2);
8565 // If the inserted element is an UNDEF, just use the input vector.
8566 if (InVal.getOpcode() == ISD::UNDEF)
8569 EVT VT = InVec.getValueType();
8571 // If we can't generate a legal BUILD_VECTOR, exit
8572 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
8575 // Check that we know which element is being inserted
8576 if (!isa<ConstantSDNode>(EltNo))
8578 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
8580 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
8581 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
8583 SmallVector<SDValue, 8> Ops;
8584 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
8585 Ops.append(InVec.getNode()->op_begin(),
8586 InVec.getNode()->op_end());
8587 } else if (InVec.getOpcode() == ISD::UNDEF) {
8588 unsigned NElts = VT.getVectorNumElements();
8589 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
8594 // Insert the element
8595 if (Elt < Ops.size()) {
8596 // All the operands of BUILD_VECTOR must have the same type;
8597 // we enforce that here.
8598 EVT OpVT = Ops[0].getValueType();
8599 if (InVal.getValueType() != OpVT)
8600 InVal = OpVT.bitsGT(InVal.getValueType()) ?
8601 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
8602 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
8606 // Return the new vector
8607 return DAG.getNode(ISD::BUILD_VECTOR, dl,
8608 VT, &Ops[0], Ops.size());
8611 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
8612 // (vextract (scalar_to_vector val, 0) -> val
8613 SDValue InVec = N->getOperand(0);
8614 EVT VT = InVec.getValueType();
8615 EVT NVT = N->getValueType(0);
8617 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
8618 // Check if the result type doesn't match the inserted element type. A
8619 // SCALAR_TO_VECTOR may truncate the inserted element and the
8620 // EXTRACT_VECTOR_ELT may widen the extracted vector.
8621 SDValue InOp = InVec.getOperand(0);
8622 if (InOp.getValueType() != NVT) {
8623 assert(InOp.getValueType().isInteger() && NVT.isInteger());
8624 return DAG.getSExtOrTrunc(InOp, SDLoc(InVec), NVT);
8629 SDValue EltNo = N->getOperand(1);
8630 bool ConstEltNo = isa<ConstantSDNode>(EltNo);
8632 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
8633 // We only perform this optimization before the op legalization phase because
8634 // we may introduce new vector instructions which are not backed by TD
8635 // patterns. For example on AVX, extracting elements from a wide vector
8636 // without using extract_subvector.
8637 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
8638 && ConstEltNo && !LegalOperations) {
8639 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
8640 int NumElem = VT.getVectorNumElements();
8641 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
8642 // Find the new index to extract from.
8643 int OrigElt = SVOp->getMaskElt(Elt);
8645 // Extracting an undef index is undef.
8647 return DAG.getUNDEF(NVT);
8649 // Select the right vector half to extract from.
8650 if (OrigElt < NumElem) {
8651 InVec = InVec->getOperand(0);
8653 InVec = InVec->getOperand(1);
8657 EVT IndexTy = N->getOperand(1).getValueType();
8658 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), NVT,
8659 InVec, DAG.getConstant(OrigElt, IndexTy));
8662 // Perform only after legalization to ensure build_vector / vector_shuffle
8663 // optimizations have already been done.
8664 if (!LegalOperations) return SDValue();
8666 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
8667 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
8668 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
8671 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
8672 bool NewLoad = false;
8673 bool BCNumEltsChanged = false;
8674 EVT ExtVT = VT.getVectorElementType();
8677 // If the result of load has to be truncated, then it's not necessarily
8679 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT))
8682 if (InVec.getOpcode() == ISD::BITCAST) {
8683 // Don't duplicate a load with other uses.
8684 if (!InVec.hasOneUse())
8687 EVT BCVT = InVec.getOperand(0).getValueType();
8688 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
8690 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
8691 BCNumEltsChanged = true;
8692 InVec = InVec.getOperand(0);
8693 ExtVT = BCVT.getVectorElementType();
8697 LoadSDNode *LN0 = NULL;
8698 const ShuffleVectorSDNode *SVN = NULL;
8699 if (ISD::isNormalLoad(InVec.getNode())) {
8700 LN0 = cast<LoadSDNode>(InVec);
8701 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
8702 InVec.getOperand(0).getValueType() == ExtVT &&
8703 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
8704 // Don't duplicate a load with other uses.
8705 if (!InVec.hasOneUse())
8708 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
8709 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
8710 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
8712 // (load $addr+1*size)
8714 // Don't duplicate a load with other uses.
8715 if (!InVec.hasOneUse())
8718 // If the bit convert changed the number of elements, it is unsafe
8719 // to examine the mask.
8720 if (BCNumEltsChanged)
8723 // Select the input vector, guarding against out of range extract vector.
8724 unsigned NumElems = VT.getVectorNumElements();
8725 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
8726 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
8728 if (InVec.getOpcode() == ISD::BITCAST) {
8729 // Don't duplicate a load with other uses.
8730 if (!InVec.hasOneUse())
8733 InVec = InVec.getOperand(0);
8735 if (ISD::isNormalLoad(InVec.getNode())) {
8736 LN0 = cast<LoadSDNode>(InVec);
8737 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
8741 // Make sure we found a non-volatile load and the extractelement is
8743 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
8746 // If Idx was -1 above, Elt is going to be -1, so just return undef.
8748 return DAG.getUNDEF(LVT);
8750 unsigned Align = LN0->getAlignment();
8752 // Check the resultant load doesn't need a higher alignment than the
8756 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
8758 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
8764 SDValue NewPtr = LN0->getBasePtr();
8765 unsigned PtrOff = 0;
8768 PtrOff = LVT.getSizeInBits() * Elt / 8;
8769 EVT PtrType = NewPtr.getValueType();
8770 if (TLI.isBigEndian())
8771 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
8772 NewPtr = DAG.getNode(ISD::ADD, SDLoc(N), PtrType, NewPtr,
8773 DAG.getConstant(PtrOff, PtrType));
8776 // The replacement we need to do here is a little tricky: we need to
8777 // replace an extractelement of a load with a load.
8778 // Use ReplaceAllUsesOfValuesWith to do the replacement.
8779 // Note that this replacement assumes that the extractvalue is the only
8780 // use of the load; that's okay because we don't want to perform this
8781 // transformation in other cases anyway.
8784 if (NVT.bitsGT(LVT)) {
8785 // If the result type of vextract is wider than the load, then issue an
8786 // extending load instead.
8787 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT)
8788 ? ISD::ZEXTLOAD : ISD::EXTLOAD;
8789 Load = DAG.getExtLoad(ExtType, SDLoc(N), NVT, LN0->getChain(),
8790 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff),
8791 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align);
8792 Chain = Load.getValue(1);
8794 Load = DAG.getLoad(LVT, SDLoc(N), LN0->getChain(), NewPtr,
8795 LN0->getPointerInfo().getWithOffset(PtrOff),
8796 LN0->isVolatile(), LN0->isNonTemporal(),
8797 LN0->isInvariant(), Align);
8798 Chain = Load.getValue(1);
8799 if (NVT.bitsLT(LVT))
8800 Load = DAG.getNode(ISD::TRUNCATE, SDLoc(N), NVT, Load);
8802 Load = DAG.getNode(ISD::BITCAST, SDLoc(N), NVT, Load);
8804 WorkListRemover DeadNodes(*this);
8805 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) };
8806 SDValue To[] = { Load, Chain };
8807 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
8808 // Since we're explcitly calling ReplaceAllUses, add the new node to the
8809 // worklist explicitly as well.
8810 AddToWorkList(Load.getNode());
8811 AddUsersToWorkList(Load.getNode()); // Add users too
8812 // Make sure to revisit this node to clean it up; it will usually be dead.
8814 return SDValue(N, 0);
8820 // Simplify (build_vec (ext )) to (bitcast (build_vec ))
8821 SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) {
8822 // We perform this optimization post type-legalization because
8823 // the type-legalizer often scalarizes integer-promoted vectors.
8824 // Performing this optimization before may create bit-casts which
8825 // will be type-legalized to complex code sequences.
8826 // We perform this optimization only before the operation legalizer because we
8827 // may introduce illegal operations.
8828 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes)
8831 unsigned NumInScalars = N->getNumOperands();
8833 EVT VT = N->getValueType(0);
8835 // Check to see if this is a BUILD_VECTOR of a bunch of values
8836 // which come from any_extend or zero_extend nodes. If so, we can create
8837 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR
8838 // optimizations. We do not handle sign-extend because we can't fill the sign
8840 EVT SourceType = MVT::Other;
8841 bool AllAnyExt = true;
8843 for (unsigned i = 0; i != NumInScalars; ++i) {
8844 SDValue In = N->getOperand(i);
8845 // Ignore undef inputs.
8846 if (In.getOpcode() == ISD::UNDEF) continue;
8848 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
8849 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
8851 // Abort if the element is not an extension.
8852 if (!ZeroExt && !AnyExt) {
8853 SourceType = MVT::Other;
8857 // The input is a ZeroExt or AnyExt. Check the original type.
8858 EVT InTy = In.getOperand(0).getValueType();
8860 // Check that all of the widened source types are the same.
8861 if (SourceType == MVT::Other)
8864 else if (InTy != SourceType) {
8865 // Multiple income types. Abort.
8866 SourceType = MVT::Other;
8870 // Check if all of the extends are ANY_EXTENDs.
8871 AllAnyExt &= AnyExt;
8874 // In order to have valid types, all of the inputs must be extended from the
8875 // same source type and all of the inputs must be any or zero extend.
8876 // Scalar sizes must be a power of two.
8877 EVT OutScalarTy = VT.getScalarType();
8878 bool ValidTypes = SourceType != MVT::Other &&
8879 isPowerOf2_32(OutScalarTy.getSizeInBits()) &&
8880 isPowerOf2_32(SourceType.getSizeInBits());
8882 // Create a new simpler BUILD_VECTOR sequence which other optimizations can
8883 // turn into a single shuffle instruction.
8887 bool isLE = TLI.isLittleEndian();
8888 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits();
8889 assert(ElemRatio > 1 && "Invalid element size ratio");
8890 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType):
8891 DAG.getConstant(0, SourceType);
8893 unsigned NewBVElems = ElemRatio * VT.getVectorNumElements();
8894 SmallVector<SDValue, 8> Ops(NewBVElems, Filler);
8896 // Populate the new build_vector
8897 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
8898 SDValue Cast = N->getOperand(i);
8899 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
8900 Cast.getOpcode() == ISD::ZERO_EXTEND ||
8901 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
8903 if (Cast.getOpcode() == ISD::UNDEF)
8904 In = DAG.getUNDEF(SourceType);
8906 In = Cast->getOperand(0);
8907 unsigned Index = isLE ? (i * ElemRatio) :
8908 (i * ElemRatio + (ElemRatio - 1));
8910 assert(Index < Ops.size() && "Invalid index");
8914 // The type of the new BUILD_VECTOR node.
8915 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems);
8916 assert(VecVT.getSizeInBits() == VT.getSizeInBits() &&
8917 "Invalid vector size");
8918 // Check if the new vector type is legal.
8919 if (!isTypeLegal(VecVT)) return SDValue();
8921 // Make the new BUILD_VECTOR.
8922 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], Ops.size());
8924 // The new BUILD_VECTOR node has the potential to be further optimized.
8925 AddToWorkList(BV.getNode());
8926 // Bitcast to the desired type.
8927 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
8930 SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) {
8931 EVT VT = N->getValueType(0);
8933 unsigned NumInScalars = N->getNumOperands();
8936 EVT SrcVT = MVT::Other;
8937 unsigned Opcode = ISD::DELETED_NODE;
8938 unsigned NumDefs = 0;
8940 for (unsigned i = 0; i != NumInScalars; ++i) {
8941 SDValue In = N->getOperand(i);
8942 unsigned Opc = In.getOpcode();
8944 if (Opc == ISD::UNDEF)
8947 // If all scalar values are floats and converted from integers.
8948 if (Opcode == ISD::DELETED_NODE &&
8949 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) {
8956 EVT InVT = In.getOperand(0).getValueType();
8958 // If all scalar values are typed differently, bail out. It's chosen to
8959 // simplify BUILD_VECTOR of integer types.
8960 if (SrcVT == MVT::Other)
8967 // If the vector has just one element defined, it's not worth to fold it into
8968 // a vectorized one.
8972 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP)
8973 && "Should only handle conversion from integer to float.");
8974 assert(SrcVT != MVT::Other && "Cannot determine source type!");
8976 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars);
8978 if (!TLI.isOperationLegalOrCustom(Opcode, NVT))
8981 SmallVector<SDValue, 8> Opnds;
8982 for (unsigned i = 0; i != NumInScalars; ++i) {
8983 SDValue In = N->getOperand(i);
8985 if (In.getOpcode() == ISD::UNDEF)
8986 Opnds.push_back(DAG.getUNDEF(SrcVT));
8988 Opnds.push_back(In.getOperand(0));
8990 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT,
8991 &Opnds[0], Opnds.size());
8992 AddToWorkList(BV.getNode());
8994 return DAG.getNode(Opcode, dl, VT, BV);
8997 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
8998 unsigned NumInScalars = N->getNumOperands();
9000 EVT VT = N->getValueType(0);
9002 // A vector built entirely of undefs is undef.
9003 if (ISD::allOperandsUndef(N))
9004 return DAG.getUNDEF(VT);
9006 SDValue V = reduceBuildVecExtToExtBuildVec(N);
9010 V = reduceBuildVecConvertToConvertBuildVec(N);
9014 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
9015 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
9016 // at most two distinct vectors, turn this into a shuffle node.
9018 // May only combine to shuffle after legalize if shuffle is legal.
9019 if (LegalOperations &&
9020 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT))
9023 SDValue VecIn1, VecIn2;
9024 for (unsigned i = 0; i != NumInScalars; ++i) {
9025 // Ignore undef inputs.
9026 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
9028 // If this input is something other than a EXTRACT_VECTOR_ELT with a
9029 // constant index, bail out.
9030 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
9031 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
9032 VecIn1 = VecIn2 = SDValue(0, 0);
9036 // We allow up to two distinct input vectors.
9037 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
9038 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
9041 if (VecIn1.getNode() == 0) {
9042 VecIn1 = ExtractedFromVec;
9043 } else if (VecIn2.getNode() == 0) {
9044 VecIn2 = ExtractedFromVec;
9047 VecIn1 = VecIn2 = SDValue(0, 0);
9052 // If everything is good, we can make a shuffle operation.
9053 if (VecIn1.getNode()) {
9054 SmallVector<int, 8> Mask;
9055 for (unsigned i = 0; i != NumInScalars; ++i) {
9056 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
9061 // If extracting from the first vector, just use the index directly.
9062 SDValue Extract = N->getOperand(i);
9063 SDValue ExtVal = Extract.getOperand(1);
9064 if (Extract.getOperand(0) == VecIn1) {
9065 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
9066 if (ExtIndex > VT.getVectorNumElements())
9069 Mask.push_back(ExtIndex);
9073 // Otherwise, use InIdx + VecSize
9074 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
9075 Mask.push_back(Idx+NumInScalars);
9078 // We can't generate a shuffle node with mismatched input and output types.
9079 // Attempt to transform a single input vector to the correct type.
9080 if ((VT != VecIn1.getValueType())) {
9081 // We don't support shuffeling between TWO values of different types.
9082 if (VecIn2.getNode() != 0)
9085 // We only support widening of vectors which are half the size of the
9086 // output registers. For example XMM->YMM widening on X86 with AVX.
9087 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits())
9090 // If the input vector type has a different base type to the output
9091 // vector type, bail out.
9092 if (VecIn1.getValueType().getVectorElementType() !=
9093 VT.getVectorElementType())
9096 // Widen the input vector by adding undef values.
9097 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9098 VecIn1, DAG.getUNDEF(VecIn1.getValueType()));
9101 // If VecIn2 is unused then change it to undef.
9102 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
9104 // Check that we were able to transform all incoming values to the same
9106 if (VecIn2.getValueType() != VecIn1.getValueType() ||
9107 VecIn1.getValueType() != VT)
9110 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes.
9111 if (!isTypeLegal(VT))
9114 // Return the new VECTOR_SHUFFLE node.
9118 return DAG.getVectorShuffle(VT, dl, Ops[0], Ops[1], &Mask[0]);
9124 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
9125 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
9126 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
9127 // inputs come from at most two distinct vectors, turn this into a shuffle
9130 // If we only have one input vector, we don't need to do any concatenation.
9131 if (N->getNumOperands() == 1)
9132 return N->getOperand(0);
9134 // Check if all of the operands are undefs.
9135 if (ISD::allOperandsUndef(N))
9136 return DAG.getUNDEF(N->getValueType(0));
9138 // Type legalization of vectors and DAG canonicalization of SHUFFLE_VECTOR
9139 // nodes often generate nop CONCAT_VECTOR nodes.
9140 // Scan the CONCAT_VECTOR operands and look for a CONCAT operations that
9141 // place the incoming vectors at the exact same location.
9142 SDValue SingleSource = SDValue();
9143 unsigned PartNumElem = N->getOperand(0).getValueType().getVectorNumElements();
9145 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
9146 SDValue Op = N->getOperand(i);
9148 if (Op.getOpcode() == ISD::UNDEF)
9151 // Check if this is the identity extract:
9152 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR)
9155 // Find the single incoming vector for the extract_subvector.
9156 if (SingleSource.getNode()) {
9157 if (Op.getOperand(0) != SingleSource)
9160 SingleSource = Op.getOperand(0);
9162 // Check the source type is the same as the type of the result.
9163 // If not, this concat may extend the vector, so we can not
9164 // optimize it away.
9165 if (SingleSource.getValueType() != N->getValueType(0))
9169 unsigned IdentityIndex = i * PartNumElem;
9170 ConstantSDNode *CS = dyn_cast<ConstantSDNode>(Op.getOperand(1));
9171 // The extract index must be constant.
9175 // Check that we are reading from the identity index.
9176 if (CS->getZExtValue() != IdentityIndex)
9180 if (SingleSource.getNode())
9181 return SingleSource;
9186 SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
9187 EVT NVT = N->getValueType(0);
9188 SDValue V = N->getOperand(0);
9190 if (V->getOpcode() == ISD::CONCAT_VECTORS) {
9192 // (extract_subvec (concat V1, V2, ...), i)
9195 // Only operand 0 is checked as 'concat' assumes all inputs of the same type.
9196 if (V->getOperand(0).getValueType() != NVT)
9198 unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
9199 unsigned NumElems = NVT.getVectorNumElements();
9200 assert((Idx % NumElems) == 0 &&
9201 "IDX in concat is not a multiple of the result vector length.");
9202 return V->getOperand(Idx / NumElems);
9206 if (V->getOpcode() == ISD::BITCAST)
9207 V = V.getOperand(0);
9209 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
9211 // Handle only simple case where vector being inserted and vector
9212 // being extracted are of same type, and are half size of larger vectors.
9213 EVT BigVT = V->getOperand(0).getValueType();
9214 EVT SmallVT = V->getOperand(1).getValueType();
9215 if (!NVT.bitsEq(SmallVT) || NVT.getSizeInBits()*2 != BigVT.getSizeInBits())
9218 // Only handle cases where both indexes are constants with the same type.
9219 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
9220 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2));
9222 if (InsIdx && ExtIdx &&
9223 InsIdx->getValueType(0).getSizeInBits() <= 64 &&
9224 ExtIdx->getValueType(0).getSizeInBits() <= 64) {
9226 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx)
9228 // indices are equal or bit offsets are equal => V1
9229 // otherwise => (extract_subvec V1, ExtIdx)
9230 if (InsIdx->getZExtValue() * SmallVT.getScalarType().getSizeInBits() ==
9231 ExtIdx->getZExtValue() * NVT.getScalarType().getSizeInBits())
9232 return DAG.getNode(ISD::BITCAST, dl, NVT, V->getOperand(1));
9233 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT,
9234 DAG.getNode(ISD::BITCAST, dl,
9235 N->getOperand(0).getValueType(),
9236 V->getOperand(0)), N->getOperand(1));
9243 // Tries to turn a shuffle of two CONCAT_VECTORS into a single concat.
9244 static SDValue partitionShuffleOfConcats(SDNode *N, SelectionDAG &DAG) {
9245 EVT VT = N->getValueType(0);
9246 unsigned NumElts = VT.getVectorNumElements();
9248 SDValue N0 = N->getOperand(0);
9249 SDValue N1 = N->getOperand(1);
9250 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
9252 SmallVector<SDValue, 4> Ops;
9253 EVT ConcatVT = N0.getOperand(0).getValueType();
9254 unsigned NumElemsPerConcat = ConcatVT.getVectorNumElements();
9255 unsigned NumConcats = NumElts / NumElemsPerConcat;
9257 // Look at every vector that's inserted. We're looking for exact
9258 // subvector-sized copies from a concatenated vector
9259 for (unsigned I = 0; I != NumConcats; ++I) {
9260 // Make sure we're dealing with a copy.
9261 unsigned Begin = I * NumElemsPerConcat;
9262 bool AllUndef = true, NoUndef = true;
9263 for (unsigned J = Begin; J != Begin + NumElemsPerConcat; ++J) {
9264 if (SVN->getMaskElt(J) >= 0)
9271 if (SVN->getMaskElt(Begin) % NumElemsPerConcat != 0)
9274 for (unsigned J = 1; J != NumElemsPerConcat; ++J)
9275 if (SVN->getMaskElt(Begin + J - 1) + 1 != SVN->getMaskElt(Begin + J))
9278 unsigned FirstElt = SVN->getMaskElt(Begin) / NumElemsPerConcat;
9279 if (FirstElt < N0.getNumOperands())
9280 Ops.push_back(N0.getOperand(FirstElt));
9282 Ops.push_back(N1.getOperand(FirstElt - N0.getNumOperands()));
9284 } else if (AllUndef) {
9285 Ops.push_back(DAG.getUNDEF(N0.getOperand(0).getValueType()));
9286 } else { // Mixed with general masks and undefs, can't do optimization.
9291 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops.data(),
9295 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
9296 EVT VT = N->getValueType(0);
9297 unsigned NumElts = VT.getVectorNumElements();
9299 SDValue N0 = N->getOperand(0);
9300 SDValue N1 = N->getOperand(1);
9302 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG");
9304 // Canonicalize shuffle undef, undef -> undef
9305 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
9306 return DAG.getUNDEF(VT);
9308 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
9310 // Canonicalize shuffle v, v -> v, undef
9312 SmallVector<int, 8> NewMask;
9313 for (unsigned i = 0; i != NumElts; ++i) {
9314 int Idx = SVN->getMaskElt(i);
9315 if (Idx >= (int)NumElts) Idx -= NumElts;
9316 NewMask.push_back(Idx);
9318 return DAG.getVectorShuffle(VT, SDLoc(N), N0, DAG.getUNDEF(VT),
9322 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
9323 if (N0.getOpcode() == ISD::UNDEF) {
9324 SmallVector<int, 8> NewMask;
9325 for (unsigned i = 0; i != NumElts; ++i) {
9326 int Idx = SVN->getMaskElt(i);
9328 if (Idx < (int)NumElts)
9333 NewMask.push_back(Idx);
9335 return DAG.getVectorShuffle(VT, SDLoc(N), N1, DAG.getUNDEF(VT),
9339 // Remove references to rhs if it is undef
9340 if (N1.getOpcode() == ISD::UNDEF) {
9341 bool Changed = false;
9342 SmallVector<int, 8> NewMask;
9343 for (unsigned i = 0; i != NumElts; ++i) {
9344 int Idx = SVN->getMaskElt(i);
9345 if (Idx >= (int)NumElts) {
9349 NewMask.push_back(Idx);
9352 return DAG.getVectorShuffle(VT, SDLoc(N), N0, N1, &NewMask[0]);
9355 // If it is a splat, check if the argument vector is another splat or a
9356 // build_vector with all scalar elements the same.
9357 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
9358 SDNode *V = N0.getNode();
9360 // If this is a bit convert that changes the element type of the vector but
9361 // not the number of vector elements, look through it. Be careful not to
9362 // look though conversions that change things like v4f32 to v2f64.
9363 if (V->getOpcode() == ISD::BITCAST) {
9364 SDValue ConvInput = V->getOperand(0);
9365 if (ConvInput.getValueType().isVector() &&
9366 ConvInput.getValueType().getVectorNumElements() == NumElts)
9367 V = ConvInput.getNode();
9370 if (V->getOpcode() == ISD::BUILD_VECTOR) {
9371 assert(V->getNumOperands() == NumElts &&
9372 "BUILD_VECTOR has wrong number of operands");
9374 bool AllSame = true;
9375 for (unsigned i = 0; i != NumElts; ++i) {
9376 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
9377 Base = V->getOperand(i);
9381 // Splat of <u, u, u, u>, return <u, u, u, u>
9382 if (!Base.getNode())
9384 for (unsigned i = 0; i != NumElts; ++i) {
9385 if (V->getOperand(i) != Base) {
9390 // Splat of <x, x, x, x>, return <x, x, x, x>
9396 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
9397 Level < AfterLegalizeVectorOps &&
9398 (N1.getOpcode() == ISD::UNDEF ||
9399 (N1.getOpcode() == ISD::CONCAT_VECTORS &&
9400 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()))) {
9401 SDValue V = partitionShuffleOfConcats(N, DAG);
9407 // If this shuffle node is simply a swizzle of another shuffle node,
9408 // and it reverses the swizzle of the previous shuffle then we can
9409 // optimize shuffle(shuffle(x, undef), undef) -> x.
9410 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
9411 N1.getOpcode() == ISD::UNDEF) {
9413 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
9415 // Shuffle nodes can only reverse shuffles with a single non-undef value.
9416 if (N0.getOperand(1).getOpcode() != ISD::UNDEF)
9419 // The incoming shuffle must be of the same type as the result of the
9421 assert(OtherSV->getOperand(0).getValueType() == VT &&
9422 "Shuffle types don't match");
9424 for (unsigned i = 0; i != NumElts; ++i) {
9425 int Idx = SVN->getMaskElt(i);
9426 assert(Idx < (int)NumElts && "Index references undef operand");
9427 // Next, this index comes from the first value, which is the incoming
9428 // shuffle. Adopt the incoming index.
9430 Idx = OtherSV->getMaskElt(Idx);
9432 // The combined shuffle must map each index to itself.
9433 if (Idx >= 0 && (unsigned)Idx != i)
9437 return OtherSV->getOperand(0);
9443 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
9444 /// an AND to a vector_shuffle with the destination vector and a zero vector.
9445 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
9446 /// vector_shuffle V, Zero, <0, 4, 2, 4>
9447 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
9448 EVT VT = N->getValueType(0);
9450 SDValue LHS = N->getOperand(0);
9451 SDValue RHS = N->getOperand(1);
9452 if (N->getOpcode() == ISD::AND) {
9453 if (RHS.getOpcode() == ISD::BITCAST)
9454 RHS = RHS.getOperand(0);
9455 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
9456 SmallVector<int, 8> Indices;
9457 unsigned NumElts = RHS.getNumOperands();
9458 for (unsigned i = 0; i != NumElts; ++i) {
9459 SDValue Elt = RHS.getOperand(i);
9460 if (!isa<ConstantSDNode>(Elt))
9463 if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
9464 Indices.push_back(i);
9465 else if (cast<ConstantSDNode>(Elt)->isNullValue())
9466 Indices.push_back(NumElts);
9471 // Let's see if the target supports this vector_shuffle.
9472 EVT RVT = RHS.getValueType();
9473 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
9476 // Return the new VECTOR_SHUFFLE node.
9477 EVT EltVT = RVT.getVectorElementType();
9478 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
9479 DAG.getConstant(0, EltVT));
9480 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
9481 RVT, &ZeroOps[0], ZeroOps.size());
9482 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
9483 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
9484 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
9491 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
9492 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
9493 assert(N->getValueType(0).isVector() &&
9494 "SimplifyVBinOp only works on vectors!");
9496 SDValue LHS = N->getOperand(0);
9497 SDValue RHS = N->getOperand(1);
9498 SDValue Shuffle = XformToShuffleWithZero(N);
9499 if (Shuffle.getNode()) return Shuffle;
9501 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
9503 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
9504 RHS.getOpcode() == ISD::BUILD_VECTOR) {
9505 SmallVector<SDValue, 8> Ops;
9506 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
9507 SDValue LHSOp = LHS.getOperand(i);
9508 SDValue RHSOp = RHS.getOperand(i);
9509 // If these two elements can't be folded, bail out.
9510 if ((LHSOp.getOpcode() != ISD::UNDEF &&
9511 LHSOp.getOpcode() != ISD::Constant &&
9512 LHSOp.getOpcode() != ISD::ConstantFP) ||
9513 (RHSOp.getOpcode() != ISD::UNDEF &&
9514 RHSOp.getOpcode() != ISD::Constant &&
9515 RHSOp.getOpcode() != ISD::ConstantFP))
9518 // Can't fold divide by zero.
9519 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
9520 N->getOpcode() == ISD::FDIV) {
9521 if ((RHSOp.getOpcode() == ISD::Constant &&
9522 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
9523 (RHSOp.getOpcode() == ISD::ConstantFP &&
9524 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
9528 EVT VT = LHSOp.getValueType();
9529 EVT RVT = RHSOp.getValueType();
9531 // Integer BUILD_VECTOR operands may have types larger than the element
9532 // size (e.g., when the element type is not legal). Prior to type
9533 // legalization, the types may not match between the two BUILD_VECTORS.
9534 // Truncate one of the operands to make them match.
9535 if (RVT.getSizeInBits() > VT.getSizeInBits()) {
9536 RHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, RHSOp);
9538 LHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), RVT, LHSOp);
9542 SDValue FoldOp = DAG.getNode(N->getOpcode(), SDLoc(LHS), VT,
9544 if (FoldOp.getOpcode() != ISD::UNDEF &&
9545 FoldOp.getOpcode() != ISD::Constant &&
9546 FoldOp.getOpcode() != ISD::ConstantFP)
9548 Ops.push_back(FoldOp);
9549 AddToWorkList(FoldOp.getNode());
9552 if (Ops.size() == LHS.getNumOperands())
9553 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
9554 LHS.getValueType(), &Ops[0], Ops.size());
9560 /// SimplifyVUnaryOp - Visit a binary vector operation, like FABS/FNEG.
9561 SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) {
9562 assert(N->getValueType(0).isVector() &&
9563 "SimplifyVUnaryOp only works on vectors!");
9565 SDValue N0 = N->getOperand(0);
9567 if (N0.getOpcode() != ISD::BUILD_VECTOR)
9570 // Operand is a BUILD_VECTOR node, see if we can constant fold it.
9571 SmallVector<SDValue, 8> Ops;
9572 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
9573 SDValue Op = N0.getOperand(i);
9574 if (Op.getOpcode() != ISD::UNDEF &&
9575 Op.getOpcode() != ISD::ConstantFP)
9577 EVT EltVT = Op.getValueType();
9578 SDValue FoldOp = DAG.getNode(N->getOpcode(), SDLoc(N0), EltVT, Op);
9579 if (FoldOp.getOpcode() != ISD::UNDEF &&
9580 FoldOp.getOpcode() != ISD::ConstantFP)
9582 Ops.push_back(FoldOp);
9583 AddToWorkList(FoldOp.getNode());
9586 if (Ops.size() != N0.getNumOperands())
9589 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
9590 N0.getValueType(), &Ops[0], Ops.size());
9593 SDValue DAGCombiner::SimplifySelect(SDLoc DL, SDValue N0,
9594 SDValue N1, SDValue N2){
9595 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
9597 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
9598 cast<CondCodeSDNode>(N0.getOperand(2))->get());
9600 // If we got a simplified select_cc node back from SimplifySelectCC, then
9601 // break it down into a new SETCC node, and a new SELECT node, and then return
9602 // the SELECT node, since we were called with a SELECT node.
9603 if (SCC.getNode()) {
9604 // Check to see if we got a select_cc back (to turn into setcc/select).
9605 // Otherwise, just return whatever node we got back, like fabs.
9606 if (SCC.getOpcode() == ISD::SELECT_CC) {
9607 SDValue SETCC = DAG.getNode(ISD::SETCC, SDLoc(N0),
9609 SCC.getOperand(0), SCC.getOperand(1),
9611 AddToWorkList(SETCC.getNode());
9612 return DAG.getSelect(SDLoc(SCC), SCC.getValueType(),
9613 SCC.getOperand(2), SCC.getOperand(3), SETCC);
9621 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
9622 /// are the two values being selected between, see if we can simplify the
9623 /// select. Callers of this should assume that TheSelect is deleted if this
9624 /// returns true. As such, they should return the appropriate thing (e.g. the
9625 /// node) back to the top-level of the DAG combiner loop to avoid it being
9627 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
9630 // Cannot simplify select with vector condition
9631 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
9633 // If this is a select from two identical things, try to pull the operation
9634 // through the select.
9635 if (LHS.getOpcode() != RHS.getOpcode() ||
9636 !LHS.hasOneUse() || !RHS.hasOneUse())
9639 // If this is a load and the token chain is identical, replace the select
9640 // of two loads with a load through a select of the address to load from.
9641 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
9642 // constants have been dropped into the constant pool.
9643 if (LHS.getOpcode() == ISD::LOAD) {
9644 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
9645 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
9647 // Token chains must be identical.
9648 if (LHS.getOperand(0) != RHS.getOperand(0) ||
9649 // Do not let this transformation reduce the number of volatile loads.
9650 LLD->isVolatile() || RLD->isVolatile() ||
9651 // If this is an EXTLOAD, the VT's must match.
9652 LLD->getMemoryVT() != RLD->getMemoryVT() ||
9653 // If this is an EXTLOAD, the kind of extension must match.
9654 (LLD->getExtensionType() != RLD->getExtensionType() &&
9655 // The only exception is if one of the extensions is anyext.
9656 LLD->getExtensionType() != ISD::EXTLOAD &&
9657 RLD->getExtensionType() != ISD::EXTLOAD) ||
9658 // FIXME: this discards src value information. This is
9659 // over-conservative. It would be beneficial to be able to remember
9660 // both potential memory locations. Since we are discarding
9661 // src value info, don't do the transformation if the memory
9662 // locations are not in the default address space.
9663 LLD->getPointerInfo().getAddrSpace() != 0 ||
9664 RLD->getPointerInfo().getAddrSpace() != 0 ||
9665 !TLI.isOperationLegalOrCustom(TheSelect->getOpcode(),
9666 LLD->getBasePtr().getValueType()))
9669 // Check that the select condition doesn't reach either load. If so,
9670 // folding this will induce a cycle into the DAG. If not, this is safe to
9671 // xform, so create a select of the addresses.
9673 if (TheSelect->getOpcode() == ISD::SELECT) {
9674 SDNode *CondNode = TheSelect->getOperand(0).getNode();
9675 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
9676 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
9678 // The loads must not depend on one another.
9679 if (LLD->isPredecessorOf(RLD) ||
9680 RLD->isPredecessorOf(LLD))
9682 Addr = DAG.getSelect(SDLoc(TheSelect),
9683 LLD->getBasePtr().getValueType(),
9684 TheSelect->getOperand(0), LLD->getBasePtr(),
9686 } else { // Otherwise SELECT_CC
9687 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
9688 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
9690 if ((LLD->hasAnyUseOfValue(1) &&
9691 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
9692 (RLD->hasAnyUseOfValue(1) &&
9693 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS))))
9696 Addr = DAG.getNode(ISD::SELECT_CC, SDLoc(TheSelect),
9697 LLD->getBasePtr().getValueType(),
9698 TheSelect->getOperand(0),
9699 TheSelect->getOperand(1),
9700 LLD->getBasePtr(), RLD->getBasePtr(),
9701 TheSelect->getOperand(4));
9705 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
9706 Load = DAG.getLoad(TheSelect->getValueType(0),
9708 // FIXME: Discards pointer info.
9709 LLD->getChain(), Addr, MachinePointerInfo(),
9710 LLD->isVolatile(), LLD->isNonTemporal(),
9711 LLD->isInvariant(), LLD->getAlignment());
9713 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
9714 RLD->getExtensionType() : LLD->getExtensionType(),
9716 TheSelect->getValueType(0),
9717 // FIXME: Discards pointer info.
9718 LLD->getChain(), Addr, MachinePointerInfo(),
9719 LLD->getMemoryVT(), LLD->isVolatile(),
9720 LLD->isNonTemporal(), LLD->getAlignment());
9723 // Users of the select now use the result of the load.
9724 CombineTo(TheSelect, Load);
9726 // Users of the old loads now use the new load's chain. We know the
9727 // old-load value is dead now.
9728 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
9729 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
9736 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
9737 /// where 'cond' is the comparison specified by CC.
9738 SDValue DAGCombiner::SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1,
9739 SDValue N2, SDValue N3,
9740 ISD::CondCode CC, bool NotExtCompare) {
9741 // (x ? y : y) -> y.
9742 if (N2 == N3) return N2;
9744 EVT VT = N2.getValueType();
9745 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
9746 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
9747 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
9749 // Determine if the condition we're dealing with is constant
9750 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
9751 N0, N1, CC, DL, false);
9752 if (SCC.getNode()) AddToWorkList(SCC.getNode());
9753 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
9755 // fold select_cc true, x, y -> x
9756 if (SCCC && !SCCC->isNullValue())
9758 // fold select_cc false, x, y -> y
9759 if (SCCC && SCCC->isNullValue())
9762 // Check to see if we can simplify the select into an fabs node
9763 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
9764 // Allow either -0.0 or 0.0
9765 if (CFP->getValueAPF().isZero()) {
9766 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
9767 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
9768 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
9769 N2 == N3.getOperand(0))
9770 return DAG.getNode(ISD::FABS, DL, VT, N0);
9772 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
9773 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
9774 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
9775 N2.getOperand(0) == N3)
9776 return DAG.getNode(ISD::FABS, DL, VT, N3);
9780 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
9781 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
9782 // in it. This is a win when the constant is not otherwise available because
9783 // it replaces two constant pool loads with one. We only do this if the FP
9784 // type is known to be legal, because if it isn't, then we are before legalize
9785 // types an we want the other legalization to happen first (e.g. to avoid
9786 // messing with soft float) and if the ConstantFP is not legal, because if
9787 // it is legal, we may not need to store the FP constant in a constant pool.
9788 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
9789 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
9790 if (TLI.isTypeLegal(N2.getValueType()) &&
9791 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
9792 TargetLowering::Legal) &&
9793 // If both constants have multiple uses, then we won't need to do an
9794 // extra load, they are likely around in registers for other users.
9795 (TV->hasOneUse() || FV->hasOneUse())) {
9796 Constant *Elts[] = {
9797 const_cast<ConstantFP*>(FV->getConstantFPValue()),
9798 const_cast<ConstantFP*>(TV->getConstantFPValue())
9800 Type *FPTy = Elts[0]->getType();
9801 const DataLayout &TD = *TLI.getDataLayout();
9803 // Create a ConstantArray of the two constants.
9804 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
9805 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
9806 TD.getPrefTypeAlignment(FPTy));
9807 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9809 // Get the offsets to the 0 and 1 element of the array so that we can
9810 // select between them.
9811 SDValue Zero = DAG.getIntPtrConstant(0);
9812 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
9813 SDValue One = DAG.getIntPtrConstant(EltSize);
9815 SDValue Cond = DAG.getSetCC(DL,
9816 getSetCCResultType(N0.getValueType()),
9818 AddToWorkList(Cond.getNode());
9819 SDValue CstOffset = DAG.getSelect(DL, Zero.getValueType(),
9821 AddToWorkList(CstOffset.getNode());
9822 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
9824 AddToWorkList(CPIdx.getNode());
9825 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
9826 MachinePointerInfo::getConstantPool(), false,
9827 false, false, Alignment);
9832 // Check to see if we can perform the "gzip trick", transforming
9833 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
9834 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
9835 (N1C->isNullValue() || // (a < 0) ? b : 0
9836 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
9837 EVT XType = N0.getValueType();
9838 EVT AType = N2.getValueType();
9839 if (XType.bitsGE(AType)) {
9840 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
9841 // single-bit constant.
9842 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
9843 unsigned ShCtV = N2C->getAPIntValue().logBase2();
9844 ShCtV = XType.getSizeInBits()-ShCtV-1;
9845 SDValue ShCt = DAG.getConstant(ShCtV,
9846 getShiftAmountTy(N0.getValueType()));
9847 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0),
9849 AddToWorkList(Shift.getNode());
9851 if (XType.bitsGT(AType)) {
9852 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
9853 AddToWorkList(Shift.getNode());
9856 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
9859 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0),
9861 DAG.getConstant(XType.getSizeInBits()-1,
9862 getShiftAmountTy(N0.getValueType())));
9863 AddToWorkList(Shift.getNode());
9865 if (XType.bitsGT(AType)) {
9866 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
9867 AddToWorkList(Shift.getNode());
9870 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
9874 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
9875 // where y is has a single bit set.
9876 // A plaintext description would be, we can turn the SELECT_CC into an AND
9877 // when the condition can be materialized as an all-ones register. Any
9878 // single bit-test can be materialized as an all-ones register with
9879 // shift-left and shift-right-arith.
9880 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
9881 N0->getValueType(0) == VT &&
9882 N1C && N1C->isNullValue() &&
9883 N2C && N2C->isNullValue()) {
9884 SDValue AndLHS = N0->getOperand(0);
9885 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
9886 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
9887 // Shift the tested bit over the sign bit.
9888 APInt AndMask = ConstAndRHS->getAPIntValue();
9890 DAG.getConstant(AndMask.countLeadingZeros(),
9891 getShiftAmountTy(AndLHS.getValueType()));
9892 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt);
9894 // Now arithmetic right shift it all the way over, so the result is either
9895 // all-ones, or zero.
9897 DAG.getConstant(AndMask.getBitWidth()-1,
9898 getShiftAmountTy(Shl.getValueType()));
9899 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt);
9901 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
9905 // fold select C, 16, 0 -> shl C, 4
9906 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
9907 TLI.getBooleanContents(N0.getValueType().isVector()) ==
9908 TargetLowering::ZeroOrOneBooleanContent) {
9910 // If the caller doesn't want us to simplify this into a zext of a compare,
9912 if (NotExtCompare && N2C->getAPIntValue() == 1)
9915 // Get a SetCC of the condition
9916 // NOTE: Don't create a SETCC if it's not legal on this target.
9917 if (!LegalOperations ||
9918 TLI.isOperationLegal(ISD::SETCC,
9919 LegalTypes ? getSetCCResultType(N0.getValueType()) : MVT::i1)) {
9921 // cast from setcc result type to select result type
9923 SCC = DAG.getSetCC(DL, getSetCCResultType(N0.getValueType()),
9925 if (N2.getValueType().bitsLT(SCC.getValueType()))
9926 Temp = DAG.getZeroExtendInReg(SCC, SDLoc(N2),
9929 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
9930 N2.getValueType(), SCC);
9932 SCC = DAG.getSetCC(SDLoc(N0), MVT::i1, N0, N1, CC);
9933 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
9934 N2.getValueType(), SCC);
9937 AddToWorkList(SCC.getNode());
9938 AddToWorkList(Temp.getNode());
9940 if (N2C->getAPIntValue() == 1)
9943 // shl setcc result by log2 n2c
9944 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
9945 DAG.getConstant(N2C->getAPIntValue().logBase2(),
9946 getShiftAmountTy(Temp.getValueType())));
9950 // Check to see if this is the equivalent of setcc
9951 // FIXME: Turn all of these into setcc if setcc if setcc is legal
9952 // otherwise, go ahead with the folds.
9953 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
9954 EVT XType = N0.getValueType();
9955 if (!LegalOperations ||
9956 TLI.isOperationLegal(ISD::SETCC, getSetCCResultType(XType))) {
9957 SDValue Res = DAG.getSetCC(DL, getSetCCResultType(XType), N0, N1, CC);
9958 if (Res.getValueType() != VT)
9959 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
9963 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
9964 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
9965 (!LegalOperations ||
9966 TLI.isOperationLegal(ISD::CTLZ, XType))) {
9967 SDValue Ctlz = DAG.getNode(ISD::CTLZ, SDLoc(N0), XType, N0);
9968 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
9969 DAG.getConstant(Log2_32(XType.getSizeInBits()),
9970 getShiftAmountTy(Ctlz.getValueType())));
9972 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
9973 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
9974 SDValue NegN0 = DAG.getNode(ISD::SUB, SDLoc(N0),
9975 XType, DAG.getConstant(0, XType), N0);
9976 SDValue NotN0 = DAG.getNOT(SDLoc(N0), N0, XType);
9977 return DAG.getNode(ISD::SRL, DL, XType,
9978 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
9979 DAG.getConstant(XType.getSizeInBits()-1,
9980 getShiftAmountTy(XType)));
9982 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
9983 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
9984 SDValue Sign = DAG.getNode(ISD::SRL, SDLoc(N0), XType, N0,
9985 DAG.getConstant(XType.getSizeInBits()-1,
9986 getShiftAmountTy(N0.getValueType())));
9987 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
9991 // Check to see if this is an integer abs.
9992 // select_cc setg[te] X, 0, X, -X ->
9993 // select_cc setgt X, -1, X, -X ->
9994 // select_cc setl[te] X, 0, -X, X ->
9995 // select_cc setlt X, 1, -X, X ->
9996 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
9998 ConstantSDNode *SubC = NULL;
9999 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
10000 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
10001 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
10002 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
10003 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
10004 (N1C->isOne() && CC == ISD::SETLT)) &&
10005 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
10006 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
10008 EVT XType = N0.getValueType();
10009 if (SubC && SubC->isNullValue() && XType.isInteger()) {
10010 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0), XType,
10012 DAG.getConstant(XType.getSizeInBits()-1,
10013 getShiftAmountTy(N0.getValueType())));
10014 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0),
10016 AddToWorkList(Shift.getNode());
10017 AddToWorkList(Add.getNode());
10018 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
10025 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
10026 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
10027 SDValue N1, ISD::CondCode Cond,
10028 SDLoc DL, bool foldBooleans) {
10029 TargetLowering::DAGCombinerInfo
10030 DagCombineInfo(DAG, Level, false, this);
10031 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
10034 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
10035 /// return a DAG expression to select that will generate the same value by
10036 /// multiplying by a magic number. See:
10037 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
10038 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
10039 std::vector<SDNode*> Built;
10040 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built);
10042 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
10044 AddToWorkList(*ii);
10048 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
10049 /// return a DAG expression to select that will generate the same value by
10050 /// multiplying by a magic number. See:
10051 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
10052 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
10053 std::vector<SDNode*> Built;
10054 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built);
10056 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
10058 AddToWorkList(*ii);
10062 /// FindBaseOffset - Return true if base is a frame index, which is known not
10063 // to alias with anything but itself. Provides base object and offset as
10065 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
10066 const GlobalValue *&GV, const void *&CV) {
10067 // Assume it is a primitive operation.
10068 Base = Ptr; Offset = 0; GV = 0; CV = 0;
10070 // If it's an adding a simple constant then integrate the offset.
10071 if (Base.getOpcode() == ISD::ADD) {
10072 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
10073 Base = Base.getOperand(0);
10074 Offset += C->getZExtValue();
10078 // Return the underlying GlobalValue, and update the Offset. Return false
10079 // for GlobalAddressSDNode since the same GlobalAddress may be represented
10080 // by multiple nodes with different offsets.
10081 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
10082 GV = G->getGlobal();
10083 Offset += G->getOffset();
10087 // Return the underlying Constant value, and update the Offset. Return false
10088 // for ConstantSDNodes since the same constant pool entry may be represented
10089 // by multiple nodes with different offsets.
10090 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
10091 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal()
10092 : (const void *)C->getConstVal();
10093 Offset += C->getOffset();
10096 // If it's any of the following then it can't alias with anything but itself.
10097 return isa<FrameIndexSDNode>(Base);
10100 /// isAlias - Return true if there is any possibility that the two addresses
10102 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
10103 const Value *SrcValue1, int SrcValueOffset1,
10104 unsigned SrcValueAlign1,
10105 const MDNode *TBAAInfo1,
10106 SDValue Ptr2, int64_t Size2,
10107 const Value *SrcValue2, int SrcValueOffset2,
10108 unsigned SrcValueAlign2,
10109 const MDNode *TBAAInfo2) const {
10110 // If they are the same then they must be aliases.
10111 if (Ptr1 == Ptr2) return true;
10113 // Gather base node and offset information.
10114 SDValue Base1, Base2;
10115 int64_t Offset1, Offset2;
10116 const GlobalValue *GV1, *GV2;
10117 const void *CV1, *CV2;
10118 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
10119 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
10121 // If they have a same base address then check to see if they overlap.
10122 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
10123 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
10125 // It is possible for different frame indices to alias each other, mostly
10126 // when tail call optimization reuses return address slots for arguments.
10127 // To catch this case, look up the actual index of frame indices to compute
10128 // the real alias relationship.
10129 if (isFrameIndex1 && isFrameIndex2) {
10130 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10131 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
10132 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
10133 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
10136 // Otherwise, if we know what the bases are, and they aren't identical, then
10137 // we know they cannot alias.
10138 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
10141 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
10142 // compared to the size and offset of the access, we may be able to prove they
10143 // do not alias. This check is conservative for now to catch cases created by
10144 // splitting vector types.
10145 if ((SrcValueAlign1 == SrcValueAlign2) &&
10146 (SrcValueOffset1 != SrcValueOffset2) &&
10147 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
10148 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
10149 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
10151 // There is no overlap between these relatively aligned accesses of similar
10152 // size, return no alias.
10153 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
10157 if (CombinerGlobalAA) {
10158 // Use alias analysis information.
10159 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
10160 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
10161 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
10162 AliasAnalysis::AliasResult AAResult =
10163 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1),
10164 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2));
10165 if (AAResult == AliasAnalysis::NoAlias)
10169 // Otherwise we have to assume they alias.
10173 bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) {
10174 SDValue Ptr0, Ptr1;
10175 int64_t Size0, Size1;
10176 const Value *SrcValue0, *SrcValue1;
10177 int SrcValueOffset0, SrcValueOffset1;
10178 unsigned SrcValueAlign0, SrcValueAlign1;
10179 const MDNode *SrcTBAAInfo0, *SrcTBAAInfo1;
10180 FindAliasInfo(Op0, Ptr0, Size0, SrcValue0, SrcValueOffset0,
10181 SrcValueAlign0, SrcTBAAInfo0);
10182 FindAliasInfo(Op1, Ptr1, Size1, SrcValue1, SrcValueOffset1,
10183 SrcValueAlign1, SrcTBAAInfo1);
10184 return isAlias(Ptr0, Size0, SrcValue0, SrcValueOffset0,
10185 SrcValueAlign0, SrcTBAAInfo0,
10186 Ptr1, Size1, SrcValue1, SrcValueOffset1,
10187 SrcValueAlign1, SrcTBAAInfo1);
10190 /// FindAliasInfo - Extracts the relevant alias information from the memory
10191 /// node. Returns true if the operand was a load.
10192 bool DAGCombiner::FindAliasInfo(SDNode *N,
10193 SDValue &Ptr, int64_t &Size,
10194 const Value *&SrcValue,
10195 int &SrcValueOffset,
10196 unsigned &SrcValueAlign,
10197 const MDNode *&TBAAInfo) const {
10198 LSBaseSDNode *LS = cast<LSBaseSDNode>(N);
10200 Ptr = LS->getBasePtr();
10201 Size = LS->getMemoryVT().getSizeInBits() >> 3;
10202 SrcValue = LS->getSrcValue();
10203 SrcValueOffset = LS->getSrcValueOffset();
10204 SrcValueAlign = LS->getOriginalAlignment();
10205 TBAAInfo = LS->getTBAAInfo();
10206 return isa<LoadSDNode>(LS);
10209 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
10210 /// looking for aliasing nodes and adding them to the Aliases vector.
10211 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
10212 SmallVector<SDValue, 8> &Aliases) {
10213 SmallVector<SDValue, 8> Chains; // List of chains to visit.
10214 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
10216 // Get alias information for node.
10219 const Value *SrcValue;
10220 int SrcValueOffset;
10221 unsigned SrcValueAlign;
10222 const MDNode *SrcTBAAInfo;
10223 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
10224 SrcValueAlign, SrcTBAAInfo);
10227 Chains.push_back(OriginalChain);
10228 unsigned Depth = 0;
10230 // Look at each chain and determine if it is an alias. If so, add it to the
10231 // aliases list. If not, then continue up the chain looking for the next
10233 while (!Chains.empty()) {
10234 SDValue Chain = Chains.back();
10237 // For TokenFactor nodes, look at each operand and only continue up the
10238 // chain until we find two aliases. If we've seen two aliases, assume we'll
10239 // find more and revert to original chain since the xform is unlikely to be
10242 // FIXME: The depth check could be made to return the last non-aliasing
10243 // chain we found before we hit a tokenfactor rather than the original
10245 if (Depth > 6 || Aliases.size() == 2) {
10247 Aliases.push_back(OriginalChain);
10251 // Don't bother if we've been before.
10252 if (!Visited.insert(Chain.getNode()))
10255 switch (Chain.getOpcode()) {
10256 case ISD::EntryToken:
10257 // Entry token is ideal chain operand, but handled in FindBetterChain.
10262 // Get alias information for Chain.
10265 const Value *OpSrcValue;
10266 int OpSrcValueOffset;
10267 unsigned OpSrcValueAlign;
10268 const MDNode *OpSrcTBAAInfo;
10269 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
10270 OpSrcValue, OpSrcValueOffset,
10274 // If chain is alias then stop here.
10275 if (!(IsLoad && IsOpLoad) &&
10276 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
10278 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
10279 OpSrcValueAlign, OpSrcTBAAInfo)) {
10280 Aliases.push_back(Chain);
10282 // Look further up the chain.
10283 Chains.push_back(Chain.getOperand(0));
10289 case ISD::TokenFactor:
10290 // We have to check each of the operands of the token factor for "small"
10291 // token factors, so we queue them up. Adding the operands to the queue
10292 // (stack) in reverse order maintains the original order and increases the
10293 // likelihood that getNode will find a matching token factor (CSE.)
10294 if (Chain.getNumOperands() > 16) {
10295 Aliases.push_back(Chain);
10298 for (unsigned n = Chain.getNumOperands(); n;)
10299 Chains.push_back(Chain.getOperand(--n));
10304 // For all other instructions we will just have to take what we can get.
10305 Aliases.push_back(Chain);
10311 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
10312 /// for a better chain (aliasing node.)
10313 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
10314 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
10316 // Accumulate all the aliases to this node.
10317 GatherAllAliases(N, OldChain, Aliases);
10319 // If no operands then chain to entry token.
10320 if (Aliases.size() == 0)
10321 return DAG.getEntryNode();
10323 // If a single operand then chain to it. We don't need to revisit it.
10324 if (Aliases.size() == 1)
10327 // Construct a custom tailored token factor.
10328 return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other,
10329 &Aliases[0], Aliases.size());
10332 // SelectionDAG::Combine - This is the entry point for the file.
10334 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
10335 CodeGenOpt::Level OptLevel) {
10336 /// run - This is the main entry point to this class.
10338 DAGCombiner(*this, AA, OptLevel).Run(Level);