1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: divide by zero is currently left unfolded. do we want to turn this
27 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "dagcombine"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/Analysis/AliasAnalysis.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Target/TargetLowering.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/Support/Compiler.h"
40 #include "llvm/Support/CommandLine.h"
44 STATISTIC(NodesCombined , "Number of dag nodes combined");
45 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
46 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
51 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
52 cl::desc("Pop up a window to show dags before the first "
55 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
56 cl::desc("Pop up a window to show dags before the second "
59 static const bool ViewDAGCombine1 = false;
60 static const bool ViewDAGCombine2 = false;
64 CombinerAA("combiner-alias-analysis", cl::Hidden,
65 cl::desc("Turn on alias analysis during testing"));
68 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
69 cl::desc("Include global information in alias analysis"));
71 //------------------------------ DAGCombiner ---------------------------------//
73 class VISIBILITY_HIDDEN DAGCombiner {
78 // Worklist of all of the nodes that need to be simplified.
79 std::vector<SDNode*> WorkList;
81 // AA - Used for DAG load/store alias analysis.
84 /// AddUsersToWorkList - When an instruction is simplified, add all users of
85 /// the instruction to the work lists because they might get more simplified
88 void AddUsersToWorkList(SDNode *N) {
89 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
94 /// removeFromWorkList - remove all instances of N from the worklist.
96 void removeFromWorkList(SDNode *N) {
97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
102 /// AddToWorkList - Add to the work list making sure it's instance is at the
103 /// the back (next to be processed.)
104 void AddToWorkList(SDNode *N) {
105 removeFromWorkList(N);
106 WorkList.push_back(N);
109 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
111 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
113 DOUT << "\nReplacing.1 "; DEBUG(N->dump());
114 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
115 DOUT << " and " << NumTo-1 << " other values\n";
116 std::vector<SDNode*> NowDead;
117 DAG.ReplaceAllUsesWith(N, To, &NowDead);
120 // Push the new nodes and any users onto the worklist
121 for (unsigned i = 0, e = NumTo; i != e; ++i) {
122 AddToWorkList(To[i].Val);
123 AddUsersToWorkList(To[i].Val);
127 // Nodes can be reintroduced into the worklist. Make sure we do not
128 // process a node that has been replaced.
129 removeFromWorkList(N);
130 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
131 removeFromWorkList(NowDead[i]);
133 // Finally, since the node is now dead, remove it from the graph.
135 return SDOperand(N, 0);
138 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
139 return CombineTo(N, &Res, 1, AddTo);
142 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
144 SDOperand To[] = { Res0, Res1 };
145 return CombineTo(N, To, 2, AddTo);
149 /// SimplifyDemandedBits - Check the specified integer node value to see if
150 /// it can be simplified or if things it uses can be simplified by bit
151 /// propagation. If so, return true.
152 bool SimplifyDemandedBits(SDOperand Op) {
153 TargetLowering::TargetLoweringOpt TLO(DAG);
154 uint64_t KnownZero, KnownOne;
155 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
156 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
160 AddToWorkList(Op.Val);
162 // Replace the old value with the new one.
164 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump());
165 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
168 std::vector<SDNode*> NowDead;
169 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
171 // Push the new node and any (possibly new) users onto the worklist.
172 AddToWorkList(TLO.New.Val);
173 AddUsersToWorkList(TLO.New.Val);
175 // Nodes can end up on the worklist more than once. Make sure we do
176 // not process a node that has been replaced.
177 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
178 removeFromWorkList(NowDead[i]);
180 // Finally, if the node is now dead, remove it from the graph. The node
181 // may not be dead if the replacement process recursively simplified to
182 // something else needing this node.
183 if (TLO.Old.Val->use_empty()) {
184 removeFromWorkList(TLO.Old.Val);
185 DAG.DeleteNode(TLO.Old.Val);
190 bool CombineToPreIndexedLoadStore(SDNode *N);
191 bool CombineToPostIndexedLoadStore(SDNode *N);
194 /// visit - call the node-specific routine that knows how to fold each
195 /// particular type of node.
196 SDOperand visit(SDNode *N);
198 // Visitation implementation - Implement dag node combining for different
199 // node types. The semantics are as follows:
201 // SDOperand.Val == 0 - No change was made
202 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
203 // otherwise - N should be replaced by the returned Operand.
205 SDOperand visitTokenFactor(SDNode *N);
206 SDOperand visitADD(SDNode *N);
207 SDOperand visitSUB(SDNode *N);
208 SDOperand visitADDC(SDNode *N);
209 SDOperand visitADDE(SDNode *N);
210 SDOperand visitMUL(SDNode *N);
211 SDOperand visitSDIV(SDNode *N);
212 SDOperand visitUDIV(SDNode *N);
213 SDOperand visitSREM(SDNode *N);
214 SDOperand visitUREM(SDNode *N);
215 SDOperand visitMULHU(SDNode *N);
216 SDOperand visitMULHS(SDNode *N);
217 SDOperand visitAND(SDNode *N);
218 SDOperand visitOR(SDNode *N);
219 SDOperand visitXOR(SDNode *N);
220 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp);
221 SDOperand visitSHL(SDNode *N);
222 SDOperand visitSRA(SDNode *N);
223 SDOperand visitSRL(SDNode *N);
224 SDOperand visitCTLZ(SDNode *N);
225 SDOperand visitCTTZ(SDNode *N);
226 SDOperand visitCTPOP(SDNode *N);
227 SDOperand visitSELECT(SDNode *N);
228 SDOperand visitSELECT_CC(SDNode *N);
229 SDOperand visitSETCC(SDNode *N);
230 SDOperand visitSIGN_EXTEND(SDNode *N);
231 SDOperand visitZERO_EXTEND(SDNode *N);
232 SDOperand visitANY_EXTEND(SDNode *N);
233 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
234 SDOperand visitTRUNCATE(SDNode *N);
235 SDOperand visitBIT_CONVERT(SDNode *N);
236 SDOperand visitVBIT_CONVERT(SDNode *N);
237 SDOperand visitFADD(SDNode *N);
238 SDOperand visitFSUB(SDNode *N);
239 SDOperand visitFMUL(SDNode *N);
240 SDOperand visitFDIV(SDNode *N);
241 SDOperand visitFREM(SDNode *N);
242 SDOperand visitFCOPYSIGN(SDNode *N);
243 SDOperand visitSINT_TO_FP(SDNode *N);
244 SDOperand visitUINT_TO_FP(SDNode *N);
245 SDOperand visitFP_TO_SINT(SDNode *N);
246 SDOperand visitFP_TO_UINT(SDNode *N);
247 SDOperand visitFP_ROUND(SDNode *N);
248 SDOperand visitFP_ROUND_INREG(SDNode *N);
249 SDOperand visitFP_EXTEND(SDNode *N);
250 SDOperand visitFNEG(SDNode *N);
251 SDOperand visitFABS(SDNode *N);
252 SDOperand visitBRCOND(SDNode *N);
253 SDOperand visitBR_CC(SDNode *N);
254 SDOperand visitLOAD(SDNode *N);
255 SDOperand visitSTORE(SDNode *N);
256 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
257 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
258 SDOperand visitVBUILD_VECTOR(SDNode *N);
259 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
260 SDOperand visitVVECTOR_SHUFFLE(SDNode *N);
262 SDOperand XformToShuffleWithZero(SDNode *N);
263 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
265 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
266 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
267 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
268 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
269 SDOperand N3, ISD::CondCode CC);
270 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
271 ISD::CondCode Cond, bool foldBooleans = true);
272 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType);
273 SDOperand BuildSDIV(SDNode *N);
274 SDOperand BuildUDIV(SDNode *N);
275 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
277 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
278 /// looking for aliasing nodes and adding them to the Aliases vector.
279 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
280 SmallVector<SDOperand, 8> &Aliases);
282 /// isAlias - Return true if there is any possibility that the two addresses
284 bool isAlias(SDOperand Ptr1, int64_t Size1,
285 const Value *SrcValue1, int SrcValueOffset1,
286 SDOperand Ptr2, int64_t Size2,
287 const Value *SrcValue2, int SrcValueOffset2);
289 /// FindAliasInfo - Extracts the relevant alias information from the memory
290 /// node. Returns true if the operand was a load.
291 bool FindAliasInfo(SDNode *N,
292 SDOperand &Ptr, int64_t &Size,
293 const Value *&SrcValue, int &SrcValueOffset);
295 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
296 /// looking for a better chain (aliasing node.)
297 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
300 DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
302 TLI(D.getTargetLoweringInfo()),
303 AfterLegalize(false),
306 /// Run - runs the dag combiner on all nodes in the work list
307 void Run(bool RunningAfterLegalize);
311 //===----------------------------------------------------------------------===//
312 // TargetLowering::DAGCombinerInfo implementation
313 //===----------------------------------------------------------------------===//
315 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
316 ((DAGCombiner*)DC)->AddToWorkList(N);
319 SDOperand TargetLowering::DAGCombinerInfo::
320 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
321 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
324 SDOperand TargetLowering::DAGCombinerInfo::
325 CombineTo(SDNode *N, SDOperand Res) {
326 return ((DAGCombiner*)DC)->CombineTo(N, Res);
330 SDOperand TargetLowering::DAGCombinerInfo::
331 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
332 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
338 //===----------------------------------------------------------------------===//
341 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
342 // that selects between the values 1 and 0, making it equivalent to a setcc.
343 // Also, set the incoming LHS, RHS, and CC references to the appropriate
344 // nodes based on the type of node we are checking. This simplifies life a
345 // bit for the callers.
346 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
348 if (N.getOpcode() == ISD::SETCC) {
349 LHS = N.getOperand(0);
350 RHS = N.getOperand(1);
351 CC = N.getOperand(2);
354 if (N.getOpcode() == ISD::SELECT_CC &&
355 N.getOperand(2).getOpcode() == ISD::Constant &&
356 N.getOperand(3).getOpcode() == ISD::Constant &&
357 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
358 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
359 LHS = N.getOperand(0);
360 RHS = N.getOperand(1);
361 CC = N.getOperand(4);
367 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
368 // one use. If this is true, it allows the users to invert the operation for
369 // free when it is profitable to do so.
370 static bool isOneUseSetCC(SDOperand N) {
371 SDOperand N0, N1, N2;
372 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
377 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
378 MVT::ValueType VT = N0.getValueType();
379 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
380 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
381 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
382 if (isa<ConstantSDNode>(N1)) {
383 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
384 AddToWorkList(OpNode.Val);
385 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
386 } else if (N0.hasOneUse()) {
387 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
388 AddToWorkList(OpNode.Val);
389 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
392 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
393 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
394 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
395 if (isa<ConstantSDNode>(N0)) {
396 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
397 AddToWorkList(OpNode.Val);
398 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
399 } else if (N1.hasOneUse()) {
400 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
401 AddToWorkList(OpNode.Val);
402 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
408 void DAGCombiner::Run(bool RunningAfterLegalize) {
409 // set the instance variable, so that the various visit routines may use it.
410 AfterLegalize = RunningAfterLegalize;
412 // Add all the dag nodes to the worklist.
413 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
414 E = DAG.allnodes_end(); I != E; ++I)
415 WorkList.push_back(I);
417 // Create a dummy node (which is not added to allnodes), that adds a reference
418 // to the root node, preventing it from being deleted, and tracking any
419 // changes of the root.
420 HandleSDNode Dummy(DAG.getRoot());
422 // The root of the dag may dangle to deleted nodes until the dag combiner is
423 // done. Set it to null to avoid confusion.
424 DAG.setRoot(SDOperand());
426 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
427 TargetLowering::DAGCombinerInfo
428 DagCombineInfo(DAG, !RunningAfterLegalize, false, this);
430 // while the worklist isn't empty, inspect the node on the end of it and
431 // try and combine it.
432 while (!WorkList.empty()) {
433 SDNode *N = WorkList.back();
436 // If N has no uses, it is dead. Make sure to revisit all N's operands once
437 // N is deleted from the DAG, since they too may now be dead or may have a
438 // reduced number of uses, allowing other xforms.
439 if (N->use_empty() && N != &Dummy) {
440 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
441 AddToWorkList(N->getOperand(i).Val);
447 SDOperand RV = visit(N);
449 // If nothing happened, try a target-specific DAG combine.
451 assert(N->getOpcode() != ISD::DELETED_NODE &&
452 "Node was deleted but visit returned NULL!");
453 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
454 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
455 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
460 // If we get back the same node we passed in, rather than a new node or
461 // zero, we know that the node must have defined multiple values and
462 // CombineTo was used. Since CombineTo takes care of the worklist
463 // mechanics for us, we have no work to do in this case.
465 assert(N->getOpcode() != ISD::DELETED_NODE &&
466 RV.Val->getOpcode() != ISD::DELETED_NODE &&
467 "Node was deleted but visit returned new node!");
469 DOUT << "\nReplacing.3 "; DEBUG(N->dump());
470 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
472 std::vector<SDNode*> NowDead;
473 if (N->getNumValues() == RV.Val->getNumValues())
474 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
476 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
478 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
481 // Push the new node and any users onto the worklist
482 AddToWorkList(RV.Val);
483 AddUsersToWorkList(RV.Val);
485 // Nodes can be reintroduced into the worklist. Make sure we do not
486 // process a node that has been replaced.
487 removeFromWorkList(N);
488 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
489 removeFromWorkList(NowDead[i]);
491 // Finally, since the node is now dead, remove it from the graph.
497 // If the root changed (e.g. it was a dead load, update the root).
498 DAG.setRoot(Dummy.getValue());
501 SDOperand DAGCombiner::visit(SDNode *N) {
502 switch(N->getOpcode()) {
504 case ISD::TokenFactor: return visitTokenFactor(N);
505 case ISD::ADD: return visitADD(N);
506 case ISD::SUB: return visitSUB(N);
507 case ISD::ADDC: return visitADDC(N);
508 case ISD::ADDE: return visitADDE(N);
509 case ISD::MUL: return visitMUL(N);
510 case ISD::SDIV: return visitSDIV(N);
511 case ISD::UDIV: return visitUDIV(N);
512 case ISD::SREM: return visitSREM(N);
513 case ISD::UREM: return visitUREM(N);
514 case ISD::MULHU: return visitMULHU(N);
515 case ISD::MULHS: return visitMULHS(N);
516 case ISD::AND: return visitAND(N);
517 case ISD::OR: return visitOR(N);
518 case ISD::XOR: return visitXOR(N);
519 case ISD::SHL: return visitSHL(N);
520 case ISD::SRA: return visitSRA(N);
521 case ISD::SRL: return visitSRL(N);
522 case ISD::CTLZ: return visitCTLZ(N);
523 case ISD::CTTZ: return visitCTTZ(N);
524 case ISD::CTPOP: return visitCTPOP(N);
525 case ISD::SELECT: return visitSELECT(N);
526 case ISD::SELECT_CC: return visitSELECT_CC(N);
527 case ISD::SETCC: return visitSETCC(N);
528 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
529 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
530 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
531 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
532 case ISD::TRUNCATE: return visitTRUNCATE(N);
533 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
534 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N);
535 case ISD::FADD: return visitFADD(N);
536 case ISD::FSUB: return visitFSUB(N);
537 case ISD::FMUL: return visitFMUL(N);
538 case ISD::FDIV: return visitFDIV(N);
539 case ISD::FREM: return visitFREM(N);
540 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
541 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
542 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
543 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
544 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
545 case ISD::FP_ROUND: return visitFP_ROUND(N);
546 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
547 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
548 case ISD::FNEG: return visitFNEG(N);
549 case ISD::FABS: return visitFABS(N);
550 case ISD::BRCOND: return visitBRCOND(N);
551 case ISD::BR_CC: return visitBR_CC(N);
552 case ISD::LOAD: return visitLOAD(N);
553 case ISD::STORE: return visitSTORE(N);
554 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
555 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
556 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N);
557 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
558 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N);
559 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD);
560 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB);
561 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL);
562 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV);
563 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV);
564 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND);
565 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR);
566 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR);
571 /// getInputChainForNode - Given a node, return its input chain if it has one,
572 /// otherwise return a null sd operand.
573 static SDOperand getInputChainForNode(SDNode *N) {
574 if (unsigned NumOps = N->getNumOperands()) {
575 if (N->getOperand(0).getValueType() == MVT::Other)
576 return N->getOperand(0);
577 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
578 return N->getOperand(NumOps-1);
579 for (unsigned i = 1; i < NumOps-1; ++i)
580 if (N->getOperand(i).getValueType() == MVT::Other)
581 return N->getOperand(i);
583 return SDOperand(0, 0);
586 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
587 // If N has two operands, where one has an input chain equal to the other,
588 // the 'other' chain is redundant.
589 if (N->getNumOperands() == 2) {
590 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
591 return N->getOperand(0);
592 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
593 return N->getOperand(1);
597 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
598 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
599 bool Changed = false; // If we should replace this token factor.
601 // Start out with this token factor.
604 // Iterate through token factors. The TFs grows when new token factors are
606 for (unsigned i = 0; i < TFs.size(); ++i) {
609 // Check each of the operands.
610 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
611 SDOperand Op = TF->getOperand(i);
613 switch (Op.getOpcode()) {
614 case ISD::EntryToken:
615 // Entry tokens don't need to be added to the list. They are
620 case ISD::TokenFactor:
621 if ((CombinerAA || Op.hasOneUse()) &&
622 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
623 // Queue up for processing.
624 TFs.push_back(Op.Val);
625 // Clean up in case the token factor is removed.
626 AddToWorkList(Op.Val);
633 // Only add if not there prior.
634 if (std::find(Ops.begin(), Ops.end(), Op) == Ops.end())
643 // If we've change things around then replace token factor.
645 if (Ops.size() == 0) {
646 // The entry token is the only possible outcome.
647 Result = DAG.getEntryNode();
649 // New and improved token factor.
650 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
653 // Don't add users to work list.
654 return CombineTo(N, Result, false);
661 SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
662 MVT::ValueType VT = N0.getValueType();
663 SDOperand N00 = N0.getOperand(0);
664 SDOperand N01 = N0.getOperand(1);
665 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
666 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
667 isa<ConstantSDNode>(N00.getOperand(1))) {
668 N0 = DAG.getNode(ISD::ADD, VT,
669 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01),
670 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01));
671 return DAG.getNode(ISD::ADD, VT, N0, N1);
676 SDOperand DAGCombiner::visitADD(SDNode *N) {
677 SDOperand N0 = N->getOperand(0);
678 SDOperand N1 = N->getOperand(1);
679 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
680 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
681 MVT::ValueType VT = N0.getValueType();
683 // fold (add c1, c2) -> c1+c2
685 return DAG.getNode(ISD::ADD, VT, N0, N1);
686 // canonicalize constant to RHS
688 return DAG.getNode(ISD::ADD, VT, N1, N0);
689 // fold (add x, 0) -> x
690 if (N1C && N1C->isNullValue())
692 // fold ((c1-A)+c2) -> (c1+c2)-A
693 if (N1C && N0.getOpcode() == ISD::SUB)
694 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
695 return DAG.getNode(ISD::SUB, VT,
696 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
699 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
702 // fold ((0-A) + B) -> B-A
703 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
704 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
705 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
706 // fold (A + (0-B)) -> A-B
707 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
708 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
709 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
710 // fold (A+(B-A)) -> B
711 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
712 return N1.getOperand(0);
714 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
715 return SDOperand(N, 0);
717 // fold (a+b) -> (a|b) iff a and b share no bits.
718 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
719 uint64_t LHSZero, LHSOne;
720 uint64_t RHSZero, RHSOne;
721 uint64_t Mask = MVT::getIntVTBitMask(VT);
722 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
724 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
726 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
727 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
728 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
729 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
730 return DAG.getNode(ISD::OR, VT, N0, N1);
734 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
735 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) {
736 SDOperand Result = combineShlAddConstant(N0, N1, DAG);
737 if (Result.Val) return Result;
739 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) {
740 SDOperand Result = combineShlAddConstant(N1, N0, DAG);
741 if (Result.Val) return Result;
747 SDOperand DAGCombiner::visitADDC(SDNode *N) {
748 SDOperand N0 = N->getOperand(0);
749 SDOperand N1 = N->getOperand(1);
750 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
751 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
752 MVT::ValueType VT = N0.getValueType();
754 // If the flag result is dead, turn this into an ADD.
755 if (N->hasNUsesOfValue(0, 1))
756 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0),
757 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
759 // canonicalize constant to RHS.
761 SDOperand Ops[] = { N1, N0 };
762 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
765 // fold (addc x, 0) -> x + no carry out
766 if (N1C && N1C->isNullValue())
767 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
769 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
770 uint64_t LHSZero, LHSOne;
771 uint64_t RHSZero, RHSOne;
772 uint64_t Mask = MVT::getIntVTBitMask(VT);
773 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
775 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
777 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
778 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
779 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
780 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
781 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1),
782 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
788 SDOperand DAGCombiner::visitADDE(SDNode *N) {
789 SDOperand N0 = N->getOperand(0);
790 SDOperand N1 = N->getOperand(1);
791 SDOperand CarryIn = N->getOperand(2);
792 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
793 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
794 //MVT::ValueType VT = N0.getValueType();
796 // canonicalize constant to RHS
798 SDOperand Ops[] = { N1, N0, CarryIn };
799 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3);
802 // fold (adde x, y, false) -> (addc x, y)
803 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) {
804 SDOperand Ops[] = { N1, N0 };
805 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
813 SDOperand DAGCombiner::visitSUB(SDNode *N) {
814 SDOperand N0 = N->getOperand(0);
815 SDOperand N1 = N->getOperand(1);
816 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
817 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
818 MVT::ValueType VT = N0.getValueType();
820 // fold (sub x, x) -> 0
822 return DAG.getConstant(0, N->getValueType(0));
823 // fold (sub c1, c2) -> c1-c2
825 return DAG.getNode(ISD::SUB, VT, N0, N1);
826 // fold (sub x, c) -> (add x, -c)
828 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
830 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
831 return N0.getOperand(1);
833 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
834 return N0.getOperand(0);
838 SDOperand DAGCombiner::visitMUL(SDNode *N) {
839 SDOperand N0 = N->getOperand(0);
840 SDOperand N1 = N->getOperand(1);
841 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
842 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
843 MVT::ValueType VT = N0.getValueType();
845 // fold (mul c1, c2) -> c1*c2
847 return DAG.getNode(ISD::MUL, VT, N0, N1);
848 // canonicalize constant to RHS
850 return DAG.getNode(ISD::MUL, VT, N1, N0);
851 // fold (mul x, 0) -> 0
852 if (N1C && N1C->isNullValue())
854 // fold (mul x, -1) -> 0-x
855 if (N1C && N1C->isAllOnesValue())
856 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
857 // fold (mul x, (1 << c)) -> x << c
858 if (N1C && isPowerOf2_64(N1C->getValue()))
859 return DAG.getNode(ISD::SHL, VT, N0,
860 DAG.getConstant(Log2_64(N1C->getValue()),
861 TLI.getShiftAmountTy()));
862 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
863 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
864 // FIXME: If the input is something that is easily negated (e.g. a
865 // single-use add), we should put the negate there.
866 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
867 DAG.getNode(ISD::SHL, VT, N0,
868 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
869 TLI.getShiftAmountTy())));
872 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
873 if (N1C && N0.getOpcode() == ISD::SHL &&
874 isa<ConstantSDNode>(N0.getOperand(1))) {
875 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
876 AddToWorkList(C3.Val);
877 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
880 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
883 SDOperand Sh(0,0), Y(0,0);
884 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
885 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
886 N0.Val->hasOneUse()) {
888 } else if (N1.getOpcode() == ISD::SHL &&
889 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
893 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
894 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
897 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
898 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
899 isa<ConstantSDNode>(N0.getOperand(1))) {
900 return DAG.getNode(ISD::ADD, VT,
901 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
902 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
906 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
912 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
913 SDOperand N0 = N->getOperand(0);
914 SDOperand N1 = N->getOperand(1);
915 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
916 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
917 MVT::ValueType VT = N->getValueType(0);
919 // fold (sdiv c1, c2) -> c1/c2
920 if (N0C && N1C && !N1C->isNullValue())
921 return DAG.getNode(ISD::SDIV, VT, N0, N1);
922 // fold (sdiv X, 1) -> X
923 if (N1C && N1C->getSignExtended() == 1LL)
925 // fold (sdiv X, -1) -> 0-X
926 if (N1C && N1C->isAllOnesValue())
927 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
928 // If we know the sign bits of both operands are zero, strength reduce to a
929 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
930 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
931 if (TLI.MaskedValueIsZero(N1, SignBit) &&
932 TLI.MaskedValueIsZero(N0, SignBit))
933 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
934 // fold (sdiv X, pow2) -> simple ops after legalize
935 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
936 (isPowerOf2_64(N1C->getSignExtended()) ||
937 isPowerOf2_64(-N1C->getSignExtended()))) {
938 // If dividing by powers of two is cheap, then don't perform the following
940 if (TLI.isPow2DivCheap())
942 int64_t pow2 = N1C->getSignExtended();
943 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
944 unsigned lg2 = Log2_64(abs2);
945 // Splat the sign bit into the register
946 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
947 DAG.getConstant(MVT::getSizeInBits(VT)-1,
948 TLI.getShiftAmountTy()));
949 AddToWorkList(SGN.Val);
950 // Add (N0 < 0) ? abs2 - 1 : 0;
951 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
952 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
953 TLI.getShiftAmountTy()));
954 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
955 AddToWorkList(SRL.Val);
956 AddToWorkList(ADD.Val); // Divide by pow2
957 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
958 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
959 // If we're dividing by a positive value, we're done. Otherwise, we must
960 // negate the result.
963 AddToWorkList(SRA.Val);
964 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
966 // if integer divide is expensive and we satisfy the requirements, emit an
967 // alternate sequence.
968 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
969 !TLI.isIntDivCheap()) {
970 SDOperand Op = BuildSDIV(N);
971 if (Op.Val) return Op;
976 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
977 SDOperand N0 = N->getOperand(0);
978 SDOperand N1 = N->getOperand(1);
979 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
980 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
981 MVT::ValueType VT = N->getValueType(0);
983 // fold (udiv c1, c2) -> c1/c2
984 if (N0C && N1C && !N1C->isNullValue())
985 return DAG.getNode(ISD::UDIV, VT, N0, N1);
986 // fold (udiv x, (1 << c)) -> x >>u c
987 if (N1C && isPowerOf2_64(N1C->getValue()))
988 return DAG.getNode(ISD::SRL, VT, N0,
989 DAG.getConstant(Log2_64(N1C->getValue()),
990 TLI.getShiftAmountTy()));
991 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
992 if (N1.getOpcode() == ISD::SHL) {
993 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
994 if (isPowerOf2_64(SHC->getValue())) {
995 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
996 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
997 DAG.getConstant(Log2_64(SHC->getValue()),
999 AddToWorkList(Add.Val);
1000 return DAG.getNode(ISD::SRL, VT, N0, Add);
1004 // fold (udiv x, c) -> alternate
1005 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
1006 SDOperand Op = BuildUDIV(N);
1007 if (Op.Val) return Op;
1012 SDOperand DAGCombiner::visitSREM(SDNode *N) {
1013 SDOperand N0 = N->getOperand(0);
1014 SDOperand N1 = N->getOperand(1);
1015 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1016 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1017 MVT::ValueType VT = N->getValueType(0);
1019 // fold (srem c1, c2) -> c1%c2
1020 if (N0C && N1C && !N1C->isNullValue())
1021 return DAG.getNode(ISD::SREM, VT, N0, N1);
1022 // If we know the sign bits of both operands are zero, strength reduce to a
1023 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1024 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1025 if (TLI.MaskedValueIsZero(N1, SignBit) &&
1026 TLI.MaskedValueIsZero(N0, SignBit))
1027 return DAG.getNode(ISD::UREM, VT, N0, N1);
1029 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
1030 // the remainder operation.
1031 if (N1C && !N1C->isNullValue()) {
1032 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
1033 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
1034 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1035 AddToWorkList(Div.Val);
1036 AddToWorkList(Mul.Val);
1043 SDOperand DAGCombiner::visitUREM(SDNode *N) {
1044 SDOperand N0 = N->getOperand(0);
1045 SDOperand N1 = N->getOperand(1);
1046 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1047 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1048 MVT::ValueType VT = N->getValueType(0);
1050 // fold (urem c1, c2) -> c1%c2
1051 if (N0C && N1C && !N1C->isNullValue())
1052 return DAG.getNode(ISD::UREM, VT, N0, N1);
1053 // fold (urem x, pow2) -> (and x, pow2-1)
1054 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
1055 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
1056 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1057 if (N1.getOpcode() == ISD::SHL) {
1058 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1059 if (isPowerOf2_64(SHC->getValue())) {
1060 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
1061 AddToWorkList(Add.Val);
1062 return DAG.getNode(ISD::AND, VT, N0, Add);
1067 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
1068 // the remainder operation.
1069 if (N1C && !N1C->isNullValue()) {
1070 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
1071 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
1072 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1073 AddToWorkList(Div.Val);
1074 AddToWorkList(Mul.Val);
1081 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
1082 SDOperand N0 = N->getOperand(0);
1083 SDOperand N1 = N->getOperand(1);
1084 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1086 // fold (mulhs x, 0) -> 0
1087 if (N1C && N1C->isNullValue())
1089 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1090 if (N1C && N1C->getValue() == 1)
1091 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
1092 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
1093 TLI.getShiftAmountTy()));
1097 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
1098 SDOperand N0 = N->getOperand(0);
1099 SDOperand N1 = N->getOperand(1);
1100 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1102 // fold (mulhu x, 0) -> 0
1103 if (N1C && N1C->isNullValue())
1105 // fold (mulhu x, 1) -> 0
1106 if (N1C && N1C->getValue() == 1)
1107 return DAG.getConstant(0, N0.getValueType());
1111 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1112 /// two operands of the same opcode, try to simplify it.
1113 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1114 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
1115 MVT::ValueType VT = N0.getValueType();
1116 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1118 // For each of OP in AND/OR/XOR:
1119 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1120 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1121 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1122 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1123 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1124 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1125 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1126 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1127 N0.getOperand(0).getValueType(),
1128 N0.getOperand(0), N1.getOperand(0));
1129 AddToWorkList(ORNode.Val);
1130 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1133 // For each of OP in SHL/SRL/SRA/AND...
1134 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1135 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1136 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1137 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1138 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1139 N0.getOperand(1) == N1.getOperand(1)) {
1140 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1141 N0.getOperand(0).getValueType(),
1142 N0.getOperand(0), N1.getOperand(0));
1143 AddToWorkList(ORNode.Val);
1144 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1150 SDOperand DAGCombiner::visitAND(SDNode *N) {
1151 SDOperand N0 = N->getOperand(0);
1152 SDOperand N1 = N->getOperand(1);
1153 SDOperand LL, LR, RL, RR, CC0, CC1;
1154 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1155 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1156 MVT::ValueType VT = N1.getValueType();
1158 // fold (and c1, c2) -> c1&c2
1160 return DAG.getNode(ISD::AND, VT, N0, N1);
1161 // canonicalize constant to RHS
1163 return DAG.getNode(ISD::AND, VT, N1, N0);
1164 // fold (and x, -1) -> x
1165 if (N1C && N1C->isAllOnesValue())
1167 // if (and x, c) is known to be zero, return 0
1168 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1169 return DAG.getConstant(0, VT);
1171 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1174 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1175 if (N1C && N0.getOpcode() == ISD::OR)
1176 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1177 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1179 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1180 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1181 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1182 if (TLI.MaskedValueIsZero(N0.getOperand(0),
1183 ~N1C->getValue() & InMask)) {
1184 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1187 // Replace uses of the AND with uses of the Zero extend node.
1190 // We actually want to replace all uses of the any_extend with the
1191 // zero_extend, to avoid duplicating things. This will later cause this
1192 // AND to be folded.
1193 CombineTo(N0.Val, Zext);
1194 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1197 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1198 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1199 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1200 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1202 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1203 MVT::isInteger(LL.getValueType())) {
1204 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1205 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1206 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1207 AddToWorkList(ORNode.Val);
1208 return DAG.getSetCC(VT, ORNode, LR, Op1);
1210 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1211 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1212 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1213 AddToWorkList(ANDNode.Val);
1214 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1216 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1217 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1218 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1219 AddToWorkList(ORNode.Val);
1220 return DAG.getSetCC(VT, ORNode, LR, Op1);
1223 // canonicalize equivalent to ll == rl
1224 if (LL == RR && LR == RL) {
1225 Op1 = ISD::getSetCCSwappedOperands(Op1);
1228 if (LL == RL && LR == RR) {
1229 bool isInteger = MVT::isInteger(LL.getValueType());
1230 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1231 if (Result != ISD::SETCC_INVALID)
1232 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1236 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1237 if (N0.getOpcode() == N1.getOpcode()) {
1238 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1239 if (Tmp.Val) return Tmp;
1242 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1243 // fold (and (sra)) -> (and (srl)) when possible.
1244 if (!MVT::isVector(VT) &&
1245 SimplifyDemandedBits(SDOperand(N, 0)))
1246 return SDOperand(N, 0);
1247 // fold (zext_inreg (extload x)) -> (zextload x)
1248 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
1249 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1250 MVT::ValueType EVT = LN0->getLoadedVT();
1251 // If we zero all the possible extended bits, then we can turn this into
1252 // a zextload if we are running before legalize or the operation is legal.
1253 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1254 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1255 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1256 LN0->getBasePtr(), LN0->getSrcValue(),
1257 LN0->getSrcValueOffset(), EVT);
1259 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1260 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1263 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1264 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
1266 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1267 MVT::ValueType EVT = LN0->getLoadedVT();
1268 // If we zero all the possible extended bits, then we can turn this into
1269 // a zextload if we are running before legalize or the operation is legal.
1270 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1271 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1272 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1273 LN0->getBasePtr(), LN0->getSrcValue(),
1274 LN0->getSrcValueOffset(), EVT);
1276 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1277 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1281 // fold (and (load x), 255) -> (zextload x, i8)
1282 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1283 if (N1C && N0.getOpcode() == ISD::LOAD) {
1284 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1285 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1286 LN0->getAddressingMode() == ISD::UNINDEXED &&
1288 MVT::ValueType EVT, LoadedVT;
1289 if (N1C->getValue() == 255)
1291 else if (N1C->getValue() == 65535)
1293 else if (N1C->getValue() == ~0U)
1298 LoadedVT = LN0->getLoadedVT();
1299 if (EVT != MVT::Other && LoadedVT > EVT &&
1300 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1301 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1302 // For big endian targets, we need to add an offset to the pointer to
1303 // load the correct bytes. For little endian systems, we merely need to
1304 // read fewer bytes from the same pointer.
1306 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1307 SDOperand NewPtr = LN0->getBasePtr();
1308 if (!TLI.isLittleEndian())
1309 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1310 DAG.getConstant(PtrOff, PtrType));
1311 AddToWorkList(NewPtr.Val);
1313 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1314 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT);
1316 CombineTo(N0.Val, Load, Load.getValue(1));
1317 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1325 SDOperand DAGCombiner::visitOR(SDNode *N) {
1326 SDOperand N0 = N->getOperand(0);
1327 SDOperand N1 = N->getOperand(1);
1328 SDOperand LL, LR, RL, RR, CC0, CC1;
1329 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1330 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1331 MVT::ValueType VT = N1.getValueType();
1332 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1334 // fold (or c1, c2) -> c1|c2
1336 return DAG.getNode(ISD::OR, VT, N0, N1);
1337 // canonicalize constant to RHS
1339 return DAG.getNode(ISD::OR, VT, N1, N0);
1340 // fold (or x, 0) -> x
1341 if (N1C && N1C->isNullValue())
1343 // fold (or x, -1) -> -1
1344 if (N1C && N1C->isAllOnesValue())
1346 // fold (or x, c) -> c iff (x & ~c) == 0
1348 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1351 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1354 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1355 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1356 isa<ConstantSDNode>(N0.getOperand(1))) {
1357 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1358 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1360 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1362 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1363 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1364 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1365 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1367 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1368 MVT::isInteger(LL.getValueType())) {
1369 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1370 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1371 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1372 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1373 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1374 AddToWorkList(ORNode.Val);
1375 return DAG.getSetCC(VT, ORNode, LR, Op1);
1377 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1378 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1379 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1380 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1381 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1382 AddToWorkList(ANDNode.Val);
1383 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1386 // canonicalize equivalent to ll == rl
1387 if (LL == RR && LR == RL) {
1388 Op1 = ISD::getSetCCSwappedOperands(Op1);
1391 if (LL == RL && LR == RR) {
1392 bool isInteger = MVT::isInteger(LL.getValueType());
1393 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1394 if (Result != ISD::SETCC_INVALID)
1395 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1399 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1400 if (N0.getOpcode() == N1.getOpcode()) {
1401 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1402 if (Tmp.Val) return Tmp;
1405 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1406 if (N0.getOpcode() == ISD::AND &&
1407 N1.getOpcode() == ISD::AND &&
1408 N0.getOperand(1).getOpcode() == ISD::Constant &&
1409 N1.getOperand(1).getOpcode() == ISD::Constant &&
1410 // Don't increase # computations.
1411 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1412 // We can only do this xform if we know that bits from X that are set in C2
1413 // but not in C1 are already zero. Likewise for Y.
1414 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1415 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1417 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1418 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1419 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1420 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1425 // See if this is some rotate idiom.
1426 if (SDNode *Rot = MatchRotate(N0, N1))
1427 return SDOperand(Rot, 0);
1433 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1434 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1435 if (Op.getOpcode() == ISD::AND) {
1436 if (isa<ConstantSDNode>(Op.getOperand(1))) {
1437 Mask = Op.getOperand(1);
1438 Op = Op.getOperand(0);
1444 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1452 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1453 // idioms for rotate, and if the target supports rotation instructions, generate
1455 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1456 // Must be a legal type. Expanded an promoted things won't work with rotates.
1457 MVT::ValueType VT = LHS.getValueType();
1458 if (!TLI.isTypeLegal(VT)) return 0;
1460 // The target must have at least one rotate flavor.
1461 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1462 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1463 if (!HasROTL && !HasROTR) return 0;
1465 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1466 SDOperand LHSShift; // The shift.
1467 SDOperand LHSMask; // AND value if any.
1468 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1469 return 0; // Not part of a rotate.
1471 SDOperand RHSShift; // The shift.
1472 SDOperand RHSMask; // AND value if any.
1473 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1474 return 0; // Not part of a rotate.
1476 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1477 return 0; // Not shifting the same value.
1479 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1480 return 0; // Shifts must disagree.
1482 // Canonicalize shl to left side in a shl/srl pair.
1483 if (RHSShift.getOpcode() == ISD::SHL) {
1484 std::swap(LHS, RHS);
1485 std::swap(LHSShift, RHSShift);
1486 std::swap(LHSMask , RHSMask );
1489 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1491 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1492 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1493 if (LHSShift.getOperand(1).getOpcode() == ISD::Constant &&
1494 RHSShift.getOperand(1).getOpcode() == ISD::Constant) {
1495 uint64_t LShVal = cast<ConstantSDNode>(LHSShift.getOperand(1))->getValue();
1496 uint64_t RShVal = cast<ConstantSDNode>(RHSShift.getOperand(1))->getValue();
1497 if ((LShVal + RShVal) != OpSizeInBits)
1502 Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1503 LHSShift.getOperand(1));
1505 Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1506 RHSShift.getOperand(1));
1508 // If there is an AND of either shifted operand, apply it to the result.
1509 if (LHSMask.Val || RHSMask.Val) {
1510 uint64_t Mask = MVT::getIntVTBitMask(VT);
1513 uint64_t RHSBits = (1ULL << LShVal)-1;
1514 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1517 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1518 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1521 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1527 // If there is a mask here, and we have a variable shift, we can't be sure
1528 // that we're masking out the right stuff.
1529 if (LHSMask.Val || RHSMask.Val)
1532 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1533 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1534 if (RHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1535 LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) {
1536 if (ConstantSDNode *SUBC =
1537 dyn_cast<ConstantSDNode>(RHSShift.getOperand(1).getOperand(0))) {
1538 if (SUBC->getValue() == OpSizeInBits)
1540 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1541 LHSShift.getOperand(1)).Val;
1543 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1544 LHSShift.getOperand(1)).Val;
1548 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1549 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1550 if (LHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1551 RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) {
1552 if (ConstantSDNode *SUBC =
1553 dyn_cast<ConstantSDNode>(LHSShift.getOperand(1).getOperand(0))) {
1554 if (SUBC->getValue() == OpSizeInBits)
1556 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1557 LHSShift.getOperand(1)).Val;
1559 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1560 RHSShift.getOperand(1)).Val;
1568 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1569 SDOperand N0 = N->getOperand(0);
1570 SDOperand N1 = N->getOperand(1);
1571 SDOperand LHS, RHS, CC;
1572 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1573 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1574 MVT::ValueType VT = N0.getValueType();
1576 // fold (xor c1, c2) -> c1^c2
1578 return DAG.getNode(ISD::XOR, VT, N0, N1);
1579 // canonicalize constant to RHS
1581 return DAG.getNode(ISD::XOR, VT, N1, N0);
1582 // fold (xor x, 0) -> x
1583 if (N1C && N1C->isNullValue())
1586 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1589 // fold !(x cc y) -> (x !cc y)
1590 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1591 bool isInt = MVT::isInteger(LHS.getValueType());
1592 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1594 if (N0.getOpcode() == ISD::SETCC)
1595 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1596 if (N0.getOpcode() == ISD::SELECT_CC)
1597 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1598 assert(0 && "Unhandled SetCC Equivalent!");
1601 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1602 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 &&
1603 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1604 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1605 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1606 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1607 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1608 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1609 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1610 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1613 // fold !(x or y) -> (!x and !y) iff x or y are constants
1614 if (N1C && N1C->isAllOnesValue() &&
1615 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1616 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1617 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1618 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1619 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1620 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1621 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1622 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1625 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1626 if (N1C && N0.getOpcode() == ISD::XOR) {
1627 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1628 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1630 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1631 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1633 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1634 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1636 // fold (xor x, x) -> 0
1638 if (!MVT::isVector(VT)) {
1639 return DAG.getConstant(0, VT);
1640 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1641 // Produce a vector of zeros.
1642 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
1643 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
1644 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1648 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
1649 if (N0.getOpcode() == N1.getOpcode()) {
1650 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1651 if (Tmp.Val) return Tmp;
1654 // Simplify the expression using non-local knowledge.
1655 if (!MVT::isVector(VT) &&
1656 SimplifyDemandedBits(SDOperand(N, 0)))
1657 return SDOperand(N, 0);
1662 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1663 SDOperand N0 = N->getOperand(0);
1664 SDOperand N1 = N->getOperand(1);
1665 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1666 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1667 MVT::ValueType VT = N0.getValueType();
1668 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1670 // fold (shl c1, c2) -> c1<<c2
1672 return DAG.getNode(ISD::SHL, VT, N0, N1);
1673 // fold (shl 0, x) -> 0
1674 if (N0C && N0C->isNullValue())
1676 // fold (shl x, c >= size(x)) -> undef
1677 if (N1C && N1C->getValue() >= OpSizeInBits)
1678 return DAG.getNode(ISD::UNDEF, VT);
1679 // fold (shl x, 0) -> x
1680 if (N1C && N1C->isNullValue())
1682 // if (shl x, c) is known to be zero, return 0
1683 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1684 return DAG.getConstant(0, VT);
1685 if (SimplifyDemandedBits(SDOperand(N, 0)))
1686 return SDOperand(N, 0);
1687 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1688 if (N1C && N0.getOpcode() == ISD::SHL &&
1689 N0.getOperand(1).getOpcode() == ISD::Constant) {
1690 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1691 uint64_t c2 = N1C->getValue();
1692 if (c1 + c2 > OpSizeInBits)
1693 return DAG.getConstant(0, VT);
1694 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1695 DAG.getConstant(c1 + c2, N1.getValueType()));
1697 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1698 // (srl (and x, -1 << c1), c1-c2)
1699 if (N1C && N0.getOpcode() == ISD::SRL &&
1700 N0.getOperand(1).getOpcode() == ISD::Constant) {
1701 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1702 uint64_t c2 = N1C->getValue();
1703 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1704 DAG.getConstant(~0ULL << c1, VT));
1706 return DAG.getNode(ISD::SHL, VT, Mask,
1707 DAG.getConstant(c2-c1, N1.getValueType()));
1709 return DAG.getNode(ISD::SRL, VT, Mask,
1710 DAG.getConstant(c1-c2, N1.getValueType()));
1712 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1713 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1714 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1715 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1719 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1720 SDOperand N0 = N->getOperand(0);
1721 SDOperand N1 = N->getOperand(1);
1722 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1723 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1724 MVT::ValueType VT = N0.getValueType();
1726 // fold (sra c1, c2) -> c1>>c2
1728 return DAG.getNode(ISD::SRA, VT, N0, N1);
1729 // fold (sra 0, x) -> 0
1730 if (N0C && N0C->isNullValue())
1732 // fold (sra -1, x) -> -1
1733 if (N0C && N0C->isAllOnesValue())
1735 // fold (sra x, c >= size(x)) -> undef
1736 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
1737 return DAG.getNode(ISD::UNDEF, VT);
1738 // fold (sra x, 0) -> x
1739 if (N1C && N1C->isNullValue())
1741 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
1743 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
1744 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
1747 default: EVT = MVT::Other; break;
1748 case 1: EVT = MVT::i1; break;
1749 case 8: EVT = MVT::i8; break;
1750 case 16: EVT = MVT::i16; break;
1751 case 32: EVT = MVT::i32; break;
1753 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
1754 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1755 DAG.getValueType(EVT));
1758 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
1759 if (N1C && N0.getOpcode() == ISD::SRA) {
1760 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1761 unsigned Sum = N1C->getValue() + C1->getValue();
1762 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
1763 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
1764 DAG.getConstant(Sum, N1C->getValueType(0)));
1768 // Simplify, based on bits shifted out of the LHS.
1769 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
1770 return SDOperand(N, 0);
1773 // If the sign bit is known to be zero, switch this to a SRL.
1774 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
1775 return DAG.getNode(ISD::SRL, VT, N0, N1);
1779 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1780 SDOperand N0 = N->getOperand(0);
1781 SDOperand N1 = N->getOperand(1);
1782 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1783 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1784 MVT::ValueType VT = N0.getValueType();
1785 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1787 // fold (srl c1, c2) -> c1 >>u c2
1789 return DAG.getNode(ISD::SRL, VT, N0, N1);
1790 // fold (srl 0, x) -> 0
1791 if (N0C && N0C->isNullValue())
1793 // fold (srl x, c >= size(x)) -> undef
1794 if (N1C && N1C->getValue() >= OpSizeInBits)
1795 return DAG.getNode(ISD::UNDEF, VT);
1796 // fold (srl x, 0) -> x
1797 if (N1C && N1C->isNullValue())
1799 // if (srl x, c) is known to be zero, return 0
1800 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1801 return DAG.getConstant(0, VT);
1802 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1803 if (N1C && N0.getOpcode() == ISD::SRL &&
1804 N0.getOperand(1).getOpcode() == ISD::Constant) {
1805 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1806 uint64_t c2 = N1C->getValue();
1807 if (c1 + c2 > OpSizeInBits)
1808 return DAG.getConstant(0, VT);
1809 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1810 DAG.getConstant(c1 + c2, N1.getValueType()));
1813 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
1814 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1815 // Shifting in all undef bits?
1816 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
1817 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
1818 return DAG.getNode(ISD::UNDEF, VT);
1820 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
1821 AddToWorkList(SmallShift.Val);
1822 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
1825 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
1826 // bit, which is unmodified by sra.
1827 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
1828 if (N0.getOpcode() == ISD::SRA)
1829 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
1832 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
1833 if (N1C && N0.getOpcode() == ISD::CTLZ &&
1834 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
1835 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
1836 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
1838 // If any of the input bits are KnownOne, then the input couldn't be all
1839 // zeros, thus the result of the srl will always be zero.
1840 if (KnownOne) return DAG.getConstant(0, VT);
1842 // If all of the bits input the to ctlz node are known to be zero, then
1843 // the result of the ctlz is "32" and the result of the shift is one.
1844 uint64_t UnknownBits = ~KnownZero & Mask;
1845 if (UnknownBits == 0) return DAG.getConstant(1, VT);
1847 // Otherwise, check to see if there is exactly one bit input to the ctlz.
1848 if ((UnknownBits & (UnknownBits-1)) == 0) {
1849 // Okay, we know that only that the single bit specified by UnknownBits
1850 // could be set on input to the CTLZ node. If this bit is set, the SRL
1851 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
1852 // to an SRL,XOR pair, which is likely to simplify more.
1853 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
1854 SDOperand Op = N0.getOperand(0);
1856 Op = DAG.getNode(ISD::SRL, VT, Op,
1857 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
1858 AddToWorkList(Op.Val);
1860 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
1867 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1868 SDOperand N0 = N->getOperand(0);
1869 MVT::ValueType VT = N->getValueType(0);
1871 // fold (ctlz c1) -> c2
1872 if (isa<ConstantSDNode>(N0))
1873 return DAG.getNode(ISD::CTLZ, VT, N0);
1877 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1878 SDOperand N0 = N->getOperand(0);
1879 MVT::ValueType VT = N->getValueType(0);
1881 // fold (cttz c1) -> c2
1882 if (isa<ConstantSDNode>(N0))
1883 return DAG.getNode(ISD::CTTZ, VT, N0);
1887 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1888 SDOperand N0 = N->getOperand(0);
1889 MVT::ValueType VT = N->getValueType(0);
1891 // fold (ctpop c1) -> c2
1892 if (isa<ConstantSDNode>(N0))
1893 return DAG.getNode(ISD::CTPOP, VT, N0);
1897 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1898 SDOperand N0 = N->getOperand(0);
1899 SDOperand N1 = N->getOperand(1);
1900 SDOperand N2 = N->getOperand(2);
1901 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1902 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1903 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1904 MVT::ValueType VT = N->getValueType(0);
1906 // fold select C, X, X -> X
1909 // fold select true, X, Y -> X
1910 if (N0C && !N0C->isNullValue())
1912 // fold select false, X, Y -> Y
1913 if (N0C && N0C->isNullValue())
1915 // fold select C, 1, X -> C | X
1916 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1917 return DAG.getNode(ISD::OR, VT, N0, N2);
1918 // fold select C, 0, X -> ~C & X
1919 // FIXME: this should check for C type == X type, not i1?
1920 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1921 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1922 AddToWorkList(XORNode.Val);
1923 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1925 // fold select C, X, 1 -> ~C | X
1926 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1927 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1928 AddToWorkList(XORNode.Val);
1929 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1931 // fold select C, X, 0 -> C & X
1932 // FIXME: this should check for C type == X type, not i1?
1933 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1934 return DAG.getNode(ISD::AND, VT, N0, N1);
1935 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1936 if (MVT::i1 == VT && N0 == N1)
1937 return DAG.getNode(ISD::OR, VT, N0, N2);
1938 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1939 if (MVT::i1 == VT && N0 == N2)
1940 return DAG.getNode(ISD::AND, VT, N0, N1);
1942 // If we can fold this based on the true/false value, do so.
1943 if (SimplifySelectOps(N, N1, N2))
1944 return SDOperand(N, 0); // Don't revisit N.
1946 // fold selects based on a setcc into other things, such as min/max/abs
1947 if (N0.getOpcode() == ISD::SETCC)
1949 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1950 // having to say they don't support SELECT_CC on every type the DAG knows
1951 // about, since there is no way to mark an opcode illegal at all value types
1952 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1953 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1954 N1, N2, N0.getOperand(2));
1956 return SimplifySelect(N0, N1, N2);
1960 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1961 SDOperand N0 = N->getOperand(0);
1962 SDOperand N1 = N->getOperand(1);
1963 SDOperand N2 = N->getOperand(2);
1964 SDOperand N3 = N->getOperand(3);
1965 SDOperand N4 = N->getOperand(4);
1966 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1968 // fold select_cc lhs, rhs, x, x, cc -> x
1972 // Determine if the condition we're dealing with is constant
1973 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1974 if (SCC.Val) AddToWorkList(SCC.Val);
1976 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
1977 if (SCCC->getValue())
1978 return N2; // cond always true -> true val
1980 return N3; // cond always false -> false val
1983 // Fold to a simpler select_cc
1984 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
1985 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
1986 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
1989 // If we can fold this based on the true/false value, do so.
1990 if (SimplifySelectOps(N, N2, N3))
1991 return SDOperand(N, 0); // Don't revisit N.
1993 // fold select_cc into other things, such as min/max/abs
1994 return SimplifySelectCC(N0, N1, N2, N3, CC);
1997 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1998 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1999 cast<CondCodeSDNode>(N->getOperand(2))->get());
2002 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
2003 SDOperand N0 = N->getOperand(0);
2004 MVT::ValueType VT = N->getValueType(0);
2006 // fold (sext c1) -> c1
2007 if (isa<ConstantSDNode>(N0))
2008 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
2010 // fold (sext (sext x)) -> (sext x)
2011 // fold (sext (aext x)) -> (sext x)
2012 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2013 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
2015 if (N0.getOpcode() == ISD::TRUNCATE) {
2016 // See if the value being truncated is already sign extended. If so, just
2017 // eliminate the trunc/sext pair.
2018 SDOperand Op = N0.getOperand(0);
2019 unsigned OpBits = MVT::getSizeInBits(Op.getValueType());
2020 unsigned MidBits = MVT::getSizeInBits(N0.getValueType());
2021 unsigned DestBits = MVT::getSizeInBits(VT);
2022 unsigned NumSignBits = TLI.ComputeNumSignBits(Op);
2024 if (OpBits == DestBits) {
2025 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
2026 // bits, it is already ready.
2027 if (NumSignBits > DestBits-MidBits)
2029 } else if (OpBits < DestBits) {
2030 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
2031 // bits, just sext from i32.
2032 if (NumSignBits > OpBits-MidBits)
2033 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op);
2035 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
2036 // bits, just truncate to i32.
2037 if (NumSignBits > OpBits-MidBits)
2038 return DAG.getNode(ISD::TRUNCATE, VT, Op);
2041 // fold (sext (truncate x)) -> (sextinreg x).
2042 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
2043 N0.getValueType())) {
2044 if (Op.getValueType() < VT)
2045 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2046 else if (Op.getValueType() > VT)
2047 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2048 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
2049 DAG.getValueType(N0.getValueType()));
2053 // fold (sext (load x)) -> (sext (truncate (sextload x)))
2054 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2055 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
2056 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2057 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2058 LN0->getBasePtr(), LN0->getSrcValue(),
2059 LN0->getSrcValueOffset(),
2061 CombineTo(N, ExtLoad);
2062 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2063 ExtLoad.getValue(1));
2064 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2067 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
2068 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
2069 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2070 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2071 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2072 MVT::ValueType EVT = LN0->getLoadedVT();
2073 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
2074 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2075 LN0->getBasePtr(), LN0->getSrcValue(),
2076 LN0->getSrcValueOffset(), EVT);
2077 CombineTo(N, ExtLoad);
2078 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2079 ExtLoad.getValue(1));
2080 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2087 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
2088 SDOperand N0 = N->getOperand(0);
2089 MVT::ValueType VT = N->getValueType(0);
2091 // fold (zext c1) -> c1
2092 if (isa<ConstantSDNode>(N0))
2093 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2094 // fold (zext (zext x)) -> (zext x)
2095 // fold (zext (aext x)) -> (zext x)
2096 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2097 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
2099 // fold (zext (truncate x)) -> (and x, mask)
2100 if (N0.getOpcode() == ISD::TRUNCATE &&
2101 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
2102 SDOperand Op = N0.getOperand(0);
2103 if (Op.getValueType() < VT) {
2104 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2105 } else if (Op.getValueType() > VT) {
2106 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2108 return DAG.getZeroExtendInReg(Op, N0.getValueType());
2111 // fold (zext (and (trunc x), cst)) -> (and x, cst).
2112 if (N0.getOpcode() == ISD::AND &&
2113 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2114 N0.getOperand(1).getOpcode() == ISD::Constant) {
2115 SDOperand X = N0.getOperand(0).getOperand(0);
2116 if (X.getValueType() < VT) {
2117 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2118 } else if (X.getValueType() > VT) {
2119 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2121 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2122 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2125 // fold (zext (load x)) -> (zext (truncate (zextload x)))
2126 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2127 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
2128 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2129 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2130 LN0->getBasePtr(), LN0->getSrcValue(),
2131 LN0->getSrcValueOffset(),
2133 CombineTo(N, ExtLoad);
2134 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2135 ExtLoad.getValue(1));
2136 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2139 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
2140 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
2141 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2142 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2143 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2144 MVT::ValueType EVT = LN0->getLoadedVT();
2145 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2146 LN0->getBasePtr(), LN0->getSrcValue(),
2147 LN0->getSrcValueOffset(), EVT);
2148 CombineTo(N, ExtLoad);
2149 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2150 ExtLoad.getValue(1));
2151 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2156 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
2157 SDOperand N0 = N->getOperand(0);
2158 MVT::ValueType VT = N->getValueType(0);
2160 // fold (aext c1) -> c1
2161 if (isa<ConstantSDNode>(N0))
2162 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
2163 // fold (aext (aext x)) -> (aext x)
2164 // fold (aext (zext x)) -> (zext x)
2165 // fold (aext (sext x)) -> (sext x)
2166 if (N0.getOpcode() == ISD::ANY_EXTEND ||
2167 N0.getOpcode() == ISD::ZERO_EXTEND ||
2168 N0.getOpcode() == ISD::SIGN_EXTEND)
2169 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2171 // fold (aext (truncate x))
2172 if (N0.getOpcode() == ISD::TRUNCATE) {
2173 SDOperand TruncOp = N0.getOperand(0);
2174 if (TruncOp.getValueType() == VT)
2175 return TruncOp; // x iff x size == zext size.
2176 if (TruncOp.getValueType() > VT)
2177 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
2178 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
2181 // fold (aext (and (trunc x), cst)) -> (and x, cst).
2182 if (N0.getOpcode() == ISD::AND &&
2183 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2184 N0.getOperand(1).getOpcode() == ISD::Constant) {
2185 SDOperand X = N0.getOperand(0).getOperand(0);
2186 if (X.getValueType() < VT) {
2187 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2188 } else if (X.getValueType() > VT) {
2189 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2191 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2192 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2195 // fold (aext (load x)) -> (aext (truncate (extload x)))
2196 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2197 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2198 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2199 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2200 LN0->getBasePtr(), LN0->getSrcValue(),
2201 LN0->getSrcValueOffset(),
2203 CombineTo(N, ExtLoad);
2204 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2205 ExtLoad.getValue(1));
2206 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2209 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2210 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2211 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2212 if (N0.getOpcode() == ISD::LOAD &&
2213 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
2215 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2216 MVT::ValueType EVT = LN0->getLoadedVT();
2217 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2218 LN0->getChain(), LN0->getBasePtr(),
2220 LN0->getSrcValueOffset(), EVT);
2221 CombineTo(N, ExtLoad);
2222 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2223 ExtLoad.getValue(1));
2224 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2230 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
2231 SDOperand N0 = N->getOperand(0);
2232 SDOperand N1 = N->getOperand(1);
2233 MVT::ValueType VT = N->getValueType(0);
2234 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
2235 unsigned EVTBits = MVT::getSizeInBits(EVT);
2237 // fold (sext_in_reg c1) -> c1
2238 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
2239 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
2241 // If the input is already sign extended, just drop the extension.
2242 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
2245 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
2246 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2247 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
2248 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
2251 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
2252 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
2253 return DAG.getZeroExtendInReg(N0, EVT);
2255 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
2256 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
2257 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
2258 if (N0.getOpcode() == ISD::SRL) {
2259 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2260 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
2261 // We can turn this into an SRA iff the input to the SRL is already sign
2263 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0));
2264 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
2265 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
2269 // fold (sext_inreg (extload x)) -> (sextload x)
2270 if (ISD::isEXTLoad(N0.Val) &&
2271 ISD::isUNINDEXEDLoad(N0.Val) &&
2272 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2273 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2274 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2275 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2276 LN0->getBasePtr(), LN0->getSrcValue(),
2277 LN0->getSrcValueOffset(), EVT);
2278 CombineTo(N, ExtLoad);
2279 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2280 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2282 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
2283 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
2285 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2286 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2287 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2288 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2289 LN0->getBasePtr(), LN0->getSrcValue(),
2290 LN0->getSrcValueOffset(), EVT);
2291 CombineTo(N, ExtLoad);
2292 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2293 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2298 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
2299 SDOperand N0 = N->getOperand(0);
2300 MVT::ValueType VT = N->getValueType(0);
2301 unsigned VTBits = MVT::getSizeInBits(VT);
2304 if (N0.getValueType() == N->getValueType(0))
2306 // fold (truncate c1) -> c1
2307 if (isa<ConstantSDNode>(N0))
2308 return DAG.getNode(ISD::TRUNCATE, VT, N0);
2309 // fold (truncate (truncate x)) -> (truncate x)
2310 if (N0.getOpcode() == ISD::TRUNCATE)
2311 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2312 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
2313 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
2314 N0.getOpcode() == ISD::ANY_EXTEND) {
2315 if (N0.getOperand(0).getValueType() < VT)
2316 // if the source is smaller than the dest, we still need an extend
2317 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2318 else if (N0.getOperand(0).getValueType() > VT)
2319 // if the source is larger than the dest, than we just need the truncate
2320 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2322 // if the source and dest are the same type, we can drop both the extend
2324 return N0.getOperand(0);
2327 // fold (truncate (load x)) -> (smaller load x)
2328 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
2330 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
2331 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2332 ShAmt = N01->getValue();
2333 // Is the shift amount a multiple of size of VT?
2334 if ((ShAmt & (VTBits-1)) == 0) {
2335 N0 = N0.getOperand(0);
2336 if (MVT::getSizeInBits(N0.getValueType()) <= VTBits)
2342 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2343 // Do not allow folding to i1 here. i1 is implicitly stored in memory in
2344 // zero extended form: by shrinking the load, we lose track of the fact
2345 // that it is already zero extended.
2346 // FIXME: This should be reevaluated.
2348 assert(MVT::getSizeInBits(N0.getValueType()) > VTBits &&
2349 "Cannot truncate to larger type!");
2350 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2351 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2352 // For big endian targets, we need to add an offset to the pointer to load
2353 // the correct bytes. For little endian systems, we merely need to read
2354 // fewer bytes from the same pointer.
2355 uint64_t PtrOff = ShAmt
2356 ? ShAmt : (TLI.isLittleEndian() ? 0
2357 : (MVT::getSizeInBits(N0.getValueType()) - VTBits) / 8);
2358 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
2359 DAG.getConstant(PtrOff, PtrType));
2360 AddToWorkList(NewPtr.Val);
2361 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), NewPtr,
2362 LN0->getSrcValue(), LN0->getSrcValueOffset());
2364 CombineTo(N0.Val, Load, Load.getValue(1));
2366 return DAG.getNode(ISD::TRUNCATE, VT, Load);
2367 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2372 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
2373 SDOperand N0 = N->getOperand(0);
2374 MVT::ValueType VT = N->getValueType(0);
2376 // If the input is a constant, let getNode() fold it.
2377 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
2378 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2379 if (Res.Val != N) return Res;
2382 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
2383 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
2385 // fold (conv (load x)) -> (load (conv*)x)
2386 // FIXME: These xforms need to know that the resultant load doesn't need a
2387 // higher alignment than the original!
2388 if (0 && ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) {
2389 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2390 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
2391 LN0->getSrcValue(), LN0->getSrcValueOffset());
2393 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
2401 SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) {
2402 SDOperand N0 = N->getOperand(0);
2403 MVT::ValueType VT = N->getValueType(0);
2405 // If the input is a VBUILD_VECTOR with all constant elements, fold this now.
2406 // First check to see if this is all constant.
2407 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() &&
2408 VT == MVT::Vector) {
2409 bool isSimple = true;
2410 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i)
2411 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
2412 N0.getOperand(i).getOpcode() != ISD::Constant &&
2413 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
2418 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT();
2419 if (isSimple && !MVT::isVector(DestEltVT)) {
2420 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT);
2427 /// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector
2428 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
2429 /// destination element value type.
2430 SDOperand DAGCombiner::
2431 ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
2432 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
2434 // If this is already the right type, we're done.
2435 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
2437 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
2438 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
2440 // If this is a conversion of N elements of one type to N elements of another
2441 // type, convert each element. This handles FP<->INT cases.
2442 if (SrcBitSize == DstBitSize) {
2443 SmallVector<SDOperand, 8> Ops;
2444 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2445 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
2446 AddToWorkList(Ops.back().Val);
2448 Ops.push_back(*(BV->op_end()-2)); // Add num elements.
2449 Ops.push_back(DAG.getValueType(DstEltVT));
2450 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2453 // Otherwise, we're growing or shrinking the elements. To avoid having to
2454 // handle annoying details of growing/shrinking FP values, we convert them to
2456 if (MVT::isFloatingPoint(SrcEltVT)) {
2457 // Convert the input float vector to a int vector where the elements are the
2459 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
2460 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2461 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val;
2465 // Now we know the input is an integer vector. If the output is a FP type,
2466 // convert to integer first, then to FP of the right size.
2467 if (MVT::isFloatingPoint(DstEltVT)) {
2468 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
2469 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2470 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val;
2472 // Next, convert to FP elements of the same size.
2473 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT);
2476 // Okay, we know the src/dst types are both integers of differing types.
2477 // Handling growing first.
2478 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
2479 if (SrcBitSize < DstBitSize) {
2480 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
2482 SmallVector<SDOperand, 8> Ops;
2483 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e;
2484 i += NumInputsPerOutput) {
2485 bool isLE = TLI.isLittleEndian();
2486 uint64_t NewBits = 0;
2487 bool EltIsUndef = true;
2488 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
2489 // Shift the previously computed bits over.
2490 NewBits <<= SrcBitSize;
2491 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
2492 if (Op.getOpcode() == ISD::UNDEF) continue;
2495 NewBits |= cast<ConstantSDNode>(Op)->getValue();
2499 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2501 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
2504 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2505 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2506 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2509 // Finally, this must be the case where we are shrinking elements: each input
2510 // turns into multiple outputs.
2511 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
2512 SmallVector<SDOperand, 8> Ops;
2513 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2514 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
2515 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
2516 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2519 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
2521 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
2522 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
2523 OpVal >>= DstBitSize;
2524 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
2527 // For big endian targets, swap the order of the pieces of each element.
2528 if (!TLI.isLittleEndian())
2529 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
2531 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2532 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2533 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2538 SDOperand DAGCombiner::visitFADD(SDNode *N) {
2539 SDOperand N0 = N->getOperand(0);
2540 SDOperand N1 = N->getOperand(1);
2541 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2542 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2543 MVT::ValueType VT = N->getValueType(0);
2545 // fold (fadd c1, c2) -> c1+c2
2547 return DAG.getNode(ISD::FADD, VT, N0, N1);
2548 // canonicalize constant to RHS
2549 if (N0CFP && !N1CFP)
2550 return DAG.getNode(ISD::FADD, VT, N1, N0);
2551 // fold (A + (-B)) -> A-B
2552 if (N1.getOpcode() == ISD::FNEG)
2553 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
2554 // fold ((-A) + B) -> B-A
2555 if (N0.getOpcode() == ISD::FNEG)
2556 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
2558 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
2559 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
2560 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
2561 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
2562 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1));
2567 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
2568 SDOperand N0 = N->getOperand(0);
2569 SDOperand N1 = N->getOperand(1);
2570 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2571 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2572 MVT::ValueType VT = N->getValueType(0);
2574 // fold (fsub c1, c2) -> c1-c2
2576 return DAG.getNode(ISD::FSUB, VT, N0, N1);
2577 // fold (A-(-B)) -> A+B
2578 if (N1.getOpcode() == ISD::FNEG)
2579 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
2583 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
2584 SDOperand N0 = N->getOperand(0);
2585 SDOperand N1 = N->getOperand(1);
2586 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2587 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2588 MVT::ValueType VT = N->getValueType(0);
2590 // fold (fmul c1, c2) -> c1*c2
2592 return DAG.getNode(ISD::FMUL, VT, N0, N1);
2593 // canonicalize constant to RHS
2594 if (N0CFP && !N1CFP)
2595 return DAG.getNode(ISD::FMUL, VT, N1, N0);
2596 // fold (fmul X, 2.0) -> (fadd X, X)
2597 if (N1CFP && N1CFP->isExactlyValue(+2.0))
2598 return DAG.getNode(ISD::FADD, VT, N0, N0);
2600 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
2601 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
2602 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
2603 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
2604 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1));
2609 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
2610 SDOperand N0 = N->getOperand(0);
2611 SDOperand N1 = N->getOperand(1);
2612 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2613 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2614 MVT::ValueType VT = N->getValueType(0);
2616 // fold (fdiv c1, c2) -> c1/c2
2618 return DAG.getNode(ISD::FDIV, VT, N0, N1);
2622 SDOperand DAGCombiner::visitFREM(SDNode *N) {
2623 SDOperand N0 = N->getOperand(0);
2624 SDOperand N1 = N->getOperand(1);
2625 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2626 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2627 MVT::ValueType VT = N->getValueType(0);
2629 // fold (frem c1, c2) -> fmod(c1,c2)
2631 return DAG.getNode(ISD::FREM, VT, N0, N1);
2635 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
2636 SDOperand N0 = N->getOperand(0);
2637 SDOperand N1 = N->getOperand(1);
2638 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2639 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2640 MVT::ValueType VT = N->getValueType(0);
2642 if (N0CFP && N1CFP) // Constant fold
2643 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
2646 // copysign(x, c1) -> fabs(x) iff ispos(c1)
2647 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
2652 u.d = N1CFP->getValue();
2654 return DAG.getNode(ISD::FABS, VT, N0);
2656 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
2659 // copysign(fabs(x), y) -> copysign(x, y)
2660 // copysign(fneg(x), y) -> copysign(x, y)
2661 // copysign(copysign(x,z), y) -> copysign(x, y)
2662 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
2663 N0.getOpcode() == ISD::FCOPYSIGN)
2664 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
2666 // copysign(x, abs(y)) -> abs(x)
2667 if (N1.getOpcode() == ISD::FABS)
2668 return DAG.getNode(ISD::FABS, VT, N0);
2670 // copysign(x, copysign(y,z)) -> copysign(x, z)
2671 if (N1.getOpcode() == ISD::FCOPYSIGN)
2672 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
2674 // copysign(x, fp_extend(y)) -> copysign(x, y)
2675 // copysign(x, fp_round(y)) -> copysign(x, y)
2676 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
2677 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
2684 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
2685 SDOperand N0 = N->getOperand(0);
2686 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2687 MVT::ValueType VT = N->getValueType(0);
2689 // fold (sint_to_fp c1) -> c1fp
2691 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
2695 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
2696 SDOperand N0 = N->getOperand(0);
2697 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2698 MVT::ValueType VT = N->getValueType(0);
2700 // fold (uint_to_fp c1) -> c1fp
2702 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
2706 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
2707 SDOperand N0 = N->getOperand(0);
2708 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2709 MVT::ValueType VT = N->getValueType(0);
2711 // fold (fp_to_sint c1fp) -> c1
2713 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
2717 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
2718 SDOperand N0 = N->getOperand(0);
2719 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2720 MVT::ValueType VT = N->getValueType(0);
2722 // fold (fp_to_uint c1fp) -> c1
2724 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
2728 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
2729 SDOperand N0 = N->getOperand(0);
2730 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2731 MVT::ValueType VT = N->getValueType(0);
2733 // fold (fp_round c1fp) -> c1fp
2735 return DAG.getNode(ISD::FP_ROUND, VT, N0);
2737 // fold (fp_round (fp_extend x)) -> x
2738 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
2739 return N0.getOperand(0);
2741 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
2742 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
2743 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
2744 AddToWorkList(Tmp.Val);
2745 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
2751 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
2752 SDOperand N0 = N->getOperand(0);
2753 MVT::ValueType VT = N->getValueType(0);
2754 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2755 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2757 // fold (fp_round_inreg c1fp) -> c1fp
2759 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
2760 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
2765 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
2766 SDOperand N0 = N->getOperand(0);
2767 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2768 MVT::ValueType VT = N->getValueType(0);
2770 // fold (fp_extend c1fp) -> c1fp
2772 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
2774 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
2775 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2776 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2777 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2778 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2779 LN0->getBasePtr(), LN0->getSrcValue(),
2780 LN0->getSrcValueOffset(),
2782 CombineTo(N, ExtLoad);
2783 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
2784 ExtLoad.getValue(1));
2785 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2792 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
2793 SDOperand N0 = N->getOperand(0);
2794 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2795 MVT::ValueType VT = N->getValueType(0);
2797 // fold (fneg c1) -> -c1
2799 return DAG.getNode(ISD::FNEG, VT, N0);
2800 // fold (fneg (sub x, y)) -> (sub y, x)
2801 if (N0.getOpcode() == ISD::SUB)
2802 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0));
2803 // fold (fneg (fneg x)) -> x
2804 if (N0.getOpcode() == ISD::FNEG)
2805 return N0.getOperand(0);
2809 SDOperand DAGCombiner::visitFABS(SDNode *N) {
2810 SDOperand N0 = N->getOperand(0);
2811 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2812 MVT::ValueType VT = N->getValueType(0);
2814 // fold (fabs c1) -> fabs(c1)
2816 return DAG.getNode(ISD::FABS, VT, N0);
2817 // fold (fabs (fabs x)) -> (fabs x)
2818 if (N0.getOpcode() == ISD::FABS)
2819 return N->getOperand(0);
2820 // fold (fabs (fneg x)) -> (fabs x)
2821 // fold (fabs (fcopysign x, y)) -> (fabs x)
2822 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
2823 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
2828 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
2829 SDOperand Chain = N->getOperand(0);
2830 SDOperand N1 = N->getOperand(1);
2831 SDOperand N2 = N->getOperand(2);
2832 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2834 // never taken branch, fold to chain
2835 if (N1C && N1C->isNullValue())
2837 // unconditional branch
2838 if (N1C && N1C->getValue() == 1)
2839 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2840 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
2842 if (N1.getOpcode() == ISD::SETCC &&
2843 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
2844 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
2845 N1.getOperand(0), N1.getOperand(1), N2);
2850 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
2852 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
2853 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2854 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2856 // Use SimplifySetCC to simplify SETCC's.
2857 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2858 if (Simp.Val) AddToWorkList(Simp.Val);
2860 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2862 // fold br_cc true, dest -> br dest (unconditional branch)
2863 if (SCCC && SCCC->getValue())
2864 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2866 // fold br_cc false, dest -> unconditional fall through
2867 if (SCCC && SCCC->isNullValue())
2868 return N->getOperand(0);
2870 // fold to a simpler setcc
2871 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2872 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2873 Simp.getOperand(2), Simp.getOperand(0),
2874 Simp.getOperand(1), N->getOperand(4));
2879 /// CombineToPreIndexedLoadStore - Try turning a load / store and a
2880 /// pre-indexed load / store when the base pointer is a add or subtract
2881 /// and it has other uses besides the load / store. After the
2882 /// transformation, the new indexed load / store has effectively folded
2883 /// the add / subtract in and all of its other uses are redirected to the
2884 /// new load / store.
2885 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
2892 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2893 if (LD->getAddressingMode() != ISD::UNINDEXED)
2895 VT = LD->getLoadedVT();
2896 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
2897 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
2899 Ptr = LD->getBasePtr();
2900 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2901 if (ST->getAddressingMode() != ISD::UNINDEXED)
2903 VT = ST->getStoredVT();
2904 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
2905 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
2907 Ptr = ST->getBasePtr();
2912 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
2913 // out. There is no reason to make this a preinc/predec.
2914 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
2915 Ptr.Val->hasOneUse())
2918 // Ask the target to do addressing mode selection.
2921 ISD::MemIndexedMode AM = ISD::UNINDEXED;
2922 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
2925 // Try turning it into a pre-indexed load / store except when:
2926 // 1) The base is a frame index.
2927 // 2) If N is a store and the ptr is either the same as or is a
2928 // predecessor of the value being stored.
2929 // 3) Another use of base ptr is a predecessor of N. If ptr is folded
2930 // that would create a cycle.
2931 // 4) All uses are load / store ops that use it as base ptr.
2933 // Check #1. Preinc'ing a frame index would require copying the stack pointer
2934 // (plus the implicit offset) to a register to preinc anyway.
2935 if (isa<FrameIndexSDNode>(BasePtr))
2940 SDOperand Val = cast<StoreSDNode>(N)->getValue();
2941 if (Val == Ptr || Ptr.Val->isPredecessor(Val.Val))
2945 // Now check for #2 and #3.
2946 bool RealUse = false;
2947 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
2948 E = Ptr.Val->use_end(); I != E; ++I) {
2952 if (Use->isPredecessor(N))
2955 if (!((Use->getOpcode() == ISD::LOAD &&
2956 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
2957 (Use->getOpcode() == ISD::STORE) &&
2958 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))
2966 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM);
2968 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
2971 DOUT << "\nReplacing.4 "; DEBUG(N->dump());
2972 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
2974 std::vector<SDNode*> NowDead;
2976 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
2978 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
2981 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
2985 // Nodes can end up on the worklist more than once. Make sure we do
2986 // not process a node that has been replaced.
2987 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
2988 removeFromWorkList(NowDead[i]);
2989 // Finally, since the node is now dead, remove it from the graph.
2992 // Replace the uses of Ptr with uses of the updated base value.
2993 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
2995 removeFromWorkList(Ptr.Val);
2996 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
2997 removeFromWorkList(NowDead[i]);
2998 DAG.DeleteNode(Ptr.Val);
3003 /// CombineToPostIndexedLoadStore - Try combine a load / store with a
3004 /// add / sub of the base pointer node into a post-indexed load / store.
3005 /// The transformation folded the add / subtract into the new indexed
3006 /// load / store effectively and all of its uses are redirected to the
3007 /// new load / store.
3008 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
3015 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3016 if (LD->getAddressingMode() != ISD::UNINDEXED)
3018 VT = LD->getLoadedVT();
3019 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
3020 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
3022 Ptr = LD->getBasePtr();
3023 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3024 if (ST->getAddressingMode() != ISD::UNINDEXED)
3026 VT = ST->getStoredVT();
3027 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
3028 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
3030 Ptr = ST->getBasePtr();
3035 if (Ptr.Val->hasOneUse())
3038 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3039 E = Ptr.Val->use_end(); I != E; ++I) {
3042 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
3047 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3048 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
3050 std::swap(BasePtr, Offset);
3054 // Try turning it into a post-indexed load / store except when
3055 // 1) All uses are load / store ops that use it as base ptr.
3056 // 2) Op must be independent of N, i.e. Op is neither a predecessor
3057 // nor a successor of N. Otherwise, if Op is folded that would
3061 bool TryNext = false;
3062 for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
3063 EE = BasePtr.Val->use_end(); II != EE; ++II) {
3068 // If all the uses are load / store addresses, then don't do the
3070 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
3071 bool RealUse = false;
3072 for (SDNode::use_iterator III = Use->use_begin(),
3073 EEE = Use->use_end(); III != EEE; ++III) {
3074 SDNode *UseUse = *III;
3075 if (!((UseUse->getOpcode() == ISD::LOAD &&
3076 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
3077 (UseUse->getOpcode() == ISD::STORE) &&
3078 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))
3092 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) {
3093 SDOperand Result = isLoad
3094 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
3095 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
3098 DOUT << "\nReplacing.5 "; DEBUG(N->dump());
3099 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
3101 std::vector<SDNode*> NowDead;
3103 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
3105 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
3108 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
3112 // Nodes can end up on the worklist more than once. Make sure we do
3113 // not process a node that has been replaced.
3114 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3115 removeFromWorkList(NowDead[i]);
3116 // Finally, since the node is now dead, remove it from the graph.
3119 // Replace the uses of Use with uses of the updated base value.
3120 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0),
3121 Result.getValue(isLoad ? 1 : 0),
3123 removeFromWorkList(Op);
3124 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3125 removeFromWorkList(NowDead[i]);
3136 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
3137 LoadSDNode *LD = cast<LoadSDNode>(N);
3138 SDOperand Chain = LD->getChain();
3139 SDOperand Ptr = LD->getBasePtr();
3141 // If there are no uses of the loaded value, change uses of the chain value
3142 // into uses of the chain input (i.e. delete the dead load).
3143 if (N->hasNUsesOfValue(0, 0))
3144 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
3146 // If this load is directly stored, replace the load value with the stored
3148 // TODO: Handle store large -> read small portion.
3149 // TODO: Handle TRUNCSTORE/LOADEXT
3150 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
3151 if (ISD::isNON_TRUNCStore(Chain.Val)) {
3152 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
3153 if (PrevST->getBasePtr() == Ptr &&
3154 PrevST->getValue().getValueType() == N->getValueType(0))
3155 return CombineTo(N, Chain.getOperand(1), Chain);
3160 // Walk up chain skipping non-aliasing memory nodes.
3161 SDOperand BetterChain = FindBetterChain(N, Chain);
3163 // If there is a better chain.
3164 if (Chain != BetterChain) {
3167 // Replace the chain to void dependency.
3168 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
3169 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
3170 LD->getSrcValue(), LD->getSrcValueOffset());
3172 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
3173 LD->getValueType(0),
3174 BetterChain, Ptr, LD->getSrcValue(),
3175 LD->getSrcValueOffset(),
3179 // Create token factor to keep old chain connected.
3180 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
3181 Chain, ReplLoad.getValue(1));
3183 // Replace uses with load result and token factor. Don't add users
3185 return CombineTo(N, ReplLoad.getValue(0), Token, false);
3189 // Try transforming N to an indexed load.
3190 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
3191 return SDOperand(N, 0);
3196 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
3197 StoreSDNode *ST = cast<StoreSDNode>(N);
3198 SDOperand Chain = ST->getChain();
3199 SDOperand Value = ST->getValue();
3200 SDOperand Ptr = ST->getBasePtr();
3202 // If this is a store of a bit convert, store the input value.
3203 // FIXME: This needs to know that the resultant store does not need a
3204 // higher alignment than the original.
3205 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) {
3206 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
3207 ST->getSrcValueOffset());
3210 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
3211 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
3212 if (Value.getOpcode() != ISD::TargetConstantFP) {
3214 switch (CFP->getValueType(0)) {
3215 default: assert(0 && "Unknown FP type");
3217 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) {
3218 Tmp = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
3219 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
3220 ST->getSrcValueOffset());
3224 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) {
3225 Tmp = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
3226 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
3227 ST->getSrcValueOffset());
3228 } else if (TLI.isTypeLegal(MVT::i32)) {
3229 // Many FP stores are not make apparent until after legalize, e.g. for
3230 // argument passing. Since this is so common, custom legalize the
3231 // 64-bit integer store into two 32-bit stores.
3232 uint64_t Val = DoubleToBits(CFP->getValue());
3233 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
3234 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32);
3235 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
3237 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(),
3238 ST->getSrcValueOffset());
3239 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3240 DAG.getConstant(4, Ptr.getValueType()));
3241 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(),
3242 ST->getSrcValueOffset()+4);
3243 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1);
3251 // Walk up chain skipping non-aliasing memory nodes.
3252 SDOperand BetterChain = FindBetterChain(N, Chain);
3254 // If there is a better chain.
3255 if (Chain != BetterChain) {
3256 // Replace the chain to avoid dependency.
3257 SDOperand ReplStore;
3258 if (ST->isTruncatingStore()) {
3259 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
3260 ST->getSrcValue(),ST->getSrcValueOffset(), ST->getStoredVT());
3262 ReplStore = DAG.getStore(BetterChain, Value, Ptr,
3263 ST->getSrcValue(), ST->getSrcValueOffset());
3266 // Create token to keep both nodes around.
3268 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
3270 // Don't add users to work list.
3271 return CombineTo(N, Token, false);
3275 // Try transforming N to an indexed store.
3276 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
3277 return SDOperand(N, 0);
3282 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
3283 SDOperand InVec = N->getOperand(0);
3284 SDOperand InVal = N->getOperand(1);
3285 SDOperand EltNo = N->getOperand(2);
3287 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
3288 // vector with the inserted element.
3289 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
3290 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
3291 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
3292 if (Elt < Ops.size())
3294 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
3295 &Ops[0], Ops.size());
3301 SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
3302 SDOperand InVec = N->getOperand(0);
3303 SDOperand InVal = N->getOperand(1);
3304 SDOperand EltNo = N->getOperand(2);
3305 SDOperand NumElts = N->getOperand(3);
3306 SDOperand EltType = N->getOperand(4);
3308 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new
3309 // vector with the inserted element.
3310 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
3311 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
3312 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
3313 if (Elt < Ops.size()-2)
3315 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(),
3316 &Ops[0], Ops.size());
3322 SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
3323 unsigned NumInScalars = N->getNumOperands()-2;
3324 SDOperand NumElts = N->getOperand(NumInScalars);
3325 SDOperand EltType = N->getOperand(NumInScalars+1);
3327 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT
3328 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most
3329 // two distinct vectors, turn this into a shuffle node.
3330 SDOperand VecIn1, VecIn2;
3331 for (unsigned i = 0; i != NumInScalars; ++i) {
3332 // Ignore undef inputs.
3333 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3335 // If this input is something other than a VEXTRACT_VECTOR_ELT with a
3336 // constant index, bail out.
3337 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT ||
3338 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
3339 VecIn1 = VecIn2 = SDOperand(0, 0);
3343 // If the input vector type disagrees with the result of the vbuild_vector,
3344 // we can't make a shuffle.
3345 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
3346 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts ||
3347 *(ExtractedFromVec.Val->op_end()-1) != EltType) {
3348 VecIn1 = VecIn2 = SDOperand(0, 0);
3352 // Otherwise, remember this. We allow up to two distinct input vectors.
3353 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
3356 if (VecIn1.Val == 0) {
3357 VecIn1 = ExtractedFromVec;
3358 } else if (VecIn2.Val == 0) {
3359 VecIn2 = ExtractedFromVec;
3362 VecIn1 = VecIn2 = SDOperand(0, 0);
3367 // If everything is good, we can make a shuffle operation.
3369 SmallVector<SDOperand, 8> BuildVecIndices;
3370 for (unsigned i = 0; i != NumInScalars; ++i) {
3371 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
3372 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy()));
3376 SDOperand Extract = N->getOperand(i);
3378 // If extracting from the first vector, just use the index directly.
3379 if (Extract.getOperand(0) == VecIn1) {
3380 BuildVecIndices.push_back(Extract.getOperand(1));
3384 // Otherwise, use InIdx + VecSize
3385 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
3386 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars,
3387 TLI.getPointerTy()));
3390 // Add count and size info.
3391 BuildVecIndices.push_back(NumElts);
3392 BuildVecIndices.push_back(DAG.getValueType(TLI.getPointerTy()));
3394 // Return the new VVECTOR_SHUFFLE node.
3400 // Use an undef vbuild_vector as input for the second operand.
3401 std::vector<SDOperand> UnOps(NumInScalars,
3402 DAG.getNode(ISD::UNDEF,
3403 cast<VTSDNode>(EltType)->getVT()));
3404 UnOps.push_back(NumElts);
3405 UnOps.push_back(EltType);
3406 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3407 &UnOps[0], UnOps.size());
3408 AddToWorkList(Ops[1].Val);
3410 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3411 &BuildVecIndices[0], BuildVecIndices.size());
3414 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5);
3420 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
3421 SDOperand ShufMask = N->getOperand(2);
3422 unsigned NumElts = ShufMask.getNumOperands();
3424 // If the shuffle mask is an identity operation on the LHS, return the LHS.
3425 bool isIdentity = true;
3426 for (unsigned i = 0; i != NumElts; ++i) {
3427 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3428 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
3433 if (isIdentity) return N->getOperand(0);
3435 // If the shuffle mask is an identity operation on the RHS, return the RHS.
3437 for (unsigned i = 0; i != NumElts; ++i) {
3438 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3439 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
3444 if (isIdentity) return N->getOperand(1);
3446 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
3448 bool isUnary = true;
3449 bool isSplat = true;
3451 unsigned BaseIdx = 0;
3452 for (unsigned i = 0; i != NumElts; ++i)
3453 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
3454 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
3455 int V = (Idx < NumElts) ? 0 : 1;
3469 SDOperand N0 = N->getOperand(0);
3470 SDOperand N1 = N->getOperand(1);
3471 // Normalize unary shuffle so the RHS is undef.
3472 if (isUnary && VecNum == 1)
3475 // If it is a splat, check if the argument vector is a build_vector with
3476 // all scalar elements the same.
3479 if (V->getOpcode() == ISD::BIT_CONVERT)
3480 V = V->getOperand(0).Val;
3481 if (V->getOpcode() == ISD::BUILD_VECTOR) {
3482 unsigned NumElems = V->getNumOperands()-2;
3483 if (NumElems > BaseIdx) {
3485 bool AllSame = true;
3486 for (unsigned i = 0; i != NumElems; ++i) {
3487 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3488 Base = V->getOperand(i);
3492 // Splat of <u, u, u, u>, return <u, u, u, u>
3495 for (unsigned i = 0; i != NumElems; ++i) {
3496 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3497 V->getOperand(i) != Base) {
3502 // Splat of <x, x, x, x>, return <x, x, x, x>
3509 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3511 if (isUnary || N0 == N1) {
3512 if (N0.getOpcode() == ISD::UNDEF)
3513 return DAG.getNode(ISD::UNDEF, N->getValueType(0));
3514 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3516 SmallVector<SDOperand, 8> MappedOps;
3517 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
3518 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3519 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3520 MappedOps.push_back(ShufMask.getOperand(i));
3523 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3524 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3527 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
3528 &MappedOps[0], MappedOps.size());
3529 AddToWorkList(ShufMask.Val);
3530 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
3532 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
3539 SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
3540 SDOperand ShufMask = N->getOperand(2);
3541 unsigned NumElts = ShufMask.getNumOperands()-2;
3543 // If the shuffle mask is an identity operation on the LHS, return the LHS.
3544 bool isIdentity = true;
3545 for (unsigned i = 0; i != NumElts; ++i) {
3546 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3547 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
3552 if (isIdentity) return N->getOperand(0);
3554 // If the shuffle mask is an identity operation on the RHS, return the RHS.
3556 for (unsigned i = 0; i != NumElts; ++i) {
3557 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3558 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
3563 if (isIdentity) return N->getOperand(1);
3565 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
3567 bool isUnary = true;
3568 bool isSplat = true;
3570 unsigned BaseIdx = 0;
3571 for (unsigned i = 0; i != NumElts; ++i)
3572 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
3573 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
3574 int V = (Idx < NumElts) ? 0 : 1;
3588 SDOperand N0 = N->getOperand(0);
3589 SDOperand N1 = N->getOperand(1);
3590 // Normalize unary shuffle so the RHS is undef.
3591 if (isUnary && VecNum == 1)
3594 // If it is a splat, check if the argument vector is a build_vector with
3595 // all scalar elements the same.
3599 // If this is a vbit convert that changes the element type of the vector but
3600 // not the number of vector elements, look through it. Be careful not to
3601 // look though conversions that change things like v4f32 to v2f64.
3602 if (V->getOpcode() == ISD::VBIT_CONVERT) {
3603 SDOperand ConvInput = V->getOperand(0);
3604 if (ConvInput.getValueType() == MVT::Vector &&
3606 ConvInput.getConstantOperandVal(ConvInput.getNumOperands()-2))
3610 if (V->getOpcode() == ISD::VBUILD_VECTOR) {
3611 unsigned NumElems = V->getNumOperands()-2;
3612 if (NumElems > BaseIdx) {
3614 bool AllSame = true;
3615 for (unsigned i = 0; i != NumElems; ++i) {
3616 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3617 Base = V->getOperand(i);
3621 // Splat of <u, u, u, u>, return <u, u, u, u>
3624 for (unsigned i = 0; i != NumElems; ++i) {
3625 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3626 V->getOperand(i) != Base) {
3631 // Splat of <x, x, x, x>, return <x, x, x, x>
3638 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3640 if (isUnary || N0 == N1) {
3641 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3643 SmallVector<SDOperand, 8> MappedOps;
3644 for (unsigned i = 0; i != NumElts; ++i) {
3645 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3646 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3647 MappedOps.push_back(ShufMask.getOperand(i));
3650 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3651 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3654 // Add the type/#elts values.
3655 MappedOps.push_back(ShufMask.getOperand(NumElts));
3656 MappedOps.push_back(ShufMask.getOperand(NumElts+1));
3658 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(),
3659 &MappedOps[0], MappedOps.size());
3660 AddToWorkList(ShufMask.Val);
3662 // Build the undef vector.
3663 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType());
3664 for (unsigned i = 0; i != NumElts; ++i)
3665 MappedOps[i] = UDVal;
3666 MappedOps[NumElts ] = *(N0.Val->op_end()-2);
3667 MappedOps[NumElts+1] = *(N0.Val->op_end()-1);
3668 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3669 &MappedOps[0], MappedOps.size());
3671 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3672 N0, UDVal, ShufMask,
3673 MappedOps[NumElts], MappedOps[NumElts+1]);
3679 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
3680 /// a VAND to a vector_shuffle with the destination vector and a zero vector.
3681 /// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
3682 /// vector_shuffle V, Zero, <0, 4, 2, 4>
3683 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
3684 SDOperand LHS = N->getOperand(0);
3685 SDOperand RHS = N->getOperand(1);
3686 if (N->getOpcode() == ISD::VAND) {
3687 SDOperand DstVecSize = *(LHS.Val->op_end()-2);
3688 SDOperand DstVecEVT = *(LHS.Val->op_end()-1);
3689 if (RHS.getOpcode() == ISD::VBIT_CONVERT)
3690 RHS = RHS.getOperand(0);
3691 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3692 std::vector<SDOperand> IdxOps;
3693 unsigned NumOps = RHS.getNumOperands();
3694 unsigned NumElts = NumOps-2;
3695 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT();
3696 for (unsigned i = 0; i != NumElts; ++i) {
3697 SDOperand Elt = RHS.getOperand(i);
3698 if (!isa<ConstantSDNode>(Elt))
3700 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
3701 IdxOps.push_back(DAG.getConstant(i, EVT));
3702 else if (cast<ConstantSDNode>(Elt)->isNullValue())
3703 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
3708 // Let's see if the target supports this vector_shuffle.
3709 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
3712 // Return the new VVECTOR_SHUFFLE node.
3713 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32);
3714 SDOperand EVTNode = DAG.getValueType(EVT);
3715 std::vector<SDOperand> Ops;
3716 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode,
3719 AddToWorkList(LHS.Val);
3720 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
3721 ZeroOps.push_back(NumEltsNode);
3722 ZeroOps.push_back(EVTNode);
3723 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3724 &ZeroOps[0], ZeroOps.size()));
3725 IdxOps.push_back(NumEltsNode);
3726 IdxOps.push_back(EVTNode);
3727 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3728 &IdxOps[0], IdxOps.size()));
3729 Ops.push_back(NumEltsNode);
3730 Ops.push_back(EVTNode);
3731 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3732 &Ops[0], Ops.size());
3733 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) {
3734 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
3735 DstVecSize, DstVecEVT);
3743 /// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates
3744 /// the scalar operation of the vop if it is operating on an integer vector
3745 /// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD).
3746 SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
3747 ISD::NodeType FPOp) {
3748 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT();
3749 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp;
3750 SDOperand LHS = N->getOperand(0);
3751 SDOperand RHS = N->getOperand(1);
3752 SDOperand Shuffle = XformToShuffleWithZero(N);
3753 if (Shuffle.Val) return Shuffle;
3755 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold
3757 if (LHS.getOpcode() == ISD::VBUILD_VECTOR &&
3758 RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3759 SmallVector<SDOperand, 8> Ops;
3760 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
3761 SDOperand LHSOp = LHS.getOperand(i);
3762 SDOperand RHSOp = RHS.getOperand(i);
3763 // If these two elements can't be folded, bail out.
3764 if ((LHSOp.getOpcode() != ISD::UNDEF &&
3765 LHSOp.getOpcode() != ISD::Constant &&
3766 LHSOp.getOpcode() != ISD::ConstantFP) ||
3767 (RHSOp.getOpcode() != ISD::UNDEF &&
3768 RHSOp.getOpcode() != ISD::Constant &&
3769 RHSOp.getOpcode() != ISD::ConstantFP))
3771 // Can't fold divide by zero.
3772 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) {
3773 if ((RHSOp.getOpcode() == ISD::Constant &&
3774 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
3775 (RHSOp.getOpcode() == ISD::ConstantFP &&
3776 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue()))
3779 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
3780 AddToWorkList(Ops.back().Val);
3781 assert((Ops.back().getOpcode() == ISD::UNDEF ||
3782 Ops.back().getOpcode() == ISD::Constant ||
3783 Ops.back().getOpcode() == ISD::ConstantFP) &&
3784 "Scalar binop didn't fold!");
3787 if (Ops.size() == LHS.getNumOperands()-2) {
3788 Ops.push_back(*(LHS.Val->op_end()-2));
3789 Ops.push_back(*(LHS.Val->op_end()-1));
3790 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
3797 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
3798 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
3800 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
3801 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3802 // If we got a simplified select_cc node back from SimplifySelectCC, then
3803 // break it down into a new SETCC node, and a new SELECT node, and then return
3804 // the SELECT node, since we were called with a SELECT node.
3806 // Check to see if we got a select_cc back (to turn into setcc/select).
3807 // Otherwise, just return whatever node we got back, like fabs.
3808 if (SCC.getOpcode() == ISD::SELECT_CC) {
3809 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
3810 SCC.getOperand(0), SCC.getOperand(1),
3812 AddToWorkList(SETCC.Val);
3813 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
3814 SCC.getOperand(3), SETCC);
3821 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
3822 /// are the two values being selected between, see if we can simplify the
3823 /// select. Callers of this should assume that TheSelect is deleted if this
3824 /// returns true. As such, they should return the appropriate thing (e.g. the
3825 /// node) back to the top-level of the DAG combiner loop to avoid it being
3828 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
3831 // If this is a select from two identical things, try to pull the operation
3832 // through the select.
3833 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
3834 // If this is a load and the token chain is identical, replace the select
3835 // of two loads with a load through a select of the address to load from.
3836 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
3837 // constants have been dropped into the constant pool.
3838 if (LHS.getOpcode() == ISD::LOAD &&
3839 // Token chains must be identical.
3840 LHS.getOperand(0) == RHS.getOperand(0)) {
3841 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
3842 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
3844 // If this is an EXTLOAD, the VT's must match.
3845 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
3846 // FIXME: this conflates two src values, discarding one. This is not
3847 // the right thing to do, but nothing uses srcvalues now. When they do,
3848 // turn SrcValue into a list of locations.
3850 if (TheSelect->getOpcode() == ISD::SELECT) {
3851 // Check that the condition doesn't reach either load. If so, folding
3852 // this will induce a cycle into the DAG.
3853 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
3854 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) {
3855 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
3856 TheSelect->getOperand(0), LLD->getBasePtr(),
3860 // Check that the condition doesn't reach either load. If so, folding
3861 // this will induce a cycle into the DAG.
3862 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
3863 !RLD->isPredecessor(TheSelect->getOperand(0).Val) &&
3864 !LLD->isPredecessor(TheSelect->getOperand(1).Val) &&
3865 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) {
3866 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
3867 TheSelect->getOperand(0),
3868 TheSelect->getOperand(1),
3869 LLD->getBasePtr(), RLD->getBasePtr(),
3870 TheSelect->getOperand(4));
3876 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
3877 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
3878 Addr,LLD->getSrcValue(),
3879 LLD->getSrcValueOffset());
3881 Load = DAG.getExtLoad(LLD->getExtensionType(),
3882 TheSelect->getValueType(0),
3883 LLD->getChain(), Addr, LLD->getSrcValue(),
3884 LLD->getSrcValueOffset(),
3885 LLD->getLoadedVT());
3887 // Users of the select now use the result of the load.
3888 CombineTo(TheSelect, Load);
3890 // Users of the old loads now use the new load's chain. We know the
3891 // old-load value is dead now.
3892 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
3893 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
3903 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
3904 SDOperand N2, SDOperand N3,
3907 MVT::ValueType VT = N2.getValueType();
3908 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
3909 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
3910 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
3912 // Determine if the condition we're dealing with is constant
3913 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
3914 if (SCC.Val) AddToWorkList(SCC.Val);
3915 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
3917 // fold select_cc true, x, y -> x
3918 if (SCCC && SCCC->getValue())
3920 // fold select_cc false, x, y -> y
3921 if (SCCC && SCCC->getValue() == 0)
3924 // Check to see if we can simplify the select into an fabs node
3925 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
3926 // Allow either -0.0 or 0.0
3927 if (CFP->getValue() == 0.0) {
3928 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
3929 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
3930 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
3931 N2 == N3.getOperand(0))
3932 return DAG.getNode(ISD::FABS, VT, N0);
3934 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
3935 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
3936 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
3937 N2.getOperand(0) == N3)
3938 return DAG.getNode(ISD::FABS, VT, N3);
3942 // Check to see if we can perform the "gzip trick", transforming
3943 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
3944 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
3945 MVT::isInteger(N0.getValueType()) &&
3946 MVT::isInteger(N2.getValueType()) &&
3947 (N1C->isNullValue() || // (a < 0) ? b : 0
3948 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
3949 MVT::ValueType XType = N0.getValueType();
3950 MVT::ValueType AType = N2.getValueType();
3951 if (XType >= AType) {
3952 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
3953 // single-bit constant.
3954 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
3955 unsigned ShCtV = Log2_64(N2C->getValue());
3956 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
3957 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
3958 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
3959 AddToWorkList(Shift.Val);
3960 if (XType > AType) {
3961 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3962 AddToWorkList(Shift.Val);
3964 return DAG.getNode(ISD::AND, AType, Shift, N2);
3966 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3967 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3968 TLI.getShiftAmountTy()));
3969 AddToWorkList(Shift.Val);
3970 if (XType > AType) {
3971 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3972 AddToWorkList(Shift.Val);
3974 return DAG.getNode(ISD::AND, AType, Shift, N2);
3978 // fold select C, 16, 0 -> shl C, 4
3979 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
3980 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
3981 // Get a SetCC of the condition
3982 // FIXME: Should probably make sure that setcc is legal if we ever have a
3983 // target where it isn't.
3984 SDOperand Temp, SCC;
3985 // cast from setcc result type to select result type
3986 if (AfterLegalize) {
3987 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3988 if (N2.getValueType() < SCC.getValueType())
3989 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
3991 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
3993 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
3994 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
3996 AddToWorkList(SCC.Val);
3997 AddToWorkList(Temp.Val);
3998 // shl setcc result by log2 n2c
3999 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
4000 DAG.getConstant(Log2_64(N2C->getValue()),
4001 TLI.getShiftAmountTy()));
4004 // Check to see if this is the equivalent of setcc
4005 // FIXME: Turn all of these into setcc if setcc if setcc is legal
4006 // otherwise, go ahead with the folds.
4007 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
4008 MVT::ValueType XType = N0.getValueType();
4009 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
4010 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4011 if (Res.getValueType() != VT)
4012 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
4016 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
4017 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
4018 TLI.isOperationLegal(ISD::CTLZ, XType)) {
4019 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
4020 return DAG.getNode(ISD::SRL, XType, Ctlz,
4021 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
4022 TLI.getShiftAmountTy()));
4024 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
4025 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
4026 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
4028 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
4029 DAG.getConstant(~0ULL, XType));
4030 return DAG.getNode(ISD::SRL, XType,
4031 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
4032 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4033 TLI.getShiftAmountTy()));
4035 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
4036 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
4037 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
4038 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4039 TLI.getShiftAmountTy()));
4040 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
4044 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
4045 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4046 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
4047 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
4048 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
4049 MVT::ValueType XType = N0.getValueType();
4050 if (SubC->isNullValue() && MVT::isInteger(XType)) {
4051 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4052 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4053 TLI.getShiftAmountTy()));
4054 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
4055 AddToWorkList(Shift.Val);
4056 AddToWorkList(Add.Val);
4057 return DAG.getNode(ISD::XOR, XType, Add, Shift);
4065 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
4066 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
4067 SDOperand N1, ISD::CondCode Cond,
4068 bool foldBooleans) {
4069 TargetLowering::DAGCombinerInfo
4070 DagCombineInfo(DAG, !AfterLegalize, false, this);
4071 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo);
4074 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
4075 /// return a DAG expression to select that will generate the same value by
4076 /// multiplying by a magic number. See:
4077 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4078 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
4079 std::vector<SDNode*> Built;
4080 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
4082 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4088 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
4089 /// return a DAG expression to select that will generate the same value by
4090 /// multiplying by a magic number. See:
4091 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4092 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
4093 std::vector<SDNode*> Built;
4094 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
4096 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4102 /// FindBaseOffset - Return true if base is known not to alias with anything
4103 /// but itself. Provides base object and offset as results.
4104 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
4105 // Assume it is a primitive operation.
4106 Base = Ptr; Offset = 0;
4108 // If it's an adding a simple constant then integrate the offset.
4109 if (Base.getOpcode() == ISD::ADD) {
4110 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
4111 Base = Base.getOperand(0);
4112 Offset += C->getValue();
4116 // If it's any of the following then it can't alias with anything but itself.
4117 return isa<FrameIndexSDNode>(Base) ||
4118 isa<ConstantPoolSDNode>(Base) ||
4119 isa<GlobalAddressSDNode>(Base);
4122 /// isAlias - Return true if there is any possibility that the two addresses
4124 bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1,
4125 const Value *SrcValue1, int SrcValueOffset1,
4126 SDOperand Ptr2, int64_t Size2,
4127 const Value *SrcValue2, int SrcValueOffset2)
4129 // If they are the same then they must be aliases.
4130 if (Ptr1 == Ptr2) return true;
4132 // Gather base node and offset information.
4133 SDOperand Base1, Base2;
4134 int64_t Offset1, Offset2;
4135 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
4136 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
4138 // If they have a same base address then...
4139 if (Base1 == Base2) {
4140 // Check to see if the addresses overlap.
4141 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
4144 // If we know both bases then they can't alias.
4145 if (KnownBase1 && KnownBase2) return false;
4147 if (CombinerGlobalAA) {
4148 // Use alias analysis information.
4149 int Overlap1 = Size1 + SrcValueOffset1 + Offset1;
4150 int Overlap2 = Size2 + SrcValueOffset2 + Offset2;
4151 AliasAnalysis::AliasResult AAResult =
4152 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
4153 if (AAResult == AliasAnalysis::NoAlias)
4157 // Otherwise we have to assume they alias.
4161 /// FindAliasInfo - Extracts the relevant alias information from the memory
4162 /// node. Returns true if the operand was a load.
4163 bool DAGCombiner::FindAliasInfo(SDNode *N,
4164 SDOperand &Ptr, int64_t &Size,
4165 const Value *&SrcValue, int &SrcValueOffset) {
4166 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4167 Ptr = LD->getBasePtr();
4168 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3;
4169 SrcValue = LD->getSrcValue();
4170 SrcValueOffset = LD->getSrcValueOffset();
4172 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4173 Ptr = ST->getBasePtr();
4174 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3;
4175 SrcValue = ST->getSrcValue();
4176 SrcValueOffset = ST->getSrcValueOffset();
4178 assert(0 && "FindAliasInfo expected a memory operand");
4184 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
4185 /// looking for aliasing nodes and adding them to the Aliases vector.
4186 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
4187 SmallVector<SDOperand, 8> &Aliases) {
4188 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
4189 std::set<SDNode *> Visited; // Visited node set.
4191 // Get alias information for node.
4194 const Value *SrcValue;
4196 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
4199 Chains.push_back(OriginalChain);
4201 // Look at each chain and determine if it is an alias. If so, add it to the
4202 // aliases list. If not, then continue up the chain looking for the next
4204 while (!Chains.empty()) {
4205 SDOperand Chain = Chains.back();
4208 // Don't bother if we've been before.
4209 if (Visited.find(Chain.Val) != Visited.end()) continue;
4210 Visited.insert(Chain.Val);
4212 switch (Chain.getOpcode()) {
4213 case ISD::EntryToken:
4214 // Entry token is ideal chain operand, but handled in FindBetterChain.
4219 // Get alias information for Chain.
4222 const Value *OpSrcValue;
4223 int OpSrcValueOffset;
4224 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
4225 OpSrcValue, OpSrcValueOffset);
4227 // If chain is alias then stop here.
4228 if (!(IsLoad && IsOpLoad) &&
4229 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
4230 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
4231 Aliases.push_back(Chain);
4233 // Look further up the chain.
4234 Chains.push_back(Chain.getOperand(0));
4235 // Clean up old chain.
4236 AddToWorkList(Chain.Val);
4241 case ISD::TokenFactor:
4242 // We have to check each of the operands of the token factor, so we queue
4243 // then up. Adding the operands to the queue (stack) in reverse order
4244 // maintains the original order and increases the likelihood that getNode
4245 // will find a matching token factor (CSE.)
4246 for (unsigned n = Chain.getNumOperands(); n;)
4247 Chains.push_back(Chain.getOperand(--n));
4248 // Eliminate the token factor if we can.
4249 AddToWorkList(Chain.Val);
4253 // For all other instructions we will just have to take what we can get.
4254 Aliases.push_back(Chain);
4260 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
4261 /// for a better chain (aliasing node.)
4262 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
4263 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
4265 // Accumulate all the aliases to this node.
4266 GatherAllAliases(N, OldChain, Aliases);
4268 if (Aliases.size() == 0) {
4269 // If no operands then chain to entry token.
4270 return DAG.getEntryNode();
4271 } else if (Aliases.size() == 1) {
4272 // If a single operand then chain to it. We don't need to revisit it.
4276 // Construct a custom tailored token factor.
4277 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4278 &Aliases[0], Aliases.size());
4280 // Make sure the old chain gets cleaned up.
4281 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
4286 // SelectionDAG::Combine - This is the entry point for the file.
4288 void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
4289 if (!RunningAfterLegalize && ViewDAGCombine1)
4291 if (RunningAfterLegalize && ViewDAGCombine2)
4293 /// run - This is the main entry point to this class.
4295 DAGCombiner(*this, AA).Run(RunningAfterLegalize);