1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/Target/TargetData.h"
27 #include "llvm/Target/TargetLowering.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/ADT/SmallPtrSet.h"
31 #include "llvm/ADT/Statistic.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
40 STATISTIC(NodesCombined , "Number of dag nodes combined");
41 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
42 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
43 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
44 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
48 CombinerAA("combiner-alias-analysis", cl::Hidden,
49 cl::desc("Turn on alias analysis during testing"));
52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
53 cl::desc("Include global information in alias analysis"));
55 //------------------------------ DAGCombiner ---------------------------------//
59 const TargetLowering &TLI;
61 CodeGenOpt::Level OptLevel;
65 // Worklist of all of the nodes that need to be simplified.
67 // This has the semantics that when adding to the worklist,
68 // the item added must be next to be processed. It should
69 // also only appear once. The naive approach to this takes
72 // To reduce the insert/remove time to logarithmic, we use
73 // a set and a vector to maintain our worklist.
75 // The set contains the items on the worklist, but does not
76 // maintain the order they should be visited.
78 // The vector maintains the order nodes should be visited, but may
79 // contain duplicate or removed nodes. When choosing a node to
80 // visit, we pop off the order stack until we find an item that is
81 // also in the contents set. All operations are O(log N).
82 SmallPtrSet<SDNode*, 64> WorkListContents;
83 std::vector<SDNode*> WorkListOrder;
85 // AA - Used for DAG load/store alias analysis.
88 /// AddUsersToWorkList - When an instruction is simplified, add all users of
89 /// the instruction to the work lists because they might get more simplified
92 void AddUsersToWorkList(SDNode *N) {
93 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
98 /// visit - call the node-specific routine that knows how to fold each
99 /// particular type of node.
100 SDValue visit(SDNode *N);
103 /// AddToWorkList - Add to the work list making sure its instance is at the
104 /// back (next to be processed.)
105 void AddToWorkList(SDNode *N) {
106 WorkListContents.insert(N);
107 WorkListOrder.push_back(N);
110 /// removeFromWorkList - remove all instances of N from the worklist.
112 void removeFromWorkList(SDNode *N) {
113 WorkListContents.erase(N);
116 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
119 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
120 return CombineTo(N, &Res, 1, AddTo);
123 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
125 SDValue To[] = { Res0, Res1 };
126 return CombineTo(N, To, 2, AddTo);
129 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
133 /// SimplifyDemandedBits - Check the specified integer node value to see if
134 /// it can be simplified or if things it uses can be simplified by bit
135 /// propagation. If so, return true.
136 bool SimplifyDemandedBits(SDValue Op) {
137 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
138 APInt Demanded = APInt::getAllOnesValue(BitWidth);
139 return SimplifyDemandedBits(Op, Demanded);
142 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
144 bool CombineToPreIndexedLoadStore(SDNode *N);
145 bool CombineToPostIndexedLoadStore(SDNode *N);
147 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
148 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
149 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
150 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
151 SDValue PromoteIntBinOp(SDValue Op);
152 SDValue PromoteIntShiftOp(SDValue Op);
153 SDValue PromoteExtend(SDValue Op);
154 bool PromoteLoad(SDValue Op);
156 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
157 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
158 ISD::NodeType ExtType);
160 /// combine - call the node-specific routine that knows how to fold each
161 /// particular type of node. If that doesn't do anything, try the
162 /// target-specific DAG combines.
163 SDValue combine(SDNode *N);
165 // Visitation implementation - Implement dag node combining for different
166 // node types. The semantics are as follows:
168 // SDValue.getNode() == 0 - No change was made
169 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
170 // otherwise - N should be replaced by the returned Operand.
172 SDValue visitTokenFactor(SDNode *N);
173 SDValue visitMERGE_VALUES(SDNode *N);
174 SDValue visitADD(SDNode *N);
175 SDValue visitSUB(SDNode *N);
176 SDValue visitADDC(SDNode *N);
177 SDValue visitSUBC(SDNode *N);
178 SDValue visitADDE(SDNode *N);
179 SDValue visitSUBE(SDNode *N);
180 SDValue visitMUL(SDNode *N);
181 SDValue visitSDIV(SDNode *N);
182 SDValue visitUDIV(SDNode *N);
183 SDValue visitSREM(SDNode *N);
184 SDValue visitUREM(SDNode *N);
185 SDValue visitMULHU(SDNode *N);
186 SDValue visitMULHS(SDNode *N);
187 SDValue visitSMUL_LOHI(SDNode *N);
188 SDValue visitUMUL_LOHI(SDNode *N);
189 SDValue visitSMULO(SDNode *N);
190 SDValue visitUMULO(SDNode *N);
191 SDValue visitSDIVREM(SDNode *N);
192 SDValue visitUDIVREM(SDNode *N);
193 SDValue visitAND(SDNode *N);
194 SDValue visitOR(SDNode *N);
195 SDValue visitXOR(SDNode *N);
196 SDValue SimplifyVBinOp(SDNode *N);
197 SDValue visitSHL(SDNode *N);
198 SDValue visitSRA(SDNode *N);
199 SDValue visitSRL(SDNode *N);
200 SDValue visitCTLZ(SDNode *N);
201 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
202 SDValue visitCTTZ(SDNode *N);
203 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
204 SDValue visitCTPOP(SDNode *N);
205 SDValue visitSELECT(SDNode *N);
206 SDValue visitSELECT_CC(SDNode *N);
207 SDValue visitSETCC(SDNode *N);
208 SDValue visitSIGN_EXTEND(SDNode *N);
209 SDValue visitZERO_EXTEND(SDNode *N);
210 SDValue visitANY_EXTEND(SDNode *N);
211 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
212 SDValue visitTRUNCATE(SDNode *N);
213 SDValue visitBITCAST(SDNode *N);
214 SDValue visitBUILD_PAIR(SDNode *N);
215 SDValue visitFADD(SDNode *N);
216 SDValue visitFSUB(SDNode *N);
217 SDValue visitFMUL(SDNode *N);
218 SDValue visitFDIV(SDNode *N);
219 SDValue visitFREM(SDNode *N);
220 SDValue visitFCOPYSIGN(SDNode *N);
221 SDValue visitSINT_TO_FP(SDNode *N);
222 SDValue visitUINT_TO_FP(SDNode *N);
223 SDValue visitFP_TO_SINT(SDNode *N);
224 SDValue visitFP_TO_UINT(SDNode *N);
225 SDValue visitFP_ROUND(SDNode *N);
226 SDValue visitFP_ROUND_INREG(SDNode *N);
227 SDValue visitFP_EXTEND(SDNode *N);
228 SDValue visitFNEG(SDNode *N);
229 SDValue visitFABS(SDNode *N);
230 SDValue visitBRCOND(SDNode *N);
231 SDValue visitBR_CC(SDNode *N);
232 SDValue visitLOAD(SDNode *N);
233 SDValue visitSTORE(SDNode *N);
234 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
235 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
236 SDValue visitBUILD_VECTOR(SDNode *N);
237 SDValue visitCONCAT_VECTORS(SDNode *N);
238 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
239 SDValue visitVECTOR_SHUFFLE(SDNode *N);
240 SDValue visitMEMBARRIER(SDNode *N);
242 SDValue XformToShuffleWithZero(SDNode *N);
243 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
245 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
247 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
248 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
249 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
250 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
251 SDValue N3, ISD::CondCode CC,
252 bool NotExtCompare = false);
253 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
254 DebugLoc DL, bool foldBooleans = true);
255 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
257 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
258 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
259 SDValue BuildSDIV(SDNode *N);
260 SDValue BuildUDIV(SDNode *N);
261 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
262 bool DemandHighBits = true);
263 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
264 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
265 SDValue ReduceLoadWidth(SDNode *N);
266 SDValue ReduceLoadOpStoreWidth(SDNode *N);
267 SDValue TransformFPLoadStorePair(SDNode *N);
269 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
271 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
272 /// looking for aliasing nodes and adding them to the Aliases vector.
273 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
274 SmallVector<SDValue, 8> &Aliases);
276 /// isAlias - Return true if there is any possibility that the two addresses
278 bool isAlias(SDValue Ptr1, int64_t Size1,
279 const Value *SrcValue1, int SrcValueOffset1,
280 unsigned SrcValueAlign1,
281 const MDNode *TBAAInfo1,
282 SDValue Ptr2, int64_t Size2,
283 const Value *SrcValue2, int SrcValueOffset2,
284 unsigned SrcValueAlign2,
285 const MDNode *TBAAInfo2) const;
287 /// FindAliasInfo - Extracts the relevant alias information from the memory
288 /// node. Returns true if the operand was a load.
289 bool FindAliasInfo(SDNode *N,
290 SDValue &Ptr, int64_t &Size,
291 const Value *&SrcValue, int &SrcValueOffset,
292 unsigned &SrcValueAlignment,
293 const MDNode *&TBAAInfo) const;
295 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
296 /// looking for a better chain (aliasing node.)
297 SDValue FindBetterChain(SDNode *N, SDValue Chain);
300 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
301 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
302 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
304 /// Run - runs the dag combiner on all nodes in the work list
305 void Run(CombineLevel AtLevel);
307 SelectionDAG &getDAG() const { return DAG; }
309 /// getShiftAmountTy - Returns a type large enough to hold any valid
310 /// shift amount - before type legalization these can be huge.
311 EVT getShiftAmountTy(EVT LHSTy) {
312 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy();
315 /// isTypeLegal - This method returns true if we are running before type
316 /// legalization or if the specified VT is legal.
317 bool isTypeLegal(const EVT &VT) {
318 if (!LegalTypes) return true;
319 return TLI.isTypeLegal(VT);
326 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
327 /// nodes from the worklist.
328 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
331 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
333 virtual void NodeDeleted(SDNode *N, SDNode *E) {
334 DC.removeFromWorkList(N);
337 virtual void NodeUpdated(SDNode *N) {
343 //===----------------------------------------------------------------------===//
344 // TargetLowering::DAGCombinerInfo implementation
345 //===----------------------------------------------------------------------===//
347 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
348 ((DAGCombiner*)DC)->AddToWorkList(N);
351 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
352 ((DAGCombiner*)DC)->removeFromWorkList(N);
355 SDValue TargetLowering::DAGCombinerInfo::
356 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
357 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
360 SDValue TargetLowering::DAGCombinerInfo::
361 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
362 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
366 SDValue TargetLowering::DAGCombinerInfo::
367 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
368 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
371 void TargetLowering::DAGCombinerInfo::
372 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
373 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
376 //===----------------------------------------------------------------------===//
378 //===----------------------------------------------------------------------===//
380 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
381 /// specified expression for the same cost as the expression itself, or 2 if we
382 /// can compute the negated form more cheaply than the expression itself.
383 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
384 const TargetLowering &TLI,
385 const TargetOptions *Options,
386 unsigned Depth = 0) {
387 // No compile time optimizations on this type.
388 if (Op.getValueType() == MVT::ppcf128)
391 // fneg is removable even if it has multiple uses.
392 if (Op.getOpcode() == ISD::FNEG) return 2;
394 // Don't allow anything with multiple uses.
395 if (!Op.hasOneUse()) return 0;
397 // Don't recurse exponentially.
398 if (Depth > 6) return 0;
400 switch (Op.getOpcode()) {
401 default: return false;
402 case ISD::ConstantFP:
403 // Don't invert constant FP values after legalize. The negated constant
404 // isn't necessarily legal.
405 return LegalOperations ? 0 : 1;
407 // FIXME: determine better conditions for this xform.
408 if (!Options->UnsafeFPMath) return 0;
410 // After operation legalization, it might not be legal to create new FSUBs.
411 if (LegalOperations &&
412 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
415 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
416 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
419 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
420 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
423 // We can't turn -(A-B) into B-A when we honor signed zeros.
424 if (!Options->UnsafeFPMath) return 0;
426 // fold (fneg (fsub A, B)) -> (fsub B, A)
431 if (Options->HonorSignDependentRoundingFPMath()) return 0;
433 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
434 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
438 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
444 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
449 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
450 /// returns the newly negated expression.
451 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
452 bool LegalOperations, unsigned Depth = 0) {
453 // fneg is removable even if it has multiple uses.
454 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
456 // Don't allow anything with multiple uses.
457 assert(Op.hasOneUse() && "Unknown reuse!");
459 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
460 switch (Op.getOpcode()) {
461 default: llvm_unreachable("Unknown code");
462 case ISD::ConstantFP: {
463 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
465 return DAG.getConstantFP(V, Op.getValueType());
468 // FIXME: determine better conditions for this xform.
469 assert(DAG.getTarget().Options.UnsafeFPMath);
471 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
472 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
473 DAG.getTargetLoweringInfo(),
474 &DAG.getTarget().Options, Depth+1))
475 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
476 GetNegatedExpression(Op.getOperand(0), DAG,
477 LegalOperations, Depth+1),
479 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
480 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
481 GetNegatedExpression(Op.getOperand(1), DAG,
482 LegalOperations, Depth+1),
485 // We can't turn -(A-B) into B-A when we honor signed zeros.
486 assert(DAG.getTarget().Options.UnsafeFPMath);
488 // fold (fneg (fsub 0, B)) -> B
489 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
490 if (N0CFP->getValueAPF().isZero())
491 return Op.getOperand(1);
493 // fold (fneg (fsub A, B)) -> (fsub B, A)
494 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
495 Op.getOperand(1), Op.getOperand(0));
499 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath());
501 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
502 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
503 DAG.getTargetLoweringInfo(),
504 &DAG.getTarget().Options, Depth+1))
505 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
506 GetNegatedExpression(Op.getOperand(0), DAG,
507 LegalOperations, Depth+1),
510 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
511 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
513 GetNegatedExpression(Op.getOperand(1), DAG,
514 LegalOperations, Depth+1));
518 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
519 GetNegatedExpression(Op.getOperand(0), DAG,
520 LegalOperations, Depth+1));
522 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
523 GetNegatedExpression(Op.getOperand(0), DAG,
524 LegalOperations, Depth+1),
530 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
531 // that selects between the values 1 and 0, making it equivalent to a setcc.
532 // Also, set the incoming LHS, RHS, and CC references to the appropriate
533 // nodes based on the type of node we are checking. This simplifies life a
534 // bit for the callers.
535 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
537 if (N.getOpcode() == ISD::SETCC) {
538 LHS = N.getOperand(0);
539 RHS = N.getOperand(1);
540 CC = N.getOperand(2);
543 if (N.getOpcode() == ISD::SELECT_CC &&
544 N.getOperand(2).getOpcode() == ISD::Constant &&
545 N.getOperand(3).getOpcode() == ISD::Constant &&
546 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
547 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
548 LHS = N.getOperand(0);
549 RHS = N.getOperand(1);
550 CC = N.getOperand(4);
556 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
557 // one use. If this is true, it allows the users to invert the operation for
558 // free when it is profitable to do so.
559 static bool isOneUseSetCC(SDValue N) {
561 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
566 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
567 SDValue N0, SDValue N1) {
568 EVT VT = N0.getValueType();
569 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
570 if (isa<ConstantSDNode>(N1)) {
571 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
573 DAG.FoldConstantArithmetic(Opc, VT,
574 cast<ConstantSDNode>(N0.getOperand(1)),
575 cast<ConstantSDNode>(N1));
576 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
578 if (N0.hasOneUse()) {
579 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
580 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
581 N0.getOperand(0), N1);
582 AddToWorkList(OpNode.getNode());
583 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
587 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
588 if (isa<ConstantSDNode>(N0)) {
589 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
591 DAG.FoldConstantArithmetic(Opc, VT,
592 cast<ConstantSDNode>(N1.getOperand(1)),
593 cast<ConstantSDNode>(N0));
594 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
596 if (N1.hasOneUse()) {
597 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
598 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
599 N1.getOperand(0), N0);
600 AddToWorkList(OpNode.getNode());
601 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
608 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
610 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
612 DEBUG(dbgs() << "\nReplacing.1 ";
614 dbgs() << "\nWith: ";
615 To[0].getNode()->dump(&DAG);
616 dbgs() << " and " << NumTo-1 << " other values\n";
617 for (unsigned i = 0, e = NumTo; i != e; ++i)
618 assert((!To[i].getNode() ||
619 N->getValueType(i) == To[i].getValueType()) &&
620 "Cannot combine value to value of different type!"));
621 WorkListRemover DeadNodes(*this);
622 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
625 // Push the new nodes and any users onto the worklist
626 for (unsigned i = 0, e = NumTo; i != e; ++i) {
627 if (To[i].getNode()) {
628 AddToWorkList(To[i].getNode());
629 AddUsersToWorkList(To[i].getNode());
634 // Finally, if the node is now dead, remove it from the graph. The node
635 // may not be dead if the replacement process recursively simplified to
636 // something else needing this node.
637 if (N->use_empty()) {
638 // Nodes can be reintroduced into the worklist. Make sure we do not
639 // process a node that has been replaced.
640 removeFromWorkList(N);
642 // Finally, since the node is now dead, remove it from the graph.
645 return SDValue(N, 0);
649 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
650 // Replace all uses. If any nodes become isomorphic to other nodes and
651 // are deleted, make sure to remove them from our worklist.
652 WorkListRemover DeadNodes(*this);
653 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
655 // Push the new node and any (possibly new) users onto the worklist.
656 AddToWorkList(TLO.New.getNode());
657 AddUsersToWorkList(TLO.New.getNode());
659 // Finally, if the node is now dead, remove it from the graph. The node
660 // may not be dead if the replacement process recursively simplified to
661 // something else needing this node.
662 if (TLO.Old.getNode()->use_empty()) {
663 removeFromWorkList(TLO.Old.getNode());
665 // If the operands of this node are only used by the node, they will now
666 // be dead. Make sure to visit them first to delete dead nodes early.
667 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
668 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
669 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
671 DAG.DeleteNode(TLO.Old.getNode());
675 /// SimplifyDemandedBits - Check the specified integer node value to see if
676 /// it can be simplified or if things it uses can be simplified by bit
677 /// propagation. If so, return true.
678 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
679 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
680 APInt KnownZero, KnownOne;
681 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
685 AddToWorkList(Op.getNode());
687 // Replace the old value with the new one.
689 DEBUG(dbgs() << "\nReplacing.2 ";
690 TLO.Old.getNode()->dump(&DAG);
691 dbgs() << "\nWith: ";
692 TLO.New.getNode()->dump(&DAG);
695 CommitTargetLoweringOpt(TLO);
699 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
700 DebugLoc dl = Load->getDebugLoc();
701 EVT VT = Load->getValueType(0);
702 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
704 DEBUG(dbgs() << "\nReplacing.9 ";
706 dbgs() << "\nWith: ";
707 Trunc.getNode()->dump(&DAG);
709 WorkListRemover DeadNodes(*this);
710 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes);
711 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1),
713 removeFromWorkList(Load);
714 DAG.DeleteNode(Load);
715 AddToWorkList(Trunc.getNode());
718 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
720 DebugLoc dl = Op.getDebugLoc();
721 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
722 EVT MemVT = LD->getMemoryVT();
723 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
724 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
726 : LD->getExtensionType();
728 return DAG.getExtLoad(ExtType, dl, PVT,
729 LD->getChain(), LD->getBasePtr(),
730 LD->getPointerInfo(),
731 MemVT, LD->isVolatile(),
732 LD->isNonTemporal(), LD->getAlignment());
735 unsigned Opc = Op.getOpcode();
738 case ISD::AssertSext:
739 return DAG.getNode(ISD::AssertSext, dl, PVT,
740 SExtPromoteOperand(Op.getOperand(0), PVT),
742 case ISD::AssertZext:
743 return DAG.getNode(ISD::AssertZext, dl, PVT,
744 ZExtPromoteOperand(Op.getOperand(0), PVT),
746 case ISD::Constant: {
748 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
749 return DAG.getNode(ExtOpc, dl, PVT, Op);
753 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
755 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
758 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
759 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
761 EVT OldVT = Op.getValueType();
762 DebugLoc dl = Op.getDebugLoc();
763 bool Replace = false;
764 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
765 if (NewOp.getNode() == 0)
767 AddToWorkList(NewOp.getNode());
770 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
771 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
772 DAG.getValueType(OldVT));
775 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
776 EVT OldVT = Op.getValueType();
777 DebugLoc dl = Op.getDebugLoc();
778 bool Replace = false;
779 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
780 if (NewOp.getNode() == 0)
782 AddToWorkList(NewOp.getNode());
785 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
786 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
789 /// PromoteIntBinOp - Promote the specified integer binary operation if the
790 /// target indicates it is beneficial. e.g. On x86, it's usually better to
791 /// promote i16 operations to i32 since i16 instructions are longer.
792 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
793 if (!LegalOperations)
796 EVT VT = Op.getValueType();
797 if (VT.isVector() || !VT.isInteger())
800 // If operation type is 'undesirable', e.g. i16 on x86, consider
802 unsigned Opc = Op.getOpcode();
803 if (TLI.isTypeDesirableForOp(Opc, VT))
807 // Consult target whether it is a good idea to promote this operation and
808 // what's the right type to promote it to.
809 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
810 assert(PVT != VT && "Don't know what type to promote to!");
812 bool Replace0 = false;
813 SDValue N0 = Op.getOperand(0);
814 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
815 if (NN0.getNode() == 0)
818 bool Replace1 = false;
819 SDValue N1 = Op.getOperand(1);
824 NN1 = PromoteOperand(N1, PVT, Replace1);
825 if (NN1.getNode() == 0)
829 AddToWorkList(NN0.getNode());
831 AddToWorkList(NN1.getNode());
834 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
836 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
838 DEBUG(dbgs() << "\nPromoting ";
839 Op.getNode()->dump(&DAG));
840 DebugLoc dl = Op.getDebugLoc();
841 return DAG.getNode(ISD::TRUNCATE, dl, VT,
842 DAG.getNode(Opc, dl, PVT, NN0, NN1));
847 /// PromoteIntShiftOp - Promote the specified integer shift operation if the
848 /// target indicates it is beneficial. e.g. On x86, it's usually better to
849 /// promote i16 operations to i32 since i16 instructions are longer.
850 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
851 if (!LegalOperations)
854 EVT VT = Op.getValueType();
855 if (VT.isVector() || !VT.isInteger())
858 // If operation type is 'undesirable', e.g. i16 on x86, consider
860 unsigned Opc = Op.getOpcode();
861 if (TLI.isTypeDesirableForOp(Opc, VT))
865 // Consult target whether it is a good idea to promote this operation and
866 // what's the right type to promote it to.
867 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
868 assert(PVT != VT && "Don't know what type to promote to!");
870 bool Replace = false;
871 SDValue N0 = Op.getOperand(0);
873 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
874 else if (Opc == ISD::SRL)
875 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
877 N0 = PromoteOperand(N0, PVT, Replace);
878 if (N0.getNode() == 0)
881 AddToWorkList(N0.getNode());
883 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
885 DEBUG(dbgs() << "\nPromoting ";
886 Op.getNode()->dump(&DAG));
887 DebugLoc dl = Op.getDebugLoc();
888 return DAG.getNode(ISD::TRUNCATE, dl, VT,
889 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
894 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
895 if (!LegalOperations)
898 EVT VT = Op.getValueType();
899 if (VT.isVector() || !VT.isInteger())
902 // If operation type is 'undesirable', e.g. i16 on x86, consider
904 unsigned Opc = Op.getOpcode();
905 if (TLI.isTypeDesirableForOp(Opc, VT))
909 // Consult target whether it is a good idea to promote this operation and
910 // what's the right type to promote it to.
911 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
912 assert(PVT != VT && "Don't know what type to promote to!");
913 // fold (aext (aext x)) -> (aext x)
914 // fold (aext (zext x)) -> (zext x)
915 // fold (aext (sext x)) -> (sext x)
916 DEBUG(dbgs() << "\nPromoting ";
917 Op.getNode()->dump(&DAG));
918 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0));
923 bool DAGCombiner::PromoteLoad(SDValue Op) {
924 if (!LegalOperations)
927 EVT VT = Op.getValueType();
928 if (VT.isVector() || !VT.isInteger())
931 // If operation type is 'undesirable', e.g. i16 on x86, consider
933 unsigned Opc = Op.getOpcode();
934 if (TLI.isTypeDesirableForOp(Opc, VT))
938 // Consult target whether it is a good idea to promote this operation and
939 // what's the right type to promote it to.
940 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
941 assert(PVT != VT && "Don't know what type to promote to!");
943 DebugLoc dl = Op.getDebugLoc();
944 SDNode *N = Op.getNode();
945 LoadSDNode *LD = cast<LoadSDNode>(N);
946 EVT MemVT = LD->getMemoryVT();
947 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
948 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
950 : LD->getExtensionType();
951 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
952 LD->getChain(), LD->getBasePtr(),
953 LD->getPointerInfo(),
954 MemVT, LD->isVolatile(),
955 LD->isNonTemporal(), LD->getAlignment());
956 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
958 DEBUG(dbgs() << "\nPromoting ";
961 Result.getNode()->dump(&DAG);
963 WorkListRemover DeadNodes(*this);
964 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes);
965 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes);
966 removeFromWorkList(N);
968 AddToWorkList(Result.getNode());
975 //===----------------------------------------------------------------------===//
976 // Main DAG Combiner implementation
977 //===----------------------------------------------------------------------===//
979 void DAGCombiner::Run(CombineLevel AtLevel) {
980 // set the instance variables, so that the various visit routines may use it.
982 LegalOperations = Level >= AfterLegalizeVectorOps;
983 LegalTypes = Level >= AfterLegalizeTypes;
985 // Add all the dag nodes to the worklist.
986 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
987 E = DAG.allnodes_end(); I != E; ++I)
990 // Create a dummy node (which is not added to allnodes), that adds a reference
991 // to the root node, preventing it from being deleted, and tracking any
992 // changes of the root.
993 HandleSDNode Dummy(DAG.getRoot());
995 // The root of the dag may dangle to deleted nodes until the dag combiner is
996 // done. Set it to null to avoid confusion.
997 DAG.setRoot(SDValue());
999 // while the worklist isn't empty, find a node and
1000 // try and combine it.
1001 while (!WorkListContents.empty()) {
1003 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates.
1004 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the
1005 // worklist *should* contain, and check the node we want to visit is should
1006 // actually be visited.
1008 N = WorkListOrder.back();
1009 WorkListOrder.pop_back();
1010 } while (!WorkListContents.erase(N));
1012 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1013 // N is deleted from the DAG, since they too may now be dead or may have a
1014 // reduced number of uses, allowing other xforms.
1015 if (N->use_empty() && N != &Dummy) {
1016 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1017 AddToWorkList(N->getOperand(i).getNode());
1023 SDValue RV = combine(N);
1025 if (RV.getNode() == 0)
1030 // If we get back the same node we passed in, rather than a new node or
1031 // zero, we know that the node must have defined multiple values and
1032 // CombineTo was used. Since CombineTo takes care of the worklist
1033 // mechanics for us, we have no work to do in this case.
1034 if (RV.getNode() == N)
1037 assert(N->getOpcode() != ISD::DELETED_NODE &&
1038 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1039 "Node was deleted but visit returned new node!");
1041 DEBUG(dbgs() << "\nReplacing.3 ";
1043 dbgs() << "\nWith: ";
1044 RV.getNode()->dump(&DAG);
1047 // Transfer debug value.
1048 DAG.TransferDbgValues(SDValue(N, 0), RV);
1049 WorkListRemover DeadNodes(*this);
1050 if (N->getNumValues() == RV.getNode()->getNumValues())
1051 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
1053 assert(N->getValueType(0) == RV.getValueType() &&
1054 N->getNumValues() == 1 && "Type mismatch");
1056 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
1059 // Push the new node and any users onto the worklist
1060 AddToWorkList(RV.getNode());
1061 AddUsersToWorkList(RV.getNode());
1063 // Add any uses of the old node to the worklist in case this node is the
1064 // last one that uses them. They may become dead after this node is
1066 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1067 AddToWorkList(N->getOperand(i).getNode());
1069 // Finally, if the node is now dead, remove it from the graph. The node
1070 // may not be dead if the replacement process recursively simplified to
1071 // something else needing this node.
1072 if (N->use_empty()) {
1073 // Nodes can be reintroduced into the worklist. Make sure we do not
1074 // process a node that has been replaced.
1075 removeFromWorkList(N);
1077 // Finally, since the node is now dead, remove it from the graph.
1082 // If the root changed (e.g. it was a dead load, update the root).
1083 DAG.setRoot(Dummy.getValue());
1086 SDValue DAGCombiner::visit(SDNode *N) {
1087 switch (N->getOpcode()) {
1089 case ISD::TokenFactor: return visitTokenFactor(N);
1090 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1091 case ISD::ADD: return visitADD(N);
1092 case ISD::SUB: return visitSUB(N);
1093 case ISD::ADDC: return visitADDC(N);
1094 case ISD::SUBC: return visitSUBC(N);
1095 case ISD::ADDE: return visitADDE(N);
1096 case ISD::SUBE: return visitSUBE(N);
1097 case ISD::MUL: return visitMUL(N);
1098 case ISD::SDIV: return visitSDIV(N);
1099 case ISD::UDIV: return visitUDIV(N);
1100 case ISD::SREM: return visitSREM(N);
1101 case ISD::UREM: return visitUREM(N);
1102 case ISD::MULHU: return visitMULHU(N);
1103 case ISD::MULHS: return visitMULHS(N);
1104 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1105 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1106 case ISD::SMULO: return visitSMULO(N);
1107 case ISD::UMULO: return visitUMULO(N);
1108 case ISD::SDIVREM: return visitSDIVREM(N);
1109 case ISD::UDIVREM: return visitUDIVREM(N);
1110 case ISD::AND: return visitAND(N);
1111 case ISD::OR: return visitOR(N);
1112 case ISD::XOR: return visitXOR(N);
1113 case ISD::SHL: return visitSHL(N);
1114 case ISD::SRA: return visitSRA(N);
1115 case ISD::SRL: return visitSRL(N);
1116 case ISD::CTLZ: return visitCTLZ(N);
1117 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1118 case ISD::CTTZ: return visitCTTZ(N);
1119 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1120 case ISD::CTPOP: return visitCTPOP(N);
1121 case ISD::SELECT: return visitSELECT(N);
1122 case ISD::SELECT_CC: return visitSELECT_CC(N);
1123 case ISD::SETCC: return visitSETCC(N);
1124 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1125 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1126 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1127 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1128 case ISD::TRUNCATE: return visitTRUNCATE(N);
1129 case ISD::BITCAST: return visitBITCAST(N);
1130 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1131 case ISD::FADD: return visitFADD(N);
1132 case ISD::FSUB: return visitFSUB(N);
1133 case ISD::FMUL: return visitFMUL(N);
1134 case ISD::FDIV: return visitFDIV(N);
1135 case ISD::FREM: return visitFREM(N);
1136 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1137 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1138 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1139 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1140 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1141 case ISD::FP_ROUND: return visitFP_ROUND(N);
1142 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1143 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1144 case ISD::FNEG: return visitFNEG(N);
1145 case ISD::FABS: return visitFABS(N);
1146 case ISD::BRCOND: return visitBRCOND(N);
1147 case ISD::BR_CC: return visitBR_CC(N);
1148 case ISD::LOAD: return visitLOAD(N);
1149 case ISD::STORE: return visitSTORE(N);
1150 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1151 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1152 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1153 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1154 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1155 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1156 case ISD::MEMBARRIER: return visitMEMBARRIER(N);
1161 SDValue DAGCombiner::combine(SDNode *N) {
1162 SDValue RV = visit(N);
1164 // If nothing happened, try a target-specific DAG combine.
1165 if (RV.getNode() == 0) {
1166 assert(N->getOpcode() != ISD::DELETED_NODE &&
1167 "Node was deleted but visit returned NULL!");
1169 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1170 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1172 // Expose the DAG combiner to the target combiner impls.
1173 TargetLowering::DAGCombinerInfo
1174 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
1176 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1180 // If nothing happened still, try promoting the operation.
1181 if (RV.getNode() == 0) {
1182 switch (N->getOpcode()) {
1190 RV = PromoteIntBinOp(SDValue(N, 0));
1195 RV = PromoteIntShiftOp(SDValue(N, 0));
1197 case ISD::SIGN_EXTEND:
1198 case ISD::ZERO_EXTEND:
1199 case ISD::ANY_EXTEND:
1200 RV = PromoteExtend(SDValue(N, 0));
1203 if (PromoteLoad(SDValue(N, 0)))
1209 // If N is a commutative binary node, try commuting it to enable more
1211 if (RV.getNode() == 0 &&
1212 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1213 N->getNumValues() == 1) {
1214 SDValue N0 = N->getOperand(0);
1215 SDValue N1 = N->getOperand(1);
1217 // Constant operands are canonicalized to RHS.
1218 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1219 SDValue Ops[] = { N1, N0 };
1220 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1223 return SDValue(CSENode, 0);
1230 /// getInputChainForNode - Given a node, return its input chain if it has one,
1231 /// otherwise return a null sd operand.
1232 static SDValue getInputChainForNode(SDNode *N) {
1233 if (unsigned NumOps = N->getNumOperands()) {
1234 if (N->getOperand(0).getValueType() == MVT::Other)
1235 return N->getOperand(0);
1236 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1237 return N->getOperand(NumOps-1);
1238 for (unsigned i = 1; i < NumOps-1; ++i)
1239 if (N->getOperand(i).getValueType() == MVT::Other)
1240 return N->getOperand(i);
1245 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1246 // If N has two operands, where one has an input chain equal to the other,
1247 // the 'other' chain is redundant.
1248 if (N->getNumOperands() == 2) {
1249 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1250 return N->getOperand(0);
1251 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1252 return N->getOperand(1);
1255 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1256 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1257 SmallPtrSet<SDNode*, 16> SeenOps;
1258 bool Changed = false; // If we should replace this token factor.
1260 // Start out with this token factor.
1263 // Iterate through token factors. The TFs grows when new token factors are
1265 for (unsigned i = 0; i < TFs.size(); ++i) {
1266 SDNode *TF = TFs[i];
1268 // Check each of the operands.
1269 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1270 SDValue Op = TF->getOperand(i);
1272 switch (Op.getOpcode()) {
1273 case ISD::EntryToken:
1274 // Entry tokens don't need to be added to the list. They are
1279 case ISD::TokenFactor:
1280 if (Op.hasOneUse() &&
1281 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1282 // Queue up for processing.
1283 TFs.push_back(Op.getNode());
1284 // Clean up in case the token factor is removed.
1285 AddToWorkList(Op.getNode());
1292 // Only add if it isn't already in the list.
1293 if (SeenOps.insert(Op.getNode()))
1304 // If we've change things around then replace token factor.
1307 // The entry token is the only possible outcome.
1308 Result = DAG.getEntryNode();
1310 // New and improved token factor.
1311 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
1312 MVT::Other, &Ops[0], Ops.size());
1315 // Don't add users to work list.
1316 return CombineTo(N, Result, false);
1322 /// MERGE_VALUES can always be eliminated.
1323 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1324 WorkListRemover DeadNodes(*this);
1325 // Replacing results may cause a different MERGE_VALUES to suddenly
1326 // be CSE'd with N, and carry its uses with it. Iterate until no
1327 // uses remain, to ensure that the node can be safely deleted.
1329 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1330 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
1332 } while (!N->use_empty());
1333 removeFromWorkList(N);
1335 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1339 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
1340 SelectionDAG &DAG) {
1341 EVT VT = N0.getValueType();
1342 SDValue N00 = N0.getOperand(0);
1343 SDValue N01 = N0.getOperand(1);
1344 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1346 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1347 isa<ConstantSDNode>(N00.getOperand(1))) {
1348 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1349 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1350 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1351 N00.getOperand(0), N01),
1352 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1353 N00.getOperand(1), N01));
1354 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1360 SDValue DAGCombiner::visitADD(SDNode *N) {
1361 SDValue N0 = N->getOperand(0);
1362 SDValue N1 = N->getOperand(1);
1363 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1364 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1365 EVT VT = N0.getValueType();
1368 if (VT.isVector()) {
1369 SDValue FoldedVOp = SimplifyVBinOp(N);
1370 if (FoldedVOp.getNode()) return FoldedVOp;
1373 // fold (add x, undef) -> undef
1374 if (N0.getOpcode() == ISD::UNDEF)
1376 if (N1.getOpcode() == ISD::UNDEF)
1378 // fold (add c1, c2) -> c1+c2
1380 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1381 // canonicalize constant to RHS
1383 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1384 // fold (add x, 0) -> x
1385 if (N1C && N1C->isNullValue())
1387 // fold (add Sym, c) -> Sym+c
1388 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1389 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1390 GA->getOpcode() == ISD::GlobalAddress)
1391 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1393 (uint64_t)N1C->getSExtValue());
1394 // fold ((c1-A)+c2) -> (c1+c2)-A
1395 if (N1C && N0.getOpcode() == ISD::SUB)
1396 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1397 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1398 DAG.getConstant(N1C->getAPIntValue()+
1399 N0C->getAPIntValue(), VT),
1402 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1403 if (RADD.getNode() != 0)
1405 // fold ((0-A) + B) -> B-A
1406 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1407 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1408 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1409 // fold (A + (0-B)) -> A-B
1410 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1411 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1412 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1413 // fold (A+(B-A)) -> B
1414 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1415 return N1.getOperand(0);
1416 // fold ((B-A)+A) -> B
1417 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1418 return N0.getOperand(0);
1419 // fold (A+(B-(A+C))) to (B-C)
1420 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1421 N0 == N1.getOperand(1).getOperand(0))
1422 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1423 N1.getOperand(1).getOperand(1));
1424 // fold (A+(B-(C+A))) to (B-C)
1425 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1426 N0 == N1.getOperand(1).getOperand(1))
1427 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1428 N1.getOperand(1).getOperand(0));
1429 // fold (A+((B-A)+or-C)) to (B+or-C)
1430 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1431 N1.getOperand(0).getOpcode() == ISD::SUB &&
1432 N0 == N1.getOperand(0).getOperand(1))
1433 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1434 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1436 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1437 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1438 SDValue N00 = N0.getOperand(0);
1439 SDValue N01 = N0.getOperand(1);
1440 SDValue N10 = N1.getOperand(0);
1441 SDValue N11 = N1.getOperand(1);
1443 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1444 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1445 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1446 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1449 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1450 return SDValue(N, 0);
1452 // fold (a+b) -> (a|b) iff a and b share no bits.
1453 if (VT.isInteger() && !VT.isVector()) {
1454 APInt LHSZero, LHSOne;
1455 APInt RHSZero, RHSOne;
1456 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1457 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1459 if (LHSZero.getBoolValue()) {
1460 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1462 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1463 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1464 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1465 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1466 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1470 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1471 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1472 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1473 if (Result.getNode()) return Result;
1475 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1476 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1477 if (Result.getNode()) return Result;
1480 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1481 if (N1.getOpcode() == ISD::SHL &&
1482 N1.getOperand(0).getOpcode() == ISD::SUB)
1483 if (ConstantSDNode *C =
1484 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1485 if (C->getAPIntValue() == 0)
1486 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1487 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1488 N1.getOperand(0).getOperand(1),
1490 if (N0.getOpcode() == ISD::SHL &&
1491 N0.getOperand(0).getOpcode() == ISD::SUB)
1492 if (ConstantSDNode *C =
1493 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1494 if (C->getAPIntValue() == 0)
1495 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1496 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1497 N0.getOperand(0).getOperand(1),
1500 if (N1.getOpcode() == ISD::AND) {
1501 SDValue AndOp0 = N1.getOperand(0);
1502 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1503 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1504 unsigned DestBits = VT.getScalarType().getSizeInBits();
1506 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1507 // and similar xforms where the inner op is either ~0 or 0.
1508 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1509 DebugLoc DL = N->getDebugLoc();
1510 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1514 // add (sext i1), X -> sub X, (zext i1)
1515 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1516 N0.getOperand(0).getValueType() == MVT::i1 &&
1517 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1518 DebugLoc DL = N->getDebugLoc();
1519 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1520 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1526 SDValue DAGCombiner::visitADDC(SDNode *N) {
1527 SDValue N0 = N->getOperand(0);
1528 SDValue N1 = N->getOperand(1);
1529 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1530 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1531 EVT VT = N0.getValueType();
1533 // If the flag result is dead, turn this into an ADD.
1534 if (!N->hasAnyUseOfValue(1))
1535 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1),
1536 DAG.getNode(ISD::CARRY_FALSE,
1537 N->getDebugLoc(), MVT::Glue));
1539 // canonicalize constant to RHS.
1541 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1543 // fold (addc x, 0) -> x + no carry out
1544 if (N1C && N1C->isNullValue())
1545 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1546 N->getDebugLoc(), MVT::Glue));
1548 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1549 APInt LHSZero, LHSOne;
1550 APInt RHSZero, RHSOne;
1551 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1552 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1554 if (LHSZero.getBoolValue()) {
1555 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1557 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1558 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1559 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1560 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1561 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1562 DAG.getNode(ISD::CARRY_FALSE,
1563 N->getDebugLoc(), MVT::Glue));
1569 SDValue DAGCombiner::visitADDE(SDNode *N) {
1570 SDValue N0 = N->getOperand(0);
1571 SDValue N1 = N->getOperand(1);
1572 SDValue CarryIn = N->getOperand(2);
1573 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1574 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1576 // canonicalize constant to RHS
1578 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1581 // fold (adde x, y, false) -> (addc x, y)
1582 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1583 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1);
1588 // Since it may not be valid to emit a fold to zero for vector initializers
1589 // check if we can before folding.
1590 static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT,
1591 SelectionDAG &DAG, bool LegalOperations) {
1592 if (!VT.isVector()) {
1593 return DAG.getConstant(0, VT);
1595 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1596 // Produce a vector of zeros.
1597 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
1598 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
1599 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
1600 &Ops[0], Ops.size());
1605 SDValue DAGCombiner::visitSUB(SDNode *N) {
1606 SDValue N0 = N->getOperand(0);
1607 SDValue N1 = N->getOperand(1);
1608 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1609 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1610 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 :
1611 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1612 EVT VT = N0.getValueType();
1615 if (VT.isVector()) {
1616 SDValue FoldedVOp = SimplifyVBinOp(N);
1617 if (FoldedVOp.getNode()) return FoldedVOp;
1620 // fold (sub x, x) -> 0
1621 // FIXME: Refactor this and xor and other similar operations together.
1623 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
1624 // fold (sub c1, c2) -> c1-c2
1626 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1627 // fold (sub x, c) -> (add x, -c)
1629 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1630 DAG.getConstant(-N1C->getAPIntValue(), VT));
1631 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1632 if (N0C && N0C->isAllOnesValue())
1633 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1634 // fold A-(A-B) -> B
1635 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1636 return N1.getOperand(1);
1637 // fold (A+B)-A -> B
1638 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1639 return N0.getOperand(1);
1640 // fold (A+B)-B -> A
1641 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1642 return N0.getOperand(0);
1643 // fold C2-(A+C1) -> (C2-C1)-A
1644 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1645 SDValue NewC = DAG.getConstant((N0C->getAPIntValue() - N1C1->getAPIntValue()), VT);
1646 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC,
1649 // fold ((A+(B+or-C))-B) -> A+or-C
1650 if (N0.getOpcode() == ISD::ADD &&
1651 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1652 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1653 N0.getOperand(1).getOperand(0) == N1)
1654 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1655 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1656 // fold ((A+(C+B))-B) -> A+C
1657 if (N0.getOpcode() == ISD::ADD &&
1658 N0.getOperand(1).getOpcode() == ISD::ADD &&
1659 N0.getOperand(1).getOperand(1) == N1)
1660 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1661 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1662 // fold ((A-(B-C))-C) -> A-B
1663 if (N0.getOpcode() == ISD::SUB &&
1664 N0.getOperand(1).getOpcode() == ISD::SUB &&
1665 N0.getOperand(1).getOperand(1) == N1)
1666 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1667 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1669 // If either operand of a sub is undef, the result is undef
1670 if (N0.getOpcode() == ISD::UNDEF)
1672 if (N1.getOpcode() == ISD::UNDEF)
1675 // If the relocation model supports it, consider symbol offsets.
1676 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1677 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1678 // fold (sub Sym, c) -> Sym-c
1679 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1680 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1682 (uint64_t)N1C->getSExtValue());
1683 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1684 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1685 if (GA->getGlobal() == GB->getGlobal())
1686 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1693 SDValue DAGCombiner::visitSUBC(SDNode *N) {
1694 SDValue N0 = N->getOperand(0);
1695 SDValue N1 = N->getOperand(1);
1696 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1697 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1698 EVT VT = N0.getValueType();
1700 // If the flag result is dead, turn this into an SUB.
1701 if (!N->hasAnyUseOfValue(1))
1702 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1),
1703 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1706 // fold (subc x, x) -> 0 + no borrow
1708 return CombineTo(N, DAG.getConstant(0, VT),
1709 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1712 // fold (subc x, 0) -> x + no borrow
1713 if (N1C && N1C->isNullValue())
1714 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1717 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
1718 if (N0C && N0C->isAllOnesValue())
1719 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0),
1720 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1726 SDValue DAGCombiner::visitSUBE(SDNode *N) {
1727 SDValue N0 = N->getOperand(0);
1728 SDValue N1 = N->getOperand(1);
1729 SDValue CarryIn = N->getOperand(2);
1731 // fold (sube x, y, false) -> (subc x, y)
1732 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1733 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1);
1738 SDValue DAGCombiner::visitMUL(SDNode *N) {
1739 SDValue N0 = N->getOperand(0);
1740 SDValue N1 = N->getOperand(1);
1741 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1742 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1743 EVT VT = N0.getValueType();
1746 if (VT.isVector()) {
1747 SDValue FoldedVOp = SimplifyVBinOp(N);
1748 if (FoldedVOp.getNode()) return FoldedVOp;
1751 // fold (mul x, undef) -> 0
1752 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1753 return DAG.getConstant(0, VT);
1754 // fold (mul c1, c2) -> c1*c2
1756 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1757 // canonicalize constant to RHS
1759 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1760 // fold (mul x, 0) -> 0
1761 if (N1C && N1C->isNullValue())
1763 // fold (mul x, -1) -> 0-x
1764 if (N1C && N1C->isAllOnesValue())
1765 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1766 DAG.getConstant(0, VT), N0);
1767 // fold (mul x, (1 << c)) -> x << c
1768 if (N1C && N1C->getAPIntValue().isPowerOf2())
1769 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1770 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1771 getShiftAmountTy(N0.getValueType())));
1772 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1773 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1774 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1775 // FIXME: If the input is something that is easily negated (e.g. a
1776 // single-use add), we should put the negate there.
1777 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1778 DAG.getConstant(0, VT),
1779 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1780 DAG.getConstant(Log2Val,
1781 getShiftAmountTy(N0.getValueType()))));
1783 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1784 if (N1C && N0.getOpcode() == ISD::SHL &&
1785 isa<ConstantSDNode>(N0.getOperand(1))) {
1786 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1787 N1, N0.getOperand(1));
1788 AddToWorkList(C3.getNode());
1789 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1790 N0.getOperand(0), C3);
1793 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1796 SDValue Sh(0,0), Y(0,0);
1797 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1798 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1799 N0.getNode()->hasOneUse()) {
1801 } else if (N1.getOpcode() == ISD::SHL &&
1802 isa<ConstantSDNode>(N1.getOperand(1)) &&
1803 N1.getNode()->hasOneUse()) {
1808 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1809 Sh.getOperand(0), Y);
1810 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1811 Mul, Sh.getOperand(1));
1815 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1816 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1817 isa<ConstantSDNode>(N0.getOperand(1)))
1818 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1819 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1820 N0.getOperand(0), N1),
1821 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1822 N0.getOperand(1), N1));
1825 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1826 if (RMUL.getNode() != 0)
1832 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1833 SDValue N0 = N->getOperand(0);
1834 SDValue N1 = N->getOperand(1);
1835 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1836 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1837 EVT VT = N->getValueType(0);
1840 if (VT.isVector()) {
1841 SDValue FoldedVOp = SimplifyVBinOp(N);
1842 if (FoldedVOp.getNode()) return FoldedVOp;
1845 // fold (sdiv c1, c2) -> c1/c2
1846 if (N0C && N1C && !N1C->isNullValue())
1847 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1848 // fold (sdiv X, 1) -> X
1849 if (N1C && N1C->getAPIntValue() == 1LL)
1851 // fold (sdiv X, -1) -> 0-X
1852 if (N1C && N1C->isAllOnesValue())
1853 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1854 DAG.getConstant(0, VT), N0);
1855 // If we know the sign bits of both operands are zero, strength reduce to a
1856 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1857 if (!VT.isVector()) {
1858 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1859 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1862 // fold (sdiv X, pow2) -> simple ops after legalize
1863 if (N1C && !N1C->isNullValue() &&
1864 (N1C->getAPIntValue().isPowerOf2() ||
1865 (-N1C->getAPIntValue()).isPowerOf2())) {
1866 // If dividing by powers of two is cheap, then don't perform the following
1868 if (TLI.isPow2DivCheap())
1871 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
1873 // Splat the sign bit into the register
1874 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1875 DAG.getConstant(VT.getSizeInBits()-1,
1876 getShiftAmountTy(N0.getValueType())));
1877 AddToWorkList(SGN.getNode());
1879 // Add (N0 < 0) ? abs2 - 1 : 0;
1880 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1881 DAG.getConstant(VT.getSizeInBits() - lg2,
1882 getShiftAmountTy(SGN.getValueType())));
1883 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1884 AddToWorkList(SRL.getNode());
1885 AddToWorkList(ADD.getNode()); // Divide by pow2
1886 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1887 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
1889 // If we're dividing by a positive value, we're done. Otherwise, we must
1890 // negate the result.
1891 if (N1C->getAPIntValue().isNonNegative())
1894 AddToWorkList(SRA.getNode());
1895 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1896 DAG.getConstant(0, VT), SRA);
1899 // if integer divide is expensive and we satisfy the requirements, emit an
1900 // alternate sequence.
1901 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1902 SDValue Op = BuildSDIV(N);
1903 if (Op.getNode()) return Op;
1907 if (N0.getOpcode() == ISD::UNDEF)
1908 return DAG.getConstant(0, VT);
1909 // X / undef -> undef
1910 if (N1.getOpcode() == ISD::UNDEF)
1916 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1917 SDValue N0 = N->getOperand(0);
1918 SDValue N1 = N->getOperand(1);
1919 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1920 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1921 EVT VT = N->getValueType(0);
1924 if (VT.isVector()) {
1925 SDValue FoldedVOp = SimplifyVBinOp(N);
1926 if (FoldedVOp.getNode()) return FoldedVOp;
1929 // fold (udiv c1, c2) -> c1/c2
1930 if (N0C && N1C && !N1C->isNullValue())
1931 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1932 // fold (udiv x, (1 << c)) -> x >>u c
1933 if (N1C && N1C->getAPIntValue().isPowerOf2())
1934 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1935 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1936 getShiftAmountTy(N0.getValueType())));
1937 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1938 if (N1.getOpcode() == ISD::SHL) {
1939 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1940 if (SHC->getAPIntValue().isPowerOf2()) {
1941 EVT ADDVT = N1.getOperand(1).getValueType();
1942 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1944 DAG.getConstant(SHC->getAPIntValue()
1947 AddToWorkList(Add.getNode());
1948 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1952 // fold (udiv x, c) -> alternate
1953 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1954 SDValue Op = BuildUDIV(N);
1955 if (Op.getNode()) return Op;
1959 if (N0.getOpcode() == ISD::UNDEF)
1960 return DAG.getConstant(0, VT);
1961 // X / undef -> undef
1962 if (N1.getOpcode() == ISD::UNDEF)
1968 SDValue DAGCombiner::visitSREM(SDNode *N) {
1969 SDValue N0 = N->getOperand(0);
1970 SDValue N1 = N->getOperand(1);
1971 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1972 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1973 EVT VT = N->getValueType(0);
1975 // fold (srem c1, c2) -> c1%c2
1976 if (N0C && N1C && !N1C->isNullValue())
1977 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1978 // If we know the sign bits of both operands are zero, strength reduce to a
1979 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1980 if (!VT.isVector()) {
1981 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1982 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1985 // If X/C can be simplified by the division-by-constant logic, lower
1986 // X%C to the equivalent of X-X/C*C.
1987 if (N1C && !N1C->isNullValue()) {
1988 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1989 AddToWorkList(Div.getNode());
1990 SDValue OptimizedDiv = combine(Div.getNode());
1991 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1992 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1994 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1995 AddToWorkList(Mul.getNode());
2001 if (N0.getOpcode() == ISD::UNDEF)
2002 return DAG.getConstant(0, VT);
2003 // X % undef -> undef
2004 if (N1.getOpcode() == ISD::UNDEF)
2010 SDValue DAGCombiner::visitUREM(SDNode *N) {
2011 SDValue N0 = N->getOperand(0);
2012 SDValue N1 = N->getOperand(1);
2013 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2014 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2015 EVT VT = N->getValueType(0);
2017 // fold (urem c1, c2) -> c1%c2
2018 if (N0C && N1C && !N1C->isNullValue())
2019 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
2020 // fold (urem x, pow2) -> (and x, pow2-1)
2021 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
2022 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
2023 DAG.getConstant(N1C->getAPIntValue()-1,VT));
2024 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
2025 if (N1.getOpcode() == ISD::SHL) {
2026 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2027 if (SHC->getAPIntValue().isPowerOf2()) {
2029 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
2030 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
2032 AddToWorkList(Add.getNode());
2033 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
2038 // If X/C can be simplified by the division-by-constant logic, lower
2039 // X%C to the equivalent of X-X/C*C.
2040 if (N1C && !N1C->isNullValue()) {
2041 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
2042 AddToWorkList(Div.getNode());
2043 SDValue OptimizedDiv = combine(Div.getNode());
2044 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2045 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
2047 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
2048 AddToWorkList(Mul.getNode());
2054 if (N0.getOpcode() == ISD::UNDEF)
2055 return DAG.getConstant(0, VT);
2056 // X % undef -> undef
2057 if (N1.getOpcode() == ISD::UNDEF)
2063 SDValue DAGCombiner::visitMULHS(SDNode *N) {
2064 SDValue N0 = N->getOperand(0);
2065 SDValue N1 = N->getOperand(1);
2066 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2067 EVT VT = N->getValueType(0);
2068 DebugLoc DL = N->getDebugLoc();
2070 // fold (mulhs x, 0) -> 0
2071 if (N1C && N1C->isNullValue())
2073 // fold (mulhs x, 1) -> (sra x, size(x)-1)
2074 if (N1C && N1C->getAPIntValue() == 1)
2075 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
2076 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2077 getShiftAmountTy(N0.getValueType())));
2078 // fold (mulhs x, undef) -> 0
2079 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2080 return DAG.getConstant(0, VT);
2082 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2084 if (VT.isSimple() && !VT.isVector()) {
2085 MVT Simple = VT.getSimpleVT();
2086 unsigned SimpleSize = Simple.getSizeInBits();
2087 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2088 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2089 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2090 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2091 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2092 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2093 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2094 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2101 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2102 SDValue N0 = N->getOperand(0);
2103 SDValue N1 = N->getOperand(1);
2104 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2105 EVT VT = N->getValueType(0);
2106 DebugLoc DL = N->getDebugLoc();
2108 // fold (mulhu x, 0) -> 0
2109 if (N1C && N1C->isNullValue())
2111 // fold (mulhu x, 1) -> 0
2112 if (N1C && N1C->getAPIntValue() == 1)
2113 return DAG.getConstant(0, N0.getValueType());
2114 // fold (mulhu x, undef) -> 0
2115 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2116 return DAG.getConstant(0, VT);
2118 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2120 if (VT.isSimple() && !VT.isVector()) {
2121 MVT Simple = VT.getSimpleVT();
2122 unsigned SimpleSize = Simple.getSizeInBits();
2123 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2124 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2125 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2126 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2127 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2128 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2129 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2130 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2137 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
2138 /// compute two values. LoOp and HiOp give the opcodes for the two computations
2139 /// that are being performed. Return true if a simplification was made.
2141 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2143 // If the high half is not needed, just compute the low half.
2144 bool HiExists = N->hasAnyUseOfValue(1);
2146 (!LegalOperations ||
2147 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
2148 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2149 N->op_begin(), N->getNumOperands());
2150 return CombineTo(N, Res, Res);
2153 // If the low half is not needed, just compute the high half.
2154 bool LoExists = N->hasAnyUseOfValue(0);
2156 (!LegalOperations ||
2157 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2158 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2159 N->op_begin(), N->getNumOperands());
2160 return CombineTo(N, Res, Res);
2163 // If both halves are used, return as it is.
2164 if (LoExists && HiExists)
2167 // If the two computed results can be simplified separately, separate them.
2169 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2170 N->op_begin(), N->getNumOperands());
2171 AddToWorkList(Lo.getNode());
2172 SDValue LoOpt = combine(Lo.getNode());
2173 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2174 (!LegalOperations ||
2175 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2176 return CombineTo(N, LoOpt, LoOpt);
2180 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2181 N->op_begin(), N->getNumOperands());
2182 AddToWorkList(Hi.getNode());
2183 SDValue HiOpt = combine(Hi.getNode());
2184 if (HiOpt.getNode() && HiOpt != Hi &&
2185 (!LegalOperations ||
2186 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2187 return CombineTo(N, HiOpt, HiOpt);
2193 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2194 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2195 if (Res.getNode()) return Res;
2197 EVT VT = N->getValueType(0);
2198 DebugLoc DL = N->getDebugLoc();
2200 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2202 if (VT.isSimple() && !VT.isVector()) {
2203 MVT Simple = VT.getSimpleVT();
2204 unsigned SimpleSize = Simple.getSizeInBits();
2205 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2206 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2207 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2208 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2209 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2210 // Compute the high part as N1.
2211 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2212 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2213 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2214 // Compute the low part as N0.
2215 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2216 return CombineTo(N, Lo, Hi);
2223 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2224 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2225 if (Res.getNode()) return Res;
2227 EVT VT = N->getValueType(0);
2228 DebugLoc DL = N->getDebugLoc();
2230 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2232 if (VT.isSimple() && !VT.isVector()) {
2233 MVT Simple = VT.getSimpleVT();
2234 unsigned SimpleSize = Simple.getSizeInBits();
2235 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2236 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2237 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2238 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2239 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2240 // Compute the high part as N1.
2241 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2242 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2243 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2244 // Compute the low part as N0.
2245 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2246 return CombineTo(N, Lo, Hi);
2253 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2254 // (smulo x, 2) -> (saddo x, x)
2255 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2256 if (C2->getAPIntValue() == 2)
2257 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(),
2258 N->getOperand(0), N->getOperand(0));
2263 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2264 // (umulo x, 2) -> (uaddo x, x)
2265 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2266 if (C2->getAPIntValue() == 2)
2267 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(),
2268 N->getOperand(0), N->getOperand(0));
2273 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2274 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2275 if (Res.getNode()) return Res;
2280 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2281 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2282 if (Res.getNode()) return Res;
2287 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2288 /// two operands of the same opcode, try to simplify it.
2289 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2290 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2291 EVT VT = N0.getValueType();
2292 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2294 // Bail early if none of these transforms apply.
2295 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2297 // For each of OP in AND/OR/XOR:
2298 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2299 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2300 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2301 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2303 // do not sink logical op inside of a vector extend, since it may combine
2305 EVT Op0VT = N0.getOperand(0).getValueType();
2306 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2307 N0.getOpcode() == ISD::SIGN_EXTEND ||
2308 // Avoid infinite looping with PromoteIntBinOp.
2309 (N0.getOpcode() == ISD::ANY_EXTEND &&
2310 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2311 (N0.getOpcode() == ISD::TRUNCATE &&
2312 (!TLI.isZExtFree(VT, Op0VT) ||
2313 !TLI.isTruncateFree(Op0VT, VT)) &&
2314 TLI.isTypeLegal(Op0VT))) &&
2316 Op0VT == N1.getOperand(0).getValueType() &&
2317 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2318 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2319 N0.getOperand(0).getValueType(),
2320 N0.getOperand(0), N1.getOperand(0));
2321 AddToWorkList(ORNode.getNode());
2322 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
2325 // For each of OP in SHL/SRL/SRA/AND...
2326 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2327 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2328 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2329 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2330 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2331 N0.getOperand(1) == N1.getOperand(1)) {
2332 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2333 N0.getOperand(0).getValueType(),
2334 N0.getOperand(0), N1.getOperand(0));
2335 AddToWorkList(ORNode.getNode());
2336 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
2337 ORNode, N0.getOperand(1));
2343 SDValue DAGCombiner::visitAND(SDNode *N) {
2344 SDValue N0 = N->getOperand(0);
2345 SDValue N1 = N->getOperand(1);
2346 SDValue LL, LR, RL, RR, CC0, CC1;
2347 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2348 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2349 EVT VT = N1.getValueType();
2350 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2353 if (VT.isVector()) {
2354 SDValue FoldedVOp = SimplifyVBinOp(N);
2355 if (FoldedVOp.getNode()) return FoldedVOp;
2358 // fold (and x, undef) -> 0
2359 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2360 return DAG.getConstant(0, VT);
2361 // fold (and c1, c2) -> c1&c2
2363 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2364 // canonicalize constant to RHS
2366 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
2367 // fold (and x, -1) -> x
2368 if (N1C && N1C->isAllOnesValue())
2370 // if (and x, c) is known to be zero, return 0
2371 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2372 APInt::getAllOnesValue(BitWidth)))
2373 return DAG.getConstant(0, VT);
2375 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
2376 if (RAND.getNode() != 0)
2378 // fold (and (or x, C), D) -> D if (C & D) == D
2379 if (N1C && N0.getOpcode() == ISD::OR)
2380 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2381 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2383 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2384 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2385 SDValue N0Op0 = N0.getOperand(0);
2386 APInt Mask = ~N1C->getAPIntValue();
2387 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2388 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2389 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
2390 N0.getValueType(), N0Op0);
2392 // Replace uses of the AND with uses of the Zero extend node.
2395 // We actually want to replace all uses of the any_extend with the
2396 // zero_extend, to avoid duplicating things. This will later cause this
2397 // AND to be folded.
2398 CombineTo(N0.getNode(), Zext);
2399 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2402 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
2403 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
2404 // already be zero by virtue of the width of the base type of the load.
2406 // the 'X' node here can either be nothing or an extract_vector_elt to catch
2408 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
2409 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
2410 N0.getOpcode() == ISD::LOAD) {
2411 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
2412 N0 : N0.getOperand(0) );
2414 // Get the constant (if applicable) the zero'th operand is being ANDed with.
2415 // This can be a pure constant or a vector splat, in which case we treat the
2416 // vector as a scalar and use the splat value.
2417 APInt Constant = APInt::getNullValue(1);
2418 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
2419 Constant = C->getAPIntValue();
2420 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
2421 APInt SplatValue, SplatUndef;
2422 unsigned SplatBitSize;
2424 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
2425 SplatBitSize, HasAnyUndefs);
2427 // Undef bits can contribute to a possible optimisation if set, so
2429 SplatValue |= SplatUndef;
2431 // The splat value may be something like "0x00FFFFFF", which means 0 for
2432 // the first vector value and FF for the rest, repeating. We need a mask
2433 // that will apply equally to all members of the vector, so AND all the
2434 // lanes of the constant together.
2435 EVT VT = Vector->getValueType(0);
2436 unsigned BitWidth = VT.getVectorElementType().getSizeInBits();
2437 Constant = APInt::getAllOnesValue(BitWidth);
2438 for (unsigned i = 0, n = VT.getVectorNumElements(); i < n; ++i)
2439 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
2443 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
2444 // actually legal and isn't going to get expanded, else this is a false
2446 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
2447 Load->getMemoryVT());
2449 // Resize the constant to the same size as the original memory access before
2450 // extension. If it is still the AllOnesValue then this AND is completely
2453 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits());
2456 switch (Load->getExtensionType()) {
2457 default: B = false; break;
2458 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
2460 case ISD::NON_EXTLOAD: B = true; break;
2463 if (B && Constant.isAllOnesValue()) {
2464 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
2465 // preserve semantics once we get rid of the AND.
2466 SDValue NewLoad(Load, 0);
2467 if (Load->getExtensionType() == ISD::EXTLOAD) {
2468 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
2469 Load->getValueType(0), Load->getDebugLoc(),
2470 Load->getChain(), Load->getBasePtr(),
2471 Load->getOffset(), Load->getMemoryVT(),
2472 Load->getMemOperand());
2473 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
2474 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
2477 // Fold the AND away, taking care not to fold to the old load node if we
2479 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
2481 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2484 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2485 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2486 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2487 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2489 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2490 LL.getValueType().isInteger()) {
2491 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2492 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2493 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2494 LR.getValueType(), LL, RL);
2495 AddToWorkList(ORNode.getNode());
2496 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2498 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2499 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2500 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
2501 LR.getValueType(), LL, RL);
2502 AddToWorkList(ANDNode.getNode());
2503 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2505 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2506 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2507 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2508 LR.getValueType(), LL, RL);
2509 AddToWorkList(ORNode.getNode());
2510 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2513 // canonicalize equivalent to ll == rl
2514 if (LL == RR && LR == RL) {
2515 Op1 = ISD::getSetCCSwappedOperands(Op1);
2518 if (LL == RL && LR == RR) {
2519 bool isInteger = LL.getValueType().isInteger();
2520 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2521 if (Result != ISD::SETCC_INVALID &&
2522 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2523 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2528 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2529 if (N0.getOpcode() == N1.getOpcode()) {
2530 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2531 if (Tmp.getNode()) return Tmp;
2534 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2535 // fold (and (sra)) -> (and (srl)) when possible.
2536 if (!VT.isVector() &&
2537 SimplifyDemandedBits(SDValue(N, 0)))
2538 return SDValue(N, 0);
2540 // fold (zext_inreg (extload x)) -> (zextload x)
2541 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2542 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2543 EVT MemVT = LN0->getMemoryVT();
2544 // If we zero all the possible extended bits, then we can turn this into
2545 // a zextload if we are running before legalize or the operation is legal.
2546 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2547 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2548 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2549 ((!LegalOperations && !LN0->isVolatile()) ||
2550 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2551 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2552 LN0->getChain(), LN0->getBasePtr(),
2553 LN0->getPointerInfo(), MemVT,
2554 LN0->isVolatile(), LN0->isNonTemporal(),
2555 LN0->getAlignment());
2557 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2558 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2561 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2562 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2564 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2565 EVT MemVT = LN0->getMemoryVT();
2566 // If we zero all the possible extended bits, then we can turn this into
2567 // a zextload if we are running before legalize or the operation is legal.
2568 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2569 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2570 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2571 ((!LegalOperations && !LN0->isVolatile()) ||
2572 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2573 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2575 LN0->getBasePtr(), LN0->getPointerInfo(),
2577 LN0->isVolatile(), LN0->isNonTemporal(),
2578 LN0->getAlignment());
2580 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2581 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2585 // fold (and (load x), 255) -> (zextload x, i8)
2586 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2587 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2588 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2589 (N0.getOpcode() == ISD::ANY_EXTEND &&
2590 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2591 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2592 LoadSDNode *LN0 = HasAnyExt
2593 ? cast<LoadSDNode>(N0.getOperand(0))
2594 : cast<LoadSDNode>(N0);
2595 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2596 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2597 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2598 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2599 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2600 EVT LoadedVT = LN0->getMemoryVT();
2602 if (ExtVT == LoadedVT &&
2603 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2604 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2607 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2608 LN0->getChain(), LN0->getBasePtr(),
2609 LN0->getPointerInfo(),
2610 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2611 LN0->getAlignment());
2613 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2614 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2617 // Do not change the width of a volatile load.
2618 // Do not generate loads of non-round integer types since these can
2619 // be expensive (and would be wrong if the type is not byte sized).
2620 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2621 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2622 EVT PtrType = LN0->getOperand(1).getValueType();
2624 unsigned Alignment = LN0->getAlignment();
2625 SDValue NewPtr = LN0->getBasePtr();
2627 // For big endian targets, we need to add an offset to the pointer
2628 // to load the correct bytes. For little endian systems, we merely
2629 // need to read fewer bytes from the same pointer.
2630 if (TLI.isBigEndian()) {
2631 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2632 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2633 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2634 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2635 NewPtr, DAG.getConstant(PtrOff, PtrType));
2636 Alignment = MinAlign(Alignment, PtrOff);
2639 AddToWorkList(NewPtr.getNode());
2641 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2643 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2644 LN0->getChain(), NewPtr,
2645 LN0->getPointerInfo(),
2646 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2649 CombineTo(LN0, Load, Load.getValue(1));
2650 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2659 /// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16
2661 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
2662 bool DemandHighBits) {
2663 if (!LegalOperations)
2666 EVT VT = N->getValueType(0);
2667 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
2669 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2672 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
2673 bool LookPassAnd0 = false;
2674 bool LookPassAnd1 = false;
2675 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2677 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
2679 if (N0.getOpcode() == ISD::AND) {
2680 if (!N0.getNode()->hasOneUse())
2682 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2683 if (!N01C || N01C->getZExtValue() != 0xFF00)
2685 N0 = N0.getOperand(0);
2686 LookPassAnd0 = true;
2689 if (N1.getOpcode() == ISD::AND) {
2690 if (!N1.getNode()->hasOneUse())
2692 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2693 if (!N11C || N11C->getZExtValue() != 0xFF)
2695 N1 = N1.getOperand(0);
2696 LookPassAnd1 = true;
2699 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2701 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2703 if (!N0.getNode()->hasOneUse() ||
2704 !N1.getNode()->hasOneUse())
2707 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2708 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2711 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
2714 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
2715 SDValue N00 = N0->getOperand(0);
2716 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
2717 if (!N00.getNode()->hasOneUse())
2719 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
2720 if (!N001C || N001C->getZExtValue() != 0xFF)
2722 N00 = N00.getOperand(0);
2723 LookPassAnd0 = true;
2726 SDValue N10 = N1->getOperand(0);
2727 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
2728 if (!N10.getNode()->hasOneUse())
2730 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
2731 if (!N101C || N101C->getZExtValue() != 0xFF00)
2733 N10 = N10.getOperand(0);
2734 LookPassAnd1 = true;
2740 // Make sure everything beyond the low halfword is zero since the SRL 16
2741 // will clear the top bits.
2742 unsigned OpSizeInBits = VT.getSizeInBits();
2743 if (DemandHighBits && OpSizeInBits > 16 &&
2744 (!LookPassAnd0 || !LookPassAnd1) &&
2745 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16)))
2748 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00);
2749 if (OpSizeInBits > 16)
2750 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res,
2751 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT)));
2755 /// isBSwapHWordElement - Return true if the specified node is an element
2756 /// that makes up a 32-bit packed halfword byteswap. i.e.
2757 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2758 static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) {
2759 if (!N.getNode()->hasOneUse())
2762 unsigned Opc = N.getOpcode();
2763 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
2766 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2771 switch (N1C->getZExtValue()) {
2774 case 0xFF: Num = 0; break;
2775 case 0xFF00: Num = 1; break;
2776 case 0xFF0000: Num = 2; break;
2777 case 0xFF000000: Num = 3; break;
2780 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
2781 SDValue N0 = N.getOperand(0);
2782 if (Opc == ISD::AND) {
2783 if (Num == 0 || Num == 2) {
2785 // (x >> 8) & 0xff0000
2786 if (N0.getOpcode() != ISD::SRL)
2788 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2789 if (!C || C->getZExtValue() != 8)
2792 // (x << 8) & 0xff00
2793 // (x << 8) & 0xff000000
2794 if (N0.getOpcode() != ISD::SHL)
2796 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2797 if (!C || C->getZExtValue() != 8)
2800 } else if (Opc == ISD::SHL) {
2802 // (x & 0xff0000) << 8
2803 if (Num != 0 && Num != 2)
2805 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2806 if (!C || C->getZExtValue() != 8)
2808 } else { // Opc == ISD::SRL
2809 // (x & 0xff00) >> 8
2810 // (x & 0xff000000) >> 8
2811 if (Num != 1 && Num != 3)
2813 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2814 if (!C || C->getZExtValue() != 8)
2821 Parts[Num] = N0.getOperand(0).getNode();
2825 /// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is
2826 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2827 /// => (rotl (bswap x), 16)
2828 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
2829 if (!LegalOperations)
2832 EVT VT = N->getValueType(0);
2835 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2838 SmallVector<SDNode*,4> Parts(4, (SDNode*)0);
2840 // (or (or (and), (and)), (or (and), (and)))
2841 // (or (or (or (and), (and)), (and)), (and))
2842 if (N0.getOpcode() != ISD::OR)
2844 SDValue N00 = N0.getOperand(0);
2845 SDValue N01 = N0.getOperand(1);
2847 if (N1.getOpcode() == ISD::OR) {
2848 // (or (or (and), (and)), (or (and), (and)))
2849 SDValue N000 = N00.getOperand(0);
2850 if (!isBSwapHWordElement(N000, Parts))
2853 SDValue N001 = N00.getOperand(1);
2854 if (!isBSwapHWordElement(N001, Parts))
2856 SDValue N010 = N01.getOperand(0);
2857 if (!isBSwapHWordElement(N010, Parts))
2859 SDValue N011 = N01.getOperand(1);
2860 if (!isBSwapHWordElement(N011, Parts))
2863 // (or (or (or (and), (and)), (and)), (and))
2864 if (!isBSwapHWordElement(N1, Parts))
2866 if (!isBSwapHWordElement(N01, Parts))
2868 if (N00.getOpcode() != ISD::OR)
2870 SDValue N000 = N00.getOperand(0);
2871 if (!isBSwapHWordElement(N000, Parts))
2873 SDValue N001 = N00.getOperand(1);
2874 if (!isBSwapHWordElement(N001, Parts))
2878 // Make sure the parts are all coming from the same node.
2879 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
2882 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT,
2883 SDValue(Parts[0],0));
2885 // Result of the bswap should be rotated by 16. If it's not legal, than
2886 // do (x << 16) | (x >> 16).
2887 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT));
2888 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
2889 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt);
2890 else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
2891 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt);
2892 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT,
2893 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt),
2894 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt));
2897 SDValue DAGCombiner::visitOR(SDNode *N) {
2898 SDValue N0 = N->getOperand(0);
2899 SDValue N1 = N->getOperand(1);
2900 SDValue LL, LR, RL, RR, CC0, CC1;
2901 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2902 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2903 EVT VT = N1.getValueType();
2906 if (VT.isVector()) {
2907 SDValue FoldedVOp = SimplifyVBinOp(N);
2908 if (FoldedVOp.getNode()) return FoldedVOp;
2911 // fold (or x, undef) -> -1
2912 if (!LegalOperations &&
2913 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
2914 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
2915 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
2917 // fold (or c1, c2) -> c1|c2
2919 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
2920 // canonicalize constant to RHS
2922 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
2923 // fold (or x, 0) -> x
2924 if (N1C && N1C->isNullValue())
2926 // fold (or x, -1) -> -1
2927 if (N1C && N1C->isAllOnesValue())
2929 // fold (or x, c) -> c iff (x & ~c) == 0
2930 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
2933 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
2934 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
2935 if (BSwap.getNode() != 0)
2937 BSwap = MatchBSwapHWordLow(N, N0, N1);
2938 if (BSwap.getNode() != 0)
2942 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
2943 if (ROR.getNode() != 0)
2945 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
2946 // iff (c1 & c2) == 0.
2947 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
2948 isa<ConstantSDNode>(N0.getOperand(1))) {
2949 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
2950 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
2951 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
2952 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2953 N0.getOperand(0), N1),
2954 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
2956 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
2957 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2958 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2959 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2961 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2962 LL.getValueType().isInteger()) {
2963 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
2964 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
2965 if (cast<ConstantSDNode>(LR)->isNullValue() &&
2966 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
2967 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
2968 LR.getValueType(), LL, RL);
2969 AddToWorkList(ORNode.getNode());
2970 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2972 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
2973 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
2974 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2975 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
2976 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
2977 LR.getValueType(), LL, RL);
2978 AddToWorkList(ANDNode.getNode());
2979 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2982 // canonicalize equivalent to ll == rl
2983 if (LL == RR && LR == RL) {
2984 Op1 = ISD::getSetCCSwappedOperands(Op1);
2987 if (LL == RL && LR == RR) {
2988 bool isInteger = LL.getValueType().isInteger();
2989 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
2990 if (Result != ISD::SETCC_INVALID &&
2991 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2992 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2997 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
2998 if (N0.getOpcode() == N1.getOpcode()) {
2999 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3000 if (Tmp.getNode()) return Tmp;
3003 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
3004 if (N0.getOpcode() == ISD::AND &&
3005 N1.getOpcode() == ISD::AND &&
3006 N0.getOperand(1).getOpcode() == ISD::Constant &&
3007 N1.getOperand(1).getOpcode() == ISD::Constant &&
3008 // Don't increase # computations.
3009 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3010 // We can only do this xform if we know that bits from X that are set in C2
3011 // but not in C1 are already zero. Likewise for Y.
3012 const APInt &LHSMask =
3013 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3014 const APInt &RHSMask =
3015 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
3017 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
3018 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
3019 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
3020 N0.getOperand(0), N1.getOperand(0));
3021 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
3022 DAG.getConstant(LHSMask | RHSMask, VT));
3026 // See if this is some rotate idiom.
3027 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
3028 return SDValue(Rot, 0);
3030 // Simplify the operands using demanded-bits information.
3031 if (!VT.isVector() &&
3032 SimplifyDemandedBits(SDValue(N, 0)))
3033 return SDValue(N, 0);
3038 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
3039 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
3040 if (Op.getOpcode() == ISD::AND) {
3041 if (isa<ConstantSDNode>(Op.getOperand(1))) {
3042 Mask = Op.getOperand(1);
3043 Op = Op.getOperand(0);
3049 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3057 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
3058 // idioms for rotate, and if the target supports rotation instructions, generate
3060 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
3061 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
3062 EVT VT = LHS.getValueType();
3063 if (!TLI.isTypeLegal(VT)) return 0;
3065 // The target must have at least one rotate flavor.
3066 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
3067 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
3068 if (!HasROTL && !HasROTR) return 0;
3070 // Match "(X shl/srl V1) & V2" where V2 may not be present.
3071 SDValue LHSShift; // The shift.
3072 SDValue LHSMask; // AND value if any.
3073 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
3074 return 0; // Not part of a rotate.
3076 SDValue RHSShift; // The shift.
3077 SDValue RHSMask; // AND value if any.
3078 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
3079 return 0; // Not part of a rotate.
3081 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
3082 return 0; // Not shifting the same value.
3084 if (LHSShift.getOpcode() == RHSShift.getOpcode())
3085 return 0; // Shifts must disagree.
3087 // Canonicalize shl to left side in a shl/srl pair.
3088 if (RHSShift.getOpcode() == ISD::SHL) {
3089 std::swap(LHS, RHS);
3090 std::swap(LHSShift, RHSShift);
3091 std::swap(LHSMask , RHSMask );
3094 unsigned OpSizeInBits = VT.getSizeInBits();
3095 SDValue LHSShiftArg = LHSShift.getOperand(0);
3096 SDValue LHSShiftAmt = LHSShift.getOperand(1);
3097 SDValue RHSShiftAmt = RHSShift.getOperand(1);
3099 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
3100 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
3101 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
3102 RHSShiftAmt.getOpcode() == ISD::Constant) {
3103 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
3104 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
3105 if ((LShVal + RShVal) != OpSizeInBits)
3110 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
3112 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
3114 // If there is an AND of either shifted operand, apply it to the result.
3115 if (LHSMask.getNode() || RHSMask.getNode()) {
3116 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
3118 if (LHSMask.getNode()) {
3119 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
3120 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
3122 if (RHSMask.getNode()) {
3123 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
3124 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
3127 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
3130 return Rot.getNode();
3133 // If there is a mask here, and we have a variable shift, we can't be sure
3134 // that we're masking out the right stuff.
3135 if (LHSMask.getNode() || RHSMask.getNode())
3138 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
3139 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
3140 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
3141 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
3142 if (ConstantSDNode *SUBC =
3143 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
3144 if (SUBC->getAPIntValue() == OpSizeInBits) {
3146 return DAG.getNode(ISD::ROTL, DL, VT,
3147 LHSShiftArg, LHSShiftAmt).getNode();
3149 return DAG.getNode(ISD::ROTR, DL, VT,
3150 LHSShiftArg, RHSShiftAmt).getNode();
3155 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
3156 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
3157 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
3158 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
3159 if (ConstantSDNode *SUBC =
3160 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
3161 if (SUBC->getAPIntValue() == OpSizeInBits) {
3163 return DAG.getNode(ISD::ROTR, DL, VT,
3164 LHSShiftArg, RHSShiftAmt).getNode();
3166 return DAG.getNode(ISD::ROTL, DL, VT,
3167 LHSShiftArg, LHSShiftAmt).getNode();
3172 // Look for sign/zext/any-extended or truncate cases:
3173 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
3174 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
3175 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
3176 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3177 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
3178 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
3179 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
3180 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3181 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
3182 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
3183 if (RExtOp0.getOpcode() == ISD::SUB &&
3184 RExtOp0.getOperand(1) == LExtOp0) {
3185 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3187 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3188 // (rotr x, (sub 32, y))
3189 if (ConstantSDNode *SUBC =
3190 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
3191 if (SUBC->getAPIntValue() == OpSizeInBits) {
3192 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3194 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
3197 } else if (LExtOp0.getOpcode() == ISD::SUB &&
3198 RExtOp0 == LExtOp0.getOperand(1)) {
3199 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3201 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3202 // (rotl x, (sub 32, y))
3203 if (ConstantSDNode *SUBC =
3204 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
3205 if (SUBC->getAPIntValue() == OpSizeInBits) {
3206 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
3208 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
3217 SDValue DAGCombiner::visitXOR(SDNode *N) {
3218 SDValue N0 = N->getOperand(0);
3219 SDValue N1 = N->getOperand(1);
3220 SDValue LHS, RHS, CC;
3221 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3222 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3223 EVT VT = N0.getValueType();
3226 if (VT.isVector()) {
3227 SDValue FoldedVOp = SimplifyVBinOp(N);
3228 if (FoldedVOp.getNode()) return FoldedVOp;
3231 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3232 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3233 return DAG.getConstant(0, VT);
3234 // fold (xor x, undef) -> undef
3235 if (N0.getOpcode() == ISD::UNDEF)
3237 if (N1.getOpcode() == ISD::UNDEF)
3239 // fold (xor c1, c2) -> c1^c2
3241 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3242 // canonicalize constant to RHS
3244 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
3245 // fold (xor x, 0) -> x
3246 if (N1C && N1C->isNullValue())
3249 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
3250 if (RXOR.getNode() != 0)
3253 // fold !(x cc y) -> (x !cc y)
3254 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3255 bool isInt = LHS.getValueType().isInteger();
3256 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3259 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
3260 switch (N0.getOpcode()) {
3262 llvm_unreachable("Unhandled SetCC Equivalent!");
3264 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
3265 case ISD::SELECT_CC:
3266 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
3267 N0.getOperand(3), NotCC);
3272 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
3273 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3274 N0.getNode()->hasOneUse() &&
3275 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3276 SDValue V = N0.getOperand(0);
3277 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
3278 DAG.getConstant(1, V.getValueType()));
3279 AddToWorkList(V.getNode());
3280 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
3283 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
3284 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
3285 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3286 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3287 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
3288 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3289 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3290 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3291 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3292 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3295 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
3296 if (N1C && N1C->isAllOnesValue() &&
3297 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3298 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3299 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
3300 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3301 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3302 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3303 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3304 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3307 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
3308 if (N1C && N0.getOpcode() == ISD::XOR) {
3309 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3310 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3312 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
3313 DAG.getConstant(N1C->getAPIntValue() ^
3314 N00C->getAPIntValue(), VT));
3316 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
3317 DAG.getConstant(N1C->getAPIntValue() ^
3318 N01C->getAPIntValue(), VT));
3320 // fold (xor x, x) -> 0
3322 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
3324 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
3325 if (N0.getOpcode() == N1.getOpcode()) {
3326 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3327 if (Tmp.getNode()) return Tmp;
3330 // Simplify the expression using non-local knowledge.
3331 if (!VT.isVector() &&
3332 SimplifyDemandedBits(SDValue(N, 0)))
3333 return SDValue(N, 0);
3338 /// visitShiftByConstant - Handle transforms common to the three shifts, when
3339 /// the shift amount is a constant.
3340 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
3341 SDNode *LHS = N->getOperand(0).getNode();
3342 if (!LHS->hasOneUse()) return SDValue();
3344 // We want to pull some binops through shifts, so that we have (and (shift))
3345 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
3346 // thing happens with address calculations, so it's important to canonicalize
3348 bool HighBitSet = false; // Can we transform this if the high bit is set?
3350 switch (LHS->getOpcode()) {
3351 default: return SDValue();
3354 HighBitSet = false; // We can only transform sra if the high bit is clear.
3357 HighBitSet = true; // We can only transform sra if the high bit is set.
3360 if (N->getOpcode() != ISD::SHL)
3361 return SDValue(); // only shl(add) not sr[al](add).
3362 HighBitSet = false; // We can only transform sra if the high bit is clear.
3366 // We require the RHS of the binop to be a constant as well.
3367 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
3368 if (!BinOpCst) return SDValue();
3370 // FIXME: disable this unless the input to the binop is a shift by a constant.
3371 // If it is not a shift, it pessimizes some common cases like:
3373 // void foo(int *X, int i) { X[i & 1235] = 1; }
3374 // int bar(int *X, int i) { return X[i & 255]; }
3375 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
3376 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
3377 BinOpLHSVal->getOpcode() != ISD::SRA &&
3378 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3379 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
3382 EVT VT = N->getValueType(0);
3384 // If this is a signed shift right, and the high bit is modified by the
3385 // logical operation, do not perform the transformation. The highBitSet
3386 // boolean indicates the value of the high bit of the constant which would
3387 // cause it to be modified for this operation.
3388 if (N->getOpcode() == ISD::SRA) {
3389 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
3390 if (BinOpRHSSignSet != HighBitSet)
3394 // Fold the constants, shifting the binop RHS by the shift amount.
3395 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
3397 LHS->getOperand(1), N->getOperand(1));
3399 // Create the new shift.
3400 SDValue NewShift = DAG.getNode(N->getOpcode(),
3401 LHS->getOperand(0).getDebugLoc(),
3402 VT, LHS->getOperand(0), N->getOperand(1));
3404 // Create the new binop.
3405 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
3408 SDValue DAGCombiner::visitSHL(SDNode *N) {
3409 SDValue N0 = N->getOperand(0);
3410 SDValue N1 = N->getOperand(1);
3411 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3412 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3413 EVT VT = N0.getValueType();
3414 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3416 // fold (shl c1, c2) -> c1<<c2
3418 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
3419 // fold (shl 0, x) -> 0
3420 if (N0C && N0C->isNullValue())
3422 // fold (shl x, c >= size(x)) -> undef
3423 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3424 return DAG.getUNDEF(VT);
3425 // fold (shl x, 0) -> x
3426 if (N1C && N1C->isNullValue())
3428 // fold (shl undef, x) -> 0
3429 if (N0.getOpcode() == ISD::UNDEF)
3430 return DAG.getConstant(0, VT);
3431 // if (shl x, c) is known to be zero, return 0
3432 if (DAG.MaskedValueIsZero(SDValue(N, 0),
3433 APInt::getAllOnesValue(OpSizeInBits)))
3434 return DAG.getConstant(0, VT);
3435 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
3436 if (N1.getOpcode() == ISD::TRUNCATE &&
3437 N1.getOperand(0).getOpcode() == ISD::AND &&
3438 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3439 SDValue N101 = N1.getOperand(0).getOperand(1);
3440 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3441 EVT TruncVT = N1.getValueType();
3442 SDValue N100 = N1.getOperand(0).getOperand(0);
3443 APInt TruncC = N101C->getAPIntValue();
3444 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3445 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
3446 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
3447 DAG.getNode(ISD::TRUNCATE,
3450 DAG.getConstant(TruncC, TruncVT)));
3454 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3455 return SDValue(N, 0);
3457 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
3458 if (N1C && N0.getOpcode() == ISD::SHL &&
3459 N0.getOperand(1).getOpcode() == ISD::Constant) {
3460 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3461 uint64_t c2 = N1C->getZExtValue();
3462 if (c1 + c2 >= OpSizeInBits)
3463 return DAG.getConstant(0, VT);
3464 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3465 DAG.getConstant(c1 + c2, N1.getValueType()));
3468 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
3469 // For this to be valid, the second form must not preserve any of the bits
3470 // that are shifted out by the inner shift in the first form. This means
3471 // the outer shift size must be >= the number of bits added by the ext.
3472 // As a corollary, we don't care what kind of ext it is.
3473 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
3474 N0.getOpcode() == ISD::ANY_EXTEND ||
3475 N0.getOpcode() == ISD::SIGN_EXTEND) &&
3476 N0.getOperand(0).getOpcode() == ISD::SHL &&
3477 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3479 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3480 uint64_t c2 = N1C->getZExtValue();
3481 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3482 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3483 if (c2 >= OpSizeInBits - InnerShiftSize) {
3484 if (c1 + c2 >= OpSizeInBits)
3485 return DAG.getConstant(0, VT);
3486 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT,
3487 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT,
3488 N0.getOperand(0)->getOperand(0)),
3489 DAG.getConstant(c1 + c2, N1.getValueType()));
3493 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
3494 // (and (srl x, (sub c1, c2), MASK)
3495 // Only fold this if the inner shift has no other uses -- if it does, folding
3496 // this will increase the total number of instructions.
3497 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() &&
3498 N0.getOperand(1).getOpcode() == ISD::Constant) {
3499 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3500 if (c1 < VT.getSizeInBits()) {
3501 uint64_t c2 = N1C->getZExtValue();
3502 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
3503 VT.getSizeInBits() - c1);
3506 Mask = Mask.shl(c2-c1);
3507 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3508 DAG.getConstant(c2-c1, N1.getValueType()));
3510 Mask = Mask.lshr(c1-c2);
3511 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3512 DAG.getConstant(c1-c2, N1.getValueType()));
3514 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift,
3515 DAG.getConstant(Mask, VT));
3518 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
3519 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
3520 SDValue HiBitsMask =
3521 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
3522 VT.getSizeInBits() -
3523 N1C->getZExtValue()),
3525 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3530 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
3531 if (NewSHL.getNode())
3538 SDValue DAGCombiner::visitSRA(SDNode *N) {
3539 SDValue N0 = N->getOperand(0);
3540 SDValue N1 = N->getOperand(1);
3541 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3542 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3543 EVT VT = N0.getValueType();
3544 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3546 // fold (sra c1, c2) -> (sra c1, c2)
3548 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
3549 // fold (sra 0, x) -> 0
3550 if (N0C && N0C->isNullValue())
3552 // fold (sra -1, x) -> -1
3553 if (N0C && N0C->isAllOnesValue())
3555 // fold (sra x, (setge c, size(x))) -> undef
3556 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3557 return DAG.getUNDEF(VT);
3558 // fold (sra x, 0) -> x
3559 if (N1C && N1C->isNullValue())
3561 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
3563 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
3564 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
3565 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
3567 ExtVT = EVT::getVectorVT(*DAG.getContext(),
3568 ExtVT, VT.getVectorNumElements());
3569 if ((!LegalOperations ||
3570 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
3571 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3572 N0.getOperand(0), DAG.getValueType(ExtVT));
3575 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
3576 if (N1C && N0.getOpcode() == ISD::SRA) {
3577 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3578 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
3579 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
3580 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
3581 DAG.getConstant(Sum, N1C->getValueType(0)));
3585 // fold (sra (shl X, m), (sub result_size, n))
3586 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
3587 // result_size - n != m.
3588 // If truncate is free for the target sext(shl) is likely to result in better
3590 if (N0.getOpcode() == ISD::SHL) {
3591 // Get the two constanst of the shifts, CN0 = m, CN = n.
3592 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3594 // Determine what the truncate's result bitsize and type would be.
3596 EVT::getIntegerVT(*DAG.getContext(),
3597 OpSizeInBits - N1C->getZExtValue());
3598 // Determine the residual right-shift amount.
3599 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
3601 // If the shift is not a no-op (in which case this should be just a sign
3602 // extend already), the truncated to type is legal, sign_extend is legal
3603 // on that type, and the truncate to that type is both legal and free,
3604 // perform the transform.
3605 if ((ShiftAmt > 0) &&
3606 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
3607 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
3608 TLI.isTruncateFree(VT, TruncVT)) {
3610 SDValue Amt = DAG.getConstant(ShiftAmt,
3611 getShiftAmountTy(N0.getOperand(0).getValueType()));
3612 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3613 N0.getOperand(0), Amt);
3614 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
3616 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
3617 N->getValueType(0), Trunc);
3622 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
3623 if (N1.getOpcode() == ISD::TRUNCATE &&
3624 N1.getOperand(0).getOpcode() == ISD::AND &&
3625 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3626 SDValue N101 = N1.getOperand(0).getOperand(1);
3627 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3628 EVT TruncVT = N1.getValueType();
3629 SDValue N100 = N1.getOperand(0).getOperand(0);
3630 APInt TruncC = N101C->getAPIntValue();
3631 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
3632 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
3633 DAG.getNode(ISD::AND, N->getDebugLoc(),
3635 DAG.getNode(ISD::TRUNCATE,
3638 DAG.getConstant(TruncC, TruncVT)));
3642 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2))
3643 // if c1 is equal to the number of bits the trunc removes
3644 if (N0.getOpcode() == ISD::TRUNCATE &&
3645 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3646 N0.getOperand(0).getOpcode() == ISD::SRA) &&
3647 N0.getOperand(0).hasOneUse() &&
3648 N0.getOperand(0).getOperand(1).hasOneUse() &&
3649 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) {
3650 EVT LargeVT = N0.getOperand(0).getValueType();
3651 ConstantSDNode *LargeShiftAmt =
3652 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1));
3654 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits ==
3655 LargeShiftAmt->getZExtValue()) {
3657 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(),
3658 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType()));
3659 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT,
3660 N0.getOperand(0).getOperand(0), Amt);
3661 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA);
3665 // Simplify, based on bits shifted out of the LHS.
3666 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3667 return SDValue(N, 0);
3670 // If the sign bit is known to be zero, switch this to a SRL.
3671 if (DAG.SignBitIsZero(N0))
3672 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3675 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
3676 if (NewSRA.getNode())
3683 SDValue DAGCombiner::visitSRL(SDNode *N) {
3684 SDValue N0 = N->getOperand(0);
3685 SDValue N1 = N->getOperand(1);
3686 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3687 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3688 EVT VT = N0.getValueType();
3689 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3691 // fold (srl c1, c2) -> c1 >>u c2
3693 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3694 // fold (srl 0, x) -> 0
3695 if (N0C && N0C->isNullValue())
3697 // fold (srl x, c >= size(x)) -> undef
3698 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3699 return DAG.getUNDEF(VT);
3700 // fold (srl x, 0) -> x
3701 if (N1C && N1C->isNullValue())
3703 // if (srl x, c) is known to be zero, return 0
3704 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3705 APInt::getAllOnesValue(OpSizeInBits)))
3706 return DAG.getConstant(0, VT);
3708 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3709 if (N1C && N0.getOpcode() == ISD::SRL &&
3710 N0.getOperand(1).getOpcode() == ISD::Constant) {
3711 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3712 uint64_t c2 = N1C->getZExtValue();
3713 if (c1 + c2 >= OpSizeInBits)
3714 return DAG.getConstant(0, VT);
3715 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3716 DAG.getConstant(c1 + c2, N1.getValueType()));
3719 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
3720 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
3721 N0.getOperand(0).getOpcode() == ISD::SRL &&
3722 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3724 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3725 uint64_t c2 = N1C->getZExtValue();
3726 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3727 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
3728 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3729 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
3730 if (c1 + OpSizeInBits == InnerShiftSize) {
3731 if (c1 + c2 >= InnerShiftSize)
3732 return DAG.getConstant(0, VT);
3733 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT,
3734 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
3735 N0.getOperand(0)->getOperand(0),
3736 DAG.getConstant(c1 + c2, ShiftCountVT)));
3740 // fold (srl (shl x, c), c) -> (and x, cst2)
3741 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3742 N0.getValueSizeInBits() <= 64) {
3743 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3744 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3745 DAG.getConstant(~0ULL >> ShAmt, VT));
3749 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3750 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3751 // Shifting in all undef bits?
3752 EVT SmallVT = N0.getOperand(0).getValueType();
3753 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
3754 return DAG.getUNDEF(VT);
3756 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3757 uint64_t ShiftAmt = N1C->getZExtValue();
3758 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3760 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));
3761 AddToWorkList(SmallShift.getNode());
3762 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
3766 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
3767 // bit, which is unmodified by sra.
3768 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
3769 if (N0.getOpcode() == ISD::SRA)
3770 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3773 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3774 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3775 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
3776 APInt KnownZero, KnownOne;
3777 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
3778 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
3780 // If any of the input bits are KnownOne, then the input couldn't be all
3781 // zeros, thus the result of the srl will always be zero.
3782 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
3784 // If all of the bits input the to ctlz node are known to be zero, then
3785 // the result of the ctlz is "32" and the result of the shift is one.
3786 APInt UnknownBits = ~KnownZero & Mask;
3787 if (UnknownBits == 0) return DAG.getConstant(1, VT);
3789 // Otherwise, check to see if there is exactly one bit input to the ctlz.
3790 if ((UnknownBits & (UnknownBits - 1)) == 0) {
3791 // Okay, we know that only that the single bit specified by UnknownBits
3792 // could be set on input to the CTLZ node. If this bit is set, the SRL
3793 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3794 // to an SRL/XOR pair, which is likely to simplify more.
3795 unsigned ShAmt = UnknownBits.countTrailingZeros();
3796 SDValue Op = N0.getOperand(0);
3799 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3800 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType())));
3801 AddToWorkList(Op.getNode());
3804 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3805 Op, DAG.getConstant(1, VT));
3809 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3810 if (N1.getOpcode() == ISD::TRUNCATE &&
3811 N1.getOperand(0).getOpcode() == ISD::AND &&
3812 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3813 SDValue N101 = N1.getOperand(0).getOperand(1);
3814 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3815 EVT TruncVT = N1.getValueType();
3816 SDValue N100 = N1.getOperand(0).getOperand(0);
3817 APInt TruncC = N101C->getAPIntValue();
3818 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3819 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3820 DAG.getNode(ISD::AND, N->getDebugLoc(),
3822 DAG.getNode(ISD::TRUNCATE,
3825 DAG.getConstant(TruncC, TruncVT)));
3829 // fold operands of srl based on knowledge that the low bits are not
3831 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3832 return SDValue(N, 0);
3835 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
3836 if (NewSRL.getNode())
3840 // Attempt to convert a srl of a load into a narrower zero-extending load.
3841 SDValue NarrowLoad = ReduceLoadWidth(N);
3842 if (NarrowLoad.getNode())
3845 // Here is a common situation. We want to optimize:
3848 // %b = and i32 %a, 2
3849 // %c = srl i32 %b, 1
3850 // brcond i32 %c ...
3856 // %c = setcc eq %b, 0
3859 // However when after the source operand of SRL is optimized into AND, the SRL
3860 // itself may not be optimized further. Look for it and add the BRCOND into
3862 if (N->hasOneUse()) {
3863 SDNode *Use = *N->use_begin();
3864 if (Use->getOpcode() == ISD::BRCOND)
3866 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
3867 // Also look pass the truncate.
3868 Use = *Use->use_begin();
3869 if (Use->getOpcode() == ISD::BRCOND)
3877 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
3878 SDValue N0 = N->getOperand(0);
3879 EVT VT = N->getValueType(0);
3881 // fold (ctlz c1) -> c2
3882 if (isa<ConstantSDNode>(N0))
3883 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
3887 SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) {
3888 SDValue N0 = N->getOperand(0);
3889 EVT VT = N->getValueType(0);
3891 // fold (ctlz_zero_undef c1) -> c2
3892 if (isa<ConstantSDNode>(N0))
3893 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0);
3897 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
3898 SDValue N0 = N->getOperand(0);
3899 EVT VT = N->getValueType(0);
3901 // fold (cttz c1) -> c2
3902 if (isa<ConstantSDNode>(N0))
3903 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
3907 SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) {
3908 SDValue N0 = N->getOperand(0);
3909 EVT VT = N->getValueType(0);
3911 // fold (cttz_zero_undef c1) -> c2
3912 if (isa<ConstantSDNode>(N0))
3913 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0);
3917 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
3918 SDValue N0 = N->getOperand(0);
3919 EVT VT = N->getValueType(0);
3921 // fold (ctpop c1) -> c2
3922 if (isa<ConstantSDNode>(N0))
3923 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
3927 SDValue DAGCombiner::visitSELECT(SDNode *N) {
3928 SDValue N0 = N->getOperand(0);
3929 SDValue N1 = N->getOperand(1);
3930 SDValue N2 = N->getOperand(2);
3931 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3932 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3933 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
3934 EVT VT = N->getValueType(0);
3935 EVT VT0 = N0.getValueType();
3937 // fold (select C, X, X) -> X
3940 // fold (select true, X, Y) -> X
3941 if (N0C && !N0C->isNullValue())
3943 // fold (select false, X, Y) -> Y
3944 if (N0C && N0C->isNullValue())
3946 // fold (select C, 1, X) -> (or C, X)
3947 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
3948 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3949 // fold (select C, 0, 1) -> (xor C, 1)
3950 if (VT.isInteger() &&
3953 TLI.getBooleanContents(false) == TargetLowering::ZeroOrOneBooleanContent)) &&
3954 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
3957 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
3958 N0, DAG.getConstant(1, VT0));
3959 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
3960 N0, DAG.getConstant(1, VT0));
3961 AddToWorkList(XORNode.getNode());
3963 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
3964 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
3966 // fold (select C, 0, X) -> (and (not C), X)
3967 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
3968 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3969 AddToWorkList(NOTNode.getNode());
3970 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
3972 // fold (select C, X, 1) -> (or (not C), X)
3973 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
3974 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3975 AddToWorkList(NOTNode.getNode());
3976 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
3978 // fold (select C, X, 0) -> (and C, X)
3979 if (VT == MVT::i1 && N2C && N2C->isNullValue())
3980 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3981 // fold (select X, X, Y) -> (or X, Y)
3982 // fold (select X, 1, Y) -> (or X, Y)
3983 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
3984 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3985 // fold (select X, Y, X) -> (and X, Y)
3986 // fold (select X, Y, 0) -> (and X, Y)
3987 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
3988 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3990 // If we can fold this based on the true/false value, do so.
3991 if (SimplifySelectOps(N, N1, N2))
3992 return SDValue(N, 0); // Don't revisit N.
3994 // fold selects based on a setcc into other things, such as min/max/abs
3995 if (N0.getOpcode() == ISD::SETCC) {
3997 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
3998 // having to say they don't support SELECT_CC on every type the DAG knows
3999 // about, since there is no way to mark an opcode illegal at all value types
4000 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
4001 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
4002 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
4003 N0.getOperand(0), N0.getOperand(1),
4004 N1, N2, N0.getOperand(2));
4005 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
4011 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
4012 SDValue N0 = N->getOperand(0);
4013 SDValue N1 = N->getOperand(1);
4014 SDValue N2 = N->getOperand(2);
4015 SDValue N3 = N->getOperand(3);
4016 SDValue N4 = N->getOperand(4);
4017 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
4019 // fold select_cc lhs, rhs, x, x, cc -> x
4023 // Determine if the condition we're dealing with is constant
4024 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
4025 N0, N1, CC, N->getDebugLoc(), false);
4026 if (SCC.getNode()) AddToWorkList(SCC.getNode());
4028 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
4029 if (!SCCC->isNullValue())
4030 return N2; // cond always true -> true val
4032 return N3; // cond always false -> false val
4035 // Fold to a simpler select_cc
4036 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
4037 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
4038 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
4041 // If we can fold this based on the true/false value, do so.
4042 if (SimplifySelectOps(N, N2, N3))
4043 return SDValue(N, 0); // Don't revisit N.
4045 // fold select_cc into other things, such as min/max/abs
4046 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
4049 SDValue DAGCombiner::visitSETCC(SDNode *N) {
4050 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
4051 cast<CondCodeSDNode>(N->getOperand(2))->get(),
4055 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
4056 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
4057 // transformation. Returns true if extension are possible and the above
4058 // mentioned transformation is profitable.
4059 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
4061 SmallVector<SDNode*, 4> &ExtendNodes,
4062 const TargetLowering &TLI) {
4063 bool HasCopyToRegUses = false;
4064 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
4065 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
4066 UE = N0.getNode()->use_end();
4071 if (UI.getUse().getResNo() != N0.getResNo())
4073 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
4074 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
4075 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
4076 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
4077 // Sign bits will be lost after a zext.
4080 for (unsigned i = 0; i != 2; ++i) {
4081 SDValue UseOp = User->getOperand(i);
4084 if (!isa<ConstantSDNode>(UseOp))
4089 ExtendNodes.push_back(User);
4092 // If truncates aren't free and there are users we can't
4093 // extend, it isn't worthwhile.
4096 // Remember if this value is live-out.
4097 if (User->getOpcode() == ISD::CopyToReg)
4098 HasCopyToRegUses = true;
4101 if (HasCopyToRegUses) {
4102 bool BothLiveOut = false;
4103 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
4105 SDUse &Use = UI.getUse();
4106 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
4112 // Both unextended and extended values are live out. There had better be
4113 // a good reason for the transformation.
4114 return ExtendNodes.size();
4119 void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
4120 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
4121 ISD::NodeType ExtType) {
4122 // Extend SetCC uses if necessary.
4123 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
4124 SDNode *SetCC = SetCCs[i];
4125 SmallVector<SDValue, 4> Ops;
4127 for (unsigned j = 0; j != 2; ++j) {
4128 SDValue SOp = SetCC->getOperand(j);
4130 Ops.push_back(ExtLoad);
4132 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
4135 Ops.push_back(SetCC->getOperand(2));
4136 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0),
4137 &Ops[0], Ops.size()));
4141 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
4142 SDValue N0 = N->getOperand(0);
4143 EVT VT = N->getValueType(0);
4145 // fold (sext c1) -> c1
4146 if (isa<ConstantSDNode>(N0))
4147 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
4149 // fold (sext (sext x)) -> (sext x)
4150 // fold (sext (aext x)) -> (sext x)
4151 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4152 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
4155 if (N0.getOpcode() == ISD::TRUNCATE) {
4156 // fold (sext (truncate (load x))) -> (sext (smaller load x))
4157 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
4158 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4159 if (NarrowLoad.getNode()) {
4160 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4161 if (NarrowLoad.getNode() != N0.getNode()) {
4162 CombineTo(N0.getNode(), NarrowLoad);
4163 // CombineTo deleted the truncate, if needed, but not what's under it.
4166 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4169 // See if the value being truncated is already sign extended. If so, just
4170 // eliminate the trunc/sext pair.
4171 SDValue Op = N0.getOperand(0);
4172 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
4173 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
4174 unsigned DestBits = VT.getScalarType().getSizeInBits();
4175 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
4177 if (OpBits == DestBits) {
4178 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
4179 // bits, it is already ready.
4180 if (NumSignBits > DestBits-MidBits)
4182 } else if (OpBits < DestBits) {
4183 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
4184 // bits, just sext from i32.
4185 if (NumSignBits > OpBits-MidBits)
4186 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
4188 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
4189 // bits, just truncate to i32.
4190 if (NumSignBits > OpBits-MidBits)
4191 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4194 // fold (sext (truncate x)) -> (sextinreg x).
4195 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
4196 N0.getValueType())) {
4197 if (OpBits < DestBits)
4198 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
4199 else if (OpBits > DestBits)
4200 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
4201 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
4202 DAG.getValueType(N0.getValueType()));
4206 // fold (sext (load x)) -> (sext (truncate (sextload x)))
4207 // None of the supported targets knows how to perform load and sign extend
4208 // on vectors in one instruction. We only perform this transformation on
4210 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4211 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4212 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
4213 bool DoXform = true;
4214 SmallVector<SDNode*, 4> SetCCs;
4215 if (!N0.hasOneUse())
4216 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
4218 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4219 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4221 LN0->getBasePtr(), LN0->getPointerInfo(),
4223 LN0->isVolatile(), LN0->isNonTemporal(),
4224 LN0->getAlignment());
4225 CombineTo(N, ExtLoad);
4226 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4227 N0.getValueType(), ExtLoad);
4228 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4229 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4231 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4235 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
4236 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
4237 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4238 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4239 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4240 EVT MemVT = LN0->getMemoryVT();
4241 if ((!LegalOperations && !LN0->isVolatile()) ||
4242 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
4243 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4245 LN0->getBasePtr(), LN0->getPointerInfo(),
4247 LN0->isVolatile(), LN0->isNonTemporal(),
4248 LN0->getAlignment());
4249 CombineTo(N, ExtLoad);
4250 CombineTo(N0.getNode(),
4251 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4252 N0.getValueType(), ExtLoad),
4253 ExtLoad.getValue(1));
4254 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4258 // fold (sext (and/or/xor (load x), cst)) ->
4259 // (and/or/xor (sextload x), (sext cst))
4260 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4261 N0.getOpcode() == ISD::XOR) &&
4262 isa<LoadSDNode>(N0.getOperand(0)) &&
4263 N0.getOperand(1).getOpcode() == ISD::Constant &&
4264 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
4265 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4266 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4267 if (LN0->getExtensionType() != ISD::ZEXTLOAD) {
4268 bool DoXform = true;
4269 SmallVector<SDNode*, 4> SetCCs;
4270 if (!N0.hasOneUse())
4271 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
4274 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT,
4275 LN0->getChain(), LN0->getBasePtr(),
4276 LN0->getPointerInfo(),
4279 LN0->isNonTemporal(),
4280 LN0->getAlignment());
4281 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4282 Mask = Mask.sext(VT.getSizeInBits());
4283 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4284 ExtLoad, DAG.getConstant(Mask, VT));
4285 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4286 N0.getOperand(0).getDebugLoc(),
4287 N0.getOperand(0).getValueType(), ExtLoad);
4289 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4290 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4292 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4297 if (N0.getOpcode() == ISD::SETCC) {
4298 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
4299 // Only do this before legalize for now.
4300 if (VT.isVector() && !LegalOperations) {
4301 EVT N0VT = N0.getOperand(0).getValueType();
4302 // We know that the # elements of the results is the same as the
4303 // # elements of the compare (and the # elements of the compare result
4304 // for that matter). Check to see that they are the same size. If so,
4305 // we know that the element size of the sext'd result matches the
4306 // element size of the compare operands.
4307 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4308 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4310 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4311 // If the desired elements are smaller or larger than the source
4312 // elements we can use a matching integer vector type and then
4313 // truncate/sign extend
4315 EVT MatchingElementType =
4316 EVT::getIntegerVT(*DAG.getContext(),
4317 N0VT.getScalarType().getSizeInBits());
4318 EVT MatchingVectorType =
4319 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4320 N0VT.getVectorNumElements());
4322 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4324 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4325 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4329 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
4330 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
4332 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
4334 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4335 NegOne, DAG.getConstant(0, VT),
4336 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4337 if (SCC.getNode()) return SCC;
4338 if (!LegalOperations ||
4339 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
4340 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4341 DAG.getSetCC(N->getDebugLoc(),
4342 TLI.getSetCCResultType(VT),
4343 N0.getOperand(0), N0.getOperand(1),
4344 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4345 NegOne, DAG.getConstant(0, VT));
4348 // fold (sext x) -> (zext x) if the sign bit is known zero.
4349 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
4350 DAG.SignBitIsZero(N0))
4351 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4356 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
4357 SDValue N0 = N->getOperand(0);
4358 EVT VT = N->getValueType(0);
4360 // fold (zext c1) -> c1
4361 if (isa<ConstantSDNode>(N0))
4362 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4363 // fold (zext (zext x)) -> (zext x)
4364 // fold (zext (aext x)) -> (zext x)
4365 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4366 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
4369 // fold (zext (truncate x)) -> (zext x) or
4370 // (zext (truncate x)) -> (truncate x)
4371 // This is valid when the truncated bits of x are already zero.
4372 // FIXME: We should extend this to work for vectors too.
4373 if (N0.getOpcode() == ISD::TRUNCATE && !VT.isVector()) {
4374 SDValue Op = N0.getOperand(0);
4376 = APInt::getBitsSet(Op.getValueSizeInBits(),
4377 N0.getValueSizeInBits(),
4378 std::min(Op.getValueSizeInBits(),
4379 VT.getSizeInBits()));
4380 APInt KnownZero, KnownOne;
4381 DAG.ComputeMaskedBits(Op, TruncatedBits, KnownZero, KnownOne);
4382 if (TruncatedBits == KnownZero) {
4383 if (VT.bitsGT(Op.getValueType()))
4384 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op);
4385 if (VT.bitsLT(Op.getValueType()))
4386 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4392 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4393 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
4394 if (N0.getOpcode() == ISD::TRUNCATE) {
4395 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4396 if (NarrowLoad.getNode()) {
4397 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4398 if (NarrowLoad.getNode() != N0.getNode()) {
4399 CombineTo(N0.getNode(), NarrowLoad);
4400 // CombineTo deleted the truncate, if needed, but not what's under it.
4403 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4407 // fold (zext (truncate x)) -> (and x, mask)
4408 if (N0.getOpcode() == ISD::TRUNCATE &&
4409 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
4411 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4412 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
4413 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4414 if (NarrowLoad.getNode()) {
4415 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4416 if (NarrowLoad.getNode() != N0.getNode()) {
4417 CombineTo(N0.getNode(), NarrowLoad);
4418 // CombineTo deleted the truncate, if needed, but not what's under it.
4421 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4424 SDValue Op = N0.getOperand(0);
4425 if (Op.getValueType().bitsLT(VT)) {
4426 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
4427 } else if (Op.getValueType().bitsGT(VT)) {
4428 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4430 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
4431 N0.getValueType().getScalarType());
4434 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
4435 // if either of the casts is not free.
4436 if (N0.getOpcode() == ISD::AND &&
4437 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4438 N0.getOperand(1).getOpcode() == ISD::Constant &&
4439 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4440 N0.getValueType()) ||
4441 !TLI.isZExtFree(N0.getValueType(), VT))) {
4442 SDValue X = N0.getOperand(0).getOperand(0);
4443 if (X.getValueType().bitsLT(VT)) {
4444 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
4445 } else if (X.getValueType().bitsGT(VT)) {
4446 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4448 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4449 Mask = Mask.zext(VT.getSizeInBits());
4450 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4451 X, DAG.getConstant(Mask, VT));
4454 // fold (zext (load x)) -> (zext (truncate (zextload x)))
4455 // None of the supported targets knows how to perform load and vector_zext
4456 // on vectors in one instruction. We only perform this transformation on
4458 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4459 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4460 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
4461 bool DoXform = true;
4462 SmallVector<SDNode*, 4> SetCCs;
4463 if (!N0.hasOneUse())
4464 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
4466 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4467 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4469 LN0->getBasePtr(), LN0->getPointerInfo(),
4471 LN0->isVolatile(), LN0->isNonTemporal(),
4472 LN0->getAlignment());
4473 CombineTo(N, ExtLoad);
4474 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4475 N0.getValueType(), ExtLoad);
4476 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4478 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4480 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4484 // fold (zext (and/or/xor (load x), cst)) ->
4485 // (and/or/xor (zextload x), (zext cst))
4486 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4487 N0.getOpcode() == ISD::XOR) &&
4488 isa<LoadSDNode>(N0.getOperand(0)) &&
4489 N0.getOperand(1).getOpcode() == ISD::Constant &&
4490 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
4491 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4492 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4493 if (LN0->getExtensionType() != ISD::SEXTLOAD) {
4494 bool DoXform = true;
4495 SmallVector<SDNode*, 4> SetCCs;
4496 if (!N0.hasOneUse())
4497 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
4500 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT,
4501 LN0->getChain(), LN0->getBasePtr(),
4502 LN0->getPointerInfo(),
4505 LN0->isNonTemporal(),
4506 LN0->getAlignment());
4507 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4508 Mask = Mask.zext(VT.getSizeInBits());
4509 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4510 ExtLoad, DAG.getConstant(Mask, VT));
4511 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4512 N0.getOperand(0).getDebugLoc(),
4513 N0.getOperand(0).getValueType(), ExtLoad);
4515 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4516 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4518 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4523 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
4524 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
4525 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4526 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4527 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4528 EVT MemVT = LN0->getMemoryVT();
4529 if ((!LegalOperations && !LN0->isVolatile()) ||
4530 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
4531 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4533 LN0->getBasePtr(), LN0->getPointerInfo(),
4535 LN0->isVolatile(), LN0->isNonTemporal(),
4536 LN0->getAlignment());
4537 CombineTo(N, ExtLoad);
4538 CombineTo(N0.getNode(),
4539 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
4541 ExtLoad.getValue(1));
4542 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4546 if (N0.getOpcode() == ISD::SETCC) {
4547 if (!LegalOperations && VT.isVector()) {
4548 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
4549 // Only do this before legalize for now.
4550 EVT N0VT = N0.getOperand(0).getValueType();
4551 EVT EltVT = VT.getVectorElementType();
4552 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
4553 DAG.getConstant(1, EltVT));
4554 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4555 // We know that the # elements of the results is the same as the
4556 // # elements of the compare (and the # elements of the compare result
4557 // for that matter). Check to see that they are the same size. If so,
4558 // we know that the element size of the sext'd result matches the
4559 // element size of the compare operands.
4560 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4561 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4563 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4564 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4565 &OneOps[0], OneOps.size()));
4567 // If the desired elements are smaller or larger than the source
4568 // elements we can use a matching integer vector type and then
4569 // truncate/sign extend
4570 EVT MatchingElementType =
4571 EVT::getIntegerVT(*DAG.getContext(),
4572 N0VT.getScalarType().getSizeInBits());
4573 EVT MatchingVectorType =
4574 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4575 N0VT.getVectorNumElements());
4577 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4579 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4580 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4581 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT),
4582 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4583 &OneOps[0], OneOps.size()));
4586 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4588 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4589 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4590 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4591 if (SCC.getNode()) return SCC;
4594 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
4595 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
4596 isa<ConstantSDNode>(N0.getOperand(1)) &&
4597 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
4599 SDValue ShAmt = N0.getOperand(1);
4600 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
4601 if (N0.getOpcode() == ISD::SHL) {
4602 SDValue InnerZExt = N0.getOperand(0);
4603 // If the original shl may be shifting out bits, do not perform this
4605 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
4606 InnerZExt.getOperand(0).getValueType().getSizeInBits();
4607 if (ShAmtVal > KnownZeroBits)
4611 DebugLoc DL = N->getDebugLoc();
4613 // Ensure that the shift amount is wide enough for the shifted value.
4614 if (VT.getSizeInBits() >= 256)
4615 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
4617 return DAG.getNode(N0.getOpcode(), DL, VT,
4618 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
4625 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
4626 SDValue N0 = N->getOperand(0);
4627 EVT VT = N->getValueType(0);
4629 // fold (aext c1) -> c1
4630 if (isa<ConstantSDNode>(N0))
4631 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
4632 // fold (aext (aext x)) -> (aext x)
4633 // fold (aext (zext x)) -> (zext x)
4634 // fold (aext (sext x)) -> (sext x)
4635 if (N0.getOpcode() == ISD::ANY_EXTEND ||
4636 N0.getOpcode() == ISD::ZERO_EXTEND ||
4637 N0.getOpcode() == ISD::SIGN_EXTEND)
4638 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
4640 // fold (aext (truncate (load x))) -> (aext (smaller load x))
4641 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
4642 if (N0.getOpcode() == ISD::TRUNCATE) {
4643 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4644 if (NarrowLoad.getNode()) {
4645 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4646 if (NarrowLoad.getNode() != N0.getNode()) {
4647 CombineTo(N0.getNode(), NarrowLoad);
4648 // CombineTo deleted the truncate, if needed, but not what's under it.
4651 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4655 // fold (aext (truncate x))
4656 if (N0.getOpcode() == ISD::TRUNCATE) {
4657 SDValue TruncOp = N0.getOperand(0);
4658 if (TruncOp.getValueType() == VT)
4659 return TruncOp; // x iff x size == zext size.
4660 if (TruncOp.getValueType().bitsGT(VT))
4661 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
4662 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
4665 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
4666 // if the trunc is not free.
4667 if (N0.getOpcode() == ISD::AND &&
4668 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4669 N0.getOperand(1).getOpcode() == ISD::Constant &&
4670 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4671 N0.getValueType())) {
4672 SDValue X = N0.getOperand(0).getOperand(0);
4673 if (X.getValueType().bitsLT(VT)) {
4674 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
4675 } else if (X.getValueType().bitsGT(VT)) {
4676 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
4678 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4679 Mask = Mask.zext(VT.getSizeInBits());
4680 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4681 X, DAG.getConstant(Mask, VT));
4684 // fold (aext (load x)) -> (aext (truncate (extload x)))
4685 // None of the supported targets knows how to perform load and any_ext
4686 // on vectors in one instruction. We only perform this transformation on
4688 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4689 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4690 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4691 bool DoXform = true;
4692 SmallVector<SDNode*, 4> SetCCs;
4693 if (!N0.hasOneUse())
4694 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
4696 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4697 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4699 LN0->getBasePtr(), LN0->getPointerInfo(),
4701 LN0->isVolatile(), LN0->isNonTemporal(),
4702 LN0->getAlignment());
4703 CombineTo(N, ExtLoad);
4704 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4705 N0.getValueType(), ExtLoad);
4706 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4707 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4709 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4713 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
4714 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
4715 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
4716 if (N0.getOpcode() == ISD::LOAD &&
4717 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4719 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4720 EVT MemVT = LN0->getMemoryVT();
4721 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
4722 VT, LN0->getChain(), LN0->getBasePtr(),
4723 LN0->getPointerInfo(), MemVT,
4724 LN0->isVolatile(), LN0->isNonTemporal(),
4725 LN0->getAlignment());
4726 CombineTo(N, ExtLoad);
4727 CombineTo(N0.getNode(),
4728 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4729 N0.getValueType(), ExtLoad),
4730 ExtLoad.getValue(1));
4731 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4734 if (N0.getOpcode() == ISD::SETCC) {
4735 // aext(setcc) -> sext_in_reg(vsetcc) for vectors.
4736 // Only do this before legalize for now.
4737 if (VT.isVector() && !LegalOperations) {
4738 EVT N0VT = N0.getOperand(0).getValueType();
4739 // We know that the # elements of the results is the same as the
4740 // # elements of the compare (and the # elements of the compare result
4741 // for that matter). Check to see that they are the same size. If so,
4742 // we know that the element size of the sext'd result matches the
4743 // element size of the compare operands.
4744 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4745 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4747 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4748 // If the desired elements are smaller or larger than the source
4749 // elements we can use a matching integer vector type and then
4750 // truncate/sign extend
4752 EVT MatchingElementType =
4753 EVT::getIntegerVT(*DAG.getContext(),
4754 N0VT.getScalarType().getSizeInBits());
4755 EVT MatchingVectorType =
4756 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4757 N0VT.getVectorNumElements());
4759 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4761 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4762 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4766 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4768 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4769 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4770 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4778 /// GetDemandedBits - See if the specified operand can be simplified with the
4779 /// knowledge that only the bits specified by Mask are used. If so, return the
4780 /// simpler operand, otherwise return a null SDValue.
4781 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
4782 switch (V.getOpcode()) {
4784 case ISD::Constant: {
4785 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode());
4786 assert(CV != 0 && "Const value should be ConstSDNode.");
4787 const APInt &CVal = CV->getAPIntValue();
4788 APInt NewVal = CVal & Mask;
4789 if (NewVal != CVal) {
4790 return DAG.getConstant(NewVal, V.getValueType());
4796 // If the LHS or RHS don't contribute bits to the or, drop them.
4797 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
4798 return V.getOperand(1);
4799 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
4800 return V.getOperand(0);
4803 // Only look at single-use SRLs.
4804 if (!V.getNode()->hasOneUse())
4806 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
4807 // See if we can recursively simplify the LHS.
4808 unsigned Amt = RHSC->getZExtValue();
4810 // Watch out for shift count overflow though.
4811 if (Amt >= Mask.getBitWidth()) break;
4812 APInt NewMask = Mask << Amt;
4813 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
4814 if (SimplifyLHS.getNode())
4815 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
4816 SimplifyLHS, V.getOperand(1));
4822 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
4823 /// bits and then truncated to a narrower type and where N is a multiple
4824 /// of number of bits of the narrower type, transform it to a narrower load
4825 /// from address + N / num of bits of new type. If the result is to be
4826 /// extended, also fold the extension to form a extending load.
4827 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
4828 unsigned Opc = N->getOpcode();
4830 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
4831 SDValue N0 = N->getOperand(0);
4832 EVT VT = N->getValueType(0);
4835 // This transformation isn't valid for vector loads.
4839 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
4841 if (Opc == ISD::SIGN_EXTEND_INREG) {
4842 ExtType = ISD::SEXTLOAD;
4843 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4844 } else if (Opc == ISD::SRL) {
4845 // Another special-case: SRL is basically zero-extending a narrower value.
4846 ExtType = ISD::ZEXTLOAD;
4848 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4849 if (!N01) return SDValue();
4850 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
4851 VT.getSizeInBits() - N01->getZExtValue());
4853 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
4856 unsigned EVTBits = ExtVT.getSizeInBits();
4858 // Do not generate loads of non-round integer types since these can
4859 // be expensive (and would be wrong if the type is not byte sized).
4860 if (!ExtVT.isRound())
4864 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4865 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4866 ShAmt = N01->getZExtValue();
4867 // Is the shift amount a multiple of size of VT?
4868 if ((ShAmt & (EVTBits-1)) == 0) {
4869 N0 = N0.getOperand(0);
4870 // Is the load width a multiple of size of VT?
4871 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
4875 // At this point, we must have a load or else we can't do the transform.
4876 if (!isa<LoadSDNode>(N0)) return SDValue();
4878 // If the shift amount is larger than the input type then we're not
4879 // accessing any of the loaded bytes. If the load was a zextload/extload
4880 // then the result of the shift+trunc is zero/undef (handled elsewhere).
4881 // If the load was a sextload then the result is a splat of the sign bit
4882 // of the extended byte. This is not worth optimizing for.
4883 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
4888 // If the load is shifted left (and the result isn't shifted back right),
4889 // we can fold the truncate through the shift.
4890 unsigned ShLeftAmt = 0;
4891 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
4892 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
4893 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4894 ShLeftAmt = N01->getZExtValue();
4895 N0 = N0.getOperand(0);
4899 // If we haven't found a load, we can't narrow it. Don't transform one with
4900 // multiple uses, this would require adding a new load.
4901 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() ||
4902 // Don't change the width of a volatile load.
4903 cast<LoadSDNode>(N0)->isVolatile())
4906 // Verify that we are actually reducing a load width here.
4907 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits)
4910 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4911 EVT PtrType = N0.getOperand(1).getValueType();
4913 // For big endian targets, we need to adjust the offset to the pointer to
4914 // load the correct bytes.
4915 if (TLI.isBigEndian()) {
4916 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
4917 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
4918 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
4921 uint64_t PtrOff = ShAmt / 8;
4922 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
4923 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
4924 PtrType, LN0->getBasePtr(),
4925 DAG.getConstant(PtrOff, PtrType));
4926 AddToWorkList(NewPtr.getNode());
4929 if (ExtType == ISD::NON_EXTLOAD)
4930 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
4931 LN0->getPointerInfo().getWithOffset(PtrOff),
4932 LN0->isVolatile(), LN0->isNonTemporal(),
4933 LN0->isInvariant(), NewAlign);
4935 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr,
4936 LN0->getPointerInfo().getWithOffset(PtrOff),
4937 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
4940 // Replace the old load's chain with the new load's chain.
4941 WorkListRemover DeadNodes(*this);
4942 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
4945 // Shift the result left, if we've swallowed a left shift.
4946 SDValue Result = Load;
4947 if (ShLeftAmt != 0) {
4948 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
4949 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
4951 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT,
4952 Result, DAG.getConstant(ShLeftAmt, ShImmTy));
4955 // Return the new loaded value.
4959 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
4960 SDValue N0 = N->getOperand(0);
4961 SDValue N1 = N->getOperand(1);
4962 EVT VT = N->getValueType(0);
4963 EVT EVT = cast<VTSDNode>(N1)->getVT();
4964 unsigned VTBits = VT.getScalarType().getSizeInBits();
4965 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
4967 // fold (sext_in_reg c1) -> c1
4968 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
4969 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
4971 // If the input is already sign extended, just drop the extension.
4972 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
4975 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
4976 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
4977 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
4978 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
4979 N0.getOperand(0), N1);
4982 // fold (sext_in_reg (sext x)) -> (sext x)
4983 // fold (sext_in_reg (aext x)) -> (sext x)
4984 // if x is small enough.
4985 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
4986 SDValue N00 = N0.getOperand(0);
4987 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
4988 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
4989 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
4992 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
4993 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
4994 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
4996 // fold operands of sext_in_reg based on knowledge that the top bits are not
4998 if (SimplifyDemandedBits(SDValue(N, 0)))
4999 return SDValue(N, 0);
5001 // fold (sext_in_reg (load x)) -> (smaller sextload x)
5002 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
5003 SDValue NarrowLoad = ReduceLoadWidth(N);
5004 if (NarrowLoad.getNode())
5007 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
5008 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
5009 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
5010 if (N0.getOpcode() == ISD::SRL) {
5011 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
5012 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
5013 // We can turn this into an SRA iff the input to the SRL is already sign
5015 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
5016 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
5017 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
5018 N0.getOperand(0), N0.getOperand(1));
5022 // fold (sext_inreg (extload x)) -> (sextload x)
5023 if (ISD::isEXTLoad(N0.getNode()) &&
5024 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5025 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5026 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5027 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5028 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5029 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
5031 LN0->getBasePtr(), LN0->getPointerInfo(),
5033 LN0->isVolatile(), LN0->isNonTemporal(),
5034 LN0->getAlignment());
5035 CombineTo(N, ExtLoad);
5036 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5037 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5039 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
5040 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5042 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5043 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5044 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5045 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5046 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
5048 LN0->getBasePtr(), LN0->getPointerInfo(),
5050 LN0->isVolatile(), LN0->isNonTemporal(),
5051 LN0->getAlignment());
5052 CombineTo(N, ExtLoad);
5053 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5054 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5057 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
5058 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
5059 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
5060 N0.getOperand(1), false);
5061 if (BSwap.getNode() != 0)
5062 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
5069 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
5070 SDValue N0 = N->getOperand(0);
5071 EVT VT = N->getValueType(0);
5072 bool isLE = TLI.isLittleEndian();
5075 if (N0.getValueType() == N->getValueType(0))
5077 // fold (truncate c1) -> c1
5078 if (isa<ConstantSDNode>(N0))
5079 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
5080 // fold (truncate (truncate x)) -> (truncate x)
5081 if (N0.getOpcode() == ISD::TRUNCATE)
5082 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
5083 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
5084 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
5085 N0.getOpcode() == ISD::SIGN_EXTEND ||
5086 N0.getOpcode() == ISD::ANY_EXTEND) {
5087 if (N0.getOperand(0).getValueType().bitsLT(VT))
5088 // if the source is smaller than the dest, we still need an extend
5089 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
5091 else if (N0.getOperand(0).getValueType().bitsGT(VT))
5092 // if the source is larger than the dest, than we just need the truncate
5093 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
5095 // if the source and dest are the same type, we can drop both the extend
5096 // and the truncate.
5097 return N0.getOperand(0);
5100 // Fold extract-and-trunc into a narrow extract. For example:
5101 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
5102 // i32 y = TRUNCATE(i64 x)
5104 // v16i8 b = BITCAST (v2i64 val)
5105 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8)
5107 // Note: We only run this optimization after type legalization (which often
5108 // creates this pattern) and before operation legalization after which
5109 // we need to be more careful about the vector instructions that we generate.
5110 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5111 LegalTypes && !LegalOperations && N0->hasOneUse()) {
5113 EVT VecTy = N0.getOperand(0).getValueType();
5114 EVT ExTy = N0.getValueType();
5115 EVT TrTy = N->getValueType(0);
5117 unsigned NumElem = VecTy.getVectorNumElements();
5118 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits();
5120 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem);
5121 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size");
5123 SDValue EltNo = N0->getOperand(1);
5124 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
5125 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5127 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
5129 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5130 NVT, N0.getOperand(0));
5132 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
5133 N->getDebugLoc(), TrTy, V,
5134 DAG.getConstant(Index, MVT::i32));
5138 // See if we can simplify the input to this truncate through knowledge that
5139 // only the low bits are being used.
5140 // For example "trunc (or (shl x, 8), y)" // -> trunc y
5141 // Currently we only perform this optimization on scalars because vectors
5142 // may have different active low bits.
5143 if (!VT.isVector()) {
5145 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
5146 VT.getSizeInBits()));
5147 if (Shorter.getNode())
5148 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
5150 // fold (truncate (load x)) -> (smaller load x)
5151 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
5152 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
5153 SDValue Reduced = ReduceLoadWidth(N);
5154 if (Reduced.getNode())
5158 // Simplify the operands using demanded-bits information.
5159 if (!VT.isVector() &&
5160 SimplifyDemandedBits(SDValue(N, 0)))
5161 return SDValue(N, 0);
5166 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
5167 SDValue Elt = N->getOperand(i);
5168 if (Elt.getOpcode() != ISD::MERGE_VALUES)
5169 return Elt.getNode();
5170 return Elt.getOperand(Elt.getResNo()).getNode();
5173 /// CombineConsecutiveLoads - build_pair (load, load) -> load
5174 /// if load locations are consecutive.
5175 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
5176 assert(N->getOpcode() == ISD::BUILD_PAIR);
5178 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
5179 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
5180 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
5181 LD1->getPointerInfo().getAddrSpace() !=
5182 LD2->getPointerInfo().getAddrSpace())
5184 EVT LD1VT = LD1->getValueType(0);
5186 if (ISD::isNON_EXTLoad(LD2) &&
5188 // If both are volatile this would reduce the number of volatile loads.
5189 // If one is volatile it might be ok, but play conservative and bail out.
5190 !LD1->isVolatile() &&
5191 !LD2->isVolatile() &&
5192 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
5193 unsigned Align = LD1->getAlignment();
5194 unsigned NewAlign = TLI.getTargetData()->
5195 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5197 if (NewAlign <= Align &&
5198 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
5199 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
5200 LD1->getBasePtr(), LD1->getPointerInfo(),
5201 false, false, false, Align);
5207 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
5208 SDValue N0 = N->getOperand(0);
5209 EVT VT = N->getValueType(0);
5211 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
5212 // Only do this before legalize, since afterward the target may be depending
5213 // on the bitconvert.
5214 // First check to see if this is all constant.
5216 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
5218 bool isSimple = true;
5219 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
5220 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
5221 N0.getOperand(i).getOpcode() != ISD::Constant &&
5222 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
5227 EVT DestEltVT = N->getValueType(0).getVectorElementType();
5228 assert(!DestEltVT.isVector() &&
5229 "Element type of vector ValueType must not be vector!");
5231 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
5234 // If the input is a constant, let getNode fold it.
5235 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
5236 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0);
5237 if (Res.getNode() != N) {
5238 if (!LegalOperations ||
5239 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
5242 // Folding it resulted in an illegal node, and it's too late to
5243 // do that. Clean up the old node and forego the transformation.
5244 // Ideally this won't happen very often, because instcombine
5245 // and the earlier dagcombine runs (where illegal nodes are
5246 // permitted) should have folded most of them already.
5247 DAG.DeleteNode(Res.getNode());
5251 // (conv (conv x, t1), t2) -> (conv x, t2)
5252 if (N0.getOpcode() == ISD::BITCAST)
5253 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT,
5256 // fold (conv (load x)) -> (load (conv*)x)
5257 // If the resultant load doesn't need a higher alignment than the original!
5258 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
5259 // Do not change the width of a volatile load.
5260 !cast<LoadSDNode>(N0)->isVolatile() &&
5261 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
5262 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5263 unsigned Align = TLI.getTargetData()->
5264 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5265 unsigned OrigAlign = LN0->getAlignment();
5267 if (Align <= OrigAlign) {
5268 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
5269 LN0->getBasePtr(), LN0->getPointerInfo(),
5270 LN0->isVolatile(), LN0->isNonTemporal(),
5271 LN0->isInvariant(), OrigAlign);
5273 CombineTo(N0.getNode(),
5274 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5275 N0.getValueType(), Load),
5281 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
5282 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
5283 // This often reduces constant pool loads.
5284 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
5285 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
5286 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT,
5288 AddToWorkList(NewConv.getNode());
5290 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5291 if (N0.getOpcode() == ISD::FNEG)
5292 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
5293 NewConv, DAG.getConstant(SignBit, VT));
5294 assert(N0.getOpcode() == ISD::FABS);
5295 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
5296 NewConv, DAG.getConstant(~SignBit, VT));
5299 // fold (bitconvert (fcopysign cst, x)) ->
5300 // (or (and (bitconvert x), sign), (and cst, (not sign)))
5301 // Note that we don't handle (copysign x, cst) because this can always be
5302 // folded to an fneg or fabs.
5303 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
5304 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
5305 VT.isInteger() && !VT.isVector()) {
5306 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
5307 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
5308 if (isTypeLegal(IntXVT)) {
5309 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5310 IntXVT, N0.getOperand(1));
5311 AddToWorkList(X.getNode());
5313 // If X has a different width than the result/lhs, sext it or truncate it.
5314 unsigned VTWidth = VT.getSizeInBits();
5315 if (OrigXWidth < VTWidth) {
5316 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
5317 AddToWorkList(X.getNode());
5318 } else if (OrigXWidth > VTWidth) {
5319 // To get the sign bit in the right place, we have to shift it right
5320 // before truncating.
5321 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
5322 X.getValueType(), X,
5323 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
5324 AddToWorkList(X.getNode());
5325 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
5326 AddToWorkList(X.getNode());
5329 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5330 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
5331 X, DAG.getConstant(SignBit, VT));
5332 AddToWorkList(X.getNode());
5334 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5335 VT, N0.getOperand(0));
5336 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
5337 Cst, DAG.getConstant(~SignBit, VT));
5338 AddToWorkList(Cst.getNode());
5340 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
5344 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
5345 if (N0.getOpcode() == ISD::BUILD_PAIR) {
5346 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
5347 if (CombineLD.getNode())
5354 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
5355 EVT VT = N->getValueType(0);
5356 return CombineConsecutiveLoads(N, VT);
5359 /// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector
5360 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
5361 /// destination element value type.
5362 SDValue DAGCombiner::
5363 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
5364 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
5366 // If this is already the right type, we're done.
5367 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
5369 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
5370 unsigned DstBitSize = DstEltVT.getSizeInBits();
5372 // If this is a conversion of N elements of one type to N elements of another
5373 // type, convert each element. This handles FP<->INT cases.
5374 if (SrcBitSize == DstBitSize) {
5375 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5376 BV->getValueType(0).getVectorNumElements());
5378 // Due to the FP element handling below calling this routine recursively,
5379 // we can end up with a scalar-to-vector node here.
5380 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
5381 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5382 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5383 DstEltVT, BV->getOperand(0)));
5385 SmallVector<SDValue, 8> Ops;
5386 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5387 SDValue Op = BV->getOperand(i);
5388 // If the vector element type is not legal, the BUILD_VECTOR operands
5389 // are promoted and implicitly truncated. Make that explicit here.
5390 if (Op.getValueType() != SrcEltVT)
5391 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
5392 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5394 AddToWorkList(Ops.back().getNode());
5396 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5397 &Ops[0], Ops.size());
5400 // Otherwise, we're growing or shrinking the elements. To avoid having to
5401 // handle annoying details of growing/shrinking FP values, we convert them to
5403 if (SrcEltVT.isFloatingPoint()) {
5404 // Convert the input float vector to a int vector where the elements are the
5406 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
5407 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
5408 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
5412 // Now we know the input is an integer vector. If the output is a FP type,
5413 // convert to integer first, then to FP of the right size.
5414 if (DstEltVT.isFloatingPoint()) {
5415 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
5416 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
5417 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
5419 // Next, convert to FP elements of the same size.
5420 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
5423 // Okay, we know the src/dst types are both integers of differing types.
5424 // Handling growing first.
5425 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
5426 if (SrcBitSize < DstBitSize) {
5427 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
5429 SmallVector<SDValue, 8> Ops;
5430 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
5431 i += NumInputsPerOutput) {
5432 bool isLE = TLI.isLittleEndian();
5433 APInt NewBits = APInt(DstBitSize, 0);
5434 bool EltIsUndef = true;
5435 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
5436 // Shift the previously computed bits over.
5437 NewBits <<= SrcBitSize;
5438 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
5439 if (Op.getOpcode() == ISD::UNDEF) continue;
5442 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
5443 zextOrTrunc(SrcBitSize).zext(DstBitSize);
5447 Ops.push_back(DAG.getUNDEF(DstEltVT));
5449 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
5452 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
5453 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5454 &Ops[0], Ops.size());
5457 // Finally, this must be the case where we are shrinking elements: each input
5458 // turns into multiple outputs.
5459 bool isS2V = ISD::isScalarToVector(BV);
5460 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
5461 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5462 NumOutputsPerInput*BV->getNumOperands());
5463 SmallVector<SDValue, 8> Ops;
5465 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5466 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
5467 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
5468 Ops.push_back(DAG.getUNDEF(DstEltVT));
5472 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
5473 getAPIntValue().zextOrTrunc(SrcBitSize);
5475 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
5476 APInt ThisVal = OpVal.trunc(DstBitSize);
5477 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
5478 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
5479 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
5480 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5482 OpVal = OpVal.lshr(DstBitSize);
5485 // For big endian targets, swap the order of the pieces of each element.
5486 if (TLI.isBigEndian())
5487 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
5490 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5491 &Ops[0], Ops.size());
5494 SDValue DAGCombiner::visitFADD(SDNode *N) {
5495 SDValue N0 = N->getOperand(0);
5496 SDValue N1 = N->getOperand(1);
5497 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5498 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5499 EVT VT = N->getValueType(0);
5502 if (VT.isVector()) {
5503 SDValue FoldedVOp = SimplifyVBinOp(N);
5504 if (FoldedVOp.getNode()) return FoldedVOp;
5507 // fold (fadd c1, c2) -> (fadd c1, c2)
5508 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5509 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
5510 // canonicalize constant to RHS
5511 if (N0CFP && !N1CFP)
5512 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
5513 // fold (fadd A, 0) -> A
5514 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5515 N1CFP->getValueAPF().isZero())
5517 // fold (fadd A, (fneg B)) -> (fsub A, B)
5518 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5519 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
5520 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
5521 GetNegatedExpression(N1, DAG, LegalOperations));
5522 // fold (fadd (fneg A), B) -> (fsub B, A)
5523 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5524 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
5525 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
5526 GetNegatedExpression(N0, DAG, LegalOperations));
5528 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
5529 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5530 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
5531 isa<ConstantFPSDNode>(N0.getOperand(1)))
5532 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
5533 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5534 N0.getOperand(1), N1));
5539 SDValue DAGCombiner::visitFSUB(SDNode *N) {
5540 SDValue N0 = N->getOperand(0);
5541 SDValue N1 = N->getOperand(1);
5542 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5543 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5544 EVT VT = N->getValueType(0);
5547 if (VT.isVector()) {
5548 SDValue FoldedVOp = SimplifyVBinOp(N);
5549 if (FoldedVOp.getNode()) return FoldedVOp;
5552 // fold (fsub c1, c2) -> c1-c2
5553 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5554 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
5555 // fold (fsub A, 0) -> A
5556 if (DAG.getTarget().Options.UnsafeFPMath &&
5557 N1CFP && N1CFP->getValueAPF().isZero())
5559 // fold (fsub 0, B) -> -B
5560 if (DAG.getTarget().Options.UnsafeFPMath &&
5561 N0CFP && N0CFP->getValueAPF().isZero()) {
5562 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options))
5563 return GetNegatedExpression(N1, DAG, LegalOperations);
5564 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5565 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
5567 // fold (fsub A, (fneg B)) -> (fadd A, B)
5568 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options))
5569 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
5570 GetNegatedExpression(N1, DAG, LegalOperations));
5575 SDValue DAGCombiner::visitFMUL(SDNode *N) {
5576 SDValue N0 = N->getOperand(0);
5577 SDValue N1 = N->getOperand(1);
5578 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5579 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5580 EVT VT = N->getValueType(0);
5581 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5584 if (VT.isVector()) {
5585 SDValue FoldedVOp = SimplifyVBinOp(N);
5586 if (FoldedVOp.getNode()) return FoldedVOp;
5589 // fold (fmul c1, c2) -> c1*c2
5590 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5591 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
5592 // canonicalize constant to RHS
5593 if (N0CFP && !N1CFP)
5594 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
5595 // fold (fmul A, 0) -> 0
5596 if (DAG.getTarget().Options.UnsafeFPMath &&
5597 N1CFP && N1CFP->getValueAPF().isZero())
5599 // fold (fmul A, 0) -> 0, vector edition.
5600 if (DAG.getTarget().Options.UnsafeFPMath &&
5601 ISD::isBuildVectorAllZeros(N1.getNode()))
5603 // fold (fmul X, 2.0) -> (fadd X, X)
5604 if (N1CFP && N1CFP->isExactlyValue(+2.0))
5605 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
5606 // fold (fmul X, -1.0) -> (fneg X)
5607 if (N1CFP && N1CFP->isExactlyValue(-1.0))
5608 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5609 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
5611 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
5612 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
5613 &DAG.getTarget().Options)) {
5614 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI,
5615 &DAG.getTarget().Options)) {
5616 // Both can be negated for free, check to see if at least one is cheaper
5618 if (LHSNeg == 2 || RHSNeg == 2)
5619 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5620 GetNegatedExpression(N0, DAG, LegalOperations),
5621 GetNegatedExpression(N1, DAG, LegalOperations));
5625 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
5626 if (DAG.getTarget().Options.UnsafeFPMath &&
5627 N1CFP && N0.getOpcode() == ISD::FMUL &&
5628 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
5629 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
5630 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5631 N0.getOperand(1), N1));
5636 SDValue DAGCombiner::visitFDIV(SDNode *N) {
5637 SDValue N0 = N->getOperand(0);
5638 SDValue N1 = N->getOperand(1);
5639 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5640 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5641 EVT VT = N->getValueType(0);
5642 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5645 if (VT.isVector()) {
5646 SDValue FoldedVOp = SimplifyVBinOp(N);
5647 if (FoldedVOp.getNode()) return FoldedVOp;
5650 // fold (fdiv c1, c2) -> c1/c2
5651 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5652 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
5655 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
5656 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
5657 &DAG.getTarget().Options)) {
5658 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI,
5659 &DAG.getTarget().Options)) {
5660 // Both can be negated for free, check to see if at least one is cheaper
5662 if (LHSNeg == 2 || RHSNeg == 2)
5663 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
5664 GetNegatedExpression(N0, DAG, LegalOperations),
5665 GetNegatedExpression(N1, DAG, LegalOperations));
5672 SDValue DAGCombiner::visitFREM(SDNode *N) {
5673 SDValue N0 = N->getOperand(0);
5674 SDValue N1 = N->getOperand(1);
5675 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5676 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5677 EVT VT = N->getValueType(0);
5679 // fold (frem c1, c2) -> fmod(c1,c2)
5680 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5681 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
5686 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
5687 SDValue N0 = N->getOperand(0);
5688 SDValue N1 = N->getOperand(1);
5689 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5690 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5691 EVT VT = N->getValueType(0);
5693 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
5694 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
5697 const APFloat& V = N1CFP->getValueAPF();
5698 // copysign(x, c1) -> fabs(x) iff ispos(c1)
5699 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
5700 if (!V.isNegative()) {
5701 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
5702 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5704 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5705 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
5706 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
5710 // copysign(fabs(x), y) -> copysign(x, y)
5711 // copysign(fneg(x), y) -> copysign(x, y)
5712 // copysign(copysign(x,z), y) -> copysign(x, y)
5713 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
5714 N0.getOpcode() == ISD::FCOPYSIGN)
5715 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5716 N0.getOperand(0), N1);
5718 // copysign(x, abs(y)) -> abs(x)
5719 if (N1.getOpcode() == ISD::FABS)
5720 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5722 // copysign(x, copysign(y,z)) -> copysign(x, z)
5723 if (N1.getOpcode() == ISD::FCOPYSIGN)
5724 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5725 N0, N1.getOperand(1));
5727 // copysign(x, fp_extend(y)) -> copysign(x, y)
5728 // copysign(x, fp_round(y)) -> copysign(x, y)
5729 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
5730 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5731 N0, N1.getOperand(0));
5736 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
5737 SDValue N0 = N->getOperand(0);
5738 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
5739 EVT VT = N->getValueType(0);
5740 EVT OpVT = N0.getValueType();
5742 // fold (sint_to_fp c1) -> c1fp
5743 if (N0C && OpVT != MVT::ppcf128 &&
5744 // ...but only if the target supports immediate floating-point values
5745 (!LegalOperations ||
5746 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
5747 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5749 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
5750 // but UINT_TO_FP is legal on this target, try to convert.
5751 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
5752 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
5753 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
5754 if (DAG.SignBitIsZero(N0))
5755 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5761 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
5762 SDValue N0 = N->getOperand(0);
5763 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
5764 EVT VT = N->getValueType(0);
5765 EVT OpVT = N0.getValueType();
5767 // fold (uint_to_fp c1) -> c1fp
5768 if (N0C && OpVT != MVT::ppcf128 &&
5769 // ...but only if the target supports immediate floating-point values
5770 (!LegalOperations ||
5771 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
5772 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5774 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
5775 // but SINT_TO_FP is legal on this target, try to convert.
5776 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
5777 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
5778 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
5779 if (DAG.SignBitIsZero(N0))
5780 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5786 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
5787 SDValue N0 = N->getOperand(0);
5788 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5789 EVT VT = N->getValueType(0);
5791 // fold (fp_to_sint c1fp) -> c1
5793 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
5798 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
5799 SDValue N0 = N->getOperand(0);
5800 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5801 EVT VT = N->getValueType(0);
5803 // fold (fp_to_uint c1fp) -> c1
5804 if (N0CFP && VT != MVT::ppcf128)
5805 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
5810 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
5811 SDValue N0 = N->getOperand(0);
5812 SDValue N1 = N->getOperand(1);
5813 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5814 EVT VT = N->getValueType(0);
5816 // fold (fp_round c1fp) -> c1fp
5817 if (N0CFP && N0.getValueType() != MVT::ppcf128)
5818 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
5820 // fold (fp_round (fp_extend x)) -> x
5821 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
5822 return N0.getOperand(0);
5824 // fold (fp_round (fp_round x)) -> (fp_round x)
5825 if (N0.getOpcode() == ISD::FP_ROUND) {
5826 // This is a value preserving truncation if both round's are.
5827 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
5828 N0.getNode()->getConstantOperandVal(1) == 1;
5829 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
5830 DAG.getIntPtrConstant(IsTrunc));
5833 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
5834 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
5835 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
5836 N0.getOperand(0), N1);
5837 AddToWorkList(Tmp.getNode());
5838 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5839 Tmp, N0.getOperand(1));
5845 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
5846 SDValue N0 = N->getOperand(0);
5847 EVT VT = N->getValueType(0);
5848 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
5849 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5851 // fold (fp_round_inreg c1fp) -> c1fp
5852 if (N0CFP && isTypeLegal(EVT)) {
5853 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
5854 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
5860 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
5861 SDValue N0 = N->getOperand(0);
5862 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5863 EVT VT = N->getValueType(0);
5865 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
5866 if (N->hasOneUse() &&
5867 N->use_begin()->getOpcode() == ISD::FP_ROUND)
5870 // fold (fp_extend c1fp) -> c1fp
5871 if (N0CFP && VT != MVT::ppcf128)
5872 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
5874 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
5876 if (N0.getOpcode() == ISD::FP_ROUND
5877 && N0.getNode()->getConstantOperandVal(1) == 1) {
5878 SDValue In = N0.getOperand(0);
5879 if (In.getValueType() == VT) return In;
5880 if (VT.bitsLT(In.getValueType()))
5881 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
5882 In, N0.getOperand(1));
5883 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
5886 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
5887 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
5888 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5889 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
5890 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5891 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
5893 LN0->getBasePtr(), LN0->getPointerInfo(),
5895 LN0->isVolatile(), LN0->isNonTemporal(),
5896 LN0->getAlignment());
5897 CombineTo(N, ExtLoad);
5898 CombineTo(N0.getNode(),
5899 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
5900 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
5901 ExtLoad.getValue(1));
5902 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5908 SDValue DAGCombiner::visitFNEG(SDNode *N) {
5909 SDValue N0 = N->getOperand(0);
5910 EVT VT = N->getValueType(0);
5912 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(),
5913 &DAG.getTarget().Options))
5914 return GetNegatedExpression(N0, DAG, LegalOperations);
5916 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
5917 // constant pool values.
5918 if (N0.getOpcode() == ISD::BITCAST &&
5920 N0.getNode()->hasOneUse() &&
5921 N0.getOperand(0).getValueType().isInteger()) {
5922 SDValue Int = N0.getOperand(0);
5923 EVT IntVT = Int.getValueType();
5924 if (IntVT.isInteger() && !IntVT.isVector()) {
5925 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
5926 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5927 AddToWorkList(Int.getNode());
5928 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5936 SDValue DAGCombiner::visitFABS(SDNode *N) {
5937 SDValue N0 = N->getOperand(0);
5938 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5939 EVT VT = N->getValueType(0);
5941 // fold (fabs c1) -> fabs(c1)
5942 if (N0CFP && VT != MVT::ppcf128)
5943 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5944 // fold (fabs (fabs x)) -> (fabs x)
5945 if (N0.getOpcode() == ISD::FABS)
5946 return N->getOperand(0);
5947 // fold (fabs (fneg x)) -> (fabs x)
5948 // fold (fabs (fcopysign x, y)) -> (fabs x)
5949 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
5950 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
5952 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
5953 // constant pool values.
5954 if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
5955 N0.getOperand(0).getValueType().isInteger() &&
5956 !N0.getOperand(0).getValueType().isVector()) {
5957 SDValue Int = N0.getOperand(0);
5958 EVT IntVT = Int.getValueType();
5959 if (IntVT.isInteger() && !IntVT.isVector()) {
5960 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
5961 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5962 AddToWorkList(Int.getNode());
5963 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5964 N->getValueType(0), Int);
5971 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
5972 SDValue Chain = N->getOperand(0);
5973 SDValue N1 = N->getOperand(1);
5974 SDValue N2 = N->getOperand(2);
5976 // If N is a constant we could fold this into a fallthrough or unconditional
5977 // branch. However that doesn't happen very often in normal code, because
5978 // Instcombine/SimplifyCFG should have handled the available opportunities.
5979 // If we did this folding here, it would be necessary to update the
5980 // MachineBasicBlock CFG, which is awkward.
5982 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
5984 if (N1.getOpcode() == ISD::SETCC &&
5985 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
5986 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5987 Chain, N1.getOperand(2),
5988 N1.getOperand(0), N1.getOperand(1), N2);
5991 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
5992 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
5993 (N1.getOperand(0).hasOneUse() &&
5994 N1.getOperand(0).getOpcode() == ISD::SRL))) {
5996 if (N1.getOpcode() == ISD::TRUNCATE) {
5997 // Look pass the truncate.
5998 Trunc = N1.getNode();
5999 N1 = N1.getOperand(0);
6002 // Match this pattern so that we can generate simpler code:
6005 // %b = and i32 %a, 2
6006 // %c = srl i32 %b, 1
6007 // brcond i32 %c ...
6012 // %b = and i32 %a, 2
6013 // %c = setcc eq %b, 0
6016 // This applies only when the AND constant value has one bit set and the
6017 // SRL constant is equal to the log2 of the AND constant. The back-end is
6018 // smart enough to convert the result into a TEST/JMP sequence.
6019 SDValue Op0 = N1.getOperand(0);
6020 SDValue Op1 = N1.getOperand(1);
6022 if (Op0.getOpcode() == ISD::AND &&
6023 Op1.getOpcode() == ISD::Constant) {
6024 SDValue AndOp1 = Op0.getOperand(1);
6026 if (AndOp1.getOpcode() == ISD::Constant) {
6027 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
6029 if (AndConst.isPowerOf2() &&
6030 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
6032 DAG.getSetCC(N->getDebugLoc(),
6033 TLI.getSetCCResultType(Op0.getValueType()),
6034 Op0, DAG.getConstant(0, Op0.getValueType()),
6037 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6038 MVT::Other, Chain, SetCC, N2);
6039 // Don't add the new BRCond into the worklist or else SimplifySelectCC
6040 // will convert it back to (X & C1) >> C2.
6041 CombineTo(N, NewBRCond, false);
6042 // Truncate is dead.
6044 removeFromWorkList(Trunc);
6045 DAG.DeleteNode(Trunc);
6047 // Replace the uses of SRL with SETCC
6048 WorkListRemover DeadNodes(*this);
6049 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
6050 removeFromWorkList(N1.getNode());
6051 DAG.DeleteNode(N1.getNode());
6052 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6058 // Restore N1 if the above transformation doesn't match.
6059 N1 = N->getOperand(1);
6062 // Transform br(xor(x, y)) -> br(x != y)
6063 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
6064 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
6065 SDNode *TheXor = N1.getNode();
6066 SDValue Op0 = TheXor->getOperand(0);
6067 SDValue Op1 = TheXor->getOperand(1);
6068 if (Op0.getOpcode() == Op1.getOpcode()) {
6069 // Avoid missing important xor optimizations.
6070 SDValue Tmp = visitXOR(TheXor);
6071 if (Tmp.getNode() && Tmp.getNode() != TheXor) {
6072 DEBUG(dbgs() << "\nReplacing.8 ";
6074 dbgs() << "\nWith: ";
6075 Tmp.getNode()->dump(&DAG);
6077 WorkListRemover DeadNodes(*this);
6078 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes);
6079 removeFromWorkList(TheXor);
6080 DAG.DeleteNode(TheXor);
6081 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6082 MVT::Other, Chain, Tmp, N2);
6086 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
6088 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
6089 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
6090 Op0.getOpcode() == ISD::XOR) {
6091 TheXor = Op0.getNode();
6095 EVT SetCCVT = N1.getValueType();
6097 SetCCVT = TLI.getSetCCResultType(SetCCVT);
6098 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
6101 Equal ? ISD::SETEQ : ISD::SETNE);
6102 // Replace the uses of XOR with SETCC
6103 WorkListRemover DeadNodes(*this);
6104 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
6105 removeFromWorkList(N1.getNode());
6106 DAG.DeleteNode(N1.getNode());
6107 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6108 MVT::Other, Chain, SetCC, N2);
6115 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
6117 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
6118 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
6119 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
6121 // If N is a constant we could fold this into a fallthrough or unconditional
6122 // branch. However that doesn't happen very often in normal code, because
6123 // Instcombine/SimplifyCFG should have handled the available opportunities.
6124 // If we did this folding here, it would be necessary to update the
6125 // MachineBasicBlock CFG, which is awkward.
6127 // Use SimplifySetCC to simplify SETCC's.
6128 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
6129 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
6131 if (Simp.getNode()) AddToWorkList(Simp.getNode());
6133 // fold to a simpler setcc
6134 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
6135 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
6136 N->getOperand(0), Simp.getOperand(2),
6137 Simp.getOperand(0), Simp.getOperand(1),
6143 /// canFoldInAddressingMode - Return true if 'Use' is a load or a store that
6144 /// uses N as its base pointer and that N may be folded in the load / store
6145 /// addressing mode.
6146 static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
6148 const TargetLowering &TLI) {
6150 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) {
6151 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
6153 VT = Use->getValueType(0);
6154 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) {
6155 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
6157 VT = ST->getValue().getValueType();
6161 TargetLowering::AddrMode AM;
6162 if (N->getOpcode() == ISD::ADD) {
6163 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
6166 AM.BaseOffs = Offset->getSExtValue();
6170 } else if (N->getOpcode() == ISD::SUB) {
6171 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
6174 AM.BaseOffs = -Offset->getSExtValue();
6181 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext()));
6184 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
6185 /// pre-indexed load / store when the base pointer is an add or subtract
6186 /// and it has other uses besides the load / store. After the
6187 /// transformation, the new indexed load / store has effectively folded
6188 /// the add / subtract in and all of its other uses are redirected to the
6189 /// new load / store.
6190 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
6191 if (Level < AfterLegalizeDAG)
6197 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6198 if (LD->isIndexed())
6200 VT = LD->getMemoryVT();
6201 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
6202 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
6204 Ptr = LD->getBasePtr();
6205 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6206 if (ST->isIndexed())
6208 VT = ST->getMemoryVT();
6209 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
6210 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
6212 Ptr = ST->getBasePtr();
6218 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
6219 // out. There is no reason to make this a preinc/predec.
6220 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
6221 Ptr.getNode()->hasOneUse())
6224 // Ask the target to do addressing mode selection.
6227 ISD::MemIndexedMode AM = ISD::UNINDEXED;
6228 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
6230 // Don't create a indexed load / store with zero offset.
6231 if (isa<ConstantSDNode>(Offset) &&
6232 cast<ConstantSDNode>(Offset)->isNullValue())
6235 // Try turning it into a pre-indexed load / store except when:
6236 // 1) The new base ptr is a frame index.
6237 // 2) If N is a store and the new base ptr is either the same as or is a
6238 // predecessor of the value being stored.
6239 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
6240 // that would create a cycle.
6241 // 4) All uses are load / store ops that use it as old base ptr.
6243 // Check #1. Preinc'ing a frame index would require copying the stack pointer
6244 // (plus the implicit offset) to a register to preinc anyway.
6245 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
6250 SDValue Val = cast<StoreSDNode>(N)->getValue();
6251 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
6255 // Now check for #3 and #4.
6256 bool RealUse = false;
6258 // Caches for hasPredecessorHelper
6259 SmallPtrSet<const SDNode *, 32> Visited;
6260 SmallVector<const SDNode *, 16> Worklist;
6262 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
6263 E = Ptr.getNode()->use_end(); I != E; ++I) {
6267 if (N->hasPredecessorHelper(Use, Visited, Worklist))
6270 // If Ptr may be folded in addressing mode of other use, then it's
6271 // not profitable to do this transformation.
6272 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI))
6281 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
6282 BasePtr, Offset, AM);
6284 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
6285 BasePtr, Offset, AM);
6288 DEBUG(dbgs() << "\nReplacing.4 ";
6290 dbgs() << "\nWith: ";
6291 Result.getNode()->dump(&DAG);
6293 WorkListRemover DeadNodes(*this);
6295 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
6297 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
6300 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
6304 // Finally, since the node is now dead, remove it from the graph.
6307 // Replace the uses of Ptr with uses of the updated base value.
6308 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
6310 removeFromWorkList(Ptr.getNode());
6311 DAG.DeleteNode(Ptr.getNode());
6316 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
6317 /// add / sub of the base pointer node into a post-indexed load / store.
6318 /// The transformation folded the add / subtract into the new indexed
6319 /// load / store effectively and all of its uses are redirected to the
6320 /// new load / store.
6321 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
6322 if (Level < AfterLegalizeDAG)
6328 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6329 if (LD->isIndexed())
6331 VT = LD->getMemoryVT();
6332 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
6333 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
6335 Ptr = LD->getBasePtr();
6336 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6337 if (ST->isIndexed())
6339 VT = ST->getMemoryVT();
6340 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
6341 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
6343 Ptr = ST->getBasePtr();
6349 if (Ptr.getNode()->hasOneUse())
6352 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
6353 E = Ptr.getNode()->use_end(); I != E; ++I) {
6356 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
6361 ISD::MemIndexedMode AM = ISD::UNINDEXED;
6362 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
6363 // Don't create a indexed load / store with zero offset.
6364 if (isa<ConstantSDNode>(Offset) &&
6365 cast<ConstantSDNode>(Offset)->isNullValue())
6368 // Try turning it into a post-indexed load / store except when
6369 // 1) All uses are load / store ops that use it as base ptr (and
6370 // it may be folded as addressing mmode).
6371 // 2) Op must be independent of N, i.e. Op is neither a predecessor
6372 // nor a successor of N. Otherwise, if Op is folded that would
6375 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
6379 bool TryNext = false;
6380 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
6381 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
6383 if (Use == Ptr.getNode())
6386 // If all the uses are load / store addresses, then don't do the
6388 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
6389 bool RealUse = false;
6390 for (SDNode::use_iterator III = Use->use_begin(),
6391 EEE = Use->use_end(); III != EEE; ++III) {
6392 SDNode *UseUse = *III;
6393 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI))
6408 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
6409 SDValue Result = isLoad
6410 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
6411 BasePtr, Offset, AM)
6412 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
6413 BasePtr, Offset, AM);
6416 DEBUG(dbgs() << "\nReplacing.5 ";
6418 dbgs() << "\nWith: ";
6419 Result.getNode()->dump(&DAG);
6421 WorkListRemover DeadNodes(*this);
6423 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
6425 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
6428 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
6432 // Finally, since the node is now dead, remove it from the graph.
6435 // Replace the uses of Use with uses of the updated base value.
6436 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
6437 Result.getValue(isLoad ? 1 : 0),
6439 removeFromWorkList(Op);
6449 SDValue DAGCombiner::visitLOAD(SDNode *N) {
6450 LoadSDNode *LD = cast<LoadSDNode>(N);
6451 SDValue Chain = LD->getChain();
6452 SDValue Ptr = LD->getBasePtr();
6454 // If load is not volatile and there are no uses of the loaded value (and
6455 // the updated indexed value in case of indexed loads), change uses of the
6456 // chain value into uses of the chain input (i.e. delete the dead load).
6457 if (!LD->isVolatile()) {
6458 if (N->getValueType(1) == MVT::Other) {
6460 if (!N->hasAnyUseOfValue(0)) {
6461 // It's not safe to use the two value CombineTo variant here. e.g.
6462 // v1, chain2 = load chain1, loc
6463 // v2, chain3 = load chain2, loc
6465 // Now we replace use of chain2 with chain1. This makes the second load
6466 // isomorphic to the one we are deleting, and thus makes this load live.
6467 DEBUG(dbgs() << "\nReplacing.6 ";
6469 dbgs() << "\nWith chain: ";
6470 Chain.getNode()->dump(&DAG);
6472 WorkListRemover DeadNodes(*this);
6473 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
6475 if (N->use_empty()) {
6476 removeFromWorkList(N);
6480 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6484 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
6485 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) {
6486 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
6487 DEBUG(dbgs() << "\nReplacing.7 ";
6489 dbgs() << "\nWith: ";
6490 Undef.getNode()->dump(&DAG);
6491 dbgs() << " and 2 other values\n");
6492 WorkListRemover DeadNodes(*this);
6493 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
6494 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
6495 DAG.getUNDEF(N->getValueType(1)),
6497 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
6498 removeFromWorkList(N);
6500 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6505 // If this load is directly stored, replace the load value with the stored
6507 // TODO: Handle store large -> read small portion.
6508 // TODO: Handle TRUNCSTORE/LOADEXT
6509 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
6510 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
6511 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
6512 if (PrevST->getBasePtr() == Ptr &&
6513 PrevST->getValue().getValueType() == N->getValueType(0))
6514 return CombineTo(N, Chain.getOperand(1), Chain);
6518 // Try to infer better alignment information than the load already has.
6519 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
6520 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
6521 if (Align > LD->getAlignment())
6522 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
6523 LD->getValueType(0),
6524 Chain, Ptr, LD->getPointerInfo(),
6526 LD->isVolatile(), LD->isNonTemporal(), Align);
6531 // Walk up chain skipping non-aliasing memory nodes.
6532 SDValue BetterChain = FindBetterChain(N, Chain);
6534 // If there is a better chain.
6535 if (Chain != BetterChain) {
6538 // Replace the chain to void dependency.
6539 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
6540 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
6541 BetterChain, Ptr, LD->getPointerInfo(),
6542 LD->isVolatile(), LD->isNonTemporal(),
6543 LD->isInvariant(), LD->getAlignment());
6545 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
6546 LD->getValueType(0),
6547 BetterChain, Ptr, LD->getPointerInfo(),
6550 LD->isNonTemporal(),
6551 LD->getAlignment());
6554 // Create token factor to keep old chain connected.
6555 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
6556 MVT::Other, Chain, ReplLoad.getValue(1));
6558 // Make sure the new and old chains are cleaned up.
6559 AddToWorkList(Token.getNode());
6561 // Replace uses with load result and token factor. Don't add users
6563 return CombineTo(N, ReplLoad.getValue(0), Token, false);
6567 // Try transforming N to an indexed load.
6568 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
6569 return SDValue(N, 0);
6574 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
6575 /// load is having specific bytes cleared out. If so, return the byte size
6576 /// being masked out and the shift amount.
6577 static std::pair<unsigned, unsigned>
6578 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
6579 std::pair<unsigned, unsigned> Result(0, 0);
6581 // Check for the structure we're looking for.
6582 if (V->getOpcode() != ISD::AND ||
6583 !isa<ConstantSDNode>(V->getOperand(1)) ||
6584 !ISD::isNormalLoad(V->getOperand(0).getNode()))
6587 // Check the chain and pointer.
6588 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
6589 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
6591 // The store should be chained directly to the load or be an operand of a
6593 if (LD == Chain.getNode())
6595 else if (Chain->getOpcode() != ISD::TokenFactor)
6596 return Result; // Fail.
6599 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
6600 if (Chain->getOperand(i).getNode() == LD) {
6604 if (!isOk) return Result;
6607 // This only handles simple types.
6608 if (V.getValueType() != MVT::i16 &&
6609 V.getValueType() != MVT::i32 &&
6610 V.getValueType() != MVT::i64)
6613 // Check the constant mask. Invert it so that the bits being masked out are
6614 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
6615 // follow the sign bit for uniformity.
6616 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
6617 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask);
6618 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
6619 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask);
6620 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
6621 if (NotMaskLZ == 64) return Result; // All zero mask.
6623 // See if we have a continuous run of bits. If so, we have 0*1+0*
6624 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
6627 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
6628 if (V.getValueType() != MVT::i64 && NotMaskLZ)
6629 NotMaskLZ -= 64-V.getValueSizeInBits();
6631 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
6632 switch (MaskedBytes) {
6636 default: return Result; // All one mask, or 5-byte mask.
6639 // Verify that the first bit starts at a multiple of mask so that the access
6640 // is aligned the same as the access width.
6641 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
6643 Result.first = MaskedBytes;
6644 Result.second = NotMaskTZ/8;
6649 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
6650 /// provides a value as specified by MaskInfo. If so, replace the specified
6651 /// store with a narrower store of truncated IVal.
6653 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
6654 SDValue IVal, StoreSDNode *St,
6656 unsigned NumBytes = MaskInfo.first;
6657 unsigned ByteShift = MaskInfo.second;
6658 SelectionDAG &DAG = DC->getDAG();
6660 // Check to see if IVal is all zeros in the part being masked in by the 'or'
6661 // that uses this. If not, this is not a replacement.
6662 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
6663 ByteShift*8, (ByteShift+NumBytes)*8);
6664 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
6666 // Check that it is legal on the target to do this. It is legal if the new
6667 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
6669 MVT VT = MVT::getIntegerVT(NumBytes*8);
6670 if (!DC->isTypeLegal(VT))
6673 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
6674 // shifted by ByteShift and truncated down to NumBytes.
6676 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
6677 DAG.getConstant(ByteShift*8,
6678 DC->getShiftAmountTy(IVal.getValueType())));
6680 // Figure out the offset for the store and the alignment of the access.
6682 unsigned NewAlign = St->getAlignment();
6684 if (DAG.getTargetLoweringInfo().isLittleEndian())
6685 StOffset = ByteShift;
6687 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
6689 SDValue Ptr = St->getBasePtr();
6691 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
6692 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
6693 NewAlign = MinAlign(NewAlign, StOffset);
6696 // Truncate down to the new size.
6697 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
6700 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr,
6701 St->getPointerInfo().getWithOffset(StOffset),
6702 false, false, NewAlign).getNode();
6706 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
6707 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
6708 /// of the loaded bits, try narrowing the load and store if it would end up
6709 /// being a win for performance or code size.
6710 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
6711 StoreSDNode *ST = cast<StoreSDNode>(N);
6712 if (ST->isVolatile())
6715 SDValue Chain = ST->getChain();
6716 SDValue Value = ST->getValue();
6717 SDValue Ptr = ST->getBasePtr();
6718 EVT VT = Value.getValueType();
6720 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
6723 unsigned Opc = Value.getOpcode();
6725 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
6726 // is a byte mask indicating a consecutive number of bytes, check to see if
6727 // Y is known to provide just those bytes. If so, we try to replace the
6728 // load + replace + store sequence with a single (narrower) store, which makes
6730 if (Opc == ISD::OR) {
6731 std::pair<unsigned, unsigned> MaskedLoad;
6732 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
6733 if (MaskedLoad.first)
6734 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
6735 Value.getOperand(1), ST,this))
6736 return SDValue(NewST, 0);
6738 // Or is commutative, so try swapping X and Y.
6739 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
6740 if (MaskedLoad.first)
6741 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
6742 Value.getOperand(0), ST,this))
6743 return SDValue(NewST, 0);
6746 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
6747 Value.getOperand(1).getOpcode() != ISD::Constant)
6750 SDValue N0 = Value.getOperand(0);
6751 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6752 Chain == SDValue(N0.getNode(), 1)) {
6753 LoadSDNode *LD = cast<LoadSDNode>(N0);
6754 if (LD->getBasePtr() != Ptr ||
6755 LD->getPointerInfo().getAddrSpace() !=
6756 ST->getPointerInfo().getAddrSpace())
6759 // Find the type to narrow it the load / op / store to.
6760 SDValue N1 = Value.getOperand(1);
6761 unsigned BitWidth = N1.getValueSizeInBits();
6762 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
6763 if (Opc == ISD::AND)
6764 Imm ^= APInt::getAllOnesValue(BitWidth);
6765 if (Imm == 0 || Imm.isAllOnesValue())
6767 unsigned ShAmt = Imm.countTrailingZeros();
6768 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
6769 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
6770 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
6771 while (NewBW < BitWidth &&
6772 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
6773 TLI.isNarrowingProfitable(VT, NewVT))) {
6774 NewBW = NextPowerOf2(NewBW);
6775 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
6777 if (NewBW >= BitWidth)
6780 // If the lsb changed does not start at the type bitwidth boundary,
6781 // start at the previous one.
6783 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
6784 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
6785 if ((Imm & Mask) == Imm) {
6786 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
6787 if (Opc == ISD::AND)
6788 NewImm ^= APInt::getAllOnesValue(NewBW);
6789 uint64_t PtrOff = ShAmt / 8;
6790 // For big endian targets, we need to adjust the offset to the pointer to
6791 // load the correct bytes.
6792 if (TLI.isBigEndian())
6793 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
6795 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
6796 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
6797 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy))
6800 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
6801 Ptr.getValueType(), Ptr,
6802 DAG.getConstant(PtrOff, Ptr.getValueType()));
6803 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
6804 LD->getChain(), NewPtr,
6805 LD->getPointerInfo().getWithOffset(PtrOff),
6806 LD->isVolatile(), LD->isNonTemporal(),
6807 LD->isInvariant(), NewAlign);
6808 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
6809 DAG.getConstant(NewImm, NewVT));
6810 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
6812 ST->getPointerInfo().getWithOffset(PtrOff),
6813 false, false, NewAlign);
6815 AddToWorkList(NewPtr.getNode());
6816 AddToWorkList(NewLD.getNode());
6817 AddToWorkList(NewVal.getNode());
6818 WorkListRemover DeadNodes(*this);
6819 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1),
6829 /// TransformFPLoadStorePair - For a given floating point load / store pair,
6830 /// if the load value isn't used by any other operations, then consider
6831 /// transforming the pair to integer load / store operations if the target
6832 /// deems the transformation profitable.
6833 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
6834 StoreSDNode *ST = cast<StoreSDNode>(N);
6835 SDValue Chain = ST->getChain();
6836 SDValue Value = ST->getValue();
6837 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
6838 Value.hasOneUse() &&
6839 Chain == SDValue(Value.getNode(), 1)) {
6840 LoadSDNode *LD = cast<LoadSDNode>(Value);
6841 EVT VT = LD->getMemoryVT();
6842 if (!VT.isFloatingPoint() ||
6843 VT != ST->getMemoryVT() ||
6844 LD->isNonTemporal() ||
6845 ST->isNonTemporal() ||
6846 LD->getPointerInfo().getAddrSpace() != 0 ||
6847 ST->getPointerInfo().getAddrSpace() != 0)
6850 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
6851 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
6852 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
6853 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
6854 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
6857 unsigned LDAlign = LD->getAlignment();
6858 unsigned STAlign = ST->getAlignment();
6859 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
6860 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy);
6861 if (LDAlign < ABIAlign || STAlign < ABIAlign)
6864 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(),
6865 LD->getChain(), LD->getBasePtr(),
6866 LD->getPointerInfo(),
6867 false, false, false, LDAlign);
6869 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(),
6870 NewLD, ST->getBasePtr(),
6871 ST->getPointerInfo(),
6872 false, false, STAlign);
6874 AddToWorkList(NewLD.getNode());
6875 AddToWorkList(NewST.getNode());
6876 WorkListRemover DeadNodes(*this);
6877 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1),
6886 SDValue DAGCombiner::visitSTORE(SDNode *N) {
6887 StoreSDNode *ST = cast<StoreSDNode>(N);
6888 SDValue Chain = ST->getChain();
6889 SDValue Value = ST->getValue();
6890 SDValue Ptr = ST->getBasePtr();
6892 // If this is a store of a bit convert, store the input value if the
6893 // resultant store does not need a higher alignment than the original.
6894 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
6895 ST->isUnindexed()) {
6896 unsigned OrigAlign = ST->getAlignment();
6897 EVT SVT = Value.getOperand(0).getValueType();
6898 unsigned Align = TLI.getTargetData()->
6899 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
6900 if (Align <= OrigAlign &&
6901 ((!LegalOperations && !ST->isVolatile()) ||
6902 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
6903 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
6904 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6905 ST->isNonTemporal(), OrigAlign);
6908 // Turn 'store undef, Ptr' -> nothing.
6909 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
6912 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
6913 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
6914 // NOTE: If the original store is volatile, this transform must not increase
6915 // the number of stores. For example, on x86-32 an f64 can be stored in one
6916 // processor operation but an i64 (which is not legal) requires two. So the
6917 // transform should not be done in this case.
6918 if (Value.getOpcode() != ISD::TargetConstantFP) {
6920 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
6921 default: llvm_unreachable("Unknown FP type");
6922 case MVT::f80: // We don't do this for these yet.
6927 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
6928 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
6929 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
6930 bitcastToAPInt().getZExtValue(), MVT::i32);
6931 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
6932 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6933 ST->isNonTemporal(), ST->getAlignment());
6937 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
6938 !ST->isVolatile()) ||
6939 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
6940 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
6941 getZExtValue(), MVT::i64);
6942 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
6943 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6944 ST->isNonTemporal(), ST->getAlignment());
6947 if (!ST->isVolatile() &&
6948 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
6949 // Many FP stores are not made apparent until after legalize, e.g. for
6950 // argument passing. Since this is so common, custom legalize the
6951 // 64-bit integer store into two 32-bit stores.
6952 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
6953 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
6954 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
6955 if (TLI.isBigEndian()) std::swap(Lo, Hi);
6957 unsigned Alignment = ST->getAlignment();
6958 bool isVolatile = ST->isVolatile();
6959 bool isNonTemporal = ST->isNonTemporal();
6961 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
6962 Ptr, ST->getPointerInfo(),
6963 isVolatile, isNonTemporal,
6964 ST->getAlignment());
6965 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
6966 DAG.getConstant(4, Ptr.getValueType()));
6967 Alignment = MinAlign(Alignment, 4U);
6968 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
6969 Ptr, ST->getPointerInfo().getWithOffset(4),
6970 isVolatile, isNonTemporal,
6972 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
6981 // Try to infer better alignment information than the store already has.
6982 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
6983 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
6984 if (Align > ST->getAlignment())
6985 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
6986 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6987 ST->isVolatile(), ST->isNonTemporal(), Align);
6991 // Try transforming a pair floating point load / store ops to integer
6992 // load / store ops.
6993 SDValue NewST = TransformFPLoadStorePair(N);
6994 if (NewST.getNode())
6998 // Walk up chain skipping non-aliasing memory nodes.
6999 SDValue BetterChain = FindBetterChain(N, Chain);
7001 // If there is a better chain.
7002 if (Chain != BetterChain) {
7005 // Replace the chain to avoid dependency.
7006 if (ST->isTruncatingStore()) {
7007 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
7008 ST->getPointerInfo(),
7009 ST->getMemoryVT(), ST->isVolatile(),
7010 ST->isNonTemporal(), ST->getAlignment());
7012 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
7013 ST->getPointerInfo(),
7014 ST->isVolatile(), ST->isNonTemporal(),
7015 ST->getAlignment());
7018 // Create token to keep both nodes around.
7019 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
7020 MVT::Other, Chain, ReplStore);
7022 // Make sure the new and old chains are cleaned up.
7023 AddToWorkList(Token.getNode());
7025 // Don't add users to work list.
7026 return CombineTo(N, Token, false);
7030 // Try transforming N to an indexed store.
7031 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
7032 return SDValue(N, 0);
7034 // FIXME: is there such a thing as a truncating indexed store?
7035 if (ST->isTruncatingStore() && ST->isUnindexed() &&
7036 Value.getValueType().isInteger()) {
7037 // See if we can simplify the input to this truncstore with knowledge that
7038 // only the low bits are being used. For example:
7039 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
7041 GetDemandedBits(Value,
7042 APInt::getLowBitsSet(
7043 Value.getValueType().getScalarType().getSizeInBits(),
7044 ST->getMemoryVT().getScalarType().getSizeInBits()));
7045 AddToWorkList(Value.getNode());
7046 if (Shorter.getNode())
7047 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
7048 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
7049 ST->isVolatile(), ST->isNonTemporal(),
7050 ST->getAlignment());
7052 // Otherwise, see if we can simplify the operation with
7053 // SimplifyDemandedBits, which only works if the value has a single use.
7054 if (SimplifyDemandedBits(Value,
7055 APInt::getLowBitsSet(
7056 Value.getValueType().getScalarType().getSizeInBits(),
7057 ST->getMemoryVT().getScalarType().getSizeInBits())))
7058 return SDValue(N, 0);
7061 // If this is a load followed by a store to the same location, then the store
7063 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
7064 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
7065 ST->isUnindexed() && !ST->isVolatile() &&
7066 // There can't be any side effects between the load and store, such as
7068 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
7069 // The store is dead, remove it.
7074 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
7075 // truncating store. We can do this even if this is already a truncstore.
7076 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
7077 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
7078 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
7079 ST->getMemoryVT())) {
7080 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
7081 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
7082 ST->isVolatile(), ST->isNonTemporal(),
7083 ST->getAlignment());
7086 return ReduceLoadOpStoreWidth(N);
7089 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
7090 SDValue InVec = N->getOperand(0);
7091 SDValue InVal = N->getOperand(1);
7092 SDValue EltNo = N->getOperand(2);
7093 DebugLoc dl = N->getDebugLoc();
7095 // If the inserted element is an UNDEF, just use the input vector.
7096 if (InVal.getOpcode() == ISD::UNDEF)
7099 EVT VT = InVec.getValueType();
7101 // If we can't generate a legal BUILD_VECTOR, exit
7102 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
7105 // Check that we know which element is being inserted
7106 if (!isa<ConstantSDNode>(EltNo))
7108 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
7110 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
7111 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
7113 SmallVector<SDValue, 8> Ops;
7114 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
7115 Ops.append(InVec.getNode()->op_begin(),
7116 InVec.getNode()->op_end());
7117 } else if (InVec.getOpcode() == ISD::UNDEF) {
7118 unsigned NElts = VT.getVectorNumElements();
7119 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
7124 // Insert the element
7125 if (Elt < Ops.size()) {
7126 // All the operands of BUILD_VECTOR must have the same type;
7127 // we enforce that here.
7128 EVT OpVT = Ops[0].getValueType();
7129 if (InVal.getValueType() != OpVT)
7130 InVal = OpVT.bitsGT(InVal.getValueType()) ?
7131 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
7132 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
7136 // Return the new vector
7137 return DAG.getNode(ISD::BUILD_VECTOR, dl,
7138 VT, &Ops[0], Ops.size());
7141 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
7142 // (vextract (scalar_to_vector val, 0) -> val
7143 SDValue InVec = N->getOperand(0);
7144 EVT VT = InVec.getValueType();
7145 EVT NVT = N->getValueType(0);
7147 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
7148 // Check if the result type doesn't match the inserted element type. A
7149 // SCALAR_TO_VECTOR may truncate the inserted element and the
7150 // EXTRACT_VECTOR_ELT may widen the extracted vector.
7151 SDValue InOp = InVec.getOperand(0);
7152 if (InOp.getValueType() != NVT) {
7153 assert(InOp.getValueType().isInteger() && NVT.isInteger());
7154 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
7159 SDValue EltNo = N->getOperand(1);
7160 bool ConstEltNo = isa<ConstantSDNode>(EltNo);
7162 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
7163 // We only perform this optimization before the op legalization phase because
7164 // we may introduce new vector instructions which are not backed by TD patterns.
7165 // For example on AVX, extracting elements from a wide vector without using
7166 // extract_subvector.
7167 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
7168 && ConstEltNo && !LegalOperations) {
7169 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
7170 int NumElem = VT.getVectorNumElements();
7171 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
7172 // Find the new index to extract from.
7173 int OrigElt = SVOp->getMaskElt(Elt);
7175 // Extracting an undef index is undef.
7177 return DAG.getUNDEF(NVT);
7179 // Select the right vector half to extract from.
7180 if (OrigElt < NumElem) {
7181 InVec = InVec->getOperand(0);
7183 InVec = InVec->getOperand(1);
7187 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT,
7188 InVec, DAG.getConstant(OrigElt, MVT::i32));
7191 // Perform only after legalization to ensure build_vector / vector_shuffle
7192 // optimizations have already been done.
7193 if (!LegalOperations) return SDValue();
7195 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
7196 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
7197 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
7200 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
7201 bool NewLoad = false;
7202 bool BCNumEltsChanged = false;
7203 EVT ExtVT = VT.getVectorElementType();
7206 if (InVec.getOpcode() == ISD::BITCAST) {
7207 // Don't duplicate a load with other uses.
7208 if (!InVec.hasOneUse())
7211 EVT BCVT = InVec.getOperand(0).getValueType();
7212 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
7214 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
7215 BCNumEltsChanged = true;
7216 InVec = InVec.getOperand(0);
7217 ExtVT = BCVT.getVectorElementType();
7221 LoadSDNode *LN0 = NULL;
7222 const ShuffleVectorSDNode *SVN = NULL;
7223 if (ISD::isNormalLoad(InVec.getNode())) {
7224 LN0 = cast<LoadSDNode>(InVec);
7225 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7226 InVec.getOperand(0).getValueType() == ExtVT &&
7227 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
7228 // Don't duplicate a load with other uses.
7229 if (!InVec.hasOneUse())
7232 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
7233 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
7234 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
7236 // (load $addr+1*size)
7238 // Don't duplicate a load with other uses.
7239 if (!InVec.hasOneUse())
7242 // If the bit convert changed the number of elements, it is unsafe
7243 // to examine the mask.
7244 if (BCNumEltsChanged)
7247 // Select the input vector, guarding against out of range extract vector.
7248 unsigned NumElems = VT.getVectorNumElements();
7249 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
7250 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
7252 if (InVec.getOpcode() == ISD::BITCAST) {
7253 // Don't duplicate a load with other uses.
7254 if (!InVec.hasOneUse())
7257 InVec = InVec.getOperand(0);
7259 if (ISD::isNormalLoad(InVec.getNode())) {
7260 LN0 = cast<LoadSDNode>(InVec);
7261 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
7265 // Make sure we found a non-volatile load and the extractelement is
7267 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
7270 // If Idx was -1 above, Elt is going to be -1, so just return undef.
7272 return DAG.getUNDEF(LVT);
7274 unsigned Align = LN0->getAlignment();
7276 // Check the resultant load doesn't need a higher alignment than the
7280 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
7282 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
7288 SDValue NewPtr = LN0->getBasePtr();
7289 unsigned PtrOff = 0;
7292 PtrOff = LVT.getSizeInBits() * Elt / 8;
7293 EVT PtrType = NewPtr.getValueType();
7294 if (TLI.isBigEndian())
7295 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
7296 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
7297 DAG.getConstant(PtrOff, PtrType));
7300 // The replacement we need to do here is a little tricky: we need to
7301 // replace an extractelement of a load with a load.
7302 // Use ReplaceAllUsesOfValuesWith to do the replacement.
7303 // Note that this replacement assumes that the extractvalue is the only
7304 // use of the load; that's okay because we don't want to perform this
7305 // transformation in other cases anyway.
7306 SDValue Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
7307 LN0->getPointerInfo().getWithOffset(PtrOff),
7308 LN0->isVolatile(), LN0->isNonTemporal(),
7309 LN0->isInvariant(), Align);
7310 WorkListRemover DeadNodes(*this);
7311 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) };
7312 SDValue To[] = { Load.getValue(0), Load.getValue(1) };
7313 DAG.ReplaceAllUsesOfValuesWith(From, To, 2, &DeadNodes);
7314 // Since we're explcitly calling ReplaceAllUses, add the new node to the
7315 // worklist explicitly as well.
7316 AddToWorkList(Load.getNode());
7317 // Make sure to revisit this node to clean it up; it will usually be dead.
7319 return SDValue(N, 0);
7325 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
7326 unsigned NumInScalars = N->getNumOperands();
7327 DebugLoc dl = N->getDebugLoc();
7328 EVT VT = N->getValueType(0);
7329 // Check to see if this is a BUILD_VECTOR of a bunch of values
7330 // which come from any_extend or zero_extend nodes. If so, we can create
7331 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR
7332 // optimizations. We do not handle sign-extend because we can't fill the sign
7334 EVT SourceType = MVT::Other;
7335 bool AllAnyExt = true;
7336 bool AllUndef = true;
7337 for (unsigned i = 0; i != NumInScalars; ++i) {
7338 SDValue In = N->getOperand(i);
7339 // Ignore undef inputs.
7340 if (In.getOpcode() == ISD::UNDEF) continue;
7343 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
7344 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
7346 // Abort if the element is not an extension.
7347 if (!ZeroExt && !AnyExt) {
7348 SourceType = MVT::Other;
7352 // The input is a ZeroExt or AnyExt. Check the original type.
7353 EVT InTy = In.getOperand(0).getValueType();
7355 // Check that all of the widened source types are the same.
7356 if (SourceType == MVT::Other)
7359 else if (InTy != SourceType) {
7360 // Multiple income types. Abort.
7361 SourceType = MVT::Other;
7365 // Check if all of the extends are ANY_EXTENDs.
7366 AllAnyExt &= AnyExt;
7370 return DAG.getUNDEF(VT);
7372 // In order to have valid types, all of the inputs must be extended from the
7373 // same source type and all of the inputs must be any or zero extend.
7374 // Scalar sizes must be a power of two.
7375 EVT OutScalarTy = N->getValueType(0).getScalarType();
7376 bool ValidTypes = SourceType != MVT::Other &&
7377 isPowerOf2_32(OutScalarTy.getSizeInBits()) &&
7378 isPowerOf2_32(SourceType.getSizeInBits());
7380 // We perform this optimization post type-legalization because
7381 // the type-legalizer often scalarizes integer-promoted vectors.
7382 // Performing this optimization before may create bit-casts which
7383 // will be type-legalized to complex code sequences.
7384 // We perform this optimization only before the operation legalizer because we
7385 // may introduce illegal operations.
7386 if ((Level == AfterLegalizeVectorOps || Level == AfterLegalizeTypes) &&
7388 bool isLE = TLI.isLittleEndian();
7389 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits();
7390 assert(ElemRatio > 1 && "Invalid element size ratio");
7391 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType):
7392 DAG.getConstant(0, SourceType);
7394 unsigned NewBVElems = ElemRatio * N->getValueType(0).getVectorNumElements();
7395 SmallVector<SDValue, 8> Ops(NewBVElems, Filler);
7397 // Populate the new build_vector
7398 for (unsigned i=0; i < N->getNumOperands(); ++i) {
7399 SDValue Cast = N->getOperand(i);
7400 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
7401 Cast.getOpcode() == ISD::ZERO_EXTEND ||
7402 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
7404 if (Cast.getOpcode() == ISD::UNDEF)
7405 In = DAG.getUNDEF(SourceType);
7407 In = Cast->getOperand(0);
7408 unsigned Index = isLE ? (i * ElemRatio) :
7409 (i * ElemRatio + (ElemRatio - 1));
7411 assert(Index < Ops.size() && "Invalid index");
7415 // The type of the new BUILD_VECTOR node.
7416 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems);
7417 assert(VecVT.getSizeInBits() == N->getValueType(0).getSizeInBits() &&
7418 "Invalid vector size");
7419 // Check if the new vector type is legal.
7420 if (!isTypeLegal(VecVT)) return SDValue();
7422 // Make the new BUILD_VECTOR.
7423 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
7424 VecVT, &Ops[0], Ops.size());
7426 // Bitcast to the desired type.
7427 return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV);
7430 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
7431 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
7432 // at most two distinct vectors, turn this into a shuffle node.
7433 SDValue VecIn1, VecIn2;
7434 for (unsigned i = 0; i != NumInScalars; ++i) {
7435 // Ignore undef inputs.
7436 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
7438 // If this input is something other than a EXTRACT_VECTOR_ELT with a
7439 // constant index, bail out.
7440 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
7441 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
7442 VecIn1 = VecIn2 = SDValue(0, 0);
7446 // We allow up to two distinct input vectors.
7447 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
7448 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
7451 if (VecIn1.getNode() == 0) {
7452 VecIn1 = ExtractedFromVec;
7453 } else if (VecIn2.getNode() == 0) {
7454 VecIn2 = ExtractedFromVec;
7457 VecIn1 = VecIn2 = SDValue(0, 0);
7462 // If everything is good, we can make a shuffle operation.
7463 if (VecIn1.getNode()) {
7464 SmallVector<int, 8> Mask;
7465 for (unsigned i = 0; i != NumInScalars; ++i) {
7466 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
7471 // If extracting from the first vector, just use the index directly.
7472 SDValue Extract = N->getOperand(i);
7473 SDValue ExtVal = Extract.getOperand(1);
7474 if (Extract.getOperand(0) == VecIn1) {
7475 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
7476 if (ExtIndex > VT.getVectorNumElements())
7479 Mask.push_back(ExtIndex);
7483 // Otherwise, use InIdx + VecSize
7484 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
7485 Mask.push_back(Idx+NumInScalars);
7488 // We can't generate a shuffle node with mismatched input and output types.
7489 // Attempt to transform a single input vector to the correct type.
7490 if ((VT != VecIn1.getValueType())) {
7491 // We don't support shuffeling between TWO values of different types.
7492 if (VecIn2.getNode() != 0)
7495 // We only support widening of vectors which are half the size of the
7496 // output registers. For example XMM->YMM widening on X86 with AVX.
7497 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits())
7500 // Widen the input vector by adding undef values.
7501 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
7502 VecIn1, DAG.getUNDEF(VecIn1.getValueType()));
7505 // If VecIn2 is unused then change it to undef.
7506 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
7508 // Check that we were able to transform all incoming values to the same type.
7509 if (VecIn2.getValueType() != VecIn1.getValueType() ||
7510 VecIn1.getValueType() != VT)
7513 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes.
7514 if (!isTypeLegal(VT))
7517 // Return the new VECTOR_SHUFFLE node.
7521 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
7527 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
7528 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
7529 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
7530 // inputs come from at most two distinct vectors, turn this into a shuffle
7533 // If we only have one input vector, we don't need to do any concatenation.
7534 if (N->getNumOperands() == 1)
7535 return N->getOperand(0);
7540 SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
7541 EVT NVT = N->getValueType(0);
7542 SDValue V = N->getOperand(0);
7544 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
7545 // Handle only simple case where vector being inserted and vector
7546 // being extracted are of same type, and are half size of larger vectors.
7547 EVT BigVT = V->getOperand(0).getValueType();
7548 EVT SmallVT = V->getOperand(1).getValueType();
7549 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits())
7552 // Only handle cases where both indexes are constants with the same type.
7553 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
7554 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(V->getOperand(2));
7556 if (InsIdx && ExtIdx &&
7557 InsIdx->getValueType(0).getSizeInBits() <= 64 &&
7558 ExtIdx->getValueType(0).getSizeInBits() <= 64) {
7560 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx)
7562 // indices are equal => V1
7563 // otherwise => (extract_subvec V1, ExtIdx)
7564 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue())
7565 return V->getOperand(1);
7566 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT,
7567 V->getOperand(0), N->getOperand(1));
7574 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
7575 EVT VT = N->getValueType(0);
7576 unsigned NumElts = VT.getVectorNumElements();
7578 SDValue N0 = N->getOperand(0);
7579 SDValue N1 = N->getOperand(1);
7581 assert(N0.getValueType().getVectorNumElements() == NumElts &&
7582 "Vector shuffle must be normalized in DAG");
7584 // Canonicalize shuffle undef, undef -> undef
7585 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
7586 return DAG.getUNDEF(VT);
7588 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
7590 // Canonicalize shuffle v, v -> v, undef
7592 SmallVector<int, 8> NewMask;
7593 for (unsigned i = 0; i != NumElts; ++i) {
7594 int Idx = SVN->getMaskElt(i);
7595 if (Idx >= (int)NumElts) Idx -= NumElts;
7596 NewMask.push_back(Idx);
7598 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT),
7602 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
7603 if (N0.getOpcode() == ISD::UNDEF) {
7604 SmallVector<int, 8> NewMask;
7605 for (unsigned i = 0; i != NumElts; ++i) {
7606 int Idx = SVN->getMaskElt(i);
7608 NewMask.push_back(Idx);
7609 else if (Idx < (int)NumElts)
7610 NewMask.push_back(Idx + NumElts);
7612 NewMask.push_back(Idx - NumElts);
7614 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT),
7618 // Remove references to rhs if it is undef
7619 if (N1.getOpcode() == ISD::UNDEF) {
7620 bool Changed = false;
7621 SmallVector<int, 8> NewMask;
7622 for (unsigned i = 0; i != NumElts; ++i) {
7623 int Idx = SVN->getMaskElt(i);
7624 if (Idx >= (int)NumElts) {
7628 NewMask.push_back(Idx);
7631 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]);
7634 // If it is a splat, check if the argument vector is another splat or a
7635 // build_vector with all scalar elements the same.
7636 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
7637 SDNode *V = N0.getNode();
7639 // If this is a bit convert that changes the element type of the vector but
7640 // not the number of vector elements, look through it. Be careful not to
7641 // look though conversions that change things like v4f32 to v2f64.
7642 if (V->getOpcode() == ISD::BITCAST) {
7643 SDValue ConvInput = V->getOperand(0);
7644 if (ConvInput.getValueType().isVector() &&
7645 ConvInput.getValueType().getVectorNumElements() == NumElts)
7646 V = ConvInput.getNode();
7649 if (V->getOpcode() == ISD::BUILD_VECTOR) {
7650 assert(V->getNumOperands() == NumElts &&
7651 "BUILD_VECTOR has wrong number of operands");
7653 bool AllSame = true;
7654 for (unsigned i = 0; i != NumElts; ++i) {
7655 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
7656 Base = V->getOperand(i);
7660 // Splat of <u, u, u, u>, return <u, u, u, u>
7661 if (!Base.getNode())
7663 for (unsigned i = 0; i != NumElts; ++i) {
7664 if (V->getOperand(i) != Base) {
7669 // Splat of <x, x, x, x>, return <x, x, x, x>
7677 SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) {
7678 if (!TLI.getShouldFoldAtomicFences())
7681 SDValue atomic = N->getOperand(0);
7682 switch (atomic.getOpcode()) {
7683 case ISD::ATOMIC_CMP_SWAP:
7684 case ISD::ATOMIC_SWAP:
7685 case ISD::ATOMIC_LOAD_ADD:
7686 case ISD::ATOMIC_LOAD_SUB:
7687 case ISD::ATOMIC_LOAD_AND:
7688 case ISD::ATOMIC_LOAD_OR:
7689 case ISD::ATOMIC_LOAD_XOR:
7690 case ISD::ATOMIC_LOAD_NAND:
7691 case ISD::ATOMIC_LOAD_MIN:
7692 case ISD::ATOMIC_LOAD_MAX:
7693 case ISD::ATOMIC_LOAD_UMIN:
7694 case ISD::ATOMIC_LOAD_UMAX:
7700 SDValue fence = atomic.getOperand(0);
7701 if (fence.getOpcode() != ISD::MEMBARRIER)
7704 switch (atomic.getOpcode()) {
7705 case ISD::ATOMIC_CMP_SWAP:
7706 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
7707 fence.getOperand(0),
7708 atomic.getOperand(1), atomic.getOperand(2),
7709 atomic.getOperand(3)), atomic.getResNo());
7710 case ISD::ATOMIC_SWAP:
7711 case ISD::ATOMIC_LOAD_ADD:
7712 case ISD::ATOMIC_LOAD_SUB:
7713 case ISD::ATOMIC_LOAD_AND:
7714 case ISD::ATOMIC_LOAD_OR:
7715 case ISD::ATOMIC_LOAD_XOR:
7716 case ISD::ATOMIC_LOAD_NAND:
7717 case ISD::ATOMIC_LOAD_MIN:
7718 case ISD::ATOMIC_LOAD_MAX:
7719 case ISD::ATOMIC_LOAD_UMIN:
7720 case ISD::ATOMIC_LOAD_UMAX:
7721 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
7722 fence.getOperand(0),
7723 atomic.getOperand(1), atomic.getOperand(2)),
7730 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
7731 /// an AND to a vector_shuffle with the destination vector and a zero vector.
7732 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
7733 /// vector_shuffle V, Zero, <0, 4, 2, 4>
7734 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
7735 EVT VT = N->getValueType(0);
7736 DebugLoc dl = N->getDebugLoc();
7737 SDValue LHS = N->getOperand(0);
7738 SDValue RHS = N->getOperand(1);
7739 if (N->getOpcode() == ISD::AND) {
7740 if (RHS.getOpcode() == ISD::BITCAST)
7741 RHS = RHS.getOperand(0);
7742 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
7743 SmallVector<int, 8> Indices;
7744 unsigned NumElts = RHS.getNumOperands();
7745 for (unsigned i = 0; i != NumElts; ++i) {
7746 SDValue Elt = RHS.getOperand(i);
7747 if (!isa<ConstantSDNode>(Elt))
7749 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
7750 Indices.push_back(i);
7751 else if (cast<ConstantSDNode>(Elt)->isNullValue())
7752 Indices.push_back(NumElts);
7757 // Let's see if the target supports this vector_shuffle.
7758 EVT RVT = RHS.getValueType();
7759 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
7762 // Return the new VECTOR_SHUFFLE node.
7763 EVT EltVT = RVT.getVectorElementType();
7764 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
7765 DAG.getConstant(0, EltVT));
7766 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
7767 RVT, &ZeroOps[0], ZeroOps.size());
7768 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
7769 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
7770 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
7777 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
7778 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
7779 // After legalize, the target may be depending on adds and other
7780 // binary ops to provide legal ways to construct constants or other
7781 // things. Simplifying them may result in a loss of legality.
7782 if (LegalOperations) return SDValue();
7784 assert(N->getValueType(0).isVector() &&
7785 "SimplifyVBinOp only works on vectors!");
7787 SDValue LHS = N->getOperand(0);
7788 SDValue RHS = N->getOperand(1);
7789 SDValue Shuffle = XformToShuffleWithZero(N);
7790 if (Shuffle.getNode()) return Shuffle;
7792 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
7794 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
7795 RHS.getOpcode() == ISD::BUILD_VECTOR) {
7796 SmallVector<SDValue, 8> Ops;
7797 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
7798 SDValue LHSOp = LHS.getOperand(i);
7799 SDValue RHSOp = RHS.getOperand(i);
7800 // If these two elements can't be folded, bail out.
7801 if ((LHSOp.getOpcode() != ISD::UNDEF &&
7802 LHSOp.getOpcode() != ISD::Constant &&
7803 LHSOp.getOpcode() != ISD::ConstantFP) ||
7804 (RHSOp.getOpcode() != ISD::UNDEF &&
7805 RHSOp.getOpcode() != ISD::Constant &&
7806 RHSOp.getOpcode() != ISD::ConstantFP))
7809 // Can't fold divide by zero.
7810 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
7811 N->getOpcode() == ISD::FDIV) {
7812 if ((RHSOp.getOpcode() == ISD::Constant &&
7813 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
7814 (RHSOp.getOpcode() == ISD::ConstantFP &&
7815 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
7819 EVT VT = LHSOp.getValueType();
7820 EVT RVT = RHSOp.getValueType();
7822 // Integer BUILD_VECTOR operands may have types larger than the element
7823 // size (e.g., when the element type is not legal). Prior to type
7824 // legalization, the types may not match between the two BUILD_VECTORS.
7825 // Truncate one of the operands to make them match.
7826 if (RVT.getSizeInBits() > VT.getSizeInBits()) {
7827 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp);
7829 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp);
7833 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT,
7835 if (FoldOp.getOpcode() != ISD::UNDEF &&
7836 FoldOp.getOpcode() != ISD::Constant &&
7837 FoldOp.getOpcode() != ISD::ConstantFP)
7839 Ops.push_back(FoldOp);
7840 AddToWorkList(FoldOp.getNode());
7843 if (Ops.size() == LHS.getNumOperands())
7844 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
7845 LHS.getValueType(), &Ops[0], Ops.size());
7851 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
7852 SDValue N1, SDValue N2){
7853 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
7855 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
7856 cast<CondCodeSDNode>(N0.getOperand(2))->get());
7858 // If we got a simplified select_cc node back from SimplifySelectCC, then
7859 // break it down into a new SETCC node, and a new SELECT node, and then return
7860 // the SELECT node, since we were called with a SELECT node.
7861 if (SCC.getNode()) {
7862 // Check to see if we got a select_cc back (to turn into setcc/select).
7863 // Otherwise, just return whatever node we got back, like fabs.
7864 if (SCC.getOpcode() == ISD::SELECT_CC) {
7865 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
7867 SCC.getOperand(0), SCC.getOperand(1),
7869 AddToWorkList(SETCC.getNode());
7870 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
7871 SCC.getOperand(2), SCC.getOperand(3), SETCC);
7879 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
7880 /// are the two values being selected between, see if we can simplify the
7881 /// select. Callers of this should assume that TheSelect is deleted if this
7882 /// returns true. As such, they should return the appropriate thing (e.g. the
7883 /// node) back to the top-level of the DAG combiner loop to avoid it being
7885 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
7888 // Cannot simplify select with vector condition
7889 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
7891 // If this is a select from two identical things, try to pull the operation
7892 // through the select.
7893 if (LHS.getOpcode() != RHS.getOpcode() ||
7894 !LHS.hasOneUse() || !RHS.hasOneUse())
7897 // If this is a load and the token chain is identical, replace the select
7898 // of two loads with a load through a select of the address to load from.
7899 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
7900 // constants have been dropped into the constant pool.
7901 if (LHS.getOpcode() == ISD::LOAD) {
7902 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
7903 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
7905 // Token chains must be identical.
7906 if (LHS.getOperand(0) != RHS.getOperand(0) ||
7907 // Do not let this transformation reduce the number of volatile loads.
7908 LLD->isVolatile() || RLD->isVolatile() ||
7909 // If this is an EXTLOAD, the VT's must match.
7910 LLD->getMemoryVT() != RLD->getMemoryVT() ||
7911 // If this is an EXTLOAD, the kind of extension must match.
7912 (LLD->getExtensionType() != RLD->getExtensionType() &&
7913 // The only exception is if one of the extensions is anyext.
7914 LLD->getExtensionType() != ISD::EXTLOAD &&
7915 RLD->getExtensionType() != ISD::EXTLOAD) ||
7916 // FIXME: this discards src value information. This is
7917 // over-conservative. It would be beneficial to be able to remember
7918 // both potential memory locations. Since we are discarding
7919 // src value info, don't do the transformation if the memory
7920 // locations are not in the default address space.
7921 LLD->getPointerInfo().getAddrSpace() != 0 ||
7922 RLD->getPointerInfo().getAddrSpace() != 0)
7925 // Check that the select condition doesn't reach either load. If so,
7926 // folding this will induce a cycle into the DAG. If not, this is safe to
7927 // xform, so create a select of the addresses.
7929 if (TheSelect->getOpcode() == ISD::SELECT) {
7930 SDNode *CondNode = TheSelect->getOperand(0).getNode();
7931 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
7932 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
7934 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
7935 LLD->getBasePtr().getValueType(),
7936 TheSelect->getOperand(0), LLD->getBasePtr(),
7938 } else { // Otherwise SELECT_CC
7939 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
7940 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
7942 if ((LLD->hasAnyUseOfValue(1) &&
7943 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
7944 (LLD->hasAnyUseOfValue(1) &&
7945 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))))
7948 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
7949 LLD->getBasePtr().getValueType(),
7950 TheSelect->getOperand(0),
7951 TheSelect->getOperand(1),
7952 LLD->getBasePtr(), RLD->getBasePtr(),
7953 TheSelect->getOperand(4));
7957 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
7958 Load = DAG.getLoad(TheSelect->getValueType(0),
7959 TheSelect->getDebugLoc(),
7960 // FIXME: Discards pointer info.
7961 LLD->getChain(), Addr, MachinePointerInfo(),
7962 LLD->isVolatile(), LLD->isNonTemporal(),
7963 LLD->isInvariant(), LLD->getAlignment());
7965 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
7966 RLD->getExtensionType() : LLD->getExtensionType(),
7967 TheSelect->getDebugLoc(),
7968 TheSelect->getValueType(0),
7969 // FIXME: Discards pointer info.
7970 LLD->getChain(), Addr, MachinePointerInfo(),
7971 LLD->getMemoryVT(), LLD->isVolatile(),
7972 LLD->isNonTemporal(), LLD->getAlignment());
7975 // Users of the select now use the result of the load.
7976 CombineTo(TheSelect, Load);
7978 // Users of the old loads now use the new load's chain. We know the
7979 // old-load value is dead now.
7980 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
7981 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
7988 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
7989 /// where 'cond' is the comparison specified by CC.
7990 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
7991 SDValue N2, SDValue N3,
7992 ISD::CondCode CC, bool NotExtCompare) {
7993 // (x ? y : y) -> y.
7994 if (N2 == N3) return N2;
7996 EVT VT = N2.getValueType();
7997 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
7998 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
7999 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
8001 // Determine if the condition we're dealing with is constant
8002 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
8003 N0, N1, CC, DL, false);
8004 if (SCC.getNode()) AddToWorkList(SCC.getNode());
8005 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
8007 // fold select_cc true, x, y -> x
8008 if (SCCC && !SCCC->isNullValue())
8010 // fold select_cc false, x, y -> y
8011 if (SCCC && SCCC->isNullValue())
8014 // Check to see if we can simplify the select into an fabs node
8015 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
8016 // Allow either -0.0 or 0.0
8017 if (CFP->getValueAPF().isZero()) {
8018 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
8019 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
8020 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
8021 N2 == N3.getOperand(0))
8022 return DAG.getNode(ISD::FABS, DL, VT, N0);
8024 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
8025 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
8026 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
8027 N2.getOperand(0) == N3)
8028 return DAG.getNode(ISD::FABS, DL, VT, N3);
8032 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
8033 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
8034 // in it. This is a win when the constant is not otherwise available because
8035 // it replaces two constant pool loads with one. We only do this if the FP
8036 // type is known to be legal, because if it isn't, then we are before legalize
8037 // types an we want the other legalization to happen first (e.g. to avoid
8038 // messing with soft float) and if the ConstantFP is not legal, because if
8039 // it is legal, we may not need to store the FP constant in a constant pool.
8040 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
8041 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
8042 if (TLI.isTypeLegal(N2.getValueType()) &&
8043 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
8044 TargetLowering::Legal) &&
8045 // If both constants have multiple uses, then we won't need to do an
8046 // extra load, they are likely around in registers for other users.
8047 (TV->hasOneUse() || FV->hasOneUse())) {
8048 Constant *Elts[] = {
8049 const_cast<ConstantFP*>(FV->getConstantFPValue()),
8050 const_cast<ConstantFP*>(TV->getConstantFPValue())
8052 Type *FPTy = Elts[0]->getType();
8053 const TargetData &TD = *TLI.getTargetData();
8055 // Create a ConstantArray of the two constants.
8056 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
8057 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
8058 TD.getPrefTypeAlignment(FPTy));
8059 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
8061 // Get the offsets to the 0 and 1 element of the array so that we can
8062 // select between them.
8063 SDValue Zero = DAG.getIntPtrConstant(0);
8064 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
8065 SDValue One = DAG.getIntPtrConstant(EltSize);
8067 SDValue Cond = DAG.getSetCC(DL,
8068 TLI.getSetCCResultType(N0.getValueType()),
8070 AddToWorkList(Cond.getNode());
8071 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
8073 AddToWorkList(CstOffset.getNode());
8074 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
8076 AddToWorkList(CPIdx.getNode());
8077 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
8078 MachinePointerInfo::getConstantPool(), false,
8079 false, false, Alignment);
8084 // Check to see if we can perform the "gzip trick", transforming
8085 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
8086 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
8087 (N1C->isNullValue() || // (a < 0) ? b : 0
8088 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
8089 EVT XType = N0.getValueType();
8090 EVT AType = N2.getValueType();
8091 if (XType.bitsGE(AType)) {
8092 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
8093 // single-bit constant.
8094 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
8095 unsigned ShCtV = N2C->getAPIntValue().logBase2();
8096 ShCtV = XType.getSizeInBits()-ShCtV-1;
8097 SDValue ShCt = DAG.getConstant(ShCtV,
8098 getShiftAmountTy(N0.getValueType()));
8099 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
8101 AddToWorkList(Shift.getNode());
8103 if (XType.bitsGT(AType)) {
8104 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
8105 AddToWorkList(Shift.getNode());
8108 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
8111 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
8113 DAG.getConstant(XType.getSizeInBits()-1,
8114 getShiftAmountTy(N0.getValueType())));
8115 AddToWorkList(Shift.getNode());
8117 if (XType.bitsGT(AType)) {
8118 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
8119 AddToWorkList(Shift.getNode());
8122 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
8126 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
8127 // where y is has a single bit set.
8128 // A plaintext description would be, we can turn the SELECT_CC into an AND
8129 // when the condition can be materialized as an all-ones register. Any
8130 // single bit-test can be materialized as an all-ones register with
8131 // shift-left and shift-right-arith.
8132 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
8133 N0->getValueType(0) == VT &&
8134 N1C && N1C->isNullValue() &&
8135 N2C && N2C->isNullValue()) {
8136 SDValue AndLHS = N0->getOperand(0);
8137 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
8138 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
8139 // Shift the tested bit over the sign bit.
8140 APInt AndMask = ConstAndRHS->getAPIntValue();
8142 DAG.getConstant(AndMask.countLeadingZeros(),
8143 getShiftAmountTy(AndLHS.getValueType()));
8144 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt);
8146 // Now arithmetic right shift it all the way over, so the result is either
8147 // all-ones, or zero.
8149 DAG.getConstant(AndMask.getBitWidth()-1,
8150 getShiftAmountTy(Shl.getValueType()));
8151 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt);
8153 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
8157 // fold select C, 16, 0 -> shl C, 4
8158 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
8159 TLI.getBooleanContents(N0.getValueType().isVector()) ==
8160 TargetLowering::ZeroOrOneBooleanContent) {
8162 // If the caller doesn't want us to simplify this into a zext of a compare,
8164 if (NotExtCompare && N2C->getAPIntValue() == 1)
8167 // Get a SetCC of the condition
8168 // FIXME: Should probably make sure that setcc is legal if we ever have a
8169 // target where it isn't.
8171 // cast from setcc result type to select result type
8173 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
8175 if (N2.getValueType().bitsLT(SCC.getValueType()))
8176 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
8178 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
8179 N2.getValueType(), SCC);
8181 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
8182 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
8183 N2.getValueType(), SCC);
8186 AddToWorkList(SCC.getNode());
8187 AddToWorkList(Temp.getNode());
8189 if (N2C->getAPIntValue() == 1)
8192 // shl setcc result by log2 n2c
8193 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
8194 DAG.getConstant(N2C->getAPIntValue().logBase2(),
8195 getShiftAmountTy(Temp.getValueType())));
8198 // Check to see if this is the equivalent of setcc
8199 // FIXME: Turn all of these into setcc if setcc if setcc is legal
8200 // otherwise, go ahead with the folds.
8201 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
8202 EVT XType = N0.getValueType();
8203 if (!LegalOperations ||
8204 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
8205 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
8206 if (Res.getValueType() != VT)
8207 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
8211 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
8212 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
8213 (!LegalOperations ||
8214 TLI.isOperationLegal(ISD::CTLZ, XType))) {
8215 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
8216 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
8217 DAG.getConstant(Log2_32(XType.getSizeInBits()),
8218 getShiftAmountTy(Ctlz.getValueType())));
8220 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
8221 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
8222 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
8223 XType, DAG.getConstant(0, XType), N0);
8224 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
8225 return DAG.getNode(ISD::SRL, DL, XType,
8226 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
8227 DAG.getConstant(XType.getSizeInBits()-1,
8228 getShiftAmountTy(XType)));
8230 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
8231 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
8232 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
8233 DAG.getConstant(XType.getSizeInBits()-1,
8234 getShiftAmountTy(N0.getValueType())));
8235 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
8239 // Check to see if this is an integer abs.
8240 // select_cc setg[te] X, 0, X, -X ->
8241 // select_cc setgt X, -1, X, -X ->
8242 // select_cc setl[te] X, 0, -X, X ->
8243 // select_cc setlt X, 1, -X, X ->
8244 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
8246 ConstantSDNode *SubC = NULL;
8247 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
8248 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
8249 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
8250 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
8251 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
8252 (N1C->isOne() && CC == ISD::SETLT)) &&
8253 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
8254 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
8256 EVT XType = N0.getValueType();
8257 if (SubC && SubC->isNullValue() && XType.isInteger()) {
8258 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
8260 DAG.getConstant(XType.getSizeInBits()-1,
8261 getShiftAmountTy(N0.getValueType())));
8262 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
8264 AddToWorkList(Shift.getNode());
8265 AddToWorkList(Add.getNode());
8266 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
8273 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
8274 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
8275 SDValue N1, ISD::CondCode Cond,
8276 DebugLoc DL, bool foldBooleans) {
8277 TargetLowering::DAGCombinerInfo
8278 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
8279 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
8282 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
8283 /// return a DAG expression to select that will generate the same value by
8284 /// multiplying by a magic number. See:
8285 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
8286 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
8287 std::vector<SDNode*> Built;
8288 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built);
8290 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
8296 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
8297 /// return a DAG expression to select that will generate the same value by
8298 /// multiplying by a magic number. See:
8299 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
8300 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
8301 std::vector<SDNode*> Built;
8302 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built);
8304 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
8310 /// FindBaseOffset - Return true if base is a frame index, which is known not
8311 // to alias with anything but itself. Provides base object and offset as
8313 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
8314 const GlobalValue *&GV, void *&CV) {
8315 // Assume it is a primitive operation.
8316 Base = Ptr; Offset = 0; GV = 0; CV = 0;
8318 // If it's an adding a simple constant then integrate the offset.
8319 if (Base.getOpcode() == ISD::ADD) {
8320 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
8321 Base = Base.getOperand(0);
8322 Offset += C->getZExtValue();
8326 // Return the underlying GlobalValue, and update the Offset. Return false
8327 // for GlobalAddressSDNode since the same GlobalAddress may be represented
8328 // by multiple nodes with different offsets.
8329 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
8330 GV = G->getGlobal();
8331 Offset += G->getOffset();
8335 // Return the underlying Constant value, and update the Offset. Return false
8336 // for ConstantSDNodes since the same constant pool entry may be represented
8337 // by multiple nodes with different offsets.
8338 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
8339 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal()
8340 : (void *)C->getConstVal();
8341 Offset += C->getOffset();
8344 // If it's any of the following then it can't alias with anything but itself.
8345 return isa<FrameIndexSDNode>(Base);
8348 /// isAlias - Return true if there is any possibility that the two addresses
8350 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
8351 const Value *SrcValue1, int SrcValueOffset1,
8352 unsigned SrcValueAlign1,
8353 const MDNode *TBAAInfo1,
8354 SDValue Ptr2, int64_t Size2,
8355 const Value *SrcValue2, int SrcValueOffset2,
8356 unsigned SrcValueAlign2,
8357 const MDNode *TBAAInfo2) const {
8358 // If they are the same then they must be aliases.
8359 if (Ptr1 == Ptr2) return true;
8361 // Gather base node and offset information.
8362 SDValue Base1, Base2;
8363 int64_t Offset1, Offset2;
8364 const GlobalValue *GV1, *GV2;
8366 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
8367 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
8369 // If they have a same base address then check to see if they overlap.
8370 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
8371 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
8373 // It is possible for different frame indices to alias each other, mostly
8374 // when tail call optimization reuses return address slots for arguments.
8375 // To catch this case, look up the actual index of frame indices to compute
8376 // the real alias relationship.
8377 if (isFrameIndex1 && isFrameIndex2) {
8378 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8379 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
8380 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
8381 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
8384 // Otherwise, if we know what the bases are, and they aren't identical, then
8385 // we know they cannot alias.
8386 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
8389 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
8390 // compared to the size and offset of the access, we may be able to prove they
8391 // do not alias. This check is conservative for now to catch cases created by
8392 // splitting vector types.
8393 if ((SrcValueAlign1 == SrcValueAlign2) &&
8394 (SrcValueOffset1 != SrcValueOffset2) &&
8395 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
8396 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
8397 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
8399 // There is no overlap between these relatively aligned accesses of similar
8400 // size, return no alias.
8401 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
8405 if (CombinerGlobalAA) {
8406 // Use alias analysis information.
8407 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
8408 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
8409 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
8410 AliasAnalysis::AliasResult AAResult =
8411 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1),
8412 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2));
8413 if (AAResult == AliasAnalysis::NoAlias)
8417 // Otherwise we have to assume they alias.
8421 /// FindAliasInfo - Extracts the relevant alias information from the memory
8422 /// node. Returns true if the operand was a load.
8423 bool DAGCombiner::FindAliasInfo(SDNode *N,
8424 SDValue &Ptr, int64_t &Size,
8425 const Value *&SrcValue,
8426 int &SrcValueOffset,
8427 unsigned &SrcValueAlign,
8428 const MDNode *&TBAAInfo) const {
8429 LSBaseSDNode *LS = cast<LSBaseSDNode>(N);
8431 Ptr = LS->getBasePtr();
8432 Size = LS->getMemoryVT().getSizeInBits() >> 3;
8433 SrcValue = LS->getSrcValue();
8434 SrcValueOffset = LS->getSrcValueOffset();
8435 SrcValueAlign = LS->getOriginalAlignment();
8436 TBAAInfo = LS->getTBAAInfo();
8437 return isa<LoadSDNode>(LS);
8440 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
8441 /// looking for aliasing nodes and adding them to the Aliases vector.
8442 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
8443 SmallVector<SDValue, 8> &Aliases) {
8444 SmallVector<SDValue, 8> Chains; // List of chains to visit.
8445 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
8447 // Get alias information for node.
8450 const Value *SrcValue;
8452 unsigned SrcValueAlign;
8453 const MDNode *SrcTBAAInfo;
8454 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
8455 SrcValueAlign, SrcTBAAInfo);
8458 Chains.push_back(OriginalChain);
8461 // Look at each chain and determine if it is an alias. If so, add it to the
8462 // aliases list. If not, then continue up the chain looking for the next
8464 while (!Chains.empty()) {
8465 SDValue Chain = Chains.back();
8468 // For TokenFactor nodes, look at each operand and only continue up the
8469 // chain until we find two aliases. If we've seen two aliases, assume we'll
8470 // find more and revert to original chain since the xform is unlikely to be
8473 // FIXME: The depth check could be made to return the last non-aliasing
8474 // chain we found before we hit a tokenfactor rather than the original
8476 if (Depth > 6 || Aliases.size() == 2) {
8478 Aliases.push_back(OriginalChain);
8482 // Don't bother if we've been before.
8483 if (!Visited.insert(Chain.getNode()))
8486 switch (Chain.getOpcode()) {
8487 case ISD::EntryToken:
8488 // Entry token is ideal chain operand, but handled in FindBetterChain.
8493 // Get alias information for Chain.
8496 const Value *OpSrcValue;
8497 int OpSrcValueOffset;
8498 unsigned OpSrcValueAlign;
8499 const MDNode *OpSrcTBAAInfo;
8500 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
8501 OpSrcValue, OpSrcValueOffset,
8505 // If chain is alias then stop here.
8506 if (!(IsLoad && IsOpLoad) &&
8507 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
8509 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
8510 OpSrcValueAlign, OpSrcTBAAInfo)) {
8511 Aliases.push_back(Chain);
8513 // Look further up the chain.
8514 Chains.push_back(Chain.getOperand(0));
8520 case ISD::TokenFactor:
8521 // We have to check each of the operands of the token factor for "small"
8522 // token factors, so we queue them up. Adding the operands to the queue
8523 // (stack) in reverse order maintains the original order and increases the
8524 // likelihood that getNode will find a matching token factor (CSE.)
8525 if (Chain.getNumOperands() > 16) {
8526 Aliases.push_back(Chain);
8529 for (unsigned n = Chain.getNumOperands(); n;)
8530 Chains.push_back(Chain.getOperand(--n));
8535 // For all other instructions we will just have to take what we can get.
8536 Aliases.push_back(Chain);
8542 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
8543 /// for a better chain (aliasing node.)
8544 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
8545 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
8547 // Accumulate all the aliases to this node.
8548 GatherAllAliases(N, OldChain, Aliases);
8550 // If no operands then chain to entry token.
8551 if (Aliases.size() == 0)
8552 return DAG.getEntryNode();
8554 // If a single operand then chain to it. We don't need to revisit it.
8555 if (Aliases.size() == 1)
8558 // Construct a custom tailored token factor.
8559 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
8560 &Aliases[0], Aliases.size());
8563 // SelectionDAG::Combine - This is the entry point for the file.
8565 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
8566 CodeGenOpt::Level OptLevel) {
8567 /// run - This is the main entry point to this class.
8569 DAGCombiner(*this, AA, OptLevel).Run(Level);