1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: divide by zero is currently left unfolded. do we want to turn this
27 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "dagcombine"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/Analysis/AliasAnalysis.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Target/TargetLowering.h"
38 #include "llvm/Support/Compiler.h"
39 #include "llvm/Support/CommandLine.h"
47 static Statistic<> NodesCombined ("dagcombiner",
48 "Number of dag nodes combined");
51 CombinerAA("combiner-alias-analysis", cl::Hidden,
52 cl::desc("Turn on alias analysis during testing"));
55 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
56 cl::desc("Include global information in alias analysis"));
58 //------------------------------ DAGCombiner ---------------------------------//
60 class VISIBILITY_HIDDEN DAGCombiner {
65 // Worklist of all of the nodes that need to be simplified.
66 std::vector<SDNode*> WorkList;
68 // AA - Used for DAG load/store alias analysis.
71 /// AddUsersToWorkList - When an instruction is simplified, add all users of
72 /// the instruction to the work lists because they might get more simplified
75 void AddUsersToWorkList(SDNode *N) {
76 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
81 /// removeFromWorkList - remove all instances of N from the worklist.
83 void removeFromWorkList(SDNode *N) {
84 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
89 /// AddToWorkList - Add to the work list making sure it's instance is at the
90 /// the back (next to be processed.)
91 void AddToWorkList(SDNode *N) {
92 removeFromWorkList(N);
93 WorkList.push_back(N);
96 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
98 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
100 DEBUG(std::cerr << "\nReplacing.1 "; N->dump();
101 std::cerr << "\nWith: "; To[0].Val->dump(&DAG);
102 std::cerr << " and " << NumTo-1 << " other values\n");
103 std::vector<SDNode*> NowDead;
104 DAG.ReplaceAllUsesWith(N, To, &NowDead);
107 // Push the new nodes and any users onto the worklist
108 for (unsigned i = 0, e = NumTo; i != e; ++i) {
109 AddToWorkList(To[i].Val);
110 AddUsersToWorkList(To[i].Val);
114 // Nodes can be reintroduced into the worklist. Make sure we do not
115 // process a node that has been replaced.
116 removeFromWorkList(N);
117 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
118 removeFromWorkList(NowDead[i]);
120 // Finally, since the node is now dead, remove it from the graph.
122 return SDOperand(N, 0);
125 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
126 return CombineTo(N, &Res, 1, AddTo);
129 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
131 SDOperand To[] = { Res0, Res1 };
132 return CombineTo(N, To, 2, AddTo);
136 /// SimplifyDemandedBits - Check the specified integer node value to see if
137 /// it can be simplified or if things it uses can be simplified by bit
138 /// propagation. If so, return true.
139 bool SimplifyDemandedBits(SDOperand Op) {
140 TargetLowering::TargetLoweringOpt TLO(DAG);
141 uint64_t KnownZero, KnownOne;
142 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
143 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
147 AddToWorkList(Op.Val);
149 // Replace the old value with the new one.
151 DEBUG(std::cerr << "\nReplacing.2 "; TLO.Old.Val->dump();
152 std::cerr << "\nWith: "; TLO.New.Val->dump(&DAG);
155 std::vector<SDNode*> NowDead;
156 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
158 // Push the new node and any (possibly new) users onto the worklist.
159 AddToWorkList(TLO.New.Val);
160 AddUsersToWorkList(TLO.New.Val);
162 // Nodes can end up on the worklist more than once. Make sure we do
163 // not process a node that has been replaced.
164 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
165 removeFromWorkList(NowDead[i]);
167 // Finally, if the node is now dead, remove it from the graph. The node
168 // may not be dead if the replacement process recursively simplified to
169 // something else needing this node.
170 if (TLO.Old.Val->use_empty()) {
171 removeFromWorkList(TLO.Old.Val);
172 DAG.DeleteNode(TLO.Old.Val);
177 /// visit - call the node-specific routine that knows how to fold each
178 /// particular type of node.
179 SDOperand visit(SDNode *N);
181 // Visitation implementation - Implement dag node combining for different
182 // node types. The semantics are as follows:
184 // SDOperand.Val == 0 - No change was made
185 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
186 // otherwise - N should be replaced by the returned Operand.
188 SDOperand visitTokenFactor(SDNode *N);
189 SDOperand visitADD(SDNode *N);
190 SDOperand visitSUB(SDNode *N);
191 SDOperand visitMUL(SDNode *N);
192 SDOperand visitSDIV(SDNode *N);
193 SDOperand visitUDIV(SDNode *N);
194 SDOperand visitSREM(SDNode *N);
195 SDOperand visitUREM(SDNode *N);
196 SDOperand visitMULHU(SDNode *N);
197 SDOperand visitMULHS(SDNode *N);
198 SDOperand visitAND(SDNode *N);
199 SDOperand visitOR(SDNode *N);
200 SDOperand visitXOR(SDNode *N);
201 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp);
202 SDOperand visitSHL(SDNode *N);
203 SDOperand visitSRA(SDNode *N);
204 SDOperand visitSRL(SDNode *N);
205 SDOperand visitCTLZ(SDNode *N);
206 SDOperand visitCTTZ(SDNode *N);
207 SDOperand visitCTPOP(SDNode *N);
208 SDOperand visitSELECT(SDNode *N);
209 SDOperand visitSELECT_CC(SDNode *N);
210 SDOperand visitSETCC(SDNode *N);
211 SDOperand visitSIGN_EXTEND(SDNode *N);
212 SDOperand visitZERO_EXTEND(SDNode *N);
213 SDOperand visitANY_EXTEND(SDNode *N);
214 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
215 SDOperand visitTRUNCATE(SDNode *N);
216 SDOperand visitBIT_CONVERT(SDNode *N);
217 SDOperand visitVBIT_CONVERT(SDNode *N);
218 SDOperand visitFADD(SDNode *N);
219 SDOperand visitFSUB(SDNode *N);
220 SDOperand visitFMUL(SDNode *N);
221 SDOperand visitFDIV(SDNode *N);
222 SDOperand visitFREM(SDNode *N);
223 SDOperand visitFCOPYSIGN(SDNode *N);
224 SDOperand visitSINT_TO_FP(SDNode *N);
225 SDOperand visitUINT_TO_FP(SDNode *N);
226 SDOperand visitFP_TO_SINT(SDNode *N);
227 SDOperand visitFP_TO_UINT(SDNode *N);
228 SDOperand visitFP_ROUND(SDNode *N);
229 SDOperand visitFP_ROUND_INREG(SDNode *N);
230 SDOperand visitFP_EXTEND(SDNode *N);
231 SDOperand visitFNEG(SDNode *N);
232 SDOperand visitFABS(SDNode *N);
233 SDOperand visitBRCOND(SDNode *N);
234 SDOperand visitBR_CC(SDNode *N);
235 SDOperand visitLOAD(SDNode *N);
236 SDOperand visitSTORE(SDNode *N);
237 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
238 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
239 SDOperand visitVBUILD_VECTOR(SDNode *N);
240 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
241 SDOperand visitVVECTOR_SHUFFLE(SDNode *N);
243 SDOperand XformToShuffleWithZero(SDNode *N);
244 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
246 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
247 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
248 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
249 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
250 SDOperand N3, ISD::CondCode CC);
251 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
252 ISD::CondCode Cond, bool foldBooleans = true);
253 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType);
254 SDOperand BuildSDIV(SDNode *N);
255 SDOperand BuildUDIV(SDNode *N);
256 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
258 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
259 /// looking for aliasing nodes and adding them to the Aliases vector.
260 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
261 SmallVector<SDOperand, 8> &Aliases);
263 /// isAlias - Return true if there is any possibility that the two addresses
265 bool isAlias(SDOperand Ptr1, int64_t Size1,
266 const Value *SrcValue1, int SrcValueOffset1,
267 SDOperand Ptr2, int64_t Size2,
268 const Value *SrcValue2, int SrcValueOffset1);
270 /// FindAliasInfo - Extracts the relevant alias information from the memory
271 /// node. Returns true if the operand was a load.
272 bool FindAliasInfo(SDNode *N,
273 SDOperand &Ptr, int64_t &Size,
274 const Value *&SrcValue, int &SrcValueOffset);
276 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
277 /// looking for a better chain (aliasing node.)
278 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
281 DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
283 TLI(D.getTargetLoweringInfo()),
284 AfterLegalize(false),
287 /// Run - runs the dag combiner on all nodes in the work list
288 void Run(bool RunningAfterLegalize);
292 //===----------------------------------------------------------------------===//
293 // TargetLowering::DAGCombinerInfo implementation
294 //===----------------------------------------------------------------------===//
296 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
297 ((DAGCombiner*)DC)->AddToWorkList(N);
300 SDOperand TargetLowering::DAGCombinerInfo::
301 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
302 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
305 SDOperand TargetLowering::DAGCombinerInfo::
306 CombineTo(SDNode *N, SDOperand Res) {
307 return ((DAGCombiner*)DC)->CombineTo(N, Res);
311 SDOperand TargetLowering::DAGCombinerInfo::
312 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
313 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
319 //===----------------------------------------------------------------------===//
322 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
323 // that selects between the values 1 and 0, making it equivalent to a setcc.
324 // Also, set the incoming LHS, RHS, and CC references to the appropriate
325 // nodes based on the type of node we are checking. This simplifies life a
326 // bit for the callers.
327 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
329 if (N.getOpcode() == ISD::SETCC) {
330 LHS = N.getOperand(0);
331 RHS = N.getOperand(1);
332 CC = N.getOperand(2);
335 if (N.getOpcode() == ISD::SELECT_CC &&
336 N.getOperand(2).getOpcode() == ISD::Constant &&
337 N.getOperand(3).getOpcode() == ISD::Constant &&
338 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
339 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
340 LHS = N.getOperand(0);
341 RHS = N.getOperand(1);
342 CC = N.getOperand(4);
348 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
349 // one use. If this is true, it allows the users to invert the operation for
350 // free when it is profitable to do so.
351 static bool isOneUseSetCC(SDOperand N) {
352 SDOperand N0, N1, N2;
353 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
358 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
359 MVT::ValueType VT = N0.getValueType();
360 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
361 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
362 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
363 if (isa<ConstantSDNode>(N1)) {
364 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
365 AddToWorkList(OpNode.Val);
366 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
367 } else if (N0.hasOneUse()) {
368 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
369 AddToWorkList(OpNode.Val);
370 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
373 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
374 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
375 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
376 if (isa<ConstantSDNode>(N0)) {
377 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
378 AddToWorkList(OpNode.Val);
379 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
380 } else if (N1.hasOneUse()) {
381 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
382 AddToWorkList(OpNode.Val);
383 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
389 void DAGCombiner::Run(bool RunningAfterLegalize) {
390 // set the instance variable, so that the various visit routines may use it.
391 AfterLegalize = RunningAfterLegalize;
393 // Add all the dag nodes to the worklist.
394 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
395 E = DAG.allnodes_end(); I != E; ++I)
396 WorkList.push_back(I);
398 // Create a dummy node (which is not added to allnodes), that adds a reference
399 // to the root node, preventing it from being deleted, and tracking any
400 // changes of the root.
401 HandleSDNode Dummy(DAG.getRoot());
403 // The root of the dag may dangle to deleted nodes until the dag combiner is
404 // done. Set it to null to avoid confusion.
405 DAG.setRoot(SDOperand());
407 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
408 TargetLowering::DAGCombinerInfo
409 DagCombineInfo(DAG, !RunningAfterLegalize, this);
411 // while the worklist isn't empty, inspect the node on the end of it and
412 // try and combine it.
413 while (!WorkList.empty()) {
414 SDNode *N = WorkList.back();
417 // If N has no uses, it is dead. Make sure to revisit all N's operands once
418 // N is deleted from the DAG, since they too may now be dead or may have a
419 // reduced number of uses, allowing other xforms.
420 if (N->use_empty() && N != &Dummy) {
421 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
422 AddToWorkList(N->getOperand(i).Val);
428 SDOperand RV = visit(N);
430 // If nothing happened, try a target-specific DAG combine.
432 assert(N->getOpcode() != ISD::DELETED_NODE &&
433 "Node was deleted but visit returned NULL!");
434 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
435 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
436 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
441 // If we get back the same node we passed in, rather than a new node or
442 // zero, we know that the node must have defined multiple values and
443 // CombineTo was used. Since CombineTo takes care of the worklist
444 // mechanics for us, we have no work to do in this case.
446 assert(N->getOpcode() != ISD::DELETED_NODE &&
447 RV.Val->getOpcode() != ISD::DELETED_NODE &&
448 "Node was deleted but visit returned new node!");
450 DEBUG(std::cerr << "\nReplacing.3 "; N->dump();
451 std::cerr << "\nWith: "; RV.Val->dump(&DAG);
453 std::vector<SDNode*> NowDead;
454 if (N->getNumValues() == RV.Val->getNumValues())
455 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
457 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
459 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
462 // Push the new node and any users onto the worklist
463 AddToWorkList(RV.Val);
464 AddUsersToWorkList(RV.Val);
466 // Nodes can be reintroduced into the worklist. Make sure we do not
467 // process a node that has been replaced.
468 removeFromWorkList(N);
469 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
470 removeFromWorkList(NowDead[i]);
472 // Finally, since the node is now dead, remove it from the graph.
478 // If the root changed (e.g. it was a dead load, update the root).
479 DAG.setRoot(Dummy.getValue());
482 SDOperand DAGCombiner::visit(SDNode *N) {
483 switch(N->getOpcode()) {
485 case ISD::TokenFactor: return visitTokenFactor(N);
486 case ISD::ADD: return visitADD(N);
487 case ISD::SUB: return visitSUB(N);
488 case ISD::MUL: return visitMUL(N);
489 case ISD::SDIV: return visitSDIV(N);
490 case ISD::UDIV: return visitUDIV(N);
491 case ISD::SREM: return visitSREM(N);
492 case ISD::UREM: return visitUREM(N);
493 case ISD::MULHU: return visitMULHU(N);
494 case ISD::MULHS: return visitMULHS(N);
495 case ISD::AND: return visitAND(N);
496 case ISD::OR: return visitOR(N);
497 case ISD::XOR: return visitXOR(N);
498 case ISD::SHL: return visitSHL(N);
499 case ISD::SRA: return visitSRA(N);
500 case ISD::SRL: return visitSRL(N);
501 case ISD::CTLZ: return visitCTLZ(N);
502 case ISD::CTTZ: return visitCTTZ(N);
503 case ISD::CTPOP: return visitCTPOP(N);
504 case ISD::SELECT: return visitSELECT(N);
505 case ISD::SELECT_CC: return visitSELECT_CC(N);
506 case ISD::SETCC: return visitSETCC(N);
507 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
508 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
509 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
510 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
511 case ISD::TRUNCATE: return visitTRUNCATE(N);
512 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
513 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N);
514 case ISD::FADD: return visitFADD(N);
515 case ISD::FSUB: return visitFSUB(N);
516 case ISD::FMUL: return visitFMUL(N);
517 case ISD::FDIV: return visitFDIV(N);
518 case ISD::FREM: return visitFREM(N);
519 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
520 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
521 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
522 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
523 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
524 case ISD::FP_ROUND: return visitFP_ROUND(N);
525 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
526 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
527 case ISD::FNEG: return visitFNEG(N);
528 case ISD::FABS: return visitFABS(N);
529 case ISD::BRCOND: return visitBRCOND(N);
530 case ISD::BR_CC: return visitBR_CC(N);
531 case ISD::LOAD: return visitLOAD(N);
532 case ISD::STORE: return visitSTORE(N);
533 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
534 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
535 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N);
536 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
537 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N);
538 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD);
539 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB);
540 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL);
541 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV);
542 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV);
543 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND);
544 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR);
545 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR);
550 /// getInputChainForNode - Given a node, return its input chain if it has one,
551 /// otherwise return a null sd operand.
552 static SDOperand getInputChainForNode(SDNode *N) {
553 if (unsigned NumOps = N->getNumOperands()) {
554 if (N->getOperand(0).getValueType() == MVT::Other)
555 return N->getOperand(0);
556 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
557 return N->getOperand(NumOps-1);
558 for (unsigned i = 1; i < NumOps-1; ++i)
559 if (N->getOperand(i).getValueType() == MVT::Other)
560 return N->getOperand(i);
562 return SDOperand(0, 0);
565 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
566 // If N has two operands, where one has an input chain equal to the other,
567 // the 'other' chain is redundant.
568 if (N->getNumOperands() == 2) {
569 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
570 return N->getOperand(0);
571 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
572 return N->getOperand(1);
576 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
577 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
578 bool Changed = false; // If we should replace this token factor.
580 // Start out with this token factor.
583 // Iterate through token factors. The TFs grows when new token factors are
585 for (unsigned i = 0; i < TFs.size(); ++i) {
588 // Check each of the operands.
589 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
590 SDOperand Op = TF->getOperand(i);
592 switch (Op.getOpcode()) {
593 case ISD::EntryToken:
594 // Entry tokens don't need to be added to the list. They are
599 case ISD::TokenFactor:
600 if ((CombinerAA || Op.hasOneUse()) &&
601 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
602 // Queue up for processing.
603 TFs.push_back(Op.Val);
604 // Clean up in case the token factor is removed.
605 AddToWorkList(Op.Val);
612 // Only add if not there prior.
613 if (std::find(Ops.begin(), Ops.end(), Op) == Ops.end())
622 // If we've change things around then replace token factor.
624 if (Ops.size() == 0) {
625 // The entry token is the only possible outcome.
626 Result = DAG.getEntryNode();
628 // New and improved token factor.
629 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
632 // Don't add users to work list.
633 return CombineTo(N, Result, false);
639 SDOperand DAGCombiner::visitADD(SDNode *N) {
640 SDOperand N0 = N->getOperand(0);
641 SDOperand N1 = N->getOperand(1);
642 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
643 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
644 MVT::ValueType VT = N0.getValueType();
646 // fold (add c1, c2) -> c1+c2
648 return DAG.getNode(ISD::ADD, VT, N0, N1);
649 // canonicalize constant to RHS
651 return DAG.getNode(ISD::ADD, VT, N1, N0);
652 // fold (add x, 0) -> x
653 if (N1C && N1C->isNullValue())
655 // fold ((c1-A)+c2) -> (c1+c2)-A
656 if (N1C && N0.getOpcode() == ISD::SUB)
657 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
658 return DAG.getNode(ISD::SUB, VT,
659 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
662 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
665 // fold ((0-A) + B) -> B-A
666 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
667 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
668 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
669 // fold (A + (0-B)) -> A-B
670 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
671 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
672 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
673 // fold (A+(B-A)) -> B
674 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
675 return N1.getOperand(0);
677 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
678 return SDOperand(N, 0);
680 // fold (a+b) -> (a|b) iff a and b share no bits.
681 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
682 uint64_t LHSZero, LHSOne;
683 uint64_t RHSZero, RHSOne;
684 uint64_t Mask = MVT::getIntVTBitMask(VT);
685 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
687 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
689 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
690 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
691 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
692 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
693 return DAG.getNode(ISD::OR, VT, N0, N1);
700 SDOperand DAGCombiner::visitSUB(SDNode *N) {
701 SDOperand N0 = N->getOperand(0);
702 SDOperand N1 = N->getOperand(1);
703 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
704 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
705 MVT::ValueType VT = N0.getValueType();
707 // fold (sub x, x) -> 0
709 return DAG.getConstant(0, N->getValueType(0));
710 // fold (sub c1, c2) -> c1-c2
712 return DAG.getNode(ISD::SUB, VT, N0, N1);
713 // fold (sub x, c) -> (add x, -c)
715 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
717 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
718 return N0.getOperand(1);
720 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
721 return N0.getOperand(0);
725 SDOperand DAGCombiner::visitMUL(SDNode *N) {
726 SDOperand N0 = N->getOperand(0);
727 SDOperand N1 = N->getOperand(1);
728 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
729 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
730 MVT::ValueType VT = N0.getValueType();
732 // fold (mul c1, c2) -> c1*c2
734 return DAG.getNode(ISD::MUL, VT, N0, N1);
735 // canonicalize constant to RHS
737 return DAG.getNode(ISD::MUL, VT, N1, N0);
738 // fold (mul x, 0) -> 0
739 if (N1C && N1C->isNullValue())
741 // fold (mul x, -1) -> 0-x
742 if (N1C && N1C->isAllOnesValue())
743 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
744 // fold (mul x, (1 << c)) -> x << c
745 if (N1C && isPowerOf2_64(N1C->getValue()))
746 return DAG.getNode(ISD::SHL, VT, N0,
747 DAG.getConstant(Log2_64(N1C->getValue()),
748 TLI.getShiftAmountTy()));
749 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
750 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
751 // FIXME: If the input is something that is easily negated (e.g. a
752 // single-use add), we should put the negate there.
753 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
754 DAG.getNode(ISD::SHL, VT, N0,
755 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
756 TLI.getShiftAmountTy())));
759 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
760 if (N1C && N0.getOpcode() == ISD::SHL &&
761 isa<ConstantSDNode>(N0.getOperand(1))) {
762 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
763 AddToWorkList(C3.Val);
764 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
767 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
770 SDOperand Sh(0,0), Y(0,0);
771 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
772 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
773 N0.Val->hasOneUse()) {
775 } else if (N1.getOpcode() == ISD::SHL &&
776 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
780 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
781 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
784 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
785 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
786 isa<ConstantSDNode>(N0.getOperand(1))) {
787 return DAG.getNode(ISD::ADD, VT,
788 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
789 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
793 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
799 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
800 SDOperand N0 = N->getOperand(0);
801 SDOperand N1 = N->getOperand(1);
802 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
803 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
804 MVT::ValueType VT = N->getValueType(0);
806 // fold (sdiv c1, c2) -> c1/c2
807 if (N0C && N1C && !N1C->isNullValue())
808 return DAG.getNode(ISD::SDIV, VT, N0, N1);
809 // fold (sdiv X, 1) -> X
810 if (N1C && N1C->getSignExtended() == 1LL)
812 // fold (sdiv X, -1) -> 0-X
813 if (N1C && N1C->isAllOnesValue())
814 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
815 // If we know the sign bits of both operands are zero, strength reduce to a
816 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
817 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
818 if (TLI.MaskedValueIsZero(N1, SignBit) &&
819 TLI.MaskedValueIsZero(N0, SignBit))
820 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
821 // fold (sdiv X, pow2) -> simple ops after legalize
822 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
823 (isPowerOf2_64(N1C->getSignExtended()) ||
824 isPowerOf2_64(-N1C->getSignExtended()))) {
825 // If dividing by powers of two is cheap, then don't perform the following
827 if (TLI.isPow2DivCheap())
829 int64_t pow2 = N1C->getSignExtended();
830 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
831 unsigned lg2 = Log2_64(abs2);
832 // Splat the sign bit into the register
833 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
834 DAG.getConstant(MVT::getSizeInBits(VT)-1,
835 TLI.getShiftAmountTy()));
836 AddToWorkList(SGN.Val);
837 // Add (N0 < 0) ? abs2 - 1 : 0;
838 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
839 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
840 TLI.getShiftAmountTy()));
841 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
842 AddToWorkList(SRL.Val);
843 AddToWorkList(ADD.Val); // Divide by pow2
844 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
845 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
846 // If we're dividing by a positive value, we're done. Otherwise, we must
847 // negate the result.
850 AddToWorkList(SRA.Val);
851 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
853 // if integer divide is expensive and we satisfy the requirements, emit an
854 // alternate sequence.
855 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
856 !TLI.isIntDivCheap()) {
857 SDOperand Op = BuildSDIV(N);
858 if (Op.Val) return Op;
863 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
864 SDOperand N0 = N->getOperand(0);
865 SDOperand N1 = N->getOperand(1);
866 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
867 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
868 MVT::ValueType VT = N->getValueType(0);
870 // fold (udiv c1, c2) -> c1/c2
871 if (N0C && N1C && !N1C->isNullValue())
872 return DAG.getNode(ISD::UDIV, VT, N0, N1);
873 // fold (udiv x, (1 << c)) -> x >>u c
874 if (N1C && isPowerOf2_64(N1C->getValue()))
875 return DAG.getNode(ISD::SRL, VT, N0,
876 DAG.getConstant(Log2_64(N1C->getValue()),
877 TLI.getShiftAmountTy()));
878 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
879 if (N1.getOpcode() == ISD::SHL) {
880 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
881 if (isPowerOf2_64(SHC->getValue())) {
882 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
883 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
884 DAG.getConstant(Log2_64(SHC->getValue()),
886 AddToWorkList(Add.Val);
887 return DAG.getNode(ISD::SRL, VT, N0, Add);
891 // fold (udiv x, c) -> alternate
892 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
893 SDOperand Op = BuildUDIV(N);
894 if (Op.Val) return Op;
899 SDOperand DAGCombiner::visitSREM(SDNode *N) {
900 SDOperand N0 = N->getOperand(0);
901 SDOperand N1 = N->getOperand(1);
902 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
903 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
904 MVT::ValueType VT = N->getValueType(0);
906 // fold (srem c1, c2) -> c1%c2
907 if (N0C && N1C && !N1C->isNullValue())
908 return DAG.getNode(ISD::SREM, VT, N0, N1);
909 // If we know the sign bits of both operands are zero, strength reduce to a
910 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
911 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
912 if (TLI.MaskedValueIsZero(N1, SignBit) &&
913 TLI.MaskedValueIsZero(N0, SignBit))
914 return DAG.getNode(ISD::UREM, VT, N0, N1);
916 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
917 // the remainder operation.
918 if (N1C && !N1C->isNullValue()) {
919 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
920 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
921 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
922 AddToWorkList(Div.Val);
923 AddToWorkList(Mul.Val);
930 SDOperand DAGCombiner::visitUREM(SDNode *N) {
931 SDOperand N0 = N->getOperand(0);
932 SDOperand N1 = N->getOperand(1);
933 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
934 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
935 MVT::ValueType VT = N->getValueType(0);
937 // fold (urem c1, c2) -> c1%c2
938 if (N0C && N1C && !N1C->isNullValue())
939 return DAG.getNode(ISD::UREM, VT, N0, N1);
940 // fold (urem x, pow2) -> (and x, pow2-1)
941 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
942 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
943 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
944 if (N1.getOpcode() == ISD::SHL) {
945 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
946 if (isPowerOf2_64(SHC->getValue())) {
947 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
948 AddToWorkList(Add.Val);
949 return DAG.getNode(ISD::AND, VT, N0, Add);
954 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
955 // the remainder operation.
956 if (N1C && !N1C->isNullValue()) {
957 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
958 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
959 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
960 AddToWorkList(Div.Val);
961 AddToWorkList(Mul.Val);
968 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
969 SDOperand N0 = N->getOperand(0);
970 SDOperand N1 = N->getOperand(1);
971 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
973 // fold (mulhs x, 0) -> 0
974 if (N1C && N1C->isNullValue())
976 // fold (mulhs x, 1) -> (sra x, size(x)-1)
977 if (N1C && N1C->getValue() == 1)
978 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
979 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
980 TLI.getShiftAmountTy()));
984 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
985 SDOperand N0 = N->getOperand(0);
986 SDOperand N1 = N->getOperand(1);
987 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
989 // fold (mulhu x, 0) -> 0
990 if (N1C && N1C->isNullValue())
992 // fold (mulhu x, 1) -> 0
993 if (N1C && N1C->getValue() == 1)
994 return DAG.getConstant(0, N0.getValueType());
998 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
999 /// two operands of the same opcode, try to simplify it.
1000 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1001 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
1002 MVT::ValueType VT = N0.getValueType();
1003 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1005 // For each of OP in AND/OR/XOR:
1006 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1007 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1008 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1009 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1010 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1011 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1012 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1013 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1014 N0.getOperand(0).getValueType(),
1015 N0.getOperand(0), N1.getOperand(0));
1016 AddToWorkList(ORNode.Val);
1017 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1020 // For each of OP in SHL/SRL/SRA/AND...
1021 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1022 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1023 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1024 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1025 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1026 N0.getOperand(1) == N1.getOperand(1)) {
1027 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1028 N0.getOperand(0).getValueType(),
1029 N0.getOperand(0), N1.getOperand(0));
1030 AddToWorkList(ORNode.Val);
1031 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1037 SDOperand DAGCombiner::visitAND(SDNode *N) {
1038 SDOperand N0 = N->getOperand(0);
1039 SDOperand N1 = N->getOperand(1);
1040 SDOperand LL, LR, RL, RR, CC0, CC1;
1041 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1042 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1043 MVT::ValueType VT = N1.getValueType();
1044 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1046 // fold (and c1, c2) -> c1&c2
1048 return DAG.getNode(ISD::AND, VT, N0, N1);
1049 // canonicalize constant to RHS
1051 return DAG.getNode(ISD::AND, VT, N1, N0);
1052 // fold (and x, -1) -> x
1053 if (N1C && N1C->isAllOnesValue())
1055 // if (and x, c) is known to be zero, return 0
1056 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1057 return DAG.getConstant(0, VT);
1059 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1062 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1063 if (N1C && N0.getOpcode() == ISD::OR)
1064 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1065 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1067 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1068 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1069 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1070 if (TLI.MaskedValueIsZero(N0.getOperand(0),
1071 ~N1C->getValue() & InMask)) {
1072 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1075 // Replace uses of the AND with uses of the Zero extend node.
1078 // We actually want to replace all uses of the any_extend with the
1079 // zero_extend, to avoid duplicating things. This will later cause this
1080 // AND to be folded.
1081 CombineTo(N0.Val, Zext);
1082 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1085 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1086 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1087 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1088 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1090 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1091 MVT::isInteger(LL.getValueType())) {
1092 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1093 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1094 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1095 AddToWorkList(ORNode.Val);
1096 return DAG.getSetCC(VT, ORNode, LR, Op1);
1098 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1099 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1100 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1101 AddToWorkList(ANDNode.Val);
1102 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1104 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1105 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1106 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1107 AddToWorkList(ORNode.Val);
1108 return DAG.getSetCC(VT, ORNode, LR, Op1);
1111 // canonicalize equivalent to ll == rl
1112 if (LL == RR && LR == RL) {
1113 Op1 = ISD::getSetCCSwappedOperands(Op1);
1116 if (LL == RL && LR == RR) {
1117 bool isInteger = MVT::isInteger(LL.getValueType());
1118 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1119 if (Result != ISD::SETCC_INVALID)
1120 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1124 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1125 if (N0.getOpcode() == N1.getOpcode()) {
1126 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1127 if (Tmp.Val) return Tmp;
1130 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1131 // fold (and (sra)) -> (and (srl)) when possible.
1132 if (!MVT::isVector(VT) &&
1133 SimplifyDemandedBits(SDOperand(N, 0)))
1134 return SDOperand(N, 0);
1135 // fold (zext_inreg (extload x)) -> (zextload x)
1136 if (ISD::isEXTLoad(N0.Val)) {
1137 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1138 MVT::ValueType EVT = LN0->getLoadedVT();
1139 // If we zero all the possible extended bits, then we can turn this into
1140 // a zextload if we are running before legalize or the operation is legal.
1141 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1142 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1143 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1144 LN0->getBasePtr(), LN0->getSrcValue(),
1145 LN0->getSrcValueOffset(), EVT);
1147 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1148 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1151 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1152 if (ISD::isSEXTLoad(N0.Val) && N0.hasOneUse()) {
1153 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1154 MVT::ValueType EVT = LN0->getLoadedVT();
1155 // If we zero all the possible extended bits, then we can turn this into
1156 // a zextload if we are running before legalize or the operation is legal.
1157 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1158 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1159 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1160 LN0->getBasePtr(), LN0->getSrcValue(),
1161 LN0->getSrcValueOffset(), EVT);
1163 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1164 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1168 // fold (and (load x), 255) -> (zextload x, i8)
1169 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1170 if (N1C && N0.getOpcode() == ISD::LOAD) {
1171 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1172 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1174 MVT::ValueType EVT, LoadedVT;
1175 if (N1C->getValue() == 255)
1177 else if (N1C->getValue() == 65535)
1179 else if (N1C->getValue() == ~0U)
1184 LoadedVT = LN0->getLoadedVT();
1185 if (EVT != MVT::Other && LoadedVT > EVT &&
1186 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1187 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1188 // For big endian targets, we need to add an offset to the pointer to
1189 // load the correct bytes. For little endian systems, we merely need to
1190 // read fewer bytes from the same pointer.
1192 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1193 SDOperand NewPtr = LN0->getBasePtr();
1194 if (!TLI.isLittleEndian())
1195 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1196 DAG.getConstant(PtrOff, PtrType));
1197 AddToWorkList(NewPtr.Val);
1199 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1200 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT);
1202 CombineTo(N0.Val, Load, Load.getValue(1));
1203 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1211 SDOperand DAGCombiner::visitOR(SDNode *N) {
1212 SDOperand N0 = N->getOperand(0);
1213 SDOperand N1 = N->getOperand(1);
1214 SDOperand LL, LR, RL, RR, CC0, CC1;
1215 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1216 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1217 MVT::ValueType VT = N1.getValueType();
1218 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1220 // fold (or c1, c2) -> c1|c2
1222 return DAG.getNode(ISD::OR, VT, N0, N1);
1223 // canonicalize constant to RHS
1225 return DAG.getNode(ISD::OR, VT, N1, N0);
1226 // fold (or x, 0) -> x
1227 if (N1C && N1C->isNullValue())
1229 // fold (or x, -1) -> -1
1230 if (N1C && N1C->isAllOnesValue())
1232 // fold (or x, c) -> c iff (x & ~c) == 0
1234 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1237 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1240 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1241 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1242 isa<ConstantSDNode>(N0.getOperand(1))) {
1243 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1244 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1246 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1248 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1249 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1250 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1251 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1253 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1254 MVT::isInteger(LL.getValueType())) {
1255 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1256 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1257 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1258 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1259 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1260 AddToWorkList(ORNode.Val);
1261 return DAG.getSetCC(VT, ORNode, LR, Op1);
1263 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1264 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1265 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1266 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1267 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1268 AddToWorkList(ANDNode.Val);
1269 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1272 // canonicalize equivalent to ll == rl
1273 if (LL == RR && LR == RL) {
1274 Op1 = ISD::getSetCCSwappedOperands(Op1);
1277 if (LL == RL && LR == RR) {
1278 bool isInteger = MVT::isInteger(LL.getValueType());
1279 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1280 if (Result != ISD::SETCC_INVALID)
1281 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1285 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1286 if (N0.getOpcode() == N1.getOpcode()) {
1287 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1288 if (Tmp.Val) return Tmp;
1291 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1292 if (N0.getOpcode() == ISD::AND &&
1293 N1.getOpcode() == ISD::AND &&
1294 N0.getOperand(1).getOpcode() == ISD::Constant &&
1295 N1.getOperand(1).getOpcode() == ISD::Constant &&
1296 // Don't increase # computations.
1297 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1298 // We can only do this xform if we know that bits from X that are set in C2
1299 // but not in C1 are already zero. Likewise for Y.
1300 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1301 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1303 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1304 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1305 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1306 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1311 // See if this is some rotate idiom.
1312 if (SDNode *Rot = MatchRotate(N0, N1))
1313 return SDOperand(Rot, 0);
1319 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1320 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1321 if (Op.getOpcode() == ISD::AND) {
1322 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1323 Mask = Op.getOperand(1);
1324 Op = Op.getOperand(0);
1330 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1338 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1339 // idioms for rotate, and if the target supports rotation instructions, generate
1341 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1342 // Must be a legal type. Expanded an promoted things won't work with rotates.
1343 MVT::ValueType VT = LHS.getValueType();
1344 if (!TLI.isTypeLegal(VT)) return 0;
1346 // The target must have at least one rotate flavor.
1347 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1348 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1349 if (!HasROTL && !HasROTR) return 0;
1351 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1352 SDOperand LHSShift; // The shift.
1353 SDOperand LHSMask; // AND value if any.
1354 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1355 return 0; // Not part of a rotate.
1357 SDOperand RHSShift; // The shift.
1358 SDOperand RHSMask; // AND value if any.
1359 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1360 return 0; // Not part of a rotate.
1362 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1363 return 0; // Not shifting the same value.
1365 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1366 return 0; // Shifts must disagree.
1368 // Canonicalize shl to left side in a shl/srl pair.
1369 if (RHSShift.getOpcode() == ISD::SHL) {
1370 std::swap(LHS, RHS);
1371 std::swap(LHSShift, RHSShift);
1372 std::swap(LHSMask , RHSMask );
1375 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1377 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1378 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1379 if (LHSShift.getOperand(1).getOpcode() == ISD::Constant &&
1380 RHSShift.getOperand(1).getOpcode() == ISD::Constant) {
1381 uint64_t LShVal = cast<ConstantSDNode>(LHSShift.getOperand(1))->getValue();
1382 uint64_t RShVal = cast<ConstantSDNode>(RHSShift.getOperand(1))->getValue();
1383 if ((LShVal + RShVal) != OpSizeInBits)
1388 Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1389 LHSShift.getOperand(1));
1391 Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1392 RHSShift.getOperand(1));
1394 // If there is an AND of either shifted operand, apply it to the result.
1395 if (LHSMask.Val || RHSMask.Val) {
1396 uint64_t Mask = MVT::getIntVTBitMask(VT);
1399 uint64_t RHSBits = (1ULL << LShVal)-1;
1400 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1403 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1404 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1407 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1413 // If there is a mask here, and we have a variable shift, we can't be sure
1414 // that we're masking out the right stuff.
1415 if (LHSMask.Val || RHSMask.Val)
1418 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1419 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1420 if (RHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1421 LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) {
1422 if (ConstantSDNode *SUBC =
1423 dyn_cast<ConstantSDNode>(RHSShift.getOperand(1).getOperand(0))) {
1424 if (SUBC->getValue() == OpSizeInBits)
1426 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1427 LHSShift.getOperand(1)).Val;
1429 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1430 LHSShift.getOperand(1)).Val;
1434 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1435 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1436 if (LHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1437 RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) {
1438 if (ConstantSDNode *SUBC =
1439 dyn_cast<ConstantSDNode>(LHSShift.getOperand(1).getOperand(0))) {
1440 if (SUBC->getValue() == OpSizeInBits)
1442 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1443 LHSShift.getOperand(1)).Val;
1445 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1446 RHSShift.getOperand(1)).Val;
1454 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1455 SDOperand N0 = N->getOperand(0);
1456 SDOperand N1 = N->getOperand(1);
1457 SDOperand LHS, RHS, CC;
1458 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1459 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1460 MVT::ValueType VT = N0.getValueType();
1462 // fold (xor c1, c2) -> c1^c2
1464 return DAG.getNode(ISD::XOR, VT, N0, N1);
1465 // canonicalize constant to RHS
1467 return DAG.getNode(ISD::XOR, VT, N1, N0);
1468 // fold (xor x, 0) -> x
1469 if (N1C && N1C->isNullValue())
1472 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1475 // fold !(x cc y) -> (x !cc y)
1476 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1477 bool isInt = MVT::isInteger(LHS.getValueType());
1478 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1480 if (N0.getOpcode() == ISD::SETCC)
1481 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1482 if (N0.getOpcode() == ISD::SELECT_CC)
1483 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1484 assert(0 && "Unhandled SetCC Equivalent!");
1487 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1488 if (N1C && N1C->getValue() == 1 &&
1489 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1490 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1491 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1492 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1493 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1494 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1495 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1496 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1499 // fold !(x or y) -> (!x and !y) iff x or y are constants
1500 if (N1C && N1C->isAllOnesValue() &&
1501 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1502 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1503 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1504 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1505 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1506 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1507 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1508 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1511 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1512 if (N1C && N0.getOpcode() == ISD::XOR) {
1513 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1514 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1516 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1517 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1519 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1520 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1522 // fold (xor x, x) -> 0
1524 if (!MVT::isVector(VT)) {
1525 return DAG.getConstant(0, VT);
1526 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1527 // Produce a vector of zeros.
1528 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
1529 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
1530 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1534 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
1535 if (N0.getOpcode() == N1.getOpcode()) {
1536 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1537 if (Tmp.Val) return Tmp;
1540 // Simplify the expression using non-local knowledge.
1541 if (!MVT::isVector(VT) &&
1542 SimplifyDemandedBits(SDOperand(N, 0)))
1543 return SDOperand(N, 0);
1548 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1549 SDOperand N0 = N->getOperand(0);
1550 SDOperand N1 = N->getOperand(1);
1551 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1552 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1553 MVT::ValueType VT = N0.getValueType();
1554 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1556 // fold (shl c1, c2) -> c1<<c2
1558 return DAG.getNode(ISD::SHL, VT, N0, N1);
1559 // fold (shl 0, x) -> 0
1560 if (N0C && N0C->isNullValue())
1562 // fold (shl x, c >= size(x)) -> undef
1563 if (N1C && N1C->getValue() >= OpSizeInBits)
1564 return DAG.getNode(ISD::UNDEF, VT);
1565 // fold (shl x, 0) -> x
1566 if (N1C && N1C->isNullValue())
1568 // if (shl x, c) is known to be zero, return 0
1569 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1570 return DAG.getConstant(0, VT);
1571 if (SimplifyDemandedBits(SDOperand(N, 0)))
1572 return SDOperand(N, 0);
1573 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1574 if (N1C && N0.getOpcode() == ISD::SHL &&
1575 N0.getOperand(1).getOpcode() == ISD::Constant) {
1576 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1577 uint64_t c2 = N1C->getValue();
1578 if (c1 + c2 > OpSizeInBits)
1579 return DAG.getConstant(0, VT);
1580 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1581 DAG.getConstant(c1 + c2, N1.getValueType()));
1583 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1584 // (srl (and x, -1 << c1), c1-c2)
1585 if (N1C && N0.getOpcode() == ISD::SRL &&
1586 N0.getOperand(1).getOpcode() == ISD::Constant) {
1587 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1588 uint64_t c2 = N1C->getValue();
1589 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1590 DAG.getConstant(~0ULL << c1, VT));
1592 return DAG.getNode(ISD::SHL, VT, Mask,
1593 DAG.getConstant(c2-c1, N1.getValueType()));
1595 return DAG.getNode(ISD::SRL, VT, Mask,
1596 DAG.getConstant(c1-c2, N1.getValueType()));
1598 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1599 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1600 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1601 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1602 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
1603 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1604 isa<ConstantSDNode>(N0.getOperand(1))) {
1605 return DAG.getNode(ISD::ADD, VT,
1606 DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1),
1607 DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1));
1612 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1613 SDOperand N0 = N->getOperand(0);
1614 SDOperand N1 = N->getOperand(1);
1615 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1616 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1617 MVT::ValueType VT = N0.getValueType();
1619 // fold (sra c1, c2) -> c1>>c2
1621 return DAG.getNode(ISD::SRA, VT, N0, N1);
1622 // fold (sra 0, x) -> 0
1623 if (N0C && N0C->isNullValue())
1625 // fold (sra -1, x) -> -1
1626 if (N0C && N0C->isAllOnesValue())
1628 // fold (sra x, c >= size(x)) -> undef
1629 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
1630 return DAG.getNode(ISD::UNDEF, VT);
1631 // fold (sra x, 0) -> x
1632 if (N1C && N1C->isNullValue())
1634 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
1636 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
1637 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
1640 default: EVT = MVT::Other; break;
1641 case 1: EVT = MVT::i1; break;
1642 case 8: EVT = MVT::i8; break;
1643 case 16: EVT = MVT::i16; break;
1644 case 32: EVT = MVT::i32; break;
1646 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
1647 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1648 DAG.getValueType(EVT));
1651 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
1652 if (N1C && N0.getOpcode() == ISD::SRA) {
1653 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1654 unsigned Sum = N1C->getValue() + C1->getValue();
1655 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
1656 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
1657 DAG.getConstant(Sum, N1C->getValueType(0)));
1661 // Simplify, based on bits shifted out of the LHS.
1662 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
1663 return SDOperand(N, 0);
1666 // If the sign bit is known to be zero, switch this to a SRL.
1667 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
1668 return DAG.getNode(ISD::SRL, VT, N0, N1);
1672 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1673 SDOperand N0 = N->getOperand(0);
1674 SDOperand N1 = N->getOperand(1);
1675 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1676 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1677 MVT::ValueType VT = N0.getValueType();
1678 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1680 // fold (srl c1, c2) -> c1 >>u c2
1682 return DAG.getNode(ISD::SRL, VT, N0, N1);
1683 // fold (srl 0, x) -> 0
1684 if (N0C && N0C->isNullValue())
1686 // fold (srl x, c >= size(x)) -> undef
1687 if (N1C && N1C->getValue() >= OpSizeInBits)
1688 return DAG.getNode(ISD::UNDEF, VT);
1689 // fold (srl x, 0) -> x
1690 if (N1C && N1C->isNullValue())
1692 // if (srl x, c) is known to be zero, return 0
1693 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1694 return DAG.getConstant(0, VT);
1695 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1696 if (N1C && N0.getOpcode() == ISD::SRL &&
1697 N0.getOperand(1).getOpcode() == ISD::Constant) {
1698 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1699 uint64_t c2 = N1C->getValue();
1700 if (c1 + c2 > OpSizeInBits)
1701 return DAG.getConstant(0, VT);
1702 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1703 DAG.getConstant(c1 + c2, N1.getValueType()));
1706 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
1707 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1708 // Shifting in all undef bits?
1709 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
1710 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
1711 return DAG.getNode(ISD::UNDEF, VT);
1713 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
1714 AddToWorkList(SmallShift.Val);
1715 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
1718 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
1719 // bit, which is unmodified by sra.
1720 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
1721 if (N0.getOpcode() == ISD::SRA)
1722 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
1725 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
1726 if (N1C && N0.getOpcode() == ISD::CTLZ &&
1727 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
1728 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
1729 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
1731 // If any of the input bits are KnownOne, then the input couldn't be all
1732 // zeros, thus the result of the srl will always be zero.
1733 if (KnownOne) return DAG.getConstant(0, VT);
1735 // If all of the bits input the to ctlz node are known to be zero, then
1736 // the result of the ctlz is "32" and the result of the shift is one.
1737 uint64_t UnknownBits = ~KnownZero & Mask;
1738 if (UnknownBits == 0) return DAG.getConstant(1, VT);
1740 // Otherwise, check to see if there is exactly one bit input to the ctlz.
1741 if ((UnknownBits & (UnknownBits-1)) == 0) {
1742 // Okay, we know that only that the single bit specified by UnknownBits
1743 // could be set on input to the CTLZ node. If this bit is set, the SRL
1744 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
1745 // to an SRL,XOR pair, which is likely to simplify more.
1746 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
1747 SDOperand Op = N0.getOperand(0);
1749 Op = DAG.getNode(ISD::SRL, VT, Op,
1750 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
1751 AddToWorkList(Op.Val);
1753 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
1760 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1761 SDOperand N0 = N->getOperand(0);
1762 MVT::ValueType VT = N->getValueType(0);
1764 // fold (ctlz c1) -> c2
1765 if (isa<ConstantSDNode>(N0))
1766 return DAG.getNode(ISD::CTLZ, VT, N0);
1770 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1771 SDOperand N0 = N->getOperand(0);
1772 MVT::ValueType VT = N->getValueType(0);
1774 // fold (cttz c1) -> c2
1775 if (isa<ConstantSDNode>(N0))
1776 return DAG.getNode(ISD::CTTZ, VT, N0);
1780 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1781 SDOperand N0 = N->getOperand(0);
1782 MVT::ValueType VT = N->getValueType(0);
1784 // fold (ctpop c1) -> c2
1785 if (isa<ConstantSDNode>(N0))
1786 return DAG.getNode(ISD::CTPOP, VT, N0);
1790 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1791 SDOperand N0 = N->getOperand(0);
1792 SDOperand N1 = N->getOperand(1);
1793 SDOperand N2 = N->getOperand(2);
1794 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1795 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1796 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1797 MVT::ValueType VT = N->getValueType(0);
1799 // fold select C, X, X -> X
1802 // fold select true, X, Y -> X
1803 if (N0C && !N0C->isNullValue())
1805 // fold select false, X, Y -> Y
1806 if (N0C && N0C->isNullValue())
1808 // fold select C, 1, X -> C | X
1809 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1810 return DAG.getNode(ISD::OR, VT, N0, N2);
1811 // fold select C, 0, X -> ~C & X
1812 // FIXME: this should check for C type == X type, not i1?
1813 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1814 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1815 AddToWorkList(XORNode.Val);
1816 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1818 // fold select C, X, 1 -> ~C | X
1819 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1820 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1821 AddToWorkList(XORNode.Val);
1822 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1824 // fold select C, X, 0 -> C & X
1825 // FIXME: this should check for C type == X type, not i1?
1826 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1827 return DAG.getNode(ISD::AND, VT, N0, N1);
1828 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1829 if (MVT::i1 == VT && N0 == N1)
1830 return DAG.getNode(ISD::OR, VT, N0, N2);
1831 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1832 if (MVT::i1 == VT && N0 == N2)
1833 return DAG.getNode(ISD::AND, VT, N0, N1);
1835 // If we can fold this based on the true/false value, do so.
1836 if (SimplifySelectOps(N, N1, N2))
1837 return SDOperand(N, 0); // Don't revisit N.
1839 // fold selects based on a setcc into other things, such as min/max/abs
1840 if (N0.getOpcode() == ISD::SETCC)
1842 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1843 // having to say they don't support SELECT_CC on every type the DAG knows
1844 // about, since there is no way to mark an opcode illegal at all value types
1845 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1846 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1847 N1, N2, N0.getOperand(2));
1849 return SimplifySelect(N0, N1, N2);
1853 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1854 SDOperand N0 = N->getOperand(0);
1855 SDOperand N1 = N->getOperand(1);
1856 SDOperand N2 = N->getOperand(2);
1857 SDOperand N3 = N->getOperand(3);
1858 SDOperand N4 = N->getOperand(4);
1859 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1860 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1861 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1862 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1864 // fold select_cc lhs, rhs, x, x, cc -> x
1868 // Determine if the condition we're dealing with is constant
1869 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1870 if (SCC.Val) AddToWorkList(SCC.Val);
1872 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
1873 if (SCCC->getValue())
1874 return N2; // cond always true -> true val
1876 return N3; // cond always false -> false val
1879 // Fold to a simpler select_cc
1880 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
1881 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
1882 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
1885 // If we can fold this based on the true/false value, do so.
1886 if (SimplifySelectOps(N, N2, N3))
1887 return SDOperand(N, 0); // Don't revisit N.
1889 // fold select_cc into other things, such as min/max/abs
1890 return SimplifySelectCC(N0, N1, N2, N3, CC);
1893 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1894 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1895 cast<CondCodeSDNode>(N->getOperand(2))->get());
1898 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1899 SDOperand N0 = N->getOperand(0);
1900 MVT::ValueType VT = N->getValueType(0);
1902 // fold (sext c1) -> c1
1903 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
1904 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
1906 // fold (sext (sext x)) -> (sext x)
1907 // fold (sext (aext x)) -> (sext x)
1908 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1909 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1911 // fold (sext (truncate x)) -> (sextinreg x).
1912 if (N0.getOpcode() == ISD::TRUNCATE &&
1913 (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
1914 N0.getValueType()))) {
1915 SDOperand Op = N0.getOperand(0);
1916 if (Op.getValueType() < VT) {
1917 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
1918 } else if (Op.getValueType() > VT) {
1919 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
1921 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
1922 DAG.getValueType(N0.getValueType()));
1925 // fold (sext (load x)) -> (sext (truncate (sextload x)))
1926 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
1927 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
1928 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1929 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
1930 LN0->getBasePtr(), LN0->getSrcValue(),
1931 LN0->getSrcValueOffset(),
1933 CombineTo(N, ExtLoad);
1934 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1935 ExtLoad.getValue(1));
1936 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1939 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
1940 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
1941 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
1942 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1943 MVT::ValueType EVT = LN0->getLoadedVT();
1944 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
1945 LN0->getBasePtr(), LN0->getSrcValue(),
1946 LN0->getSrcValueOffset(), EVT);
1947 CombineTo(N, ExtLoad);
1948 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1949 ExtLoad.getValue(1));
1950 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1956 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1957 SDOperand N0 = N->getOperand(0);
1958 MVT::ValueType VT = N->getValueType(0);
1960 // fold (zext c1) -> c1
1961 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
1962 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1963 // fold (zext (zext x)) -> (zext x)
1964 // fold (zext (aext x)) -> (zext x)
1965 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1966 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1968 // fold (zext (truncate x)) -> (and x, mask)
1969 if (N0.getOpcode() == ISD::TRUNCATE &&
1970 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
1971 SDOperand Op = N0.getOperand(0);
1972 if (Op.getValueType() < VT) {
1973 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
1974 } else if (Op.getValueType() > VT) {
1975 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
1977 return DAG.getZeroExtendInReg(Op, N0.getValueType());
1980 // fold (zext (and (trunc x), cst)) -> (and x, cst).
1981 if (N0.getOpcode() == ISD::AND &&
1982 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
1983 N0.getOperand(1).getOpcode() == ISD::Constant) {
1984 SDOperand X = N0.getOperand(0).getOperand(0);
1985 if (X.getValueType() < VT) {
1986 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
1987 } else if (X.getValueType() > VT) {
1988 X = DAG.getNode(ISD::TRUNCATE, VT, X);
1990 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1991 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
1994 // fold (zext (load x)) -> (zext (truncate (zextload x)))
1995 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
1996 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
1997 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1998 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1999 LN0->getBasePtr(), LN0->getSrcValue(),
2000 LN0->getSrcValueOffset(),
2002 CombineTo(N, ExtLoad);
2003 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2004 ExtLoad.getValue(1));
2005 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2008 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
2009 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
2010 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
2011 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2012 MVT::ValueType EVT = LN0->getLoadedVT();
2013 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2014 LN0->getBasePtr(), LN0->getSrcValue(),
2015 LN0->getSrcValueOffset(), EVT);
2016 CombineTo(N, ExtLoad);
2017 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2018 ExtLoad.getValue(1));
2019 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2024 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
2025 SDOperand N0 = N->getOperand(0);
2026 MVT::ValueType VT = N->getValueType(0);
2028 // fold (aext c1) -> c1
2029 if (isa<ConstantSDNode>(N0))
2030 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
2031 // fold (aext (aext x)) -> (aext x)
2032 // fold (aext (zext x)) -> (zext x)
2033 // fold (aext (sext x)) -> (sext x)
2034 if (N0.getOpcode() == ISD::ANY_EXTEND ||
2035 N0.getOpcode() == ISD::ZERO_EXTEND ||
2036 N0.getOpcode() == ISD::SIGN_EXTEND)
2037 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2039 // fold (aext (truncate x))
2040 if (N0.getOpcode() == ISD::TRUNCATE) {
2041 SDOperand TruncOp = N0.getOperand(0);
2042 if (TruncOp.getValueType() == VT)
2043 return TruncOp; // x iff x size == zext size.
2044 if (TruncOp.getValueType() > VT)
2045 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
2046 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
2049 // fold (aext (and (trunc x), cst)) -> (and x, cst).
2050 if (N0.getOpcode() == ISD::AND &&
2051 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2052 N0.getOperand(1).getOpcode() == ISD::Constant) {
2053 SDOperand X = N0.getOperand(0).getOperand(0);
2054 if (X.getValueType() < VT) {
2055 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2056 } else if (X.getValueType() > VT) {
2057 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2059 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2060 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2063 // fold (aext (load x)) -> (aext (truncate (extload x)))
2064 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2065 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2066 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2067 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2068 LN0->getBasePtr(), LN0->getSrcValue(),
2069 LN0->getSrcValueOffset(),
2071 CombineTo(N, ExtLoad);
2072 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2073 ExtLoad.getValue(1));
2074 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2077 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2078 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2079 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2080 if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.Val) &&
2082 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2083 MVT::ValueType EVT = LN0->getLoadedVT();
2084 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2085 LN0->getChain(), LN0->getBasePtr(),
2087 LN0->getSrcValueOffset(), EVT);
2088 CombineTo(N, ExtLoad);
2089 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2090 ExtLoad.getValue(1));
2091 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2097 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
2098 SDOperand N0 = N->getOperand(0);
2099 SDOperand N1 = N->getOperand(1);
2100 MVT::ValueType VT = N->getValueType(0);
2101 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
2102 unsigned EVTBits = MVT::getSizeInBits(EVT);
2104 // fold (sext_in_reg c1) -> c1
2105 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
2106 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
2108 // If the input is already sign extended, just drop the extension.
2109 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
2112 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
2113 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2114 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
2115 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
2118 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
2119 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
2120 return DAG.getZeroExtendInReg(N0, EVT);
2122 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
2123 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
2124 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
2125 if (N0.getOpcode() == ISD::SRL) {
2126 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2127 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
2128 // We can turn this into an SRA iff the input to the SRL is already sign
2130 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0));
2131 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
2132 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
2136 // fold (sext_inreg (extload x)) -> (sextload x)
2137 if (ISD::isEXTLoad(N0.Val) &&
2138 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2139 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2140 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2141 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2142 LN0->getBasePtr(), LN0->getSrcValue(),
2143 LN0->getSrcValueOffset(), EVT);
2144 CombineTo(N, ExtLoad);
2145 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2146 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2148 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
2149 if (ISD::isZEXTLoad(N0.Val) && N0.hasOneUse() &&
2150 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2151 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2152 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2153 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2154 LN0->getBasePtr(), LN0->getSrcValue(),
2155 LN0->getSrcValueOffset(), EVT);
2156 CombineTo(N, ExtLoad);
2157 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2158 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2163 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
2164 SDOperand N0 = N->getOperand(0);
2165 MVT::ValueType VT = N->getValueType(0);
2168 if (N0.getValueType() == N->getValueType(0))
2170 // fold (truncate c1) -> c1
2171 if (isa<ConstantSDNode>(N0))
2172 return DAG.getNode(ISD::TRUNCATE, VT, N0);
2173 // fold (truncate (truncate x)) -> (truncate x)
2174 if (N0.getOpcode() == ISD::TRUNCATE)
2175 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2176 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
2177 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
2178 N0.getOpcode() == ISD::ANY_EXTEND) {
2179 if (N0.getValueType() < VT)
2180 // if the source is smaller than the dest, we still need an extend
2181 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2182 else if (N0.getValueType() > VT)
2183 // if the source is larger than the dest, than we just need the truncate
2184 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2186 // if the source and dest are the same type, we can drop both the extend
2188 return N0.getOperand(0);
2190 // fold (truncate (load x)) -> (smaller load x)
2191 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) {
2192 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
2193 "Cannot truncate to larger type!");
2194 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2195 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2196 // For big endian targets, we need to add an offset to the pointer to load
2197 // the correct bytes. For little endian systems, we merely need to read
2198 // fewer bytes from the same pointer.
2200 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
2201 SDOperand NewPtr = TLI.isLittleEndian() ? LN0->getBasePtr() :
2202 DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
2203 DAG.getConstant(PtrOff, PtrType));
2204 AddToWorkList(NewPtr.Val);
2205 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), NewPtr,
2206 LN0->getSrcValue(), LN0->getSrcValueOffset());
2208 CombineTo(N0.Val, Load, Load.getValue(1));
2209 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2214 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
2215 SDOperand N0 = N->getOperand(0);
2216 MVT::ValueType VT = N->getValueType(0);
2218 // If the input is a constant, let getNode() fold it.
2219 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
2220 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2221 if (Res.Val != N) return Res;
2224 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
2225 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
2227 // fold (conv (load x)) -> (load (conv*)x)
2228 // FIXME: These xforms need to know that the resultant load doesn't need a
2229 // higher alignment than the original!
2230 if (0 && ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) {
2231 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2232 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
2233 LN0->getSrcValue(), LN0->getSrcValueOffset());
2235 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
2243 SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) {
2244 SDOperand N0 = N->getOperand(0);
2245 MVT::ValueType VT = N->getValueType(0);
2247 // If the input is a VBUILD_VECTOR with all constant elements, fold this now.
2248 // First check to see if this is all constant.
2249 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() &&
2250 VT == MVT::Vector) {
2251 bool isSimple = true;
2252 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i)
2253 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
2254 N0.getOperand(i).getOpcode() != ISD::Constant &&
2255 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
2260 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT();
2261 if (isSimple && !MVT::isVector(DestEltVT)) {
2262 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT);
2269 /// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector
2270 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
2271 /// destination element value type.
2272 SDOperand DAGCombiner::
2273 ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
2274 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
2276 // If this is already the right type, we're done.
2277 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
2279 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
2280 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
2282 // If this is a conversion of N elements of one type to N elements of another
2283 // type, convert each element. This handles FP<->INT cases.
2284 if (SrcBitSize == DstBitSize) {
2285 SmallVector<SDOperand, 8> Ops;
2286 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2287 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
2288 AddToWorkList(Ops.back().Val);
2290 Ops.push_back(*(BV->op_end()-2)); // Add num elements.
2291 Ops.push_back(DAG.getValueType(DstEltVT));
2292 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2295 // Otherwise, we're growing or shrinking the elements. To avoid having to
2296 // handle annoying details of growing/shrinking FP values, we convert them to
2298 if (MVT::isFloatingPoint(SrcEltVT)) {
2299 // Convert the input float vector to a int vector where the elements are the
2301 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
2302 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2303 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val;
2307 // Now we know the input is an integer vector. If the output is a FP type,
2308 // convert to integer first, then to FP of the right size.
2309 if (MVT::isFloatingPoint(DstEltVT)) {
2310 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
2311 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2312 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val;
2314 // Next, convert to FP elements of the same size.
2315 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT);
2318 // Okay, we know the src/dst types are both integers of differing types.
2319 // Handling growing first.
2320 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
2321 if (SrcBitSize < DstBitSize) {
2322 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
2324 SmallVector<SDOperand, 8> Ops;
2325 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e;
2326 i += NumInputsPerOutput) {
2327 bool isLE = TLI.isLittleEndian();
2328 uint64_t NewBits = 0;
2329 bool EltIsUndef = true;
2330 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
2331 // Shift the previously computed bits over.
2332 NewBits <<= SrcBitSize;
2333 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
2334 if (Op.getOpcode() == ISD::UNDEF) continue;
2337 NewBits |= cast<ConstantSDNode>(Op)->getValue();
2341 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2343 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
2346 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2347 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2348 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2351 // Finally, this must be the case where we are shrinking elements: each input
2352 // turns into multiple outputs.
2353 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
2354 SmallVector<SDOperand, 8> Ops;
2355 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2356 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
2357 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
2358 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2361 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
2363 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
2364 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
2365 OpVal >>= DstBitSize;
2366 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
2369 // For big endian targets, swap the order of the pieces of each element.
2370 if (!TLI.isLittleEndian())
2371 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
2373 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2374 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2375 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2380 SDOperand DAGCombiner::visitFADD(SDNode *N) {
2381 SDOperand N0 = N->getOperand(0);
2382 SDOperand N1 = N->getOperand(1);
2383 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2384 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2385 MVT::ValueType VT = N->getValueType(0);
2387 // fold (fadd c1, c2) -> c1+c2
2389 return DAG.getNode(ISD::FADD, VT, N0, N1);
2390 // canonicalize constant to RHS
2391 if (N0CFP && !N1CFP)
2392 return DAG.getNode(ISD::FADD, VT, N1, N0);
2393 // fold (A + (-B)) -> A-B
2394 if (N1.getOpcode() == ISD::FNEG)
2395 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
2396 // fold ((-A) + B) -> B-A
2397 if (N0.getOpcode() == ISD::FNEG)
2398 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
2402 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
2403 SDOperand N0 = N->getOperand(0);
2404 SDOperand N1 = N->getOperand(1);
2405 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2406 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2407 MVT::ValueType VT = N->getValueType(0);
2409 // fold (fsub c1, c2) -> c1-c2
2411 return DAG.getNode(ISD::FSUB, VT, N0, N1);
2412 // fold (A-(-B)) -> A+B
2413 if (N1.getOpcode() == ISD::FNEG)
2414 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
2418 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
2419 SDOperand N0 = N->getOperand(0);
2420 SDOperand N1 = N->getOperand(1);
2421 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2422 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2423 MVT::ValueType VT = N->getValueType(0);
2425 // fold (fmul c1, c2) -> c1*c2
2427 return DAG.getNode(ISD::FMUL, VT, N0, N1);
2428 // canonicalize constant to RHS
2429 if (N0CFP && !N1CFP)
2430 return DAG.getNode(ISD::FMUL, VT, N1, N0);
2431 // fold (fmul X, 2.0) -> (fadd X, X)
2432 if (N1CFP && N1CFP->isExactlyValue(+2.0))
2433 return DAG.getNode(ISD::FADD, VT, N0, N0);
2437 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
2438 SDOperand N0 = N->getOperand(0);
2439 SDOperand N1 = N->getOperand(1);
2440 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2441 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2442 MVT::ValueType VT = N->getValueType(0);
2444 // fold (fdiv c1, c2) -> c1/c2
2446 return DAG.getNode(ISD::FDIV, VT, N0, N1);
2450 SDOperand DAGCombiner::visitFREM(SDNode *N) {
2451 SDOperand N0 = N->getOperand(0);
2452 SDOperand N1 = N->getOperand(1);
2453 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2454 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2455 MVT::ValueType VT = N->getValueType(0);
2457 // fold (frem c1, c2) -> fmod(c1,c2)
2459 return DAG.getNode(ISD::FREM, VT, N0, N1);
2463 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
2464 SDOperand N0 = N->getOperand(0);
2465 SDOperand N1 = N->getOperand(1);
2466 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2467 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2468 MVT::ValueType VT = N->getValueType(0);
2470 if (N0CFP && N1CFP) // Constant fold
2471 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
2474 // copysign(x, c1) -> fabs(x) iff ispos(c1)
2475 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
2480 u.d = N1CFP->getValue();
2482 return DAG.getNode(ISD::FABS, VT, N0);
2484 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
2487 // copysign(fabs(x), y) -> copysign(x, y)
2488 // copysign(fneg(x), y) -> copysign(x, y)
2489 // copysign(copysign(x,z), y) -> copysign(x, y)
2490 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
2491 N0.getOpcode() == ISD::FCOPYSIGN)
2492 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
2494 // copysign(x, abs(y)) -> abs(x)
2495 if (N1.getOpcode() == ISD::FABS)
2496 return DAG.getNode(ISD::FABS, VT, N0);
2498 // copysign(x, copysign(y,z)) -> copysign(x, z)
2499 if (N1.getOpcode() == ISD::FCOPYSIGN)
2500 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
2502 // copysign(x, fp_extend(y)) -> copysign(x, y)
2503 // copysign(x, fp_round(y)) -> copysign(x, y)
2504 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
2505 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
2512 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
2513 SDOperand N0 = N->getOperand(0);
2514 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2515 MVT::ValueType VT = N->getValueType(0);
2517 // fold (sint_to_fp c1) -> c1fp
2519 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
2523 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
2524 SDOperand N0 = N->getOperand(0);
2525 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2526 MVT::ValueType VT = N->getValueType(0);
2528 // fold (uint_to_fp c1) -> c1fp
2530 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
2534 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
2535 SDOperand N0 = N->getOperand(0);
2536 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2537 MVT::ValueType VT = N->getValueType(0);
2539 // fold (fp_to_sint c1fp) -> c1
2541 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
2545 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
2546 SDOperand N0 = N->getOperand(0);
2547 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2548 MVT::ValueType VT = N->getValueType(0);
2550 // fold (fp_to_uint c1fp) -> c1
2552 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
2556 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
2557 SDOperand N0 = N->getOperand(0);
2558 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2559 MVT::ValueType VT = N->getValueType(0);
2561 // fold (fp_round c1fp) -> c1fp
2563 return DAG.getNode(ISD::FP_ROUND, VT, N0);
2565 // fold (fp_round (fp_extend x)) -> x
2566 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
2567 return N0.getOperand(0);
2569 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
2570 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
2571 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
2572 AddToWorkList(Tmp.Val);
2573 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
2579 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
2580 SDOperand N0 = N->getOperand(0);
2581 MVT::ValueType VT = N->getValueType(0);
2582 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2583 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2585 // fold (fp_round_inreg c1fp) -> c1fp
2587 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
2588 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
2593 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
2594 SDOperand N0 = N->getOperand(0);
2595 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2596 MVT::ValueType VT = N->getValueType(0);
2598 // fold (fp_extend c1fp) -> c1fp
2600 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
2602 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
2603 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2604 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2605 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2606 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2607 LN0->getBasePtr(), LN0->getSrcValue(),
2608 LN0->getSrcValueOffset(),
2610 CombineTo(N, ExtLoad);
2611 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
2612 ExtLoad.getValue(1));
2613 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2620 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
2621 SDOperand N0 = N->getOperand(0);
2622 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2623 MVT::ValueType VT = N->getValueType(0);
2625 // fold (fneg c1) -> -c1
2627 return DAG.getNode(ISD::FNEG, VT, N0);
2628 // fold (fneg (sub x, y)) -> (sub y, x)
2629 if (N0.getOpcode() == ISD::SUB)
2630 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0));
2631 // fold (fneg (fneg x)) -> x
2632 if (N0.getOpcode() == ISD::FNEG)
2633 return N0.getOperand(0);
2637 SDOperand DAGCombiner::visitFABS(SDNode *N) {
2638 SDOperand N0 = N->getOperand(0);
2639 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2640 MVT::ValueType VT = N->getValueType(0);
2642 // fold (fabs c1) -> fabs(c1)
2644 return DAG.getNode(ISD::FABS, VT, N0);
2645 // fold (fabs (fabs x)) -> (fabs x)
2646 if (N0.getOpcode() == ISD::FABS)
2647 return N->getOperand(0);
2648 // fold (fabs (fneg x)) -> (fabs x)
2649 // fold (fabs (fcopysign x, y)) -> (fabs x)
2650 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
2651 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
2656 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
2657 SDOperand Chain = N->getOperand(0);
2658 SDOperand N1 = N->getOperand(1);
2659 SDOperand N2 = N->getOperand(2);
2660 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2662 // never taken branch, fold to chain
2663 if (N1C && N1C->isNullValue())
2665 // unconditional branch
2666 if (N1C && N1C->getValue() == 1)
2667 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2668 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
2670 if (N1.getOpcode() == ISD::SETCC &&
2671 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
2672 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
2673 N1.getOperand(0), N1.getOperand(1), N2);
2678 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
2680 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
2681 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2682 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2684 // Use SimplifySetCC to simplify SETCC's.
2685 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2686 if (Simp.Val) AddToWorkList(Simp.Val);
2688 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2690 // fold br_cc true, dest -> br dest (unconditional branch)
2691 if (SCCC && SCCC->getValue())
2692 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2694 // fold br_cc false, dest -> unconditional fall through
2695 if (SCCC && SCCC->isNullValue())
2696 return N->getOperand(0);
2698 // fold to a simpler setcc
2699 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2700 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2701 Simp.getOperand(2), Simp.getOperand(0),
2702 Simp.getOperand(1), N->getOperand(4));
2706 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
2707 LoadSDNode *LD = cast<LoadSDNode>(N);
2708 SDOperand Chain = LD->getChain();
2709 SDOperand Ptr = LD->getBasePtr();
2711 // If there are no uses of the loaded value, change uses of the chain value
2712 // into uses of the chain input (i.e. delete the dead load).
2713 if (N->hasNUsesOfValue(0, 0))
2714 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
2716 // If this load is directly stored, replace the load value with the stored
2718 // TODO: Handle store large -> read small portion.
2719 // TODO: Handle TRUNCSTORE/LOADEXT
2720 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
2721 if (ISD::isNON_TRUNCStore(Chain.Val)) {
2722 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
2723 if (PrevST->getBasePtr() == Ptr &&
2724 PrevST->getValue().getValueType() == N->getValueType(0))
2725 return CombineTo(N, Chain.getOperand(1), Chain);
2730 // Walk up chain skipping non-aliasing memory nodes.
2731 SDOperand BetterChain = FindBetterChain(N, Chain);
2733 // If there is a better chain.
2734 if (Chain != BetterChain) {
2737 // Replace the chain to void dependency.
2738 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
2739 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
2740 LD->getSrcValue(), LD->getSrcValueOffset());
2742 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
2743 LD->getValueType(0),
2744 BetterChain, Ptr, LD->getSrcValue(),
2745 LD->getSrcValueOffset(),
2749 // Create token factor to keep old chain connected.
2750 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
2751 Chain, ReplLoad.getValue(1));
2753 // Replace uses with load result and token factor. Don't add users
2755 return CombineTo(N, ReplLoad.getValue(0), Token, false);
2762 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
2763 StoreSDNode *ST = cast<StoreSDNode>(N);
2764 SDOperand Chain = ST->getChain();
2765 SDOperand Value = ST->getValue();
2766 SDOperand Ptr = ST->getBasePtr();
2768 // If this is a store of a bit convert, store the input value.
2769 // FIXME: This needs to know that the resultant store does not need a
2770 // higher alignment than the original.
2771 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) {
2772 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
2773 ST->getSrcValueOffset());
2777 // Walk up chain skipping non-aliasing memory nodes.
2778 SDOperand BetterChain = FindBetterChain(N, Chain);
2780 // If there is a better chain.
2781 if (Chain != BetterChain) {
2782 // Replace the chain to avoid dependency.
2783 SDOperand ReplStore;
2784 if (ST->isTruncatingStore()) {
2785 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
2786 ST->getSrcValue(),ST->getSrcValueOffset(), ST->getStoredVT());
2788 ReplStore = DAG.getStore(BetterChain, Value, Ptr,
2789 ST->getSrcValue(), ST->getSrcValueOffset());
2792 // Create token to keep both nodes around.
2794 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
2796 // Don't add users to work list.
2797 return CombineTo(N, Token, false);
2804 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
2805 SDOperand InVec = N->getOperand(0);
2806 SDOperand InVal = N->getOperand(1);
2807 SDOperand EltNo = N->getOperand(2);
2809 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
2810 // vector with the inserted element.
2811 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2812 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2813 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2814 if (Elt < Ops.size())
2816 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
2817 &Ops[0], Ops.size());
2823 SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
2824 SDOperand InVec = N->getOperand(0);
2825 SDOperand InVal = N->getOperand(1);
2826 SDOperand EltNo = N->getOperand(2);
2827 SDOperand NumElts = N->getOperand(3);
2828 SDOperand EltType = N->getOperand(4);
2830 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new
2831 // vector with the inserted element.
2832 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2833 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2834 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2835 if (Elt < Ops.size()-2)
2837 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(),
2838 &Ops[0], Ops.size());
2844 SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
2845 unsigned NumInScalars = N->getNumOperands()-2;
2846 SDOperand NumElts = N->getOperand(NumInScalars);
2847 SDOperand EltType = N->getOperand(NumInScalars+1);
2849 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT
2850 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most
2851 // two distinct vectors, turn this into a shuffle node.
2852 SDOperand VecIn1, VecIn2;
2853 for (unsigned i = 0; i != NumInScalars; ++i) {
2854 // Ignore undef inputs.
2855 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
2857 // If this input is something other than a VEXTRACT_VECTOR_ELT with a
2858 // constant index, bail out.
2859 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT ||
2860 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
2861 VecIn1 = VecIn2 = SDOperand(0, 0);
2865 // If the input vector type disagrees with the result of the vbuild_vector,
2866 // we can't make a shuffle.
2867 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
2868 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts ||
2869 *(ExtractedFromVec.Val->op_end()-1) != EltType) {
2870 VecIn1 = VecIn2 = SDOperand(0, 0);
2874 // Otherwise, remember this. We allow up to two distinct input vectors.
2875 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
2878 if (VecIn1.Val == 0) {
2879 VecIn1 = ExtractedFromVec;
2880 } else if (VecIn2.Val == 0) {
2881 VecIn2 = ExtractedFromVec;
2884 VecIn1 = VecIn2 = SDOperand(0, 0);
2889 // If everything is good, we can make a shuffle operation.
2891 SmallVector<SDOperand, 8> BuildVecIndices;
2892 for (unsigned i = 0; i != NumInScalars; ++i) {
2893 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
2894 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
2898 SDOperand Extract = N->getOperand(i);
2900 // If extracting from the first vector, just use the index directly.
2901 if (Extract.getOperand(0) == VecIn1) {
2902 BuildVecIndices.push_back(Extract.getOperand(1));
2906 // Otherwise, use InIdx + VecSize
2907 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
2908 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32));
2911 // Add count and size info.
2912 BuildVecIndices.push_back(NumElts);
2913 BuildVecIndices.push_back(DAG.getValueType(MVT::i32));
2915 // Return the new VVECTOR_SHUFFLE node.
2921 // Use an undef vbuild_vector as input for the second operand.
2922 std::vector<SDOperand> UnOps(NumInScalars,
2923 DAG.getNode(ISD::UNDEF,
2924 cast<VTSDNode>(EltType)->getVT()));
2925 UnOps.push_back(NumElts);
2926 UnOps.push_back(EltType);
2927 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
2928 &UnOps[0], UnOps.size());
2929 AddToWorkList(Ops[1].Val);
2931 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
2932 &BuildVecIndices[0], BuildVecIndices.size());
2935 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5);
2941 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
2942 SDOperand ShufMask = N->getOperand(2);
2943 unsigned NumElts = ShufMask.getNumOperands();
2945 // If the shuffle mask is an identity operation on the LHS, return the LHS.
2946 bool isIdentity = true;
2947 for (unsigned i = 0; i != NumElts; ++i) {
2948 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2949 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
2954 if (isIdentity) return N->getOperand(0);
2956 // If the shuffle mask is an identity operation on the RHS, return the RHS.
2958 for (unsigned i = 0; i != NumElts; ++i) {
2959 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2960 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
2965 if (isIdentity) return N->getOperand(1);
2967 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
2969 bool isUnary = true;
2970 bool isSplat = true;
2972 unsigned BaseIdx = 0;
2973 for (unsigned i = 0; i != NumElts; ++i)
2974 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
2975 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
2976 int V = (Idx < NumElts) ? 0 : 1;
2990 SDOperand N0 = N->getOperand(0);
2991 SDOperand N1 = N->getOperand(1);
2992 // Normalize unary shuffle so the RHS is undef.
2993 if (isUnary && VecNum == 1)
2996 // If it is a splat, check if the argument vector is a build_vector with
2997 // all scalar elements the same.
3000 if (V->getOpcode() == ISD::BIT_CONVERT)
3001 V = V->getOperand(0).Val;
3002 if (V->getOpcode() == ISD::BUILD_VECTOR) {
3003 unsigned NumElems = V->getNumOperands()-2;
3004 if (NumElems > BaseIdx) {
3006 bool AllSame = true;
3007 for (unsigned i = 0; i != NumElems; ++i) {
3008 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3009 Base = V->getOperand(i);
3013 // Splat of <u, u, u, u>, return <u, u, u, u>
3016 for (unsigned i = 0; i != NumElems; ++i) {
3017 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3018 V->getOperand(i) != Base) {
3023 // Splat of <x, x, x, x>, return <x, x, x, x>
3030 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3032 if (isUnary || N0 == N1) {
3033 if (N0.getOpcode() == ISD::UNDEF)
3034 return DAG.getNode(ISD::UNDEF, N->getValueType(0));
3035 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3037 SmallVector<SDOperand, 8> MappedOps;
3038 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
3039 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3040 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3041 MappedOps.push_back(ShufMask.getOperand(i));
3044 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3045 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3048 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
3049 &MappedOps[0], MappedOps.size());
3050 AddToWorkList(ShufMask.Val);
3051 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
3053 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
3060 SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
3061 SDOperand ShufMask = N->getOperand(2);
3062 unsigned NumElts = ShufMask.getNumOperands()-2;
3064 // If the shuffle mask is an identity operation on the LHS, return the LHS.
3065 bool isIdentity = true;
3066 for (unsigned i = 0; i != NumElts; ++i) {
3067 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3068 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
3073 if (isIdentity) return N->getOperand(0);
3075 // If the shuffle mask is an identity operation on the RHS, return the RHS.
3077 for (unsigned i = 0; i != NumElts; ++i) {
3078 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3079 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
3084 if (isIdentity) return N->getOperand(1);
3086 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
3088 bool isUnary = true;
3089 bool isSplat = true;
3091 unsigned BaseIdx = 0;
3092 for (unsigned i = 0; i != NumElts; ++i)
3093 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
3094 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
3095 int V = (Idx < NumElts) ? 0 : 1;
3109 SDOperand N0 = N->getOperand(0);
3110 SDOperand N1 = N->getOperand(1);
3111 // Normalize unary shuffle so the RHS is undef.
3112 if (isUnary && VecNum == 1)
3115 // If it is a splat, check if the argument vector is a build_vector with
3116 // all scalar elements the same.
3120 // If this is a vbit convert that changes the element type of the vector but
3121 // not the number of vector elements, look through it. Be careful not to
3122 // look though conversions that change things like v4f32 to v2f64.
3123 if (V->getOpcode() == ISD::VBIT_CONVERT) {
3124 SDOperand ConvInput = V->getOperand(0);
3125 if (ConvInput.getValueType() == MVT::Vector &&
3127 ConvInput.getConstantOperandVal(ConvInput.getNumOperands()-2))
3131 if (V->getOpcode() == ISD::VBUILD_VECTOR) {
3132 unsigned NumElems = V->getNumOperands()-2;
3133 if (NumElems > BaseIdx) {
3135 bool AllSame = true;
3136 for (unsigned i = 0; i != NumElems; ++i) {
3137 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3138 Base = V->getOperand(i);
3142 // Splat of <u, u, u, u>, return <u, u, u, u>
3145 for (unsigned i = 0; i != NumElems; ++i) {
3146 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3147 V->getOperand(i) != Base) {
3152 // Splat of <x, x, x, x>, return <x, x, x, x>
3159 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3161 if (isUnary || N0 == N1) {
3162 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3164 SmallVector<SDOperand, 8> MappedOps;
3165 for (unsigned i = 0; i != NumElts; ++i) {
3166 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3167 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3168 MappedOps.push_back(ShufMask.getOperand(i));
3171 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3172 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3175 // Add the type/#elts values.
3176 MappedOps.push_back(ShufMask.getOperand(NumElts));
3177 MappedOps.push_back(ShufMask.getOperand(NumElts+1));
3179 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(),
3180 &MappedOps[0], MappedOps.size());
3181 AddToWorkList(ShufMask.Val);
3183 // Build the undef vector.
3184 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType());
3185 for (unsigned i = 0; i != NumElts; ++i)
3186 MappedOps[i] = UDVal;
3187 MappedOps[NumElts ] = *(N0.Val->op_end()-2);
3188 MappedOps[NumElts+1] = *(N0.Val->op_end()-1);
3189 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3190 &MappedOps[0], MappedOps.size());
3192 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3193 N0, UDVal, ShufMask,
3194 MappedOps[NumElts], MappedOps[NumElts+1]);
3200 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
3201 /// a VAND to a vector_shuffle with the destination vector and a zero vector.
3202 /// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
3203 /// vector_shuffle V, Zero, <0, 4, 2, 4>
3204 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
3205 SDOperand LHS = N->getOperand(0);
3206 SDOperand RHS = N->getOperand(1);
3207 if (N->getOpcode() == ISD::VAND) {
3208 SDOperand DstVecSize = *(LHS.Val->op_end()-2);
3209 SDOperand DstVecEVT = *(LHS.Val->op_end()-1);
3210 if (RHS.getOpcode() == ISD::VBIT_CONVERT)
3211 RHS = RHS.getOperand(0);
3212 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3213 std::vector<SDOperand> IdxOps;
3214 unsigned NumOps = RHS.getNumOperands();
3215 unsigned NumElts = NumOps-2;
3216 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT();
3217 for (unsigned i = 0; i != NumElts; ++i) {
3218 SDOperand Elt = RHS.getOperand(i);
3219 if (!isa<ConstantSDNode>(Elt))
3221 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
3222 IdxOps.push_back(DAG.getConstant(i, EVT));
3223 else if (cast<ConstantSDNode>(Elt)->isNullValue())
3224 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
3229 // Let's see if the target supports this vector_shuffle.
3230 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
3233 // Return the new VVECTOR_SHUFFLE node.
3234 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32);
3235 SDOperand EVTNode = DAG.getValueType(EVT);
3236 std::vector<SDOperand> Ops;
3237 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode,
3240 AddToWorkList(LHS.Val);
3241 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
3242 ZeroOps.push_back(NumEltsNode);
3243 ZeroOps.push_back(EVTNode);
3244 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3245 &ZeroOps[0], ZeroOps.size()));
3246 IdxOps.push_back(NumEltsNode);
3247 IdxOps.push_back(EVTNode);
3248 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3249 &IdxOps[0], IdxOps.size()));
3250 Ops.push_back(NumEltsNode);
3251 Ops.push_back(EVTNode);
3252 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3253 &Ops[0], Ops.size());
3254 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) {
3255 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
3256 DstVecSize, DstVecEVT);
3264 /// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates
3265 /// the scalar operation of the vop if it is operating on an integer vector
3266 /// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD).
3267 SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
3268 ISD::NodeType FPOp) {
3269 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT();
3270 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp;
3271 SDOperand LHS = N->getOperand(0);
3272 SDOperand RHS = N->getOperand(1);
3273 SDOperand Shuffle = XformToShuffleWithZero(N);
3274 if (Shuffle.Val) return Shuffle;
3276 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold
3278 if (LHS.getOpcode() == ISD::VBUILD_VECTOR &&
3279 RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3280 SmallVector<SDOperand, 8> Ops;
3281 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
3282 SDOperand LHSOp = LHS.getOperand(i);
3283 SDOperand RHSOp = RHS.getOperand(i);
3284 // If these two elements can't be folded, bail out.
3285 if ((LHSOp.getOpcode() != ISD::UNDEF &&
3286 LHSOp.getOpcode() != ISD::Constant &&
3287 LHSOp.getOpcode() != ISD::ConstantFP) ||
3288 (RHSOp.getOpcode() != ISD::UNDEF &&
3289 RHSOp.getOpcode() != ISD::Constant &&
3290 RHSOp.getOpcode() != ISD::ConstantFP))
3292 // Can't fold divide by zero.
3293 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) {
3294 if ((RHSOp.getOpcode() == ISD::Constant &&
3295 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
3296 (RHSOp.getOpcode() == ISD::ConstantFP &&
3297 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue()))
3300 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
3301 AddToWorkList(Ops.back().Val);
3302 assert((Ops.back().getOpcode() == ISD::UNDEF ||
3303 Ops.back().getOpcode() == ISD::Constant ||
3304 Ops.back().getOpcode() == ISD::ConstantFP) &&
3305 "Scalar binop didn't fold!");
3308 if (Ops.size() == LHS.getNumOperands()-2) {
3309 Ops.push_back(*(LHS.Val->op_end()-2));
3310 Ops.push_back(*(LHS.Val->op_end()-1));
3311 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
3318 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
3319 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
3321 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
3322 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3323 // If we got a simplified select_cc node back from SimplifySelectCC, then
3324 // break it down into a new SETCC node, and a new SELECT node, and then return
3325 // the SELECT node, since we were called with a SELECT node.
3327 // Check to see if we got a select_cc back (to turn into setcc/select).
3328 // Otherwise, just return whatever node we got back, like fabs.
3329 if (SCC.getOpcode() == ISD::SELECT_CC) {
3330 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
3331 SCC.getOperand(0), SCC.getOperand(1),
3333 AddToWorkList(SETCC.Val);
3334 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
3335 SCC.getOperand(3), SETCC);
3342 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
3343 /// are the two values being selected between, see if we can simplify the
3344 /// select. Callers of this should assume that TheSelect is deleted if this
3345 /// returns true. As such, they should return the appropriate thing (e.g. the
3346 /// node) back to the top-level of the DAG combiner loop to avoid it being
3349 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
3352 // If this is a select from two identical things, try to pull the operation
3353 // through the select.
3354 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
3355 // If this is a load and the token chain is identical, replace the select
3356 // of two loads with a load through a select of the address to load from.
3357 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
3358 // constants have been dropped into the constant pool.
3359 if (LHS.getOpcode() == ISD::LOAD &&
3360 // Token chains must be identical.
3361 LHS.getOperand(0) == RHS.getOperand(0)) {
3362 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
3363 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
3365 // If this is an EXTLOAD, the VT's must match.
3366 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
3367 // FIXME: this conflates two src values, discarding one. This is not
3368 // the right thing to do, but nothing uses srcvalues now. When they do,
3369 // turn SrcValue into a list of locations.
3371 if (TheSelect->getOpcode() == ISD::SELECT)
3372 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
3373 TheSelect->getOperand(0), LLD->getBasePtr(),
3376 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
3377 TheSelect->getOperand(0),
3378 TheSelect->getOperand(1),
3379 LLD->getBasePtr(), RLD->getBasePtr(),
3380 TheSelect->getOperand(4));
3383 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
3384 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
3385 Addr,LLD->getSrcValue(), LLD->getSrcValueOffset());
3387 Load = DAG.getExtLoad(LLD->getExtensionType(),
3388 TheSelect->getValueType(0),
3389 LLD->getChain(), Addr, LLD->getSrcValue(),
3390 LLD->getSrcValueOffset(),
3391 LLD->getLoadedVT());
3393 // Users of the select now use the result of the load.
3394 CombineTo(TheSelect, Load);
3396 // Users of the old loads now use the new load's chain. We know the
3397 // old-load value is dead now.
3398 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
3399 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
3408 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
3409 SDOperand N2, SDOperand N3,
3412 MVT::ValueType VT = N2.getValueType();
3413 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
3414 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
3415 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
3417 // Determine if the condition we're dealing with is constant
3418 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
3419 if (SCC.Val) AddToWorkList(SCC.Val);
3420 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
3422 // fold select_cc true, x, y -> x
3423 if (SCCC && SCCC->getValue())
3425 // fold select_cc false, x, y -> y
3426 if (SCCC && SCCC->getValue() == 0)
3429 // Check to see if we can simplify the select into an fabs node
3430 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
3431 // Allow either -0.0 or 0.0
3432 if (CFP->getValue() == 0.0) {
3433 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
3434 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
3435 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
3436 N2 == N3.getOperand(0))
3437 return DAG.getNode(ISD::FABS, VT, N0);
3439 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
3440 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
3441 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
3442 N2.getOperand(0) == N3)
3443 return DAG.getNode(ISD::FABS, VT, N3);
3447 // Check to see if we can perform the "gzip trick", transforming
3448 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
3449 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
3450 MVT::isInteger(N0.getValueType()) &&
3451 MVT::isInteger(N2.getValueType()) &&
3452 (N1C->isNullValue() || // (a < 0) ? b : 0
3453 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
3454 MVT::ValueType XType = N0.getValueType();
3455 MVT::ValueType AType = N2.getValueType();
3456 if (XType >= AType) {
3457 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
3458 // single-bit constant.
3459 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
3460 unsigned ShCtV = Log2_64(N2C->getValue());
3461 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
3462 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
3463 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
3464 AddToWorkList(Shift.Val);
3465 if (XType > AType) {
3466 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3467 AddToWorkList(Shift.Val);
3469 return DAG.getNode(ISD::AND, AType, Shift, N2);
3471 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3472 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3473 TLI.getShiftAmountTy()));
3474 AddToWorkList(Shift.Val);
3475 if (XType > AType) {
3476 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3477 AddToWorkList(Shift.Val);
3479 return DAG.getNode(ISD::AND, AType, Shift, N2);
3483 // fold select C, 16, 0 -> shl C, 4
3484 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
3485 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
3486 // Get a SetCC of the condition
3487 // FIXME: Should probably make sure that setcc is legal if we ever have a
3488 // target where it isn't.
3489 SDOperand Temp, SCC;
3490 // cast from setcc result type to select result type
3491 if (AfterLegalize) {
3492 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3493 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
3495 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
3496 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
3498 AddToWorkList(SCC.Val);
3499 AddToWorkList(Temp.Val);
3500 // shl setcc result by log2 n2c
3501 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
3502 DAG.getConstant(Log2_64(N2C->getValue()),
3503 TLI.getShiftAmountTy()));
3506 // Check to see if this is the equivalent of setcc
3507 // FIXME: Turn all of these into setcc if setcc if setcc is legal
3508 // otherwise, go ahead with the folds.
3509 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
3510 MVT::ValueType XType = N0.getValueType();
3511 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
3512 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3513 if (Res.getValueType() != VT)
3514 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
3518 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
3519 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
3520 TLI.isOperationLegal(ISD::CTLZ, XType)) {
3521 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
3522 return DAG.getNode(ISD::SRL, XType, Ctlz,
3523 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
3524 TLI.getShiftAmountTy()));
3526 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
3527 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
3528 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
3530 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
3531 DAG.getConstant(~0ULL, XType));
3532 return DAG.getNode(ISD::SRL, XType,
3533 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
3534 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3535 TLI.getShiftAmountTy()));
3537 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
3538 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
3539 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
3540 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3541 TLI.getShiftAmountTy()));
3542 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
3546 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
3547 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
3548 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
3549 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
3550 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
3551 MVT::ValueType XType = N0.getValueType();
3552 if (SubC->isNullValue() && MVT::isInteger(XType)) {
3553 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3554 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3555 TLI.getShiftAmountTy()));
3556 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
3557 AddToWorkList(Shift.Val);
3558 AddToWorkList(Add.Val);
3559 return DAG.getNode(ISD::XOR, XType, Add, Shift);
3567 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
3568 SDOperand N1, ISD::CondCode Cond,
3569 bool foldBooleans) {
3570 // These setcc operations always fold.
3574 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
3576 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
3579 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
3580 uint64_t C1 = N1C->getValue();
3581 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
3582 return DAG.FoldSetCC(VT, N0, N1, Cond);
3584 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
3585 // equality comparison, then we're just comparing whether X itself is
3587 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
3588 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
3589 N0.getOperand(1).getOpcode() == ISD::Constant) {
3590 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
3591 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3592 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) {
3593 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
3594 // (srl (ctlz x), 5) == 0 -> X != 0
3595 // (srl (ctlz x), 5) != 1 -> X != 0
3598 // (srl (ctlz x), 5) != 0 -> X == 0
3599 // (srl (ctlz x), 5) == 1 -> X == 0
3602 SDOperand Zero = DAG.getConstant(0, N0.getValueType());
3603 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
3608 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
3609 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
3610 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
3612 // If the comparison constant has bits in the upper part, the
3613 // zero-extended value could never match.
3614 if (C1 & (~0ULL << InSize)) {
3615 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
3619 case ISD::SETEQ: return DAG.getConstant(0, VT);
3622 case ISD::SETNE: return DAG.getConstant(1, VT);
3625 // True if the sign bit of C1 is set.
3626 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
3629 // True if the sign bit of C1 isn't set.
3630 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
3636 // Otherwise, we can perform the comparison with the low bits.
3644 return DAG.getSetCC(VT, N0.getOperand(0),
3645 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
3648 break; // todo, be more careful with signed comparisons
3650 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3651 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3652 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
3653 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
3654 MVT::ValueType ExtDstTy = N0.getValueType();
3655 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
3657 // If the extended part has any inconsistent bits, it cannot ever
3658 // compare equal. In other words, they have to be all ones or all
3661 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
3662 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
3663 return DAG.getConstant(Cond == ISD::SETNE, VT);
3666 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
3667 if (Op0Ty == ExtSrcTy) {
3668 ZextOp = N0.getOperand(0);
3670 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
3671 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
3672 DAG.getConstant(Imm, Op0Ty));
3674 AddToWorkList(ZextOp.Val);
3675 // Otherwise, make this a use of a zext.
3676 return DAG.getSetCC(VT, ZextOp,
3677 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
3680 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
3681 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3683 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
3684 if (N0.getOpcode() == ISD::SETCC) {
3685 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1);
3689 // Invert the condition.
3690 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
3691 CC = ISD::getSetCCInverse(CC,
3692 MVT::isInteger(N0.getOperand(0).getValueType()));
3693 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC);
3696 if ((N0.getOpcode() == ISD::XOR ||
3697 (N0.getOpcode() == ISD::AND &&
3698 N0.getOperand(0).getOpcode() == ISD::XOR &&
3699 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
3700 isa<ConstantSDNode>(N0.getOperand(1)) &&
3701 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
3702 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
3703 // can only do this if the top bits are known zero.
3704 if (TLI.MaskedValueIsZero(N0,
3705 MVT::getIntVTBitMask(N0.getValueType())-1)){
3706 // Okay, get the un-inverted input value.
3708 if (N0.getOpcode() == ISD::XOR)
3709 Val = N0.getOperand(0);
3711 assert(N0.getOpcode() == ISD::AND &&
3712 N0.getOperand(0).getOpcode() == ISD::XOR);
3713 // ((X^1)&1)^1 -> X & 1
3714 Val = DAG.getNode(ISD::AND, N0.getValueType(),
3715 N0.getOperand(0).getOperand(0),
3718 return DAG.getSetCC(VT, Val, N1,
3719 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3724 uint64_t MinVal, MaxVal;
3725 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
3726 if (ISD::isSignedIntSetCC(Cond)) {
3727 MinVal = 1ULL << (OperandBitSize-1);
3728 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
3729 MaxVal = ~0ULL >> (65-OperandBitSize);
3734 MaxVal = ~0ULL >> (64-OperandBitSize);
3737 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
3738 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
3739 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
3740 --C1; // X >= C0 --> X > (C0-1)
3741 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3742 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
3745 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
3746 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
3747 ++C1; // X <= C0 --> X < (C0+1)
3748 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3749 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
3752 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
3753 return DAG.getConstant(0, VT); // X < MIN --> false
3755 // Canonicalize setgt X, Min --> setne X, Min
3756 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
3757 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3758 // Canonicalize setlt X, Max --> setne X, Max
3759 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
3760 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3762 // If we have setult X, 1, turn it into seteq X, 0
3763 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
3764 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
3766 // If we have setugt X, Max-1, turn it into seteq X, Max
3767 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
3768 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
3771 // If we have "setcc X, C0", check to see if we can shrink the immediate
3774 // SETUGT X, SINTMAX -> SETLT X, 0
3775 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
3776 C1 == (~0ULL >> (65-OperandBitSize)))
3777 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
3780 // FIXME: Implement the rest of these.
3782 // Fold bit comparisons when we can.
3783 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3784 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
3785 if (ConstantSDNode *AndRHS =
3786 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3787 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
3788 // Perform the xform if the AND RHS is a single bit.
3789 if (isPowerOf2_64(AndRHS->getValue())) {
3790 return DAG.getNode(ISD::SRL, VT, N0,
3791 DAG.getConstant(Log2_64(AndRHS->getValue()),
3792 TLI.getShiftAmountTy()));
3794 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
3795 // (X & 8) == 8 --> (X & 8) >> 3
3796 // Perform the xform if C1 is a single bit.
3797 if (isPowerOf2_64(C1)) {
3798 return DAG.getNode(ISD::SRL, VT, N0,
3799 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
3804 } else if (isa<ConstantSDNode>(N0.Val)) {
3805 // Ensure that the constant occurs on the RHS.
3806 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
3809 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val)) {
3810 // Constant fold or commute setcc.
3811 SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond);
3812 if (O.Val) return O;
3816 // We can always fold X == X for integer setcc's.
3817 if (MVT::isInteger(N0.getValueType()))
3818 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3819 unsigned UOF = ISD::getUnorderedFlavor(Cond);
3820 if (UOF == 2) // FP operators that are undefined on NaNs.
3821 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3822 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
3823 return DAG.getConstant(UOF, VT);
3824 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
3825 // if it is not already.
3826 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
3827 if (NewCond != Cond)
3828 return DAG.getSetCC(VT, N0, N1, NewCond);
3831 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3832 MVT::isInteger(N0.getValueType())) {
3833 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
3834 N0.getOpcode() == ISD::XOR) {
3835 // Simplify (X+Y) == (X+Z) --> Y == Z
3836 if (N0.getOpcode() == N1.getOpcode()) {
3837 if (N0.getOperand(0) == N1.getOperand(0))
3838 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
3839 if (N0.getOperand(1) == N1.getOperand(1))
3840 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
3841 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
3842 // If X op Y == Y op X, try other combinations.
3843 if (N0.getOperand(0) == N1.getOperand(1))
3844 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
3845 if (N0.getOperand(1) == N1.getOperand(0))
3846 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
3850 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
3851 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3852 // Turn (X+C1) == C2 --> X == C2-C1
3853 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
3854 return DAG.getSetCC(VT, N0.getOperand(0),
3855 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
3856 N0.getValueType()), Cond);
3859 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
3860 if (N0.getOpcode() == ISD::XOR)
3861 // If we know that all of the inverted bits are zero, don't bother
3862 // performing the inversion.
3863 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
3864 return DAG.getSetCC(VT, N0.getOperand(0),
3865 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
3866 N0.getValueType()), Cond);
3869 // Turn (C1-X) == C2 --> X == C1-C2
3870 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
3871 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
3872 return DAG.getSetCC(VT, N0.getOperand(1),
3873 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
3874 N0.getValueType()), Cond);
3879 // Simplify (X+Z) == X --> Z == 0
3880 if (N0.getOperand(0) == N1)
3881 return DAG.getSetCC(VT, N0.getOperand(1),
3882 DAG.getConstant(0, N0.getValueType()), Cond);
3883 if (N0.getOperand(1) == N1) {
3884 if (DAG.isCommutativeBinOp(N0.getOpcode()))
3885 return DAG.getSetCC(VT, N0.getOperand(0),
3886 DAG.getConstant(0, N0.getValueType()), Cond);
3888 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
3889 // (Z-X) == X --> Z == X<<1
3890 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
3892 DAG.getConstant(1,TLI.getShiftAmountTy()));
3893 AddToWorkList(SH.Val);
3894 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
3899 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
3900 N1.getOpcode() == ISD::XOR) {
3901 // Simplify X == (X+Z) --> Z == 0
3902 if (N1.getOperand(0) == N0) {
3903 return DAG.getSetCC(VT, N1.getOperand(1),
3904 DAG.getConstant(0, N1.getValueType()), Cond);
3905 } else if (N1.getOperand(1) == N0) {
3906 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
3907 return DAG.getSetCC(VT, N1.getOperand(0),
3908 DAG.getConstant(0, N1.getValueType()), Cond);
3910 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
3911 // X == (Z-X) --> X<<1 == Z
3912 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
3913 DAG.getConstant(1,TLI.getShiftAmountTy()));
3914 AddToWorkList(SH.Val);
3915 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
3921 // Fold away ALL boolean setcc's.
3923 if (N0.getValueType() == MVT::i1 && foldBooleans) {
3925 default: assert(0 && "Unknown integer setcc!");
3926 case ISD::SETEQ: // X == Y -> (X^Y)^1
3927 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
3928 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
3929 AddToWorkList(Temp.Val);
3931 case ISD::SETNE: // X != Y --> (X^Y)
3932 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
3934 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
3935 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
3936 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
3937 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
3938 AddToWorkList(Temp.Val);
3940 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
3941 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
3942 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
3943 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
3944 AddToWorkList(Temp.Val);
3946 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
3947 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
3948 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
3949 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
3950 AddToWorkList(Temp.Val);
3952 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
3953 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
3954 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
3955 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
3958 if (VT != MVT::i1) {
3959 AddToWorkList(N0.Val);
3960 // FIXME: If running after legalize, we probably can't do this.
3961 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
3966 // Could not fold it.
3970 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3971 /// return a DAG expression to select that will generate the same value by
3972 /// multiplying by a magic number. See:
3973 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3974 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
3975 std::vector<SDNode*> Built;
3976 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
3978 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
3984 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3985 /// return a DAG expression to select that will generate the same value by
3986 /// multiplying by a magic number. See:
3987 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3988 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
3989 std::vector<SDNode*> Built;
3990 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
3992 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
3998 /// FindBaseOffset - Return true if base is known not to alias with anything
3999 /// but itself. Provides base object and offset as results.
4000 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
4001 // Assume it is a primitive operation.
4002 Base = Ptr; Offset = 0;
4004 // If it's an adding a simple constant then integrate the offset.
4005 if (Base.getOpcode() == ISD::ADD) {
4006 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
4007 Base = Base.getOperand(0);
4008 Offset += C->getValue();
4012 // If it's any of the following then it can't alias with anything but itself.
4013 return isa<FrameIndexSDNode>(Base) ||
4014 isa<ConstantPoolSDNode>(Base) ||
4015 isa<GlobalAddressSDNode>(Base);
4018 /// isAlias - Return true if there is any possibility that the two addresses
4020 bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1,
4021 const Value *SrcValue1, int SrcValueOffset1,
4022 SDOperand Ptr2, int64_t Size2,
4023 const Value *SrcValue2, int SrcValueOffset2)
4025 // If they are the same then they must be aliases.
4026 if (Ptr1 == Ptr2) return true;
4028 // Gather base node and offset information.
4029 SDOperand Base1, Base2;
4030 int64_t Offset1, Offset2;
4031 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
4032 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
4034 // If they have a same base address then...
4035 if (Base1 == Base2) {
4036 // Check to see if the addresses overlap.
4037 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
4040 // If we know both bases then they can't alias.
4041 if (KnownBase1 && KnownBase2) return false;
4043 if (CombinerGlobalAA) {
4044 // Use alias analysis information.
4045 int Overlap1 = Size1 + SrcValueOffset1 + Offset1;
4046 int Overlap2 = Size2 + SrcValueOffset2 + Offset2;
4047 AliasAnalysis::AliasResult AAResult =
4048 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
4049 if (AAResult == AliasAnalysis::NoAlias)
4053 // Otherwise we have to assume they alias.
4057 /// FindAliasInfo - Extracts the relevant alias information from the memory
4058 /// node. Returns true if the operand was a load.
4059 bool DAGCombiner::FindAliasInfo(SDNode *N,
4060 SDOperand &Ptr, int64_t &Size,
4061 const Value *&SrcValue, int &SrcValueOffset) {
4062 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4063 Ptr = LD->getBasePtr();
4064 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3;
4065 SrcValue = LD->getSrcValue();
4066 SrcValueOffset = LD->getSrcValueOffset();
4068 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4069 Ptr = ST->getBasePtr();
4070 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3;
4071 SrcValue = ST->getSrcValue();
4072 SrcValueOffset = ST->getSrcValueOffset();
4074 assert(0 && "FindAliasInfo expected a memory operand");
4080 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
4081 /// looking for aliasing nodes and adding them to the Aliases vector.
4082 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
4083 SmallVector<SDOperand, 8> &Aliases) {
4084 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
4085 std::set<SDNode *> Visited; // Visited node set.
4087 // Get alias information for node.
4090 const Value *SrcValue;
4092 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
4095 Chains.push_back(OriginalChain);
4097 // Look at each chain and determine if it is an alias. If so, add it to the
4098 // aliases list. If not, then continue up the chain looking for the next
4100 while (!Chains.empty()) {
4101 SDOperand Chain = Chains.back();
4104 // Don't bother if we've been before.
4105 if (Visited.find(Chain.Val) != Visited.end()) continue;
4106 Visited.insert(Chain.Val);
4108 switch (Chain.getOpcode()) {
4109 case ISD::EntryToken:
4110 // Entry token is ideal chain operand, but handled in FindBetterChain.
4115 // Get alias information for Chain.
4118 const Value *OpSrcValue;
4119 int OpSrcValueOffset;
4120 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
4121 OpSrcValue, OpSrcValueOffset);
4123 // If chain is alias then stop here.
4124 if (!(IsLoad && IsOpLoad) &&
4125 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
4126 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
4127 Aliases.push_back(Chain);
4129 // Look further up the chain.
4130 Chains.push_back(Chain.getOperand(0));
4131 // Clean up old chain.
4132 AddToWorkList(Chain.Val);
4137 case ISD::TokenFactor:
4138 // We have to check each of the operands of the token factor, so we queue
4139 // then up. Adding the operands to the queue (stack) in reverse order
4140 // maintains the original order and increases the likelihood that getNode
4141 // will find a matching token factor (CSE.)
4142 for (unsigned n = Chain.getNumOperands(); n;)
4143 Chains.push_back(Chain.getOperand(--n));
4144 // Eliminate the token factor if we can.
4145 AddToWorkList(Chain.Val);
4149 // For all other instructions we will just have to take what we can get.
4150 Aliases.push_back(Chain);
4156 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
4157 /// for a better chain (aliasing node.)
4158 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
4159 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
4161 // Accumulate all the aliases to this node.
4162 GatherAllAliases(N, OldChain, Aliases);
4164 if (Aliases.size() == 0) {
4165 // If no operands then chain to entry token.
4166 return DAG.getEntryNode();
4167 } else if (Aliases.size() == 1) {
4168 // If a single operand then chain to it. We don't need to revisit it.
4172 // Construct a custom tailored token factor.
4173 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4174 &Aliases[0], Aliases.size());
4176 // Make sure the old chain gets cleaned up.
4177 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
4182 // SelectionDAG::Combine - This is the entry point for the file.
4184 void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
4185 /// run - This is the main entry point to this class.
4187 DAGCombiner(*this, AA).Run(RunningAfterLegalize);