1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: divide by zero is currently left unfolded. do we want to turn this
27 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "dagcombine"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/Analysis/AliasAnalysis.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Target/TargetLowering.h"
38 #include "llvm/Support/Compiler.h"
39 #include "llvm/Support/CommandLine.h"
47 static Statistic<> NodesCombined ("dagcombiner",
48 "Number of dag nodes combined");
51 CombinerAA("combiner-alias-analysis", cl::Hidden,
52 cl::desc("Turn on alias analysis during testing"));
54 //------------------------------ DAGCombiner ---------------------------------//
56 class VISIBILITY_HIDDEN DAGCombiner {
61 // Worklist of all of the nodes that need to be simplified.
62 std::vector<SDNode*> WorkList;
64 // AA - Used for DAG load/store alias analysis.
67 /// AddUsersToWorkList - When an instruction is simplified, add all users of
68 /// the instruction to the work lists because they might get more simplified
71 void AddUsersToWorkList(SDNode *N) {
72 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
77 /// removeFromWorkList - remove all instances of N from the worklist.
79 void removeFromWorkList(SDNode *N) {
80 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
85 /// AddToWorkList - Add to the work list making sure it's instance is at the
86 /// the back (next to be processed.)
87 void AddToWorkList(SDNode *N) {
88 removeFromWorkList(N);
89 WorkList.push_back(N);
92 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
94 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
96 DEBUG(std::cerr << "\nReplacing.1 "; N->dump();
97 std::cerr << "\nWith: "; To[0].Val->dump(&DAG);
98 std::cerr << " and " << NumTo-1 << " other values\n");
99 std::vector<SDNode*> NowDead;
100 DAG.ReplaceAllUsesWith(N, To, &NowDead);
103 // Push the new nodes and any users onto the worklist
104 for (unsigned i = 0, e = NumTo; i != e; ++i) {
105 AddToWorkList(To[i].Val);
106 AddUsersToWorkList(To[i].Val);
110 // Nodes can be reintroduced into the worklist. Make sure we do not
111 // process a node that has been replaced.
112 removeFromWorkList(N);
113 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
114 removeFromWorkList(NowDead[i]);
116 // Finally, since the node is now dead, remove it from the graph.
118 return SDOperand(N, 0);
121 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
122 return CombineTo(N, &Res, 1, AddTo);
125 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
127 SDOperand To[] = { Res0, Res1 };
128 return CombineTo(N, To, 2, AddTo);
132 /// SimplifyDemandedBits - Check the specified integer node value to see if
133 /// it can be simplified or if things it uses can be simplified by bit
134 /// propagation. If so, return true.
135 bool SimplifyDemandedBits(SDOperand Op) {
136 TargetLowering::TargetLoweringOpt TLO(DAG);
137 uint64_t KnownZero, KnownOne;
138 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
139 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
143 AddToWorkList(Op.Val);
145 // Replace the old value with the new one.
147 DEBUG(std::cerr << "\nReplacing.2 "; TLO.Old.Val->dump();
148 std::cerr << "\nWith: "; TLO.New.Val->dump(&DAG);
151 std::vector<SDNode*> NowDead;
152 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
154 // Push the new node and any (possibly new) users onto the worklist.
155 AddToWorkList(TLO.New.Val);
156 AddUsersToWorkList(TLO.New.Val);
158 // Nodes can end up on the worklist more than once. Make sure we do
159 // not process a node that has been replaced.
160 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
161 removeFromWorkList(NowDead[i]);
163 // Finally, if the node is now dead, remove it from the graph. The node
164 // may not be dead if the replacement process recursively simplified to
165 // something else needing this node.
166 if (TLO.Old.Val->use_empty()) {
167 removeFromWorkList(TLO.Old.Val);
168 DAG.DeleteNode(TLO.Old.Val);
173 /// visit - call the node-specific routine that knows how to fold each
174 /// particular type of node.
175 SDOperand visit(SDNode *N);
177 // Visitation implementation - Implement dag node combining for different
178 // node types. The semantics are as follows:
180 // SDOperand.Val == 0 - No change was made
181 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
182 // otherwise - N should be replaced by the returned Operand.
184 SDOperand visitTokenFactor(SDNode *N);
185 SDOperand visitADD(SDNode *N);
186 SDOperand visitSUB(SDNode *N);
187 SDOperand visitMUL(SDNode *N);
188 SDOperand visitSDIV(SDNode *N);
189 SDOperand visitUDIV(SDNode *N);
190 SDOperand visitSREM(SDNode *N);
191 SDOperand visitUREM(SDNode *N);
192 SDOperand visitMULHU(SDNode *N);
193 SDOperand visitMULHS(SDNode *N);
194 SDOperand visitAND(SDNode *N);
195 SDOperand visitOR(SDNode *N);
196 SDOperand visitXOR(SDNode *N);
197 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp);
198 SDOperand visitSHL(SDNode *N);
199 SDOperand visitSRA(SDNode *N);
200 SDOperand visitSRL(SDNode *N);
201 SDOperand visitCTLZ(SDNode *N);
202 SDOperand visitCTTZ(SDNode *N);
203 SDOperand visitCTPOP(SDNode *N);
204 SDOperand visitSELECT(SDNode *N);
205 SDOperand visitSELECT_CC(SDNode *N);
206 SDOperand visitSETCC(SDNode *N);
207 SDOperand visitSIGN_EXTEND(SDNode *N);
208 SDOperand visitZERO_EXTEND(SDNode *N);
209 SDOperand visitANY_EXTEND(SDNode *N);
210 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
211 SDOperand visitTRUNCATE(SDNode *N);
212 SDOperand visitBIT_CONVERT(SDNode *N);
213 SDOperand visitVBIT_CONVERT(SDNode *N);
214 SDOperand visitFADD(SDNode *N);
215 SDOperand visitFSUB(SDNode *N);
216 SDOperand visitFMUL(SDNode *N);
217 SDOperand visitFDIV(SDNode *N);
218 SDOperand visitFREM(SDNode *N);
219 SDOperand visitFCOPYSIGN(SDNode *N);
220 SDOperand visitSINT_TO_FP(SDNode *N);
221 SDOperand visitUINT_TO_FP(SDNode *N);
222 SDOperand visitFP_TO_SINT(SDNode *N);
223 SDOperand visitFP_TO_UINT(SDNode *N);
224 SDOperand visitFP_ROUND(SDNode *N);
225 SDOperand visitFP_ROUND_INREG(SDNode *N);
226 SDOperand visitFP_EXTEND(SDNode *N);
227 SDOperand visitFNEG(SDNode *N);
228 SDOperand visitFABS(SDNode *N);
229 SDOperand visitBRCOND(SDNode *N);
230 SDOperand visitBR_CC(SDNode *N);
231 SDOperand visitLOAD(SDNode *N);
232 SDOperand visitSTORE(SDNode *N);
233 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
234 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
235 SDOperand visitVBUILD_VECTOR(SDNode *N);
236 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
237 SDOperand visitVVECTOR_SHUFFLE(SDNode *N);
239 SDOperand XformToShuffleWithZero(SDNode *N);
240 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
242 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
243 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
244 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
245 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
246 SDOperand N3, ISD::CondCode CC);
247 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
248 ISD::CondCode Cond, bool foldBooleans = true);
249 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType);
250 SDOperand BuildSDIV(SDNode *N);
251 SDOperand BuildUDIV(SDNode *N);
252 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
254 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
255 /// looking for aliasing nodes and adding them to the Aliases vector.
256 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
257 SmallVector<SDOperand, 8> &Aliases);
259 /// isAlias - Return true if there is any possibility that the two addresses
261 bool isAlias(SDOperand Ptr1, int64_t Size1,
262 const Value *SrcValue1, int SrcValueOffset1,
263 SDOperand Ptr2, int64_t Size2,
264 const Value *SrcValue2, int SrcValueOffset1);
266 /// FindAliasInfo - Extracts the relevant alias information from the memory
267 /// node. Returns true if the operand was a load.
268 bool FindAliasInfo(SDNode *N,
269 SDOperand &Ptr, int64_t &Size,
270 const Value *&SrcValue, int &SrcValueOffset);
272 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
273 /// looking for a better chain (aliasing node.)
274 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
277 DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
279 TLI(D.getTargetLoweringInfo()),
280 AfterLegalize(false),
283 /// Run - runs the dag combiner on all nodes in the work list
284 void Run(bool RunningAfterLegalize);
288 //===----------------------------------------------------------------------===//
289 // TargetLowering::DAGCombinerInfo implementation
290 //===----------------------------------------------------------------------===//
292 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
293 ((DAGCombiner*)DC)->AddToWorkList(N);
296 SDOperand TargetLowering::DAGCombinerInfo::
297 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
298 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
301 SDOperand TargetLowering::DAGCombinerInfo::
302 CombineTo(SDNode *N, SDOperand Res) {
303 return ((DAGCombiner*)DC)->CombineTo(N, Res);
307 SDOperand TargetLowering::DAGCombinerInfo::
308 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
309 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
315 //===----------------------------------------------------------------------===//
318 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
319 // that selects between the values 1 and 0, making it equivalent to a setcc.
320 // Also, set the incoming LHS, RHS, and CC references to the appropriate
321 // nodes based on the type of node we are checking. This simplifies life a
322 // bit for the callers.
323 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
325 if (N.getOpcode() == ISD::SETCC) {
326 LHS = N.getOperand(0);
327 RHS = N.getOperand(1);
328 CC = N.getOperand(2);
331 if (N.getOpcode() == ISD::SELECT_CC &&
332 N.getOperand(2).getOpcode() == ISD::Constant &&
333 N.getOperand(3).getOpcode() == ISD::Constant &&
334 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
335 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
336 LHS = N.getOperand(0);
337 RHS = N.getOperand(1);
338 CC = N.getOperand(4);
344 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
345 // one use. If this is true, it allows the users to invert the operation for
346 // free when it is profitable to do so.
347 static bool isOneUseSetCC(SDOperand N) {
348 SDOperand N0, N1, N2;
349 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
354 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
355 MVT::ValueType VT = N0.getValueType();
356 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
357 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
358 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
359 if (isa<ConstantSDNode>(N1)) {
360 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
361 AddToWorkList(OpNode.Val);
362 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
363 } else if (N0.hasOneUse()) {
364 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
365 AddToWorkList(OpNode.Val);
366 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
369 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
370 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
371 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
372 if (isa<ConstantSDNode>(N0)) {
373 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
374 AddToWorkList(OpNode.Val);
375 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
376 } else if (N1.hasOneUse()) {
377 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
378 AddToWorkList(OpNode.Val);
379 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
385 void DAGCombiner::Run(bool RunningAfterLegalize) {
386 // set the instance variable, so that the various visit routines may use it.
387 AfterLegalize = RunningAfterLegalize;
389 // Add all the dag nodes to the worklist.
390 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
391 E = DAG.allnodes_end(); I != E; ++I)
392 WorkList.push_back(I);
394 // Create a dummy node (which is not added to allnodes), that adds a reference
395 // to the root node, preventing it from being deleted, and tracking any
396 // changes of the root.
397 HandleSDNode Dummy(DAG.getRoot());
399 // The root of the dag may dangle to deleted nodes until the dag combiner is
400 // done. Set it to null to avoid confusion.
401 DAG.setRoot(SDOperand());
403 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
404 TargetLowering::DAGCombinerInfo
405 DagCombineInfo(DAG, !RunningAfterLegalize, this);
407 // while the worklist isn't empty, inspect the node on the end of it and
408 // try and combine it.
409 while (!WorkList.empty()) {
410 SDNode *N = WorkList.back();
413 // If N has no uses, it is dead. Make sure to revisit all N's operands once
414 // N is deleted from the DAG, since they too may now be dead or may have a
415 // reduced number of uses, allowing other xforms.
416 if (N->use_empty() && N != &Dummy) {
417 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
418 AddToWorkList(N->getOperand(i).Val);
424 SDOperand RV = visit(N);
426 // If nothing happened, try a target-specific DAG combine.
428 assert(N->getOpcode() != ISD::DELETED_NODE &&
429 "Node was deleted but visit returned NULL!");
430 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
431 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
432 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
437 // If we get back the same node we passed in, rather than a new node or
438 // zero, we know that the node must have defined multiple values and
439 // CombineTo was used. Since CombineTo takes care of the worklist
440 // mechanics for us, we have no work to do in this case.
442 assert(N->getOpcode() != ISD::DELETED_NODE &&
443 RV.Val->getOpcode() != ISD::DELETED_NODE &&
444 "Node was deleted but visit returned new node!");
446 DEBUG(std::cerr << "\nReplacing.3 "; N->dump();
447 std::cerr << "\nWith: "; RV.Val->dump(&DAG);
449 std::vector<SDNode*> NowDead;
450 if (N->getNumValues() == RV.Val->getNumValues())
451 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
453 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
455 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
458 // Push the new node and any users onto the worklist
459 AddToWorkList(RV.Val);
460 AddUsersToWorkList(RV.Val);
462 // Nodes can be reintroduced into the worklist. Make sure we do not
463 // process a node that has been replaced.
464 removeFromWorkList(N);
465 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
466 removeFromWorkList(NowDead[i]);
468 // Finally, since the node is now dead, remove it from the graph.
474 // If the root changed (e.g. it was a dead load, update the root).
475 DAG.setRoot(Dummy.getValue());
478 SDOperand DAGCombiner::visit(SDNode *N) {
479 switch(N->getOpcode()) {
481 case ISD::TokenFactor: return visitTokenFactor(N);
482 case ISD::ADD: return visitADD(N);
483 case ISD::SUB: return visitSUB(N);
484 case ISD::MUL: return visitMUL(N);
485 case ISD::SDIV: return visitSDIV(N);
486 case ISD::UDIV: return visitUDIV(N);
487 case ISD::SREM: return visitSREM(N);
488 case ISD::UREM: return visitUREM(N);
489 case ISD::MULHU: return visitMULHU(N);
490 case ISD::MULHS: return visitMULHS(N);
491 case ISD::AND: return visitAND(N);
492 case ISD::OR: return visitOR(N);
493 case ISD::XOR: return visitXOR(N);
494 case ISD::SHL: return visitSHL(N);
495 case ISD::SRA: return visitSRA(N);
496 case ISD::SRL: return visitSRL(N);
497 case ISD::CTLZ: return visitCTLZ(N);
498 case ISD::CTTZ: return visitCTTZ(N);
499 case ISD::CTPOP: return visitCTPOP(N);
500 case ISD::SELECT: return visitSELECT(N);
501 case ISD::SELECT_CC: return visitSELECT_CC(N);
502 case ISD::SETCC: return visitSETCC(N);
503 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
504 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
505 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
506 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
507 case ISD::TRUNCATE: return visitTRUNCATE(N);
508 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
509 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N);
510 case ISD::FADD: return visitFADD(N);
511 case ISD::FSUB: return visitFSUB(N);
512 case ISD::FMUL: return visitFMUL(N);
513 case ISD::FDIV: return visitFDIV(N);
514 case ISD::FREM: return visitFREM(N);
515 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
516 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
517 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
518 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
519 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
520 case ISD::FP_ROUND: return visitFP_ROUND(N);
521 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
522 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
523 case ISD::FNEG: return visitFNEG(N);
524 case ISD::FABS: return visitFABS(N);
525 case ISD::BRCOND: return visitBRCOND(N);
526 case ISD::BR_CC: return visitBR_CC(N);
527 case ISD::LOAD: return visitLOAD(N);
528 case ISD::STORE: return visitSTORE(N);
529 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
530 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
531 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N);
532 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
533 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N);
534 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD);
535 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB);
536 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL);
537 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV);
538 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV);
539 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND);
540 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR);
541 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR);
546 /// getInputChainForNode - Given a node, return its input chain if it has one,
547 /// otherwise return a null sd operand.
548 static SDOperand getInputChainForNode(SDNode *N) {
549 if (unsigned NumOps = N->getNumOperands()) {
550 if (N->getOperand(0).getValueType() == MVT::Other)
551 return N->getOperand(0);
552 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
553 return N->getOperand(NumOps-1);
554 for (unsigned i = 1; i < NumOps-1; ++i)
555 if (N->getOperand(i).getValueType() == MVT::Other)
556 return N->getOperand(i);
558 return SDOperand(0, 0);
561 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
562 // If N has two operands, where one has an input chain equal to the other,
563 // the 'other' chain is redundant.
564 if (N->getNumOperands() == 2) {
565 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
566 return N->getOperand(0);
567 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
568 return N->getOperand(1);
572 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
573 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
574 bool Changed = false; // If we should replace this token factor.
576 // Start out with this token factor.
579 // Iterate through token factors. The TFs grows when new token factors are
581 for (unsigned i = 0; i < TFs.size(); ++i) {
584 // Check each of the operands.
585 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
586 SDOperand Op = TF->getOperand(i);
588 switch (Op.getOpcode()) {
589 case ISD::EntryToken:
590 // Entry tokens don't need to be added to the list. They are
595 case ISD::TokenFactor:
596 if ((CombinerAA || Op.hasOneUse()) &&
597 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
598 // Queue up for processing.
599 TFs.push_back(Op.Val);
600 // Clean up in case the token factor is removed.
601 AddToWorkList(Op.Val);
608 // Only add if not there prior.
609 if (std::find(Ops.begin(), Ops.end(), Op) == Ops.end())
618 // If we've change things around then replace token factor.
620 if (Ops.size() == 0) {
621 // The entry token is the only possible outcome.
622 Result = DAG.getEntryNode();
624 // New and improved token factor.
625 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
628 // Don't add users to work list.
629 return CombineTo(N, Result, false);
635 SDOperand DAGCombiner::visitADD(SDNode *N) {
636 SDOperand N0 = N->getOperand(0);
637 SDOperand N1 = N->getOperand(1);
638 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
639 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
640 MVT::ValueType VT = N0.getValueType();
642 // fold (add c1, c2) -> c1+c2
644 return DAG.getNode(ISD::ADD, VT, N0, N1);
645 // canonicalize constant to RHS
647 return DAG.getNode(ISD::ADD, VT, N1, N0);
648 // fold (add x, 0) -> x
649 if (N1C && N1C->isNullValue())
651 // fold ((c1-A)+c2) -> (c1+c2)-A
652 if (N1C && N0.getOpcode() == ISD::SUB)
653 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
654 return DAG.getNode(ISD::SUB, VT,
655 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
658 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
661 // fold ((0-A) + B) -> B-A
662 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
663 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
664 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
665 // fold (A + (0-B)) -> A-B
666 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
667 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
668 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
669 // fold (A+(B-A)) -> B
670 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
671 return N1.getOperand(0);
673 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
674 return SDOperand(N, 0);
676 // fold (a+b) -> (a|b) iff a and b share no bits.
677 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
678 uint64_t LHSZero, LHSOne;
679 uint64_t RHSZero, RHSOne;
680 uint64_t Mask = MVT::getIntVTBitMask(VT);
681 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
683 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
685 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
686 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
687 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
688 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
689 return DAG.getNode(ISD::OR, VT, N0, N1);
696 SDOperand DAGCombiner::visitSUB(SDNode *N) {
697 SDOperand N0 = N->getOperand(0);
698 SDOperand N1 = N->getOperand(1);
699 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
700 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
701 MVT::ValueType VT = N0.getValueType();
703 // fold (sub x, x) -> 0
705 return DAG.getConstant(0, N->getValueType(0));
706 // fold (sub c1, c2) -> c1-c2
708 return DAG.getNode(ISD::SUB, VT, N0, N1);
709 // fold (sub x, c) -> (add x, -c)
711 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
713 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
714 return N0.getOperand(1);
716 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
717 return N0.getOperand(0);
721 SDOperand DAGCombiner::visitMUL(SDNode *N) {
722 SDOperand N0 = N->getOperand(0);
723 SDOperand N1 = N->getOperand(1);
724 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
725 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
726 MVT::ValueType VT = N0.getValueType();
728 // fold (mul c1, c2) -> c1*c2
730 return DAG.getNode(ISD::MUL, VT, N0, N1);
731 // canonicalize constant to RHS
733 return DAG.getNode(ISD::MUL, VT, N1, N0);
734 // fold (mul x, 0) -> 0
735 if (N1C && N1C->isNullValue())
737 // fold (mul x, -1) -> 0-x
738 if (N1C && N1C->isAllOnesValue())
739 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
740 // fold (mul x, (1 << c)) -> x << c
741 if (N1C && isPowerOf2_64(N1C->getValue()))
742 return DAG.getNode(ISD::SHL, VT, N0,
743 DAG.getConstant(Log2_64(N1C->getValue()),
744 TLI.getShiftAmountTy()));
745 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
746 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
747 // FIXME: If the input is something that is easily negated (e.g. a
748 // single-use add), we should put the negate there.
749 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
750 DAG.getNode(ISD::SHL, VT, N0,
751 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
752 TLI.getShiftAmountTy())));
755 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
756 if (N1C && N0.getOpcode() == ISD::SHL &&
757 isa<ConstantSDNode>(N0.getOperand(1))) {
758 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
759 AddToWorkList(C3.Val);
760 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
763 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
766 SDOperand Sh(0,0), Y(0,0);
767 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
768 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
769 N0.Val->hasOneUse()) {
771 } else if (N1.getOpcode() == ISD::SHL &&
772 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
776 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
777 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
780 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
781 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
782 isa<ConstantSDNode>(N0.getOperand(1))) {
783 return DAG.getNode(ISD::ADD, VT,
784 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
785 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
789 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
795 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
796 SDOperand N0 = N->getOperand(0);
797 SDOperand N1 = N->getOperand(1);
798 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
799 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
800 MVT::ValueType VT = N->getValueType(0);
802 // fold (sdiv c1, c2) -> c1/c2
803 if (N0C && N1C && !N1C->isNullValue())
804 return DAG.getNode(ISD::SDIV, VT, N0, N1);
805 // fold (sdiv X, 1) -> X
806 if (N1C && N1C->getSignExtended() == 1LL)
808 // fold (sdiv X, -1) -> 0-X
809 if (N1C && N1C->isAllOnesValue())
810 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
811 // If we know the sign bits of both operands are zero, strength reduce to a
812 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
813 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
814 if (TLI.MaskedValueIsZero(N1, SignBit) &&
815 TLI.MaskedValueIsZero(N0, SignBit))
816 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
817 // fold (sdiv X, pow2) -> simple ops after legalize
818 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
819 (isPowerOf2_64(N1C->getSignExtended()) ||
820 isPowerOf2_64(-N1C->getSignExtended()))) {
821 // If dividing by powers of two is cheap, then don't perform the following
823 if (TLI.isPow2DivCheap())
825 int64_t pow2 = N1C->getSignExtended();
826 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
827 unsigned lg2 = Log2_64(abs2);
828 // Splat the sign bit into the register
829 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
830 DAG.getConstant(MVT::getSizeInBits(VT)-1,
831 TLI.getShiftAmountTy()));
832 AddToWorkList(SGN.Val);
833 // Add (N0 < 0) ? abs2 - 1 : 0;
834 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
835 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
836 TLI.getShiftAmountTy()));
837 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
838 AddToWorkList(SRL.Val);
839 AddToWorkList(ADD.Val); // Divide by pow2
840 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
841 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
842 // If we're dividing by a positive value, we're done. Otherwise, we must
843 // negate the result.
846 AddToWorkList(SRA.Val);
847 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
849 // if integer divide is expensive and we satisfy the requirements, emit an
850 // alternate sequence.
851 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
852 !TLI.isIntDivCheap()) {
853 SDOperand Op = BuildSDIV(N);
854 if (Op.Val) return Op;
859 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
860 SDOperand N0 = N->getOperand(0);
861 SDOperand N1 = N->getOperand(1);
862 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
863 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
864 MVT::ValueType VT = N->getValueType(0);
866 // fold (udiv c1, c2) -> c1/c2
867 if (N0C && N1C && !N1C->isNullValue())
868 return DAG.getNode(ISD::UDIV, VT, N0, N1);
869 // fold (udiv x, (1 << c)) -> x >>u c
870 if (N1C && isPowerOf2_64(N1C->getValue()))
871 return DAG.getNode(ISD::SRL, VT, N0,
872 DAG.getConstant(Log2_64(N1C->getValue()),
873 TLI.getShiftAmountTy()));
874 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
875 if (N1.getOpcode() == ISD::SHL) {
876 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
877 if (isPowerOf2_64(SHC->getValue())) {
878 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
879 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
880 DAG.getConstant(Log2_64(SHC->getValue()),
882 AddToWorkList(Add.Val);
883 return DAG.getNode(ISD::SRL, VT, N0, Add);
887 // fold (udiv x, c) -> alternate
888 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
889 SDOperand Op = BuildUDIV(N);
890 if (Op.Val) return Op;
895 SDOperand DAGCombiner::visitSREM(SDNode *N) {
896 SDOperand N0 = N->getOperand(0);
897 SDOperand N1 = N->getOperand(1);
898 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
899 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
900 MVT::ValueType VT = N->getValueType(0);
902 // fold (srem c1, c2) -> c1%c2
903 if (N0C && N1C && !N1C->isNullValue())
904 return DAG.getNode(ISD::SREM, VT, N0, N1);
905 // If we know the sign bits of both operands are zero, strength reduce to a
906 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
907 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
908 if (TLI.MaskedValueIsZero(N1, SignBit) &&
909 TLI.MaskedValueIsZero(N0, SignBit))
910 return DAG.getNode(ISD::UREM, VT, N0, N1);
912 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
913 // the remainder operation.
914 if (N1C && !N1C->isNullValue()) {
915 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
916 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
917 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
918 AddToWorkList(Div.Val);
919 AddToWorkList(Mul.Val);
926 SDOperand DAGCombiner::visitUREM(SDNode *N) {
927 SDOperand N0 = N->getOperand(0);
928 SDOperand N1 = N->getOperand(1);
929 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
930 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
931 MVT::ValueType VT = N->getValueType(0);
933 // fold (urem c1, c2) -> c1%c2
934 if (N0C && N1C && !N1C->isNullValue())
935 return DAG.getNode(ISD::UREM, VT, N0, N1);
936 // fold (urem x, pow2) -> (and x, pow2-1)
937 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
938 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
939 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
940 if (N1.getOpcode() == ISD::SHL) {
941 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
942 if (isPowerOf2_64(SHC->getValue())) {
943 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
944 AddToWorkList(Add.Val);
945 return DAG.getNode(ISD::AND, VT, N0, Add);
950 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
951 // the remainder operation.
952 if (N1C && !N1C->isNullValue()) {
953 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
954 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
955 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
956 AddToWorkList(Div.Val);
957 AddToWorkList(Mul.Val);
964 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
965 SDOperand N0 = N->getOperand(0);
966 SDOperand N1 = N->getOperand(1);
967 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
969 // fold (mulhs x, 0) -> 0
970 if (N1C && N1C->isNullValue())
972 // fold (mulhs x, 1) -> (sra x, size(x)-1)
973 if (N1C && N1C->getValue() == 1)
974 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
975 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
976 TLI.getShiftAmountTy()));
980 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
981 SDOperand N0 = N->getOperand(0);
982 SDOperand N1 = N->getOperand(1);
983 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
985 // fold (mulhu x, 0) -> 0
986 if (N1C && N1C->isNullValue())
988 // fold (mulhu x, 1) -> 0
989 if (N1C && N1C->getValue() == 1)
990 return DAG.getConstant(0, N0.getValueType());
994 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
995 /// two operands of the same opcode, try to simplify it.
996 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
997 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
998 MVT::ValueType VT = N0.getValueType();
999 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1001 // For each of OP in AND/OR/XOR:
1002 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1003 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1004 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1005 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1006 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1007 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1008 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1009 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1010 N0.getOperand(0).getValueType(),
1011 N0.getOperand(0), N1.getOperand(0));
1012 AddToWorkList(ORNode.Val);
1013 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1016 // For each of OP in SHL/SRL/SRA/AND...
1017 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1018 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1019 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1020 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1021 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1022 N0.getOperand(1) == N1.getOperand(1)) {
1023 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1024 N0.getOperand(0).getValueType(),
1025 N0.getOperand(0), N1.getOperand(0));
1026 AddToWorkList(ORNode.Val);
1027 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1033 SDOperand DAGCombiner::visitAND(SDNode *N) {
1034 SDOperand N0 = N->getOperand(0);
1035 SDOperand N1 = N->getOperand(1);
1036 SDOperand LL, LR, RL, RR, CC0, CC1;
1037 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1038 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1039 MVT::ValueType VT = N1.getValueType();
1040 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1042 // fold (and c1, c2) -> c1&c2
1044 return DAG.getNode(ISD::AND, VT, N0, N1);
1045 // canonicalize constant to RHS
1047 return DAG.getNode(ISD::AND, VT, N1, N0);
1048 // fold (and x, -1) -> x
1049 if (N1C && N1C->isAllOnesValue())
1051 // if (and x, c) is known to be zero, return 0
1052 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1053 return DAG.getConstant(0, VT);
1055 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1058 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1059 if (N1C && N0.getOpcode() == ISD::OR)
1060 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1061 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1063 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1064 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1065 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1066 if (TLI.MaskedValueIsZero(N0.getOperand(0),
1067 ~N1C->getValue() & InMask)) {
1068 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1071 // Replace uses of the AND with uses of the Zero extend node.
1074 // We actually want to replace all uses of the any_extend with the
1075 // zero_extend, to avoid duplicating things. This will later cause this
1076 // AND to be folded.
1077 CombineTo(N0.Val, Zext);
1078 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1081 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1082 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1083 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1084 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1086 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1087 MVT::isInteger(LL.getValueType())) {
1088 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1089 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1090 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1091 AddToWorkList(ORNode.Val);
1092 return DAG.getSetCC(VT, ORNode, LR, Op1);
1094 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1095 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1096 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1097 AddToWorkList(ANDNode.Val);
1098 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1100 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1101 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1102 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1103 AddToWorkList(ORNode.Val);
1104 return DAG.getSetCC(VT, ORNode, LR, Op1);
1107 // canonicalize equivalent to ll == rl
1108 if (LL == RR && LR == RL) {
1109 Op1 = ISD::getSetCCSwappedOperands(Op1);
1112 if (LL == RL && LR == RR) {
1113 bool isInteger = MVT::isInteger(LL.getValueType());
1114 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1115 if (Result != ISD::SETCC_INVALID)
1116 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1120 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1121 if (N0.getOpcode() == N1.getOpcode()) {
1122 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1123 if (Tmp.Val) return Tmp;
1126 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1127 // fold (and (sra)) -> (and (srl)) when possible.
1128 if (!MVT::isVector(VT) &&
1129 SimplifyDemandedBits(SDOperand(N, 0)))
1130 return SDOperand(N, 0);
1131 // fold (zext_inreg (extload x)) -> (zextload x)
1132 if (ISD::isEXTLoad(N0.Val)) {
1133 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1134 MVT::ValueType EVT = LN0->getLoadedVT();
1135 // If we zero all the possible extended bits, then we can turn this into
1136 // a zextload if we are running before legalize or the operation is legal.
1137 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1138 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1139 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1140 LN0->getBasePtr(), LN0->getSrcValue(),
1141 LN0->getSrcValueOffset(), EVT);
1143 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1144 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1147 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1148 if (ISD::isSEXTLoad(N0.Val) && N0.hasOneUse()) {
1149 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1150 MVT::ValueType EVT = LN0->getLoadedVT();
1151 // If we zero all the possible extended bits, then we can turn this into
1152 // a zextload if we are running before legalize or the operation is legal.
1153 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1154 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1155 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1156 LN0->getBasePtr(), LN0->getSrcValue(),
1157 LN0->getSrcValueOffset(), EVT);
1159 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1160 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1164 // fold (and (load x), 255) -> (zextload x, i8)
1165 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1166 if (N1C && N0.getOpcode() == ISD::LOAD) {
1167 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1168 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1170 MVT::ValueType EVT, LoadedVT;
1171 if (N1C->getValue() == 255)
1173 else if (N1C->getValue() == 65535)
1175 else if (N1C->getValue() == ~0U)
1180 LoadedVT = LN0->getLoadedVT();
1181 if (EVT != MVT::Other && LoadedVT > EVT &&
1182 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1183 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1184 // For big endian targets, we need to add an offset to the pointer to
1185 // load the correct bytes. For little endian systems, we merely need to
1186 // read fewer bytes from the same pointer.
1188 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1189 SDOperand NewPtr = LN0->getBasePtr();
1190 if (!TLI.isLittleEndian())
1191 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1192 DAG.getConstant(PtrOff, PtrType));
1193 AddToWorkList(NewPtr.Val);
1195 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1196 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT);
1198 CombineTo(N0.Val, Load, Load.getValue(1));
1199 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1207 SDOperand DAGCombiner::visitOR(SDNode *N) {
1208 SDOperand N0 = N->getOperand(0);
1209 SDOperand N1 = N->getOperand(1);
1210 SDOperand LL, LR, RL, RR, CC0, CC1;
1211 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1212 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1213 MVT::ValueType VT = N1.getValueType();
1214 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1216 // fold (or c1, c2) -> c1|c2
1218 return DAG.getNode(ISD::OR, VT, N0, N1);
1219 // canonicalize constant to RHS
1221 return DAG.getNode(ISD::OR, VT, N1, N0);
1222 // fold (or x, 0) -> x
1223 if (N1C && N1C->isNullValue())
1225 // fold (or x, -1) -> -1
1226 if (N1C && N1C->isAllOnesValue())
1228 // fold (or x, c) -> c iff (x & ~c) == 0
1230 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1233 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1236 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1237 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1238 isa<ConstantSDNode>(N0.getOperand(1))) {
1239 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1240 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1242 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1244 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1245 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1246 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1247 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1249 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1250 MVT::isInteger(LL.getValueType())) {
1251 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1252 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1253 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1254 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1255 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1256 AddToWorkList(ORNode.Val);
1257 return DAG.getSetCC(VT, ORNode, LR, Op1);
1259 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1260 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1261 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1262 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1263 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1264 AddToWorkList(ANDNode.Val);
1265 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1268 // canonicalize equivalent to ll == rl
1269 if (LL == RR && LR == RL) {
1270 Op1 = ISD::getSetCCSwappedOperands(Op1);
1273 if (LL == RL && LR == RR) {
1274 bool isInteger = MVT::isInteger(LL.getValueType());
1275 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1276 if (Result != ISD::SETCC_INVALID)
1277 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1281 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1282 if (N0.getOpcode() == N1.getOpcode()) {
1283 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1284 if (Tmp.Val) return Tmp;
1287 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1288 if (N0.getOpcode() == ISD::AND &&
1289 N1.getOpcode() == ISD::AND &&
1290 N0.getOperand(1).getOpcode() == ISD::Constant &&
1291 N1.getOperand(1).getOpcode() == ISD::Constant &&
1292 // Don't increase # computations.
1293 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1294 // We can only do this xform if we know that bits from X that are set in C2
1295 // but not in C1 are already zero. Likewise for Y.
1296 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1297 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1299 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1300 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1301 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1302 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1307 // See if this is some rotate idiom.
1308 if (SDNode *Rot = MatchRotate(N0, N1))
1309 return SDOperand(Rot, 0);
1315 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1316 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1317 if (Op.getOpcode() == ISD::AND) {
1318 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1319 Mask = Op.getOperand(1);
1320 Op = Op.getOperand(0);
1326 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1334 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1335 // idioms for rotate, and if the target supports rotation instructions, generate
1337 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1338 // Must be a legal type. Expanded an promoted things won't work with rotates.
1339 MVT::ValueType VT = LHS.getValueType();
1340 if (!TLI.isTypeLegal(VT)) return 0;
1342 // The target must have at least one rotate flavor.
1343 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1344 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1345 if (!HasROTL && !HasROTR) return 0;
1347 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1348 SDOperand LHSShift; // The shift.
1349 SDOperand LHSMask; // AND value if any.
1350 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1351 return 0; // Not part of a rotate.
1353 SDOperand RHSShift; // The shift.
1354 SDOperand RHSMask; // AND value if any.
1355 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1356 return 0; // Not part of a rotate.
1358 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1359 return 0; // Not shifting the same value.
1361 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1362 return 0; // Shifts must disagree.
1364 // Canonicalize shl to left side in a shl/srl pair.
1365 if (RHSShift.getOpcode() == ISD::SHL) {
1366 std::swap(LHS, RHS);
1367 std::swap(LHSShift, RHSShift);
1368 std::swap(LHSMask , RHSMask );
1371 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1373 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1374 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1375 if (LHSShift.getOperand(1).getOpcode() == ISD::Constant &&
1376 RHSShift.getOperand(1).getOpcode() == ISD::Constant) {
1377 uint64_t LShVal = cast<ConstantSDNode>(LHSShift.getOperand(1))->getValue();
1378 uint64_t RShVal = cast<ConstantSDNode>(RHSShift.getOperand(1))->getValue();
1379 if ((LShVal + RShVal) != OpSizeInBits)
1384 Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1385 LHSShift.getOperand(1));
1387 Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1388 RHSShift.getOperand(1));
1390 // If there is an AND of either shifted operand, apply it to the result.
1391 if (LHSMask.Val || RHSMask.Val) {
1392 uint64_t Mask = MVT::getIntVTBitMask(VT);
1395 uint64_t RHSBits = (1ULL << LShVal)-1;
1396 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1399 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1400 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1403 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1409 // If there is a mask here, and we have a variable shift, we can't be sure
1410 // that we're masking out the right stuff.
1411 if (LHSMask.Val || RHSMask.Val)
1414 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1415 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1416 if (RHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1417 LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) {
1418 if (ConstantSDNode *SUBC =
1419 dyn_cast<ConstantSDNode>(RHSShift.getOperand(1).getOperand(0))) {
1420 if (SUBC->getValue() == OpSizeInBits)
1422 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1423 LHSShift.getOperand(1)).Val;
1425 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1426 LHSShift.getOperand(1)).Val;
1430 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1431 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1432 if (LHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1433 RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) {
1434 if (ConstantSDNode *SUBC =
1435 dyn_cast<ConstantSDNode>(LHSShift.getOperand(1).getOperand(0))) {
1436 if (SUBC->getValue() == OpSizeInBits)
1438 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1439 LHSShift.getOperand(1)).Val;
1441 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1442 RHSShift.getOperand(1)).Val;
1450 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1451 SDOperand N0 = N->getOperand(0);
1452 SDOperand N1 = N->getOperand(1);
1453 SDOperand LHS, RHS, CC;
1454 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1455 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1456 MVT::ValueType VT = N0.getValueType();
1458 // fold (xor c1, c2) -> c1^c2
1460 return DAG.getNode(ISD::XOR, VT, N0, N1);
1461 // canonicalize constant to RHS
1463 return DAG.getNode(ISD::XOR, VT, N1, N0);
1464 // fold (xor x, 0) -> x
1465 if (N1C && N1C->isNullValue())
1468 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1471 // fold !(x cc y) -> (x !cc y)
1472 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1473 bool isInt = MVT::isInteger(LHS.getValueType());
1474 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1476 if (N0.getOpcode() == ISD::SETCC)
1477 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1478 if (N0.getOpcode() == ISD::SELECT_CC)
1479 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1480 assert(0 && "Unhandled SetCC Equivalent!");
1483 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1484 if (N1C && N1C->getValue() == 1 &&
1485 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1486 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1487 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1488 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1489 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1490 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1491 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1492 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1495 // fold !(x or y) -> (!x and !y) iff x or y are constants
1496 if (N1C && N1C->isAllOnesValue() &&
1497 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1498 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1499 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1500 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1501 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1502 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1503 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1504 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1507 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1508 if (N1C && N0.getOpcode() == ISD::XOR) {
1509 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1510 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1512 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1513 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1515 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1516 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1518 // fold (xor x, x) -> 0
1520 if (!MVT::isVector(VT)) {
1521 return DAG.getConstant(0, VT);
1522 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1523 // Produce a vector of zeros.
1524 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
1525 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
1526 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1530 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
1531 if (N0.getOpcode() == N1.getOpcode()) {
1532 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1533 if (Tmp.Val) return Tmp;
1536 // Simplify the expression using non-local knowledge.
1537 if (!MVT::isVector(VT) &&
1538 SimplifyDemandedBits(SDOperand(N, 0)))
1539 return SDOperand(N, 0);
1544 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1545 SDOperand N0 = N->getOperand(0);
1546 SDOperand N1 = N->getOperand(1);
1547 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1548 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1549 MVT::ValueType VT = N0.getValueType();
1550 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1552 // fold (shl c1, c2) -> c1<<c2
1554 return DAG.getNode(ISD::SHL, VT, N0, N1);
1555 // fold (shl 0, x) -> 0
1556 if (N0C && N0C->isNullValue())
1558 // fold (shl x, c >= size(x)) -> undef
1559 if (N1C && N1C->getValue() >= OpSizeInBits)
1560 return DAG.getNode(ISD::UNDEF, VT);
1561 // fold (shl x, 0) -> x
1562 if (N1C && N1C->isNullValue())
1564 // if (shl x, c) is known to be zero, return 0
1565 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1566 return DAG.getConstant(0, VT);
1567 if (SimplifyDemandedBits(SDOperand(N, 0)))
1568 return SDOperand(N, 0);
1569 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1570 if (N1C && N0.getOpcode() == ISD::SHL &&
1571 N0.getOperand(1).getOpcode() == ISD::Constant) {
1572 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1573 uint64_t c2 = N1C->getValue();
1574 if (c1 + c2 > OpSizeInBits)
1575 return DAG.getConstant(0, VT);
1576 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1577 DAG.getConstant(c1 + c2, N1.getValueType()));
1579 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1580 // (srl (and x, -1 << c1), c1-c2)
1581 if (N1C && N0.getOpcode() == ISD::SRL &&
1582 N0.getOperand(1).getOpcode() == ISD::Constant) {
1583 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1584 uint64_t c2 = N1C->getValue();
1585 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1586 DAG.getConstant(~0ULL << c1, VT));
1588 return DAG.getNode(ISD::SHL, VT, Mask,
1589 DAG.getConstant(c2-c1, N1.getValueType()));
1591 return DAG.getNode(ISD::SRL, VT, Mask,
1592 DAG.getConstant(c1-c2, N1.getValueType()));
1594 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1595 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1596 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1597 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1598 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
1599 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1600 isa<ConstantSDNode>(N0.getOperand(1))) {
1601 return DAG.getNode(ISD::ADD, VT,
1602 DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1),
1603 DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1));
1608 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1609 SDOperand N0 = N->getOperand(0);
1610 SDOperand N1 = N->getOperand(1);
1611 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1612 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1613 MVT::ValueType VT = N0.getValueType();
1615 // fold (sra c1, c2) -> c1>>c2
1617 return DAG.getNode(ISD::SRA, VT, N0, N1);
1618 // fold (sra 0, x) -> 0
1619 if (N0C && N0C->isNullValue())
1621 // fold (sra -1, x) -> -1
1622 if (N0C && N0C->isAllOnesValue())
1624 // fold (sra x, c >= size(x)) -> undef
1625 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
1626 return DAG.getNode(ISD::UNDEF, VT);
1627 // fold (sra x, 0) -> x
1628 if (N1C && N1C->isNullValue())
1630 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
1632 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
1633 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
1636 default: EVT = MVT::Other; break;
1637 case 1: EVT = MVT::i1; break;
1638 case 8: EVT = MVT::i8; break;
1639 case 16: EVT = MVT::i16; break;
1640 case 32: EVT = MVT::i32; break;
1642 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
1643 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1644 DAG.getValueType(EVT));
1647 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
1648 if (N1C && N0.getOpcode() == ISD::SRA) {
1649 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1650 unsigned Sum = N1C->getValue() + C1->getValue();
1651 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
1652 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
1653 DAG.getConstant(Sum, N1C->getValueType(0)));
1657 // Simplify, based on bits shifted out of the LHS.
1658 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
1659 return SDOperand(N, 0);
1662 // If the sign bit is known to be zero, switch this to a SRL.
1663 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
1664 return DAG.getNode(ISD::SRL, VT, N0, N1);
1668 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1669 SDOperand N0 = N->getOperand(0);
1670 SDOperand N1 = N->getOperand(1);
1671 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1672 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1673 MVT::ValueType VT = N0.getValueType();
1674 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1676 // fold (srl c1, c2) -> c1 >>u c2
1678 return DAG.getNode(ISD::SRL, VT, N0, N1);
1679 // fold (srl 0, x) -> 0
1680 if (N0C && N0C->isNullValue())
1682 // fold (srl x, c >= size(x)) -> undef
1683 if (N1C && N1C->getValue() >= OpSizeInBits)
1684 return DAG.getNode(ISD::UNDEF, VT);
1685 // fold (srl x, 0) -> x
1686 if (N1C && N1C->isNullValue())
1688 // if (srl x, c) is known to be zero, return 0
1689 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1690 return DAG.getConstant(0, VT);
1691 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1692 if (N1C && N0.getOpcode() == ISD::SRL &&
1693 N0.getOperand(1).getOpcode() == ISD::Constant) {
1694 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1695 uint64_t c2 = N1C->getValue();
1696 if (c1 + c2 > OpSizeInBits)
1697 return DAG.getConstant(0, VT);
1698 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1699 DAG.getConstant(c1 + c2, N1.getValueType()));
1702 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
1703 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1704 // Shifting in all undef bits?
1705 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
1706 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
1707 return DAG.getNode(ISD::UNDEF, VT);
1709 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
1710 AddToWorkList(SmallShift.Val);
1711 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
1714 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
1715 // bit, which is unmodified by sra.
1716 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
1717 if (N0.getOpcode() == ISD::SRA)
1718 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
1721 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
1722 if (N1C && N0.getOpcode() == ISD::CTLZ &&
1723 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
1724 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
1725 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
1727 // If any of the input bits are KnownOne, then the input couldn't be all
1728 // zeros, thus the result of the srl will always be zero.
1729 if (KnownOne) return DAG.getConstant(0, VT);
1731 // If all of the bits input the to ctlz node are known to be zero, then
1732 // the result of the ctlz is "32" and the result of the shift is one.
1733 uint64_t UnknownBits = ~KnownZero & Mask;
1734 if (UnknownBits == 0) return DAG.getConstant(1, VT);
1736 // Otherwise, check to see if there is exactly one bit input to the ctlz.
1737 if ((UnknownBits & (UnknownBits-1)) == 0) {
1738 // Okay, we know that only that the single bit specified by UnknownBits
1739 // could be set on input to the CTLZ node. If this bit is set, the SRL
1740 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
1741 // to an SRL,XOR pair, which is likely to simplify more.
1742 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
1743 SDOperand Op = N0.getOperand(0);
1745 Op = DAG.getNode(ISD::SRL, VT, Op,
1746 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
1747 AddToWorkList(Op.Val);
1749 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
1756 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1757 SDOperand N0 = N->getOperand(0);
1758 MVT::ValueType VT = N->getValueType(0);
1760 // fold (ctlz c1) -> c2
1761 if (isa<ConstantSDNode>(N0))
1762 return DAG.getNode(ISD::CTLZ, VT, N0);
1766 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1767 SDOperand N0 = N->getOperand(0);
1768 MVT::ValueType VT = N->getValueType(0);
1770 // fold (cttz c1) -> c2
1771 if (isa<ConstantSDNode>(N0))
1772 return DAG.getNode(ISD::CTTZ, VT, N0);
1776 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1777 SDOperand N0 = N->getOperand(0);
1778 MVT::ValueType VT = N->getValueType(0);
1780 // fold (ctpop c1) -> c2
1781 if (isa<ConstantSDNode>(N0))
1782 return DAG.getNode(ISD::CTPOP, VT, N0);
1786 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1787 SDOperand N0 = N->getOperand(0);
1788 SDOperand N1 = N->getOperand(1);
1789 SDOperand N2 = N->getOperand(2);
1790 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1791 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1792 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1793 MVT::ValueType VT = N->getValueType(0);
1795 // fold select C, X, X -> X
1798 // fold select true, X, Y -> X
1799 if (N0C && !N0C->isNullValue())
1801 // fold select false, X, Y -> Y
1802 if (N0C && N0C->isNullValue())
1804 // fold select C, 1, X -> C | X
1805 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1806 return DAG.getNode(ISD::OR, VT, N0, N2);
1807 // fold select C, 0, X -> ~C & X
1808 // FIXME: this should check for C type == X type, not i1?
1809 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1810 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1811 AddToWorkList(XORNode.Val);
1812 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1814 // fold select C, X, 1 -> ~C | X
1815 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1816 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1817 AddToWorkList(XORNode.Val);
1818 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1820 // fold select C, X, 0 -> C & X
1821 // FIXME: this should check for C type == X type, not i1?
1822 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1823 return DAG.getNode(ISD::AND, VT, N0, N1);
1824 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1825 if (MVT::i1 == VT && N0 == N1)
1826 return DAG.getNode(ISD::OR, VT, N0, N2);
1827 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1828 if (MVT::i1 == VT && N0 == N2)
1829 return DAG.getNode(ISD::AND, VT, N0, N1);
1831 // If we can fold this based on the true/false value, do so.
1832 if (SimplifySelectOps(N, N1, N2))
1833 return SDOperand(N, 0); // Don't revisit N.
1835 // fold selects based on a setcc into other things, such as min/max/abs
1836 if (N0.getOpcode() == ISD::SETCC)
1838 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1839 // having to say they don't support SELECT_CC on every type the DAG knows
1840 // about, since there is no way to mark an opcode illegal at all value types
1841 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1842 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1843 N1, N2, N0.getOperand(2));
1845 return SimplifySelect(N0, N1, N2);
1849 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1850 SDOperand N0 = N->getOperand(0);
1851 SDOperand N1 = N->getOperand(1);
1852 SDOperand N2 = N->getOperand(2);
1853 SDOperand N3 = N->getOperand(3);
1854 SDOperand N4 = N->getOperand(4);
1855 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1856 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1857 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1858 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1860 // fold select_cc lhs, rhs, x, x, cc -> x
1864 // Determine if the condition we're dealing with is constant
1865 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1866 if (SCC.Val) AddToWorkList(SCC.Val);
1868 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
1869 if (SCCC->getValue())
1870 return N2; // cond always true -> true val
1872 return N3; // cond always false -> false val
1875 // Fold to a simpler select_cc
1876 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
1877 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
1878 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
1881 // If we can fold this based on the true/false value, do so.
1882 if (SimplifySelectOps(N, N2, N3))
1883 return SDOperand(N, 0); // Don't revisit N.
1885 // fold select_cc into other things, such as min/max/abs
1886 return SimplifySelectCC(N0, N1, N2, N3, CC);
1889 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1890 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1891 cast<CondCodeSDNode>(N->getOperand(2))->get());
1894 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1895 SDOperand N0 = N->getOperand(0);
1896 MVT::ValueType VT = N->getValueType(0);
1898 // fold (sext c1) -> c1
1899 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
1900 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
1902 // fold (sext (sext x)) -> (sext x)
1903 // fold (sext (aext x)) -> (sext x)
1904 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1905 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1907 // fold (sext (truncate x)) -> (sextinreg x).
1908 if (N0.getOpcode() == ISD::TRUNCATE &&
1909 (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
1910 N0.getValueType()))) {
1911 SDOperand Op = N0.getOperand(0);
1912 if (Op.getValueType() < VT) {
1913 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
1914 } else if (Op.getValueType() > VT) {
1915 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
1917 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
1918 DAG.getValueType(N0.getValueType()));
1921 // fold (sext (load x)) -> (sext (truncate (sextload x)))
1922 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
1923 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
1924 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1925 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
1926 LN0->getBasePtr(), LN0->getSrcValue(),
1927 LN0->getSrcValueOffset(),
1929 CombineTo(N, ExtLoad);
1930 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1931 ExtLoad.getValue(1));
1932 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1935 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
1936 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
1937 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
1938 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1939 MVT::ValueType EVT = LN0->getLoadedVT();
1940 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
1941 LN0->getBasePtr(), LN0->getSrcValue(),
1942 LN0->getSrcValueOffset(), EVT);
1943 CombineTo(N, ExtLoad);
1944 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1945 ExtLoad.getValue(1));
1946 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1952 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1953 SDOperand N0 = N->getOperand(0);
1954 MVT::ValueType VT = N->getValueType(0);
1956 // fold (zext c1) -> c1
1957 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
1958 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1959 // fold (zext (zext x)) -> (zext x)
1960 // fold (zext (aext x)) -> (zext x)
1961 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1962 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1964 // fold (zext (truncate x)) -> (and x, mask)
1965 if (N0.getOpcode() == ISD::TRUNCATE &&
1966 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
1967 SDOperand Op = N0.getOperand(0);
1968 if (Op.getValueType() < VT) {
1969 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
1970 } else if (Op.getValueType() > VT) {
1971 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
1973 return DAG.getZeroExtendInReg(Op, N0.getValueType());
1976 // fold (zext (and (trunc x), cst)) -> (and x, cst).
1977 if (N0.getOpcode() == ISD::AND &&
1978 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
1979 N0.getOperand(1).getOpcode() == ISD::Constant) {
1980 SDOperand X = N0.getOperand(0).getOperand(0);
1981 if (X.getValueType() < VT) {
1982 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
1983 } else if (X.getValueType() > VT) {
1984 X = DAG.getNode(ISD::TRUNCATE, VT, X);
1986 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1987 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
1990 // fold (zext (load x)) -> (zext (truncate (zextload x)))
1991 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
1992 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
1993 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1994 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1995 LN0->getBasePtr(), LN0->getSrcValue(),
1996 LN0->getSrcValueOffset(),
1998 CombineTo(N, ExtLoad);
1999 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2000 ExtLoad.getValue(1));
2001 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2004 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
2005 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
2006 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
2007 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2008 MVT::ValueType EVT = LN0->getLoadedVT();
2009 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2010 LN0->getBasePtr(), LN0->getSrcValue(),
2011 LN0->getSrcValueOffset(), EVT);
2012 CombineTo(N, ExtLoad);
2013 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2014 ExtLoad.getValue(1));
2015 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2020 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
2021 SDOperand N0 = N->getOperand(0);
2022 MVT::ValueType VT = N->getValueType(0);
2024 // fold (aext c1) -> c1
2025 if (isa<ConstantSDNode>(N0))
2026 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
2027 // fold (aext (aext x)) -> (aext x)
2028 // fold (aext (zext x)) -> (zext x)
2029 // fold (aext (sext x)) -> (sext x)
2030 if (N0.getOpcode() == ISD::ANY_EXTEND ||
2031 N0.getOpcode() == ISD::ZERO_EXTEND ||
2032 N0.getOpcode() == ISD::SIGN_EXTEND)
2033 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2035 // fold (aext (truncate x))
2036 if (N0.getOpcode() == ISD::TRUNCATE) {
2037 SDOperand TruncOp = N0.getOperand(0);
2038 if (TruncOp.getValueType() == VT)
2039 return TruncOp; // x iff x size == zext size.
2040 if (TruncOp.getValueType() > VT)
2041 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
2042 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
2045 // fold (aext (and (trunc x), cst)) -> (and x, cst).
2046 if (N0.getOpcode() == ISD::AND &&
2047 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2048 N0.getOperand(1).getOpcode() == ISD::Constant) {
2049 SDOperand X = N0.getOperand(0).getOperand(0);
2050 if (X.getValueType() < VT) {
2051 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2052 } else if (X.getValueType() > VT) {
2053 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2055 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2056 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2059 // fold (aext (load x)) -> (aext (truncate (extload x)))
2060 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2061 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2062 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2063 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2064 LN0->getBasePtr(), LN0->getSrcValue(),
2065 LN0->getSrcValueOffset(),
2067 CombineTo(N, ExtLoad);
2068 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2069 ExtLoad.getValue(1));
2070 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2073 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2074 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2075 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2076 if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.Val) &&
2078 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2079 MVT::ValueType EVT = LN0->getLoadedVT();
2080 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2081 LN0->getChain(), LN0->getBasePtr(),
2083 LN0->getSrcValueOffset(), EVT);
2084 CombineTo(N, ExtLoad);
2085 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2086 ExtLoad.getValue(1));
2087 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2093 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
2094 SDOperand N0 = N->getOperand(0);
2095 SDOperand N1 = N->getOperand(1);
2096 MVT::ValueType VT = N->getValueType(0);
2097 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
2098 unsigned EVTBits = MVT::getSizeInBits(EVT);
2100 // fold (sext_in_reg c1) -> c1
2101 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
2102 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
2104 // If the input is already sign extended, just drop the extension.
2105 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
2108 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
2109 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2110 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
2111 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
2114 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
2115 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
2116 return DAG.getZeroExtendInReg(N0, EVT);
2118 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
2119 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
2120 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
2121 if (N0.getOpcode() == ISD::SRL) {
2122 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2123 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
2124 // We can turn this into an SRA iff the input to the SRL is already sign
2126 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0));
2127 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
2128 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
2132 // fold (sext_inreg (extload x)) -> (sextload x)
2133 if (ISD::isEXTLoad(N0.Val) &&
2134 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2135 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2136 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2137 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2138 LN0->getBasePtr(), LN0->getSrcValue(),
2139 LN0->getSrcValueOffset(), EVT);
2140 CombineTo(N, ExtLoad);
2141 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2142 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2144 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
2145 if (ISD::isZEXTLoad(N0.Val) && N0.hasOneUse() &&
2146 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2147 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2148 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2149 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2150 LN0->getBasePtr(), LN0->getSrcValue(),
2151 LN0->getSrcValueOffset(), EVT);
2152 CombineTo(N, ExtLoad);
2153 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2154 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2159 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
2160 SDOperand N0 = N->getOperand(0);
2161 MVT::ValueType VT = N->getValueType(0);
2164 if (N0.getValueType() == N->getValueType(0))
2166 // fold (truncate c1) -> c1
2167 if (isa<ConstantSDNode>(N0))
2168 return DAG.getNode(ISD::TRUNCATE, VT, N0);
2169 // fold (truncate (truncate x)) -> (truncate x)
2170 if (N0.getOpcode() == ISD::TRUNCATE)
2171 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2172 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
2173 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
2174 N0.getOpcode() == ISD::ANY_EXTEND) {
2175 if (N0.getValueType() < VT)
2176 // if the source is smaller than the dest, we still need an extend
2177 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2178 else if (N0.getValueType() > VT)
2179 // if the source is larger than the dest, than we just need the truncate
2180 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2182 // if the source and dest are the same type, we can drop both the extend
2184 return N0.getOperand(0);
2186 // fold (truncate (load x)) -> (smaller load x)
2187 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) {
2188 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
2189 "Cannot truncate to larger type!");
2190 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2191 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2192 // For big endian targets, we need to add an offset to the pointer to load
2193 // the correct bytes. For little endian systems, we merely need to read
2194 // fewer bytes from the same pointer.
2196 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
2197 SDOperand NewPtr = TLI.isLittleEndian() ? LN0->getBasePtr() :
2198 DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
2199 DAG.getConstant(PtrOff, PtrType));
2200 AddToWorkList(NewPtr.Val);
2201 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), NewPtr,
2202 LN0->getSrcValue(), LN0->getSrcValueOffset());
2204 CombineTo(N0.Val, Load, Load.getValue(1));
2205 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2210 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
2211 SDOperand N0 = N->getOperand(0);
2212 MVT::ValueType VT = N->getValueType(0);
2214 // If the input is a constant, let getNode() fold it.
2215 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
2216 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2217 if (Res.Val != N) return Res;
2220 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
2221 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
2223 // fold (conv (load x)) -> (load (conv*)x)
2224 // FIXME: These xforms need to know that the resultant load doesn't need a
2225 // higher alignment than the original!
2226 if (0 && ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) {
2227 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2228 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
2229 LN0->getSrcValue(), LN0->getSrcValueOffset());
2231 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
2239 SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) {
2240 SDOperand N0 = N->getOperand(0);
2241 MVT::ValueType VT = N->getValueType(0);
2243 // If the input is a VBUILD_VECTOR with all constant elements, fold this now.
2244 // First check to see if this is all constant.
2245 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() &&
2246 VT == MVT::Vector) {
2247 bool isSimple = true;
2248 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i)
2249 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
2250 N0.getOperand(i).getOpcode() != ISD::Constant &&
2251 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
2256 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT();
2257 if (isSimple && !MVT::isVector(DestEltVT)) {
2258 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT);
2265 /// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector
2266 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
2267 /// destination element value type.
2268 SDOperand DAGCombiner::
2269 ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
2270 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
2272 // If this is already the right type, we're done.
2273 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
2275 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
2276 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
2278 // If this is a conversion of N elements of one type to N elements of another
2279 // type, convert each element. This handles FP<->INT cases.
2280 if (SrcBitSize == DstBitSize) {
2281 SmallVector<SDOperand, 8> Ops;
2282 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2283 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
2284 AddToWorkList(Ops.back().Val);
2286 Ops.push_back(*(BV->op_end()-2)); // Add num elements.
2287 Ops.push_back(DAG.getValueType(DstEltVT));
2288 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2291 // Otherwise, we're growing or shrinking the elements. To avoid having to
2292 // handle annoying details of growing/shrinking FP values, we convert them to
2294 if (MVT::isFloatingPoint(SrcEltVT)) {
2295 // Convert the input float vector to a int vector where the elements are the
2297 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
2298 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2299 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val;
2303 // Now we know the input is an integer vector. If the output is a FP type,
2304 // convert to integer first, then to FP of the right size.
2305 if (MVT::isFloatingPoint(DstEltVT)) {
2306 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
2307 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2308 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val;
2310 // Next, convert to FP elements of the same size.
2311 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT);
2314 // Okay, we know the src/dst types are both integers of differing types.
2315 // Handling growing first.
2316 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
2317 if (SrcBitSize < DstBitSize) {
2318 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
2320 SmallVector<SDOperand, 8> Ops;
2321 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e;
2322 i += NumInputsPerOutput) {
2323 bool isLE = TLI.isLittleEndian();
2324 uint64_t NewBits = 0;
2325 bool EltIsUndef = true;
2326 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
2327 // Shift the previously computed bits over.
2328 NewBits <<= SrcBitSize;
2329 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
2330 if (Op.getOpcode() == ISD::UNDEF) continue;
2333 NewBits |= cast<ConstantSDNode>(Op)->getValue();
2337 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2339 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
2342 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2343 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2344 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2347 // Finally, this must be the case where we are shrinking elements: each input
2348 // turns into multiple outputs.
2349 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
2350 SmallVector<SDOperand, 8> Ops;
2351 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2352 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
2353 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
2354 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2357 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
2359 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
2360 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
2361 OpVal >>= DstBitSize;
2362 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
2365 // For big endian targets, swap the order of the pieces of each element.
2366 if (!TLI.isLittleEndian())
2367 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
2369 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2370 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2371 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2376 SDOperand DAGCombiner::visitFADD(SDNode *N) {
2377 SDOperand N0 = N->getOperand(0);
2378 SDOperand N1 = N->getOperand(1);
2379 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2380 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2381 MVT::ValueType VT = N->getValueType(0);
2383 // fold (fadd c1, c2) -> c1+c2
2385 return DAG.getNode(ISD::FADD, VT, N0, N1);
2386 // canonicalize constant to RHS
2387 if (N0CFP && !N1CFP)
2388 return DAG.getNode(ISD::FADD, VT, N1, N0);
2389 // fold (A + (-B)) -> A-B
2390 if (N1.getOpcode() == ISD::FNEG)
2391 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
2392 // fold ((-A) + B) -> B-A
2393 if (N0.getOpcode() == ISD::FNEG)
2394 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
2398 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
2399 SDOperand N0 = N->getOperand(0);
2400 SDOperand N1 = N->getOperand(1);
2401 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2402 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2403 MVT::ValueType VT = N->getValueType(0);
2405 // fold (fsub c1, c2) -> c1-c2
2407 return DAG.getNode(ISD::FSUB, VT, N0, N1);
2408 // fold (A-(-B)) -> A+B
2409 if (N1.getOpcode() == ISD::FNEG)
2410 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
2414 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
2415 SDOperand N0 = N->getOperand(0);
2416 SDOperand N1 = N->getOperand(1);
2417 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2418 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2419 MVT::ValueType VT = N->getValueType(0);
2421 // fold (fmul c1, c2) -> c1*c2
2423 return DAG.getNode(ISD::FMUL, VT, N0, N1);
2424 // canonicalize constant to RHS
2425 if (N0CFP && !N1CFP)
2426 return DAG.getNode(ISD::FMUL, VT, N1, N0);
2427 // fold (fmul X, 2.0) -> (fadd X, X)
2428 if (N1CFP && N1CFP->isExactlyValue(+2.0))
2429 return DAG.getNode(ISD::FADD, VT, N0, N0);
2433 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
2434 SDOperand N0 = N->getOperand(0);
2435 SDOperand N1 = N->getOperand(1);
2436 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2437 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2438 MVT::ValueType VT = N->getValueType(0);
2440 // fold (fdiv c1, c2) -> c1/c2
2442 return DAG.getNode(ISD::FDIV, VT, N0, N1);
2446 SDOperand DAGCombiner::visitFREM(SDNode *N) {
2447 SDOperand N0 = N->getOperand(0);
2448 SDOperand N1 = N->getOperand(1);
2449 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2450 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2451 MVT::ValueType VT = N->getValueType(0);
2453 // fold (frem c1, c2) -> fmod(c1,c2)
2455 return DAG.getNode(ISD::FREM, VT, N0, N1);
2459 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
2460 SDOperand N0 = N->getOperand(0);
2461 SDOperand N1 = N->getOperand(1);
2462 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2463 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2464 MVT::ValueType VT = N->getValueType(0);
2466 if (N0CFP && N1CFP) // Constant fold
2467 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
2470 // copysign(x, c1) -> fabs(x) iff ispos(c1)
2471 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
2476 u.d = N1CFP->getValue();
2478 return DAG.getNode(ISD::FABS, VT, N0);
2480 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
2483 // copysign(fabs(x), y) -> copysign(x, y)
2484 // copysign(fneg(x), y) -> copysign(x, y)
2485 // copysign(copysign(x,z), y) -> copysign(x, y)
2486 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
2487 N0.getOpcode() == ISD::FCOPYSIGN)
2488 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
2490 // copysign(x, abs(y)) -> abs(x)
2491 if (N1.getOpcode() == ISD::FABS)
2492 return DAG.getNode(ISD::FABS, VT, N0);
2494 // copysign(x, copysign(y,z)) -> copysign(x, z)
2495 if (N1.getOpcode() == ISD::FCOPYSIGN)
2496 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
2498 // copysign(x, fp_extend(y)) -> copysign(x, y)
2499 // copysign(x, fp_round(y)) -> copysign(x, y)
2500 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
2501 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
2508 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
2509 SDOperand N0 = N->getOperand(0);
2510 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2511 MVT::ValueType VT = N->getValueType(0);
2513 // fold (sint_to_fp c1) -> c1fp
2515 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
2519 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
2520 SDOperand N0 = N->getOperand(0);
2521 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2522 MVT::ValueType VT = N->getValueType(0);
2524 // fold (uint_to_fp c1) -> c1fp
2526 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
2530 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
2531 SDOperand N0 = N->getOperand(0);
2532 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2533 MVT::ValueType VT = N->getValueType(0);
2535 // fold (fp_to_sint c1fp) -> c1
2537 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
2541 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
2542 SDOperand N0 = N->getOperand(0);
2543 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2544 MVT::ValueType VT = N->getValueType(0);
2546 // fold (fp_to_uint c1fp) -> c1
2548 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
2552 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
2553 SDOperand N0 = N->getOperand(0);
2554 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2555 MVT::ValueType VT = N->getValueType(0);
2557 // fold (fp_round c1fp) -> c1fp
2559 return DAG.getNode(ISD::FP_ROUND, VT, N0);
2561 // fold (fp_round (fp_extend x)) -> x
2562 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
2563 return N0.getOperand(0);
2565 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
2566 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
2567 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
2568 AddToWorkList(Tmp.Val);
2569 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
2575 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
2576 SDOperand N0 = N->getOperand(0);
2577 MVT::ValueType VT = N->getValueType(0);
2578 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2579 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2581 // fold (fp_round_inreg c1fp) -> c1fp
2583 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
2584 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
2589 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
2590 SDOperand N0 = N->getOperand(0);
2591 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2592 MVT::ValueType VT = N->getValueType(0);
2594 // fold (fp_extend c1fp) -> c1fp
2596 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
2598 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
2599 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2600 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2601 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2602 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2603 LN0->getBasePtr(), LN0->getSrcValue(),
2604 LN0->getSrcValueOffset(),
2606 CombineTo(N, ExtLoad);
2607 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
2608 ExtLoad.getValue(1));
2609 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2616 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
2617 SDOperand N0 = N->getOperand(0);
2618 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2619 MVT::ValueType VT = N->getValueType(0);
2621 // fold (fneg c1) -> -c1
2623 return DAG.getNode(ISD::FNEG, VT, N0);
2624 // fold (fneg (sub x, y)) -> (sub y, x)
2625 if (N0.getOpcode() == ISD::SUB)
2626 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0));
2627 // fold (fneg (fneg x)) -> x
2628 if (N0.getOpcode() == ISD::FNEG)
2629 return N0.getOperand(0);
2633 SDOperand DAGCombiner::visitFABS(SDNode *N) {
2634 SDOperand N0 = N->getOperand(0);
2635 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2636 MVT::ValueType VT = N->getValueType(0);
2638 // fold (fabs c1) -> fabs(c1)
2640 return DAG.getNode(ISD::FABS, VT, N0);
2641 // fold (fabs (fabs x)) -> (fabs x)
2642 if (N0.getOpcode() == ISD::FABS)
2643 return N->getOperand(0);
2644 // fold (fabs (fneg x)) -> (fabs x)
2645 // fold (fabs (fcopysign x, y)) -> (fabs x)
2646 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
2647 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
2652 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
2653 SDOperand Chain = N->getOperand(0);
2654 SDOperand N1 = N->getOperand(1);
2655 SDOperand N2 = N->getOperand(2);
2656 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2658 // never taken branch, fold to chain
2659 if (N1C && N1C->isNullValue())
2661 // unconditional branch
2662 if (N1C && N1C->getValue() == 1)
2663 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2664 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
2666 if (N1.getOpcode() == ISD::SETCC &&
2667 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
2668 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
2669 N1.getOperand(0), N1.getOperand(1), N2);
2674 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
2676 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
2677 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2678 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2680 // Use SimplifySetCC to simplify SETCC's.
2681 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2682 if (Simp.Val) AddToWorkList(Simp.Val);
2684 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2686 // fold br_cc true, dest -> br dest (unconditional branch)
2687 if (SCCC && SCCC->getValue())
2688 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2690 // fold br_cc false, dest -> unconditional fall through
2691 if (SCCC && SCCC->isNullValue())
2692 return N->getOperand(0);
2694 // fold to a simpler setcc
2695 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2696 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2697 Simp.getOperand(2), Simp.getOperand(0),
2698 Simp.getOperand(1), N->getOperand(4));
2702 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
2703 LoadSDNode *LD = cast<LoadSDNode>(N);
2704 SDOperand Chain = LD->getChain();
2705 SDOperand Ptr = LD->getBasePtr();
2707 // If there are no uses of the loaded value, change uses of the chain value
2708 // into uses of the chain input (i.e. delete the dead load).
2709 if (N->hasNUsesOfValue(0, 0))
2710 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
2712 // If this load is directly stored, replace the load value with the stored
2714 // TODO: Handle store large -> read small portion.
2715 // TODO: Handle TRUNCSTORE/LOADEXT
2716 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
2717 if (ISD::isNON_TRUNCStore(Chain.Val)) {
2718 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
2719 if (PrevST->getBasePtr() == Ptr &&
2720 PrevST->getValue().getValueType() == N->getValueType(0))
2721 return CombineTo(N, Chain.getOperand(1), Chain);
2726 // Walk up chain skipping non-aliasing memory nodes.
2727 SDOperand BetterChain = FindBetterChain(N, Chain);
2729 // If there is a better chain.
2730 if (Chain != BetterChain) {
2733 // Replace the chain to void dependency.
2734 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
2735 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
2736 LD->getSrcValue(), LD->getSrcValueOffset());
2738 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
2739 LD->getValueType(0),
2740 BetterChain, Ptr, LD->getSrcValue(),
2741 LD->getSrcValueOffset(),
2745 // Create token factor to keep old chain connected.
2746 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
2747 Chain, ReplLoad.getValue(1));
2749 // Replace uses with load result and token factor. Don't add users
2751 return CombineTo(N, ReplLoad.getValue(0), Token, false);
2758 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
2759 StoreSDNode *ST = cast<StoreSDNode>(N);
2760 SDOperand Chain = ST->getChain();
2761 SDOperand Value = ST->getValue();
2762 SDOperand Ptr = ST->getBasePtr();
2764 // If this is a store of a bit convert, store the input value.
2765 // FIXME: This needs to know that the resultant store does not need a
2766 // higher alignment than the original.
2767 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) {
2768 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
2769 ST->getSrcValueOffset());
2773 // Walk up chain skipping non-aliasing memory nodes.
2774 SDOperand BetterChain = FindBetterChain(N, Chain);
2776 // If there is a better chain.
2777 if (Chain != BetterChain) {
2778 // Replace the chain to avoid dependency.
2779 SDOperand ReplStore;
2780 if (ST->isTruncatingStore()) {
2781 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
2782 ST->getSrcValue(),ST->getSrcValueOffset(), ST->getStoredVT());
2784 ReplStore = DAG.getStore(BetterChain, Value, Ptr,
2785 ST->getSrcValue(), ST->getSrcValueOffset());
2788 // Create token to keep both nodes around.
2790 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
2792 // Don't add users to work list.
2793 return CombineTo(N, Token, false);
2800 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
2801 SDOperand InVec = N->getOperand(0);
2802 SDOperand InVal = N->getOperand(1);
2803 SDOperand EltNo = N->getOperand(2);
2805 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
2806 // vector with the inserted element.
2807 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2808 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2809 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2810 if (Elt < Ops.size())
2812 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
2813 &Ops[0], Ops.size());
2819 SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
2820 SDOperand InVec = N->getOperand(0);
2821 SDOperand InVal = N->getOperand(1);
2822 SDOperand EltNo = N->getOperand(2);
2823 SDOperand NumElts = N->getOperand(3);
2824 SDOperand EltType = N->getOperand(4);
2826 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new
2827 // vector with the inserted element.
2828 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2829 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2830 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2831 if (Elt < Ops.size()-2)
2833 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(),
2834 &Ops[0], Ops.size());
2840 SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
2841 unsigned NumInScalars = N->getNumOperands()-2;
2842 SDOperand NumElts = N->getOperand(NumInScalars);
2843 SDOperand EltType = N->getOperand(NumInScalars+1);
2845 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT
2846 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most
2847 // two distinct vectors, turn this into a shuffle node.
2848 SDOperand VecIn1, VecIn2;
2849 for (unsigned i = 0; i != NumInScalars; ++i) {
2850 // Ignore undef inputs.
2851 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
2853 // If this input is something other than a VEXTRACT_VECTOR_ELT with a
2854 // constant index, bail out.
2855 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT ||
2856 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
2857 VecIn1 = VecIn2 = SDOperand(0, 0);
2861 // If the input vector type disagrees with the result of the vbuild_vector,
2862 // we can't make a shuffle.
2863 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
2864 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts ||
2865 *(ExtractedFromVec.Val->op_end()-1) != EltType) {
2866 VecIn1 = VecIn2 = SDOperand(0, 0);
2870 // Otherwise, remember this. We allow up to two distinct input vectors.
2871 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
2874 if (VecIn1.Val == 0) {
2875 VecIn1 = ExtractedFromVec;
2876 } else if (VecIn2.Val == 0) {
2877 VecIn2 = ExtractedFromVec;
2880 VecIn1 = VecIn2 = SDOperand(0, 0);
2885 // If everything is good, we can make a shuffle operation.
2887 SmallVector<SDOperand, 8> BuildVecIndices;
2888 for (unsigned i = 0; i != NumInScalars; ++i) {
2889 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
2890 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
2894 SDOperand Extract = N->getOperand(i);
2896 // If extracting from the first vector, just use the index directly.
2897 if (Extract.getOperand(0) == VecIn1) {
2898 BuildVecIndices.push_back(Extract.getOperand(1));
2902 // Otherwise, use InIdx + VecSize
2903 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
2904 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32));
2907 // Add count and size info.
2908 BuildVecIndices.push_back(NumElts);
2909 BuildVecIndices.push_back(DAG.getValueType(MVT::i32));
2911 // Return the new VVECTOR_SHUFFLE node.
2917 // Use an undef vbuild_vector as input for the second operand.
2918 std::vector<SDOperand> UnOps(NumInScalars,
2919 DAG.getNode(ISD::UNDEF,
2920 cast<VTSDNode>(EltType)->getVT()));
2921 UnOps.push_back(NumElts);
2922 UnOps.push_back(EltType);
2923 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
2924 &UnOps[0], UnOps.size());
2925 AddToWorkList(Ops[1].Val);
2927 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
2928 &BuildVecIndices[0], BuildVecIndices.size());
2931 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5);
2937 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
2938 SDOperand ShufMask = N->getOperand(2);
2939 unsigned NumElts = ShufMask.getNumOperands();
2941 // If the shuffle mask is an identity operation on the LHS, return the LHS.
2942 bool isIdentity = true;
2943 for (unsigned i = 0; i != NumElts; ++i) {
2944 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2945 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
2950 if (isIdentity) return N->getOperand(0);
2952 // If the shuffle mask is an identity operation on the RHS, return the RHS.
2954 for (unsigned i = 0; i != NumElts; ++i) {
2955 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2956 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
2961 if (isIdentity) return N->getOperand(1);
2963 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
2965 bool isUnary = true;
2966 bool isSplat = true;
2968 unsigned BaseIdx = 0;
2969 for (unsigned i = 0; i != NumElts; ++i)
2970 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
2971 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
2972 int V = (Idx < NumElts) ? 0 : 1;
2986 SDOperand N0 = N->getOperand(0);
2987 SDOperand N1 = N->getOperand(1);
2988 // Normalize unary shuffle so the RHS is undef.
2989 if (isUnary && VecNum == 1)
2992 // If it is a splat, check if the argument vector is a build_vector with
2993 // all scalar elements the same.
2996 if (V->getOpcode() == ISD::BIT_CONVERT)
2997 V = V->getOperand(0).Val;
2998 if (V->getOpcode() == ISD::BUILD_VECTOR) {
2999 unsigned NumElems = V->getNumOperands()-2;
3000 if (NumElems > BaseIdx) {
3002 bool AllSame = true;
3003 for (unsigned i = 0; i != NumElems; ++i) {
3004 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3005 Base = V->getOperand(i);
3009 // Splat of <u, u, u, u>, return <u, u, u, u>
3012 for (unsigned i = 0; i != NumElems; ++i) {
3013 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3014 V->getOperand(i) != Base) {
3019 // Splat of <x, x, x, x>, return <x, x, x, x>
3026 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3028 if (isUnary || N0 == N1) {
3029 if (N0.getOpcode() == ISD::UNDEF)
3030 return DAG.getNode(ISD::UNDEF, N->getValueType(0));
3031 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3033 SmallVector<SDOperand, 8> MappedOps;
3034 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
3035 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3036 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3037 MappedOps.push_back(ShufMask.getOperand(i));
3040 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3041 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3044 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
3045 &MappedOps[0], MappedOps.size());
3046 AddToWorkList(ShufMask.Val);
3047 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
3049 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
3056 SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
3057 SDOperand ShufMask = N->getOperand(2);
3058 unsigned NumElts = ShufMask.getNumOperands()-2;
3060 // If the shuffle mask is an identity operation on the LHS, return the LHS.
3061 bool isIdentity = true;
3062 for (unsigned i = 0; i != NumElts; ++i) {
3063 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3064 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
3069 if (isIdentity) return N->getOperand(0);
3071 // If the shuffle mask is an identity operation on the RHS, return the RHS.
3073 for (unsigned i = 0; i != NumElts; ++i) {
3074 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3075 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
3080 if (isIdentity) return N->getOperand(1);
3082 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
3084 bool isUnary = true;
3085 bool isSplat = true;
3087 unsigned BaseIdx = 0;
3088 for (unsigned i = 0; i != NumElts; ++i)
3089 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
3090 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
3091 int V = (Idx < NumElts) ? 0 : 1;
3105 SDOperand N0 = N->getOperand(0);
3106 SDOperand N1 = N->getOperand(1);
3107 // Normalize unary shuffle so the RHS is undef.
3108 if (isUnary && VecNum == 1)
3111 // If it is a splat, check if the argument vector is a build_vector with
3112 // all scalar elements the same.
3116 // If this is a vbit convert that changes the element type of the vector but
3117 // not the number of vector elements, look through it. Be careful not to
3118 // look though conversions that change things like v4f32 to v2f64.
3119 if (V->getOpcode() == ISD::VBIT_CONVERT) {
3120 SDOperand ConvInput = V->getOperand(0);
3121 if (ConvInput.getValueType() == MVT::Vector &&
3123 ConvInput.getConstantOperandVal(ConvInput.getNumOperands()-2))
3127 if (V->getOpcode() == ISD::VBUILD_VECTOR) {
3128 unsigned NumElems = V->getNumOperands()-2;
3129 if (NumElems > BaseIdx) {
3131 bool AllSame = true;
3132 for (unsigned i = 0; i != NumElems; ++i) {
3133 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3134 Base = V->getOperand(i);
3138 // Splat of <u, u, u, u>, return <u, u, u, u>
3141 for (unsigned i = 0; i != NumElems; ++i) {
3142 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3143 V->getOperand(i) != Base) {
3148 // Splat of <x, x, x, x>, return <x, x, x, x>
3155 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3157 if (isUnary || N0 == N1) {
3158 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3160 SmallVector<SDOperand, 8> MappedOps;
3161 for (unsigned i = 0; i != NumElts; ++i) {
3162 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3163 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3164 MappedOps.push_back(ShufMask.getOperand(i));
3167 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3168 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3171 // Add the type/#elts values.
3172 MappedOps.push_back(ShufMask.getOperand(NumElts));
3173 MappedOps.push_back(ShufMask.getOperand(NumElts+1));
3175 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(),
3176 &MappedOps[0], MappedOps.size());
3177 AddToWorkList(ShufMask.Val);
3179 // Build the undef vector.
3180 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType());
3181 for (unsigned i = 0; i != NumElts; ++i)
3182 MappedOps[i] = UDVal;
3183 MappedOps[NumElts ] = *(N0.Val->op_end()-2);
3184 MappedOps[NumElts+1] = *(N0.Val->op_end()-1);
3185 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3186 &MappedOps[0], MappedOps.size());
3188 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3189 N0, UDVal, ShufMask,
3190 MappedOps[NumElts], MappedOps[NumElts+1]);
3196 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
3197 /// a VAND to a vector_shuffle with the destination vector and a zero vector.
3198 /// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
3199 /// vector_shuffle V, Zero, <0, 4, 2, 4>
3200 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
3201 SDOperand LHS = N->getOperand(0);
3202 SDOperand RHS = N->getOperand(1);
3203 if (N->getOpcode() == ISD::VAND) {
3204 SDOperand DstVecSize = *(LHS.Val->op_end()-2);
3205 SDOperand DstVecEVT = *(LHS.Val->op_end()-1);
3206 if (RHS.getOpcode() == ISD::VBIT_CONVERT)
3207 RHS = RHS.getOperand(0);
3208 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3209 std::vector<SDOperand> IdxOps;
3210 unsigned NumOps = RHS.getNumOperands();
3211 unsigned NumElts = NumOps-2;
3212 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT();
3213 for (unsigned i = 0; i != NumElts; ++i) {
3214 SDOperand Elt = RHS.getOperand(i);
3215 if (!isa<ConstantSDNode>(Elt))
3217 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
3218 IdxOps.push_back(DAG.getConstant(i, EVT));
3219 else if (cast<ConstantSDNode>(Elt)->isNullValue())
3220 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
3225 // Let's see if the target supports this vector_shuffle.
3226 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
3229 // Return the new VVECTOR_SHUFFLE node.
3230 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32);
3231 SDOperand EVTNode = DAG.getValueType(EVT);
3232 std::vector<SDOperand> Ops;
3233 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode,
3236 AddToWorkList(LHS.Val);
3237 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
3238 ZeroOps.push_back(NumEltsNode);
3239 ZeroOps.push_back(EVTNode);
3240 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3241 &ZeroOps[0], ZeroOps.size()));
3242 IdxOps.push_back(NumEltsNode);
3243 IdxOps.push_back(EVTNode);
3244 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3245 &IdxOps[0], IdxOps.size()));
3246 Ops.push_back(NumEltsNode);
3247 Ops.push_back(EVTNode);
3248 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3249 &Ops[0], Ops.size());
3250 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) {
3251 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
3252 DstVecSize, DstVecEVT);
3260 /// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates
3261 /// the scalar operation of the vop if it is operating on an integer vector
3262 /// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD).
3263 SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
3264 ISD::NodeType FPOp) {
3265 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT();
3266 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp;
3267 SDOperand LHS = N->getOperand(0);
3268 SDOperand RHS = N->getOperand(1);
3269 SDOperand Shuffle = XformToShuffleWithZero(N);
3270 if (Shuffle.Val) return Shuffle;
3272 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold
3274 if (LHS.getOpcode() == ISD::VBUILD_VECTOR &&
3275 RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3276 SmallVector<SDOperand, 8> Ops;
3277 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
3278 SDOperand LHSOp = LHS.getOperand(i);
3279 SDOperand RHSOp = RHS.getOperand(i);
3280 // If these two elements can't be folded, bail out.
3281 if ((LHSOp.getOpcode() != ISD::UNDEF &&
3282 LHSOp.getOpcode() != ISD::Constant &&
3283 LHSOp.getOpcode() != ISD::ConstantFP) ||
3284 (RHSOp.getOpcode() != ISD::UNDEF &&
3285 RHSOp.getOpcode() != ISD::Constant &&
3286 RHSOp.getOpcode() != ISD::ConstantFP))
3288 // Can't fold divide by zero.
3289 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) {
3290 if ((RHSOp.getOpcode() == ISD::Constant &&
3291 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
3292 (RHSOp.getOpcode() == ISD::ConstantFP &&
3293 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue()))
3296 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
3297 AddToWorkList(Ops.back().Val);
3298 assert((Ops.back().getOpcode() == ISD::UNDEF ||
3299 Ops.back().getOpcode() == ISD::Constant ||
3300 Ops.back().getOpcode() == ISD::ConstantFP) &&
3301 "Scalar binop didn't fold!");
3304 if (Ops.size() == LHS.getNumOperands()-2) {
3305 Ops.push_back(*(LHS.Val->op_end()-2));
3306 Ops.push_back(*(LHS.Val->op_end()-1));
3307 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
3314 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
3315 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
3317 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
3318 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3319 // If we got a simplified select_cc node back from SimplifySelectCC, then
3320 // break it down into a new SETCC node, and a new SELECT node, and then return
3321 // the SELECT node, since we were called with a SELECT node.
3323 // Check to see if we got a select_cc back (to turn into setcc/select).
3324 // Otherwise, just return whatever node we got back, like fabs.
3325 if (SCC.getOpcode() == ISD::SELECT_CC) {
3326 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
3327 SCC.getOperand(0), SCC.getOperand(1),
3329 AddToWorkList(SETCC.Val);
3330 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
3331 SCC.getOperand(3), SETCC);
3338 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
3339 /// are the two values being selected between, see if we can simplify the
3340 /// select. Callers of this should assume that TheSelect is deleted if this
3341 /// returns true. As such, they should return the appropriate thing (e.g. the
3342 /// node) back to the top-level of the DAG combiner loop to avoid it being
3345 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
3348 // If this is a select from two identical things, try to pull the operation
3349 // through the select.
3350 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
3351 // If this is a load and the token chain is identical, replace the select
3352 // of two loads with a load through a select of the address to load from.
3353 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
3354 // constants have been dropped into the constant pool.
3355 if (LHS.getOpcode() == ISD::LOAD &&
3356 // Token chains must be identical.
3357 LHS.getOperand(0) == RHS.getOperand(0)) {
3358 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
3359 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
3361 // If this is an EXTLOAD, the VT's must match.
3362 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
3363 // FIXME: this conflates two src values, discarding one. This is not
3364 // the right thing to do, but nothing uses srcvalues now. When they do,
3365 // turn SrcValue into a list of locations.
3367 if (TheSelect->getOpcode() == ISD::SELECT)
3368 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
3369 TheSelect->getOperand(0), LLD->getBasePtr(),
3372 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
3373 TheSelect->getOperand(0),
3374 TheSelect->getOperand(1),
3375 LLD->getBasePtr(), RLD->getBasePtr(),
3376 TheSelect->getOperand(4));
3379 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
3380 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
3381 Addr,LLD->getSrcValue(), LLD->getSrcValueOffset());
3383 Load = DAG.getExtLoad(LLD->getExtensionType(),
3384 TheSelect->getValueType(0),
3385 LLD->getChain(), Addr, LLD->getSrcValue(),
3386 LLD->getSrcValueOffset(),
3387 LLD->getLoadedVT());
3389 // Users of the select now use the result of the load.
3390 CombineTo(TheSelect, Load);
3392 // Users of the old loads now use the new load's chain. We know the
3393 // old-load value is dead now.
3394 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
3395 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
3404 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
3405 SDOperand N2, SDOperand N3,
3408 MVT::ValueType VT = N2.getValueType();
3409 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
3410 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
3411 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
3413 // Determine if the condition we're dealing with is constant
3414 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
3415 if (SCC.Val) AddToWorkList(SCC.Val);
3416 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
3418 // fold select_cc true, x, y -> x
3419 if (SCCC && SCCC->getValue())
3421 // fold select_cc false, x, y -> y
3422 if (SCCC && SCCC->getValue() == 0)
3425 // Check to see if we can simplify the select into an fabs node
3426 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
3427 // Allow either -0.0 or 0.0
3428 if (CFP->getValue() == 0.0) {
3429 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
3430 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
3431 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
3432 N2 == N3.getOperand(0))
3433 return DAG.getNode(ISD::FABS, VT, N0);
3435 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
3436 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
3437 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
3438 N2.getOperand(0) == N3)
3439 return DAG.getNode(ISD::FABS, VT, N3);
3443 // Check to see if we can perform the "gzip trick", transforming
3444 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
3445 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
3446 MVT::isInteger(N0.getValueType()) &&
3447 MVT::isInteger(N2.getValueType()) &&
3448 (N1C->isNullValue() || // (a < 0) ? b : 0
3449 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
3450 MVT::ValueType XType = N0.getValueType();
3451 MVT::ValueType AType = N2.getValueType();
3452 if (XType >= AType) {
3453 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
3454 // single-bit constant.
3455 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
3456 unsigned ShCtV = Log2_64(N2C->getValue());
3457 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
3458 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
3459 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
3460 AddToWorkList(Shift.Val);
3461 if (XType > AType) {
3462 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3463 AddToWorkList(Shift.Val);
3465 return DAG.getNode(ISD::AND, AType, Shift, N2);
3467 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3468 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3469 TLI.getShiftAmountTy()));
3470 AddToWorkList(Shift.Val);
3471 if (XType > AType) {
3472 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3473 AddToWorkList(Shift.Val);
3475 return DAG.getNode(ISD::AND, AType, Shift, N2);
3479 // fold select C, 16, 0 -> shl C, 4
3480 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
3481 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
3482 // Get a SetCC of the condition
3483 // FIXME: Should probably make sure that setcc is legal if we ever have a
3484 // target where it isn't.
3485 SDOperand Temp, SCC;
3486 // cast from setcc result type to select result type
3487 if (AfterLegalize) {
3488 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3489 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
3491 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
3492 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
3494 AddToWorkList(SCC.Val);
3495 AddToWorkList(Temp.Val);
3496 // shl setcc result by log2 n2c
3497 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
3498 DAG.getConstant(Log2_64(N2C->getValue()),
3499 TLI.getShiftAmountTy()));
3502 // Check to see if this is the equivalent of setcc
3503 // FIXME: Turn all of these into setcc if setcc if setcc is legal
3504 // otherwise, go ahead with the folds.
3505 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
3506 MVT::ValueType XType = N0.getValueType();
3507 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
3508 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3509 if (Res.getValueType() != VT)
3510 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
3514 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
3515 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
3516 TLI.isOperationLegal(ISD::CTLZ, XType)) {
3517 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
3518 return DAG.getNode(ISD::SRL, XType, Ctlz,
3519 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
3520 TLI.getShiftAmountTy()));
3522 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
3523 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
3524 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
3526 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
3527 DAG.getConstant(~0ULL, XType));
3528 return DAG.getNode(ISD::SRL, XType,
3529 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
3530 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3531 TLI.getShiftAmountTy()));
3533 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
3534 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
3535 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
3536 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3537 TLI.getShiftAmountTy()));
3538 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
3542 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
3543 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
3544 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
3545 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
3546 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
3547 MVT::ValueType XType = N0.getValueType();
3548 if (SubC->isNullValue() && MVT::isInteger(XType)) {
3549 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3550 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3551 TLI.getShiftAmountTy()));
3552 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
3553 AddToWorkList(Shift.Val);
3554 AddToWorkList(Add.Val);
3555 return DAG.getNode(ISD::XOR, XType, Add, Shift);
3563 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
3564 SDOperand N1, ISD::CondCode Cond,
3565 bool foldBooleans) {
3566 // These setcc operations always fold.
3570 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
3572 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
3575 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
3576 uint64_t C1 = N1C->getValue();
3577 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
3578 return DAG.FoldSetCC(VT, N0, N1, Cond);
3580 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
3581 // equality comparison, then we're just comparing whether X itself is
3583 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
3584 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
3585 N0.getOperand(1).getOpcode() == ISD::Constant) {
3586 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
3587 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3588 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) {
3589 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
3590 // (srl (ctlz x), 5) == 0 -> X != 0
3591 // (srl (ctlz x), 5) != 1 -> X != 0
3594 // (srl (ctlz x), 5) != 0 -> X == 0
3595 // (srl (ctlz x), 5) == 1 -> X == 0
3598 SDOperand Zero = DAG.getConstant(0, N0.getValueType());
3599 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
3604 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
3605 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
3606 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
3608 // If the comparison constant has bits in the upper part, the
3609 // zero-extended value could never match.
3610 if (C1 & (~0ULL << InSize)) {
3611 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
3615 case ISD::SETEQ: return DAG.getConstant(0, VT);
3618 case ISD::SETNE: return DAG.getConstant(1, VT);
3621 // True if the sign bit of C1 is set.
3622 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
3625 // True if the sign bit of C1 isn't set.
3626 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
3632 // Otherwise, we can perform the comparison with the low bits.
3640 return DAG.getSetCC(VT, N0.getOperand(0),
3641 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
3644 break; // todo, be more careful with signed comparisons
3646 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3647 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3648 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
3649 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
3650 MVT::ValueType ExtDstTy = N0.getValueType();
3651 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
3653 // If the extended part has any inconsistent bits, it cannot ever
3654 // compare equal. In other words, they have to be all ones or all
3657 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
3658 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
3659 return DAG.getConstant(Cond == ISD::SETNE, VT);
3662 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
3663 if (Op0Ty == ExtSrcTy) {
3664 ZextOp = N0.getOperand(0);
3666 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
3667 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
3668 DAG.getConstant(Imm, Op0Ty));
3670 AddToWorkList(ZextOp.Val);
3671 // Otherwise, make this a use of a zext.
3672 return DAG.getSetCC(VT, ZextOp,
3673 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
3676 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
3677 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3679 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
3680 if (N0.getOpcode() == ISD::SETCC) {
3681 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1);
3685 // Invert the condition.
3686 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
3687 CC = ISD::getSetCCInverse(CC,
3688 MVT::isInteger(N0.getOperand(0).getValueType()));
3689 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC);
3692 if ((N0.getOpcode() == ISD::XOR ||
3693 (N0.getOpcode() == ISD::AND &&
3694 N0.getOperand(0).getOpcode() == ISD::XOR &&
3695 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
3696 isa<ConstantSDNode>(N0.getOperand(1)) &&
3697 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
3698 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
3699 // can only do this if the top bits are known zero.
3700 if (TLI.MaskedValueIsZero(N0,
3701 MVT::getIntVTBitMask(N0.getValueType())-1)){
3702 // Okay, get the un-inverted input value.
3704 if (N0.getOpcode() == ISD::XOR)
3705 Val = N0.getOperand(0);
3707 assert(N0.getOpcode() == ISD::AND &&
3708 N0.getOperand(0).getOpcode() == ISD::XOR);
3709 // ((X^1)&1)^1 -> X & 1
3710 Val = DAG.getNode(ISD::AND, N0.getValueType(),
3711 N0.getOperand(0).getOperand(0),
3714 return DAG.getSetCC(VT, Val, N1,
3715 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3720 uint64_t MinVal, MaxVal;
3721 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
3722 if (ISD::isSignedIntSetCC(Cond)) {
3723 MinVal = 1ULL << (OperandBitSize-1);
3724 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
3725 MaxVal = ~0ULL >> (65-OperandBitSize);
3730 MaxVal = ~0ULL >> (64-OperandBitSize);
3733 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
3734 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
3735 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
3736 --C1; // X >= C0 --> X > (C0-1)
3737 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3738 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
3741 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
3742 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
3743 ++C1; // X <= C0 --> X < (C0+1)
3744 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3745 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
3748 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
3749 return DAG.getConstant(0, VT); // X < MIN --> false
3751 // Canonicalize setgt X, Min --> setne X, Min
3752 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
3753 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3754 // Canonicalize setlt X, Max --> setne X, Max
3755 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
3756 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3758 // If we have setult X, 1, turn it into seteq X, 0
3759 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
3760 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
3762 // If we have setugt X, Max-1, turn it into seteq X, Max
3763 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
3764 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
3767 // If we have "setcc X, C0", check to see if we can shrink the immediate
3770 // SETUGT X, SINTMAX -> SETLT X, 0
3771 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
3772 C1 == (~0ULL >> (65-OperandBitSize)))
3773 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
3776 // FIXME: Implement the rest of these.
3778 // Fold bit comparisons when we can.
3779 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3780 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
3781 if (ConstantSDNode *AndRHS =
3782 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3783 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
3784 // Perform the xform if the AND RHS is a single bit.
3785 if (isPowerOf2_64(AndRHS->getValue())) {
3786 return DAG.getNode(ISD::SRL, VT, N0,
3787 DAG.getConstant(Log2_64(AndRHS->getValue()),
3788 TLI.getShiftAmountTy()));
3790 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
3791 // (X & 8) == 8 --> (X & 8) >> 3
3792 // Perform the xform if C1 is a single bit.
3793 if (isPowerOf2_64(C1)) {
3794 return DAG.getNode(ISD::SRL, VT, N0,
3795 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
3800 } else if (isa<ConstantSDNode>(N0.Val)) {
3801 // Ensure that the constant occurs on the RHS.
3802 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
3805 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val)) {
3806 // Constant fold or commute setcc.
3807 SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond);
3808 if (O.Val) return O;
3812 // We can always fold X == X for integer setcc's.
3813 if (MVT::isInteger(N0.getValueType()))
3814 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3815 unsigned UOF = ISD::getUnorderedFlavor(Cond);
3816 if (UOF == 2) // FP operators that are undefined on NaNs.
3817 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3818 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
3819 return DAG.getConstant(UOF, VT);
3820 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
3821 // if it is not already.
3822 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
3823 if (NewCond != Cond)
3824 return DAG.getSetCC(VT, N0, N1, NewCond);
3827 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3828 MVT::isInteger(N0.getValueType())) {
3829 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
3830 N0.getOpcode() == ISD::XOR) {
3831 // Simplify (X+Y) == (X+Z) --> Y == Z
3832 if (N0.getOpcode() == N1.getOpcode()) {
3833 if (N0.getOperand(0) == N1.getOperand(0))
3834 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
3835 if (N0.getOperand(1) == N1.getOperand(1))
3836 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
3837 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
3838 // If X op Y == Y op X, try other combinations.
3839 if (N0.getOperand(0) == N1.getOperand(1))
3840 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
3841 if (N0.getOperand(1) == N1.getOperand(0))
3842 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
3846 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
3847 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3848 // Turn (X+C1) == C2 --> X == C2-C1
3849 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
3850 return DAG.getSetCC(VT, N0.getOperand(0),
3851 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
3852 N0.getValueType()), Cond);
3855 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
3856 if (N0.getOpcode() == ISD::XOR)
3857 // If we know that all of the inverted bits are zero, don't bother
3858 // performing the inversion.
3859 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
3860 return DAG.getSetCC(VT, N0.getOperand(0),
3861 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
3862 N0.getValueType()), Cond);
3865 // Turn (C1-X) == C2 --> X == C1-C2
3866 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
3867 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
3868 return DAG.getSetCC(VT, N0.getOperand(1),
3869 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
3870 N0.getValueType()), Cond);
3875 // Simplify (X+Z) == X --> Z == 0
3876 if (N0.getOperand(0) == N1)
3877 return DAG.getSetCC(VT, N0.getOperand(1),
3878 DAG.getConstant(0, N0.getValueType()), Cond);
3879 if (N0.getOperand(1) == N1) {
3880 if (DAG.isCommutativeBinOp(N0.getOpcode()))
3881 return DAG.getSetCC(VT, N0.getOperand(0),
3882 DAG.getConstant(0, N0.getValueType()), Cond);
3884 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
3885 // (Z-X) == X --> Z == X<<1
3886 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
3888 DAG.getConstant(1,TLI.getShiftAmountTy()));
3889 AddToWorkList(SH.Val);
3890 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
3895 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
3896 N1.getOpcode() == ISD::XOR) {
3897 // Simplify X == (X+Z) --> Z == 0
3898 if (N1.getOperand(0) == N0) {
3899 return DAG.getSetCC(VT, N1.getOperand(1),
3900 DAG.getConstant(0, N1.getValueType()), Cond);
3901 } else if (N1.getOperand(1) == N0) {
3902 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
3903 return DAG.getSetCC(VT, N1.getOperand(0),
3904 DAG.getConstant(0, N1.getValueType()), Cond);
3906 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
3907 // X == (Z-X) --> X<<1 == Z
3908 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
3909 DAG.getConstant(1,TLI.getShiftAmountTy()));
3910 AddToWorkList(SH.Val);
3911 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
3917 // Fold away ALL boolean setcc's.
3919 if (N0.getValueType() == MVT::i1 && foldBooleans) {
3921 default: assert(0 && "Unknown integer setcc!");
3922 case ISD::SETEQ: // X == Y -> (X^Y)^1
3923 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
3924 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
3925 AddToWorkList(Temp.Val);
3927 case ISD::SETNE: // X != Y --> (X^Y)
3928 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
3930 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
3931 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
3932 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
3933 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
3934 AddToWorkList(Temp.Val);
3936 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
3937 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
3938 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
3939 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
3940 AddToWorkList(Temp.Val);
3942 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
3943 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
3944 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
3945 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
3946 AddToWorkList(Temp.Val);
3948 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
3949 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
3950 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
3951 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
3954 if (VT != MVT::i1) {
3955 AddToWorkList(N0.Val);
3956 // FIXME: If running after legalize, we probably can't do this.
3957 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
3962 // Could not fold it.
3966 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3967 /// return a DAG expression to select that will generate the same value by
3968 /// multiplying by a magic number. See:
3969 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3970 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
3971 std::vector<SDNode*> Built;
3972 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
3974 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
3980 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3981 /// return a DAG expression to select that will generate the same value by
3982 /// multiplying by a magic number. See:
3983 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3984 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
3985 std::vector<SDNode*> Built;
3986 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
3988 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
3994 /// FindBaseOffset - Return true if base is known not to alias with anything
3995 /// but itself. Provides base object and offset as results.
3996 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
3997 // Assume it is a primitive operation.
3998 Base = Ptr; Offset = 0;
4000 // If it's an adding a simple constant then integrate the offset.
4001 if (Base.getOpcode() == ISD::ADD) {
4002 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
4003 Base = Base.getOperand(0);
4004 Offset += C->getValue();
4008 // If it's any of the following then it can't alias with anything but itself.
4009 return isa<FrameIndexSDNode>(Base) ||
4010 isa<ConstantPoolSDNode>(Base) ||
4011 isa<GlobalAddressSDNode>(Base);
4014 /// isAlias - Return true if there is any possibility that the two addresses
4016 bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1,
4017 const Value *SrcValue1, int SrcValueOffset1,
4018 SDOperand Ptr2, int64_t Size2,
4019 const Value *SrcValue2, int SrcValueOffset2)
4021 // If they are the same then they must be aliases.
4022 if (Ptr1 == Ptr2) return true;
4024 // Gather base node and offset information.
4025 SDOperand Base1, Base2;
4026 int64_t Offset1, Offset2;
4027 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
4028 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
4030 // If they have a same base address then...
4031 if (Base1 == Base2) {
4032 // Check to see if the addresses overlap.
4033 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
4036 // If we know both bases then they can't alias.
4037 if (KnownBase1 && KnownBase2) return false;
4039 // Use alias analysis information.
4040 int Overlap1 = Size1 + SrcValueOffset1 + Offset1;
4041 int Overlap2 = Size2 + SrcValueOffset2 + Offset2;
4042 AliasAnalysis::AliasResult AAResult =
4043 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
4044 if (AAResult == AliasAnalysis::NoAlias)
4047 // Otherwise we have to assume they alias.
4051 /// FindAliasInfo - Extracts the relevant alias information from the memory
4052 /// node. Returns true if the operand was a load.
4053 bool DAGCombiner::FindAliasInfo(SDNode *N,
4054 SDOperand &Ptr, int64_t &Size,
4055 const Value *&SrcValue, int &SrcValueOffset) {
4056 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4057 Ptr = LD->getBasePtr();
4058 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3;
4059 SrcValue = LD->getSrcValue();
4060 SrcValueOffset = LD->getSrcValueOffset();
4062 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4063 Ptr = ST->getBasePtr();
4064 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3;
4065 SrcValue = ST->getSrcValue();
4066 SrcValueOffset = ST->getSrcValueOffset();
4068 assert(0 && "FindAliasInfo expected a memory operand");
4074 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
4075 /// looking for aliasing nodes and adding them to the Aliases vector.
4076 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
4077 SmallVector<SDOperand, 8> &Aliases) {
4078 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
4079 std::set<SDNode *> Visited; // Visited node set.
4081 // Get alias information for node.
4084 const Value *SrcValue;
4086 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
4089 Chains.push_back(OriginalChain);
4091 // Look at each chain and determine if it is an alias. If so, add it to the
4092 // aliases list. If not, then continue up the chain looking for the next
4094 while (!Chains.empty()) {
4095 SDOperand Chain = Chains.back();
4098 // Don't bother if we've been before.
4099 if (Visited.find(Chain.Val) != Visited.end()) continue;
4100 Visited.insert(Chain.Val);
4102 switch (Chain.getOpcode()) {
4103 case ISD::EntryToken:
4104 // Entry token is ideal chain operand, but handled in FindBetterChain.
4109 // Get alias information for Chain.
4112 const Value *OpSrcValue;
4113 int OpSrcValueOffset;
4114 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
4115 OpSrcValue, OpSrcValueOffset);
4117 // If chain is alias then stop here.
4118 if (!(IsLoad && IsOpLoad) &&
4119 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
4120 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
4121 Aliases.push_back(Chain);
4123 // Look further up the chain.
4124 Chains.push_back(Chain.getOperand(0));
4125 // Clean up old chain.
4126 AddToWorkList(Chain.Val);
4131 case ISD::TokenFactor:
4132 // We have to check each of the operands of the token factor, so we queue
4133 // then up. Adding the operands to the queue (stack) in reverse order
4134 // maintains the original order and increases the likelihood that getNode
4135 // will find a matching token factor (CSE.)
4136 for (unsigned n = Chain.getNumOperands(); n;)
4137 Chains.push_back(Chain.getOperand(--n));
4138 // Eliminate the token factor if we can.
4139 AddToWorkList(Chain.Val);
4143 // For all other instructions we will just have to take what we can get.
4144 Aliases.push_back(Chain);
4150 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
4151 /// for a better chain (aliasing node.)
4152 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
4153 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
4155 // Accumulate all the aliases to this node.
4156 GatherAllAliases(N, OldChain, Aliases);
4158 if (Aliases.size() == 0) {
4159 // If no operands then chain to entry token.
4160 return DAG.getEntryNode();
4161 } else if (Aliases.size() == 1) {
4162 // If a single operand then chain to it. We don't need to revisit it.
4166 // Construct a custom tailored token factor.
4167 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4168 &Aliases[0], Aliases.size());
4170 // Make sure the old chain gets cleaned up.
4171 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
4176 // SelectionDAG::Combine - This is the entry point for the file.
4178 void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
4179 /// run - This is the main entry point to this class.
4181 DAGCombiner(*this, AA).Run(RunningAfterLegalize);