1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: make truncate see through SIGN_EXTEND and AND
26 // FIXME: divide by zero is currently left unfolded. do we want to turn this
28 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
30 //===----------------------------------------------------------------------===//
32 #define DEBUG_TYPE "dagcombine"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Target/TargetLowering.h"
44 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined");
51 // Worklist of all of the nodes that need to be simplified.
52 std::vector<SDNode*> WorkList;
54 /// AddUsersToWorkList - When an instruction is simplified, add all users of
55 /// the instruction to the work lists because they might get more simplified
58 void AddUsersToWorkList(SDNode *N) {
59 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
61 WorkList.push_back(*UI);
64 /// removeFromWorkList - remove all instances of N from the worklist.
65 void removeFromWorkList(SDNode *N) {
66 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
70 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
72 DEBUG(std::cerr << "\nReplacing "; N->dump();
73 std::cerr << "\nWith: "; To[0].Val->dump();
74 std::cerr << " and " << To.size()-1 << " other values\n");
75 std::vector<SDNode*> NowDead;
76 DAG.ReplaceAllUsesWith(N, To, &NowDead);
78 // Push the new nodes and any users onto the worklist
79 for (unsigned i = 0, e = To.size(); i != e; ++i) {
80 WorkList.push_back(To[i].Val);
81 AddUsersToWorkList(To[i].Val);
84 // Nodes can end up on the worklist more than once. Make sure we do
85 // not process a node that has been replaced.
86 removeFromWorkList(N);
87 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
88 removeFromWorkList(NowDead[i]);
90 // Finally, since the node is now dead, remove it from the graph.
92 return SDOperand(N, 0);
95 /// SimplifyDemandedBits - Check the specified integer node value to see if
96 /// it can be simplified or if things is uses can be simplified by bit
97 /// propagation. If so, return true.
98 bool SimplifyDemandedBits(SDOperand Op) {
99 TargetLowering::TargetLoweringOpt TLO(DAG);
100 uint64_t KnownZero, KnownOne;
101 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
102 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
106 WorkList.push_back(Op.Val);
108 // Replace the old value with the new one.
110 DEBUG(std::cerr << "\nReplacing "; TLO.Old.Val->dump();
111 std::cerr << "\nWith: "; TLO.New.Val->dump());
113 std::vector<SDNode*> NowDead;
114 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
116 // Push the new node and any (possibly new) users onto the worklist.
117 WorkList.push_back(TLO.New.Val);
118 AddUsersToWorkList(TLO.New.Val);
120 // Nodes can end up on the worklist more than once. Make sure we do
121 // not process a node that has been replaced.
122 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
123 removeFromWorkList(NowDead[i]);
125 // Finally, if the node is now dead, remove it from the graph. The node
126 // may not be dead if the replacement process recursively simplified to
127 // something else needing this node.
128 if (TLO.Old.Val->use_empty()) {
129 removeFromWorkList(TLO.Old.Val);
130 DAG.DeleteNode(TLO.Old.Val);
135 SDOperand CombineTo(SDNode *N, SDOperand Res) {
136 std::vector<SDOperand> To;
138 return CombineTo(N, To);
141 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
142 std::vector<SDOperand> To;
145 return CombineTo(N, To);
148 /// visit - call the node-specific routine that knows how to fold each
149 /// particular type of node.
150 SDOperand visit(SDNode *N);
152 // Visitation implementation - Implement dag node combining for different
153 // node types. The semantics are as follows:
155 // SDOperand.Val == 0 - No change was made
156 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
157 // otherwise - N should be replaced by the returned Operand.
159 SDOperand visitTokenFactor(SDNode *N);
160 SDOperand visitADD(SDNode *N);
161 SDOperand visitSUB(SDNode *N);
162 SDOperand visitMUL(SDNode *N);
163 SDOperand visitSDIV(SDNode *N);
164 SDOperand visitUDIV(SDNode *N);
165 SDOperand visitSREM(SDNode *N);
166 SDOperand visitUREM(SDNode *N);
167 SDOperand visitMULHU(SDNode *N);
168 SDOperand visitMULHS(SDNode *N);
169 SDOperand visitAND(SDNode *N);
170 SDOperand visitOR(SDNode *N);
171 SDOperand visitXOR(SDNode *N);
172 SDOperand visitSHL(SDNode *N);
173 SDOperand visitSRA(SDNode *N);
174 SDOperand visitSRL(SDNode *N);
175 SDOperand visitCTLZ(SDNode *N);
176 SDOperand visitCTTZ(SDNode *N);
177 SDOperand visitCTPOP(SDNode *N);
178 SDOperand visitSELECT(SDNode *N);
179 SDOperand visitSELECT_CC(SDNode *N);
180 SDOperand visitSETCC(SDNode *N);
181 SDOperand visitSIGN_EXTEND(SDNode *N);
182 SDOperand visitZERO_EXTEND(SDNode *N);
183 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
184 SDOperand visitTRUNCATE(SDNode *N);
185 SDOperand visitBIT_CONVERT(SDNode *N);
186 SDOperand visitFADD(SDNode *N);
187 SDOperand visitFSUB(SDNode *N);
188 SDOperand visitFMUL(SDNode *N);
189 SDOperand visitFDIV(SDNode *N);
190 SDOperand visitFREM(SDNode *N);
191 SDOperand visitSINT_TO_FP(SDNode *N);
192 SDOperand visitUINT_TO_FP(SDNode *N);
193 SDOperand visitFP_TO_SINT(SDNode *N);
194 SDOperand visitFP_TO_UINT(SDNode *N);
195 SDOperand visitFP_ROUND(SDNode *N);
196 SDOperand visitFP_ROUND_INREG(SDNode *N);
197 SDOperand visitFP_EXTEND(SDNode *N);
198 SDOperand visitFNEG(SDNode *N);
199 SDOperand visitFABS(SDNode *N);
200 SDOperand visitBRCOND(SDNode *N);
201 SDOperand visitBRCONDTWOWAY(SDNode *N);
202 SDOperand visitBR_CC(SDNode *N);
203 SDOperand visitBRTWOWAY_CC(SDNode *N);
204 SDOperand visitLOAD(SDNode *N);
205 SDOperand visitSTORE(SDNode *N);
207 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
209 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
210 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
211 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
212 SDOperand N3, ISD::CondCode CC);
213 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
214 ISD::CondCode Cond, bool foldBooleans = true);
216 SDOperand BuildSDIV(SDNode *N);
217 SDOperand BuildUDIV(SDNode *N);
219 DAGCombiner(SelectionDAG &D)
220 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
222 /// Run - runs the dag combiner on all nodes in the work list
223 void Run(bool RunningAfterLegalize);
228 int64_t m; // magic number
229 int64_t s; // shift amount
233 uint64_t m; // magic number
234 int64_t a; // add indicator
235 int64_t s; // shift amount
238 /// magic - calculate the magic numbers required to codegen an integer sdiv as
239 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
241 static ms magic32(int32_t d) {
243 uint32_t ad, anc, delta, q1, r1, q2, r2, t;
244 const uint32_t two31 = 0x80000000U;
248 t = two31 + ((uint32_t)d >> 31);
249 anc = t - 1 - t%ad; // absolute value of nc
250 p = 31; // initialize p
251 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
252 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
253 q2 = two31/ad; // initialize q2 = 2p/abs(d)
254 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
257 q1 = 2*q1; // update q1 = 2p/abs(nc)
258 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
259 if (r1 >= anc) { // must be unsigned comparison
263 q2 = 2*q2; // update q2 = 2p/abs(d)
264 r2 = 2*r2; // update r2 = rem(2p/abs(d))
265 if (r2 >= ad) { // must be unsigned comparison
270 } while (q1 < delta || (q1 == delta && r1 == 0));
272 mag.m = (int32_t)(q2 + 1); // make sure to sign extend
273 if (d < 0) mag.m = -mag.m; // resulting magic number
274 mag.s = p - 32; // resulting shift
278 /// magicu - calculate the magic numbers required to codegen an integer udiv as
279 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
280 static mu magicu32(uint32_t d) {
282 uint32_t nc, delta, q1, r1, q2, r2;
284 magu.a = 0; // initialize "add" indicator
286 p = 31; // initialize p
287 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
288 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
289 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
290 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
293 if (r1 >= nc - r1 ) {
294 q1 = 2*q1 + 1; // update q1
295 r1 = 2*r1 - nc; // update r1
298 q1 = 2*q1; // update q1
299 r1 = 2*r1; // update r1
301 if (r2 + 1 >= d - r2) {
302 if (q2 >= 0x7FFFFFFF) magu.a = 1;
303 q2 = 2*q2 + 1; // update q2
304 r2 = 2*r2 + 1 - d; // update r2
307 if (q2 >= 0x80000000) magu.a = 1;
308 q2 = 2*q2; // update q2
309 r2 = 2*r2 + 1; // update r2
312 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
313 magu.m = q2 + 1; // resulting magic number
314 magu.s = p - 32; // resulting shift
318 /// magic - calculate the magic numbers required to codegen an integer sdiv as
319 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
321 static ms magic64(int64_t d) {
323 uint64_t ad, anc, delta, q1, r1, q2, r2, t;
324 const uint64_t two63 = 9223372036854775808ULL; // 2^63
327 ad = d >= 0 ? d : -d;
328 t = two63 + ((uint64_t)d >> 63);
329 anc = t - 1 - t%ad; // absolute value of nc
330 p = 63; // initialize p
331 q1 = two63/anc; // initialize q1 = 2p/abs(nc)
332 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
333 q2 = two63/ad; // initialize q2 = 2p/abs(d)
334 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
337 q1 = 2*q1; // update q1 = 2p/abs(nc)
338 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
339 if (r1 >= anc) { // must be unsigned comparison
343 q2 = 2*q2; // update q2 = 2p/abs(d)
344 r2 = 2*r2; // update r2 = rem(2p/abs(d))
345 if (r2 >= ad) { // must be unsigned comparison
350 } while (q1 < delta || (q1 == delta && r1 == 0));
353 if (d < 0) mag.m = -mag.m; // resulting magic number
354 mag.s = p - 64; // resulting shift
358 /// magicu - calculate the magic numbers required to codegen an integer udiv as
359 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
360 static mu magicu64(uint64_t d)
363 uint64_t nc, delta, q1, r1, q2, r2;
365 magu.a = 0; // initialize "add" indicator
367 p = 63; // initialize p
368 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
369 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
370 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
371 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
374 if (r1 >= nc - r1 ) {
375 q1 = 2*q1 + 1; // update q1
376 r1 = 2*r1 - nc; // update r1
379 q1 = 2*q1; // update q1
380 r1 = 2*r1; // update r1
382 if (r2 + 1 >= d - r2) {
383 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
384 q2 = 2*q2 + 1; // update q2
385 r2 = 2*r2 + 1 - d; // update r2
388 if (q2 >= 0x8000000000000000ull) magu.a = 1;
389 q2 = 2*q2; // update q2
390 r2 = 2*r2 + 1; // update r2
393 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
394 magu.m = q2 + 1; // resulting magic number
395 magu.s = p - 64; // resulting shift
399 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
400 // that selects between the values 1 and 0, making it equivalent to a setcc.
401 // Also, set the incoming LHS, RHS, and CC references to the appropriate
402 // nodes based on the type of node we are checking. This simplifies life a
403 // bit for the callers.
404 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
406 if (N.getOpcode() == ISD::SETCC) {
407 LHS = N.getOperand(0);
408 RHS = N.getOperand(1);
409 CC = N.getOperand(2);
412 if (N.getOpcode() == ISD::SELECT_CC &&
413 N.getOperand(2).getOpcode() == ISD::Constant &&
414 N.getOperand(3).getOpcode() == ISD::Constant &&
415 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
416 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
417 LHS = N.getOperand(0);
418 RHS = N.getOperand(1);
419 CC = N.getOperand(4);
425 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
426 // one use. If this is true, it allows the users to invert the operation for
427 // free when it is profitable to do so.
428 static bool isOneUseSetCC(SDOperand N) {
429 SDOperand N0, N1, N2;
430 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
435 // FIXME: This should probably go in the ISD class rather than being duplicated
437 static bool isCommutativeBinOp(unsigned Opcode) {
443 case ISD::XOR: return true;
444 default: return false; // FIXME: Need commutative info for user ops!
448 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
449 MVT::ValueType VT = N0.getValueType();
450 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
451 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
452 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
453 if (isa<ConstantSDNode>(N1)) {
454 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
455 WorkList.push_back(OpNode.Val);
456 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
457 } else if (N0.hasOneUse()) {
458 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
459 WorkList.push_back(OpNode.Val);
460 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
463 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
464 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
465 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
466 if (isa<ConstantSDNode>(N0)) {
467 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
468 WorkList.push_back(OpNode.Val);
469 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
470 } else if (N1.hasOneUse()) {
471 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
472 WorkList.push_back(OpNode.Val);
473 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
479 void DAGCombiner::Run(bool RunningAfterLegalize) {
480 // set the instance variable, so that the various visit routines may use it.
481 AfterLegalize = RunningAfterLegalize;
483 // Add all the dag nodes to the worklist.
484 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
485 E = DAG.allnodes_end(); I != E; ++I)
486 WorkList.push_back(I);
488 // Create a dummy node (which is not added to allnodes), that adds a reference
489 // to the root node, preventing it from being deleted, and tracking any
490 // changes of the root.
491 HandleSDNode Dummy(DAG.getRoot());
493 // while the worklist isn't empty, inspect the node on the end of it and
494 // try and combine it.
495 while (!WorkList.empty()) {
496 SDNode *N = WorkList.back();
499 // If N has no uses, it is dead. Make sure to revisit all N's operands once
500 // N is deleted from the DAG, since they too may now be dead or may have a
501 // reduced number of uses, allowing other xforms.
502 if (N->use_empty() && N != &Dummy) {
503 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
504 WorkList.push_back(N->getOperand(i).Val);
506 removeFromWorkList(N);
511 SDOperand RV = visit(N);
514 // If we get back the same node we passed in, rather than a new node or
515 // zero, we know that the node must have defined multiple values and
516 // CombineTo was used. Since CombineTo takes care of the worklist
517 // mechanics for us, we have no work to do in this case.
519 DEBUG(std::cerr << "\nReplacing "; N->dump();
520 std::cerr << "\nWith: "; RV.Val->dump();
522 std::vector<SDNode*> NowDead;
523 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead);
525 // Push the new node and any users onto the worklist
526 WorkList.push_back(RV.Val);
527 AddUsersToWorkList(RV.Val);
529 // Nodes can end up on the worklist more than once. Make sure we do
530 // not process a node that has been replaced.
531 removeFromWorkList(N);
532 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
533 removeFromWorkList(NowDead[i]);
535 // Finally, since the node is now dead, remove it from the graph.
541 // If the root changed (e.g. it was a dead load, update the root).
542 DAG.setRoot(Dummy.getValue());
545 SDOperand DAGCombiner::visit(SDNode *N) {
546 switch(N->getOpcode()) {
548 case ISD::TokenFactor: return visitTokenFactor(N);
549 case ISD::ADD: return visitADD(N);
550 case ISD::SUB: return visitSUB(N);
551 case ISD::MUL: return visitMUL(N);
552 case ISD::SDIV: return visitSDIV(N);
553 case ISD::UDIV: return visitUDIV(N);
554 case ISD::SREM: return visitSREM(N);
555 case ISD::UREM: return visitUREM(N);
556 case ISD::MULHU: return visitMULHU(N);
557 case ISD::MULHS: return visitMULHS(N);
558 case ISD::AND: return visitAND(N);
559 case ISD::OR: return visitOR(N);
560 case ISD::XOR: return visitXOR(N);
561 case ISD::SHL: return visitSHL(N);
562 case ISD::SRA: return visitSRA(N);
563 case ISD::SRL: return visitSRL(N);
564 case ISD::CTLZ: return visitCTLZ(N);
565 case ISD::CTTZ: return visitCTTZ(N);
566 case ISD::CTPOP: return visitCTPOP(N);
567 case ISD::SELECT: return visitSELECT(N);
568 case ISD::SELECT_CC: return visitSELECT_CC(N);
569 case ISD::SETCC: return visitSETCC(N);
570 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
571 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
572 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
573 case ISD::TRUNCATE: return visitTRUNCATE(N);
574 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
575 case ISD::FADD: return visitFADD(N);
576 case ISD::FSUB: return visitFSUB(N);
577 case ISD::FMUL: return visitFMUL(N);
578 case ISD::FDIV: return visitFDIV(N);
579 case ISD::FREM: return visitFREM(N);
580 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
581 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
582 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
583 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
584 case ISD::FP_ROUND: return visitFP_ROUND(N);
585 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
586 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
587 case ISD::FNEG: return visitFNEG(N);
588 case ISD::FABS: return visitFABS(N);
589 case ISD::BRCOND: return visitBRCOND(N);
590 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N);
591 case ISD::BR_CC: return visitBR_CC(N);
592 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N);
593 case ISD::LOAD: return visitLOAD(N);
594 case ISD::STORE: return visitSTORE(N);
599 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
600 std::vector<SDOperand> Ops;
601 bool Changed = false;
603 // If the token factor has two operands and one is the entry token, replace
604 // the token factor with the other operand.
605 if (N->getNumOperands() == 2) {
606 if (N->getOperand(0).getOpcode() == ISD::EntryToken)
607 return N->getOperand(1);
608 if (N->getOperand(1).getOpcode() == ISD::EntryToken)
609 return N->getOperand(0);
612 // fold (tokenfactor (tokenfactor)) -> tokenfactor
613 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
614 SDOperand Op = N->getOperand(i);
615 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) {
617 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j)
618 Ops.push_back(Op.getOperand(j));
624 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
628 SDOperand DAGCombiner::visitADD(SDNode *N) {
629 SDOperand N0 = N->getOperand(0);
630 SDOperand N1 = N->getOperand(1);
631 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
632 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
633 MVT::ValueType VT = N0.getValueType();
635 // fold (add c1, c2) -> c1+c2
637 return DAG.getNode(ISD::ADD, VT, N0, N1);
638 // canonicalize constant to RHS
640 return DAG.getNode(ISD::ADD, VT, N1, N0);
641 // fold (add x, 0) -> x
642 if (N1C && N1C->isNullValue())
644 // fold ((c1-A)+c2) -> (c1+c2)-A
645 if (N1C && N0.getOpcode() == ISD::SUB)
646 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
647 return DAG.getNode(ISD::SUB, VT,
648 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
651 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
654 // fold ((0-A) + B) -> B-A
655 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
656 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
657 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
658 // fold (A + (0-B)) -> A-B
659 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
660 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
661 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
662 // fold (A+(B-A)) -> B
663 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
664 return N1.getOperand(0);
666 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
671 SDOperand DAGCombiner::visitSUB(SDNode *N) {
672 SDOperand N0 = N->getOperand(0);
673 SDOperand N1 = N->getOperand(1);
674 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
675 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
676 MVT::ValueType VT = N0.getValueType();
678 // fold (sub x, x) -> 0
680 return DAG.getConstant(0, N->getValueType(0));
681 // fold (sub c1, c2) -> c1-c2
683 return DAG.getNode(ISD::SUB, VT, N0, N1);
684 // fold (sub x, c) -> (add x, -c)
686 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
688 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
689 return N0.getOperand(1);
691 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
692 return N0.getOperand(0);
696 SDOperand DAGCombiner::visitMUL(SDNode *N) {
697 SDOperand N0 = N->getOperand(0);
698 SDOperand N1 = N->getOperand(1);
699 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
700 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
701 MVT::ValueType VT = N0.getValueType();
703 // fold (mul c1, c2) -> c1*c2
705 return DAG.getNode(ISD::MUL, VT, N0, N1);
706 // canonicalize constant to RHS
708 return DAG.getNode(ISD::MUL, VT, N1, N0);
709 // fold (mul x, 0) -> 0
710 if (N1C && N1C->isNullValue())
712 // fold (mul x, -1) -> 0-x
713 if (N1C && N1C->isAllOnesValue())
714 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
715 // fold (mul x, (1 << c)) -> x << c
716 if (N1C && isPowerOf2_64(N1C->getValue()))
717 return DAG.getNode(ISD::SHL, VT, N0,
718 DAG.getConstant(Log2_64(N1C->getValue()),
719 TLI.getShiftAmountTy()));
720 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
721 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
722 // FIXME: If the input is something that is easily negated (e.g. a
723 // single-use add), we should put the negate there.
724 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
725 DAG.getNode(ISD::SHL, VT, N0,
726 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
727 TLI.getShiftAmountTy())));
730 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
731 if (N1C && N0.getOpcode() == ISD::SHL &&
732 isa<ConstantSDNode>(N0.getOperand(1))) {
733 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
734 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
737 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
740 SDOperand Sh(0,0), Y(0,0);
741 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
742 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
743 N0.Val->hasOneUse()) {
745 } else if (N1.getOpcode() == ISD::SHL &&
746 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
750 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
751 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
757 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
763 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
764 SDOperand N0 = N->getOperand(0);
765 SDOperand N1 = N->getOperand(1);
766 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
767 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
768 MVT::ValueType VT = N->getValueType(0);
770 // fold (sdiv c1, c2) -> c1/c2
771 if (N0C && N1C && !N1C->isNullValue())
772 return DAG.getNode(ISD::SDIV, VT, N0, N1);
773 // fold (sdiv X, 1) -> X
774 if (N1C && N1C->getSignExtended() == 1LL)
776 // fold (sdiv X, -1) -> 0-X
777 if (N1C && N1C->isAllOnesValue())
778 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
779 // If we know the sign bits of both operands are zero, strength reduce to a
780 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
781 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
782 if (TLI.MaskedValueIsZero(N1, SignBit) &&
783 TLI.MaskedValueIsZero(N0, SignBit))
784 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
785 // fold (sdiv X, pow2) -> simple ops after legalize
786 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
787 (isPowerOf2_64(N1C->getSignExtended()) ||
788 isPowerOf2_64(-N1C->getSignExtended()))) {
789 // If dividing by powers of two is cheap, then don't perform the following
791 if (TLI.isPow2DivCheap())
793 int64_t pow2 = N1C->getSignExtended();
794 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
795 unsigned lg2 = Log2_64(abs2);
796 // Splat the sign bit into the register
797 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
798 DAG.getConstant(MVT::getSizeInBits(VT)-1,
799 TLI.getShiftAmountTy()));
800 WorkList.push_back(SGN.Val);
801 // Add (N0 < 0) ? abs2 - 1 : 0;
802 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
803 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
804 TLI.getShiftAmountTy()));
805 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
806 WorkList.push_back(SRL.Val);
807 WorkList.push_back(ADD.Val); // Divide by pow2
808 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
809 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
810 // If we're dividing by a positive value, we're done. Otherwise, we must
811 // negate the result.
814 WorkList.push_back(SRA.Val);
815 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
817 // if integer divide is expensive and we satisfy the requirements, emit an
818 // alternate sequence.
819 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
820 !TLI.isIntDivCheap()) {
821 SDOperand Op = BuildSDIV(N);
822 if (Op.Val) return Op;
827 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
828 SDOperand N0 = N->getOperand(0);
829 SDOperand N1 = N->getOperand(1);
830 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
831 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
832 MVT::ValueType VT = N->getValueType(0);
834 // fold (udiv c1, c2) -> c1/c2
835 if (N0C && N1C && !N1C->isNullValue())
836 return DAG.getNode(ISD::UDIV, VT, N0, N1);
837 // fold (udiv x, (1 << c)) -> x >>u c
838 if (N1C && isPowerOf2_64(N1C->getValue()))
839 return DAG.getNode(ISD::SRL, VT, N0,
840 DAG.getConstant(Log2_64(N1C->getValue()),
841 TLI.getShiftAmountTy()));
842 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
843 if (N1.getOpcode() == ISD::SHL) {
844 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
845 if (isPowerOf2_64(SHC->getValue())) {
846 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
847 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
848 DAG.getConstant(Log2_64(SHC->getValue()),
850 WorkList.push_back(Add.Val);
851 return DAG.getNode(ISD::SRL, VT, N0, Add);
855 // fold (udiv x, c) -> alternate
856 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
857 SDOperand Op = BuildUDIV(N);
858 if (Op.Val) return Op;
863 SDOperand DAGCombiner::visitSREM(SDNode *N) {
864 SDOperand N0 = N->getOperand(0);
865 SDOperand N1 = N->getOperand(1);
866 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
867 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
868 MVT::ValueType VT = N->getValueType(0);
870 // fold (srem c1, c2) -> c1%c2
871 if (N0C && N1C && !N1C->isNullValue())
872 return DAG.getNode(ISD::SREM, VT, N0, N1);
873 // If we know the sign bits of both operands are zero, strength reduce to a
874 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
875 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
876 if (TLI.MaskedValueIsZero(N1, SignBit) &&
877 TLI.MaskedValueIsZero(N0, SignBit))
878 return DAG.getNode(ISD::UREM, VT, N0, N1);
882 SDOperand DAGCombiner::visitUREM(SDNode *N) {
883 SDOperand N0 = N->getOperand(0);
884 SDOperand N1 = N->getOperand(1);
885 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
886 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
887 MVT::ValueType VT = N->getValueType(0);
889 // fold (urem c1, c2) -> c1%c2
890 if (N0C && N1C && !N1C->isNullValue())
891 return DAG.getNode(ISD::UREM, VT, N0, N1);
892 // fold (urem x, pow2) -> (and x, pow2-1)
893 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
894 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
895 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
896 if (N1.getOpcode() == ISD::SHL) {
897 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
898 if (isPowerOf2_64(SHC->getValue())) {
899 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
900 WorkList.push_back(Add.Val);
901 return DAG.getNode(ISD::AND, VT, N0, Add);
908 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
909 SDOperand N0 = N->getOperand(0);
910 SDOperand N1 = N->getOperand(1);
911 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
913 // fold (mulhs x, 0) -> 0
914 if (N1C && N1C->isNullValue())
916 // fold (mulhs x, 1) -> (sra x, size(x)-1)
917 if (N1C && N1C->getValue() == 1)
918 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
919 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
920 TLI.getShiftAmountTy()));
924 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
925 SDOperand N0 = N->getOperand(0);
926 SDOperand N1 = N->getOperand(1);
927 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
929 // fold (mulhu x, 0) -> 0
930 if (N1C && N1C->isNullValue())
932 // fold (mulhu x, 1) -> 0
933 if (N1C && N1C->getValue() == 1)
934 return DAG.getConstant(0, N0.getValueType());
938 SDOperand DAGCombiner::visitAND(SDNode *N) {
939 SDOperand N0 = N->getOperand(0);
940 SDOperand N1 = N->getOperand(1);
941 SDOperand LL, LR, RL, RR, CC0, CC1;
942 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
943 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
944 MVT::ValueType VT = N1.getValueType();
945 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
947 // fold (and c1, c2) -> c1&c2
949 return DAG.getNode(ISD::AND, VT, N0, N1);
950 // canonicalize constant to RHS
952 return DAG.getNode(ISD::AND, VT, N1, N0);
953 // fold (and x, -1) -> x
954 if (N1C && N1C->isAllOnesValue())
956 // if (and x, c) is known to be zero, return 0
957 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
958 return DAG.getConstant(0, VT);
960 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
963 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
964 if (N1C && N0.getOpcode() == ISD::OR)
965 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
966 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
968 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
969 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
970 unsigned InBits = MVT::getSizeInBits(N0.getOperand(0).getValueType());
971 if (TLI.MaskedValueIsZero(N0.getOperand(0),
972 ~N1C->getValue() & ((1ULL << InBits)-1))) {
973 // We actually want to replace all uses of the any_extend with the
974 // zero_extend, to avoid duplicating things. This will later cause this
976 CombineTo(N0.Val, DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
981 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
982 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
983 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
984 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
986 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
987 MVT::isInteger(LL.getValueType())) {
988 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
989 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
990 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
991 WorkList.push_back(ORNode.Val);
992 return DAG.getSetCC(VT, ORNode, LR, Op1);
994 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
995 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
996 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
997 WorkList.push_back(ANDNode.Val);
998 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1000 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1001 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1002 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1003 WorkList.push_back(ORNode.Val);
1004 return DAG.getSetCC(VT, ORNode, LR, Op1);
1007 // canonicalize equivalent to ll == rl
1008 if (LL == RR && LR == RL) {
1009 Op1 = ISD::getSetCCSwappedOperands(Op1);
1012 if (LL == RL && LR == RR) {
1013 bool isInteger = MVT::isInteger(LL.getValueType());
1014 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1015 if (Result != ISD::SETCC_INVALID)
1016 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1019 // fold (and (zext x), (zext y)) -> (zext (and x, y))
1020 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1021 N1.getOpcode() == ISD::ZERO_EXTEND &&
1022 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1023 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
1024 N0.getOperand(0), N1.getOperand(0));
1025 WorkList.push_back(ANDNode.Val);
1026 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode);
1028 // fold (and (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (and x, y))
1029 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
1030 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
1031 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
1032 N0.getOperand(1) == N1.getOperand(1)) {
1033 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
1034 N0.getOperand(0), N1.getOperand(0));
1035 WorkList.push_back(ANDNode.Val);
1036 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
1038 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1039 // fold (and (sra)) -> (and (srl)) when possible.
1040 if (SimplifyDemandedBits(SDOperand(N, 0)))
1042 // fold (zext_inreg (extload x)) -> (zextload x)
1043 if (N0.getOpcode() == ISD::EXTLOAD) {
1044 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1045 // If we zero all the possible extended bits, then we can turn this into
1046 // a zextload if we are running before legalize or the operation is legal.
1047 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1048 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1049 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1050 N0.getOperand(1), N0.getOperand(2),
1052 WorkList.push_back(N);
1053 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1057 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1058 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) {
1059 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1060 // If we zero all the possible extended bits, then we can turn this into
1061 // a zextload if we are running before legalize or the operation is legal.
1062 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1063 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1064 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1065 N0.getOperand(1), N0.getOperand(2),
1067 WorkList.push_back(N);
1068 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1073 // fold (and (load x), 255) -> (zextload x, i8)
1074 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1076 (N0.getOpcode() == ISD::LOAD || N0.getOpcode() == ISD::EXTLOAD ||
1077 N0.getOpcode() == ISD::ZEXTLOAD) &&
1079 MVT::ValueType EVT, LoadedVT;
1080 if (N1C->getValue() == 255)
1082 else if (N1C->getValue() == 65535)
1084 else if (N1C->getValue() == ~0U)
1089 LoadedVT = N0.getOpcode() == ISD::LOAD ? VT :
1090 cast<VTSDNode>(N0.getOperand(3))->getVT();
1091 if (EVT != MVT::Other && LoadedVT > EVT) {
1092 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1093 // For big endian targets, we need to add an offset to the pointer to load
1094 // the correct bytes. For little endian systems, we merely need to read
1095 // fewer bytes from the same pointer.
1097 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1098 SDOperand NewPtr = N0.getOperand(1);
1099 if (!TLI.isLittleEndian())
1100 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1101 DAG.getConstant(PtrOff, PtrType));
1102 WorkList.push_back(NewPtr.Val);
1104 DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), NewPtr,
1105 N0.getOperand(2), EVT);
1106 WorkList.push_back(N);
1107 CombineTo(N0.Val, Load, Load.getValue(1));
1115 SDOperand DAGCombiner::visitOR(SDNode *N) {
1116 SDOperand N0 = N->getOperand(0);
1117 SDOperand N1 = N->getOperand(1);
1118 SDOperand LL, LR, RL, RR, CC0, CC1;
1119 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1120 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1121 MVT::ValueType VT = N1.getValueType();
1122 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1124 // fold (or c1, c2) -> c1|c2
1126 return DAG.getNode(ISD::OR, VT, N0, N1);
1127 // canonicalize constant to RHS
1129 return DAG.getNode(ISD::OR, VT, N1, N0);
1130 // fold (or x, 0) -> x
1131 if (N1C && N1C->isNullValue())
1133 // fold (or x, -1) -> -1
1134 if (N1C && N1C->isAllOnesValue())
1136 // fold (or x, c) -> c iff (x & ~c) == 0
1138 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1141 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1144 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1145 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1146 isa<ConstantSDNode>(N0.getOperand(1))) {
1147 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1148 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1150 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1152 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1153 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1154 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1155 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1157 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1158 MVT::isInteger(LL.getValueType())) {
1159 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1160 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1161 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1162 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1163 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1164 WorkList.push_back(ORNode.Val);
1165 return DAG.getSetCC(VT, ORNode, LR, Op1);
1167 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1168 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1169 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1170 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1171 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1172 WorkList.push_back(ANDNode.Val);
1173 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1176 // canonicalize equivalent to ll == rl
1177 if (LL == RR && LR == RL) {
1178 Op1 = ISD::getSetCCSwappedOperands(Op1);
1181 if (LL == RL && LR == RR) {
1182 bool isInteger = MVT::isInteger(LL.getValueType());
1183 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1184 if (Result != ISD::SETCC_INVALID)
1185 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1188 // fold (or (zext x), (zext y)) -> (zext (or x, y))
1189 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1190 N1.getOpcode() == ISD::ZERO_EXTEND &&
1191 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1192 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
1193 N0.getOperand(0), N1.getOperand(0));
1194 WorkList.push_back(ORNode.Val);
1195 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode);
1197 // fold (or (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (or x, y))
1198 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
1199 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
1200 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
1201 N0.getOperand(1) == N1.getOperand(1)) {
1202 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
1203 N0.getOperand(0), N1.getOperand(0));
1204 WorkList.push_back(ORNode.Val);
1205 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1207 // canonicalize shl to left side in a shl/srl pair, to match rotate
1208 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
1210 // check for rotl, rotr
1211 if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL &&
1212 N0.getOperand(0) == N1.getOperand(0) &&
1213 TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) {
1214 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1215 if (N0.getOperand(1).getOpcode() == ISD::Constant &&
1216 N1.getOperand(1).getOpcode() == ISD::Constant) {
1217 uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1218 uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1219 if ((c1val + c2val) == OpSizeInBits)
1220 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
1222 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1223 if (N1.getOperand(1).getOpcode() == ISD::SUB &&
1224 N0.getOperand(1) == N1.getOperand(1).getOperand(1))
1225 if (ConstantSDNode *SUBC =
1226 dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0)))
1227 if (SUBC->getValue() == OpSizeInBits)
1228 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
1229 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1230 if (N0.getOperand(1).getOpcode() == ISD::SUB &&
1231 N1.getOperand(1) == N0.getOperand(1).getOperand(1))
1232 if (ConstantSDNode *SUBC =
1233 dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0)))
1234 if (SUBC->getValue() == OpSizeInBits) {
1235 if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT))
1236 return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0),
1239 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0),
1246 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1247 SDOperand N0 = N->getOperand(0);
1248 SDOperand N1 = N->getOperand(1);
1249 SDOperand LHS, RHS, CC;
1250 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1251 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1252 MVT::ValueType VT = N0.getValueType();
1254 // fold (xor c1, c2) -> c1^c2
1256 return DAG.getNode(ISD::XOR, VT, N0, N1);
1257 // canonicalize constant to RHS
1259 return DAG.getNode(ISD::XOR, VT, N1, N0);
1260 // fold (xor x, 0) -> x
1261 if (N1C && N1C->isNullValue())
1264 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1267 // fold !(x cc y) -> (x !cc y)
1268 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1269 bool isInt = MVT::isInteger(LHS.getValueType());
1270 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1272 if (N0.getOpcode() == ISD::SETCC)
1273 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1274 if (N0.getOpcode() == ISD::SELECT_CC)
1275 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1276 assert(0 && "Unhandled SetCC Equivalent!");
1279 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1280 if (N1C && N1C->getValue() == 1 &&
1281 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1282 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1283 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1284 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1285 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1286 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1287 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
1288 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1291 // fold !(x or y) -> (!x and !y) iff x or y are constants
1292 if (N1C && N1C->isAllOnesValue() &&
1293 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1294 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1295 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1296 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1297 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1298 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1299 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
1300 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1303 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1304 if (N1C && N0.getOpcode() == ISD::XOR) {
1305 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1306 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1308 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1309 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1311 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1312 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1314 // fold (xor x, x) -> 0
1316 return DAG.getConstant(0, VT);
1317 // fold (xor (zext x), (zext y)) -> (zext (xor x, y))
1318 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1319 N1.getOpcode() == ISD::ZERO_EXTEND &&
1320 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1321 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
1322 N0.getOperand(0), N1.getOperand(0));
1323 WorkList.push_back(XORNode.Val);
1324 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
1326 // fold (xor (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (xor x, y))
1327 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
1328 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
1329 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
1330 N0.getOperand(1) == N1.getOperand(1)) {
1331 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
1332 N0.getOperand(0), N1.getOperand(0));
1333 WorkList.push_back(XORNode.Val);
1334 return DAG.getNode(N0.getOpcode(), VT, XORNode, N0.getOperand(1));
1339 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1340 SDOperand N0 = N->getOperand(0);
1341 SDOperand N1 = N->getOperand(1);
1342 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1343 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1344 MVT::ValueType VT = N0.getValueType();
1345 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1347 // fold (shl c1, c2) -> c1<<c2
1349 return DAG.getNode(ISD::SHL, VT, N0, N1);
1350 // fold (shl 0, x) -> 0
1351 if (N0C && N0C->isNullValue())
1353 // fold (shl x, c >= size(x)) -> undef
1354 if (N1C && N1C->getValue() >= OpSizeInBits)
1355 return DAG.getNode(ISD::UNDEF, VT);
1356 // fold (shl x, 0) -> x
1357 if (N1C && N1C->isNullValue())
1359 // if (shl x, c) is known to be zero, return 0
1360 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1361 return DAG.getConstant(0, VT);
1362 if (SimplifyDemandedBits(SDOperand(N, 0)))
1364 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1365 if (N1C && N0.getOpcode() == ISD::SHL &&
1366 N0.getOperand(1).getOpcode() == ISD::Constant) {
1367 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1368 uint64_t c2 = N1C->getValue();
1369 if (c1 + c2 > OpSizeInBits)
1370 return DAG.getConstant(0, VT);
1371 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1372 DAG.getConstant(c1 + c2, N1.getValueType()));
1374 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1375 // (srl (and x, -1 << c1), c1-c2)
1376 if (N1C && N0.getOpcode() == ISD::SRL &&
1377 N0.getOperand(1).getOpcode() == ISD::Constant) {
1378 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1379 uint64_t c2 = N1C->getValue();
1380 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1381 DAG.getConstant(~0ULL << c1, VT));
1383 return DAG.getNode(ISD::SHL, VT, Mask,
1384 DAG.getConstant(c2-c1, N1.getValueType()));
1386 return DAG.getNode(ISD::SRL, VT, Mask,
1387 DAG.getConstant(c1-c2, N1.getValueType()));
1389 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1390 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1391 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1392 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1396 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1397 SDOperand N0 = N->getOperand(0);
1398 SDOperand N1 = N->getOperand(1);
1399 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1400 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1401 MVT::ValueType VT = N0.getValueType();
1403 // fold (sra c1, c2) -> c1>>c2
1405 return DAG.getNode(ISD::SRA, VT, N0, N1);
1406 // fold (sra 0, x) -> 0
1407 if (N0C && N0C->isNullValue())
1409 // fold (sra -1, x) -> -1
1410 if (N0C && N0C->isAllOnesValue())
1412 // fold (sra x, c >= size(x)) -> undef
1413 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
1414 return DAG.getNode(ISD::UNDEF, VT);
1415 // fold (sra x, 0) -> x
1416 if (N1C && N1C->isNullValue())
1418 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
1420 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
1421 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
1424 default: EVT = MVT::Other; break;
1425 case 1: EVT = MVT::i1; break;
1426 case 8: EVT = MVT::i8; break;
1427 case 16: EVT = MVT::i16; break;
1428 case 32: EVT = MVT::i32; break;
1430 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
1431 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1432 DAG.getValueType(EVT));
1435 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
1436 if (N1C && N0.getOpcode() == ISD::SRA) {
1437 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1438 unsigned Sum = N1C->getValue() + C1->getValue();
1439 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
1440 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
1441 DAG.getConstant(Sum, N1C->getValueType(0)));
1445 // If the sign bit is known to be zero, switch this to a SRL.
1446 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
1447 return DAG.getNode(ISD::SRL, VT, N0, N1);
1451 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1452 SDOperand N0 = N->getOperand(0);
1453 SDOperand N1 = N->getOperand(1);
1454 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1455 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1456 MVT::ValueType VT = N0.getValueType();
1457 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1459 // fold (srl c1, c2) -> c1 >>u c2
1461 return DAG.getNode(ISD::SRL, VT, N0, N1);
1462 // fold (srl 0, x) -> 0
1463 if (N0C && N0C->isNullValue())
1465 // fold (srl x, c >= size(x)) -> undef
1466 if (N1C && N1C->getValue() >= OpSizeInBits)
1467 return DAG.getNode(ISD::UNDEF, VT);
1468 // fold (srl x, 0) -> x
1469 if (N1C && N1C->isNullValue())
1471 // if (srl x, c) is known to be zero, return 0
1472 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1473 return DAG.getConstant(0, VT);
1474 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1475 if (N1C && N0.getOpcode() == ISD::SRL &&
1476 N0.getOperand(1).getOpcode() == ISD::Constant) {
1477 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1478 uint64_t c2 = N1C->getValue();
1479 if (c1 + c2 > OpSizeInBits)
1480 return DAG.getConstant(0, VT);
1481 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1482 DAG.getConstant(c1 + c2, N1.getValueType()));
1487 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1488 SDOperand N0 = N->getOperand(0);
1489 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1490 MVT::ValueType VT = N->getValueType(0);
1492 // fold (ctlz c1) -> c2
1494 return DAG.getNode(ISD::CTLZ, VT, N0);
1498 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1499 SDOperand N0 = N->getOperand(0);
1500 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1501 MVT::ValueType VT = N->getValueType(0);
1503 // fold (cttz c1) -> c2
1505 return DAG.getNode(ISD::CTTZ, VT, N0);
1509 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1510 SDOperand N0 = N->getOperand(0);
1511 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1512 MVT::ValueType VT = N->getValueType(0);
1514 // fold (ctpop c1) -> c2
1516 return DAG.getNode(ISD::CTPOP, VT, N0);
1520 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1521 SDOperand N0 = N->getOperand(0);
1522 SDOperand N1 = N->getOperand(1);
1523 SDOperand N2 = N->getOperand(2);
1524 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1525 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1526 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1527 MVT::ValueType VT = N->getValueType(0);
1529 // fold select C, X, X -> X
1532 // fold select true, X, Y -> X
1533 if (N0C && !N0C->isNullValue())
1535 // fold select false, X, Y -> Y
1536 if (N0C && N0C->isNullValue())
1538 // fold select C, 1, X -> C | X
1539 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1540 return DAG.getNode(ISD::OR, VT, N0, N2);
1541 // fold select C, 0, X -> ~C & X
1542 // FIXME: this should check for C type == X type, not i1?
1543 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1544 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1545 WorkList.push_back(XORNode.Val);
1546 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1548 // fold select C, X, 1 -> ~C | X
1549 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1550 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1551 WorkList.push_back(XORNode.Val);
1552 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1554 // fold select C, X, 0 -> C & X
1555 // FIXME: this should check for C type == X type, not i1?
1556 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1557 return DAG.getNode(ISD::AND, VT, N0, N1);
1558 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1559 if (MVT::i1 == VT && N0 == N1)
1560 return DAG.getNode(ISD::OR, VT, N0, N2);
1561 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1562 if (MVT::i1 == VT && N0 == N2)
1563 return DAG.getNode(ISD::AND, VT, N0, N1);
1564 // If we can fold this based on the true/false value, do so.
1565 if (SimplifySelectOps(N, N1, N2))
1567 // fold selects based on a setcc into other things, such as min/max/abs
1568 if (N0.getOpcode() == ISD::SETCC)
1570 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1571 // having to say they don't support SELECT_CC on every type the DAG knows
1572 // about, since there is no way to mark an opcode illegal at all value types
1573 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1574 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1575 N1, N2, N0.getOperand(2));
1577 return SimplifySelect(N0, N1, N2);
1581 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1582 SDOperand N0 = N->getOperand(0);
1583 SDOperand N1 = N->getOperand(1);
1584 SDOperand N2 = N->getOperand(2);
1585 SDOperand N3 = N->getOperand(3);
1586 SDOperand N4 = N->getOperand(4);
1587 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1588 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1589 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1590 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1592 // Determine if the condition we're dealing with is constant
1593 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1594 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1596 // fold select_cc lhs, rhs, x, x, cc -> x
1600 // If we can fold this based on the true/false value, do so.
1601 if (SimplifySelectOps(N, N2, N3))
1604 // fold select_cc into other things, such as min/max/abs
1605 return SimplifySelectCC(N0, N1, N2, N3, CC);
1608 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1609 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1610 cast<CondCodeSDNode>(N->getOperand(2))->get());
1613 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1614 SDOperand N0 = N->getOperand(0);
1615 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1616 MVT::ValueType VT = N->getValueType(0);
1618 // fold (sext c1) -> c1
1620 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
1621 // fold (sext (sext x)) -> (sext x)
1622 if (N0.getOpcode() == ISD::SIGN_EXTEND)
1623 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1624 // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size.
1625 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
1627 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType())))
1628 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1629 DAG.getValueType(N0.getValueType()));
1630 // fold (sext (load x)) -> (sext (truncate (sextload x)))
1631 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1632 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){
1633 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1634 N0.getOperand(1), N0.getOperand(2),
1636 CombineTo(N, ExtLoad);
1637 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1638 ExtLoad.getValue(1));
1642 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
1643 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
1644 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
1646 SDOperand ExtLoad = DAG.getNode(ISD::SEXTLOAD, VT, N0.getOperand(0),
1647 N0.getOperand(1), N0.getOperand(2),
1649 CombineTo(N, ExtLoad);
1650 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1651 ExtLoad.getValue(1));
1658 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1659 SDOperand N0 = N->getOperand(0);
1660 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1661 MVT::ValueType VT = N->getValueType(0);
1663 // fold (zext c1) -> c1
1665 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1666 // fold (zext (zext x)) -> (zext x)
1667 if (N0.getOpcode() == ISD::ZERO_EXTEND)
1668 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1669 // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size.
1670 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
1671 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType())))
1672 return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType());
1673 // fold (zext (load x)) -> (zext (truncate (zextload x)))
1674 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1675 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){
1676 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1677 N0.getOperand(1), N0.getOperand(2),
1679 CombineTo(N, ExtLoad);
1680 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1681 ExtLoad.getValue(1));
1685 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
1686 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
1687 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
1689 SDOperand ExtLoad = DAG.getNode(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1690 N0.getOperand(1), N0.getOperand(2),
1692 CombineTo(N, ExtLoad);
1693 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1694 ExtLoad.getValue(1));
1700 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1701 SDOperand N0 = N->getOperand(0);
1702 SDOperand N1 = N->getOperand(1);
1703 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1704 MVT::ValueType VT = N->getValueType(0);
1705 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
1706 unsigned EVTBits = MVT::getSizeInBits(EVT);
1708 // fold (sext_in_reg c1) -> c1
1710 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT);
1711 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate);
1713 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1
1714 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1715 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1718 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
1719 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1720 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
1721 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
1723 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x)
1724 if (N0.getOpcode() == ISD::AssertSext &&
1725 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1728 // fold (sext_in_reg (sextload x)) -> (sextload x)
1729 if (N0.getOpcode() == ISD::SEXTLOAD &&
1730 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) {
1733 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1
1734 if (N0.getOpcode() == ISD::SETCC &&
1735 TLI.getSetCCResultContents() ==
1736 TargetLowering::ZeroOrNegativeOneSetCCResult)
1738 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
1739 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
1740 return DAG.getZeroExtendInReg(N0, EVT);
1741 // fold (sext_in_reg (srl x)) -> sra x
1742 if (N0.getOpcode() == ISD::SRL &&
1743 N0.getOperand(1).getOpcode() == ISD::Constant &&
1744 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) {
1745 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0),
1748 // fold (sext_inreg (extload x)) -> (sextload x)
1749 if (N0.getOpcode() == ISD::EXTLOAD &&
1750 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1751 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1752 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1753 N0.getOperand(1), N0.getOperand(2),
1755 CombineTo(N, ExtLoad);
1756 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1759 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
1760 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() &&
1761 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1762 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1763 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1764 N0.getOperand(1), N0.getOperand(2),
1766 CombineTo(N, ExtLoad);
1767 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1773 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
1774 SDOperand N0 = N->getOperand(0);
1775 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1776 MVT::ValueType VT = N->getValueType(0);
1779 if (N0.getValueType() == N->getValueType(0))
1781 // fold (truncate c1) -> c1
1783 return DAG.getNode(ISD::TRUNCATE, VT, N0);
1784 // fold (truncate (truncate x)) -> (truncate x)
1785 if (N0.getOpcode() == ISD::TRUNCATE)
1786 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1787 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
1788 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){
1789 if (N0.getValueType() < VT)
1790 // if the source is smaller than the dest, we still need an extend
1791 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
1792 else if (N0.getValueType() > VT)
1793 // if the source is larger than the dest, than we just need the truncate
1794 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1796 // if the source and dest are the same type, we can drop both the extend
1798 return N0.getOperand(0);
1800 // fold (truncate (load x)) -> (smaller load x)
1801 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
1802 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
1803 "Cannot truncate to larger type!");
1804 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1805 // For big endian targets, we need to add an offset to the pointer to load
1806 // the correct bytes. For little endian systems, we merely need to read
1807 // fewer bytes from the same pointer.
1809 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
1810 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) :
1811 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1),
1812 DAG.getConstant(PtrOff, PtrType));
1813 WorkList.push_back(NewPtr.Val);
1814 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2));
1815 WorkList.push_back(N);
1816 CombineTo(N0.Val, Load, Load.getValue(1));
1822 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
1823 SDOperand N0 = N->getOperand(0);
1824 MVT::ValueType VT = N->getValueType(0);
1826 // If the input is a constant, let getNode() fold it.
1827 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
1828 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
1829 if (Res.Val != N) return Res;
1832 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
1833 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
1835 // fold (conv (load x)) -> (load (conv*)x)
1836 // FIXME: These xforms need to know that the resultant load doesn't need a
1837 // higher alignment than the original!
1838 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
1839 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1),
1841 WorkList.push_back(N);
1842 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
1850 SDOperand DAGCombiner::visitFADD(SDNode *N) {
1851 SDOperand N0 = N->getOperand(0);
1852 SDOperand N1 = N->getOperand(1);
1853 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1854 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1855 MVT::ValueType VT = N->getValueType(0);
1857 // fold (fadd c1, c2) -> c1+c2
1859 return DAG.getNode(ISD::FADD, VT, N0, N1);
1860 // canonicalize constant to RHS
1861 if (N0CFP && !N1CFP)
1862 return DAG.getNode(ISD::FADD, VT, N1, N0);
1863 // fold (A + (-B)) -> A-B
1864 if (N1.getOpcode() == ISD::FNEG)
1865 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
1866 // fold ((-A) + B) -> B-A
1867 if (N0.getOpcode() == ISD::FNEG)
1868 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
1872 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
1873 SDOperand N0 = N->getOperand(0);
1874 SDOperand N1 = N->getOperand(1);
1875 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1876 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1877 MVT::ValueType VT = N->getValueType(0);
1879 // fold (fsub c1, c2) -> c1-c2
1881 return DAG.getNode(ISD::FSUB, VT, N0, N1);
1882 // fold (A-(-B)) -> A+B
1883 if (N1.getOpcode() == ISD::FNEG)
1884 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
1888 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
1889 SDOperand N0 = N->getOperand(0);
1890 SDOperand N1 = N->getOperand(1);
1891 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1892 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1893 MVT::ValueType VT = N->getValueType(0);
1895 // fold (fmul c1, c2) -> c1*c2
1897 return DAG.getNode(ISD::FMUL, VT, N0, N1);
1898 // canonicalize constant to RHS
1899 if (N0CFP && !N1CFP)
1900 return DAG.getNode(ISD::FMUL, VT, N1, N0);
1901 // fold (fmul X, 2.0) -> (fadd X, X)
1902 if (N1CFP && N1CFP->isExactlyValue(+2.0))
1903 return DAG.getNode(ISD::FADD, VT, N0, N0);
1907 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
1908 SDOperand N0 = N->getOperand(0);
1909 SDOperand N1 = N->getOperand(1);
1910 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1911 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1912 MVT::ValueType VT = N->getValueType(0);
1914 // fold (fdiv c1, c2) -> c1/c2
1916 return DAG.getNode(ISD::FDIV, VT, N0, N1);
1920 SDOperand DAGCombiner::visitFREM(SDNode *N) {
1921 SDOperand N0 = N->getOperand(0);
1922 SDOperand N1 = N->getOperand(1);
1923 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1924 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1925 MVT::ValueType VT = N->getValueType(0);
1927 // fold (frem c1, c2) -> fmod(c1,c2)
1929 return DAG.getNode(ISD::FREM, VT, N0, N1);
1934 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
1935 SDOperand N0 = N->getOperand(0);
1936 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1937 MVT::ValueType VT = N->getValueType(0);
1939 // fold (sint_to_fp c1) -> c1fp
1941 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
1945 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
1946 SDOperand N0 = N->getOperand(0);
1947 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1948 MVT::ValueType VT = N->getValueType(0);
1950 // fold (uint_to_fp c1) -> c1fp
1952 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
1956 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
1957 SDOperand N0 = N->getOperand(0);
1958 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1959 MVT::ValueType VT = N->getValueType(0);
1961 // fold (fp_to_sint c1fp) -> c1
1963 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
1967 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
1968 SDOperand N0 = N->getOperand(0);
1969 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1970 MVT::ValueType VT = N->getValueType(0);
1972 // fold (fp_to_uint c1fp) -> c1
1974 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
1978 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
1979 SDOperand N0 = N->getOperand(0);
1980 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1981 MVT::ValueType VT = N->getValueType(0);
1983 // fold (fp_round c1fp) -> c1fp
1985 return DAG.getNode(ISD::FP_ROUND, VT, N0);
1989 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
1990 SDOperand N0 = N->getOperand(0);
1991 MVT::ValueType VT = N->getValueType(0);
1992 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1993 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1995 // fold (fp_round_inreg c1fp) -> c1fp
1997 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
1998 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
2003 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
2004 SDOperand N0 = N->getOperand(0);
2005 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2006 MVT::ValueType VT = N->getValueType(0);
2008 // fold (fp_extend c1fp) -> c1fp
2010 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
2014 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
2015 SDOperand N0 = N->getOperand(0);
2016 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2017 MVT::ValueType VT = N->getValueType(0);
2019 // fold (fneg c1) -> -c1
2021 return DAG.getNode(ISD::FNEG, VT, N0);
2022 // fold (fneg (sub x, y)) -> (sub y, x)
2023 if (N->getOperand(0).getOpcode() == ISD::SUB)
2024 return DAG.getNode(ISD::SUB, VT, N->getOperand(1), N->getOperand(0));
2025 // fold (fneg (fneg x)) -> x
2026 if (N->getOperand(0).getOpcode() == ISD::FNEG)
2027 return N->getOperand(0).getOperand(0);
2031 SDOperand DAGCombiner::visitFABS(SDNode *N) {
2032 SDOperand N0 = N->getOperand(0);
2033 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2034 MVT::ValueType VT = N->getValueType(0);
2036 // fold (fabs c1) -> fabs(c1)
2038 return DAG.getNode(ISD::FABS, VT, N0);
2039 // fold (fabs (fabs x)) -> (fabs x)
2040 if (N->getOperand(0).getOpcode() == ISD::FABS)
2041 return N->getOperand(0);
2042 // fold (fabs (fneg x)) -> (fabs x)
2043 if (N->getOperand(0).getOpcode() == ISD::FNEG)
2044 return DAG.getNode(ISD::FABS, VT, N->getOperand(0).getOperand(0));
2048 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
2049 SDOperand Chain = N->getOperand(0);
2050 SDOperand N1 = N->getOperand(1);
2051 SDOperand N2 = N->getOperand(2);
2052 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2054 // never taken branch, fold to chain
2055 if (N1C && N1C->isNullValue())
2057 // unconditional branch
2058 if (N1C && N1C->getValue() == 1)
2059 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2060 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
2062 if (N1.getOpcode() == ISD::SETCC &&
2063 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
2064 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
2065 N1.getOperand(0), N1.getOperand(1), N2);
2070 SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) {
2071 SDOperand Chain = N->getOperand(0);
2072 SDOperand N1 = N->getOperand(1);
2073 SDOperand N2 = N->getOperand(2);
2074 SDOperand N3 = N->getOperand(3);
2075 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2077 // unconditional branch to true mbb
2078 if (N1C && N1C->getValue() == 1)
2079 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2080 // unconditional branch to false mbb
2081 if (N1C && N1C->isNullValue())
2082 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3);
2083 // fold a brcondtwoway with a setcc condition into a BRTWOWAY_CC node if
2084 // BRTWOWAY_CC is legal on the target.
2085 if (N1.getOpcode() == ISD::SETCC &&
2086 TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) {
2087 std::vector<SDOperand> Ops;
2088 Ops.push_back(Chain);
2089 Ops.push_back(N1.getOperand(2));
2090 Ops.push_back(N1.getOperand(0));
2091 Ops.push_back(N1.getOperand(1));
2094 return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops);
2099 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
2101 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
2102 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2103 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2105 // Use SimplifySetCC to simplify SETCC's.
2106 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2107 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2109 // fold br_cc true, dest -> br dest (unconditional branch)
2110 if (SCCC && SCCC->getValue())
2111 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2113 // fold br_cc false, dest -> unconditional fall through
2114 if (SCCC && SCCC->isNullValue())
2115 return N->getOperand(0);
2116 // fold to a simpler setcc
2117 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2118 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2119 Simp.getOperand(2), Simp.getOperand(0),
2120 Simp.getOperand(1), N->getOperand(4));
2124 SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) {
2125 SDOperand Chain = N->getOperand(0);
2126 SDOperand CCN = N->getOperand(1);
2127 SDOperand LHS = N->getOperand(2);
2128 SDOperand RHS = N->getOperand(3);
2129 SDOperand N4 = N->getOperand(4);
2130 SDOperand N5 = N->getOperand(5);
2132 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS,
2133 cast<CondCodeSDNode>(CCN)->get(), false);
2134 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
2136 // fold select_cc lhs, rhs, x, x, cc -> x
2138 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
2139 // fold select_cc true, x, y -> x
2140 if (SCCC && SCCC->getValue())
2141 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
2142 // fold select_cc false, x, y -> y
2143 if (SCCC && SCCC->isNullValue())
2144 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5);
2145 // fold to a simpler setcc
2146 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) {
2147 std::vector<SDOperand> Ops;
2148 Ops.push_back(Chain);
2149 Ops.push_back(SCC.getOperand(2));
2150 Ops.push_back(SCC.getOperand(0));
2151 Ops.push_back(SCC.getOperand(1));
2154 return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops);
2159 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
2160 SDOperand Chain = N->getOperand(0);
2161 SDOperand Ptr = N->getOperand(1);
2162 SDOperand SrcValue = N->getOperand(2);
2164 // If this load is directly stored, replace the load value with the stored
2166 // TODO: Handle store large -> read small portion.
2167 // TODO: Handle TRUNCSTORE/EXTLOAD
2168 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2169 Chain.getOperand(1).getValueType() == N->getValueType(0))
2170 return CombineTo(N, Chain.getOperand(1), Chain);
2175 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
2176 SDOperand Chain = N->getOperand(0);
2177 SDOperand Value = N->getOperand(1);
2178 SDOperand Ptr = N->getOperand(2);
2179 SDOperand SrcValue = N->getOperand(3);
2181 // If this is a store that kills a previous store, remove the previous store.
2182 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2183 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ &&
2184 // Make sure that these stores are the same value type:
2185 // FIXME: we really care that the second store is >= size of the first.
2186 Value.getValueType() == Chain.getOperand(1).getValueType()) {
2187 // Create a new store of Value that replaces both stores.
2188 SDNode *PrevStore = Chain.Val;
2189 if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
2191 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other,
2192 PrevStore->getOperand(0), Value, Ptr,
2194 CombineTo(N, NewStore); // Nuke this store.
2195 CombineTo(PrevStore, NewStore); // Nuke the previous store.
2196 return SDOperand(N, 0);
2199 // If this is a store of a bit convert, store the input value.
2200 // FIXME: This needs to know that the resultant store does not need a
2201 // higher alignment than the original.
2202 if (0 && Value.getOpcode() == ISD::BIT_CONVERT)
2203 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0),
2209 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
2210 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
2212 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
2213 cast<CondCodeSDNode>(N0.getOperand(2))->get());
2214 // If we got a simplified select_cc node back from SimplifySelectCC, then
2215 // break it down into a new SETCC node, and a new SELECT node, and then return
2216 // the SELECT node, since we were called with a SELECT node.
2218 // Check to see if we got a select_cc back (to turn into setcc/select).
2219 // Otherwise, just return whatever node we got back, like fabs.
2220 if (SCC.getOpcode() == ISD::SELECT_CC) {
2221 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
2222 SCC.getOperand(0), SCC.getOperand(1),
2224 WorkList.push_back(SETCC.Val);
2225 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
2226 SCC.getOperand(3), SETCC);
2233 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
2234 /// are the two values being selected between, see if we can simplify the
2237 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
2240 // If this is a select from two identical things, try to pull the operation
2241 // through the select.
2242 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
2244 std::cerr << "SELECT: ["; LHS.Val->dump();
2245 std::cerr << "] ["; RHS.Val->dump();
2249 // If this is a load and the token chain is identical, replace the select
2250 // of two loads with a load through a select of the address to load from.
2251 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
2252 // constants have been dropped into the constant pool.
2253 if ((LHS.getOpcode() == ISD::LOAD ||
2254 LHS.getOpcode() == ISD::EXTLOAD ||
2255 LHS.getOpcode() == ISD::ZEXTLOAD ||
2256 LHS.getOpcode() == ISD::SEXTLOAD) &&
2257 // Token chains must be identical.
2258 LHS.getOperand(0) == RHS.getOperand(0) &&
2259 // If this is an EXTLOAD, the VT's must match.
2260 (LHS.getOpcode() == ISD::LOAD ||
2261 LHS.getOperand(3) == RHS.getOperand(3))) {
2262 // FIXME: this conflates two src values, discarding one. This is not
2263 // the right thing to do, but nothing uses srcvalues now. When they do,
2264 // turn SrcValue into a list of locations.
2266 if (TheSelect->getOpcode() == ISD::SELECT)
2267 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(),
2268 TheSelect->getOperand(0), LHS.getOperand(1),
2271 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(),
2272 TheSelect->getOperand(0),
2273 TheSelect->getOperand(1),
2274 LHS.getOperand(1), RHS.getOperand(1),
2275 TheSelect->getOperand(4));
2278 if (LHS.getOpcode() == ISD::LOAD)
2279 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0),
2280 Addr, LHS.getOperand(2));
2282 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0),
2283 LHS.getOperand(0), Addr, LHS.getOperand(2),
2284 cast<VTSDNode>(LHS.getOperand(3))->getVT());
2285 // Users of the select now use the result of the load.
2286 CombineTo(TheSelect, Load);
2288 // Users of the old loads now use the new load's chain. We know the
2289 // old-load value is dead now.
2290 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
2291 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
2299 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
2300 SDOperand N2, SDOperand N3,
2303 MVT::ValueType VT = N2.getValueType();
2304 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
2305 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
2306 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
2307 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
2309 // Determine if the condition we're dealing with is constant
2310 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
2311 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
2313 // fold select_cc true, x, y -> x
2314 if (SCCC && SCCC->getValue())
2316 // fold select_cc false, x, y -> y
2317 if (SCCC && SCCC->getValue() == 0)
2320 // Check to see if we can simplify the select into an fabs node
2321 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
2322 // Allow either -0.0 or 0.0
2323 if (CFP->getValue() == 0.0) {
2324 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
2325 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
2326 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
2327 N2 == N3.getOperand(0))
2328 return DAG.getNode(ISD::FABS, VT, N0);
2330 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
2331 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
2332 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
2333 N2.getOperand(0) == N3)
2334 return DAG.getNode(ISD::FABS, VT, N3);
2338 // Check to see if we can perform the "gzip trick", transforming
2339 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
2340 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() &&
2341 MVT::isInteger(N0.getValueType()) &&
2342 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) {
2343 MVT::ValueType XType = N0.getValueType();
2344 MVT::ValueType AType = N2.getValueType();
2345 if (XType >= AType) {
2346 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
2347 // single-bit constant.
2348 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
2349 unsigned ShCtV = Log2_64(N2C->getValue());
2350 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
2351 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
2352 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
2353 WorkList.push_back(Shift.Val);
2354 if (XType > AType) {
2355 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
2356 WorkList.push_back(Shift.Val);
2358 return DAG.getNode(ISD::AND, AType, Shift, N2);
2360 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
2361 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2362 TLI.getShiftAmountTy()));
2363 WorkList.push_back(Shift.Val);
2364 if (XType > AType) {
2365 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
2366 WorkList.push_back(Shift.Val);
2368 return DAG.getNode(ISD::AND, AType, Shift, N2);
2372 // fold select C, 16, 0 -> shl C, 4
2373 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
2374 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
2375 // Get a SetCC of the condition
2376 // FIXME: Should probably make sure that setcc is legal if we ever have a
2377 // target where it isn't.
2378 SDOperand Temp, SCC;
2379 // cast from setcc result type to select result type
2380 if (AfterLegalize) {
2381 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
2382 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
2384 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
2385 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
2387 WorkList.push_back(SCC.Val);
2388 WorkList.push_back(Temp.Val);
2389 // shl setcc result by log2 n2c
2390 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
2391 DAG.getConstant(Log2_64(N2C->getValue()),
2392 TLI.getShiftAmountTy()));
2395 // Check to see if this is the equivalent of setcc
2396 // FIXME: Turn all of these into setcc if setcc if setcc is legal
2397 // otherwise, go ahead with the folds.
2398 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
2399 MVT::ValueType XType = N0.getValueType();
2400 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
2401 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
2402 if (Res.getValueType() != VT)
2403 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
2407 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
2408 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
2409 TLI.isOperationLegal(ISD::CTLZ, XType)) {
2410 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
2411 return DAG.getNode(ISD::SRL, XType, Ctlz,
2412 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
2413 TLI.getShiftAmountTy()));
2415 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
2416 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
2417 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
2419 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
2420 DAG.getConstant(~0ULL, XType));
2421 return DAG.getNode(ISD::SRL, XType,
2422 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
2423 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2424 TLI.getShiftAmountTy()));
2426 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
2427 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
2428 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
2429 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2430 TLI.getShiftAmountTy()));
2431 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
2435 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
2436 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2437 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
2438 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
2439 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
2440 MVT::ValueType XType = N0.getValueType();
2441 if (SubC->isNullValue() && MVT::isInteger(XType)) {
2442 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
2443 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2444 TLI.getShiftAmountTy()));
2445 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
2446 WorkList.push_back(Shift.Val);
2447 WorkList.push_back(Add.Val);
2448 return DAG.getNode(ISD::XOR, XType, Add, Shift);
2456 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
2457 SDOperand N1, ISD::CondCode Cond,
2458 bool foldBooleans) {
2459 // These setcc operations always fold.
2463 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
2465 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
2468 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
2469 uint64_t C1 = N1C->getValue();
2470 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
2471 uint64_t C0 = N0C->getValue();
2473 // Sign extend the operands if required
2474 if (ISD::isSignedIntSetCC(Cond)) {
2475 C0 = N0C->getSignExtended();
2476 C1 = N1C->getSignExtended();
2480 default: assert(0 && "Unknown integer setcc!");
2481 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
2482 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
2483 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
2484 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
2485 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
2486 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
2487 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
2488 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
2489 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
2490 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
2493 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2494 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2495 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
2497 // If the comparison constant has bits in the upper part, the
2498 // zero-extended value could never match.
2499 if (C1 & (~0ULL << InSize)) {
2500 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
2504 case ISD::SETEQ: return DAG.getConstant(0, VT);
2507 case ISD::SETNE: return DAG.getConstant(1, VT);
2510 // True if the sign bit of C1 is set.
2511 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
2514 // True if the sign bit of C1 isn't set.
2515 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
2521 // Otherwise, we can perform the comparison with the low bits.
2529 return DAG.getSetCC(VT, N0.getOperand(0),
2530 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
2533 break; // todo, be more careful with signed comparisons
2535 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2536 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2537 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2538 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
2539 MVT::ValueType ExtDstTy = N0.getValueType();
2540 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
2542 // If the extended part has any inconsistent bits, it cannot ever
2543 // compare equal. In other words, they have to be all ones or all
2546 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
2547 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
2548 return DAG.getConstant(Cond == ISD::SETNE, VT);
2551 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
2552 if (Op0Ty == ExtSrcTy) {
2553 ZextOp = N0.getOperand(0);
2555 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
2556 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
2557 DAG.getConstant(Imm, Op0Ty));
2559 WorkList.push_back(ZextOp.Val);
2560 // Otherwise, make this a use of a zext.
2561 return DAG.getSetCC(VT, ZextOp,
2562 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
2565 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
2566 (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2567 (N0.getOpcode() == ISD::XOR ||
2568 (N0.getOpcode() == ISD::AND &&
2569 N0.getOperand(0).getOpcode() == ISD::XOR &&
2570 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2571 isa<ConstantSDNode>(N0.getOperand(1)) &&
2572 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
2573 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can
2574 // only do this if the top bits are known zero.
2575 if (TLI.MaskedValueIsZero(N1,
2576 MVT::getIntVTBitMask(N0.getValueType())-1)) {
2577 // Okay, get the un-inverted input value.
2579 if (N0.getOpcode() == ISD::XOR)
2580 Val = N0.getOperand(0);
2582 assert(N0.getOpcode() == ISD::AND &&
2583 N0.getOperand(0).getOpcode() == ISD::XOR);
2584 // ((X^1)&1)^1 -> X & 1
2585 Val = DAG.getNode(ISD::AND, N0.getValueType(),
2586 N0.getOperand(0).getOperand(0), N0.getOperand(1));
2588 return DAG.getSetCC(VT, Val, N1,
2589 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2593 uint64_t MinVal, MaxVal;
2594 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
2595 if (ISD::isSignedIntSetCC(Cond)) {
2596 MinVal = 1ULL << (OperandBitSize-1);
2597 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
2598 MaxVal = ~0ULL >> (65-OperandBitSize);
2603 MaxVal = ~0ULL >> (64-OperandBitSize);
2606 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2607 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2608 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2609 --C1; // X >= C0 --> X > (C0-1)
2610 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2611 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2614 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2615 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2616 ++C1; // X <= C0 --> X < (C0+1)
2617 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2618 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2621 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2622 return DAG.getConstant(0, VT); // X < MIN --> false
2624 // Canonicalize setgt X, Min --> setne X, Min
2625 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2626 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
2627 // Canonicalize setlt X, Max --> setne X, Max
2628 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2629 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
2631 // If we have setult X, 1, turn it into seteq X, 0
2632 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2633 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
2635 // If we have setugt X, Max-1, turn it into seteq X, Max
2636 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2637 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
2640 // If we have "setcc X, C0", check to see if we can shrink the immediate
2643 // SETUGT X, SINTMAX -> SETLT X, 0
2644 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
2645 C1 == (~0ULL >> (65-OperandBitSize)))
2646 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
2649 // FIXME: Implement the rest of these.
2651 // Fold bit comparisons when we can.
2652 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2653 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
2654 if (ConstantSDNode *AndRHS =
2655 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2656 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2657 // Perform the xform if the AND RHS is a single bit.
2658 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
2659 return DAG.getNode(ISD::SRL, VT, N0,
2660 DAG.getConstant(Log2_64(AndRHS->getValue()),
2661 TLI.getShiftAmountTy()));
2663 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
2664 // (X & 8) == 8 --> (X & 8) >> 3
2665 // Perform the xform if C1 is a single bit.
2666 if ((C1 & (C1-1)) == 0) {
2667 return DAG.getNode(ISD::SRL, VT, N0,
2668 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
2673 } else if (isa<ConstantSDNode>(N0.Val)) {
2674 // Ensure that the constant occurs on the RHS.
2675 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2678 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
2679 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
2680 double C0 = N0C->getValue(), C1 = N1C->getValue();
2683 default: break; // FIXME: Implement the rest of these!
2684 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
2685 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
2686 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
2687 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
2688 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
2689 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
2692 // Ensure that the constant occurs on the RHS.
2693 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2697 // We can always fold X == Y for integer setcc's.
2698 if (MVT::isInteger(N0.getValueType()))
2699 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2700 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2701 if (UOF == 2) // FP operators that are undefined on NaNs.
2702 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2703 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2704 return DAG.getConstant(UOF, VT);
2705 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2706 // if it is not already.
2707 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2708 if (NewCond != Cond)
2709 return DAG.getSetCC(VT, N0, N1, NewCond);
2712 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2713 MVT::isInteger(N0.getValueType())) {
2714 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2715 N0.getOpcode() == ISD::XOR) {
2716 // Simplify (X+Y) == (X+Z) --> Y == Z
2717 if (N0.getOpcode() == N1.getOpcode()) {
2718 if (N0.getOperand(0) == N1.getOperand(0))
2719 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
2720 if (N0.getOperand(1) == N1.getOperand(1))
2721 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
2722 if (isCommutativeBinOp(N0.getOpcode())) {
2723 // If X op Y == Y op X, try other combinations.
2724 if (N0.getOperand(0) == N1.getOperand(1))
2725 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
2726 if (N0.getOperand(1) == N1.getOperand(0))
2727 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
2731 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2732 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2733 // Turn (X+C1) == C2 --> X == C2-C1
2734 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
2735 return DAG.getSetCC(VT, N0.getOperand(0),
2736 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
2737 N0.getValueType()), Cond);
2740 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2741 if (N0.getOpcode() == ISD::XOR)
2742 // If we know that all of the inverted bits are zero, don't bother
2743 // performing the inversion.
2744 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
2745 return DAG.getSetCC(VT, N0.getOperand(0),
2746 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
2747 N0.getValueType()), Cond);
2750 // Turn (C1-X) == C2 --> X == C1-C2
2751 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2752 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
2753 return DAG.getSetCC(VT, N0.getOperand(1),
2754 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
2755 N0.getValueType()), Cond);
2760 // Simplify (X+Z) == X --> Z == 0
2761 if (N0.getOperand(0) == N1)
2762 return DAG.getSetCC(VT, N0.getOperand(1),
2763 DAG.getConstant(0, N0.getValueType()), Cond);
2764 if (N0.getOperand(1) == N1) {
2765 if (isCommutativeBinOp(N0.getOpcode()))
2766 return DAG.getSetCC(VT, N0.getOperand(0),
2767 DAG.getConstant(0, N0.getValueType()), Cond);
2769 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2770 // (Z-X) == X --> Z == X<<1
2771 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
2773 DAG.getConstant(1,TLI.getShiftAmountTy()));
2774 WorkList.push_back(SH.Val);
2775 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
2780 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2781 N1.getOpcode() == ISD::XOR) {
2782 // Simplify X == (X+Z) --> Z == 0
2783 if (N1.getOperand(0) == N0) {
2784 return DAG.getSetCC(VT, N1.getOperand(1),
2785 DAG.getConstant(0, N1.getValueType()), Cond);
2786 } else if (N1.getOperand(1) == N0) {
2787 if (isCommutativeBinOp(N1.getOpcode())) {
2788 return DAG.getSetCC(VT, N1.getOperand(0),
2789 DAG.getConstant(0, N1.getValueType()), Cond);
2791 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2792 // X == (Z-X) --> X<<1 == Z
2793 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
2794 DAG.getConstant(1,TLI.getShiftAmountTy()));
2795 WorkList.push_back(SH.Val);
2796 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
2802 // Fold away ALL boolean setcc's.
2804 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2806 default: assert(0 && "Unknown integer setcc!");
2807 case ISD::SETEQ: // X == Y -> (X^Y)^1
2808 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2809 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
2810 WorkList.push_back(Temp.Val);
2812 case ISD::SETNE: // X != Y --> (X^Y)
2813 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2815 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
2816 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
2817 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2818 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
2819 WorkList.push_back(Temp.Val);
2821 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
2822 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
2823 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2824 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
2825 WorkList.push_back(Temp.Val);
2827 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
2828 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
2829 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2830 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
2831 WorkList.push_back(Temp.Val);
2833 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
2834 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
2835 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2836 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
2839 if (VT != MVT::i1) {
2840 WorkList.push_back(N0.Val);
2841 // FIXME: If running after legalize, we probably can't do this.
2842 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2847 // Could not fold it.
2851 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2852 /// return a DAG expression to select that will generate the same value by
2853 /// multiplying by a magic number. See:
2854 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2855 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
2856 MVT::ValueType VT = N->getValueType(0);
2858 // Check to see if we can do this.
2859 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
2860 return SDOperand(); // BuildSDIV only operates on i32 or i64
2861 if (!TLI.isOperationLegal(ISD::MULHS, VT))
2862 return SDOperand(); // Make sure the target supports MULHS.
2864 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
2865 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
2867 // Multiply the numerator (operand 0) by the magic value
2868 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
2869 DAG.getConstant(magics.m, VT));
2870 // If d > 0 and m < 0, add the numerator
2871 if (d > 0 && magics.m < 0) {
2872 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
2873 WorkList.push_back(Q.Val);
2875 // If d < 0 and m > 0, subtract the numerator.
2876 if (d < 0 && magics.m > 0) {
2877 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
2878 WorkList.push_back(Q.Val);
2880 // Shift right algebraic if shift value is nonzero
2882 Q = DAG.getNode(ISD::SRA, VT, Q,
2883 DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
2884 WorkList.push_back(Q.Val);
2886 // Extract the sign bit and add it to the quotient
2888 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1,
2889 TLI.getShiftAmountTy()));
2890 WorkList.push_back(T.Val);
2891 return DAG.getNode(ISD::ADD, VT, Q, T);
2894 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2895 /// return a DAG expression to select that will generate the same value by
2896 /// multiplying by a magic number. See:
2897 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2898 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
2899 MVT::ValueType VT = N->getValueType(0);
2901 // Check to see if we can do this.
2902 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
2903 return SDOperand(); // BuildUDIV only operates on i32 or i64
2904 if (!TLI.isOperationLegal(ISD::MULHU, VT))
2905 return SDOperand(); // Make sure the target supports MULHU.
2907 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
2908 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
2910 // Multiply the numerator (operand 0) by the magic value
2911 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
2912 DAG.getConstant(magics.m, VT));
2913 WorkList.push_back(Q.Val);
2915 if (magics.a == 0) {
2916 return DAG.getNode(ISD::SRL, VT, Q,
2917 DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
2919 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
2920 WorkList.push_back(NPQ.Val);
2921 NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
2922 DAG.getConstant(1, TLI.getShiftAmountTy()));
2923 WorkList.push_back(NPQ.Val);
2924 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
2925 WorkList.push_back(NPQ.Val);
2926 return DAG.getNode(ISD::SRL, VT, NPQ,
2927 DAG.getConstant(magics.s-1, TLI.getShiftAmountTy()));
2931 // SelectionDAG::Combine - This is the entry point for the file.
2933 void SelectionDAG::Combine(bool RunningAfterLegalize) {
2934 /// run - This is the main entry point to this class.
2936 DAGCombiner(*this).Run(RunningAfterLegalize);