1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "dagcombine"
16 #include "llvm/CodeGen/SelectionDAG.h"
17 #include "llvm/Analysis/AliasAnalysis.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/ADT/SmallPtrSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/Support/Compiler.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
31 STATISTIC(NodesCombined , "Number of dag nodes combined");
32 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
33 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
38 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
39 cl::desc("Pop up a window to show dags before the first "
42 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
43 cl::desc("Pop up a window to show dags before the second "
46 static const bool ViewDAGCombine1 = false;
47 static const bool ViewDAGCombine2 = false;
51 CombinerAA("combiner-alias-analysis", cl::Hidden,
52 cl::desc("Turn on alias analysis during testing"));
55 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
56 cl::desc("Include global information in alias analysis"));
58 //------------------------------ DAGCombiner ---------------------------------//
60 class VISIBILITY_HIDDEN DAGCombiner {
65 // Worklist of all of the nodes that need to be simplified.
66 std::vector<SDNode*> WorkList;
68 // AA - Used for DAG load/store alias analysis.
71 /// AddUsersToWorkList - When an instruction is simplified, add all users of
72 /// the instruction to the work lists because they might get more simplified
75 void AddUsersToWorkList(SDNode *N) {
76 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
81 /// removeFromWorkList - remove all instances of N from the worklist.
83 void removeFromWorkList(SDNode *N) {
84 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
88 /// visit - call the node-specific routine that knows how to fold each
89 /// particular type of node.
90 SDOperand visit(SDNode *N);
93 /// AddToWorkList - Add to the work list making sure it's instance is at the
94 /// the back (next to be processed.)
95 void AddToWorkList(SDNode *N) {
96 removeFromWorkList(N);
97 WorkList.push_back(N);
100 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
102 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
104 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
105 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
106 DOUT << " and " << NumTo-1 << " other values\n";
107 std::vector<SDNode*> NowDead;
108 DAG.ReplaceAllUsesWith(N, To, &NowDead);
111 // Push the new nodes and any users onto the worklist
112 for (unsigned i = 0, e = NumTo; i != e; ++i) {
113 AddToWorkList(To[i].Val);
114 AddUsersToWorkList(To[i].Val);
118 // Nodes can be reintroduced into the worklist. Make sure we do not
119 // process a node that has been replaced.
120 removeFromWorkList(N);
121 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
122 removeFromWorkList(NowDead[i]);
124 // Finally, since the node is now dead, remove it from the graph.
126 return SDOperand(N, 0);
129 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
130 return CombineTo(N, &Res, 1, AddTo);
133 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
135 SDOperand To[] = { Res0, Res1 };
136 return CombineTo(N, To, 2, AddTo);
141 /// SimplifyDemandedBits - Check the specified integer node value to see if
142 /// it can be simplified or if things it uses can be simplified by bit
143 /// propagation. If so, return true.
144 bool SimplifyDemandedBits(SDOperand Op, uint64_t Demanded = ~0ULL) {
145 TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize);
146 uint64_t KnownZero, KnownOne;
147 Demanded &= MVT::getIntVTBitMask(Op.getValueType());
148 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
152 AddToWorkList(Op.Val);
154 // Replace the old value with the new one.
156 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG));
157 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
160 std::vector<SDNode*> NowDead;
161 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &NowDead);
163 // Push the new node and any (possibly new) users onto the worklist.
164 AddToWorkList(TLO.New.Val);
165 AddUsersToWorkList(TLO.New.Val);
167 // Nodes can end up on the worklist more than once. Make sure we do
168 // not process a node that has been replaced.
169 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
170 removeFromWorkList(NowDead[i]);
172 // Finally, if the node is now dead, remove it from the graph. The node
173 // may not be dead if the replacement process recursively simplified to
174 // something else needing this node.
175 if (TLO.Old.Val->use_empty()) {
176 removeFromWorkList(TLO.Old.Val);
178 // If the operands of this node are only used by the node, they will now
179 // be dead. Make sure to visit them first to delete dead nodes early.
180 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i)
181 if (TLO.Old.Val->getOperand(i).Val->hasOneUse())
182 AddToWorkList(TLO.Old.Val->getOperand(i).Val);
184 DAG.DeleteNode(TLO.Old.Val);
189 bool CombineToPreIndexedLoadStore(SDNode *N);
190 bool CombineToPostIndexedLoadStore(SDNode *N);
193 /// combine - call the node-specific routine that knows how to fold each
194 /// particular type of node. If that doesn't do anything, try the
195 /// target-specific DAG combines.
196 SDOperand combine(SDNode *N);
198 // Visitation implementation - Implement dag node combining for different
199 // node types. The semantics are as follows:
201 // SDOperand.Val == 0 - No change was made
202 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
203 // otherwise - N should be replaced by the returned Operand.
205 SDOperand visitTokenFactor(SDNode *N);
206 SDOperand visitADD(SDNode *N);
207 SDOperand visitSUB(SDNode *N);
208 SDOperand visitADDC(SDNode *N);
209 SDOperand visitADDE(SDNode *N);
210 SDOperand visitMUL(SDNode *N);
211 SDOperand visitSDIV(SDNode *N);
212 SDOperand visitUDIV(SDNode *N);
213 SDOperand visitSREM(SDNode *N);
214 SDOperand visitUREM(SDNode *N);
215 SDOperand visitMULHU(SDNode *N);
216 SDOperand visitMULHS(SDNode *N);
217 SDOperand visitSMUL_LOHI(SDNode *N);
218 SDOperand visitUMUL_LOHI(SDNode *N);
219 SDOperand visitSDIVREM(SDNode *N);
220 SDOperand visitUDIVREM(SDNode *N);
221 SDOperand visitAND(SDNode *N);
222 SDOperand visitOR(SDNode *N);
223 SDOperand visitXOR(SDNode *N);
224 SDOperand SimplifyVBinOp(SDNode *N);
225 SDOperand visitSHL(SDNode *N);
226 SDOperand visitSRA(SDNode *N);
227 SDOperand visitSRL(SDNode *N);
228 SDOperand visitCTLZ(SDNode *N);
229 SDOperand visitCTTZ(SDNode *N);
230 SDOperand visitCTPOP(SDNode *N);
231 SDOperand visitSELECT(SDNode *N);
232 SDOperand visitSELECT_CC(SDNode *N);
233 SDOperand visitSETCC(SDNode *N);
234 SDOperand visitSIGN_EXTEND(SDNode *N);
235 SDOperand visitZERO_EXTEND(SDNode *N);
236 SDOperand visitANY_EXTEND(SDNode *N);
237 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
238 SDOperand visitTRUNCATE(SDNode *N);
239 SDOperand visitBIT_CONVERT(SDNode *N);
240 SDOperand visitFADD(SDNode *N);
241 SDOperand visitFSUB(SDNode *N);
242 SDOperand visitFMUL(SDNode *N);
243 SDOperand visitFDIV(SDNode *N);
244 SDOperand visitFREM(SDNode *N);
245 SDOperand visitFCOPYSIGN(SDNode *N);
246 SDOperand visitSINT_TO_FP(SDNode *N);
247 SDOperand visitUINT_TO_FP(SDNode *N);
248 SDOperand visitFP_TO_SINT(SDNode *N);
249 SDOperand visitFP_TO_UINT(SDNode *N);
250 SDOperand visitFP_ROUND(SDNode *N);
251 SDOperand visitFP_ROUND_INREG(SDNode *N);
252 SDOperand visitFP_EXTEND(SDNode *N);
253 SDOperand visitFNEG(SDNode *N);
254 SDOperand visitFABS(SDNode *N);
255 SDOperand visitBRCOND(SDNode *N);
256 SDOperand visitBR_CC(SDNode *N);
257 SDOperand visitLOAD(SDNode *N);
258 SDOperand visitSTORE(SDNode *N);
259 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
260 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N);
261 SDOperand visitBUILD_VECTOR(SDNode *N);
262 SDOperand visitCONCAT_VECTORS(SDNode *N);
263 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
265 SDOperand XformToShuffleWithZero(SDNode *N);
266 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
268 SDOperand visitShiftByConstant(SDNode *N, unsigned Amt);
270 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
271 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
272 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
273 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
274 SDOperand N3, ISD::CondCode CC,
275 bool NotExtCompare = false);
276 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
277 ISD::CondCode Cond, bool foldBooleans = true);
278 bool SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, unsigned HiOp);
279 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType);
280 SDOperand BuildSDIV(SDNode *N);
281 SDOperand BuildUDIV(SDNode *N);
282 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
283 SDOperand ReduceLoadWidth(SDNode *N);
285 SDOperand GetDemandedBits(SDOperand V, uint64_t Mask);
287 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
288 /// looking for aliasing nodes and adding them to the Aliases vector.
289 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
290 SmallVector<SDOperand, 8> &Aliases);
292 /// isAlias - Return true if there is any possibility that the two addresses
294 bool isAlias(SDOperand Ptr1, int64_t Size1,
295 const Value *SrcValue1, int SrcValueOffset1,
296 SDOperand Ptr2, int64_t Size2,
297 const Value *SrcValue2, int SrcValueOffset2);
299 /// FindAliasInfo - Extracts the relevant alias information from the memory
300 /// node. Returns true if the operand was a load.
301 bool FindAliasInfo(SDNode *N,
302 SDOperand &Ptr, int64_t &Size,
303 const Value *&SrcValue, int &SrcValueOffset);
305 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
306 /// looking for a better chain (aliasing node.)
307 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
310 DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
312 TLI(D.getTargetLoweringInfo()),
313 AfterLegalize(false),
316 /// Run - runs the dag combiner on all nodes in the work list
317 void Run(bool RunningAfterLegalize);
321 //===----------------------------------------------------------------------===//
322 // TargetLowering::DAGCombinerInfo implementation
323 //===----------------------------------------------------------------------===//
325 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
326 ((DAGCombiner*)DC)->AddToWorkList(N);
329 SDOperand TargetLowering::DAGCombinerInfo::
330 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
331 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
334 SDOperand TargetLowering::DAGCombinerInfo::
335 CombineTo(SDNode *N, SDOperand Res) {
336 return ((DAGCombiner*)DC)->CombineTo(N, Res);
340 SDOperand TargetLowering::DAGCombinerInfo::
341 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
342 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
346 //===----------------------------------------------------------------------===//
348 //===----------------------------------------------------------------------===//
350 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
351 /// specified expression for the same cost as the expression itself, or 2 if we
352 /// can compute the negated form more cheaply than the expression itself.
353 static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) {
354 // No compile time optimizations on this type.
355 if (Op.getValueType() == MVT::ppcf128)
358 // fneg is removable even if it has multiple uses.
359 if (Op.getOpcode() == ISD::FNEG) return 2;
361 // Don't allow anything with multiple uses.
362 if (!Op.hasOneUse()) return 0;
364 // Don't recurse exponentially.
365 if (Depth > 6) return 0;
367 switch (Op.getOpcode()) {
368 default: return false;
369 case ISD::ConstantFP:
372 // FIXME: determine better conditions for this xform.
373 if (!UnsafeFPMath) return 0;
376 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
379 return isNegatibleForFree(Op.getOperand(1), Depth+1);
381 // We can't turn -(A-B) into B-A when we honor signed zeros.
382 if (!UnsafeFPMath) return 0;
389 if (HonorSignDependentRoundingFPMath()) return 0;
391 // -(X*Y) -> (-X * Y) or (X*-Y)
392 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
395 return isNegatibleForFree(Op.getOperand(1), Depth+1);
400 return isNegatibleForFree(Op.getOperand(0), Depth+1);
404 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
405 /// returns the newly negated expression.
406 static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG,
407 unsigned Depth = 0) {
408 // fneg is removable even if it has multiple uses.
409 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
411 // Don't allow anything with multiple uses.
412 assert(Op.hasOneUse() && "Unknown reuse!");
414 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
415 switch (Op.getOpcode()) {
416 default: assert(0 && "Unknown code");
417 case ISD::ConstantFP: {
418 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
420 return DAG.getConstantFP(V, Op.getValueType());
423 // FIXME: determine better conditions for this xform.
424 assert(UnsafeFPMath);
427 if (isNegatibleForFree(Op.getOperand(0), Depth+1))
428 return DAG.getNode(ISD::FSUB, Op.getValueType(),
429 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
432 return DAG.getNode(ISD::FSUB, Op.getValueType(),
433 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1),
436 // We can't turn -(A-B) into B-A when we honor signed zeros.
437 assert(UnsafeFPMath);
440 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
441 if (N0CFP->getValueAPF().isZero())
442 return Op.getOperand(1);
445 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1),
450 assert(!HonorSignDependentRoundingFPMath());
453 if (isNegatibleForFree(Op.getOperand(0), Depth+1))
454 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
455 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
459 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
461 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1));
465 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
466 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1));
468 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(),
469 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
475 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
476 // that selects between the values 1 and 0, making it equivalent to a setcc.
477 // Also, set the incoming LHS, RHS, and CC references to the appropriate
478 // nodes based on the type of node we are checking. This simplifies life a
479 // bit for the callers.
480 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
482 if (N.getOpcode() == ISD::SETCC) {
483 LHS = N.getOperand(0);
484 RHS = N.getOperand(1);
485 CC = N.getOperand(2);
488 if (N.getOpcode() == ISD::SELECT_CC &&
489 N.getOperand(2).getOpcode() == ISD::Constant &&
490 N.getOperand(3).getOpcode() == ISD::Constant &&
491 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
492 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
493 LHS = N.getOperand(0);
494 RHS = N.getOperand(1);
495 CC = N.getOperand(4);
501 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
502 // one use. If this is true, it allows the users to invert the operation for
503 // free when it is profitable to do so.
504 static bool isOneUseSetCC(SDOperand N) {
505 SDOperand N0, N1, N2;
506 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
511 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
512 MVT::ValueType VT = N0.getValueType();
513 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
514 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
515 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
516 if (isa<ConstantSDNode>(N1)) {
517 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
518 AddToWorkList(OpNode.Val);
519 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
520 } else if (N0.hasOneUse()) {
521 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
522 AddToWorkList(OpNode.Val);
523 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
526 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
527 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
528 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
529 if (isa<ConstantSDNode>(N0)) {
530 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
531 AddToWorkList(OpNode.Val);
532 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
533 } else if (N1.hasOneUse()) {
534 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
535 AddToWorkList(OpNode.Val);
536 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
542 //===----------------------------------------------------------------------===//
543 // Main DAG Combiner implementation
544 //===----------------------------------------------------------------------===//
546 void DAGCombiner::Run(bool RunningAfterLegalize) {
547 // set the instance variable, so that the various visit routines may use it.
548 AfterLegalize = RunningAfterLegalize;
550 // Add all the dag nodes to the worklist.
551 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
552 E = DAG.allnodes_end(); I != E; ++I)
553 WorkList.push_back(I);
555 // Create a dummy node (which is not added to allnodes), that adds a reference
556 // to the root node, preventing it from being deleted, and tracking any
557 // changes of the root.
558 HandleSDNode Dummy(DAG.getRoot());
560 // The root of the dag may dangle to deleted nodes until the dag combiner is
561 // done. Set it to null to avoid confusion.
562 DAG.setRoot(SDOperand());
564 // while the worklist isn't empty, inspect the node on the end of it and
565 // try and combine it.
566 while (!WorkList.empty()) {
567 SDNode *N = WorkList.back();
570 // If N has no uses, it is dead. Make sure to revisit all N's operands once
571 // N is deleted from the DAG, since they too may now be dead or may have a
572 // reduced number of uses, allowing other xforms.
573 if (N->use_empty() && N != &Dummy) {
574 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
575 AddToWorkList(N->getOperand(i).Val);
581 SDOperand RV = combine(N);
585 // If we get back the same node we passed in, rather than a new node or
586 // zero, we know that the node must have defined multiple values and
587 // CombineTo was used. Since CombineTo takes care of the worklist
588 // mechanics for us, we have no work to do in this case.
590 assert(N->getOpcode() != ISD::DELETED_NODE &&
591 RV.Val->getOpcode() != ISD::DELETED_NODE &&
592 "Node was deleted but visit returned new node!");
594 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
595 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
597 std::vector<SDNode*> NowDead;
598 if (N->getNumValues() == RV.Val->getNumValues())
599 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
601 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
603 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
606 // Push the new node and any users onto the worklist
607 AddToWorkList(RV.Val);
608 AddUsersToWorkList(RV.Val);
610 // Nodes can be reintroduced into the worklist. Make sure we do not
611 // process a node that has been replaced.
612 removeFromWorkList(N);
613 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
614 removeFromWorkList(NowDead[i]);
616 // Finally, since the node is now dead, remove it from the graph.
622 // If the root changed (e.g. it was a dead load, update the root).
623 DAG.setRoot(Dummy.getValue());
626 SDOperand DAGCombiner::visit(SDNode *N) {
627 switch(N->getOpcode()) {
629 case ISD::TokenFactor: return visitTokenFactor(N);
630 case ISD::ADD: return visitADD(N);
631 case ISD::SUB: return visitSUB(N);
632 case ISD::ADDC: return visitADDC(N);
633 case ISD::ADDE: return visitADDE(N);
634 case ISD::MUL: return visitMUL(N);
635 case ISD::SDIV: return visitSDIV(N);
636 case ISD::UDIV: return visitUDIV(N);
637 case ISD::SREM: return visitSREM(N);
638 case ISD::UREM: return visitUREM(N);
639 case ISD::MULHU: return visitMULHU(N);
640 case ISD::MULHS: return visitMULHS(N);
641 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
642 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
643 case ISD::SDIVREM: return visitSDIVREM(N);
644 case ISD::UDIVREM: return visitUDIVREM(N);
645 case ISD::AND: return visitAND(N);
646 case ISD::OR: return visitOR(N);
647 case ISD::XOR: return visitXOR(N);
648 case ISD::SHL: return visitSHL(N);
649 case ISD::SRA: return visitSRA(N);
650 case ISD::SRL: return visitSRL(N);
651 case ISD::CTLZ: return visitCTLZ(N);
652 case ISD::CTTZ: return visitCTTZ(N);
653 case ISD::CTPOP: return visitCTPOP(N);
654 case ISD::SELECT: return visitSELECT(N);
655 case ISD::SELECT_CC: return visitSELECT_CC(N);
656 case ISD::SETCC: return visitSETCC(N);
657 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
658 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
659 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
660 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
661 case ISD::TRUNCATE: return visitTRUNCATE(N);
662 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
663 case ISD::FADD: return visitFADD(N);
664 case ISD::FSUB: return visitFSUB(N);
665 case ISD::FMUL: return visitFMUL(N);
666 case ISD::FDIV: return visitFDIV(N);
667 case ISD::FREM: return visitFREM(N);
668 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
669 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
670 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
671 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
672 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
673 case ISD::FP_ROUND: return visitFP_ROUND(N);
674 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
675 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
676 case ISD::FNEG: return visitFNEG(N);
677 case ISD::FABS: return visitFABS(N);
678 case ISD::BRCOND: return visitBRCOND(N);
679 case ISD::BR_CC: return visitBR_CC(N);
680 case ISD::LOAD: return visitLOAD(N);
681 case ISD::STORE: return visitSTORE(N);
682 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
683 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
684 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
685 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
686 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
691 SDOperand DAGCombiner::combine(SDNode *N) {
693 SDOperand RV = visit(N);
695 // If nothing happened, try a target-specific DAG combine.
697 assert(N->getOpcode() != ISD::DELETED_NODE &&
698 "Node was deleted but visit returned NULL!");
700 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
701 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
703 // Expose the DAG combiner to the target combiner impls.
704 TargetLowering::DAGCombinerInfo
705 DagCombineInfo(DAG, !AfterLegalize, false, this);
707 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
714 /// getInputChainForNode - Given a node, return its input chain if it has one,
715 /// otherwise return a null sd operand.
716 static SDOperand getInputChainForNode(SDNode *N) {
717 if (unsigned NumOps = N->getNumOperands()) {
718 if (N->getOperand(0).getValueType() == MVT::Other)
719 return N->getOperand(0);
720 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
721 return N->getOperand(NumOps-1);
722 for (unsigned i = 1; i < NumOps-1; ++i)
723 if (N->getOperand(i).getValueType() == MVT::Other)
724 return N->getOperand(i);
726 return SDOperand(0, 0);
729 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
730 // If N has two operands, where one has an input chain equal to the other,
731 // the 'other' chain is redundant.
732 if (N->getNumOperands() == 2) {
733 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
734 return N->getOperand(0);
735 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
736 return N->getOperand(1);
739 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
740 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
741 SmallPtrSet<SDNode*, 16> SeenOps;
742 bool Changed = false; // If we should replace this token factor.
744 // Start out with this token factor.
747 // Iterate through token factors. The TFs grows when new token factors are
749 for (unsigned i = 0; i < TFs.size(); ++i) {
752 // Check each of the operands.
753 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
754 SDOperand Op = TF->getOperand(i);
756 switch (Op.getOpcode()) {
757 case ISD::EntryToken:
758 // Entry tokens don't need to be added to the list. They are
763 case ISD::TokenFactor:
764 if ((CombinerAA || Op.hasOneUse()) &&
765 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
766 // Queue up for processing.
767 TFs.push_back(Op.Val);
768 // Clean up in case the token factor is removed.
769 AddToWorkList(Op.Val);
776 // Only add if it isn't already in the list.
777 if (SeenOps.insert(Op.Val))
788 // If we've change things around then replace token factor.
790 if (Ops.size() == 0) {
791 // The entry token is the only possible outcome.
792 Result = DAG.getEntryNode();
794 // New and improved token factor.
795 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
798 // Don't add users to work list.
799 return CombineTo(N, Result, false);
806 SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
807 MVT::ValueType VT = N0.getValueType();
808 SDOperand N00 = N0.getOperand(0);
809 SDOperand N01 = N0.getOperand(1);
810 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
811 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
812 isa<ConstantSDNode>(N00.getOperand(1))) {
813 N0 = DAG.getNode(ISD::ADD, VT,
814 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01),
815 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01));
816 return DAG.getNode(ISD::ADD, VT, N0, N1);
822 SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp,
824 MVT::ValueType VT = N->getValueType(0);
825 unsigned Opc = N->getOpcode();
826 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
827 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
828 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
829 ISD::CondCode CC = ISD::SETCC_INVALID;
831 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
833 SDOperand CCOp = Slct.getOperand(0);
834 if (CCOp.getOpcode() == ISD::SETCC)
835 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
838 bool DoXform = false;
840 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
842 if (LHS.getOpcode() == ISD::Constant &&
843 cast<ConstantSDNode>(LHS)->isNullValue())
845 else if (CC != ISD::SETCC_INVALID &&
846 RHS.getOpcode() == ISD::Constant &&
847 cast<ConstantSDNode>(RHS)->isNullValue()) {
849 bool isInt = MVT::isInteger(isSlctCC ? Slct.getOperand(0).getValueType()
850 : Slct.getOperand(0).getOperand(0).getValueType());
851 CC = ISD::getSetCCInverse(CC, isInt);
857 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS);
859 return DAG.getSelectCC(OtherOp, Result,
860 Slct.getOperand(0), Slct.getOperand(1), CC);
861 SDOperand CCOp = Slct.getOperand(0);
863 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0),
864 CCOp.getOperand(1), CC);
865 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result);
870 SDOperand DAGCombiner::visitADD(SDNode *N) {
871 SDOperand N0 = N->getOperand(0);
872 SDOperand N1 = N->getOperand(1);
873 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
874 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
875 MVT::ValueType VT = N0.getValueType();
878 if (MVT::isVector(VT)) {
879 SDOperand FoldedVOp = SimplifyVBinOp(N);
880 if (FoldedVOp.Val) return FoldedVOp;
883 // fold (add x, undef) -> undef
884 if (N0.getOpcode() == ISD::UNDEF)
886 if (N1.getOpcode() == ISD::UNDEF)
888 // fold (add c1, c2) -> c1+c2
890 return DAG.getNode(ISD::ADD, VT, N0, N1);
891 // canonicalize constant to RHS
893 return DAG.getNode(ISD::ADD, VT, N1, N0);
894 // fold (add x, 0) -> x
895 if (N1C && N1C->isNullValue())
897 // fold ((c1-A)+c2) -> (c1+c2)-A
898 if (N1C && N0.getOpcode() == ISD::SUB)
899 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
900 return DAG.getNode(ISD::SUB, VT,
901 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
904 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
907 // fold ((0-A) + B) -> B-A
908 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
909 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
910 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
911 // fold (A + (0-B)) -> A-B
912 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
913 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
914 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
915 // fold (A+(B-A)) -> B
916 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
917 return N1.getOperand(0);
919 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
920 return SDOperand(N, 0);
922 // fold (a+b) -> (a|b) iff a and b share no bits.
923 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
924 uint64_t LHSZero, LHSOne;
925 uint64_t RHSZero, RHSOne;
926 uint64_t Mask = MVT::getIntVTBitMask(VT);
927 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
929 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
931 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
932 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
933 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
934 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
935 return DAG.getNode(ISD::OR, VT, N0, N1);
939 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
940 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) {
941 SDOperand Result = combineShlAddConstant(N0, N1, DAG);
942 if (Result.Val) return Result;
944 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) {
945 SDOperand Result = combineShlAddConstant(N1, N0, DAG);
946 if (Result.Val) return Result;
949 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
950 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) {
951 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG);
952 if (Result.Val) return Result;
954 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
955 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
956 if (Result.Val) return Result;
962 SDOperand DAGCombiner::visitADDC(SDNode *N) {
963 SDOperand N0 = N->getOperand(0);
964 SDOperand N1 = N->getOperand(1);
965 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
966 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
967 MVT::ValueType VT = N0.getValueType();
969 // If the flag result is dead, turn this into an ADD.
970 if (N->hasNUsesOfValue(0, 1))
971 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0),
972 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
974 // canonicalize constant to RHS.
976 SDOperand Ops[] = { N1, N0 };
977 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
980 // fold (addc x, 0) -> x + no carry out
981 if (N1C && N1C->isNullValue())
982 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
984 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
985 uint64_t LHSZero, LHSOne;
986 uint64_t RHSZero, RHSOne;
987 uint64_t Mask = MVT::getIntVTBitMask(VT);
988 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
990 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
992 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
993 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
994 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
995 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
996 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1),
997 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
1003 SDOperand DAGCombiner::visitADDE(SDNode *N) {
1004 SDOperand N0 = N->getOperand(0);
1005 SDOperand N1 = N->getOperand(1);
1006 SDOperand CarryIn = N->getOperand(2);
1007 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1008 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1009 //MVT::ValueType VT = N0.getValueType();
1011 // canonicalize constant to RHS
1013 SDOperand Ops[] = { N1, N0, CarryIn };
1014 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3);
1017 // fold (adde x, y, false) -> (addc x, y)
1018 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) {
1019 SDOperand Ops[] = { N1, N0 };
1020 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
1028 SDOperand DAGCombiner::visitSUB(SDNode *N) {
1029 SDOperand N0 = N->getOperand(0);
1030 SDOperand N1 = N->getOperand(1);
1031 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1032 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1033 MVT::ValueType VT = N0.getValueType();
1036 if (MVT::isVector(VT)) {
1037 SDOperand FoldedVOp = SimplifyVBinOp(N);
1038 if (FoldedVOp.Val) return FoldedVOp;
1041 // fold (sub x, x) -> 0
1043 return DAG.getConstant(0, N->getValueType(0));
1044 // fold (sub c1, c2) -> c1-c2
1046 return DAG.getNode(ISD::SUB, VT, N0, N1);
1047 // fold (sub x, c) -> (add x, -c)
1049 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
1050 // fold (A+B)-A -> B
1051 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1052 return N0.getOperand(1);
1053 // fold (A+B)-B -> A
1054 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1055 return N0.getOperand(0);
1056 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1057 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
1058 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
1059 if (Result.Val) return Result;
1061 // If either operand of a sub is undef, the result is undef
1062 if (N0.getOpcode() == ISD::UNDEF)
1064 if (N1.getOpcode() == ISD::UNDEF)
1070 SDOperand DAGCombiner::visitMUL(SDNode *N) {
1071 SDOperand N0 = N->getOperand(0);
1072 SDOperand N1 = N->getOperand(1);
1073 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1074 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1075 MVT::ValueType VT = N0.getValueType();
1078 if (MVT::isVector(VT)) {
1079 SDOperand FoldedVOp = SimplifyVBinOp(N);
1080 if (FoldedVOp.Val) return FoldedVOp;
1083 // fold (mul x, undef) -> 0
1084 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1085 return DAG.getConstant(0, VT);
1086 // fold (mul c1, c2) -> c1*c2
1088 return DAG.getNode(ISD::MUL, VT, N0, N1);
1089 // canonicalize constant to RHS
1091 return DAG.getNode(ISD::MUL, VT, N1, N0);
1092 // fold (mul x, 0) -> 0
1093 if (N1C && N1C->isNullValue())
1095 // fold (mul x, -1) -> 0-x
1096 if (N1C && N1C->isAllOnesValue())
1097 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1098 // fold (mul x, (1 << c)) -> x << c
1099 if (N1C && isPowerOf2_64(N1C->getValue()))
1100 return DAG.getNode(ISD::SHL, VT, N0,
1101 DAG.getConstant(Log2_64(N1C->getValue()),
1102 TLI.getShiftAmountTy()));
1103 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1104 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
1105 // FIXME: If the input is something that is easily negated (e.g. a
1106 // single-use add), we should put the negate there.
1107 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
1108 DAG.getNode(ISD::SHL, VT, N0,
1109 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
1110 TLI.getShiftAmountTy())));
1113 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1114 if (N1C && N0.getOpcode() == ISD::SHL &&
1115 isa<ConstantSDNode>(N0.getOperand(1))) {
1116 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
1117 AddToWorkList(C3.Val);
1118 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
1121 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1124 SDOperand Sh(0,0), Y(0,0);
1125 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1126 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1127 N0.Val->hasOneUse()) {
1129 } else if (N1.getOpcode() == ISD::SHL &&
1130 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
1134 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
1135 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
1138 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1139 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1140 isa<ConstantSDNode>(N0.getOperand(1))) {
1141 return DAG.getNode(ISD::ADD, VT,
1142 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
1143 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
1147 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
1154 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
1155 SDOperand N0 = N->getOperand(0);
1156 SDOperand N1 = N->getOperand(1);
1157 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1158 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1159 MVT::ValueType VT = N->getValueType(0);
1162 if (MVT::isVector(VT)) {
1163 SDOperand FoldedVOp = SimplifyVBinOp(N);
1164 if (FoldedVOp.Val) return FoldedVOp;
1167 // fold (sdiv c1, c2) -> c1/c2
1168 if (N0C && N1C && !N1C->isNullValue())
1169 return DAG.getNode(ISD::SDIV, VT, N0, N1);
1170 // fold (sdiv X, 1) -> X
1171 if (N1C && N1C->getSignExtended() == 1LL)
1173 // fold (sdiv X, -1) -> 0-X
1174 if (N1C && N1C->isAllOnesValue())
1175 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1176 // If we know the sign bits of both operands are zero, strength reduce to a
1177 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1178 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1179 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1180 DAG.MaskedValueIsZero(N0, SignBit))
1181 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
1182 // fold (sdiv X, pow2) -> simple ops after legalize
1183 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
1184 (isPowerOf2_64(N1C->getSignExtended()) ||
1185 isPowerOf2_64(-N1C->getSignExtended()))) {
1186 // If dividing by powers of two is cheap, then don't perform the following
1188 if (TLI.isPow2DivCheap())
1190 int64_t pow2 = N1C->getSignExtended();
1191 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1192 unsigned lg2 = Log2_64(abs2);
1193 // Splat the sign bit into the register
1194 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
1195 DAG.getConstant(MVT::getSizeInBits(VT)-1,
1196 TLI.getShiftAmountTy()));
1197 AddToWorkList(SGN.Val);
1198 // Add (N0 < 0) ? abs2 - 1 : 0;
1199 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
1200 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
1201 TLI.getShiftAmountTy()));
1202 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
1203 AddToWorkList(SRL.Val);
1204 AddToWorkList(ADD.Val); // Divide by pow2
1205 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
1206 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
1207 // If we're dividing by a positive value, we're done. Otherwise, we must
1208 // negate the result.
1211 AddToWorkList(SRA.Val);
1212 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
1214 // if integer divide is expensive and we satisfy the requirements, emit an
1215 // alternate sequence.
1216 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
1217 !TLI.isIntDivCheap()) {
1218 SDOperand Op = BuildSDIV(N);
1219 if (Op.Val) return Op;
1223 if (N0.getOpcode() == ISD::UNDEF)
1224 return DAG.getConstant(0, VT);
1225 // X / undef -> undef
1226 if (N1.getOpcode() == ISD::UNDEF)
1232 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
1233 SDOperand N0 = N->getOperand(0);
1234 SDOperand N1 = N->getOperand(1);
1235 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1236 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1237 MVT::ValueType VT = N->getValueType(0);
1240 if (MVT::isVector(VT)) {
1241 SDOperand FoldedVOp = SimplifyVBinOp(N);
1242 if (FoldedVOp.Val) return FoldedVOp;
1245 // fold (udiv c1, c2) -> c1/c2
1246 if (N0C && N1C && !N1C->isNullValue())
1247 return DAG.getNode(ISD::UDIV, VT, N0, N1);
1248 // fold (udiv x, (1 << c)) -> x >>u c
1249 if (N1C && isPowerOf2_64(N1C->getValue()))
1250 return DAG.getNode(ISD::SRL, VT, N0,
1251 DAG.getConstant(Log2_64(N1C->getValue()),
1252 TLI.getShiftAmountTy()));
1253 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1254 if (N1.getOpcode() == ISD::SHL) {
1255 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1256 if (isPowerOf2_64(SHC->getValue())) {
1257 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
1258 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
1259 DAG.getConstant(Log2_64(SHC->getValue()),
1261 AddToWorkList(Add.Val);
1262 return DAG.getNode(ISD::SRL, VT, N0, Add);
1266 // fold (udiv x, c) -> alternate
1267 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
1268 SDOperand Op = BuildUDIV(N);
1269 if (Op.Val) return Op;
1273 if (N0.getOpcode() == ISD::UNDEF)
1274 return DAG.getConstant(0, VT);
1275 // X / undef -> undef
1276 if (N1.getOpcode() == ISD::UNDEF)
1282 SDOperand DAGCombiner::visitSREM(SDNode *N) {
1283 SDOperand N0 = N->getOperand(0);
1284 SDOperand N1 = N->getOperand(1);
1285 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1286 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1287 MVT::ValueType VT = N->getValueType(0);
1289 // fold (srem c1, c2) -> c1%c2
1290 if (N0C && N1C && !N1C->isNullValue())
1291 return DAG.getNode(ISD::SREM, VT, N0, N1);
1292 // If we know the sign bits of both operands are zero, strength reduce to a
1293 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1294 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1295 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1296 DAG.MaskedValueIsZero(N0, SignBit))
1297 return DAG.getNode(ISD::UREM, VT, N0, N1);
1299 // If X/C can be simplified by the division-by-constant logic, lower
1300 // X%C to the equivalent of X-X/C*C.
1301 if (N1C && !N1C->isNullValue()) {
1302 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
1303 SDOperand OptimizedDiv = combine(Div.Val);
1304 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) {
1305 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
1306 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1307 AddToWorkList(Mul.Val);
1313 if (N0.getOpcode() == ISD::UNDEF)
1314 return DAG.getConstant(0, VT);
1315 // X % undef -> undef
1316 if (N1.getOpcode() == ISD::UNDEF)
1322 SDOperand DAGCombiner::visitUREM(SDNode *N) {
1323 SDOperand N0 = N->getOperand(0);
1324 SDOperand N1 = N->getOperand(1);
1325 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1326 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1327 MVT::ValueType VT = N->getValueType(0);
1329 // fold (urem c1, c2) -> c1%c2
1330 if (N0C && N1C && !N1C->isNullValue())
1331 return DAG.getNode(ISD::UREM, VT, N0, N1);
1332 // fold (urem x, pow2) -> (and x, pow2-1)
1333 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
1334 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
1335 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1336 if (N1.getOpcode() == ISD::SHL) {
1337 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1338 if (isPowerOf2_64(SHC->getValue())) {
1339 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
1340 AddToWorkList(Add.Val);
1341 return DAG.getNode(ISD::AND, VT, N0, Add);
1346 // If X/C can be simplified by the division-by-constant logic, lower
1347 // X%C to the equivalent of X-X/C*C.
1348 if (N1C && !N1C->isNullValue()) {
1349 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
1350 SDOperand OptimizedDiv = combine(Div.Val);
1351 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) {
1352 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
1353 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1354 AddToWorkList(Mul.Val);
1360 if (N0.getOpcode() == ISD::UNDEF)
1361 return DAG.getConstant(0, VT);
1362 // X % undef -> undef
1363 if (N1.getOpcode() == ISD::UNDEF)
1369 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
1370 SDOperand N0 = N->getOperand(0);
1371 SDOperand N1 = N->getOperand(1);
1372 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1373 MVT::ValueType VT = N->getValueType(0);
1375 // fold (mulhs x, 0) -> 0
1376 if (N1C && N1C->isNullValue())
1378 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1379 if (N1C && N1C->getValue() == 1)
1380 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
1381 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
1382 TLI.getShiftAmountTy()));
1383 // fold (mulhs x, undef) -> 0
1384 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1385 return DAG.getConstant(0, VT);
1390 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
1391 SDOperand N0 = N->getOperand(0);
1392 SDOperand N1 = N->getOperand(1);
1393 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1394 MVT::ValueType VT = N->getValueType(0);
1396 // fold (mulhu x, 0) -> 0
1397 if (N1C && N1C->isNullValue())
1399 // fold (mulhu x, 1) -> 0
1400 if (N1C && N1C->getValue() == 1)
1401 return DAG.getConstant(0, N0.getValueType());
1402 // fold (mulhu x, undef) -> 0
1403 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1404 return DAG.getConstant(0, VT);
1409 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1410 /// compute two values. LoOp and HiOp give the opcodes for the two computations
1411 /// that are being performed. Return true if a simplification was made.
1413 bool DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N,
1414 unsigned LoOp, unsigned HiOp) {
1415 // If the high half is not needed, just compute the low half.
1416 bool HiExists = N->hasAnyUseOfValue(1);
1419 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1420 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0),
1421 DAG.getNode(LoOp, N->getValueType(0),
1423 N->getNumOperands()));
1427 // If the low half is not needed, just compute the high half.
1428 bool LoExists = N->hasAnyUseOfValue(0);
1431 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
1432 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1),
1433 DAG.getNode(HiOp, N->getValueType(1),
1435 N->getNumOperands()));
1439 // If both halves are used, return as it is.
1440 if (LoExists && HiExists)
1443 // If the two computed results can be simplified separately, separate them.
1444 bool RetVal = false;
1446 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0),
1447 N->op_begin(), N->getNumOperands());
1448 SDOperand LoOpt = combine(Lo.Val);
1449 if (LoOpt.Val && LoOpt != Lo &&
1450 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())) {
1452 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), LoOpt);
1454 DAG.DeleteNode(Lo.Val);
1458 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1),
1459 N->op_begin(), N->getNumOperands());
1460 SDOperand HiOpt = combine(Hi.Val);
1461 if (HiOpt.Val && HiOpt != Hi &&
1462 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())) {
1464 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), HiOpt);
1466 DAG.DeleteNode(Hi.Val);
1472 SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) {
1474 if (SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS))
1480 SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) {
1482 if (SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU))
1488 SDOperand DAGCombiner::visitSDIVREM(SDNode *N) {
1490 if (SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM))
1496 SDOperand DAGCombiner::visitUDIVREM(SDNode *N) {
1498 if (SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM))
1504 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1505 /// two operands of the same opcode, try to simplify it.
1506 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1507 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
1508 MVT::ValueType VT = N0.getValueType();
1509 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1511 // For each of OP in AND/OR/XOR:
1512 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1513 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1514 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1515 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1516 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1517 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1518 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1519 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1520 N0.getOperand(0).getValueType(),
1521 N0.getOperand(0), N1.getOperand(0));
1522 AddToWorkList(ORNode.Val);
1523 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1526 // For each of OP in SHL/SRL/SRA/AND...
1527 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1528 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1529 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1530 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1531 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1532 N0.getOperand(1) == N1.getOperand(1)) {
1533 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1534 N0.getOperand(0).getValueType(),
1535 N0.getOperand(0), N1.getOperand(0));
1536 AddToWorkList(ORNode.Val);
1537 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1543 SDOperand DAGCombiner::visitAND(SDNode *N) {
1544 SDOperand N0 = N->getOperand(0);
1545 SDOperand N1 = N->getOperand(1);
1546 SDOperand LL, LR, RL, RR, CC0, CC1;
1547 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1548 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1549 MVT::ValueType VT = N1.getValueType();
1552 if (MVT::isVector(VT)) {
1553 SDOperand FoldedVOp = SimplifyVBinOp(N);
1554 if (FoldedVOp.Val) return FoldedVOp;
1557 // fold (and x, undef) -> 0
1558 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1559 return DAG.getConstant(0, VT);
1560 // fold (and c1, c2) -> c1&c2
1562 return DAG.getNode(ISD::AND, VT, N0, N1);
1563 // canonicalize constant to RHS
1565 return DAG.getNode(ISD::AND, VT, N1, N0);
1566 // fold (and x, -1) -> x
1567 if (N1C && N1C->isAllOnesValue())
1569 // if (and x, c) is known to be zero, return 0
1570 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1571 return DAG.getConstant(0, VT);
1573 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1576 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1577 if (N1C && N0.getOpcode() == ISD::OR)
1578 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1579 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1581 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1582 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1583 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1584 if (DAG.MaskedValueIsZero(N0.getOperand(0),
1585 ~N1C->getValue() & InMask)) {
1586 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1589 // Replace uses of the AND with uses of the Zero extend node.
1592 // We actually want to replace all uses of the any_extend with the
1593 // zero_extend, to avoid duplicating things. This will later cause this
1594 // AND to be folded.
1595 CombineTo(N0.Val, Zext);
1596 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1599 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1600 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1601 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1602 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1604 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1605 MVT::isInteger(LL.getValueType())) {
1606 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1607 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1608 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1609 AddToWorkList(ORNode.Val);
1610 return DAG.getSetCC(VT, ORNode, LR, Op1);
1612 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1613 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1614 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1615 AddToWorkList(ANDNode.Val);
1616 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1618 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1619 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1620 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1621 AddToWorkList(ORNode.Val);
1622 return DAG.getSetCC(VT, ORNode, LR, Op1);
1625 // canonicalize equivalent to ll == rl
1626 if (LL == RR && LR == RL) {
1627 Op1 = ISD::getSetCCSwappedOperands(Op1);
1630 if (LL == RL && LR == RR) {
1631 bool isInteger = MVT::isInteger(LL.getValueType());
1632 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1633 if (Result != ISD::SETCC_INVALID)
1634 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1638 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1639 if (N0.getOpcode() == N1.getOpcode()) {
1640 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1641 if (Tmp.Val) return Tmp;
1644 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1645 // fold (and (sra)) -> (and (srl)) when possible.
1646 if (!MVT::isVector(VT) &&
1647 SimplifyDemandedBits(SDOperand(N, 0)))
1648 return SDOperand(N, 0);
1649 // fold (zext_inreg (extload x)) -> (zextload x)
1650 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
1651 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1652 MVT::ValueType EVT = LN0->getLoadedVT();
1653 // If we zero all the possible extended bits, then we can turn this into
1654 // a zextload if we are running before legalize or the operation is legal.
1655 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1656 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1657 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1658 LN0->getBasePtr(), LN0->getSrcValue(),
1659 LN0->getSrcValueOffset(), EVT,
1661 LN0->getAlignment());
1663 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1664 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1667 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1668 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
1670 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1671 MVT::ValueType EVT = LN0->getLoadedVT();
1672 // If we zero all the possible extended bits, then we can turn this into
1673 // a zextload if we are running before legalize or the operation is legal.
1674 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1675 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1676 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1677 LN0->getBasePtr(), LN0->getSrcValue(),
1678 LN0->getSrcValueOffset(), EVT,
1680 LN0->getAlignment());
1682 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1683 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1687 // fold (and (load x), 255) -> (zextload x, i8)
1688 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1689 if (N1C && N0.getOpcode() == ISD::LOAD) {
1690 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1691 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1692 LN0->getAddressingMode() == ISD::UNINDEXED &&
1694 MVT::ValueType EVT, LoadedVT;
1695 if (N1C->getValue() == 255)
1697 else if (N1C->getValue() == 65535)
1699 else if (N1C->getValue() == ~0U)
1704 LoadedVT = LN0->getLoadedVT();
1705 if (EVT != MVT::Other && LoadedVT > EVT &&
1706 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1707 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1708 // For big endian targets, we need to add an offset to the pointer to
1709 // load the correct bytes. For little endian systems, we merely need to
1710 // read fewer bytes from the same pointer.
1711 unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8;
1712 unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8;
1713 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
1714 unsigned Alignment = LN0->getAlignment();
1715 SDOperand NewPtr = LN0->getBasePtr();
1716 if (!TLI.isLittleEndian()) {
1717 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1718 DAG.getConstant(PtrOff, PtrType));
1719 Alignment = MinAlign(Alignment, PtrOff);
1721 AddToWorkList(NewPtr.Val);
1723 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1724 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
1725 LN0->isVolatile(), Alignment);
1727 CombineTo(N0.Val, Load, Load.getValue(1));
1728 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1736 SDOperand DAGCombiner::visitOR(SDNode *N) {
1737 SDOperand N0 = N->getOperand(0);
1738 SDOperand N1 = N->getOperand(1);
1739 SDOperand LL, LR, RL, RR, CC0, CC1;
1740 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1741 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1742 MVT::ValueType VT = N1.getValueType();
1743 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1746 if (MVT::isVector(VT)) {
1747 SDOperand FoldedVOp = SimplifyVBinOp(N);
1748 if (FoldedVOp.Val) return FoldedVOp;
1751 // fold (or x, undef) -> -1
1752 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1753 return DAG.getConstant(~0ULL, VT);
1754 // fold (or c1, c2) -> c1|c2
1756 return DAG.getNode(ISD::OR, VT, N0, N1);
1757 // canonicalize constant to RHS
1759 return DAG.getNode(ISD::OR, VT, N1, N0);
1760 // fold (or x, 0) -> x
1761 if (N1C && N1C->isNullValue())
1763 // fold (or x, -1) -> -1
1764 if (N1C && N1C->isAllOnesValue())
1766 // fold (or x, c) -> c iff (x & ~c) == 0
1768 DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1771 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1774 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1775 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1776 isa<ConstantSDNode>(N0.getOperand(1))) {
1777 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1778 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1780 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1782 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1783 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1784 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1785 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1787 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1788 MVT::isInteger(LL.getValueType())) {
1789 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1790 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1791 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1792 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1793 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1794 AddToWorkList(ORNode.Val);
1795 return DAG.getSetCC(VT, ORNode, LR, Op1);
1797 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1798 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1799 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1800 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1801 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1802 AddToWorkList(ANDNode.Val);
1803 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1806 // canonicalize equivalent to ll == rl
1807 if (LL == RR && LR == RL) {
1808 Op1 = ISD::getSetCCSwappedOperands(Op1);
1811 if (LL == RL && LR == RR) {
1812 bool isInteger = MVT::isInteger(LL.getValueType());
1813 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1814 if (Result != ISD::SETCC_INVALID)
1815 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1819 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1820 if (N0.getOpcode() == N1.getOpcode()) {
1821 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1822 if (Tmp.Val) return Tmp;
1825 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1826 if (N0.getOpcode() == ISD::AND &&
1827 N1.getOpcode() == ISD::AND &&
1828 N0.getOperand(1).getOpcode() == ISD::Constant &&
1829 N1.getOperand(1).getOpcode() == ISD::Constant &&
1830 // Don't increase # computations.
1831 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1832 // We can only do this xform if we know that bits from X that are set in C2
1833 // but not in C1 are already zero. Likewise for Y.
1834 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1835 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1837 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1838 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1839 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1840 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1845 // See if this is some rotate idiom.
1846 if (SDNode *Rot = MatchRotate(N0, N1))
1847 return SDOperand(Rot, 0);
1853 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1854 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1855 if (Op.getOpcode() == ISD::AND) {
1856 if (isa<ConstantSDNode>(Op.getOperand(1))) {
1857 Mask = Op.getOperand(1);
1858 Op = Op.getOperand(0);
1864 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1872 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1873 // idioms for rotate, and if the target supports rotation instructions, generate
1875 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1876 // Must be a legal type. Expanded an promoted things won't work with rotates.
1877 MVT::ValueType VT = LHS.getValueType();
1878 if (!TLI.isTypeLegal(VT)) return 0;
1880 // The target must have at least one rotate flavor.
1881 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1882 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1883 if (!HasROTL && !HasROTR) return 0;
1885 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1886 SDOperand LHSShift; // The shift.
1887 SDOperand LHSMask; // AND value if any.
1888 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1889 return 0; // Not part of a rotate.
1891 SDOperand RHSShift; // The shift.
1892 SDOperand RHSMask; // AND value if any.
1893 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1894 return 0; // Not part of a rotate.
1896 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1897 return 0; // Not shifting the same value.
1899 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1900 return 0; // Shifts must disagree.
1902 // Canonicalize shl to left side in a shl/srl pair.
1903 if (RHSShift.getOpcode() == ISD::SHL) {
1904 std::swap(LHS, RHS);
1905 std::swap(LHSShift, RHSShift);
1906 std::swap(LHSMask , RHSMask );
1909 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1910 SDOperand LHSShiftArg = LHSShift.getOperand(0);
1911 SDOperand LHSShiftAmt = LHSShift.getOperand(1);
1912 SDOperand RHSShiftAmt = RHSShift.getOperand(1);
1914 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1915 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1916 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
1917 RHSShiftAmt.getOpcode() == ISD::Constant) {
1918 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue();
1919 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue();
1920 if ((LShVal + RShVal) != OpSizeInBits)
1925 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt);
1927 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
1929 // If there is an AND of either shifted operand, apply it to the result.
1930 if (LHSMask.Val || RHSMask.Val) {
1931 uint64_t Mask = MVT::getIntVTBitMask(VT);
1934 uint64_t RHSBits = (1ULL << LShVal)-1;
1935 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1938 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1939 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1942 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1948 // If there is a mask here, and we have a variable shift, we can't be sure
1949 // that we're masking out the right stuff.
1950 if (LHSMask.Val || RHSMask.Val)
1953 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1954 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1955 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
1956 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
1957 if (ConstantSDNode *SUBC =
1958 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
1959 if (SUBC->getValue() == OpSizeInBits)
1961 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1963 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1967 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1968 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1969 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
1970 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
1971 if (ConstantSDNode *SUBC =
1972 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
1973 if (SUBC->getValue() == OpSizeInBits)
1975 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1977 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1981 // Look for sign/zext/any-extended cases:
1982 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1983 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1984 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) &&
1985 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1986 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1987 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) {
1988 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0);
1989 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0);
1990 if (RExtOp0.getOpcode() == ISD::SUB &&
1991 RExtOp0.getOperand(1) == LExtOp0) {
1992 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1994 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1995 // (rotl x, (sub 32, y))
1996 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
1997 if (SUBC->getValue() == OpSizeInBits) {
1999 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
2001 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
2004 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2005 RExtOp0 == LExtOp0.getOperand(1)) {
2006 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
2008 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
2009 // (rotr x, (sub 32, y))
2010 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2011 if (SUBC->getValue() == OpSizeInBits) {
2013 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val;
2015 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
2025 SDOperand DAGCombiner::visitXOR(SDNode *N) {
2026 SDOperand N0 = N->getOperand(0);
2027 SDOperand N1 = N->getOperand(1);
2028 SDOperand LHS, RHS, CC;
2029 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2030 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2031 MVT::ValueType VT = N0.getValueType();
2034 if (MVT::isVector(VT)) {
2035 SDOperand FoldedVOp = SimplifyVBinOp(N);
2036 if (FoldedVOp.Val) return FoldedVOp;
2039 // fold (xor x, undef) -> undef
2040 if (N0.getOpcode() == ISD::UNDEF)
2042 if (N1.getOpcode() == ISD::UNDEF)
2044 // fold (xor c1, c2) -> c1^c2
2046 return DAG.getNode(ISD::XOR, VT, N0, N1);
2047 // canonicalize constant to RHS
2049 return DAG.getNode(ISD::XOR, VT, N1, N0);
2050 // fold (xor x, 0) -> x
2051 if (N1C && N1C->isNullValue())
2054 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
2057 // fold !(x cc y) -> (x !cc y)
2058 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2059 bool isInt = MVT::isInteger(LHS.getValueType());
2060 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2062 if (N0.getOpcode() == ISD::SETCC)
2063 return DAG.getSetCC(VT, LHS, RHS, NotCC);
2064 if (N0.getOpcode() == ISD::SELECT_CC)
2065 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
2066 assert(0 && "Unhandled SetCC Equivalent!");
2069 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2070 if (N1C && N1C->getValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2071 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2072 SDOperand V = N0.getOperand(0);
2073 V = DAG.getNode(ISD::XOR, V.getValueType(), V,
2074 DAG.getConstant(1, V.getValueType()));
2075 AddToWorkList(V.Val);
2076 return DAG.getNode(ISD::ZERO_EXTEND, VT, V);
2079 // fold !(x or y) -> (!x and !y) iff x or y are setcc
2080 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 &&
2081 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2082 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2083 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2084 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2085 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
2086 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
2087 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
2088 return DAG.getNode(NewOpcode, VT, LHS, RHS);
2091 // fold !(x or y) -> (!x and !y) iff x or y are constants
2092 if (N1C && N1C->isAllOnesValue() &&
2093 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2094 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2095 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2096 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2097 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
2098 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
2099 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
2100 return DAG.getNode(NewOpcode, VT, LHS, RHS);
2103 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
2104 if (N1C && N0.getOpcode() == ISD::XOR) {
2105 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2106 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2108 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
2109 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
2111 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
2112 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
2114 // fold (xor x, x) -> 0
2116 if (!MVT::isVector(VT)) {
2117 return DAG.getConstant(0, VT);
2118 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
2119 // Produce a vector of zeros.
2120 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT));
2121 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
2122 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
2126 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2127 if (N0.getOpcode() == N1.getOpcode()) {
2128 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2129 if (Tmp.Val) return Tmp;
2132 // Simplify the expression using non-local knowledge.
2133 if (!MVT::isVector(VT) &&
2134 SimplifyDemandedBits(SDOperand(N, 0)))
2135 return SDOperand(N, 0);
2140 /// visitShiftByConstant - Handle transforms common to the three shifts, when
2141 /// the shift amount is a constant.
2142 SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
2143 SDNode *LHS = N->getOperand(0).Val;
2144 if (!LHS->hasOneUse()) return SDOperand();
2146 // We want to pull some binops through shifts, so that we have (and (shift))
2147 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
2148 // thing happens with address calculations, so it's important to canonicalize
2150 bool HighBitSet = false; // Can we transform this if the high bit is set?
2152 switch (LHS->getOpcode()) {
2153 default: return SDOperand();
2156 HighBitSet = false; // We can only transform sra if the high bit is clear.
2159 HighBitSet = true; // We can only transform sra if the high bit is set.
2162 if (N->getOpcode() != ISD::SHL)
2163 return SDOperand(); // only shl(add) not sr[al](add).
2164 HighBitSet = false; // We can only transform sra if the high bit is clear.
2168 // We require the RHS of the binop to be a constant as well.
2169 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
2170 if (!BinOpCst) return SDOperand();
2173 // FIXME: disable this for unless the input to the binop is a shift by a
2174 // constant. If it is not a shift, it pessimizes some common cases like:
2176 //void foo(int *X, int i) { X[i & 1235] = 1; }
2177 //int bar(int *X, int i) { return X[i & 255]; }
2178 SDNode *BinOpLHSVal = LHS->getOperand(0).Val;
2179 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
2180 BinOpLHSVal->getOpcode() != ISD::SRA &&
2181 BinOpLHSVal->getOpcode() != ISD::SRL) ||
2182 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
2185 MVT::ValueType VT = N->getValueType(0);
2187 // If this is a signed shift right, and the high bit is modified
2188 // by the logical operation, do not perform the transformation.
2189 // The highBitSet boolean indicates the value of the high bit of
2190 // the constant which would cause it to be modified for this
2192 if (N->getOpcode() == ISD::SRA) {
2193 uint64_t BinOpRHSSign = BinOpCst->getValue() >> MVT::getSizeInBits(VT)-1;
2194 if ((bool)BinOpRHSSign != HighBitSet)
2198 // Fold the constants, shifting the binop RHS by the shift amount.
2199 SDOperand NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0),
2200 LHS->getOperand(1), N->getOperand(1));
2202 // Create the new shift.
2203 SDOperand NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0),
2206 // Create the new binop.
2207 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS);
2211 SDOperand DAGCombiner::visitSHL(SDNode *N) {
2212 SDOperand N0 = N->getOperand(0);
2213 SDOperand N1 = N->getOperand(1);
2214 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2215 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2216 MVT::ValueType VT = N0.getValueType();
2217 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2219 // fold (shl c1, c2) -> c1<<c2
2221 return DAG.getNode(ISD::SHL, VT, N0, N1);
2222 // fold (shl 0, x) -> 0
2223 if (N0C && N0C->isNullValue())
2225 // fold (shl x, c >= size(x)) -> undef
2226 if (N1C && N1C->getValue() >= OpSizeInBits)
2227 return DAG.getNode(ISD::UNDEF, VT);
2228 // fold (shl x, 0) -> x
2229 if (N1C && N1C->isNullValue())
2231 // if (shl x, c) is known to be zero, return 0
2232 if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
2233 return DAG.getConstant(0, VT);
2234 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2235 return SDOperand(N, 0);
2236 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
2237 if (N1C && N0.getOpcode() == ISD::SHL &&
2238 N0.getOperand(1).getOpcode() == ISD::Constant) {
2239 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2240 uint64_t c2 = N1C->getValue();
2241 if (c1 + c2 > OpSizeInBits)
2242 return DAG.getConstant(0, VT);
2243 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
2244 DAG.getConstant(c1 + c2, N1.getValueType()));
2246 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
2247 // (srl (and x, -1 << c1), c1-c2)
2248 if (N1C && N0.getOpcode() == ISD::SRL &&
2249 N0.getOperand(1).getOpcode() == ISD::Constant) {
2250 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2251 uint64_t c2 = N1C->getValue();
2252 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2253 DAG.getConstant(~0ULL << c1, VT));
2255 return DAG.getNode(ISD::SHL, VT, Mask,
2256 DAG.getConstant(c2-c1, N1.getValueType()));
2258 return DAG.getNode(ISD::SRL, VT, Mask,
2259 DAG.getConstant(c1-c2, N1.getValueType()));
2261 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
2262 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
2263 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2264 DAG.getConstant(~0ULL << N1C->getValue(), VT));
2266 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand();
2269 SDOperand DAGCombiner::visitSRA(SDNode *N) {
2270 SDOperand N0 = N->getOperand(0);
2271 SDOperand N1 = N->getOperand(1);
2272 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2273 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2274 MVT::ValueType VT = N0.getValueType();
2276 // fold (sra c1, c2) -> c1>>c2
2278 return DAG.getNode(ISD::SRA, VT, N0, N1);
2279 // fold (sra 0, x) -> 0
2280 if (N0C && N0C->isNullValue())
2282 // fold (sra -1, x) -> -1
2283 if (N0C && N0C->isAllOnesValue())
2285 // fold (sra x, c >= size(x)) -> undef
2286 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
2287 return DAG.getNode(ISD::UNDEF, VT);
2288 // fold (sra x, 0) -> x
2289 if (N1C && N1C->isNullValue())
2291 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2293 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2294 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
2297 default: EVT = MVT::Other; break;
2298 case 1: EVT = MVT::i1; break;
2299 case 8: EVT = MVT::i8; break;
2300 case 16: EVT = MVT::i16; break;
2301 case 32: EVT = MVT::i32; break;
2303 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
2304 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
2305 DAG.getValueType(EVT));
2308 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
2309 if (N1C && N0.getOpcode() == ISD::SRA) {
2310 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2311 unsigned Sum = N1C->getValue() + C1->getValue();
2312 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
2313 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
2314 DAG.getConstant(Sum, N1C->getValueType(0)));
2318 // Simplify, based on bits shifted out of the LHS.
2319 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2320 return SDOperand(N, 0);
2323 // If the sign bit is known to be zero, switch this to a SRL.
2324 if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
2325 return DAG.getNode(ISD::SRL, VT, N0, N1);
2327 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand();
2330 SDOperand DAGCombiner::visitSRL(SDNode *N) {
2331 SDOperand N0 = N->getOperand(0);
2332 SDOperand N1 = N->getOperand(1);
2333 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2334 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2335 MVT::ValueType VT = N0.getValueType();
2336 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2338 // fold (srl c1, c2) -> c1 >>u c2
2340 return DAG.getNode(ISD::SRL, VT, N0, N1);
2341 // fold (srl 0, x) -> 0
2342 if (N0C && N0C->isNullValue())
2344 // fold (srl x, c >= size(x)) -> undef
2345 if (N1C && N1C->getValue() >= OpSizeInBits)
2346 return DAG.getNode(ISD::UNDEF, VT);
2347 // fold (srl x, 0) -> x
2348 if (N1C && N1C->isNullValue())
2350 // if (srl x, c) is known to be zero, return 0
2351 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
2352 return DAG.getConstant(0, VT);
2354 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
2355 if (N1C && N0.getOpcode() == ISD::SRL &&
2356 N0.getOperand(1).getOpcode() == ISD::Constant) {
2357 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2358 uint64_t c2 = N1C->getValue();
2359 if (c1 + c2 > OpSizeInBits)
2360 return DAG.getConstant(0, VT);
2361 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
2362 DAG.getConstant(c1 + c2, N1.getValueType()));
2365 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
2366 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2367 // Shifting in all undef bits?
2368 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
2369 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
2370 return DAG.getNode(ISD::UNDEF, VT);
2372 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
2373 AddToWorkList(SmallShift.Val);
2374 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
2377 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
2378 // bit, which is unmodified by sra.
2379 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
2380 if (N0.getOpcode() == ISD::SRA)
2381 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
2384 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
2385 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2386 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
2387 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
2388 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
2390 // If any of the input bits are KnownOne, then the input couldn't be all
2391 // zeros, thus the result of the srl will always be zero.
2392 if (KnownOne) return DAG.getConstant(0, VT);
2394 // If all of the bits input the to ctlz node are known to be zero, then
2395 // the result of the ctlz is "32" and the result of the shift is one.
2396 uint64_t UnknownBits = ~KnownZero & Mask;
2397 if (UnknownBits == 0) return DAG.getConstant(1, VT);
2399 // Otherwise, check to see if there is exactly one bit input to the ctlz.
2400 if ((UnknownBits & (UnknownBits-1)) == 0) {
2401 // Okay, we know that only that the single bit specified by UnknownBits
2402 // could be set on input to the CTLZ node. If this bit is set, the SRL
2403 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
2404 // to an SRL,XOR pair, which is likely to simplify more.
2405 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
2406 SDOperand Op = N0.getOperand(0);
2408 Op = DAG.getNode(ISD::SRL, VT, Op,
2409 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
2410 AddToWorkList(Op.Val);
2412 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
2416 // fold operands of srl based on knowledge that the low bits are not
2418 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2419 return SDOperand(N, 0);
2421 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand();
2424 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
2425 SDOperand N0 = N->getOperand(0);
2426 MVT::ValueType VT = N->getValueType(0);
2428 // fold (ctlz c1) -> c2
2429 if (isa<ConstantSDNode>(N0))
2430 return DAG.getNode(ISD::CTLZ, VT, N0);
2434 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
2435 SDOperand N0 = N->getOperand(0);
2436 MVT::ValueType VT = N->getValueType(0);
2438 // fold (cttz c1) -> c2
2439 if (isa<ConstantSDNode>(N0))
2440 return DAG.getNode(ISD::CTTZ, VT, N0);
2444 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
2445 SDOperand N0 = N->getOperand(0);
2446 MVT::ValueType VT = N->getValueType(0);
2448 // fold (ctpop c1) -> c2
2449 if (isa<ConstantSDNode>(N0))
2450 return DAG.getNode(ISD::CTPOP, VT, N0);
2454 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
2455 SDOperand N0 = N->getOperand(0);
2456 SDOperand N1 = N->getOperand(1);
2457 SDOperand N2 = N->getOperand(2);
2458 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2459 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2460 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2461 MVT::ValueType VT = N->getValueType(0);
2462 MVT::ValueType VT0 = N0.getValueType();
2464 // fold select C, X, X -> X
2467 // fold select true, X, Y -> X
2468 if (N0C && !N0C->isNullValue())
2470 // fold select false, X, Y -> Y
2471 if (N0C && N0C->isNullValue())
2473 // fold select C, 1, X -> C | X
2474 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
2475 return DAG.getNode(ISD::OR, VT, N0, N2);
2476 // fold select C, 0, 1 -> ~C
2477 if (MVT::isInteger(VT) && MVT::isInteger(VT0) &&
2478 N1C && N2C && N1C->isNullValue() && N2C->getValue() == 1) {
2479 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0));
2482 AddToWorkList(XORNode.Val);
2483 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0))
2484 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
2485 return DAG.getNode(ISD::TRUNCATE, VT, XORNode);
2487 // fold select C, 0, X -> ~C & X
2488 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
2489 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2490 AddToWorkList(XORNode.Val);
2491 return DAG.getNode(ISD::AND, VT, XORNode, N2);
2493 // fold select C, X, 1 -> ~C | X
2494 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getValue() == 1) {
2495 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2496 AddToWorkList(XORNode.Val);
2497 return DAG.getNode(ISD::OR, VT, XORNode, N1);
2499 // fold select C, X, 0 -> C & X
2500 // FIXME: this should check for C type == X type, not i1?
2501 if (MVT::i1 == VT && N2C && N2C->isNullValue())
2502 return DAG.getNode(ISD::AND, VT, N0, N1);
2503 // fold X ? X : Y --> X ? 1 : Y --> X | Y
2504 if (MVT::i1 == VT && N0 == N1)
2505 return DAG.getNode(ISD::OR, VT, N0, N2);
2506 // fold X ? Y : X --> X ? Y : 0 --> X & Y
2507 if (MVT::i1 == VT && N0 == N2)
2508 return DAG.getNode(ISD::AND, VT, N0, N1);
2510 // If we can fold this based on the true/false value, do so.
2511 if (SimplifySelectOps(N, N1, N2))
2512 return SDOperand(N, 0); // Don't revisit N.
2514 // fold selects based on a setcc into other things, such as min/max/abs
2515 if (N0.getOpcode() == ISD::SETCC)
2517 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
2518 // having to say they don't support SELECT_CC on every type the DAG knows
2519 // about, since there is no way to mark an opcode illegal at all value types
2520 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
2521 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
2522 N1, N2, N0.getOperand(2));
2524 return SimplifySelect(N0, N1, N2);
2528 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
2529 SDOperand N0 = N->getOperand(0);
2530 SDOperand N1 = N->getOperand(1);
2531 SDOperand N2 = N->getOperand(2);
2532 SDOperand N3 = N->getOperand(3);
2533 SDOperand N4 = N->getOperand(4);
2534 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
2536 // fold select_cc lhs, rhs, x, x, cc -> x
2540 // Determine if the condition we're dealing with is constant
2541 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
2542 if (SCC.Val) AddToWorkList(SCC.Val);
2544 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
2545 if (SCCC->getValue())
2546 return N2; // cond always true -> true val
2548 return N3; // cond always false -> false val
2551 // Fold to a simpler select_cc
2552 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
2553 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
2554 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
2557 // If we can fold this based on the true/false value, do so.
2558 if (SimplifySelectOps(N, N2, N3))
2559 return SDOperand(N, 0); // Don't revisit N.
2561 // fold select_cc into other things, such as min/max/abs
2562 return SimplifySelectCC(N0, N1, N2, N3, CC);
2565 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
2566 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
2567 cast<CondCodeSDNode>(N->getOperand(2))->get());
2570 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
2571 // "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))"
2572 // transformation. Returns true if extension are possible and the above
2573 // mentioned transformation is profitable.
2574 static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0,
2576 SmallVector<SDNode*, 4> &ExtendNodes,
2577 TargetLowering &TLI) {
2578 bool HasCopyToRegUses = false;
2579 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
2580 for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end();
2585 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
2586 if (User->getOpcode() == ISD::SETCC) {
2587 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
2588 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
2589 // Sign bits will be lost after a zext.
2592 for (unsigned i = 0; i != 2; ++i) {
2593 SDOperand UseOp = User->getOperand(i);
2596 if (!isa<ConstantSDNode>(UseOp))
2601 ExtendNodes.push_back(User);
2603 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2604 SDOperand UseOp = User->getOperand(i);
2606 // If truncate from extended type to original load type is free
2607 // on this target, then it's ok to extend a CopyToReg.
2608 if (isTruncFree && User->getOpcode() == ISD::CopyToReg)
2609 HasCopyToRegUses = true;
2617 if (HasCopyToRegUses) {
2618 bool BothLiveOut = false;
2619 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
2622 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2623 SDOperand UseOp = User->getOperand(i);
2624 if (UseOp.Val == N && UseOp.ResNo == 0) {
2631 // Both unextended and extended values are live out. There had better be
2632 // good a reason for the transformation.
2633 return ExtendNodes.size();
2638 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
2639 SDOperand N0 = N->getOperand(0);
2640 MVT::ValueType VT = N->getValueType(0);
2642 // fold (sext c1) -> c1
2643 if (isa<ConstantSDNode>(N0))
2644 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
2646 // fold (sext (sext x)) -> (sext x)
2647 // fold (sext (aext x)) -> (sext x)
2648 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2649 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
2651 // fold (sext (truncate (load x))) -> (sext (smaller load x))
2652 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
2653 if (N0.getOpcode() == ISD::TRUNCATE) {
2654 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2655 if (NarrowLoad.Val) {
2656 if (NarrowLoad.Val != N0.Val)
2657 CombineTo(N0.Val, NarrowLoad);
2658 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad);
2662 // See if the value being truncated is already sign extended. If so, just
2663 // eliminate the trunc/sext pair.
2664 if (N0.getOpcode() == ISD::TRUNCATE) {
2665 SDOperand Op = N0.getOperand(0);
2666 unsigned OpBits = MVT::getSizeInBits(Op.getValueType());
2667 unsigned MidBits = MVT::getSizeInBits(N0.getValueType());
2668 unsigned DestBits = MVT::getSizeInBits(VT);
2669 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
2671 if (OpBits == DestBits) {
2672 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
2673 // bits, it is already ready.
2674 if (NumSignBits > DestBits-MidBits)
2676 } else if (OpBits < DestBits) {
2677 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
2678 // bits, just sext from i32.
2679 if (NumSignBits > OpBits-MidBits)
2680 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op);
2682 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
2683 // bits, just truncate to i32.
2684 if (NumSignBits > OpBits-MidBits)
2685 return DAG.getNode(ISD::TRUNCATE, VT, Op);
2688 // fold (sext (truncate x)) -> (sextinreg x).
2689 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
2690 N0.getValueType())) {
2691 if (Op.getValueType() < VT)
2692 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2693 else if (Op.getValueType() > VT)
2694 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2695 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
2696 DAG.getValueType(N0.getValueType()));
2700 // fold (sext (load x)) -> (sext (truncate (sextload x)))
2701 if (ISD::isNON_EXTLoad(N0.Val) &&
2702 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
2703 bool DoXform = true;
2704 SmallVector<SDNode*, 4> SetCCs;
2705 if (!N0.hasOneUse())
2706 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
2708 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2709 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2710 LN0->getBasePtr(), LN0->getSrcValue(),
2711 LN0->getSrcValueOffset(),
2714 LN0->getAlignment());
2715 CombineTo(N, ExtLoad);
2716 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
2717 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
2718 // Extend SetCC uses if necessary.
2719 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
2720 SDNode *SetCC = SetCCs[i];
2721 SmallVector<SDOperand, 4> Ops;
2722 for (unsigned j = 0; j != 2; ++j) {
2723 SDOperand SOp = SetCC->getOperand(j);
2725 Ops.push_back(ExtLoad);
2727 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp));
2729 Ops.push_back(SetCC->getOperand(2));
2730 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0),
2731 &Ops[0], Ops.size()));
2733 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2737 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
2738 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
2739 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2740 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2741 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2742 MVT::ValueType EVT = LN0->getLoadedVT();
2743 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
2744 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2745 LN0->getBasePtr(), LN0->getSrcValue(),
2746 LN0->getSrcValueOffset(), EVT,
2748 LN0->getAlignment());
2749 CombineTo(N, ExtLoad);
2750 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2751 ExtLoad.getValue(1));
2752 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2756 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc
2757 if (N0.getOpcode() == ISD::SETCC) {
2759 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2760 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
2761 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2762 if (SCC.Val) return SCC;
2768 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
2769 SDOperand N0 = N->getOperand(0);
2770 MVT::ValueType VT = N->getValueType(0);
2772 // fold (zext c1) -> c1
2773 if (isa<ConstantSDNode>(N0))
2774 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2775 // fold (zext (zext x)) -> (zext x)
2776 // fold (zext (aext x)) -> (zext x)
2777 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2778 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
2780 // fold (zext (truncate (load x))) -> (zext (smaller load x))
2781 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
2782 if (N0.getOpcode() == ISD::TRUNCATE) {
2783 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2784 if (NarrowLoad.Val) {
2785 if (NarrowLoad.Val != N0.Val)
2786 CombineTo(N0.Val, NarrowLoad);
2787 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad);
2791 // fold (zext (truncate x)) -> (and x, mask)
2792 if (N0.getOpcode() == ISD::TRUNCATE &&
2793 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
2794 SDOperand Op = N0.getOperand(0);
2795 if (Op.getValueType() < VT) {
2796 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2797 } else if (Op.getValueType() > VT) {
2798 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2800 return DAG.getZeroExtendInReg(Op, N0.getValueType());
2803 // fold (zext (and (trunc x), cst)) -> (and x, cst).
2804 if (N0.getOpcode() == ISD::AND &&
2805 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2806 N0.getOperand(1).getOpcode() == ISD::Constant) {
2807 SDOperand X = N0.getOperand(0).getOperand(0);
2808 if (X.getValueType() < VT) {
2809 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2810 } else if (X.getValueType() > VT) {
2811 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2813 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2814 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2817 // fold (zext (load x)) -> (zext (truncate (zextload x)))
2818 if (ISD::isNON_EXTLoad(N0.Val) &&
2819 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
2820 bool DoXform = true;
2821 SmallVector<SDNode*, 4> SetCCs;
2822 if (!N0.hasOneUse())
2823 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
2825 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2826 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2827 LN0->getBasePtr(), LN0->getSrcValue(),
2828 LN0->getSrcValueOffset(),
2831 LN0->getAlignment());
2832 CombineTo(N, ExtLoad);
2833 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
2834 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
2835 // Extend SetCC uses if necessary.
2836 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
2837 SDNode *SetCC = SetCCs[i];
2838 SmallVector<SDOperand, 4> Ops;
2839 for (unsigned j = 0; j != 2; ++j) {
2840 SDOperand SOp = SetCC->getOperand(j);
2842 Ops.push_back(ExtLoad);
2844 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp));
2846 Ops.push_back(SetCC->getOperand(2));
2847 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0),
2848 &Ops[0], Ops.size()));
2850 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2854 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
2855 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
2856 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2857 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2858 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2859 MVT::ValueType EVT = LN0->getLoadedVT();
2860 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2861 LN0->getBasePtr(), LN0->getSrcValue(),
2862 LN0->getSrcValueOffset(), EVT,
2864 LN0->getAlignment());
2865 CombineTo(N, ExtLoad);
2866 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2867 ExtLoad.getValue(1));
2868 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2871 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2872 if (N0.getOpcode() == ISD::SETCC) {
2874 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2875 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2876 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2877 if (SCC.Val) return SCC;
2883 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
2884 SDOperand N0 = N->getOperand(0);
2885 MVT::ValueType VT = N->getValueType(0);
2887 // fold (aext c1) -> c1
2888 if (isa<ConstantSDNode>(N0))
2889 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
2890 // fold (aext (aext x)) -> (aext x)
2891 // fold (aext (zext x)) -> (zext x)
2892 // fold (aext (sext x)) -> (sext x)
2893 if (N0.getOpcode() == ISD::ANY_EXTEND ||
2894 N0.getOpcode() == ISD::ZERO_EXTEND ||
2895 N0.getOpcode() == ISD::SIGN_EXTEND)
2896 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2898 // fold (aext (truncate (load x))) -> (aext (smaller load x))
2899 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
2900 if (N0.getOpcode() == ISD::TRUNCATE) {
2901 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2902 if (NarrowLoad.Val) {
2903 if (NarrowLoad.Val != N0.Val)
2904 CombineTo(N0.Val, NarrowLoad);
2905 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad);
2909 // fold (aext (truncate x))
2910 if (N0.getOpcode() == ISD::TRUNCATE) {
2911 SDOperand TruncOp = N0.getOperand(0);
2912 if (TruncOp.getValueType() == VT)
2913 return TruncOp; // x iff x size == zext size.
2914 if (TruncOp.getValueType() > VT)
2915 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
2916 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
2919 // fold (aext (and (trunc x), cst)) -> (and x, cst).
2920 if (N0.getOpcode() == ISD::AND &&
2921 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2922 N0.getOperand(1).getOpcode() == ISD::Constant) {
2923 SDOperand X = N0.getOperand(0).getOperand(0);
2924 if (X.getValueType() < VT) {
2925 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2926 } else if (X.getValueType() > VT) {
2927 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2929 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2930 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2933 // fold (aext (load x)) -> (aext (truncate (extload x)))
2934 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2935 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2936 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2937 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2938 LN0->getBasePtr(), LN0->getSrcValue(),
2939 LN0->getSrcValueOffset(),
2942 LN0->getAlignment());
2943 CombineTo(N, ExtLoad);
2944 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2945 ExtLoad.getValue(1));
2946 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2949 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2950 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2951 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2952 if (N0.getOpcode() == ISD::LOAD &&
2953 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
2955 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2956 MVT::ValueType EVT = LN0->getLoadedVT();
2957 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2958 LN0->getChain(), LN0->getBasePtr(),
2960 LN0->getSrcValueOffset(), EVT,
2962 LN0->getAlignment());
2963 CombineTo(N, ExtLoad);
2964 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2965 ExtLoad.getValue(1));
2966 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2969 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2970 if (N0.getOpcode() == ISD::SETCC) {
2972 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2973 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2974 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2982 /// GetDemandedBits - See if the specified operand can be simplified with the
2983 /// knowledge that only the bits specified by Mask are used. If so, return the
2984 /// simpler operand, otherwise return a null SDOperand.
2985 SDOperand DAGCombiner::GetDemandedBits(SDOperand V, uint64_t Mask) {
2986 switch (V.getOpcode()) {
2990 // If the LHS or RHS don't contribute bits to the or, drop them.
2991 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
2992 return V.getOperand(1);
2993 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
2994 return V.getOperand(0);
2997 // Only look at single-use SRLs.
2998 if (!V.Val->hasOneUse())
3000 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
3001 // See if we can recursively simplify the LHS.
3002 unsigned Amt = RHSC->getValue();
3003 Mask = (Mask << Amt) & MVT::getIntVTBitMask(V.getValueType());
3004 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), Mask);
3005 if (SimplifyLHS.Val) {
3006 return DAG.getNode(ISD::SRL, V.getValueType(),
3007 SimplifyLHS, V.getOperand(1));
3014 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
3015 /// bits and then truncated to a narrower type and where N is a multiple
3016 /// of number of bits of the narrower type, transform it to a narrower load
3017 /// from address + N / num of bits of new type. If the result is to be
3018 /// extended, also fold the extension to form a extending load.
3019 SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
3020 unsigned Opc = N->getOpcode();
3021 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
3022 SDOperand N0 = N->getOperand(0);
3023 MVT::ValueType VT = N->getValueType(0);
3024 MVT::ValueType EVT = N->getValueType(0);
3026 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
3028 if (Opc == ISD::SIGN_EXTEND_INREG) {
3029 ExtType = ISD::SEXTLOAD;
3030 EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3031 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))
3035 unsigned EVTBits = MVT::getSizeInBits(EVT);
3037 bool CombineSRL = false;
3038 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
3039 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3040 ShAmt = N01->getValue();
3041 // Is the shift amount a multiple of size of VT?
3042 if ((ShAmt & (EVTBits-1)) == 0) {
3043 N0 = N0.getOperand(0);
3044 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits)
3051 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
3052 // Do not allow folding to i1 here. i1 is implicitly stored in memory in
3053 // zero extended form: by shrinking the load, we lose track of the fact
3054 // that it is already zero extended.
3055 // FIXME: This should be reevaluated.
3057 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits &&
3058 "Cannot truncate to larger type!");
3059 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3060 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
3061 // For big endian targets, we need to adjust the offset to the pointer to
3062 // load the correct bytes.
3063 if (!TLI.isLittleEndian()) {
3064 unsigned LVTStoreBits = MVT::getStoreSizeInBits(N0.getValueType());
3065 unsigned EVTStoreBits = MVT::getStoreSizeInBits(EVT);
3066 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
3068 uint64_t PtrOff = ShAmt / 8;
3069 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
3070 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
3071 DAG.getConstant(PtrOff, PtrType));
3072 AddToWorkList(NewPtr.Val);
3073 SDOperand Load = (ExtType == ISD::NON_EXTLOAD)
3074 ? DAG.getLoad(VT, LN0->getChain(), NewPtr,
3075 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3076 LN0->isVolatile(), NewAlign)
3077 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr,
3078 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
3079 LN0->isVolatile(), NewAlign);
3082 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
3083 CombineTo(N->getOperand(0).Val, Load);
3085 CombineTo(N0.Val, Load, Load.getValue(1));
3087 if (Opc == ISD::SIGN_EXTEND_INREG)
3088 return DAG.getNode(Opc, VT, Load, N->getOperand(1));
3090 return DAG.getNode(Opc, VT, Load);
3092 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3099 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
3100 SDOperand N0 = N->getOperand(0);
3101 SDOperand N1 = N->getOperand(1);
3102 MVT::ValueType VT = N->getValueType(0);
3103 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
3104 unsigned EVTBits = MVT::getSizeInBits(EVT);
3106 // fold (sext_in_reg c1) -> c1
3107 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
3108 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
3110 // If the input is already sign extended, just drop the extension.
3111 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
3114 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
3115 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3116 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
3117 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
3120 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
3121 if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
3122 return DAG.getZeroExtendInReg(N0, EVT);
3124 // fold operands of sext_in_reg based on knowledge that the top bits are not
3126 if (SimplifyDemandedBits(SDOperand(N, 0)))
3127 return SDOperand(N, 0);
3129 // fold (sext_in_reg (load x)) -> (smaller sextload x)
3130 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
3131 SDOperand NarrowLoad = ReduceLoadWidth(N);
3135 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
3136 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
3137 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
3138 if (N0.getOpcode() == ISD::SRL) {
3139 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
3140 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
3141 // We can turn this into an SRA iff the input to the SRL is already sign
3143 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
3144 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
3145 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
3149 // fold (sext_inreg (extload x)) -> (sextload x)
3150 if (ISD::isEXTLoad(N0.Val) &&
3151 ISD::isUNINDEXEDLoad(N0.Val) &&
3152 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
3153 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
3154 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3155 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
3156 LN0->getBasePtr(), LN0->getSrcValue(),
3157 LN0->getSrcValueOffset(), EVT,
3159 LN0->getAlignment());
3160 CombineTo(N, ExtLoad);
3161 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
3162 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3164 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
3165 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
3167 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
3168 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
3169 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3170 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
3171 LN0->getBasePtr(), LN0->getSrcValue(),
3172 LN0->getSrcValueOffset(), EVT,
3174 LN0->getAlignment());
3175 CombineTo(N, ExtLoad);
3176 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
3177 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3182 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
3183 SDOperand N0 = N->getOperand(0);
3184 MVT::ValueType VT = N->getValueType(0);
3187 if (N0.getValueType() == N->getValueType(0))
3189 // fold (truncate c1) -> c1
3190 if (isa<ConstantSDNode>(N0))
3191 return DAG.getNode(ISD::TRUNCATE, VT, N0);
3192 // fold (truncate (truncate x)) -> (truncate x)
3193 if (N0.getOpcode() == ISD::TRUNCATE)
3194 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
3195 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
3196 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
3197 N0.getOpcode() == ISD::ANY_EXTEND) {
3198 if (N0.getOperand(0).getValueType() < VT)
3199 // if the source is smaller than the dest, we still need an extend
3200 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
3201 else if (N0.getOperand(0).getValueType() > VT)
3202 // if the source is larger than the dest, than we just need the truncate
3203 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
3205 // if the source and dest are the same type, we can drop both the extend
3207 return N0.getOperand(0);
3210 // See if we can simplify the input to this truncate through knowledge that
3211 // only the low bits are being used. For example "trunc (or (shl x, 8), y)"
3213 SDOperand Shorter = GetDemandedBits(N0, MVT::getIntVTBitMask(VT));
3215 return DAG.getNode(ISD::TRUNCATE, VT, Shorter);
3217 // fold (truncate (load x)) -> (smaller load x)
3218 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
3219 return ReduceLoadWidth(N);
3222 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
3223 SDOperand N0 = N->getOperand(0);
3224 MVT::ValueType VT = N->getValueType(0);
3226 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
3227 // Only do this before legalize, since afterward the target may be depending
3228 // on the bitconvert.
3229 // First check to see if this is all constant.
3230 if (!AfterLegalize &&
3231 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() &&
3232 MVT::isVector(VT)) {
3233 bool isSimple = true;
3234 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
3235 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
3236 N0.getOperand(i).getOpcode() != ISD::Constant &&
3237 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
3242 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0));
3243 assert(!MVT::isVector(DestEltVT) &&
3244 "Element type of vector ValueType must not be vector!");
3246 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT);
3250 // If the input is a constant, let getNode() fold it.
3251 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
3252 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
3253 if (Res.Val != N) return Res;
3256 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
3257 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
3259 // fold (conv (load x)) -> (load (conv*)x)
3260 // If the resultant load doesn't need a higher alignment than the original!
3261 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() &&
3262 TLI.isOperationLegal(ISD::LOAD, VT)) {
3263 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3264 unsigned Align = TLI.getTargetMachine().getTargetData()->
3265 getABITypeAlignment(MVT::getTypeForValueType(VT));
3266 unsigned OrigAlign = LN0->getAlignment();
3267 if (Align <= OrigAlign) {
3268 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
3269 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3270 LN0->isVolatile(), Align);
3272 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
3281 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
3282 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
3283 /// destination element value type.
3284 SDOperand DAGCombiner::
3285 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
3286 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
3288 // If this is already the right type, we're done.
3289 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
3291 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
3292 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
3294 // If this is a conversion of N elements of one type to N elements of another
3295 // type, convert each element. This handles FP<->INT cases.
3296 if (SrcBitSize == DstBitSize) {
3297 SmallVector<SDOperand, 8> Ops;
3298 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3299 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
3300 AddToWorkList(Ops.back().Val);
3303 MVT::getVectorType(DstEltVT,
3304 MVT::getVectorNumElements(BV->getValueType(0)));
3305 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3308 // Otherwise, we're growing or shrinking the elements. To avoid having to
3309 // handle annoying details of growing/shrinking FP values, we convert them to
3311 if (MVT::isFloatingPoint(SrcEltVT)) {
3312 // Convert the input float vector to a int vector where the elements are the
3314 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
3315 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
3316 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val;
3320 // Now we know the input is an integer vector. If the output is a FP type,
3321 // convert to integer first, then to FP of the right size.
3322 if (MVT::isFloatingPoint(DstEltVT)) {
3323 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
3324 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
3325 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val;
3327 // Next, convert to FP elements of the same size.
3328 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
3331 // Okay, we know the src/dst types are both integers of differing types.
3332 // Handling growing first.
3333 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
3334 if (SrcBitSize < DstBitSize) {
3335 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
3337 SmallVector<SDOperand, 8> Ops;
3338 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
3339 i += NumInputsPerOutput) {
3340 bool isLE = TLI.isLittleEndian();
3341 uint64_t NewBits = 0;
3342 bool EltIsUndef = true;
3343 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
3344 // Shift the previously computed bits over.
3345 NewBits <<= SrcBitSize;
3346 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
3347 if (Op.getOpcode() == ISD::UNDEF) continue;
3350 NewBits |= cast<ConstantSDNode>(Op)->getValue();
3354 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3356 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
3359 MVT::ValueType VT = MVT::getVectorType(DstEltVT,
3361 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3364 // Finally, this must be the case where we are shrinking elements: each input
3365 // turns into multiple outputs.
3366 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
3367 SmallVector<SDOperand, 8> Ops;
3368 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3369 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
3370 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
3371 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3374 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
3376 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
3377 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
3378 OpVal >>= DstBitSize;
3379 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
3382 // For big endian targets, swap the order of the pieces of each element.
3383 if (!TLI.isLittleEndian())
3384 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
3386 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size());
3387 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3392 SDOperand DAGCombiner::visitFADD(SDNode *N) {
3393 SDOperand N0 = N->getOperand(0);
3394 SDOperand N1 = N->getOperand(1);
3395 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3396 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3397 MVT::ValueType VT = N->getValueType(0);
3400 if (MVT::isVector(VT)) {
3401 SDOperand FoldedVOp = SimplifyVBinOp(N);
3402 if (FoldedVOp.Val) return FoldedVOp;
3405 // fold (fadd c1, c2) -> c1+c2
3406 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3407 return DAG.getNode(ISD::FADD, VT, N0, N1);
3408 // canonicalize constant to RHS
3409 if (N0CFP && !N1CFP)
3410 return DAG.getNode(ISD::FADD, VT, N1, N0);
3411 // fold (A + (-B)) -> A-B
3412 if (isNegatibleForFree(N1) == 2)
3413 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG));
3414 // fold ((-A) + B) -> B-A
3415 if (isNegatibleForFree(N0) == 2)
3416 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG));
3418 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
3419 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
3420 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3421 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
3422 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1));
3427 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
3428 SDOperand N0 = N->getOperand(0);
3429 SDOperand N1 = N->getOperand(1);
3430 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3431 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3432 MVT::ValueType VT = N->getValueType(0);
3435 if (MVT::isVector(VT)) {
3436 SDOperand FoldedVOp = SimplifyVBinOp(N);
3437 if (FoldedVOp.Val) return FoldedVOp;
3440 // fold (fsub c1, c2) -> c1-c2
3441 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3442 return DAG.getNode(ISD::FSUB, VT, N0, N1);
3444 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
3445 if (isNegatibleForFree(N1))
3446 return GetNegatedExpression(N1, DAG);
3447 return DAG.getNode(ISD::FNEG, VT, N1);
3449 // fold (A-(-B)) -> A+B
3450 if (isNegatibleForFree(N1))
3451 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG));
3456 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
3457 SDOperand N0 = N->getOperand(0);
3458 SDOperand N1 = N->getOperand(1);
3459 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3460 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3461 MVT::ValueType VT = N->getValueType(0);
3464 if (MVT::isVector(VT)) {
3465 SDOperand FoldedVOp = SimplifyVBinOp(N);
3466 if (FoldedVOp.Val) return FoldedVOp;
3469 // fold (fmul c1, c2) -> c1*c2
3470 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3471 return DAG.getNode(ISD::FMUL, VT, N0, N1);
3472 // canonicalize constant to RHS
3473 if (N0CFP && !N1CFP)
3474 return DAG.getNode(ISD::FMUL, VT, N1, N0);
3475 // fold (fmul X, 2.0) -> (fadd X, X)
3476 if (N1CFP && N1CFP->isExactlyValue(+2.0))
3477 return DAG.getNode(ISD::FADD, VT, N0, N0);
3478 // fold (fmul X, -1.0) -> (fneg X)
3479 if (N1CFP && N1CFP->isExactlyValue(-1.0))
3480 return DAG.getNode(ISD::FNEG, VT, N0);
3483 if (char LHSNeg = isNegatibleForFree(N0)) {
3484 if (char RHSNeg = isNegatibleForFree(N1)) {
3485 // Both can be negated for free, check to see if at least one is cheaper
3487 if (LHSNeg == 2 || RHSNeg == 2)
3488 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG),
3489 GetNegatedExpression(N1, DAG));
3493 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
3494 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
3495 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3496 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
3497 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1));
3502 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
3503 SDOperand N0 = N->getOperand(0);
3504 SDOperand N1 = N->getOperand(1);
3505 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3506 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3507 MVT::ValueType VT = N->getValueType(0);
3510 if (MVT::isVector(VT)) {
3511 SDOperand FoldedVOp = SimplifyVBinOp(N);
3512 if (FoldedVOp.Val) return FoldedVOp;
3515 // fold (fdiv c1, c2) -> c1/c2
3516 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3517 return DAG.getNode(ISD::FDIV, VT, N0, N1);
3521 if (char LHSNeg = isNegatibleForFree(N0)) {
3522 if (char RHSNeg = isNegatibleForFree(N1)) {
3523 // Both can be negated for free, check to see if at least one is cheaper
3525 if (LHSNeg == 2 || RHSNeg == 2)
3526 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG),
3527 GetNegatedExpression(N1, DAG));
3534 SDOperand DAGCombiner::visitFREM(SDNode *N) {
3535 SDOperand N0 = N->getOperand(0);
3536 SDOperand N1 = N->getOperand(1);
3537 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3538 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3539 MVT::ValueType VT = N->getValueType(0);
3541 // fold (frem c1, c2) -> fmod(c1,c2)
3542 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3543 return DAG.getNode(ISD::FREM, VT, N0, N1);
3548 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
3549 SDOperand N0 = N->getOperand(0);
3550 SDOperand N1 = N->getOperand(1);
3551 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3552 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3553 MVT::ValueType VT = N->getValueType(0);
3555 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
3556 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
3559 const APFloat& V = N1CFP->getValueAPF();
3560 // copysign(x, c1) -> fabs(x) iff ispos(c1)
3561 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
3562 if (!V.isNegative())
3563 return DAG.getNode(ISD::FABS, VT, N0);
3565 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
3568 // copysign(fabs(x), y) -> copysign(x, y)
3569 // copysign(fneg(x), y) -> copysign(x, y)
3570 // copysign(copysign(x,z), y) -> copysign(x, y)
3571 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
3572 N0.getOpcode() == ISD::FCOPYSIGN)
3573 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
3575 // copysign(x, abs(y)) -> abs(x)
3576 if (N1.getOpcode() == ISD::FABS)
3577 return DAG.getNode(ISD::FABS, VT, N0);
3579 // copysign(x, copysign(y,z)) -> copysign(x, z)
3580 if (N1.getOpcode() == ISD::FCOPYSIGN)
3581 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
3583 // copysign(x, fp_extend(y)) -> copysign(x, y)
3584 // copysign(x, fp_round(y)) -> copysign(x, y)
3585 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
3586 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
3593 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
3594 SDOperand N0 = N->getOperand(0);
3595 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3596 MVT::ValueType VT = N->getValueType(0);
3598 // fold (sint_to_fp c1) -> c1fp
3599 if (N0C && N0.getValueType() != MVT::ppcf128)
3600 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
3604 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
3605 SDOperand N0 = N->getOperand(0);
3606 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3607 MVT::ValueType VT = N->getValueType(0);
3609 // fold (uint_to_fp c1) -> c1fp
3610 if (N0C && N0.getValueType() != MVT::ppcf128)
3611 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
3615 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
3616 SDOperand N0 = N->getOperand(0);
3617 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3618 MVT::ValueType VT = N->getValueType(0);
3620 // fold (fp_to_sint c1fp) -> c1
3622 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
3626 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
3627 SDOperand N0 = N->getOperand(0);
3628 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3629 MVT::ValueType VT = N->getValueType(0);
3631 // fold (fp_to_uint c1fp) -> c1
3632 if (N0CFP && VT != MVT::ppcf128)
3633 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
3637 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
3638 SDOperand N0 = N->getOperand(0);
3639 SDOperand N1 = N->getOperand(1);
3640 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3641 MVT::ValueType VT = N->getValueType(0);
3643 // fold (fp_round c1fp) -> c1fp
3644 if (N0CFP && N0.getValueType() != MVT::ppcf128)
3645 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1);
3647 // fold (fp_round (fp_extend x)) -> x
3648 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
3649 return N0.getOperand(0);
3651 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
3652 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
3653 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1);
3654 AddToWorkList(Tmp.Val);
3655 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
3661 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
3662 SDOperand N0 = N->getOperand(0);
3663 MVT::ValueType VT = N->getValueType(0);
3664 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3665 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3667 // fold (fp_round_inreg c1fp) -> c1fp
3669 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT);
3670 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
3675 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
3676 SDOperand N0 = N->getOperand(0);
3677 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3678 MVT::ValueType VT = N->getValueType(0);
3680 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
3681 if (N->hasOneUse() && (*N->use_begin())->getOpcode() == ISD::FP_ROUND)
3684 // fold (fp_extend c1fp) -> c1fp
3685 if (N0CFP && VT != MVT::ppcf128)
3686 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
3688 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
3690 if (N0.getOpcode() == ISD::FP_ROUND && N0.Val->getConstantOperandVal(1) == 1){
3691 SDOperand In = N0.getOperand(0);
3692 if (In.getValueType() == VT) return In;
3693 if (VT < In.getValueType())
3694 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1));
3695 return DAG.getNode(ISD::FP_EXTEND, VT, In);
3698 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
3699 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
3700 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
3701 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3702 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
3703 LN0->getBasePtr(), LN0->getSrcValue(),
3704 LN0->getSrcValueOffset(),
3707 LN0->getAlignment());
3708 CombineTo(N, ExtLoad);
3709 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad,
3710 DAG.getIntPtrConstant(1)),
3711 ExtLoad.getValue(1));
3712 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3719 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
3720 SDOperand N0 = N->getOperand(0);
3722 if (isNegatibleForFree(N0))
3723 return GetNegatedExpression(N0, DAG);
3728 SDOperand DAGCombiner::visitFABS(SDNode *N) {
3729 SDOperand N0 = N->getOperand(0);
3730 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3731 MVT::ValueType VT = N->getValueType(0);
3733 // fold (fabs c1) -> fabs(c1)
3734 if (N0CFP && VT != MVT::ppcf128)
3735 return DAG.getNode(ISD::FABS, VT, N0);
3736 // fold (fabs (fabs x)) -> (fabs x)
3737 if (N0.getOpcode() == ISD::FABS)
3738 return N->getOperand(0);
3739 // fold (fabs (fneg x)) -> (fabs x)
3740 // fold (fabs (fcopysign x, y)) -> (fabs x)
3741 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
3742 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
3747 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
3748 SDOperand Chain = N->getOperand(0);
3749 SDOperand N1 = N->getOperand(1);
3750 SDOperand N2 = N->getOperand(2);
3751 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3753 // never taken branch, fold to chain
3754 if (N1C && N1C->isNullValue())
3756 // unconditional branch
3757 if (N1C && N1C->getValue() == 1)
3758 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
3759 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
3761 if (N1.getOpcode() == ISD::SETCC &&
3762 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
3763 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
3764 N1.getOperand(0), N1.getOperand(1), N2);
3769 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
3771 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
3772 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
3773 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
3775 // Use SimplifySetCC to simplify SETCC's.
3776 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
3777 if (Simp.Val) AddToWorkList(Simp.Val);
3779 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
3781 // fold br_cc true, dest -> br dest (unconditional branch)
3782 if (SCCC && SCCC->getValue())
3783 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
3785 // fold br_cc false, dest -> unconditional fall through
3786 if (SCCC && SCCC->isNullValue())
3787 return N->getOperand(0);
3789 // fold to a simpler setcc
3790 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
3791 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
3792 Simp.getOperand(2), Simp.getOperand(0),
3793 Simp.getOperand(1), N->getOperand(4));
3798 /// CombineToPreIndexedLoadStore - Try turning a load / store and a
3799 /// pre-indexed load / store when the base pointer is a add or subtract
3800 /// and it has other uses besides the load / store. After the
3801 /// transformation, the new indexed load / store has effectively folded
3802 /// the add / subtract in and all of its other uses are redirected to the
3803 /// new load / store.
3804 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
3811 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3812 if (LD->getAddressingMode() != ISD::UNINDEXED)
3814 VT = LD->getLoadedVT();
3815 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
3816 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
3818 Ptr = LD->getBasePtr();
3819 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3820 if (ST->getAddressingMode() != ISD::UNINDEXED)
3822 VT = ST->getStoredVT();
3823 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
3824 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
3826 Ptr = ST->getBasePtr();
3831 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
3832 // out. There is no reason to make this a preinc/predec.
3833 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
3834 Ptr.Val->hasOneUse())
3837 // Ask the target to do addressing mode selection.
3840 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3841 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
3843 // Don't create a indexed load / store with zero offset.
3844 if (isa<ConstantSDNode>(Offset) &&
3845 cast<ConstantSDNode>(Offset)->getValue() == 0)
3848 // Try turning it into a pre-indexed load / store except when:
3849 // 1) The new base ptr is a frame index.
3850 // 2) If N is a store and the new base ptr is either the same as or is a
3851 // predecessor of the value being stored.
3852 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
3853 // that would create a cycle.
3854 // 4) All uses are load / store ops that use it as old base ptr.
3856 // Check #1. Preinc'ing a frame index would require copying the stack pointer
3857 // (plus the implicit offset) to a register to preinc anyway.
3858 if (isa<FrameIndexSDNode>(BasePtr))
3863 SDOperand Val = cast<StoreSDNode>(N)->getValue();
3864 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val))
3868 // Now check for #3 and #4.
3869 bool RealUse = false;
3870 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3871 E = Ptr.Val->use_end(); I != E; ++I) {
3875 if (Use->isPredecessor(N))
3878 if (!((Use->getOpcode() == ISD::LOAD &&
3879 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
3880 (Use->getOpcode() == ISD::STORE) &&
3881 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))
3889 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM);
3891 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
3894 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
3895 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
3897 std::vector<SDNode*> NowDead;
3899 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
3901 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
3904 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
3908 // Nodes can end up on the worklist more than once. Make sure we do
3909 // not process a node that has been replaced.
3910 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3911 removeFromWorkList(NowDead[i]);
3912 // Finally, since the node is now dead, remove it from the graph.
3915 // Replace the uses of Ptr with uses of the updated base value.
3916 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
3918 removeFromWorkList(Ptr.Val);
3919 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3920 removeFromWorkList(NowDead[i]);
3921 DAG.DeleteNode(Ptr.Val);
3926 /// CombineToPostIndexedLoadStore - Try combine a load / store with a
3927 /// add / sub of the base pointer node into a post-indexed load / store.
3928 /// The transformation folded the add / subtract into the new indexed
3929 /// load / store effectively and all of its uses are redirected to the
3930 /// new load / store.
3931 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
3938 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3939 if (LD->getAddressingMode() != ISD::UNINDEXED)
3941 VT = LD->getLoadedVT();
3942 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
3943 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
3945 Ptr = LD->getBasePtr();
3946 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3947 if (ST->getAddressingMode() != ISD::UNINDEXED)
3949 VT = ST->getStoredVT();
3950 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
3951 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
3953 Ptr = ST->getBasePtr();
3958 if (Ptr.Val->hasOneUse())
3961 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3962 E = Ptr.Val->use_end(); I != E; ++I) {
3965 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
3970 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3971 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
3973 std::swap(BasePtr, Offset);
3976 // Don't create a indexed load / store with zero offset.
3977 if (isa<ConstantSDNode>(Offset) &&
3978 cast<ConstantSDNode>(Offset)->getValue() == 0)
3981 // Try turning it into a post-indexed load / store except when
3982 // 1) All uses are load / store ops that use it as base ptr.
3983 // 2) Op must be independent of N, i.e. Op is neither a predecessor
3984 // nor a successor of N. Otherwise, if Op is folded that would
3988 bool TryNext = false;
3989 for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
3990 EE = BasePtr.Val->use_end(); II != EE; ++II) {
3995 // If all the uses are load / store addresses, then don't do the
3997 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
3998 bool RealUse = false;
3999 for (SDNode::use_iterator III = Use->use_begin(),
4000 EEE = Use->use_end(); III != EEE; ++III) {
4001 SDNode *UseUse = *III;
4002 if (!((UseUse->getOpcode() == ISD::LOAD &&
4003 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
4004 (UseUse->getOpcode() == ISD::STORE) &&
4005 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))
4019 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) {
4020 SDOperand Result = isLoad
4021 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
4022 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
4025 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
4026 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
4028 std::vector<SDNode*> NowDead;
4030 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
4032 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
4035 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
4039 // Nodes can end up on the worklist more than once. Make sure we do
4040 // not process a node that has been replaced.
4041 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
4042 removeFromWorkList(NowDead[i]);
4043 // Finally, since the node is now dead, remove it from the graph.
4046 // Replace the uses of Use with uses of the updated base value.
4047 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0),
4048 Result.getValue(isLoad ? 1 : 0),
4050 removeFromWorkList(Op);
4051 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
4052 removeFromWorkList(NowDead[i]);
4063 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
4064 LoadSDNode *LD = cast<LoadSDNode>(N);
4065 SDOperand Chain = LD->getChain();
4066 SDOperand Ptr = LD->getBasePtr();
4068 // If load is not volatile and there are no uses of the loaded value (and
4069 // the updated indexed value in case of indexed loads), change uses of the
4070 // chain value into uses of the chain input (i.e. delete the dead load).
4071 if (!LD->isVolatile()) {
4072 if (N->getValueType(1) == MVT::Other) {
4074 if (N->hasNUsesOfValue(0, 0)) {
4075 // It's not safe to use the two value CombineTo variant here. e.g.
4076 // v1, chain2 = load chain1, loc
4077 // v2, chain3 = load chain2, loc
4079 // Now we replace use of v1 with undef, use of chain2 with chain1.
4080 // ReplaceAllUsesWith() will iterate through uses of the first load and
4082 // v1, chain2 = load chain1, loc
4083 // v2, chain3 = load chain1, loc
4085 // Now the second load is the same as the first load, SelectionDAG cse
4086 // will ensure the use of second load is replaced with the first load.
4087 // v1, chain2 = load chain1, loc
4089 // Then v1 is replaced with undef and bad things happen.
4090 std::vector<SDNode*> NowDead;
4091 SDOperand Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0));
4092 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4093 DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG));
4094 DOUT << " and 1 other value\n";
4095 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Undef, &NowDead);
4096 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Chain, &NowDead);
4097 removeFromWorkList(N);
4098 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
4099 removeFromWorkList(NowDead[i]);
4101 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
4105 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
4106 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
4107 std::vector<SDNode*> NowDead;
4108 SDOperand Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0));
4109 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4110 DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG));
4111 DOUT << " and 2 other values\n";
4112 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Undef, &NowDead);
4113 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1),
4114 DAG.getNode(ISD::UNDEF, N->getValueType(1)),
4116 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 2), Chain, &NowDead);
4117 removeFromWorkList(N);
4118 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
4119 removeFromWorkList(NowDead[i]);
4121 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
4126 // If this load is directly stored, replace the load value with the stored
4128 // TODO: Handle store large -> read small portion.
4129 // TODO: Handle TRUNCSTORE/LOADEXT
4130 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
4131 if (ISD::isNON_TRUNCStore(Chain.Val)) {
4132 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
4133 if (PrevST->getBasePtr() == Ptr &&
4134 PrevST->getValue().getValueType() == N->getValueType(0))
4135 return CombineTo(N, Chain.getOperand(1), Chain);
4140 // Walk up chain skipping non-aliasing memory nodes.
4141 SDOperand BetterChain = FindBetterChain(N, Chain);
4143 // If there is a better chain.
4144 if (Chain != BetterChain) {
4147 // Replace the chain to void dependency.
4148 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
4149 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
4150 LD->getSrcValue(), LD->getSrcValueOffset(),
4151 LD->isVolatile(), LD->getAlignment());
4153 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
4154 LD->getValueType(0),
4155 BetterChain, Ptr, LD->getSrcValue(),
4156 LD->getSrcValueOffset(),
4159 LD->getAlignment());
4162 // Create token factor to keep old chain connected.
4163 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
4164 Chain, ReplLoad.getValue(1));
4166 // Replace uses with load result and token factor. Don't add users
4168 return CombineTo(N, ReplLoad.getValue(0), Token, false);
4172 // Try transforming N to an indexed load.
4173 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4174 return SDOperand(N, 0);
4180 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
4181 StoreSDNode *ST = cast<StoreSDNode>(N);
4182 SDOperand Chain = ST->getChain();
4183 SDOperand Value = ST->getValue();
4184 SDOperand Ptr = ST->getBasePtr();
4186 // If this is a store of a bit convert, store the input value if the
4187 // resultant store does not need a higher alignment than the original.
4188 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
4189 ST->getAddressingMode() == ISD::UNINDEXED) {
4190 unsigned Align = ST->getAlignment();
4191 MVT::ValueType SVT = Value.getOperand(0).getValueType();
4192 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
4193 getABITypeAlignment(MVT::getTypeForValueType(SVT));
4194 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT))
4195 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
4196 ST->getSrcValueOffset(), ST->isVolatile(), Align);
4199 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
4200 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
4201 if (Value.getOpcode() != ISD::TargetConstantFP) {
4203 switch (CFP->getValueType(0)) {
4204 default: assert(0 && "Unknown FP type");
4205 case MVT::f80: // We don't do this for these yet.
4210 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) {
4211 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
4212 convertToAPInt().getZExtValue(), MVT::i32);
4213 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
4214 ST->getSrcValueOffset(), ST->isVolatile(),
4215 ST->getAlignment());
4219 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) {
4220 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
4221 getZExtValue(), MVT::i64);
4222 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
4223 ST->getSrcValueOffset(), ST->isVolatile(),
4224 ST->getAlignment());
4225 } else if (TLI.isTypeLegal(MVT::i32)) {
4226 // Many FP stores are not made apparent until after legalize, e.g. for
4227 // argument passing. Since this is so common, custom legalize the
4228 // 64-bit integer store into two 32-bit stores.
4229 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue();
4230 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
4231 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32);
4232 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
4234 int SVOffset = ST->getSrcValueOffset();
4235 unsigned Alignment = ST->getAlignment();
4236 bool isVolatile = ST->isVolatile();
4238 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(),
4239 ST->getSrcValueOffset(),
4240 isVolatile, ST->getAlignment());
4241 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4242 DAG.getConstant(4, Ptr.getValueType()));
4244 Alignment = MinAlign(Alignment, 4U);
4245 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(),
4246 SVOffset, isVolatile, Alignment);
4247 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1);
4255 // Walk up chain skipping non-aliasing memory nodes.
4256 SDOperand BetterChain = FindBetterChain(N, Chain);
4258 // If there is a better chain.
4259 if (Chain != BetterChain) {
4260 // Replace the chain to avoid dependency.
4261 SDOperand ReplStore;
4262 if (ST->isTruncatingStore()) {
4263 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
4264 ST->getSrcValue(), ST->getSrcValueOffset(), ST->getStoredVT(),
4265 ST->isVolatile(), ST->getAlignment());
4267 ReplStore = DAG.getStore(BetterChain, Value, Ptr,
4268 ST->getSrcValue(), ST->getSrcValueOffset(),
4269 ST->isVolatile(), ST->getAlignment());
4272 // Create token to keep both nodes around.
4274 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
4276 // Don't add users to work list.
4277 return CombineTo(N, Token, false);
4281 // Try transforming N to an indexed store.
4282 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4283 return SDOperand(N, 0);
4285 // FIXME: is there such a thing as a truncating indexed store?
4286 if (ST->isTruncatingStore() && ST->getAddressingMode() == ISD::UNINDEXED &&
4287 MVT::isInteger(Value.getValueType())) {
4288 // See if we can simplify the input to this truncstore with knowledge that
4289 // only the low bits are being used. For example:
4290 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
4292 GetDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT()));
4293 AddToWorkList(Value.Val);
4295 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(),
4296 ST->getSrcValueOffset(), ST->getStoredVT(),
4297 ST->isVolatile(), ST->getAlignment());
4299 // Otherwise, see if we can simplify the operation with
4300 // SimplifyDemandedBits, which only works if the value has a single use.
4301 if (SimplifyDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT())))
4302 return SDOperand(N, 0);
4305 // If this is a load followed by a store to the same location, then the store
4307 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
4308 if (Ld->getBasePtr() == Ptr && ST->getStoredVT() == Ld->getLoadedVT() &&
4309 ST->getAddressingMode() == ISD::UNINDEXED &&
4310 !ST->isVolatile() &&
4311 // There can't be any side effects between the load and store, such as
4313 Chain.reachesChainWithoutSideEffects(SDOperand(Ld, 1))) {
4314 // The store is dead, remove it.
4322 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
4323 SDOperand InVec = N->getOperand(0);
4324 SDOperand InVal = N->getOperand(1);
4325 SDOperand EltNo = N->getOperand(2);
4327 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
4328 // vector with the inserted element.
4329 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
4330 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
4331 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
4332 if (Elt < Ops.size())
4334 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
4335 &Ops[0], Ops.size());
4341 SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
4342 SDOperand InVec = N->getOperand(0);
4343 SDOperand EltNo = N->getOperand(1);
4345 // (vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr)
4346 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr)
4347 if (isa<ConstantSDNode>(EltNo)) {
4348 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
4349 bool NewLoad = false;
4351 MVT::ValueType VT = InVec.getValueType();
4352 MVT::ValueType EVT = MVT::getVectorElementType(VT);
4353 MVT::ValueType LVT = EVT;
4354 unsigned NumElts = MVT::getVectorNumElements(VT);
4355 if (InVec.getOpcode() == ISD::BIT_CONVERT) {
4356 MVT::ValueType BCVT = InVec.getOperand(0).getValueType();
4357 if (!MVT::isVector(BCVT) ||
4358 NumElts != MVT::getVectorNumElements(BCVT))
4360 InVec = InVec.getOperand(0);
4361 EVT = MVT::getVectorElementType(BCVT);
4364 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4365 InVec.getOperand(0).getValueType() == EVT &&
4366 ISD::isNormalLoad(InVec.getOperand(0).Val) &&
4367 InVec.getOperand(0).hasOneUse()) {
4368 LoadSDNode *LN0 = cast<LoadSDNode>(InVec.getOperand(0));
4369 unsigned Align = LN0->getAlignment();
4371 // Check the resultant load doesn't need a higher alignment than the
4373 unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
4374 getABITypeAlignment(MVT::getTypeForValueType(LVT));
4375 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align)
4380 return DAG.getLoad(LVT, LN0->getChain(), LN0->getBasePtr(),
4381 LN0->getSrcValue(), LN0->getSrcValueOffset(),
4382 LN0->isVolatile(), Align);
4390 SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
4391 unsigned NumInScalars = N->getNumOperands();
4392 MVT::ValueType VT = N->getValueType(0);
4393 unsigned NumElts = MVT::getVectorNumElements(VT);
4394 MVT::ValueType EltType = MVT::getVectorElementType(VT);
4396 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
4397 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
4398 // at most two distinct vectors, turn this into a shuffle node.
4399 SDOperand VecIn1, VecIn2;
4400 for (unsigned i = 0; i != NumInScalars; ++i) {
4401 // Ignore undef inputs.
4402 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4404 // If this input is something other than a EXTRACT_VECTOR_ELT with a
4405 // constant index, bail out.
4406 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4407 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
4408 VecIn1 = VecIn2 = SDOperand(0, 0);
4412 // If the input vector type disagrees with the result of the build_vector,
4413 // we can't make a shuffle.
4414 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
4415 if (ExtractedFromVec.getValueType() != VT) {
4416 VecIn1 = VecIn2 = SDOperand(0, 0);
4420 // Otherwise, remember this. We allow up to two distinct input vectors.
4421 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
4424 if (VecIn1.Val == 0) {
4425 VecIn1 = ExtractedFromVec;
4426 } else if (VecIn2.Val == 0) {
4427 VecIn2 = ExtractedFromVec;
4430 VecIn1 = VecIn2 = SDOperand(0, 0);
4435 // If everything is good, we can make a shuffle operation.
4437 SmallVector<SDOperand, 8> BuildVecIndices;
4438 for (unsigned i = 0; i != NumInScalars; ++i) {
4439 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
4440 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy()));
4444 SDOperand Extract = N->getOperand(i);
4446 // If extracting from the first vector, just use the index directly.
4447 if (Extract.getOperand(0) == VecIn1) {
4448 BuildVecIndices.push_back(Extract.getOperand(1));
4452 // Otherwise, use InIdx + VecSize
4453 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
4454 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars));
4457 // Add count and size info.
4458 MVT::ValueType BuildVecVT = MVT::getVectorType(TLI.getPointerTy(), NumElts);
4460 // Return the new VECTOR_SHUFFLE node.
4466 // Use an undef build_vector as input for the second operand.
4467 std::vector<SDOperand> UnOps(NumInScalars,
4468 DAG.getNode(ISD::UNDEF,
4470 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT,
4471 &UnOps[0], UnOps.size());
4472 AddToWorkList(Ops[1].Val);
4474 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT,
4475 &BuildVecIndices[0], BuildVecIndices.size());
4476 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3);
4482 SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
4483 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
4484 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
4485 // inputs come from at most two distinct vectors, turn this into a shuffle
4488 // If we only have one input vector, we don't need to do any concatenation.
4489 if (N->getNumOperands() == 1) {
4490 return N->getOperand(0);
4496 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
4497 SDOperand ShufMask = N->getOperand(2);
4498 unsigned NumElts = ShufMask.getNumOperands();
4500 // If the shuffle mask is an identity operation on the LHS, return the LHS.
4501 bool isIdentity = true;
4502 for (unsigned i = 0; i != NumElts; ++i) {
4503 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4504 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
4509 if (isIdentity) return N->getOperand(0);
4511 // If the shuffle mask is an identity operation on the RHS, return the RHS.
4513 for (unsigned i = 0; i != NumElts; ++i) {
4514 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4515 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
4520 if (isIdentity) return N->getOperand(1);
4522 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
4524 bool isUnary = true;
4525 bool isSplat = true;
4527 unsigned BaseIdx = 0;
4528 for (unsigned i = 0; i != NumElts; ++i)
4529 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
4530 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
4531 int V = (Idx < NumElts) ? 0 : 1;
4545 SDOperand N0 = N->getOperand(0);
4546 SDOperand N1 = N->getOperand(1);
4547 // Normalize unary shuffle so the RHS is undef.
4548 if (isUnary && VecNum == 1)
4551 // If it is a splat, check if the argument vector is a build_vector with
4552 // all scalar elements the same.
4556 // If this is a bit convert that changes the element type of the vector but
4557 // not the number of vector elements, look through it. Be careful not to
4558 // look though conversions that change things like v4f32 to v2f64.
4559 if (V->getOpcode() == ISD::BIT_CONVERT) {
4560 SDOperand ConvInput = V->getOperand(0);
4561 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts)
4565 if (V->getOpcode() == ISD::BUILD_VECTOR) {
4566 unsigned NumElems = V->getNumOperands();
4567 if (NumElems > BaseIdx) {
4569 bool AllSame = true;
4570 for (unsigned i = 0; i != NumElems; ++i) {
4571 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
4572 Base = V->getOperand(i);
4576 // Splat of <u, u, u, u>, return <u, u, u, u>
4579 for (unsigned i = 0; i != NumElems; ++i) {
4580 if (V->getOperand(i) != Base) {
4585 // Splat of <x, x, x, x>, return <x, x, x, x>
4592 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
4594 if (isUnary || N0 == N1) {
4595 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
4597 SmallVector<SDOperand, 8> MappedOps;
4598 for (unsigned i = 0; i != NumElts; ++i) {
4599 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
4600 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
4601 MappedOps.push_back(ShufMask.getOperand(i));
4604 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
4605 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
4608 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
4609 &MappedOps[0], MappedOps.size());
4610 AddToWorkList(ShufMask.Val);
4611 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
4613 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
4620 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
4621 /// an AND to a vector_shuffle with the destination vector and a zero vector.
4622 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
4623 /// vector_shuffle V, Zero, <0, 4, 2, 4>
4624 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
4625 SDOperand LHS = N->getOperand(0);
4626 SDOperand RHS = N->getOperand(1);
4627 if (N->getOpcode() == ISD::AND) {
4628 if (RHS.getOpcode() == ISD::BIT_CONVERT)
4629 RHS = RHS.getOperand(0);
4630 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
4631 std::vector<SDOperand> IdxOps;
4632 unsigned NumOps = RHS.getNumOperands();
4633 unsigned NumElts = NumOps;
4634 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType());
4635 for (unsigned i = 0; i != NumElts; ++i) {
4636 SDOperand Elt = RHS.getOperand(i);
4637 if (!isa<ConstantSDNode>(Elt))
4639 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
4640 IdxOps.push_back(DAG.getConstant(i, EVT));
4641 else if (cast<ConstantSDNode>(Elt)->isNullValue())
4642 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
4647 // Let's see if the target supports this vector_shuffle.
4648 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
4651 // Return the new VECTOR_SHUFFLE node.
4652 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts);
4653 std::vector<SDOperand> Ops;
4654 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS);
4656 AddToWorkList(LHS.Val);
4657 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
4658 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
4659 &ZeroOps[0], ZeroOps.size()));
4660 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
4661 &IdxOps[0], IdxOps.size()));
4662 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT,
4663 &Ops[0], Ops.size());
4664 if (VT != LHS.getValueType()) {
4665 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result);
4673 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
4674 SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) {
4675 // After legalize, the target may be depending on adds and other
4676 // binary ops to provide legal ways to construct constants or other
4677 // things. Simplifying them may result in a loss of legality.
4678 if (AfterLegalize) return SDOperand();
4680 MVT::ValueType VT = N->getValueType(0);
4681 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!");
4683 MVT::ValueType EltType = MVT::getVectorElementType(VT);
4684 SDOperand LHS = N->getOperand(0);
4685 SDOperand RHS = N->getOperand(1);
4686 SDOperand Shuffle = XformToShuffleWithZero(N);
4687 if (Shuffle.Val) return Shuffle;
4689 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
4691 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
4692 RHS.getOpcode() == ISD::BUILD_VECTOR) {
4693 SmallVector<SDOperand, 8> Ops;
4694 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
4695 SDOperand LHSOp = LHS.getOperand(i);
4696 SDOperand RHSOp = RHS.getOperand(i);
4697 // If these two elements can't be folded, bail out.
4698 if ((LHSOp.getOpcode() != ISD::UNDEF &&
4699 LHSOp.getOpcode() != ISD::Constant &&
4700 LHSOp.getOpcode() != ISD::ConstantFP) ||
4701 (RHSOp.getOpcode() != ISD::UNDEF &&
4702 RHSOp.getOpcode() != ISD::Constant &&
4703 RHSOp.getOpcode() != ISD::ConstantFP))
4705 // Can't fold divide by zero.
4706 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
4707 N->getOpcode() == ISD::FDIV) {
4708 if ((RHSOp.getOpcode() == ISD::Constant &&
4709 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
4710 (RHSOp.getOpcode() == ISD::ConstantFP &&
4711 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero()))
4714 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp));
4715 AddToWorkList(Ops.back().Val);
4716 assert((Ops.back().getOpcode() == ISD::UNDEF ||
4717 Ops.back().getOpcode() == ISD::Constant ||
4718 Ops.back().getOpcode() == ISD::ConstantFP) &&
4719 "Scalar binop didn't fold!");
4722 if (Ops.size() == LHS.getNumOperands()) {
4723 MVT::ValueType VT = LHS.getValueType();
4724 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
4731 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
4732 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
4734 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
4735 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4736 // If we got a simplified select_cc node back from SimplifySelectCC, then
4737 // break it down into a new SETCC node, and a new SELECT node, and then return
4738 // the SELECT node, since we were called with a SELECT node.
4740 // Check to see if we got a select_cc back (to turn into setcc/select).
4741 // Otherwise, just return whatever node we got back, like fabs.
4742 if (SCC.getOpcode() == ISD::SELECT_CC) {
4743 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
4744 SCC.getOperand(0), SCC.getOperand(1),
4746 AddToWorkList(SETCC.Val);
4747 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
4748 SCC.getOperand(3), SETCC);
4755 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
4756 /// are the two values being selected between, see if we can simplify the
4757 /// select. Callers of this should assume that TheSelect is deleted if this
4758 /// returns true. As such, they should return the appropriate thing (e.g. the
4759 /// node) back to the top-level of the DAG combiner loop to avoid it being
4762 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
4765 // If this is a select from two identical things, try to pull the operation
4766 // through the select.
4767 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
4768 // If this is a load and the token chain is identical, replace the select
4769 // of two loads with a load through a select of the address to load from.
4770 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
4771 // constants have been dropped into the constant pool.
4772 if (LHS.getOpcode() == ISD::LOAD &&
4773 // Token chains must be identical.
4774 LHS.getOperand(0) == RHS.getOperand(0)) {
4775 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
4776 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
4778 // If this is an EXTLOAD, the VT's must match.
4779 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
4780 // FIXME: this conflates two src values, discarding one. This is not
4781 // the right thing to do, but nothing uses srcvalues now. When they do,
4782 // turn SrcValue into a list of locations.
4784 if (TheSelect->getOpcode() == ISD::SELECT) {
4785 // Check that the condition doesn't reach either load. If so, folding
4786 // this will induce a cycle into the DAG.
4787 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4788 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) {
4789 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
4790 TheSelect->getOperand(0), LLD->getBasePtr(),
4794 // Check that the condition doesn't reach either load. If so, folding
4795 // this will induce a cycle into the DAG.
4796 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4797 !RLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4798 !LLD->isPredecessor(TheSelect->getOperand(1).Val) &&
4799 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) {
4800 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
4801 TheSelect->getOperand(0),
4802 TheSelect->getOperand(1),
4803 LLD->getBasePtr(), RLD->getBasePtr(),
4804 TheSelect->getOperand(4));
4810 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
4811 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
4812 Addr,LLD->getSrcValue(),
4813 LLD->getSrcValueOffset(),
4815 LLD->getAlignment());
4817 Load = DAG.getExtLoad(LLD->getExtensionType(),
4818 TheSelect->getValueType(0),
4819 LLD->getChain(), Addr, LLD->getSrcValue(),
4820 LLD->getSrcValueOffset(),
4823 LLD->getAlignment());
4825 // Users of the select now use the result of the load.
4826 CombineTo(TheSelect, Load);
4828 // Users of the old loads now use the new load's chain. We know the
4829 // old-load value is dead now.
4830 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
4831 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
4841 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
4842 SDOperand N2, SDOperand N3,
4843 ISD::CondCode CC, bool NotExtCompare) {
4845 MVT::ValueType VT = N2.getValueType();
4846 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
4847 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
4848 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
4850 // Determine if the condition we're dealing with is constant
4851 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
4852 if (SCC.Val) AddToWorkList(SCC.Val);
4853 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
4855 // fold select_cc true, x, y -> x
4856 if (SCCC && SCCC->getValue())
4858 // fold select_cc false, x, y -> y
4859 if (SCCC && SCCC->getValue() == 0)
4862 // Check to see if we can simplify the select into an fabs node
4863 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
4864 // Allow either -0.0 or 0.0
4865 if (CFP->getValueAPF().isZero()) {
4866 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
4867 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
4868 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
4869 N2 == N3.getOperand(0))
4870 return DAG.getNode(ISD::FABS, VT, N0);
4872 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
4873 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
4874 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
4875 N2.getOperand(0) == N3)
4876 return DAG.getNode(ISD::FABS, VT, N3);
4880 // Check to see if we can perform the "gzip trick", transforming
4881 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
4882 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
4883 MVT::isInteger(N0.getValueType()) &&
4884 MVT::isInteger(N2.getValueType()) &&
4885 (N1C->isNullValue() || // (a < 0) ? b : 0
4886 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
4887 MVT::ValueType XType = N0.getValueType();
4888 MVT::ValueType AType = N2.getValueType();
4889 if (XType >= AType) {
4890 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
4891 // single-bit constant.
4892 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
4893 unsigned ShCtV = Log2_64(N2C->getValue());
4894 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
4895 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
4896 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
4897 AddToWorkList(Shift.Val);
4898 if (XType > AType) {
4899 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
4900 AddToWorkList(Shift.Val);
4902 return DAG.getNode(ISD::AND, AType, Shift, N2);
4904 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4905 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4906 TLI.getShiftAmountTy()));
4907 AddToWorkList(Shift.Val);
4908 if (XType > AType) {
4909 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
4910 AddToWorkList(Shift.Val);
4912 return DAG.getNode(ISD::AND, AType, Shift, N2);
4916 // fold select C, 16, 0 -> shl C, 4
4917 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
4918 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
4920 // If the caller doesn't want us to simplify this into a zext of a compare,
4922 if (NotExtCompare && N2C->getValue() == 1)
4925 // Get a SetCC of the condition
4926 // FIXME: Should probably make sure that setcc is legal if we ever have a
4927 // target where it isn't.
4928 SDOperand Temp, SCC;
4929 // cast from setcc result type to select result type
4930 if (AfterLegalize) {
4931 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4932 if (N2.getValueType() < SCC.getValueType())
4933 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
4935 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
4937 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
4938 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
4940 AddToWorkList(SCC.Val);
4941 AddToWorkList(Temp.Val);
4943 if (N2C->getValue() == 1)
4945 // shl setcc result by log2 n2c
4946 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
4947 DAG.getConstant(Log2_64(N2C->getValue()),
4948 TLI.getShiftAmountTy()));
4951 // Check to see if this is the equivalent of setcc
4952 // FIXME: Turn all of these into setcc if setcc if setcc is legal
4953 // otherwise, go ahead with the folds.
4954 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
4955 MVT::ValueType XType = N0.getValueType();
4956 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
4957 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4958 if (Res.getValueType() != VT)
4959 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
4963 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
4964 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
4965 TLI.isOperationLegal(ISD::CTLZ, XType)) {
4966 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
4967 return DAG.getNode(ISD::SRL, XType, Ctlz,
4968 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
4969 TLI.getShiftAmountTy()));
4971 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
4972 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
4973 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
4975 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
4976 DAG.getConstant(~0ULL, XType));
4977 return DAG.getNode(ISD::SRL, XType,
4978 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
4979 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4980 TLI.getShiftAmountTy()));
4982 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
4983 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
4984 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
4985 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4986 TLI.getShiftAmountTy()));
4987 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
4991 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
4992 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4993 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
4994 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
4995 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) {
4996 MVT::ValueType XType = N0.getValueType();
4997 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4998 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4999 TLI.getShiftAmountTy()));
5000 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
5001 AddToWorkList(Shift.Val);
5002 AddToWorkList(Add.Val);
5003 return DAG.getNode(ISD::XOR, XType, Add, Shift);
5005 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
5006 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5007 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
5008 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
5009 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
5010 MVT::ValueType XType = N0.getValueType();
5011 if (SubC->isNullValue() && MVT::isInteger(XType)) {
5012 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
5013 DAG.getConstant(MVT::getSizeInBits(XType)-1,
5014 TLI.getShiftAmountTy()));
5015 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
5016 AddToWorkList(Shift.Val);
5017 AddToWorkList(Add.Val);
5018 return DAG.getNode(ISD::XOR, XType, Add, Shift);
5026 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
5027 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
5028 SDOperand N1, ISD::CondCode Cond,
5029 bool foldBooleans) {
5030 TargetLowering::DAGCombinerInfo
5031 DagCombineInfo(DAG, !AfterLegalize, false, this);
5032 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo);
5035 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
5036 /// return a DAG expression to select that will generate the same value by
5037 /// multiplying by a magic number. See:
5038 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
5039 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
5040 std::vector<SDNode*> Built;
5041 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
5043 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
5049 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
5050 /// return a DAG expression to select that will generate the same value by
5051 /// multiplying by a magic number. See:
5052 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
5053 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
5054 std::vector<SDNode*> Built;
5055 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
5057 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
5063 /// FindBaseOffset - Return true if base is known not to alias with anything
5064 /// but itself. Provides base object and offset as results.
5065 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
5066 // Assume it is a primitive operation.
5067 Base = Ptr; Offset = 0;
5069 // If it's an adding a simple constant then integrate the offset.
5070 if (Base.getOpcode() == ISD::ADD) {
5071 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
5072 Base = Base.getOperand(0);
5073 Offset += C->getValue();
5077 // If it's any of the following then it can't alias with anything but itself.
5078 return isa<FrameIndexSDNode>(Base) ||
5079 isa<ConstantPoolSDNode>(Base) ||
5080 isa<GlobalAddressSDNode>(Base);
5083 /// isAlias - Return true if there is any possibility that the two addresses
5085 bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1,
5086 const Value *SrcValue1, int SrcValueOffset1,
5087 SDOperand Ptr2, int64_t Size2,
5088 const Value *SrcValue2, int SrcValueOffset2)
5090 // If they are the same then they must be aliases.
5091 if (Ptr1 == Ptr2) return true;
5093 // Gather base node and offset information.
5094 SDOperand Base1, Base2;
5095 int64_t Offset1, Offset2;
5096 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
5097 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
5099 // If they have a same base address then...
5100 if (Base1 == Base2) {
5101 // Check to see if the addresses overlap.
5102 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
5105 // If we know both bases then they can't alias.
5106 if (KnownBase1 && KnownBase2) return false;
5108 if (CombinerGlobalAA) {
5109 // Use alias analysis information.
5110 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
5111 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
5112 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
5113 AliasAnalysis::AliasResult AAResult =
5114 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
5115 if (AAResult == AliasAnalysis::NoAlias)
5119 // Otherwise we have to assume they alias.
5123 /// FindAliasInfo - Extracts the relevant alias information from the memory
5124 /// node. Returns true if the operand was a load.
5125 bool DAGCombiner::FindAliasInfo(SDNode *N,
5126 SDOperand &Ptr, int64_t &Size,
5127 const Value *&SrcValue, int &SrcValueOffset) {
5128 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5129 Ptr = LD->getBasePtr();
5130 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3;
5131 SrcValue = LD->getSrcValue();
5132 SrcValueOffset = LD->getSrcValueOffset();
5134 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5135 Ptr = ST->getBasePtr();
5136 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3;
5137 SrcValue = ST->getSrcValue();
5138 SrcValueOffset = ST->getSrcValueOffset();
5140 assert(0 && "FindAliasInfo expected a memory operand");
5146 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
5147 /// looking for aliasing nodes and adding them to the Aliases vector.
5148 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
5149 SmallVector<SDOperand, 8> &Aliases) {
5150 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
5151 std::set<SDNode *> Visited; // Visited node set.
5153 // Get alias information for node.
5156 const Value *SrcValue;
5158 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
5161 Chains.push_back(OriginalChain);
5163 // Look at each chain and determine if it is an alias. If so, add it to the
5164 // aliases list. If not, then continue up the chain looking for the next
5166 while (!Chains.empty()) {
5167 SDOperand Chain = Chains.back();
5170 // Don't bother if we've been before.
5171 if (Visited.find(Chain.Val) != Visited.end()) continue;
5172 Visited.insert(Chain.Val);
5174 switch (Chain.getOpcode()) {
5175 case ISD::EntryToken:
5176 // Entry token is ideal chain operand, but handled in FindBetterChain.
5181 // Get alias information for Chain.
5184 const Value *OpSrcValue;
5185 int OpSrcValueOffset;
5186 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
5187 OpSrcValue, OpSrcValueOffset);
5189 // If chain is alias then stop here.
5190 if (!(IsLoad && IsOpLoad) &&
5191 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
5192 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
5193 Aliases.push_back(Chain);
5195 // Look further up the chain.
5196 Chains.push_back(Chain.getOperand(0));
5197 // Clean up old chain.
5198 AddToWorkList(Chain.Val);
5203 case ISD::TokenFactor:
5204 // We have to check each of the operands of the token factor, so we queue
5205 // then up. Adding the operands to the queue (stack) in reverse order
5206 // maintains the original order and increases the likelihood that getNode
5207 // will find a matching token factor (CSE.)
5208 for (unsigned n = Chain.getNumOperands(); n;)
5209 Chains.push_back(Chain.getOperand(--n));
5210 // Eliminate the token factor if we can.
5211 AddToWorkList(Chain.Val);
5215 // For all other instructions we will just have to take what we can get.
5216 Aliases.push_back(Chain);
5222 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
5223 /// for a better chain (aliasing node.)
5224 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
5225 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
5227 // Accumulate all the aliases to this node.
5228 GatherAllAliases(N, OldChain, Aliases);
5230 if (Aliases.size() == 0) {
5231 // If no operands then chain to entry token.
5232 return DAG.getEntryNode();
5233 } else if (Aliases.size() == 1) {
5234 // If a single operand then chain to it. We don't need to revisit it.
5238 // Construct a custom tailored token factor.
5239 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5240 &Aliases[0], Aliases.size());
5242 // Make sure the old chain gets cleaned up.
5243 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
5248 // SelectionDAG::Combine - This is the entry point for the file.
5250 void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
5251 if (!RunningAfterLegalize && ViewDAGCombine1)
5253 if (RunningAfterLegalize && ViewDAGCombine2)
5255 /// run - This is the main entry point to this class.
5257 DAGCombiner(*this, AA).Run(RunningAfterLegalize);