1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: divide by zero is currently left unfolded. do we want to turn this
27 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "dagcombine"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Target/TargetLowering.h"
37 #include "llvm/Support/Compiler.h"
38 #include "llvm/Support/CommandLine.h"
46 static Statistic<> NodesCombined ("dagcombiner",
47 "Number of dag nodes combined");
50 CombinerAA("combiner-alias-analysis", cl::Hidden,
51 cl::desc("Turn on alias analysis turning testing"));
53 //------------------------------ DAGCombiner ---------------------------------//
55 class VISIBILITY_HIDDEN DAGCombiner {
60 // Worklist of all of the nodes that need to be simplified.
61 std::vector<SDNode*> WorkList;
63 /// AddUsersToWorkList - When an instruction is simplified, add all users of
64 /// the instruction to the work lists because they might get more simplified
67 void AddUsersToWorkList(SDNode *N) {
68 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
73 /// removeFromWorkList - remove all instances of N from the worklist.
75 void removeFromWorkList(SDNode *N) {
76 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
81 /// AddToWorkList - Add to the work list making sure it's instance is at the
82 /// the back (next to be processed.)
83 void AddToWorkList(SDNode *N) {
84 removeFromWorkList(N);
85 WorkList.push_back(N);
88 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo) {
89 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
91 DEBUG(std::cerr << "\nReplacing.1 "; N->dump();
92 std::cerr << "\nWith: "; To[0].Val->dump(&DAG);
93 std::cerr << " and " << NumTo-1 << " other values\n");
94 std::vector<SDNode*> NowDead;
95 DAG.ReplaceAllUsesWith(N, To, &NowDead);
97 // Push the new nodes and any users onto the worklist
98 for (unsigned i = 0, e = NumTo; i != e; ++i) {
99 AddToWorkList(To[i].Val);
100 AddUsersToWorkList(To[i].Val);
103 // Nodes can be reintroduced into the worklist. Make sure we do not
104 // process a node that has been replaced.
105 removeFromWorkList(N);
106 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
107 removeFromWorkList(NowDead[i]);
109 // Finally, since the node is now dead, remove it from the graph.
111 return SDOperand(N, 0);
114 SDOperand CombineTo(SDNode *N, SDOperand Res) {
115 return CombineTo(N, &Res, 1);
118 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
119 SDOperand To[] = { Res0, Res1 };
120 return CombineTo(N, To, 2);
124 /// SimplifyDemandedBits - Check the specified integer node value to see if
125 /// it can be simplified or if things it uses can be simplified by bit
126 /// propagation. If so, return true.
127 bool SimplifyDemandedBits(SDOperand Op) {
128 TargetLowering::TargetLoweringOpt TLO(DAG);
129 uint64_t KnownZero, KnownOne;
130 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
131 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
135 AddToWorkList(Op.Val);
137 // Replace the old value with the new one.
139 DEBUG(std::cerr << "\nReplacing.2 "; TLO.Old.Val->dump();
140 std::cerr << "\nWith: "; TLO.New.Val->dump(&DAG);
143 std::vector<SDNode*> NowDead;
144 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
146 // Push the new node and any (possibly new) users onto the worklist.
147 AddToWorkList(TLO.New.Val);
148 AddUsersToWorkList(TLO.New.Val);
150 // Nodes can end up on the worklist more than once. Make sure we do
151 // not process a node that has been replaced.
152 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
153 removeFromWorkList(NowDead[i]);
155 // Finally, if the node is now dead, remove it from the graph. The node
156 // may not be dead if the replacement process recursively simplified to
157 // something else needing this node.
158 if (TLO.Old.Val->use_empty()) {
159 removeFromWorkList(TLO.Old.Val);
160 DAG.DeleteNode(TLO.Old.Val);
165 /// visit - call the node-specific routine that knows how to fold each
166 /// particular type of node.
167 SDOperand visit(SDNode *N);
169 // Visitation implementation - Implement dag node combining for different
170 // node types. The semantics are as follows:
172 // SDOperand.Val == 0 - No change was made
173 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
174 // otherwise - N should be replaced by the returned Operand.
176 SDOperand visitTokenFactor(SDNode *N);
177 SDOperand visitADD(SDNode *N);
178 SDOperand visitSUB(SDNode *N);
179 SDOperand visitMUL(SDNode *N);
180 SDOperand visitSDIV(SDNode *N);
181 SDOperand visitUDIV(SDNode *N);
182 SDOperand visitSREM(SDNode *N);
183 SDOperand visitUREM(SDNode *N);
184 SDOperand visitMULHU(SDNode *N);
185 SDOperand visitMULHS(SDNode *N);
186 SDOperand visitAND(SDNode *N);
187 SDOperand visitOR(SDNode *N);
188 SDOperand visitXOR(SDNode *N);
189 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp);
190 SDOperand visitSHL(SDNode *N);
191 SDOperand visitSRA(SDNode *N);
192 SDOperand visitSRL(SDNode *N);
193 SDOperand visitCTLZ(SDNode *N);
194 SDOperand visitCTTZ(SDNode *N);
195 SDOperand visitCTPOP(SDNode *N);
196 SDOperand visitSELECT(SDNode *N);
197 SDOperand visitSELECT_CC(SDNode *N);
198 SDOperand visitSETCC(SDNode *N);
199 SDOperand visitSIGN_EXTEND(SDNode *N);
200 SDOperand visitZERO_EXTEND(SDNode *N);
201 SDOperand visitANY_EXTEND(SDNode *N);
202 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
203 SDOperand visitTRUNCATE(SDNode *N);
204 SDOperand visitBIT_CONVERT(SDNode *N);
205 SDOperand visitVBIT_CONVERT(SDNode *N);
206 SDOperand visitFADD(SDNode *N);
207 SDOperand visitFSUB(SDNode *N);
208 SDOperand visitFMUL(SDNode *N);
209 SDOperand visitFDIV(SDNode *N);
210 SDOperand visitFREM(SDNode *N);
211 SDOperand visitFCOPYSIGN(SDNode *N);
212 SDOperand visitSINT_TO_FP(SDNode *N);
213 SDOperand visitUINT_TO_FP(SDNode *N);
214 SDOperand visitFP_TO_SINT(SDNode *N);
215 SDOperand visitFP_TO_UINT(SDNode *N);
216 SDOperand visitFP_ROUND(SDNode *N);
217 SDOperand visitFP_ROUND_INREG(SDNode *N);
218 SDOperand visitFP_EXTEND(SDNode *N);
219 SDOperand visitFNEG(SDNode *N);
220 SDOperand visitFABS(SDNode *N);
221 SDOperand visitBRCOND(SDNode *N);
222 SDOperand visitBR_CC(SDNode *N);
223 SDOperand visitLOAD(SDNode *N);
224 SDOperand visitSTORE(SDNode *N);
225 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
226 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
227 SDOperand visitVBUILD_VECTOR(SDNode *N);
228 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
229 SDOperand visitVVECTOR_SHUFFLE(SDNode *N);
231 SDOperand XformToShuffleWithZero(SDNode *N);
232 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
234 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
235 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
236 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
237 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
238 SDOperand N3, ISD::CondCode CC);
239 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
240 ISD::CondCode Cond, bool foldBooleans = true);
241 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType);
242 SDOperand BuildSDIV(SDNode *N);
243 SDOperand BuildUDIV(SDNode *N);
244 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
246 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
247 /// looking for aliasing nodes and adding them to the Aliases vector.
248 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
249 SmallVector<SDOperand, 8> &Aliases);
251 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
252 /// looking for a better chain (aliasing node.)
253 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
256 DAGCombiner(SelectionDAG &D)
257 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
259 /// Run - runs the dag combiner on all nodes in the work list
260 void Run(bool RunningAfterLegalize);
264 //===----------------------------------------------------------------------===//
265 // TargetLowering::DAGCombinerInfo implementation
266 //===----------------------------------------------------------------------===//
268 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
269 ((DAGCombiner*)DC)->AddToWorkList(N);
272 SDOperand TargetLowering::DAGCombinerInfo::
273 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
274 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
277 SDOperand TargetLowering::DAGCombinerInfo::
278 CombineTo(SDNode *N, SDOperand Res) {
279 return ((DAGCombiner*)DC)->CombineTo(N, Res);
283 SDOperand TargetLowering::DAGCombinerInfo::
284 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
285 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
291 //===----------------------------------------------------------------------===//
294 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
295 // that selects between the values 1 and 0, making it equivalent to a setcc.
296 // Also, set the incoming LHS, RHS, and CC references to the appropriate
297 // nodes based on the type of node we are checking. This simplifies life a
298 // bit for the callers.
299 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
301 if (N.getOpcode() == ISD::SETCC) {
302 LHS = N.getOperand(0);
303 RHS = N.getOperand(1);
304 CC = N.getOperand(2);
307 if (N.getOpcode() == ISD::SELECT_CC &&
308 N.getOperand(2).getOpcode() == ISD::Constant &&
309 N.getOperand(3).getOpcode() == ISD::Constant &&
310 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
311 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
312 LHS = N.getOperand(0);
313 RHS = N.getOperand(1);
314 CC = N.getOperand(4);
320 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
321 // one use. If this is true, it allows the users to invert the operation for
322 // free when it is profitable to do so.
323 static bool isOneUseSetCC(SDOperand N) {
324 SDOperand N0, N1, N2;
325 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
330 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
331 MVT::ValueType VT = N0.getValueType();
332 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
333 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
334 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
335 if (isa<ConstantSDNode>(N1)) {
336 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
337 AddToWorkList(OpNode.Val);
338 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
339 } else if (N0.hasOneUse()) {
340 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
341 AddToWorkList(OpNode.Val);
342 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
345 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
346 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
347 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
348 if (isa<ConstantSDNode>(N0)) {
349 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
350 AddToWorkList(OpNode.Val);
351 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
352 } else if (N1.hasOneUse()) {
353 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
354 AddToWorkList(OpNode.Val);
355 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
361 void DAGCombiner::Run(bool RunningAfterLegalize) {
362 // set the instance variable, so that the various visit routines may use it.
363 AfterLegalize = RunningAfterLegalize;
365 // Add all the dag nodes to the worklist.
366 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
367 E = DAG.allnodes_end(); I != E; ++I)
368 WorkList.push_back(I);
370 // Create a dummy node (which is not added to allnodes), that adds a reference
371 // to the root node, preventing it from being deleted, and tracking any
372 // changes of the root.
373 HandleSDNode Dummy(DAG.getRoot());
376 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
377 TargetLowering::DAGCombinerInfo
378 DagCombineInfo(DAG, !RunningAfterLegalize, this);
380 // while the worklist isn't empty, inspect the node on the end of it and
381 // try and combine it.
382 while (!WorkList.empty()) {
383 SDNode *N = WorkList.back();
386 // If N has no uses, it is dead. Make sure to revisit all N's operands once
387 // N is deleted from the DAG, since they too may now be dead or may have a
388 // reduced number of uses, allowing other xforms.
389 if (N->use_empty() && N != &Dummy) {
390 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
391 AddToWorkList(N->getOperand(i).Val);
397 SDOperand RV = visit(N);
399 // If nothing happened, try a target-specific DAG combine.
401 assert(N->getOpcode() != ISD::DELETED_NODE &&
402 "Node was deleted but visit returned NULL!");
403 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
404 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
405 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
410 // If we get back the same node we passed in, rather than a new node or
411 // zero, we know that the node must have defined multiple values and
412 // CombineTo was used. Since CombineTo takes care of the worklist
413 // mechanics for us, we have no work to do in this case.
415 assert(N->getOpcode() != ISD::DELETED_NODE &&
416 RV.Val->getOpcode() != ISD::DELETED_NODE &&
417 "Node was deleted but visit returned new node!");
419 DEBUG(std::cerr << "\nReplacing.3 "; N->dump();
420 std::cerr << "\nWith: "; RV.Val->dump(&DAG);
422 std::vector<SDNode*> NowDead;
423 if (N->getNumValues() == RV.Val->getNumValues())
424 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
426 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
428 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
431 // Push the new node and any users onto the worklist
432 AddToWorkList(RV.Val);
433 AddUsersToWorkList(RV.Val);
435 // Nodes can be reintroduced into the worklist. Make sure we do not
436 // process a node that has been replaced.
437 removeFromWorkList(N);
438 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
439 removeFromWorkList(NowDead[i]);
441 // Finally, since the node is now dead, remove it from the graph.
447 // If the root changed (e.g. it was a dead load, update the root).
448 DAG.setRoot(Dummy.getValue());
451 SDOperand DAGCombiner::visit(SDNode *N) {
452 switch(N->getOpcode()) {
454 case ISD::TokenFactor: return visitTokenFactor(N);
455 case ISD::ADD: return visitADD(N);
456 case ISD::SUB: return visitSUB(N);
457 case ISD::MUL: return visitMUL(N);
458 case ISD::SDIV: return visitSDIV(N);
459 case ISD::UDIV: return visitUDIV(N);
460 case ISD::SREM: return visitSREM(N);
461 case ISD::UREM: return visitUREM(N);
462 case ISD::MULHU: return visitMULHU(N);
463 case ISD::MULHS: return visitMULHS(N);
464 case ISD::AND: return visitAND(N);
465 case ISD::OR: return visitOR(N);
466 case ISD::XOR: return visitXOR(N);
467 case ISD::SHL: return visitSHL(N);
468 case ISD::SRA: return visitSRA(N);
469 case ISD::SRL: return visitSRL(N);
470 case ISD::CTLZ: return visitCTLZ(N);
471 case ISD::CTTZ: return visitCTTZ(N);
472 case ISD::CTPOP: return visitCTPOP(N);
473 case ISD::SELECT: return visitSELECT(N);
474 case ISD::SELECT_CC: return visitSELECT_CC(N);
475 case ISD::SETCC: return visitSETCC(N);
476 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
477 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
478 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
479 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
480 case ISD::TRUNCATE: return visitTRUNCATE(N);
481 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
482 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N);
483 case ISD::FADD: return visitFADD(N);
484 case ISD::FSUB: return visitFSUB(N);
485 case ISD::FMUL: return visitFMUL(N);
486 case ISD::FDIV: return visitFDIV(N);
487 case ISD::FREM: return visitFREM(N);
488 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
489 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
490 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
491 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
492 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
493 case ISD::FP_ROUND: return visitFP_ROUND(N);
494 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
495 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
496 case ISD::FNEG: return visitFNEG(N);
497 case ISD::FABS: return visitFABS(N);
498 case ISD::BRCOND: return visitBRCOND(N);
499 case ISD::BR_CC: return visitBR_CC(N);
500 case ISD::LOAD: return visitLOAD(N);
501 case ISD::STORE: return visitSTORE(N);
502 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
503 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
504 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N);
505 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
506 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N);
507 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD);
508 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB);
509 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL);
510 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV);
511 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV);
512 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND);
513 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR);
514 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR);
519 /// getInputChainForNode - Given a node, return its input chain if it has one,
520 /// otherwise return a null sd operand.
521 static SDOperand getInputChainForNode(SDNode *N) {
522 if (unsigned NumOps = N->getNumOperands()) {
523 if (N->getOperand(0).getValueType() == MVT::Other)
524 return N->getOperand(0);
525 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
526 return N->getOperand(NumOps-1);
527 for (unsigned i = 1; i < NumOps-1; ++i)
528 if (N->getOperand(i).getValueType() == MVT::Other)
529 return N->getOperand(i);
531 return SDOperand(0, 0);
534 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
535 // If N has two operands, where one has an input chain equal to the other,
536 // the 'other' chain is redundant.
537 if (N->getNumOperands() == 2) {
538 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
539 return N->getOperand(0);
540 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
541 return N->getOperand(1);
545 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
546 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
547 bool Changed = false; // If we should replace this token factor.
549 // Start out with this token factor.
552 // Iterate through token factors. The TFs grows when new token factors are
554 for (unsigned i = 0; i < TFs.size(); ++i) {
557 // Check each of the operands.
558 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
559 SDOperand Op = TF->getOperand(i);
561 switch (Op.getOpcode()) {
562 case ISD::EntryToken:
563 // Entry tokens don't need to be added to the list. They are
568 case ISD::TokenFactor:
569 if ((CombinerAA || Op.hasOneUse()) &&
570 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
571 // Queue up for processing.
572 TFs.push_back(Op.Val);
573 // Clean up in case the token factor is removed.
574 AddToWorkList(Op.Val);
581 // Only add if not there prior.
582 if (std::find(Ops.begin(), Ops.end(), Op) == Ops.end())
591 // If we've change things around then replace token factor.
593 if (Ops.size() == 0) {
594 // The entry token is the only possible outcome.
595 Result = DAG.getEntryNode();
597 // New and improved token factor.
598 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
605 SDOperand DAGCombiner::visitADD(SDNode *N) {
606 SDOperand N0 = N->getOperand(0);
607 SDOperand N1 = N->getOperand(1);
608 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
609 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
610 MVT::ValueType VT = N0.getValueType();
612 // fold (add c1, c2) -> c1+c2
614 return DAG.getNode(ISD::ADD, VT, N0, N1);
615 // canonicalize constant to RHS
617 return DAG.getNode(ISD::ADD, VT, N1, N0);
618 // fold (add x, 0) -> x
619 if (N1C && N1C->isNullValue())
621 // fold ((c1-A)+c2) -> (c1+c2)-A
622 if (N1C && N0.getOpcode() == ISD::SUB)
623 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
624 return DAG.getNode(ISD::SUB, VT,
625 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
628 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
631 // fold ((0-A) + B) -> B-A
632 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
633 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
634 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
635 // fold (A + (0-B)) -> A-B
636 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
637 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
638 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
639 // fold (A+(B-A)) -> B
640 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
641 return N1.getOperand(0);
643 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
644 return SDOperand(N, 0);
646 // fold (a+b) -> (a|b) iff a and b share no bits.
647 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
648 uint64_t LHSZero, LHSOne;
649 uint64_t RHSZero, RHSOne;
650 uint64_t Mask = MVT::getIntVTBitMask(VT);
651 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
653 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
655 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
656 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
657 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
658 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
659 return DAG.getNode(ISD::OR, VT, N0, N1);
666 SDOperand DAGCombiner::visitSUB(SDNode *N) {
667 SDOperand N0 = N->getOperand(0);
668 SDOperand N1 = N->getOperand(1);
669 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
670 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
671 MVT::ValueType VT = N0.getValueType();
673 // fold (sub x, x) -> 0
675 return DAG.getConstant(0, N->getValueType(0));
676 // fold (sub c1, c2) -> c1-c2
678 return DAG.getNode(ISD::SUB, VT, N0, N1);
679 // fold (sub x, c) -> (add x, -c)
681 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
683 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
684 return N0.getOperand(1);
686 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
687 return N0.getOperand(0);
691 SDOperand DAGCombiner::visitMUL(SDNode *N) {
692 SDOperand N0 = N->getOperand(0);
693 SDOperand N1 = N->getOperand(1);
694 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
695 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
696 MVT::ValueType VT = N0.getValueType();
698 // fold (mul c1, c2) -> c1*c2
700 return DAG.getNode(ISD::MUL, VT, N0, N1);
701 // canonicalize constant to RHS
703 return DAG.getNode(ISD::MUL, VT, N1, N0);
704 // fold (mul x, 0) -> 0
705 if (N1C && N1C->isNullValue())
707 // fold (mul x, -1) -> 0-x
708 if (N1C && N1C->isAllOnesValue())
709 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
710 // fold (mul x, (1 << c)) -> x << c
711 if (N1C && isPowerOf2_64(N1C->getValue()))
712 return DAG.getNode(ISD::SHL, VT, N0,
713 DAG.getConstant(Log2_64(N1C->getValue()),
714 TLI.getShiftAmountTy()));
715 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
716 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
717 // FIXME: If the input is something that is easily negated (e.g. a
718 // single-use add), we should put the negate there.
719 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
720 DAG.getNode(ISD::SHL, VT, N0,
721 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
722 TLI.getShiftAmountTy())));
725 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
726 if (N1C && N0.getOpcode() == ISD::SHL &&
727 isa<ConstantSDNode>(N0.getOperand(1))) {
728 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
729 AddToWorkList(C3.Val);
730 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
733 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
736 SDOperand Sh(0,0), Y(0,0);
737 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
738 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
739 N0.Val->hasOneUse()) {
741 } else if (N1.getOpcode() == ISD::SHL &&
742 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
746 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
747 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
750 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
751 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
752 isa<ConstantSDNode>(N0.getOperand(1))) {
753 return DAG.getNode(ISD::ADD, VT,
754 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
755 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
759 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
765 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
766 SDOperand N0 = N->getOperand(0);
767 SDOperand N1 = N->getOperand(1);
768 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
769 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
770 MVT::ValueType VT = N->getValueType(0);
772 // fold (sdiv c1, c2) -> c1/c2
773 if (N0C && N1C && !N1C->isNullValue())
774 return DAG.getNode(ISD::SDIV, VT, N0, N1);
775 // fold (sdiv X, 1) -> X
776 if (N1C && N1C->getSignExtended() == 1LL)
778 // fold (sdiv X, -1) -> 0-X
779 if (N1C && N1C->isAllOnesValue())
780 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
781 // If we know the sign bits of both operands are zero, strength reduce to a
782 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
783 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
784 if (TLI.MaskedValueIsZero(N1, SignBit) &&
785 TLI.MaskedValueIsZero(N0, SignBit))
786 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
787 // fold (sdiv X, pow2) -> simple ops after legalize
788 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
789 (isPowerOf2_64(N1C->getSignExtended()) ||
790 isPowerOf2_64(-N1C->getSignExtended()))) {
791 // If dividing by powers of two is cheap, then don't perform the following
793 if (TLI.isPow2DivCheap())
795 int64_t pow2 = N1C->getSignExtended();
796 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
797 unsigned lg2 = Log2_64(abs2);
798 // Splat the sign bit into the register
799 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
800 DAG.getConstant(MVT::getSizeInBits(VT)-1,
801 TLI.getShiftAmountTy()));
802 AddToWorkList(SGN.Val);
803 // Add (N0 < 0) ? abs2 - 1 : 0;
804 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
805 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
806 TLI.getShiftAmountTy()));
807 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
808 AddToWorkList(SRL.Val);
809 AddToWorkList(ADD.Val); // Divide by pow2
810 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
811 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
812 // If we're dividing by a positive value, we're done. Otherwise, we must
813 // negate the result.
816 AddToWorkList(SRA.Val);
817 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
819 // if integer divide is expensive and we satisfy the requirements, emit an
820 // alternate sequence.
821 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
822 !TLI.isIntDivCheap()) {
823 SDOperand Op = BuildSDIV(N);
824 if (Op.Val) return Op;
829 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
830 SDOperand N0 = N->getOperand(0);
831 SDOperand N1 = N->getOperand(1);
832 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
833 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
834 MVT::ValueType VT = N->getValueType(0);
836 // fold (udiv c1, c2) -> c1/c2
837 if (N0C && N1C && !N1C->isNullValue())
838 return DAG.getNode(ISD::UDIV, VT, N0, N1);
839 // fold (udiv x, (1 << c)) -> x >>u c
840 if (N1C && isPowerOf2_64(N1C->getValue()))
841 return DAG.getNode(ISD::SRL, VT, N0,
842 DAG.getConstant(Log2_64(N1C->getValue()),
843 TLI.getShiftAmountTy()));
844 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
845 if (N1.getOpcode() == ISD::SHL) {
846 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
847 if (isPowerOf2_64(SHC->getValue())) {
848 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
849 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
850 DAG.getConstant(Log2_64(SHC->getValue()),
852 AddToWorkList(Add.Val);
853 return DAG.getNode(ISD::SRL, VT, N0, Add);
857 // fold (udiv x, c) -> alternate
858 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
859 SDOperand Op = BuildUDIV(N);
860 if (Op.Val) return Op;
865 SDOperand DAGCombiner::visitSREM(SDNode *N) {
866 SDOperand N0 = N->getOperand(0);
867 SDOperand N1 = N->getOperand(1);
868 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
869 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
870 MVT::ValueType VT = N->getValueType(0);
872 // fold (srem c1, c2) -> c1%c2
873 if (N0C && N1C && !N1C->isNullValue())
874 return DAG.getNode(ISD::SREM, VT, N0, N1);
875 // If we know the sign bits of both operands are zero, strength reduce to a
876 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
877 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
878 if (TLI.MaskedValueIsZero(N1, SignBit) &&
879 TLI.MaskedValueIsZero(N0, SignBit))
880 return DAG.getNode(ISD::UREM, VT, N0, N1);
884 SDOperand DAGCombiner::visitUREM(SDNode *N) {
885 SDOperand N0 = N->getOperand(0);
886 SDOperand N1 = N->getOperand(1);
887 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
888 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
889 MVT::ValueType VT = N->getValueType(0);
891 // fold (urem c1, c2) -> c1%c2
892 if (N0C && N1C && !N1C->isNullValue())
893 return DAG.getNode(ISD::UREM, VT, N0, N1);
894 // fold (urem x, pow2) -> (and x, pow2-1)
895 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
896 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
897 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
898 if (N1.getOpcode() == ISD::SHL) {
899 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
900 if (isPowerOf2_64(SHC->getValue())) {
901 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
902 AddToWorkList(Add.Val);
903 return DAG.getNode(ISD::AND, VT, N0, Add);
910 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
911 SDOperand N0 = N->getOperand(0);
912 SDOperand N1 = N->getOperand(1);
913 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
915 // fold (mulhs x, 0) -> 0
916 if (N1C && N1C->isNullValue())
918 // fold (mulhs x, 1) -> (sra x, size(x)-1)
919 if (N1C && N1C->getValue() == 1)
920 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
921 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
922 TLI.getShiftAmountTy()));
926 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
927 SDOperand N0 = N->getOperand(0);
928 SDOperand N1 = N->getOperand(1);
929 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
931 // fold (mulhu x, 0) -> 0
932 if (N1C && N1C->isNullValue())
934 // fold (mulhu x, 1) -> 0
935 if (N1C && N1C->getValue() == 1)
936 return DAG.getConstant(0, N0.getValueType());
940 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
941 /// two operands of the same opcode, try to simplify it.
942 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
943 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
944 MVT::ValueType VT = N0.getValueType();
945 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
947 // For each of OP in AND/OR/XOR:
948 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
949 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
950 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
951 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
952 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
953 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
954 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
955 SDOperand ORNode = DAG.getNode(N->getOpcode(),
956 N0.getOperand(0).getValueType(),
957 N0.getOperand(0), N1.getOperand(0));
958 AddToWorkList(ORNode.Val);
959 return DAG.getNode(N0.getOpcode(), VT, ORNode);
962 // For each of OP in SHL/SRL/SRA/AND...
963 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
964 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
965 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
966 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
967 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
968 N0.getOperand(1) == N1.getOperand(1)) {
969 SDOperand ORNode = DAG.getNode(N->getOpcode(),
970 N0.getOperand(0).getValueType(),
971 N0.getOperand(0), N1.getOperand(0));
972 AddToWorkList(ORNode.Val);
973 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
979 SDOperand DAGCombiner::visitAND(SDNode *N) {
980 SDOperand N0 = N->getOperand(0);
981 SDOperand N1 = N->getOperand(1);
982 SDOperand LL, LR, RL, RR, CC0, CC1;
983 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
984 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
985 MVT::ValueType VT = N1.getValueType();
986 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
988 // fold (and c1, c2) -> c1&c2
990 return DAG.getNode(ISD::AND, VT, N0, N1);
991 // canonicalize constant to RHS
993 return DAG.getNode(ISD::AND, VT, N1, N0);
994 // fold (and x, -1) -> x
995 if (N1C && N1C->isAllOnesValue())
997 // if (and x, c) is known to be zero, return 0
998 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
999 return DAG.getConstant(0, VT);
1001 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1004 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1005 if (N1C && N0.getOpcode() == ISD::OR)
1006 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1007 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1009 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1010 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1011 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1012 if (TLI.MaskedValueIsZero(N0.getOperand(0),
1013 ~N1C->getValue() & InMask)) {
1014 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1017 // Replace uses of the AND with uses of the Zero extend node.
1020 // We actually want to replace all uses of the any_extend with the
1021 // zero_extend, to avoid duplicating things. This will later cause this
1022 // AND to be folded.
1023 CombineTo(N0.Val, Zext);
1024 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1027 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1028 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1029 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1030 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1032 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1033 MVT::isInteger(LL.getValueType())) {
1034 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1035 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1036 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1037 AddToWorkList(ORNode.Val);
1038 return DAG.getSetCC(VT, ORNode, LR, Op1);
1040 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1041 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1042 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1043 AddToWorkList(ANDNode.Val);
1044 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1046 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1047 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1048 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1049 AddToWorkList(ORNode.Val);
1050 return DAG.getSetCC(VT, ORNode, LR, Op1);
1053 // canonicalize equivalent to ll == rl
1054 if (LL == RR && LR == RL) {
1055 Op1 = ISD::getSetCCSwappedOperands(Op1);
1058 if (LL == RL && LR == RR) {
1059 bool isInteger = MVT::isInteger(LL.getValueType());
1060 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1061 if (Result != ISD::SETCC_INVALID)
1062 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1066 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1067 if (N0.getOpcode() == N1.getOpcode()) {
1068 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1069 if (Tmp.Val) return Tmp;
1072 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1073 // fold (and (sra)) -> (and (srl)) when possible.
1074 if (!MVT::isVector(VT) &&
1075 SimplifyDemandedBits(SDOperand(N, 0)))
1076 return SDOperand(N, 0);
1077 // fold (zext_inreg (extload x)) -> (zextload x)
1078 if (ISD::isEXTLoad(N0.Val)) {
1079 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1080 MVT::ValueType EVT = LN0->getLoadedVT();
1081 // If we zero all the possible extended bits, then we can turn this into
1082 // a zextload if we are running before legalize or the operation is legal.
1083 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1084 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1085 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1086 LN0->getBasePtr(), LN0->getSrcValue(),
1087 LN0->getSrcValueOffset(), EVT);
1089 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1090 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1093 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1094 if (ISD::isSEXTLoad(N0.Val) && N0.hasOneUse()) {
1095 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1096 MVT::ValueType EVT = LN0->getLoadedVT();
1097 // If we zero all the possible extended bits, then we can turn this into
1098 // a zextload if we are running before legalize or the operation is legal.
1099 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1100 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1101 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1102 LN0->getBasePtr(), LN0->getSrcValue(),
1103 LN0->getSrcValueOffset(), EVT);
1105 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1106 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1110 // fold (and (load x), 255) -> (zextload x, i8)
1111 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1112 if (N1C && N0.getOpcode() == ISD::LOAD) {
1113 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1114 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1116 MVT::ValueType EVT, LoadedVT;
1117 if (N1C->getValue() == 255)
1119 else if (N1C->getValue() == 65535)
1121 else if (N1C->getValue() == ~0U)
1126 LoadedVT = LN0->getLoadedVT();
1127 if (EVT != MVT::Other && LoadedVT > EVT &&
1128 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1129 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1130 // For big endian targets, we need to add an offset to the pointer to
1131 // load the correct bytes. For little endian systems, we merely need to
1132 // read fewer bytes from the same pointer.
1134 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1135 SDOperand NewPtr = LN0->getBasePtr();
1136 if (!TLI.isLittleEndian())
1137 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1138 DAG.getConstant(PtrOff, PtrType));
1139 AddToWorkList(NewPtr.Val);
1141 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1142 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT);
1144 CombineTo(N0.Val, Load, Load.getValue(1));
1145 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1153 SDOperand DAGCombiner::visitOR(SDNode *N) {
1154 SDOperand N0 = N->getOperand(0);
1155 SDOperand N1 = N->getOperand(1);
1156 SDOperand LL, LR, RL, RR, CC0, CC1;
1157 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1158 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1159 MVT::ValueType VT = N1.getValueType();
1160 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1162 // fold (or c1, c2) -> c1|c2
1164 return DAG.getNode(ISD::OR, VT, N0, N1);
1165 // canonicalize constant to RHS
1167 return DAG.getNode(ISD::OR, VT, N1, N0);
1168 // fold (or x, 0) -> x
1169 if (N1C && N1C->isNullValue())
1171 // fold (or x, -1) -> -1
1172 if (N1C && N1C->isAllOnesValue())
1174 // fold (or x, c) -> c iff (x & ~c) == 0
1176 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1179 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1182 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1183 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1184 isa<ConstantSDNode>(N0.getOperand(1))) {
1185 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1186 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1188 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1190 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1191 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1192 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1193 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1195 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1196 MVT::isInteger(LL.getValueType())) {
1197 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1198 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1199 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1200 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1201 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1202 AddToWorkList(ORNode.Val);
1203 return DAG.getSetCC(VT, ORNode, LR, Op1);
1205 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1206 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1207 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1208 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1209 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1210 AddToWorkList(ANDNode.Val);
1211 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1214 // canonicalize equivalent to ll == rl
1215 if (LL == RR && LR == RL) {
1216 Op1 = ISD::getSetCCSwappedOperands(Op1);
1219 if (LL == RL && LR == RR) {
1220 bool isInteger = MVT::isInteger(LL.getValueType());
1221 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1222 if (Result != ISD::SETCC_INVALID)
1223 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1227 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1228 if (N0.getOpcode() == N1.getOpcode()) {
1229 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1230 if (Tmp.Val) return Tmp;
1233 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1234 if (N0.getOpcode() == ISD::AND &&
1235 N1.getOpcode() == ISD::AND &&
1236 N0.getOperand(1).getOpcode() == ISD::Constant &&
1237 N1.getOperand(1).getOpcode() == ISD::Constant &&
1238 // Don't increase # computations.
1239 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1240 // We can only do this xform if we know that bits from X that are set in C2
1241 // but not in C1 are already zero. Likewise for Y.
1242 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1243 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1245 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1246 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1247 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1248 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1253 // See if this is some rotate idiom.
1254 if (SDNode *Rot = MatchRotate(N0, N1))
1255 return SDOperand(Rot, 0);
1261 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1262 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1263 if (Op.getOpcode() == ISD::AND) {
1264 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1265 Mask = Op.getOperand(1);
1266 Op = Op.getOperand(0);
1272 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1280 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1281 // idioms for rotate, and if the target supports rotation instructions, generate
1283 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1284 // Must be a legal type. Expanded an promoted things won't work with rotates.
1285 MVT::ValueType VT = LHS.getValueType();
1286 if (!TLI.isTypeLegal(VT)) return 0;
1288 // The target must have at least one rotate flavor.
1289 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1290 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1291 if (!HasROTL && !HasROTR) return 0;
1293 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1294 SDOperand LHSShift; // The shift.
1295 SDOperand LHSMask; // AND value if any.
1296 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1297 return 0; // Not part of a rotate.
1299 SDOperand RHSShift; // The shift.
1300 SDOperand RHSMask; // AND value if any.
1301 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1302 return 0; // Not part of a rotate.
1304 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1305 return 0; // Not shifting the same value.
1307 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1308 return 0; // Shifts must disagree.
1310 // Canonicalize shl to left side in a shl/srl pair.
1311 if (RHSShift.getOpcode() == ISD::SHL) {
1312 std::swap(LHS, RHS);
1313 std::swap(LHSShift, RHSShift);
1314 std::swap(LHSMask , RHSMask );
1317 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1319 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1320 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1321 if (LHSShift.getOperand(1).getOpcode() == ISD::Constant &&
1322 RHSShift.getOperand(1).getOpcode() == ISD::Constant) {
1323 uint64_t LShVal = cast<ConstantSDNode>(LHSShift.getOperand(1))->getValue();
1324 uint64_t RShVal = cast<ConstantSDNode>(RHSShift.getOperand(1))->getValue();
1325 if ((LShVal + RShVal) != OpSizeInBits)
1330 Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1331 LHSShift.getOperand(1));
1333 Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1334 RHSShift.getOperand(1));
1336 // If there is an AND of either shifted operand, apply it to the result.
1337 if (LHSMask.Val || RHSMask.Val) {
1338 uint64_t Mask = MVT::getIntVTBitMask(VT);
1341 uint64_t RHSBits = (1ULL << LShVal)-1;
1342 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1345 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1346 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1349 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1355 // If there is a mask here, and we have a variable shift, we can't be sure
1356 // that we're masking out the right stuff.
1357 if (LHSMask.Val || RHSMask.Val)
1360 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1361 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1362 if (RHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1363 LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) {
1364 if (ConstantSDNode *SUBC =
1365 dyn_cast<ConstantSDNode>(RHSShift.getOperand(1).getOperand(0))) {
1366 if (SUBC->getValue() == OpSizeInBits)
1368 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1369 LHSShift.getOperand(1)).Val;
1371 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1372 LHSShift.getOperand(1)).Val;
1376 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1377 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1378 if (LHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1379 RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) {
1380 if (ConstantSDNode *SUBC =
1381 dyn_cast<ConstantSDNode>(LHSShift.getOperand(1).getOperand(0))) {
1382 if (SUBC->getValue() == OpSizeInBits)
1384 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1385 LHSShift.getOperand(1)).Val;
1387 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1388 RHSShift.getOperand(1)).Val;
1396 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1397 SDOperand N0 = N->getOperand(0);
1398 SDOperand N1 = N->getOperand(1);
1399 SDOperand LHS, RHS, CC;
1400 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1401 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1402 MVT::ValueType VT = N0.getValueType();
1404 // fold (xor c1, c2) -> c1^c2
1406 return DAG.getNode(ISD::XOR, VT, N0, N1);
1407 // canonicalize constant to RHS
1409 return DAG.getNode(ISD::XOR, VT, N1, N0);
1410 // fold (xor x, 0) -> x
1411 if (N1C && N1C->isNullValue())
1414 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1417 // fold !(x cc y) -> (x !cc y)
1418 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1419 bool isInt = MVT::isInteger(LHS.getValueType());
1420 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1422 if (N0.getOpcode() == ISD::SETCC)
1423 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1424 if (N0.getOpcode() == ISD::SELECT_CC)
1425 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1426 assert(0 && "Unhandled SetCC Equivalent!");
1429 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1430 if (N1C && N1C->getValue() == 1 &&
1431 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1432 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1433 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1434 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1435 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1436 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1437 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1438 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1441 // fold !(x or y) -> (!x and !y) iff x or y are constants
1442 if (N1C && N1C->isAllOnesValue() &&
1443 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1444 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1445 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1446 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1447 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1448 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1449 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1450 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1453 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1454 if (N1C && N0.getOpcode() == ISD::XOR) {
1455 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1456 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1458 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1459 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1461 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1462 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1464 // fold (xor x, x) -> 0
1466 if (!MVT::isVector(VT)) {
1467 return DAG.getConstant(0, VT);
1468 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1469 // Produce a vector of zeros.
1470 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
1471 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
1472 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1476 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
1477 if (N0.getOpcode() == N1.getOpcode()) {
1478 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1479 if (Tmp.Val) return Tmp;
1482 // Simplify the expression using non-local knowledge.
1483 if (!MVT::isVector(VT) &&
1484 SimplifyDemandedBits(SDOperand(N, 0)))
1485 return SDOperand(N, 0);
1490 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1491 SDOperand N0 = N->getOperand(0);
1492 SDOperand N1 = N->getOperand(1);
1493 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1494 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1495 MVT::ValueType VT = N0.getValueType();
1496 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1498 // fold (shl c1, c2) -> c1<<c2
1500 return DAG.getNode(ISD::SHL, VT, N0, N1);
1501 // fold (shl 0, x) -> 0
1502 if (N0C && N0C->isNullValue())
1504 // fold (shl x, c >= size(x)) -> undef
1505 if (N1C && N1C->getValue() >= OpSizeInBits)
1506 return DAG.getNode(ISD::UNDEF, VT);
1507 // fold (shl x, 0) -> x
1508 if (N1C && N1C->isNullValue())
1510 // if (shl x, c) is known to be zero, return 0
1511 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1512 return DAG.getConstant(0, VT);
1513 if (SimplifyDemandedBits(SDOperand(N, 0)))
1514 return SDOperand(N, 0);
1515 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1516 if (N1C && N0.getOpcode() == ISD::SHL &&
1517 N0.getOperand(1).getOpcode() == ISD::Constant) {
1518 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1519 uint64_t c2 = N1C->getValue();
1520 if (c1 + c2 > OpSizeInBits)
1521 return DAG.getConstant(0, VT);
1522 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1523 DAG.getConstant(c1 + c2, N1.getValueType()));
1525 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1526 // (srl (and x, -1 << c1), c1-c2)
1527 if (N1C && N0.getOpcode() == ISD::SRL &&
1528 N0.getOperand(1).getOpcode() == ISD::Constant) {
1529 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1530 uint64_t c2 = N1C->getValue();
1531 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1532 DAG.getConstant(~0ULL << c1, VT));
1534 return DAG.getNode(ISD::SHL, VT, Mask,
1535 DAG.getConstant(c2-c1, N1.getValueType()));
1537 return DAG.getNode(ISD::SRL, VT, Mask,
1538 DAG.getConstant(c1-c2, N1.getValueType()));
1540 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1541 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1542 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1543 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1544 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
1545 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1546 isa<ConstantSDNode>(N0.getOperand(1))) {
1547 return DAG.getNode(ISD::ADD, VT,
1548 DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1),
1549 DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1));
1554 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1555 SDOperand N0 = N->getOperand(0);
1556 SDOperand N1 = N->getOperand(1);
1557 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1558 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1559 MVT::ValueType VT = N0.getValueType();
1561 // fold (sra c1, c2) -> c1>>c2
1563 return DAG.getNode(ISD::SRA, VT, N0, N1);
1564 // fold (sra 0, x) -> 0
1565 if (N0C && N0C->isNullValue())
1567 // fold (sra -1, x) -> -1
1568 if (N0C && N0C->isAllOnesValue())
1570 // fold (sra x, c >= size(x)) -> undef
1571 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
1572 return DAG.getNode(ISD::UNDEF, VT);
1573 // fold (sra x, 0) -> x
1574 if (N1C && N1C->isNullValue())
1576 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
1578 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
1579 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
1582 default: EVT = MVT::Other; break;
1583 case 1: EVT = MVT::i1; break;
1584 case 8: EVT = MVT::i8; break;
1585 case 16: EVT = MVT::i16; break;
1586 case 32: EVT = MVT::i32; break;
1588 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
1589 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1590 DAG.getValueType(EVT));
1593 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
1594 if (N1C && N0.getOpcode() == ISD::SRA) {
1595 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1596 unsigned Sum = N1C->getValue() + C1->getValue();
1597 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
1598 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
1599 DAG.getConstant(Sum, N1C->getValueType(0)));
1603 // Simplify, based on bits shifted out of the LHS.
1604 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
1605 return SDOperand(N, 0);
1608 // If the sign bit is known to be zero, switch this to a SRL.
1609 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
1610 return DAG.getNode(ISD::SRL, VT, N0, N1);
1614 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1615 SDOperand N0 = N->getOperand(0);
1616 SDOperand N1 = N->getOperand(1);
1617 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1618 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1619 MVT::ValueType VT = N0.getValueType();
1620 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1622 // fold (srl c1, c2) -> c1 >>u c2
1624 return DAG.getNode(ISD::SRL, VT, N0, N1);
1625 // fold (srl 0, x) -> 0
1626 if (N0C && N0C->isNullValue())
1628 // fold (srl x, c >= size(x)) -> undef
1629 if (N1C && N1C->getValue() >= OpSizeInBits)
1630 return DAG.getNode(ISD::UNDEF, VT);
1631 // fold (srl x, 0) -> x
1632 if (N1C && N1C->isNullValue())
1634 // if (srl x, c) is known to be zero, return 0
1635 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1636 return DAG.getConstant(0, VT);
1637 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1638 if (N1C && N0.getOpcode() == ISD::SRL &&
1639 N0.getOperand(1).getOpcode() == ISD::Constant) {
1640 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1641 uint64_t c2 = N1C->getValue();
1642 if (c1 + c2 > OpSizeInBits)
1643 return DAG.getConstant(0, VT);
1644 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1645 DAG.getConstant(c1 + c2, N1.getValueType()));
1648 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
1649 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1650 // Shifting in all undef bits?
1651 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
1652 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
1653 return DAG.getNode(ISD::UNDEF, VT);
1655 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
1656 AddToWorkList(SmallShift.Val);
1657 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
1660 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
1661 if (N1C && N0.getOpcode() == ISD::CTLZ &&
1662 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
1663 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
1664 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
1666 // If any of the input bits are KnownOne, then the input couldn't be all
1667 // zeros, thus the result of the srl will always be zero.
1668 if (KnownOne) return DAG.getConstant(0, VT);
1670 // If all of the bits input the to ctlz node are known to be zero, then
1671 // the result of the ctlz is "32" and the result of the shift is one.
1672 uint64_t UnknownBits = ~KnownZero & Mask;
1673 if (UnknownBits == 0) return DAG.getConstant(1, VT);
1675 // Otherwise, check to see if there is exactly one bit input to the ctlz.
1676 if ((UnknownBits & (UnknownBits-1)) == 0) {
1677 // Okay, we know that only that the single bit specified by UnknownBits
1678 // could be set on input to the CTLZ node. If this bit is set, the SRL
1679 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
1680 // to an SRL,XOR pair, which is likely to simplify more.
1681 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
1682 SDOperand Op = N0.getOperand(0);
1684 Op = DAG.getNode(ISD::SRL, VT, Op,
1685 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
1686 AddToWorkList(Op.Val);
1688 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
1695 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1696 SDOperand N0 = N->getOperand(0);
1697 MVT::ValueType VT = N->getValueType(0);
1699 // fold (ctlz c1) -> c2
1700 if (isa<ConstantSDNode>(N0))
1701 return DAG.getNode(ISD::CTLZ, VT, N0);
1705 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1706 SDOperand N0 = N->getOperand(0);
1707 MVT::ValueType VT = N->getValueType(0);
1709 // fold (cttz c1) -> c2
1710 if (isa<ConstantSDNode>(N0))
1711 return DAG.getNode(ISD::CTTZ, VT, N0);
1715 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1716 SDOperand N0 = N->getOperand(0);
1717 MVT::ValueType VT = N->getValueType(0);
1719 // fold (ctpop c1) -> c2
1720 if (isa<ConstantSDNode>(N0))
1721 return DAG.getNode(ISD::CTPOP, VT, N0);
1725 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1726 SDOperand N0 = N->getOperand(0);
1727 SDOperand N1 = N->getOperand(1);
1728 SDOperand N2 = N->getOperand(2);
1729 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1730 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1731 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1732 MVT::ValueType VT = N->getValueType(0);
1734 // fold select C, X, X -> X
1737 // fold select true, X, Y -> X
1738 if (N0C && !N0C->isNullValue())
1740 // fold select false, X, Y -> Y
1741 if (N0C && N0C->isNullValue())
1743 // fold select C, 1, X -> C | X
1744 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1745 return DAG.getNode(ISD::OR, VT, N0, N2);
1746 // fold select C, 0, X -> ~C & X
1747 // FIXME: this should check for C type == X type, not i1?
1748 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1749 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1750 AddToWorkList(XORNode.Val);
1751 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1753 // fold select C, X, 1 -> ~C | X
1754 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1755 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1756 AddToWorkList(XORNode.Val);
1757 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1759 // fold select C, X, 0 -> C & X
1760 // FIXME: this should check for C type == X type, not i1?
1761 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1762 return DAG.getNode(ISD::AND, VT, N0, N1);
1763 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1764 if (MVT::i1 == VT && N0 == N1)
1765 return DAG.getNode(ISD::OR, VT, N0, N2);
1766 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1767 if (MVT::i1 == VT && N0 == N2)
1768 return DAG.getNode(ISD::AND, VT, N0, N1);
1770 // If we can fold this based on the true/false value, do so.
1771 if (SimplifySelectOps(N, N1, N2))
1772 return SDOperand(N, 0); // Don't revisit N.
1774 // fold selects based on a setcc into other things, such as min/max/abs
1775 if (N0.getOpcode() == ISD::SETCC)
1777 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1778 // having to say they don't support SELECT_CC on every type the DAG knows
1779 // about, since there is no way to mark an opcode illegal at all value types
1780 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1781 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1782 N1, N2, N0.getOperand(2));
1784 return SimplifySelect(N0, N1, N2);
1788 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1789 SDOperand N0 = N->getOperand(0);
1790 SDOperand N1 = N->getOperand(1);
1791 SDOperand N2 = N->getOperand(2);
1792 SDOperand N3 = N->getOperand(3);
1793 SDOperand N4 = N->getOperand(4);
1794 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1795 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1796 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1797 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1799 // fold select_cc lhs, rhs, x, x, cc -> x
1803 // Determine if the condition we're dealing with is constant
1804 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1806 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
1807 if (SCCC->getValue())
1808 return N2; // cond always true -> true val
1810 return N3; // cond always false -> false val
1813 // Fold to a simpler select_cc
1814 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
1815 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
1816 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
1819 // If we can fold this based on the true/false value, do so.
1820 if (SimplifySelectOps(N, N2, N3))
1821 return SDOperand(N, 0); // Don't revisit N.
1823 // fold select_cc into other things, such as min/max/abs
1824 return SimplifySelectCC(N0, N1, N2, N3, CC);
1827 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1828 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1829 cast<CondCodeSDNode>(N->getOperand(2))->get());
1832 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1833 SDOperand N0 = N->getOperand(0);
1834 MVT::ValueType VT = N->getValueType(0);
1836 // fold (sext c1) -> c1
1837 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
1838 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
1840 // fold (sext (sext x)) -> (sext x)
1841 // fold (sext (aext x)) -> (sext x)
1842 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1843 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1845 // fold (sext (truncate x)) -> (sextinreg x).
1846 if (N0.getOpcode() == ISD::TRUNCATE &&
1847 (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
1848 N0.getValueType()))) {
1849 SDOperand Op = N0.getOperand(0);
1850 if (Op.getValueType() < VT) {
1851 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
1852 } else if (Op.getValueType() > VT) {
1853 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
1855 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
1856 DAG.getValueType(N0.getValueType()));
1859 // fold (sext (load x)) -> (sext (truncate (sextload x)))
1860 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
1861 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
1862 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1863 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
1864 LN0->getBasePtr(), LN0->getSrcValue(),
1865 LN0->getSrcValueOffset(),
1867 CombineTo(N, ExtLoad);
1868 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1869 ExtLoad.getValue(1));
1870 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1873 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
1874 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
1875 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
1876 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1877 MVT::ValueType EVT = LN0->getLoadedVT();
1878 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
1879 LN0->getBasePtr(), LN0->getSrcValue(),
1880 LN0->getSrcValueOffset(), EVT);
1881 CombineTo(N, ExtLoad);
1882 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1883 ExtLoad.getValue(1));
1884 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1890 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1891 SDOperand N0 = N->getOperand(0);
1892 MVT::ValueType VT = N->getValueType(0);
1894 // fold (zext c1) -> c1
1895 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
1896 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1897 // fold (zext (zext x)) -> (zext x)
1898 // fold (zext (aext x)) -> (zext x)
1899 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1900 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1902 // fold (zext (truncate x)) -> (and x, mask)
1903 if (N0.getOpcode() == ISD::TRUNCATE &&
1904 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
1905 SDOperand Op = N0.getOperand(0);
1906 if (Op.getValueType() < VT) {
1907 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
1908 } else if (Op.getValueType() > VT) {
1909 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
1911 return DAG.getZeroExtendInReg(Op, N0.getValueType());
1914 // fold (zext (and (trunc x), cst)) -> (and x, cst).
1915 if (N0.getOpcode() == ISD::AND &&
1916 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
1917 N0.getOperand(1).getOpcode() == ISD::Constant) {
1918 SDOperand X = N0.getOperand(0).getOperand(0);
1919 if (X.getValueType() < VT) {
1920 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
1921 } else if (X.getValueType() > VT) {
1922 X = DAG.getNode(ISD::TRUNCATE, VT, X);
1924 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1925 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
1928 // fold (zext (load x)) -> (zext (truncate (zextload x)))
1929 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
1930 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
1931 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1932 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1933 LN0->getBasePtr(), LN0->getSrcValue(),
1934 LN0->getSrcValueOffset(),
1936 CombineTo(N, ExtLoad);
1937 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1938 ExtLoad.getValue(1));
1939 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1942 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
1943 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
1944 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
1945 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1946 MVT::ValueType EVT = LN0->getLoadedVT();
1947 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1948 LN0->getBasePtr(), LN0->getSrcValue(),
1949 LN0->getSrcValueOffset(), EVT);
1950 CombineTo(N, ExtLoad);
1951 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1952 ExtLoad.getValue(1));
1953 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1958 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
1959 SDOperand N0 = N->getOperand(0);
1960 MVT::ValueType VT = N->getValueType(0);
1962 // fold (aext c1) -> c1
1963 if (isa<ConstantSDNode>(N0))
1964 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
1965 // fold (aext (aext x)) -> (aext x)
1966 // fold (aext (zext x)) -> (zext x)
1967 // fold (aext (sext x)) -> (sext x)
1968 if (N0.getOpcode() == ISD::ANY_EXTEND ||
1969 N0.getOpcode() == ISD::ZERO_EXTEND ||
1970 N0.getOpcode() == ISD::SIGN_EXTEND)
1971 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
1973 // fold (aext (truncate x))
1974 if (N0.getOpcode() == ISD::TRUNCATE) {
1975 SDOperand TruncOp = N0.getOperand(0);
1976 if (TruncOp.getValueType() == VT)
1977 return TruncOp; // x iff x size == zext size.
1978 if (TruncOp.getValueType() > VT)
1979 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
1980 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
1983 // fold (aext (and (trunc x), cst)) -> (and x, cst).
1984 if (N0.getOpcode() == ISD::AND &&
1985 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
1986 N0.getOperand(1).getOpcode() == ISD::Constant) {
1987 SDOperand X = N0.getOperand(0).getOperand(0);
1988 if (X.getValueType() < VT) {
1989 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
1990 } else if (X.getValueType() > VT) {
1991 X = DAG.getNode(ISD::TRUNCATE, VT, X);
1993 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1994 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
1997 // fold (aext (load x)) -> (aext (truncate (extload x)))
1998 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
1999 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2000 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2001 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2002 LN0->getBasePtr(), LN0->getSrcValue(),
2003 LN0->getSrcValueOffset(),
2005 CombineTo(N, ExtLoad);
2006 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2007 ExtLoad.getValue(1));
2008 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2011 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2012 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2013 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2014 if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.Val) &&
2016 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2017 MVT::ValueType EVT = LN0->getLoadedVT();
2018 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2019 LN0->getChain(), LN0->getBasePtr(),
2021 LN0->getSrcValueOffset(), EVT);
2022 CombineTo(N, ExtLoad);
2023 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2024 ExtLoad.getValue(1));
2025 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2031 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
2032 SDOperand N0 = N->getOperand(0);
2033 SDOperand N1 = N->getOperand(1);
2034 MVT::ValueType VT = N->getValueType(0);
2035 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
2036 unsigned EVTBits = MVT::getSizeInBits(EVT);
2038 // fold (sext_in_reg c1) -> c1
2039 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
2040 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
2042 // If the input is already sign extended, just drop the extension.
2043 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
2046 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
2047 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2048 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
2049 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
2052 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
2053 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
2054 return DAG.getZeroExtendInReg(N0, EVT);
2056 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
2057 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
2058 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
2059 if (N0.getOpcode() == ISD::SRL) {
2060 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2061 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
2062 // We can turn this into an SRA iff the input to the SRL is already sign
2064 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0));
2065 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
2066 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
2070 // fold (sext_inreg (extload x)) -> (sextload x)
2071 if (ISD::isEXTLoad(N0.Val) &&
2072 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2073 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2074 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2075 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2076 LN0->getBasePtr(), LN0->getSrcValue(),
2077 LN0->getSrcValueOffset(), EVT);
2078 CombineTo(N, ExtLoad);
2079 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2080 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2082 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
2083 if (ISD::isZEXTLoad(N0.Val) && N0.hasOneUse() &&
2084 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2085 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2086 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2087 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2088 LN0->getBasePtr(), LN0->getSrcValue(),
2089 LN0->getSrcValueOffset(), EVT);
2090 CombineTo(N, ExtLoad);
2091 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2092 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2097 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
2098 SDOperand N0 = N->getOperand(0);
2099 MVT::ValueType VT = N->getValueType(0);
2102 if (N0.getValueType() == N->getValueType(0))
2104 // fold (truncate c1) -> c1
2105 if (isa<ConstantSDNode>(N0))
2106 return DAG.getNode(ISD::TRUNCATE, VT, N0);
2107 // fold (truncate (truncate x)) -> (truncate x)
2108 if (N0.getOpcode() == ISD::TRUNCATE)
2109 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2110 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
2111 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
2112 N0.getOpcode() == ISD::ANY_EXTEND) {
2113 if (N0.getValueType() < VT)
2114 // if the source is smaller than the dest, we still need an extend
2115 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2116 else if (N0.getValueType() > VT)
2117 // if the source is larger than the dest, than we just need the truncate
2118 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2120 // if the source and dest are the same type, we can drop both the extend
2122 return N0.getOperand(0);
2124 // fold (truncate (load x)) -> (smaller load x)
2125 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) {
2126 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
2127 "Cannot truncate to larger type!");
2128 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2129 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2130 // For big endian targets, we need to add an offset to the pointer to load
2131 // the correct bytes. For little endian systems, we merely need to read
2132 // fewer bytes from the same pointer.
2134 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
2135 SDOperand NewPtr = TLI.isLittleEndian() ? LN0->getBasePtr() :
2136 DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
2137 DAG.getConstant(PtrOff, PtrType));
2138 AddToWorkList(NewPtr.Val);
2139 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), NewPtr,
2140 LN0->getSrcValue(), LN0->getSrcValueOffset());
2142 CombineTo(N0.Val, Load, Load.getValue(1));
2143 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2148 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
2149 SDOperand N0 = N->getOperand(0);
2150 MVT::ValueType VT = N->getValueType(0);
2152 // If the input is a constant, let getNode() fold it.
2153 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
2154 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2155 if (Res.Val != N) return Res;
2158 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
2159 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
2161 // fold (conv (load x)) -> (load (conv*)x)
2162 // FIXME: These xforms need to know that the resultant load doesn't need a
2163 // higher alignment than the original!
2164 if (0 && ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) {
2165 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2166 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
2167 LN0->getSrcValue(), LN0->getSrcValueOffset());
2169 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
2177 SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) {
2178 SDOperand N0 = N->getOperand(0);
2179 MVT::ValueType VT = N->getValueType(0);
2181 // If the input is a VBUILD_VECTOR with all constant elements, fold this now.
2182 // First check to see if this is all constant.
2183 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() &&
2184 VT == MVT::Vector) {
2185 bool isSimple = true;
2186 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i)
2187 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
2188 N0.getOperand(i).getOpcode() != ISD::Constant &&
2189 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
2194 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT();
2195 if (isSimple && !MVT::isVector(DestEltVT)) {
2196 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT);
2203 /// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector
2204 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
2205 /// destination element value type.
2206 SDOperand DAGCombiner::
2207 ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
2208 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
2210 // If this is already the right type, we're done.
2211 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
2213 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
2214 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
2216 // If this is a conversion of N elements of one type to N elements of another
2217 // type, convert each element. This handles FP<->INT cases.
2218 if (SrcBitSize == DstBitSize) {
2219 SmallVector<SDOperand, 8> Ops;
2220 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2221 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
2222 AddToWorkList(Ops.back().Val);
2224 Ops.push_back(*(BV->op_end()-2)); // Add num elements.
2225 Ops.push_back(DAG.getValueType(DstEltVT));
2226 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2229 // Otherwise, we're growing or shrinking the elements. To avoid having to
2230 // handle annoying details of growing/shrinking FP values, we convert them to
2232 if (MVT::isFloatingPoint(SrcEltVT)) {
2233 // Convert the input float vector to a int vector where the elements are the
2235 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
2236 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2237 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val;
2241 // Now we know the input is an integer vector. If the output is a FP type,
2242 // convert to integer first, then to FP of the right size.
2243 if (MVT::isFloatingPoint(DstEltVT)) {
2244 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
2245 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2246 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val;
2248 // Next, convert to FP elements of the same size.
2249 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT);
2252 // Okay, we know the src/dst types are both integers of differing types.
2253 // Handling growing first.
2254 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
2255 if (SrcBitSize < DstBitSize) {
2256 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
2258 SmallVector<SDOperand, 8> Ops;
2259 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e;
2260 i += NumInputsPerOutput) {
2261 bool isLE = TLI.isLittleEndian();
2262 uint64_t NewBits = 0;
2263 bool EltIsUndef = true;
2264 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
2265 // Shift the previously computed bits over.
2266 NewBits <<= SrcBitSize;
2267 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
2268 if (Op.getOpcode() == ISD::UNDEF) continue;
2271 NewBits |= cast<ConstantSDNode>(Op)->getValue();
2275 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2277 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
2280 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2281 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2282 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2285 // Finally, this must be the case where we are shrinking elements: each input
2286 // turns into multiple outputs.
2287 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
2288 SmallVector<SDOperand, 8> Ops;
2289 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2290 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
2291 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
2292 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2295 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
2297 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
2298 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
2299 OpVal >>= DstBitSize;
2300 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
2303 // For big endian targets, swap the order of the pieces of each element.
2304 if (!TLI.isLittleEndian())
2305 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
2307 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2308 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2309 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2314 SDOperand DAGCombiner::visitFADD(SDNode *N) {
2315 SDOperand N0 = N->getOperand(0);
2316 SDOperand N1 = N->getOperand(1);
2317 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2318 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2319 MVT::ValueType VT = N->getValueType(0);
2321 // fold (fadd c1, c2) -> c1+c2
2323 return DAG.getNode(ISD::FADD, VT, N0, N1);
2324 // canonicalize constant to RHS
2325 if (N0CFP && !N1CFP)
2326 return DAG.getNode(ISD::FADD, VT, N1, N0);
2327 // fold (A + (-B)) -> A-B
2328 if (N1.getOpcode() == ISD::FNEG)
2329 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
2330 // fold ((-A) + B) -> B-A
2331 if (N0.getOpcode() == ISD::FNEG)
2332 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
2336 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
2337 SDOperand N0 = N->getOperand(0);
2338 SDOperand N1 = N->getOperand(1);
2339 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2340 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2341 MVT::ValueType VT = N->getValueType(0);
2343 // fold (fsub c1, c2) -> c1-c2
2345 return DAG.getNode(ISD::FSUB, VT, N0, N1);
2346 // fold (A-(-B)) -> A+B
2347 if (N1.getOpcode() == ISD::FNEG)
2348 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
2352 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
2353 SDOperand N0 = N->getOperand(0);
2354 SDOperand N1 = N->getOperand(1);
2355 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2356 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2357 MVT::ValueType VT = N->getValueType(0);
2359 // fold (fmul c1, c2) -> c1*c2
2361 return DAG.getNode(ISD::FMUL, VT, N0, N1);
2362 // canonicalize constant to RHS
2363 if (N0CFP && !N1CFP)
2364 return DAG.getNode(ISD::FMUL, VT, N1, N0);
2365 // fold (fmul X, 2.0) -> (fadd X, X)
2366 if (N1CFP && N1CFP->isExactlyValue(+2.0))
2367 return DAG.getNode(ISD::FADD, VT, N0, N0);
2371 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
2372 SDOperand N0 = N->getOperand(0);
2373 SDOperand N1 = N->getOperand(1);
2374 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2375 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2376 MVT::ValueType VT = N->getValueType(0);
2378 // fold (fdiv c1, c2) -> c1/c2
2380 return DAG.getNode(ISD::FDIV, VT, N0, N1);
2384 SDOperand DAGCombiner::visitFREM(SDNode *N) {
2385 SDOperand N0 = N->getOperand(0);
2386 SDOperand N1 = N->getOperand(1);
2387 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2388 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2389 MVT::ValueType VT = N->getValueType(0);
2391 // fold (frem c1, c2) -> fmod(c1,c2)
2393 return DAG.getNode(ISD::FREM, VT, N0, N1);
2397 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
2398 SDOperand N0 = N->getOperand(0);
2399 SDOperand N1 = N->getOperand(1);
2400 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2401 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2402 MVT::ValueType VT = N->getValueType(0);
2404 if (N0CFP && N1CFP) // Constant fold
2405 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
2408 // copysign(x, c1) -> fabs(x) iff ispos(c1)
2409 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
2414 u.d = N1CFP->getValue();
2416 return DAG.getNode(ISD::FABS, VT, N0);
2418 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
2421 // copysign(fabs(x), y) -> copysign(x, y)
2422 // copysign(fneg(x), y) -> copysign(x, y)
2423 // copysign(copysign(x,z), y) -> copysign(x, y)
2424 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
2425 N0.getOpcode() == ISD::FCOPYSIGN)
2426 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
2428 // copysign(x, abs(y)) -> abs(x)
2429 if (N1.getOpcode() == ISD::FABS)
2430 return DAG.getNode(ISD::FABS, VT, N0);
2432 // copysign(x, copysign(y,z)) -> copysign(x, z)
2433 if (N1.getOpcode() == ISD::FCOPYSIGN)
2434 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
2436 // copysign(x, fp_extend(y)) -> copysign(x, y)
2437 // copysign(x, fp_round(y)) -> copysign(x, y)
2438 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
2439 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
2446 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
2447 SDOperand N0 = N->getOperand(0);
2448 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2449 MVT::ValueType VT = N->getValueType(0);
2451 // fold (sint_to_fp c1) -> c1fp
2453 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
2457 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
2458 SDOperand N0 = N->getOperand(0);
2459 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2460 MVT::ValueType VT = N->getValueType(0);
2462 // fold (uint_to_fp c1) -> c1fp
2464 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
2468 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
2469 SDOperand N0 = N->getOperand(0);
2470 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2471 MVT::ValueType VT = N->getValueType(0);
2473 // fold (fp_to_sint c1fp) -> c1
2475 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
2479 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
2480 SDOperand N0 = N->getOperand(0);
2481 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2482 MVT::ValueType VT = N->getValueType(0);
2484 // fold (fp_to_uint c1fp) -> c1
2486 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
2490 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
2491 SDOperand N0 = N->getOperand(0);
2492 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2493 MVT::ValueType VT = N->getValueType(0);
2495 // fold (fp_round c1fp) -> c1fp
2497 return DAG.getNode(ISD::FP_ROUND, VT, N0);
2499 // fold (fp_round (fp_extend x)) -> x
2500 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
2501 return N0.getOperand(0);
2503 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
2504 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
2505 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
2506 AddToWorkList(Tmp.Val);
2507 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
2513 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
2514 SDOperand N0 = N->getOperand(0);
2515 MVT::ValueType VT = N->getValueType(0);
2516 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2517 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2519 // fold (fp_round_inreg c1fp) -> c1fp
2521 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
2522 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
2527 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
2528 SDOperand N0 = N->getOperand(0);
2529 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2530 MVT::ValueType VT = N->getValueType(0);
2532 // fold (fp_extend c1fp) -> c1fp
2534 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
2536 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
2537 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2538 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2539 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2540 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2541 LN0->getBasePtr(), LN0->getSrcValue(),
2542 LN0->getSrcValueOffset(),
2544 CombineTo(N, ExtLoad);
2545 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
2546 ExtLoad.getValue(1));
2547 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2554 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
2555 SDOperand N0 = N->getOperand(0);
2556 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2557 MVT::ValueType VT = N->getValueType(0);
2559 // fold (fneg c1) -> -c1
2561 return DAG.getNode(ISD::FNEG, VT, N0);
2562 // fold (fneg (sub x, y)) -> (sub y, x)
2563 if (N0.getOpcode() == ISD::SUB)
2564 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0));
2565 // fold (fneg (fneg x)) -> x
2566 if (N0.getOpcode() == ISD::FNEG)
2567 return N0.getOperand(0);
2571 SDOperand DAGCombiner::visitFABS(SDNode *N) {
2572 SDOperand N0 = N->getOperand(0);
2573 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2574 MVT::ValueType VT = N->getValueType(0);
2576 // fold (fabs c1) -> fabs(c1)
2578 return DAG.getNode(ISD::FABS, VT, N0);
2579 // fold (fabs (fabs x)) -> (fabs x)
2580 if (N0.getOpcode() == ISD::FABS)
2581 return N->getOperand(0);
2582 // fold (fabs (fneg x)) -> (fabs x)
2583 // fold (fabs (fcopysign x, y)) -> (fabs x)
2584 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
2585 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
2590 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
2591 SDOperand Chain = N->getOperand(0);
2592 SDOperand N1 = N->getOperand(1);
2593 SDOperand N2 = N->getOperand(2);
2594 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2596 // never taken branch, fold to chain
2597 if (N1C && N1C->isNullValue())
2599 // unconditional branch
2600 if (N1C && N1C->getValue() == 1)
2601 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2602 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
2604 if (N1.getOpcode() == ISD::SETCC &&
2605 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
2606 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
2607 N1.getOperand(0), N1.getOperand(1), N2);
2612 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
2614 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
2615 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2616 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2618 // Use SimplifySetCC to simplify SETCC's.
2619 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2620 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2622 // fold br_cc true, dest -> br dest (unconditional branch)
2623 if (SCCC && SCCC->getValue())
2624 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2626 // fold br_cc false, dest -> unconditional fall through
2627 if (SCCC && SCCC->isNullValue())
2628 return N->getOperand(0);
2629 // fold to a simpler setcc
2630 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2631 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2632 Simp.getOperand(2), Simp.getOperand(0),
2633 Simp.getOperand(1), N->getOperand(4));
2637 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
2638 LoadSDNode *LD = cast<LoadSDNode>(N);
2639 SDOperand Chain = LD->getChain();
2640 SDOperand Ptr = LD->getBasePtr();
2642 // If there are no uses of the loaded value, change uses of the chain value
2643 // into uses of the chain input (i.e. delete the dead load).
2644 if (N->hasNUsesOfValue(0, 0))
2645 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
2647 if (!ISD::isNON_EXTLoad(N))
2650 // If this load is directly stored, replace the load value with the stored
2652 // TODO: Handle store large -> read small portion.
2653 // TODO: Handle TRUNCSTORE/EXTLOAD
2654 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2655 Chain.getOperand(1).getValueType() == N->getValueType(0))
2656 return CombineTo(N, Chain.getOperand(1), Chain);
2659 // Walk up chain skipping non-aliasing memory nodes.
2660 SDOperand BetterChain = FindBetterChain(N, Chain);
2662 // If there is a better chain.
2663 if (Chain != BetterChain) {
2664 // Replace the chain to void dependency.
2665 SDOperand ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
2666 LD->getSrcValue(), LD->getSrcValueOffset());
2668 // Create token factor to keep old chain connected.
2669 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
2670 Chain, ReplLoad.getValue(1));
2672 // Replace uses with load result and token factor.
2673 return CombineTo(N, ReplLoad.getValue(0), Token);
2680 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
2681 SDOperand Chain = N->getOperand(0);
2682 SDOperand Value = N->getOperand(1);
2683 SDOperand Ptr = N->getOperand(2);
2684 SDOperand SrcValue = N->getOperand(3);
2686 // If this is a store that kills a previous store, remove the previous store.
2687 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2688 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ &&
2689 // Make sure that these stores are the same value type:
2690 // FIXME: we really care that the second store is >= size of the first.
2691 Value.getValueType() == Chain.getOperand(1).getValueType()) {
2692 // Create a new store of Value that replaces both stores.
2693 SDNode *PrevStore = Chain.Val;
2694 if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
2696 SDOperand NewStore = DAG.getStore(PrevStore->getOperand(0), Value, Ptr,
2698 CombineTo(N, NewStore); // Nuke this store.
2699 CombineTo(PrevStore, NewStore); // Nuke the previous store.
2700 return SDOperand(N, 0);
2703 // If this is a store of a bit convert, store the input value.
2704 // FIXME: This needs to know that the resultant store does not need a
2705 // higher alignment than the original.
2706 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) {
2707 return DAG.getStore(Chain, Value.getOperand(0), Ptr, SrcValue);
2711 // If the store ptr is a frame index and the frame index has a use of one
2712 // and this is a return block, then the store is redundant.
2713 if (Ptr.hasOneUse() && isa<FrameIndexSDNode>(Ptr) &&
2714 DAG.getRoot().getOpcode() == ISD::RET) {
2718 // Walk up chain skipping non-aliasing memory nodes.
2719 SDOperand BetterChain = FindBetterChain(N, Chain);
2721 // If there is a better chain.
2722 if (Chain != BetterChain) {
2723 // Replace the chain to avoid dependency.
2724 SDOperand ReplStore = DAG.getStore(BetterChain, Value, Ptr, SrcValue);
2725 // Create token to keep both nodes around.
2726 return DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
2733 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
2734 SDOperand InVec = N->getOperand(0);
2735 SDOperand InVal = N->getOperand(1);
2736 SDOperand EltNo = N->getOperand(2);
2738 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
2739 // vector with the inserted element.
2740 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2741 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2742 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2743 if (Elt < Ops.size())
2745 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
2746 &Ops[0], Ops.size());
2752 SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
2753 SDOperand InVec = N->getOperand(0);
2754 SDOperand InVal = N->getOperand(1);
2755 SDOperand EltNo = N->getOperand(2);
2756 SDOperand NumElts = N->getOperand(3);
2757 SDOperand EltType = N->getOperand(4);
2759 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new
2760 // vector with the inserted element.
2761 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2762 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2763 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2764 if (Elt < Ops.size()-2)
2766 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(),
2767 &Ops[0], Ops.size());
2773 SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
2774 unsigned NumInScalars = N->getNumOperands()-2;
2775 SDOperand NumElts = N->getOperand(NumInScalars);
2776 SDOperand EltType = N->getOperand(NumInScalars+1);
2778 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT
2779 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most
2780 // two distinct vectors, turn this into a shuffle node.
2781 SDOperand VecIn1, VecIn2;
2782 for (unsigned i = 0; i != NumInScalars; ++i) {
2783 // Ignore undef inputs.
2784 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
2786 // If this input is something other than a VEXTRACT_VECTOR_ELT with a
2787 // constant index, bail out.
2788 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT ||
2789 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
2790 VecIn1 = VecIn2 = SDOperand(0, 0);
2794 // If the input vector type disagrees with the result of the vbuild_vector,
2795 // we can't make a shuffle.
2796 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
2797 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts ||
2798 *(ExtractedFromVec.Val->op_end()-1) != EltType) {
2799 VecIn1 = VecIn2 = SDOperand(0, 0);
2803 // Otherwise, remember this. We allow up to two distinct input vectors.
2804 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
2807 if (VecIn1.Val == 0) {
2808 VecIn1 = ExtractedFromVec;
2809 } else if (VecIn2.Val == 0) {
2810 VecIn2 = ExtractedFromVec;
2813 VecIn1 = VecIn2 = SDOperand(0, 0);
2818 // If everything is good, we can make a shuffle operation.
2820 SmallVector<SDOperand, 8> BuildVecIndices;
2821 for (unsigned i = 0; i != NumInScalars; ++i) {
2822 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
2823 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
2827 SDOperand Extract = N->getOperand(i);
2829 // If extracting from the first vector, just use the index directly.
2830 if (Extract.getOperand(0) == VecIn1) {
2831 BuildVecIndices.push_back(Extract.getOperand(1));
2835 // Otherwise, use InIdx + VecSize
2836 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
2837 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32));
2840 // Add count and size info.
2841 BuildVecIndices.push_back(NumElts);
2842 BuildVecIndices.push_back(DAG.getValueType(MVT::i32));
2844 // Return the new VVECTOR_SHUFFLE node.
2850 // Use an undef vbuild_vector as input for the second operand.
2851 std::vector<SDOperand> UnOps(NumInScalars,
2852 DAG.getNode(ISD::UNDEF,
2853 cast<VTSDNode>(EltType)->getVT()));
2854 UnOps.push_back(NumElts);
2855 UnOps.push_back(EltType);
2856 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
2857 &UnOps[0], UnOps.size());
2858 AddToWorkList(Ops[1].Val);
2860 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
2861 &BuildVecIndices[0], BuildVecIndices.size());
2864 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5);
2870 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
2871 SDOperand ShufMask = N->getOperand(2);
2872 unsigned NumElts = ShufMask.getNumOperands();
2874 // If the shuffle mask is an identity operation on the LHS, return the LHS.
2875 bool isIdentity = true;
2876 for (unsigned i = 0; i != NumElts; ++i) {
2877 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2878 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
2883 if (isIdentity) return N->getOperand(0);
2885 // If the shuffle mask is an identity operation on the RHS, return the RHS.
2887 for (unsigned i = 0; i != NumElts; ++i) {
2888 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2889 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
2894 if (isIdentity) return N->getOperand(1);
2896 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
2898 bool isUnary = true;
2899 bool isSplat = true;
2901 unsigned BaseIdx = 0;
2902 for (unsigned i = 0; i != NumElts; ++i)
2903 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
2904 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
2905 int V = (Idx < NumElts) ? 0 : 1;
2919 SDOperand N0 = N->getOperand(0);
2920 SDOperand N1 = N->getOperand(1);
2921 // Normalize unary shuffle so the RHS is undef.
2922 if (isUnary && VecNum == 1)
2925 // If it is a splat, check if the argument vector is a build_vector with
2926 // all scalar elements the same.
2929 if (V->getOpcode() == ISD::BIT_CONVERT)
2930 V = V->getOperand(0).Val;
2931 if (V->getOpcode() == ISD::BUILD_VECTOR) {
2932 unsigned NumElems = V->getNumOperands()-2;
2933 if (NumElems > BaseIdx) {
2935 bool AllSame = true;
2936 for (unsigned i = 0; i != NumElems; ++i) {
2937 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
2938 Base = V->getOperand(i);
2942 // Splat of <u, u, u, u>, return <u, u, u, u>
2945 for (unsigned i = 0; i != NumElems; ++i) {
2946 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
2947 V->getOperand(i) != Base) {
2952 // Splat of <x, x, x, x>, return <x, x, x, x>
2959 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
2961 if (isUnary || N0 == N1) {
2962 if (N0.getOpcode() == ISD::UNDEF)
2963 return DAG.getNode(ISD::UNDEF, N->getValueType(0));
2964 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
2966 SmallVector<SDOperand, 8> MappedOps;
2967 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
2968 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
2969 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
2970 MappedOps.push_back(ShufMask.getOperand(i));
2973 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
2974 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
2977 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
2978 &MappedOps[0], MappedOps.size());
2979 AddToWorkList(ShufMask.Val);
2980 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
2982 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
2989 SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
2990 SDOperand ShufMask = N->getOperand(2);
2991 unsigned NumElts = ShufMask.getNumOperands()-2;
2993 // If the shuffle mask is an identity operation on the LHS, return the LHS.
2994 bool isIdentity = true;
2995 for (unsigned i = 0; i != NumElts; ++i) {
2996 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2997 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
3002 if (isIdentity) return N->getOperand(0);
3004 // If the shuffle mask is an identity operation on the RHS, return the RHS.
3006 for (unsigned i = 0; i != NumElts; ++i) {
3007 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3008 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
3013 if (isIdentity) return N->getOperand(1);
3015 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
3017 bool isUnary = true;
3018 bool isSplat = true;
3020 unsigned BaseIdx = 0;
3021 for (unsigned i = 0; i != NumElts; ++i)
3022 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
3023 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
3024 int V = (Idx < NumElts) ? 0 : 1;
3038 SDOperand N0 = N->getOperand(0);
3039 SDOperand N1 = N->getOperand(1);
3040 // Normalize unary shuffle so the RHS is undef.
3041 if (isUnary && VecNum == 1)
3044 // If it is a splat, check if the argument vector is a build_vector with
3045 // all scalar elements the same.
3048 if (V->getOpcode() == ISD::VBIT_CONVERT)
3049 V = V->getOperand(0).Val;
3050 if (V->getOpcode() == ISD::VBUILD_VECTOR) {
3051 unsigned NumElems = V->getNumOperands()-2;
3052 if (NumElems > BaseIdx) {
3054 bool AllSame = true;
3055 for (unsigned i = 0; i != NumElems; ++i) {
3056 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3057 Base = V->getOperand(i);
3061 // Splat of <u, u, u, u>, return <u, u, u, u>
3064 for (unsigned i = 0; i != NumElems; ++i) {
3065 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3066 V->getOperand(i) != Base) {
3071 // Splat of <x, x, x, x>, return <x, x, x, x>
3078 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3080 if (isUnary || N0 == N1) {
3081 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3083 SmallVector<SDOperand, 8> MappedOps;
3084 for (unsigned i = 0; i != NumElts; ++i) {
3085 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3086 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3087 MappedOps.push_back(ShufMask.getOperand(i));
3090 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3091 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3094 // Add the type/#elts values.
3095 MappedOps.push_back(ShufMask.getOperand(NumElts));
3096 MappedOps.push_back(ShufMask.getOperand(NumElts+1));
3098 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(),
3099 &MappedOps[0], MappedOps.size());
3100 AddToWorkList(ShufMask.Val);
3102 // Build the undef vector.
3103 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType());
3104 for (unsigned i = 0; i != NumElts; ++i)
3105 MappedOps[i] = UDVal;
3106 MappedOps[NumElts ] = *(N0.Val->op_end()-2);
3107 MappedOps[NumElts+1] = *(N0.Val->op_end()-1);
3108 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3109 &MappedOps[0], MappedOps.size());
3111 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3112 N0, UDVal, ShufMask,
3113 MappedOps[NumElts], MappedOps[NumElts+1]);
3119 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
3120 /// a VAND to a vector_shuffle with the destination vector and a zero vector.
3121 /// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
3122 /// vector_shuffle V, Zero, <0, 4, 2, 4>
3123 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
3124 SDOperand LHS = N->getOperand(0);
3125 SDOperand RHS = N->getOperand(1);
3126 if (N->getOpcode() == ISD::VAND) {
3127 SDOperand DstVecSize = *(LHS.Val->op_end()-2);
3128 SDOperand DstVecEVT = *(LHS.Val->op_end()-1);
3129 if (RHS.getOpcode() == ISD::VBIT_CONVERT)
3130 RHS = RHS.getOperand(0);
3131 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3132 std::vector<SDOperand> IdxOps;
3133 unsigned NumOps = RHS.getNumOperands();
3134 unsigned NumElts = NumOps-2;
3135 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT();
3136 for (unsigned i = 0; i != NumElts; ++i) {
3137 SDOperand Elt = RHS.getOperand(i);
3138 if (!isa<ConstantSDNode>(Elt))
3140 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
3141 IdxOps.push_back(DAG.getConstant(i, EVT));
3142 else if (cast<ConstantSDNode>(Elt)->isNullValue())
3143 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
3148 // Let's see if the target supports this vector_shuffle.
3149 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
3152 // Return the new VVECTOR_SHUFFLE node.
3153 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32);
3154 SDOperand EVTNode = DAG.getValueType(EVT);
3155 std::vector<SDOperand> Ops;
3156 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode,
3159 AddToWorkList(LHS.Val);
3160 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
3161 ZeroOps.push_back(NumEltsNode);
3162 ZeroOps.push_back(EVTNode);
3163 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3164 &ZeroOps[0], ZeroOps.size()));
3165 IdxOps.push_back(NumEltsNode);
3166 IdxOps.push_back(EVTNode);
3167 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3168 &IdxOps[0], IdxOps.size()));
3169 Ops.push_back(NumEltsNode);
3170 Ops.push_back(EVTNode);
3171 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3172 &Ops[0], Ops.size());
3173 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) {
3174 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
3175 DstVecSize, DstVecEVT);
3183 /// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates
3184 /// the scalar operation of the vop if it is operating on an integer vector
3185 /// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD).
3186 SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
3187 ISD::NodeType FPOp) {
3188 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT();
3189 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp;
3190 SDOperand LHS = N->getOperand(0);
3191 SDOperand RHS = N->getOperand(1);
3192 SDOperand Shuffle = XformToShuffleWithZero(N);
3193 if (Shuffle.Val) return Shuffle;
3195 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold
3197 if (LHS.getOpcode() == ISD::VBUILD_VECTOR &&
3198 RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3199 SmallVector<SDOperand, 8> Ops;
3200 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
3201 SDOperand LHSOp = LHS.getOperand(i);
3202 SDOperand RHSOp = RHS.getOperand(i);
3203 // If these two elements can't be folded, bail out.
3204 if ((LHSOp.getOpcode() != ISD::UNDEF &&
3205 LHSOp.getOpcode() != ISD::Constant &&
3206 LHSOp.getOpcode() != ISD::ConstantFP) ||
3207 (RHSOp.getOpcode() != ISD::UNDEF &&
3208 RHSOp.getOpcode() != ISD::Constant &&
3209 RHSOp.getOpcode() != ISD::ConstantFP))
3211 // Can't fold divide by zero.
3212 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) {
3213 if ((RHSOp.getOpcode() == ISD::Constant &&
3214 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
3215 (RHSOp.getOpcode() == ISD::ConstantFP &&
3216 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue()))
3219 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
3220 AddToWorkList(Ops.back().Val);
3221 assert((Ops.back().getOpcode() == ISD::UNDEF ||
3222 Ops.back().getOpcode() == ISD::Constant ||
3223 Ops.back().getOpcode() == ISD::ConstantFP) &&
3224 "Scalar binop didn't fold!");
3227 if (Ops.size() == LHS.getNumOperands()-2) {
3228 Ops.push_back(*(LHS.Val->op_end()-2));
3229 Ops.push_back(*(LHS.Val->op_end()-1));
3230 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
3237 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
3238 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
3240 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
3241 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3242 // If we got a simplified select_cc node back from SimplifySelectCC, then
3243 // break it down into a new SETCC node, and a new SELECT node, and then return
3244 // the SELECT node, since we were called with a SELECT node.
3246 // Check to see if we got a select_cc back (to turn into setcc/select).
3247 // Otherwise, just return whatever node we got back, like fabs.
3248 if (SCC.getOpcode() == ISD::SELECT_CC) {
3249 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
3250 SCC.getOperand(0), SCC.getOperand(1),
3252 AddToWorkList(SETCC.Val);
3253 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
3254 SCC.getOperand(3), SETCC);
3261 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
3262 /// are the two values being selected between, see if we can simplify the
3263 /// select. Callers of this should assume that TheSelect is deleted if this
3264 /// returns true. As such, they should return the appropriate thing (e.g. the
3265 /// node) back to the top-level of the DAG combiner loop to avoid it being
3268 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
3271 // If this is a select from two identical things, try to pull the operation
3272 // through the select.
3273 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
3274 // If this is a load and the token chain is identical, replace the select
3275 // of two loads with a load through a select of the address to load from.
3276 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
3277 // constants have been dropped into the constant pool.
3278 if (LHS.getOpcode() == ISD::LOAD &&
3279 // Token chains must be identical.
3280 LHS.getOperand(0) == RHS.getOperand(0)) {
3281 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
3282 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
3284 // If this is an EXTLOAD, the VT's must match.
3285 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
3286 // FIXME: this conflates two src values, discarding one. This is not
3287 // the right thing to do, but nothing uses srcvalues now. When they do,
3288 // turn SrcValue into a list of locations.
3290 if (TheSelect->getOpcode() == ISD::SELECT)
3291 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
3292 TheSelect->getOperand(0), LLD->getBasePtr(),
3295 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
3296 TheSelect->getOperand(0),
3297 TheSelect->getOperand(1),
3298 LLD->getBasePtr(), RLD->getBasePtr(),
3299 TheSelect->getOperand(4));
3302 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
3303 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
3304 Addr,LLD->getSrcValue(), LLD->getSrcValueOffset());
3306 Load = DAG.getExtLoad(LLD->getExtensionType(),
3307 TheSelect->getValueType(0),
3308 LLD->getChain(), Addr, LLD->getSrcValue(),
3309 LLD->getSrcValueOffset(),
3310 LLD->getLoadedVT());
3312 // Users of the select now use the result of the load.
3313 CombineTo(TheSelect, Load);
3315 // Users of the old loads now use the new load's chain. We know the
3316 // old-load value is dead now.
3317 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
3318 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
3327 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
3328 SDOperand N2, SDOperand N3,
3331 MVT::ValueType VT = N2.getValueType();
3332 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
3333 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
3334 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
3336 // Determine if the condition we're dealing with is constant
3337 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
3338 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
3340 // fold select_cc true, x, y -> x
3341 if (SCCC && SCCC->getValue())
3343 // fold select_cc false, x, y -> y
3344 if (SCCC && SCCC->getValue() == 0)
3347 // Check to see if we can simplify the select into an fabs node
3348 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
3349 // Allow either -0.0 or 0.0
3350 if (CFP->getValue() == 0.0) {
3351 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
3352 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
3353 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
3354 N2 == N3.getOperand(0))
3355 return DAG.getNode(ISD::FABS, VT, N0);
3357 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
3358 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
3359 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
3360 N2.getOperand(0) == N3)
3361 return DAG.getNode(ISD::FABS, VT, N3);
3365 // Check to see if we can perform the "gzip trick", transforming
3366 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
3367 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
3368 MVT::isInteger(N0.getValueType()) &&
3369 MVT::isInteger(N2.getValueType()) &&
3370 (N1C->isNullValue() || // (a < 0) ? b : 0
3371 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
3372 MVT::ValueType XType = N0.getValueType();
3373 MVT::ValueType AType = N2.getValueType();
3374 if (XType >= AType) {
3375 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
3376 // single-bit constant.
3377 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
3378 unsigned ShCtV = Log2_64(N2C->getValue());
3379 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
3380 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
3381 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
3382 AddToWorkList(Shift.Val);
3383 if (XType > AType) {
3384 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3385 AddToWorkList(Shift.Val);
3387 return DAG.getNode(ISD::AND, AType, Shift, N2);
3389 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3390 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3391 TLI.getShiftAmountTy()));
3392 AddToWorkList(Shift.Val);
3393 if (XType > AType) {
3394 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3395 AddToWorkList(Shift.Val);
3397 return DAG.getNode(ISD::AND, AType, Shift, N2);
3401 // fold select C, 16, 0 -> shl C, 4
3402 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
3403 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
3404 // Get a SetCC of the condition
3405 // FIXME: Should probably make sure that setcc is legal if we ever have a
3406 // target where it isn't.
3407 SDOperand Temp, SCC;
3408 // cast from setcc result type to select result type
3409 if (AfterLegalize) {
3410 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3411 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
3413 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
3414 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
3416 AddToWorkList(SCC.Val);
3417 AddToWorkList(Temp.Val);
3418 // shl setcc result by log2 n2c
3419 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
3420 DAG.getConstant(Log2_64(N2C->getValue()),
3421 TLI.getShiftAmountTy()));
3424 // Check to see if this is the equivalent of setcc
3425 // FIXME: Turn all of these into setcc if setcc if setcc is legal
3426 // otherwise, go ahead with the folds.
3427 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
3428 MVT::ValueType XType = N0.getValueType();
3429 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
3430 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3431 if (Res.getValueType() != VT)
3432 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
3436 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
3437 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
3438 TLI.isOperationLegal(ISD::CTLZ, XType)) {
3439 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
3440 return DAG.getNode(ISD::SRL, XType, Ctlz,
3441 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
3442 TLI.getShiftAmountTy()));
3444 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
3445 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
3446 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
3448 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
3449 DAG.getConstant(~0ULL, XType));
3450 return DAG.getNode(ISD::SRL, XType,
3451 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
3452 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3453 TLI.getShiftAmountTy()));
3455 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
3456 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
3457 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
3458 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3459 TLI.getShiftAmountTy()));
3460 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
3464 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
3465 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
3466 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
3467 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
3468 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
3469 MVT::ValueType XType = N0.getValueType();
3470 if (SubC->isNullValue() && MVT::isInteger(XType)) {
3471 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3472 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3473 TLI.getShiftAmountTy()));
3474 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
3475 AddToWorkList(Shift.Val);
3476 AddToWorkList(Add.Val);
3477 return DAG.getNode(ISD::XOR, XType, Add, Shift);
3485 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
3486 SDOperand N1, ISD::CondCode Cond,
3487 bool foldBooleans) {
3488 // These setcc operations always fold.
3492 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
3494 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
3497 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
3498 uint64_t C1 = N1C->getValue();
3499 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
3500 uint64_t C0 = N0C->getValue();
3502 // Sign extend the operands if required
3503 if (ISD::isSignedIntSetCC(Cond)) {
3504 C0 = N0C->getSignExtended();
3505 C1 = N1C->getSignExtended();
3509 default: assert(0 && "Unknown integer setcc!");
3510 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
3511 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
3512 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
3513 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
3514 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
3515 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
3516 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
3517 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
3518 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
3519 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
3522 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
3523 // equality comparison, then we're just comparing whether X itself is
3525 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
3526 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
3527 N0.getOperand(1).getOpcode() == ISD::Constant) {
3528 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
3529 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3530 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) {
3531 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
3532 // (srl (ctlz x), 5) == 0 -> X != 0
3533 // (srl (ctlz x), 5) != 1 -> X != 0
3536 // (srl (ctlz x), 5) != 0 -> X == 0
3537 // (srl (ctlz x), 5) == 1 -> X == 0
3540 SDOperand Zero = DAG.getConstant(0, N0.getValueType());
3541 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
3546 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
3547 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
3548 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
3550 // If the comparison constant has bits in the upper part, the
3551 // zero-extended value could never match.
3552 if (C1 & (~0ULL << InSize)) {
3553 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
3557 case ISD::SETEQ: return DAG.getConstant(0, VT);
3560 case ISD::SETNE: return DAG.getConstant(1, VT);
3563 // True if the sign bit of C1 is set.
3564 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
3567 // True if the sign bit of C1 isn't set.
3568 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
3574 // Otherwise, we can perform the comparison with the low bits.
3582 return DAG.getSetCC(VT, N0.getOperand(0),
3583 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
3586 break; // todo, be more careful with signed comparisons
3588 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3589 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3590 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
3591 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
3592 MVT::ValueType ExtDstTy = N0.getValueType();
3593 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
3595 // If the extended part has any inconsistent bits, it cannot ever
3596 // compare equal. In other words, they have to be all ones or all
3599 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
3600 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
3601 return DAG.getConstant(Cond == ISD::SETNE, VT);
3604 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
3605 if (Op0Ty == ExtSrcTy) {
3606 ZextOp = N0.getOperand(0);
3608 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
3609 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
3610 DAG.getConstant(Imm, Op0Ty));
3612 AddToWorkList(ZextOp.Val);
3613 // Otherwise, make this a use of a zext.
3614 return DAG.getSetCC(VT, ZextOp,
3615 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
3618 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
3619 (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3620 (N0.getOpcode() == ISD::XOR ||
3621 (N0.getOpcode() == ISD::AND &&
3622 N0.getOperand(0).getOpcode() == ISD::XOR &&
3623 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
3624 isa<ConstantSDNode>(N0.getOperand(1)) &&
3625 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
3626 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can
3627 // only do this if the top bits are known zero.
3628 if (TLI.MaskedValueIsZero(N1,
3629 MVT::getIntVTBitMask(N0.getValueType())-1)) {
3630 // Okay, get the un-inverted input value.
3632 if (N0.getOpcode() == ISD::XOR)
3633 Val = N0.getOperand(0);
3635 assert(N0.getOpcode() == ISD::AND &&
3636 N0.getOperand(0).getOpcode() == ISD::XOR);
3637 // ((X^1)&1)^1 -> X & 1
3638 Val = DAG.getNode(ISD::AND, N0.getValueType(),
3639 N0.getOperand(0).getOperand(0), N0.getOperand(1));
3641 return DAG.getSetCC(VT, Val, N1,
3642 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3646 uint64_t MinVal, MaxVal;
3647 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
3648 if (ISD::isSignedIntSetCC(Cond)) {
3649 MinVal = 1ULL << (OperandBitSize-1);
3650 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
3651 MaxVal = ~0ULL >> (65-OperandBitSize);
3656 MaxVal = ~0ULL >> (64-OperandBitSize);
3659 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
3660 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
3661 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
3662 --C1; // X >= C0 --> X > (C0-1)
3663 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3664 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
3667 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
3668 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
3669 ++C1; // X <= C0 --> X < (C0+1)
3670 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3671 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
3674 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
3675 return DAG.getConstant(0, VT); // X < MIN --> false
3677 // Canonicalize setgt X, Min --> setne X, Min
3678 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
3679 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3680 // Canonicalize setlt X, Max --> setne X, Max
3681 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
3682 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3684 // If we have setult X, 1, turn it into seteq X, 0
3685 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
3686 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
3688 // If we have setugt X, Max-1, turn it into seteq X, Max
3689 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
3690 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
3693 // If we have "setcc X, C0", check to see if we can shrink the immediate
3696 // SETUGT X, SINTMAX -> SETLT X, 0
3697 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
3698 C1 == (~0ULL >> (65-OperandBitSize)))
3699 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
3702 // FIXME: Implement the rest of these.
3704 // Fold bit comparisons when we can.
3705 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3706 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
3707 if (ConstantSDNode *AndRHS =
3708 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3709 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
3710 // Perform the xform if the AND RHS is a single bit.
3711 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
3712 return DAG.getNode(ISD::SRL, VT, N0,
3713 DAG.getConstant(Log2_64(AndRHS->getValue()),
3714 TLI.getShiftAmountTy()));
3716 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
3717 // (X & 8) == 8 --> (X & 8) >> 3
3718 // Perform the xform if C1 is a single bit.
3719 if ((C1 & (C1-1)) == 0) {
3720 return DAG.getNode(ISD::SRL, VT, N0,
3721 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
3726 } else if (isa<ConstantSDNode>(N0.Val)) {
3727 // Ensure that the constant occurs on the RHS.
3728 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
3731 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
3732 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
3733 double C0 = N0C->getValue(), C1 = N1C->getValue();
3736 default: break; // FIXME: Implement the rest of these!
3737 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
3738 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
3739 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
3740 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
3741 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
3742 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
3745 // Ensure that the constant occurs on the RHS.
3746 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
3750 // We can always fold X == Y for integer setcc's.
3751 if (MVT::isInteger(N0.getValueType()))
3752 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3753 unsigned UOF = ISD::getUnorderedFlavor(Cond);
3754 if (UOF == 2) // FP operators that are undefined on NaNs.
3755 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3756 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
3757 return DAG.getConstant(UOF, VT);
3758 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
3759 // if it is not already.
3760 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
3761 if (NewCond != Cond)
3762 return DAG.getSetCC(VT, N0, N1, NewCond);
3765 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3766 MVT::isInteger(N0.getValueType())) {
3767 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
3768 N0.getOpcode() == ISD::XOR) {
3769 // Simplify (X+Y) == (X+Z) --> Y == Z
3770 if (N0.getOpcode() == N1.getOpcode()) {
3771 if (N0.getOperand(0) == N1.getOperand(0))
3772 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
3773 if (N0.getOperand(1) == N1.getOperand(1))
3774 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
3775 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
3776 // If X op Y == Y op X, try other combinations.
3777 if (N0.getOperand(0) == N1.getOperand(1))
3778 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
3779 if (N0.getOperand(1) == N1.getOperand(0))
3780 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
3784 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
3785 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3786 // Turn (X+C1) == C2 --> X == C2-C1
3787 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
3788 return DAG.getSetCC(VT, N0.getOperand(0),
3789 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
3790 N0.getValueType()), Cond);
3793 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
3794 if (N0.getOpcode() == ISD::XOR)
3795 // If we know that all of the inverted bits are zero, don't bother
3796 // performing the inversion.
3797 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
3798 return DAG.getSetCC(VT, N0.getOperand(0),
3799 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
3800 N0.getValueType()), Cond);
3803 // Turn (C1-X) == C2 --> X == C1-C2
3804 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
3805 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
3806 return DAG.getSetCC(VT, N0.getOperand(1),
3807 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
3808 N0.getValueType()), Cond);
3813 // Simplify (X+Z) == X --> Z == 0
3814 if (N0.getOperand(0) == N1)
3815 return DAG.getSetCC(VT, N0.getOperand(1),
3816 DAG.getConstant(0, N0.getValueType()), Cond);
3817 if (N0.getOperand(1) == N1) {
3818 if (DAG.isCommutativeBinOp(N0.getOpcode()))
3819 return DAG.getSetCC(VT, N0.getOperand(0),
3820 DAG.getConstant(0, N0.getValueType()), Cond);
3822 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
3823 // (Z-X) == X --> Z == X<<1
3824 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
3826 DAG.getConstant(1,TLI.getShiftAmountTy()));
3827 AddToWorkList(SH.Val);
3828 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
3833 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
3834 N1.getOpcode() == ISD::XOR) {
3835 // Simplify X == (X+Z) --> Z == 0
3836 if (N1.getOperand(0) == N0) {
3837 return DAG.getSetCC(VT, N1.getOperand(1),
3838 DAG.getConstant(0, N1.getValueType()), Cond);
3839 } else if (N1.getOperand(1) == N0) {
3840 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
3841 return DAG.getSetCC(VT, N1.getOperand(0),
3842 DAG.getConstant(0, N1.getValueType()), Cond);
3844 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
3845 // X == (Z-X) --> X<<1 == Z
3846 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
3847 DAG.getConstant(1,TLI.getShiftAmountTy()));
3848 AddToWorkList(SH.Val);
3849 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
3855 // Fold away ALL boolean setcc's.
3857 if (N0.getValueType() == MVT::i1 && foldBooleans) {
3859 default: assert(0 && "Unknown integer setcc!");
3860 case ISD::SETEQ: // X == Y -> (X^Y)^1
3861 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
3862 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
3863 AddToWorkList(Temp.Val);
3865 case ISD::SETNE: // X != Y --> (X^Y)
3866 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
3868 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
3869 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
3870 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
3871 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
3872 AddToWorkList(Temp.Val);
3874 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
3875 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
3876 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
3877 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
3878 AddToWorkList(Temp.Val);
3880 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
3881 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
3882 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
3883 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
3884 AddToWorkList(Temp.Val);
3886 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
3887 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
3888 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
3889 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
3892 if (VT != MVT::i1) {
3893 AddToWorkList(N0.Val);
3894 // FIXME: If running after legalize, we probably can't do this.
3895 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
3900 // Could not fold it.
3904 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3905 /// return a DAG expression to select that will generate the same value by
3906 /// multiplying by a magic number. See:
3907 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3908 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
3909 std::vector<SDNode*> Built;
3910 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
3912 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
3918 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3919 /// return a DAG expression to select that will generate the same value by
3920 /// multiplying by a magic number. See:
3921 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3922 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
3923 std::vector<SDNode*> Built;
3924 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
3926 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
3932 /// FindBaseOffset - Return true if base is known not to alias with anything
3933 /// but itself. Provides base object and offset as results.
3934 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
3935 // Assume it is a primitive operation.
3936 Base = Ptr; Offset = 0;
3938 // If it's an adding a simple constant then integrate the offset.
3939 if (Base.getOpcode() == ISD::ADD) {
3940 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
3941 Base = Base.getOperand(0);
3942 Offset += C->getValue();
3946 // If it's any of the following then it can't alias with anything but itself.
3947 return isa<FrameIndexSDNode>(Base) ||
3948 isa<ConstantPoolSDNode>(Base) ||
3949 isa<GlobalAddressSDNode>(Base);
3952 /// isAlias - Return true if there is any possibility that the two addresses
3954 static bool isAlias(SDOperand Ptr1, int64_t Size1, SDOperand SrcValue1,
3955 SDOperand Ptr2, int64_t Size2, SDOperand SrcValue2) {
3956 // If they are the same then they must be aliases.
3957 if (Ptr1 == Ptr2) return true;
3959 // Gather base node and offset information.
3960 SDOperand Base1, Base2;
3961 int64_t Offset1, Offset2;
3962 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
3963 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
3965 // If they have a same base address then...
3966 if (Base1 == Base2) {
3967 // Check to see if the addresses overlap.
3968 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
3971 // Otherwise they alias if either is unknown.
3972 return !KnownBase1 || !KnownBase2;
3975 /// FindAliasInfo - Extracts the relevant alias information from the memory
3976 /// node. Returns true if the operand was a load.
3977 static bool FindAliasInfo(SDNode *N, SDOperand &Ptr, int64_t &Size,
3978 SDOperand &SrcValue, SelectionDAG &DAG) {
3979 switch (N->getOpcode()) {
3981 if (!ISD::isNON_EXTLoad(N))
3983 Ptr = N->getOperand(1);
3984 Size = MVT::getSizeInBits(N->getValueType(0)) >> 3;
3985 SrcValue = N->getOperand(2);
3988 Ptr = N->getOperand(2);
3989 Size = MVT::getSizeInBits(N->getOperand(1).getValueType()) >> 3;
3990 SrcValue = N->getOperand(3);
3993 assert(0 && "FindAliasInfo expected a memory operand");
4000 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
4001 /// looking for aliasing nodes and adding them to the Aliases vector.
4002 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
4003 SmallVector<SDOperand, 8> &Aliases) {
4004 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
4005 std::set<SDNode *> Visited; // Visited node set.
4007 // Get alias information for node.
4011 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, DAG);
4014 Chains.push_back(OriginalChain);
4016 // Look at each chain and determine if it is an alias. If so, add it to the
4017 // aliases list. If not, then continue up the chain looking for the next
4019 while (!Chains.empty()) {
4020 SDOperand Chain = Chains.back();
4023 // Don't bother if we've been before.
4024 if (Visited.find(Chain.Val) != Visited.end()) continue;
4025 Visited.insert(Chain.Val);
4027 switch (Chain.getOpcode()) {
4028 case ISD::EntryToken:
4029 // Entry token is ideal chain operand, but handled in FindBetterChain.
4034 // Get alias information for Chain.
4037 SDOperand OpSrcValue;
4038 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, OpSrcValue, DAG);
4040 // If chain is alias then stop here.
4041 if (!(IsLoad && IsOpLoad) &&
4042 isAlias(Ptr, Size, SrcValue, OpPtr, OpSize, OpSrcValue)) {
4043 Aliases.push_back(Chain);
4045 // Look further up the chain.
4046 Chains.push_back(Chain.getOperand(0));
4047 // Clean up old chain.
4048 AddToWorkList(Chain.Val);
4053 case ISD::TokenFactor:
4054 // We have to check each of the operands of the token factor, so we queue
4055 // then up. Adding the operands to the queue (stack) in reverse order
4056 // maintains the original order and increases the likelihood that getNode
4057 // will find a matching token factor (CSE.)
4058 for (unsigned n = Chain.getNumOperands(); n;)
4059 Chains.push_back(Chain.getOperand(--n));
4060 // Eliminate the token factor if we can.
4061 AddToWorkList(Chain.Val);
4065 // For all other instructions we will just have to take what we can get.
4066 Aliases.push_back(Chain);
4072 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
4073 /// for a better chain (aliasing node.)
4074 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
4075 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
4077 // Accumulate all the aliases to this node.
4078 GatherAllAliases(N, OldChain, Aliases);
4080 if (Aliases.size() == 0) {
4081 // If no operands then chain to entry token.
4082 return DAG.getEntryNode();
4083 } else if (Aliases.size() == 1) {
4084 // If a single operand then chain to it. We don't need to revisit it.
4088 // Construct a custom tailored token factor.
4089 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4090 &Aliases[0], Aliases.size());
4092 // Make sure the old chain gets cleaned up.
4093 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
4098 // SelectionDAG::Combine - This is the entry point for the file.
4100 void SelectionDAG::Combine(bool RunningAfterLegalize) {
4101 /// run - This is the main entry point to this class.
4103 DAGCombiner(*this).Run(RunningAfterLegalize);