1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/ADT/SetVector.h"
21 #include "llvm/ADT/SmallBitVector.h"
22 #include "llvm/ADT/SmallPtrSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/Analysis/AliasAnalysis.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetLowering.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
43 #define DEBUG_TYPE "dagcombine"
45 STATISTIC(NodesCombined , "Number of dag nodes combined");
46 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
47 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
48 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
49 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
50 STATISTIC(SlicedLoads, "Number of load sliced");
54 CombinerAA("combiner-alias-analysis", cl::Hidden,
55 cl::desc("Enable DAG combiner alias-analysis heuristics"));
58 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
59 cl::desc("Enable DAG combiner's use of IR alias analysis"));
62 UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true),
63 cl::desc("Enable DAG combiner's use of TBAA"));
66 static cl::opt<std::string>
67 CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden,
68 cl::desc("Only use DAG-combiner alias analysis in this"
72 /// Hidden option to stress test load slicing, i.e., when this option
73 /// is enabled, load slicing bypasses most of its profitability guards.
75 StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden,
76 cl::desc("Bypass the profitability model of load "
81 MaySplitLoadIndex("combiner-split-load-index", cl::Hidden, cl::init(true),
82 cl::desc("DAG combiner may split indexing from loads"));
84 //------------------------------ DAGCombiner ---------------------------------//
88 const TargetLowering &TLI;
90 CodeGenOpt::Level OptLevel;
95 /// \brief Worklist of all of the nodes that need to be simplified.
97 /// This must behave as a stack -- new nodes to process are pushed onto the
98 /// back and when processing we pop off of the back.
100 /// The worklist will not contain duplicates but may contain null entries
101 /// due to nodes being deleted from the underlying DAG.
102 SmallVector<SDNode *, 64> Worklist;
104 /// \brief Mapping from an SDNode to its position on the worklist.
106 /// This is used to find and remove nodes from the worklist (by nulling
107 /// them) when they are deleted from the underlying DAG. It relies on
108 /// stable indices of nodes within the worklist.
109 DenseMap<SDNode *, unsigned> WorklistMap;
111 /// \brief Set of nodes which have been combined (at least once).
113 /// This is used to allow us to reliably add any operands of a DAG node
114 /// which have not yet been combined to the worklist.
115 SmallPtrSet<SDNode *, 64> CombinedNodes;
117 // AA - Used for DAG load/store alias analysis.
120 /// When an instruction is simplified, add all users of the instruction to
121 /// the work lists because they might get more simplified now.
122 void AddUsersToWorklist(SDNode *N) {
123 for (SDNode *Node : N->uses())
127 /// Call the node-specific routine that folds each particular type of node.
128 SDValue visit(SDNode *N);
131 /// Add to the worklist making sure its instance is at the back (next to be
133 void AddToWorklist(SDNode *N) {
134 // Skip handle nodes as they can't usefully be combined and confuse the
135 // zero-use deletion strategy.
136 if (N->getOpcode() == ISD::HANDLENODE)
139 if (WorklistMap.insert(std::make_pair(N, Worklist.size())).second)
140 Worklist.push_back(N);
143 /// Remove all instances of N from the worklist.
144 void removeFromWorklist(SDNode *N) {
145 CombinedNodes.erase(N);
147 auto It = WorklistMap.find(N);
148 if (It == WorklistMap.end())
149 return; // Not in the worklist.
151 // Null out the entry rather than erasing it to avoid a linear operation.
152 Worklist[It->second] = nullptr;
153 WorklistMap.erase(It);
156 void deleteAndRecombine(SDNode *N);
157 bool recursivelyDeleteUnusedNodes(SDNode *N);
159 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
162 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
163 return CombineTo(N, &Res, 1, AddTo);
166 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
168 SDValue To[] = { Res0, Res1 };
169 return CombineTo(N, To, 2, AddTo);
172 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
176 /// Check the specified integer node value to see if it can be simplified or
177 /// if things it uses can be simplified by bit propagation.
178 /// If so, return true.
179 bool SimplifyDemandedBits(SDValue Op) {
180 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
181 APInt Demanded = APInt::getAllOnesValue(BitWidth);
182 return SimplifyDemandedBits(Op, Demanded);
185 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
187 bool CombineToPreIndexedLoadStore(SDNode *N);
188 bool CombineToPostIndexedLoadStore(SDNode *N);
189 SDValue SplitIndexingFromLoad(LoadSDNode *LD);
190 bool SliceUpLoad(SDNode *N);
192 /// \brief Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed
195 /// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced.
196 /// \param InVecVT type of the input vector to EVE with bitcasts resolved.
197 /// \param EltNo index of the vector element to load.
198 /// \param OriginalLoad load that EVE came from to be replaced.
199 /// \returns EVE on success SDValue() on failure.
200 SDValue ReplaceExtractVectorEltOfLoadWithNarrowedLoad(
201 SDNode *EVE, EVT InVecVT, SDValue EltNo, LoadSDNode *OriginalLoad);
202 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
203 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
204 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
205 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
206 SDValue PromoteIntBinOp(SDValue Op);
207 SDValue PromoteIntShiftOp(SDValue Op);
208 SDValue PromoteExtend(SDValue Op);
209 bool PromoteLoad(SDValue Op);
211 void ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
212 SDValue Trunc, SDValue ExtLoad, SDLoc DL,
213 ISD::NodeType ExtType);
215 /// Call the node-specific routine that knows how to fold each
216 /// particular type of node. If that doesn't do anything, try the
217 /// target-specific DAG combines.
218 SDValue combine(SDNode *N);
220 // Visitation implementation - Implement dag node combining for different
221 // node types. The semantics are as follows:
223 // SDValue.getNode() == 0 - No change was made
224 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
225 // otherwise - N should be replaced by the returned Operand.
227 SDValue visitTokenFactor(SDNode *N);
228 SDValue visitMERGE_VALUES(SDNode *N);
229 SDValue visitADD(SDNode *N);
230 SDValue visitSUB(SDNode *N);
231 SDValue visitADDC(SDNode *N);
232 SDValue visitSUBC(SDNode *N);
233 SDValue visitADDE(SDNode *N);
234 SDValue visitSUBE(SDNode *N);
235 SDValue visitMUL(SDNode *N);
236 SDValue visitSDIV(SDNode *N);
237 SDValue visitUDIV(SDNode *N);
238 SDValue visitSREM(SDNode *N);
239 SDValue visitUREM(SDNode *N);
240 SDValue visitMULHU(SDNode *N);
241 SDValue visitMULHS(SDNode *N);
242 SDValue visitSMUL_LOHI(SDNode *N);
243 SDValue visitUMUL_LOHI(SDNode *N);
244 SDValue visitSMULO(SDNode *N);
245 SDValue visitUMULO(SDNode *N);
246 SDValue visitSDIVREM(SDNode *N);
247 SDValue visitUDIVREM(SDNode *N);
248 SDValue visitAND(SDNode *N);
249 SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *LocReference);
250 SDValue visitOR(SDNode *N);
251 SDValue visitORLike(SDValue N0, SDValue N1, SDNode *LocReference);
252 SDValue visitXOR(SDNode *N);
253 SDValue SimplifyVBinOp(SDNode *N);
254 SDValue visitSHL(SDNode *N);
255 SDValue visitSRA(SDNode *N);
256 SDValue visitSRL(SDNode *N);
257 SDValue visitRotate(SDNode *N);
258 SDValue visitBSWAP(SDNode *N);
259 SDValue visitCTLZ(SDNode *N);
260 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
261 SDValue visitCTTZ(SDNode *N);
262 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
263 SDValue visitCTPOP(SDNode *N);
264 SDValue visitSELECT(SDNode *N);
265 SDValue visitVSELECT(SDNode *N);
266 SDValue visitSELECT_CC(SDNode *N);
267 SDValue visitSETCC(SDNode *N);
268 SDValue visitSIGN_EXTEND(SDNode *N);
269 SDValue visitZERO_EXTEND(SDNode *N);
270 SDValue visitANY_EXTEND(SDNode *N);
271 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
272 SDValue visitSIGN_EXTEND_VECTOR_INREG(SDNode *N);
273 SDValue visitTRUNCATE(SDNode *N);
274 SDValue visitBITCAST(SDNode *N);
275 SDValue visitBUILD_PAIR(SDNode *N);
276 SDValue visitFADD(SDNode *N);
277 SDValue visitFSUB(SDNode *N);
278 SDValue visitFMUL(SDNode *N);
279 SDValue visitFMA(SDNode *N);
280 SDValue visitFDIV(SDNode *N);
281 SDValue visitFREM(SDNode *N);
282 SDValue visitFSQRT(SDNode *N);
283 SDValue visitFCOPYSIGN(SDNode *N);
284 SDValue visitSINT_TO_FP(SDNode *N);
285 SDValue visitUINT_TO_FP(SDNode *N);
286 SDValue visitFP_TO_SINT(SDNode *N);
287 SDValue visitFP_TO_UINT(SDNode *N);
288 SDValue visitFP_ROUND(SDNode *N);
289 SDValue visitFP_ROUND_INREG(SDNode *N);
290 SDValue visitFP_EXTEND(SDNode *N);
291 SDValue visitFNEG(SDNode *N);
292 SDValue visitFABS(SDNode *N);
293 SDValue visitFCEIL(SDNode *N);
294 SDValue visitFTRUNC(SDNode *N);
295 SDValue visitFFLOOR(SDNode *N);
296 SDValue visitFMINNUM(SDNode *N);
297 SDValue visitFMAXNUM(SDNode *N);
298 SDValue visitBRCOND(SDNode *N);
299 SDValue visitBR_CC(SDNode *N);
300 SDValue visitLOAD(SDNode *N);
301 SDValue visitSTORE(SDNode *N);
302 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
303 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
304 SDValue visitBUILD_VECTOR(SDNode *N);
305 SDValue visitCONCAT_VECTORS(SDNode *N);
306 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
307 SDValue visitVECTOR_SHUFFLE(SDNode *N);
308 SDValue visitSCALAR_TO_VECTOR(SDNode *N);
309 SDValue visitINSERT_SUBVECTOR(SDNode *N);
310 SDValue visitMLOAD(SDNode *N);
311 SDValue visitMSTORE(SDNode *N);
312 SDValue visitMGATHER(SDNode *N);
313 SDValue visitMSCATTER(SDNode *N);
314 SDValue visitFP_TO_FP16(SDNode *N);
316 SDValue visitFADDForFMACombine(SDNode *N);
317 SDValue visitFSUBForFMACombine(SDNode *N);
319 SDValue XformToShuffleWithZero(SDNode *N);
320 SDValue ReassociateOps(unsigned Opc, SDLoc DL, SDValue LHS, SDValue RHS);
322 SDValue visitShiftByConstant(SDNode *N, ConstantSDNode *Amt);
324 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
325 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
326 SDValue SimplifySelect(SDLoc DL, SDValue N0, SDValue N1, SDValue N2);
327 SDValue SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1, SDValue N2,
328 SDValue N3, ISD::CondCode CC,
329 bool NotExtCompare = false);
330 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
331 SDLoc DL, bool foldBooleans = true);
333 bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
335 bool isOneUseSetCC(SDValue N) const;
337 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
339 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
340 SDValue CombineExtLoad(SDNode *N);
341 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
342 SDValue BuildSDIV(SDNode *N);
343 SDValue BuildSDIVPow2(SDNode *N);
344 SDValue BuildUDIV(SDNode *N);
345 SDValue BuildReciprocalEstimate(SDValue Op);
346 SDValue BuildRsqrtEstimate(SDValue Op);
347 SDValue BuildRsqrtNROneConst(SDValue Op, SDValue Est, unsigned Iterations);
348 SDValue BuildRsqrtNRTwoConst(SDValue Op, SDValue Est, unsigned Iterations);
349 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
350 bool DemandHighBits = true);
351 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
352 SDNode *MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
353 SDValue InnerPos, SDValue InnerNeg,
354 unsigned PosOpcode, unsigned NegOpcode,
356 SDNode *MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL);
357 SDValue ReduceLoadWidth(SDNode *N);
358 SDValue ReduceLoadOpStoreWidth(SDNode *N);
359 SDValue TransformFPLoadStorePair(SDNode *N);
360 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N);
361 SDValue reduceBuildVecConvertToConvertBuildVec(SDNode *N);
363 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
365 /// Walk up chain skipping non-aliasing memory nodes,
366 /// looking for aliasing nodes and adding them to the Aliases vector.
367 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
368 SmallVectorImpl<SDValue> &Aliases);
370 /// Return true if there is any possibility that the two addresses overlap.
371 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const;
373 /// Walk up chain skipping non-aliasing memory nodes, looking for a better
374 /// chain (aliasing node.)
375 SDValue FindBetterChain(SDNode *N, SDValue Chain);
377 /// Holds a pointer to an LSBaseSDNode as well as information on where it
378 /// is located in a sequence of memory operations connected by a chain.
380 MemOpLink (LSBaseSDNode *N, int64_t Offset, unsigned Seq):
381 MemNode(N), OffsetFromBase(Offset), SequenceNum(Seq) { }
382 // Ptr to the mem node.
383 LSBaseSDNode *MemNode;
384 // Offset from the base ptr.
385 int64_t OffsetFromBase;
386 // What is the sequence number of this mem node.
387 // Lowest mem operand in the DAG starts at zero.
388 unsigned SequenceNum;
391 /// This is a helper function for MergeStoresOfConstantsOrVecElts. Returns a
392 /// constant build_vector of the stored constant values in Stores.
393 SDValue getMergedConstantVectorStore(SelectionDAG &DAG,
395 ArrayRef<MemOpLink> Stores,
398 /// This is a helper function for MergeConsecutiveStores. When the source
399 /// elements of the consecutive stores are all constants or all extracted
400 /// vector elements, try to merge them into one larger store.
401 /// \return True if a merged store was created.
402 bool MergeStoresOfConstantsOrVecElts(SmallVectorImpl<MemOpLink> &StoreNodes,
403 EVT MemVT, unsigned NumElem,
404 bool IsConstantSrc, bool UseVector);
406 /// This is a helper function for MergeConsecutiveStores.
407 /// Stores that may be merged are placed in StoreNodes.
408 /// Loads that may alias with those stores are placed in AliasLoadNodes.
409 void getStoreMergeAndAliasCandidates(
410 StoreSDNode* St, SmallVectorImpl<MemOpLink> &StoreNodes,
411 SmallVectorImpl<LSBaseSDNode*> &AliasLoadNodes);
413 /// Merge consecutive store operations into a wide store.
414 /// This optimization uses wide integers or vectors when possible.
415 /// \return True if some memory operations were changed.
416 bool MergeConsecutiveStores(StoreSDNode *N);
418 /// \brief Try to transform a truncation where C is a constant:
419 /// (trunc (and X, C)) -> (and (trunc X), (trunc C))
421 /// \p N needs to be a truncation and its first operand an AND. Other
422 /// requirements are checked by the function (e.g. that trunc is
423 /// single-use) and if missed an empty SDValue is returned.
424 SDValue distributeTruncateThroughAnd(SDNode *N);
427 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
428 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
429 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {
430 auto *F = DAG.getMachineFunction().getFunction();
431 ForCodeSize = F->hasFnAttribute(Attribute::OptimizeForSize) ||
432 F->hasFnAttribute(Attribute::MinSize);
435 /// Runs the dag combiner on all nodes in the work list
436 void Run(CombineLevel AtLevel);
438 SelectionDAG &getDAG() const { return DAG; }
440 /// Returns a type large enough to hold any valid shift amount - before type
441 /// legalization these can be huge.
442 EVT getShiftAmountTy(EVT LHSTy) {
443 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
444 if (LHSTy.isVector())
446 return LegalTypes ? TLI.getScalarShiftAmountTy(LHSTy)
447 : TLI.getPointerTy();
450 /// This method returns true if we are running before type legalization or
451 /// if the specified VT is legal.
452 bool isTypeLegal(const EVT &VT) {
453 if (!LegalTypes) return true;
454 return TLI.isTypeLegal(VT);
457 /// Convenience wrapper around TargetLowering::getSetCCResultType
458 EVT getSetCCResultType(EVT VT) const {
459 return TLI.getSetCCResultType(*DAG.getContext(), VT);
466 /// This class is a DAGUpdateListener that removes any deleted
467 /// nodes from the worklist.
468 class WorklistRemover : public SelectionDAG::DAGUpdateListener {
471 explicit WorklistRemover(DAGCombiner &dc)
472 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
474 void NodeDeleted(SDNode *N, SDNode *E) override {
475 DC.removeFromWorklist(N);
480 //===----------------------------------------------------------------------===//
481 // TargetLowering::DAGCombinerInfo implementation
482 //===----------------------------------------------------------------------===//
484 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
485 ((DAGCombiner*)DC)->AddToWorklist(N);
488 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
489 ((DAGCombiner*)DC)->removeFromWorklist(N);
492 SDValue TargetLowering::DAGCombinerInfo::
493 CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo) {
494 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
497 SDValue TargetLowering::DAGCombinerInfo::
498 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
499 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
503 SDValue TargetLowering::DAGCombinerInfo::
504 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
505 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
508 void TargetLowering::DAGCombinerInfo::
509 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
510 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
513 //===----------------------------------------------------------------------===//
515 //===----------------------------------------------------------------------===//
517 void DAGCombiner::deleteAndRecombine(SDNode *N) {
518 removeFromWorklist(N);
520 // If the operands of this node are only used by the node, they will now be
521 // dead. Make sure to re-visit them and recursively delete dead nodes.
522 for (const SDValue &Op : N->ops())
523 // For an operand generating multiple values, one of the values may
524 // become dead allowing further simplification (e.g. split index
525 // arithmetic from an indexed load).
526 if (Op->hasOneUse() || Op->getNumValues() > 1)
527 AddToWorklist(Op.getNode());
532 /// Return 1 if we can compute the negated form of the specified expression for
533 /// the same cost as the expression itself, or 2 if we can compute the negated
534 /// form more cheaply than the expression itself.
535 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
536 const TargetLowering &TLI,
537 const TargetOptions *Options,
538 unsigned Depth = 0) {
539 // fneg is removable even if it has multiple uses.
540 if (Op.getOpcode() == ISD::FNEG) return 2;
542 // Don't allow anything with multiple uses.
543 if (!Op.hasOneUse()) return 0;
545 // Don't recurse exponentially.
546 if (Depth > 6) return 0;
548 switch (Op.getOpcode()) {
549 default: return false;
550 case ISD::ConstantFP:
551 // Don't invert constant FP values after legalize. The negated constant
552 // isn't necessarily legal.
553 return LegalOperations ? 0 : 1;
555 // FIXME: determine better conditions for this xform.
556 if (!Options->UnsafeFPMath) return 0;
558 // After operation legalization, it might not be legal to create new FSUBs.
559 if (LegalOperations &&
560 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
563 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
564 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
567 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
568 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
571 // We can't turn -(A-B) into B-A when we honor signed zeros.
572 if (!Options->UnsafeFPMath) return 0;
574 // fold (fneg (fsub A, B)) -> (fsub B, A)
579 if (Options->HonorSignDependentRoundingFPMath()) return 0;
581 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
582 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
586 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
592 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
597 /// If isNegatibleForFree returns true, return the newly negated expression.
598 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
599 bool LegalOperations, unsigned Depth = 0) {
600 const TargetOptions &Options = DAG.getTarget().Options;
601 // fneg is removable even if it has multiple uses.
602 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
604 // Don't allow anything with multiple uses.
605 assert(Op.hasOneUse() && "Unknown reuse!");
607 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
608 switch (Op.getOpcode()) {
609 default: llvm_unreachable("Unknown code");
610 case ISD::ConstantFP: {
611 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
613 return DAG.getConstantFP(V, SDLoc(Op), Op.getValueType());
616 // FIXME: determine better conditions for this xform.
617 assert(Options.UnsafeFPMath);
619 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
620 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
621 DAG.getTargetLoweringInfo(), &Options, Depth+1))
622 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
623 GetNegatedExpression(Op.getOperand(0), DAG,
624 LegalOperations, Depth+1),
626 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
627 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
628 GetNegatedExpression(Op.getOperand(1), DAG,
629 LegalOperations, Depth+1),
632 // We can't turn -(A-B) into B-A when we honor signed zeros.
633 assert(Options.UnsafeFPMath);
635 // fold (fneg (fsub 0, B)) -> B
636 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
638 return Op.getOperand(1);
640 // fold (fneg (fsub A, B)) -> (fsub B, A)
641 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
642 Op.getOperand(1), Op.getOperand(0));
646 assert(!Options.HonorSignDependentRoundingFPMath());
648 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
649 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
650 DAG.getTargetLoweringInfo(), &Options, Depth+1))
651 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
652 GetNegatedExpression(Op.getOperand(0), DAG,
653 LegalOperations, Depth+1),
656 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
657 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
659 GetNegatedExpression(Op.getOperand(1), DAG,
660 LegalOperations, Depth+1));
664 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
665 GetNegatedExpression(Op.getOperand(0), DAG,
666 LegalOperations, Depth+1));
668 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(),
669 GetNegatedExpression(Op.getOperand(0), DAG,
670 LegalOperations, Depth+1),
675 // Return true if this node is a setcc, or is a select_cc
676 // that selects between the target values used for true and false, making it
677 // equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to
678 // the appropriate nodes based on the type of node we are checking. This
679 // simplifies life a bit for the callers.
680 bool DAGCombiner::isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
682 if (N.getOpcode() == ISD::SETCC) {
683 LHS = N.getOperand(0);
684 RHS = N.getOperand(1);
685 CC = N.getOperand(2);
689 if (N.getOpcode() != ISD::SELECT_CC ||
690 !TLI.isConstTrueVal(N.getOperand(2).getNode()) ||
691 !TLI.isConstFalseVal(N.getOperand(3).getNode()))
694 if (TLI.getBooleanContents(N.getValueType()) ==
695 TargetLowering::UndefinedBooleanContent)
698 LHS = N.getOperand(0);
699 RHS = N.getOperand(1);
700 CC = N.getOperand(4);
704 /// Return true if this is a SetCC-equivalent operation with only one use.
705 /// If this is true, it allows the users to invert the operation for free when
706 /// it is profitable to do so.
707 bool DAGCombiner::isOneUseSetCC(SDValue N) const {
709 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
714 /// Returns true if N is a BUILD_VECTOR node whose
715 /// elements are all the same constant or undefined.
716 static bool isConstantSplatVector(SDNode *N, APInt& SplatValue) {
717 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(N);
722 unsigned SplatBitSize;
724 EVT EltVT = N->getValueType(0).getVectorElementType();
725 return (C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
727 EltVT.getSizeInBits() >= SplatBitSize);
730 // \brief Returns the SDNode if it is a constant integer BuildVector
731 // or constant integer.
732 static SDNode *isConstantIntBuildVectorOrConstantInt(SDValue N) {
733 if (isa<ConstantSDNode>(N))
735 if (ISD::isBuildVectorOfConstantSDNodes(N.getNode()))
740 // \brief Returns the SDNode if it is a constant float BuildVector
741 // or constant float.
742 static SDNode *isConstantFPBuildVectorOrConstantFP(SDValue N) {
743 if (isa<ConstantFPSDNode>(N))
745 if (ISD::isBuildVectorOfConstantFPSDNodes(N.getNode()))
750 // \brief Returns the SDNode if it is a constant splat BuildVector or constant
752 static ConstantSDNode *isConstOrConstSplat(SDValue N) {
753 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N))
756 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
757 BitVector UndefElements;
758 ConstantSDNode *CN = BV->getConstantSplatNode(&UndefElements);
760 // BuildVectors can truncate their operands. Ignore that case here.
761 // FIXME: We blindly ignore splats which include undef which is overly
763 if (CN && UndefElements.none() &&
764 CN->getValueType(0) == N.getValueType().getScalarType())
771 // \brief Returns the SDNode if it is a constant splat BuildVector or constant
773 static ConstantFPSDNode *isConstOrConstSplatFP(SDValue N) {
774 if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N))
777 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
778 BitVector UndefElements;
779 ConstantFPSDNode *CN = BV->getConstantFPSplatNode(&UndefElements);
781 if (CN && UndefElements.none())
788 SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDLoc DL,
789 SDValue N0, SDValue N1) {
790 EVT VT = N0.getValueType();
791 if (N0.getOpcode() == Opc) {
792 if (SDNode *L = isConstantIntBuildVectorOrConstantInt(N0.getOperand(1))) {
793 if (SDNode *R = isConstantIntBuildVectorOrConstantInt(N1)) {
794 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
795 if (SDValue OpNode = DAG.FoldConstantArithmetic(Opc, DL, VT, L, R))
796 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
799 if (N0.hasOneUse()) {
800 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one
802 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0.getOperand(0), N1);
803 if (!OpNode.getNode())
805 AddToWorklist(OpNode.getNode());
806 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
811 if (N1.getOpcode() == Opc) {
812 if (SDNode *R = isConstantIntBuildVectorOrConstantInt(N1.getOperand(1))) {
813 if (SDNode *L = isConstantIntBuildVectorOrConstantInt(N0)) {
814 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
815 if (SDValue OpNode = DAG.FoldConstantArithmetic(Opc, DL, VT, R, L))
816 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
819 if (N1.hasOneUse()) {
820 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one
822 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N1.getOperand(0), N0);
823 if (!OpNode.getNode())
825 AddToWorklist(OpNode.getNode());
826 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
834 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
836 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
838 DEBUG(dbgs() << "\nReplacing.1 ";
840 dbgs() << "\nWith: ";
841 To[0].getNode()->dump(&DAG);
842 dbgs() << " and " << NumTo-1 << " other values\n");
843 for (unsigned i = 0, e = NumTo; i != e; ++i)
844 assert((!To[i].getNode() ||
845 N->getValueType(i) == To[i].getValueType()) &&
846 "Cannot combine value to value of different type!");
848 WorklistRemover DeadNodes(*this);
849 DAG.ReplaceAllUsesWith(N, To);
851 // Push the new nodes and any users onto the worklist
852 for (unsigned i = 0, e = NumTo; i != e; ++i) {
853 if (To[i].getNode()) {
854 AddToWorklist(To[i].getNode());
855 AddUsersToWorklist(To[i].getNode());
860 // Finally, if the node is now dead, remove it from the graph. The node
861 // may not be dead if the replacement process recursively simplified to
862 // something else needing this node.
864 deleteAndRecombine(N);
865 return SDValue(N, 0);
869 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
870 // Replace all uses. If any nodes become isomorphic to other nodes and
871 // are deleted, make sure to remove them from our worklist.
872 WorklistRemover DeadNodes(*this);
873 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
875 // Push the new node and any (possibly new) users onto the worklist.
876 AddToWorklist(TLO.New.getNode());
877 AddUsersToWorklist(TLO.New.getNode());
879 // Finally, if the node is now dead, remove it from the graph. The node
880 // may not be dead if the replacement process recursively simplified to
881 // something else needing this node.
882 if (TLO.Old.getNode()->use_empty())
883 deleteAndRecombine(TLO.Old.getNode());
886 /// Check the specified integer node value to see if it can be simplified or if
887 /// things it uses can be simplified by bit propagation. If so, return true.
888 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
889 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
890 APInt KnownZero, KnownOne;
891 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
895 AddToWorklist(Op.getNode());
897 // Replace the old value with the new one.
899 DEBUG(dbgs() << "\nReplacing.2 ";
900 TLO.Old.getNode()->dump(&DAG);
901 dbgs() << "\nWith: ";
902 TLO.New.getNode()->dump(&DAG);
905 CommitTargetLoweringOpt(TLO);
909 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
911 EVT VT = Load->getValueType(0);
912 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
914 DEBUG(dbgs() << "\nReplacing.9 ";
916 dbgs() << "\nWith: ";
917 Trunc.getNode()->dump(&DAG);
919 WorklistRemover DeadNodes(*this);
920 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
921 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
922 deleteAndRecombine(Load);
923 AddToWorklist(Trunc.getNode());
926 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
929 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
930 EVT MemVT = LD->getMemoryVT();
931 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
932 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, PVT, MemVT) ? ISD::ZEXTLOAD
934 : LD->getExtensionType();
936 return DAG.getExtLoad(ExtType, dl, PVT,
937 LD->getChain(), LD->getBasePtr(),
938 MemVT, LD->getMemOperand());
941 unsigned Opc = Op.getOpcode();
944 case ISD::AssertSext:
945 return DAG.getNode(ISD::AssertSext, dl, PVT,
946 SExtPromoteOperand(Op.getOperand(0), PVT),
948 case ISD::AssertZext:
949 return DAG.getNode(ISD::AssertZext, dl, PVT,
950 ZExtPromoteOperand(Op.getOperand(0), PVT),
952 case ISD::Constant: {
954 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
955 return DAG.getNode(ExtOpc, dl, PVT, Op);
959 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
961 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
964 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
965 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
967 EVT OldVT = Op.getValueType();
969 bool Replace = false;
970 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
971 if (!NewOp.getNode())
973 AddToWorklist(NewOp.getNode());
976 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
977 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
978 DAG.getValueType(OldVT));
981 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
982 EVT OldVT = Op.getValueType();
984 bool Replace = false;
985 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
986 if (!NewOp.getNode())
988 AddToWorklist(NewOp.getNode());
991 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
992 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
995 /// Promote the specified integer binary operation if the target indicates it is
996 /// beneficial. e.g. On x86, it's usually better to promote i16 operations to
997 /// i32 since i16 instructions are longer.
998 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
999 if (!LegalOperations)
1002 EVT VT = Op.getValueType();
1003 if (VT.isVector() || !VT.isInteger())
1006 // If operation type is 'undesirable', e.g. i16 on x86, consider
1008 unsigned Opc = Op.getOpcode();
1009 if (TLI.isTypeDesirableForOp(Opc, VT))
1013 // Consult target whether it is a good idea to promote this operation and
1014 // what's the right type to promote it to.
1015 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1016 assert(PVT != VT && "Don't know what type to promote to!");
1018 bool Replace0 = false;
1019 SDValue N0 = Op.getOperand(0);
1020 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
1024 bool Replace1 = false;
1025 SDValue N1 = Op.getOperand(1);
1030 NN1 = PromoteOperand(N1, PVT, Replace1);
1035 AddToWorklist(NN0.getNode());
1037 AddToWorklist(NN1.getNode());
1040 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
1042 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
1044 DEBUG(dbgs() << "\nPromoting ";
1045 Op.getNode()->dump(&DAG));
1047 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1048 DAG.getNode(Opc, dl, PVT, NN0, NN1));
1053 /// Promote the specified integer shift operation if the target indicates it is
1054 /// beneficial. e.g. On x86, it's usually better to promote i16 operations to
1055 /// i32 since i16 instructions are longer.
1056 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
1057 if (!LegalOperations)
1060 EVT VT = Op.getValueType();
1061 if (VT.isVector() || !VT.isInteger())
1064 // If operation type is 'undesirable', e.g. i16 on x86, consider
1066 unsigned Opc = Op.getOpcode();
1067 if (TLI.isTypeDesirableForOp(Opc, VT))
1071 // Consult target whether it is a good idea to promote this operation and
1072 // what's the right type to promote it to.
1073 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1074 assert(PVT != VT && "Don't know what type to promote to!");
1076 bool Replace = false;
1077 SDValue N0 = Op.getOperand(0);
1078 if (Opc == ISD::SRA)
1079 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
1080 else if (Opc == ISD::SRL)
1081 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
1083 N0 = PromoteOperand(N0, PVT, Replace);
1087 AddToWorklist(N0.getNode());
1089 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
1091 DEBUG(dbgs() << "\nPromoting ";
1092 Op.getNode()->dump(&DAG));
1094 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1095 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
1100 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
1101 if (!LegalOperations)
1104 EVT VT = Op.getValueType();
1105 if (VT.isVector() || !VT.isInteger())
1108 // If operation type is 'undesirable', e.g. i16 on x86, consider
1110 unsigned Opc = Op.getOpcode();
1111 if (TLI.isTypeDesirableForOp(Opc, VT))
1115 // Consult target whether it is a good idea to promote this operation and
1116 // what's the right type to promote it to.
1117 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1118 assert(PVT != VT && "Don't know what type to promote to!");
1119 // fold (aext (aext x)) -> (aext x)
1120 // fold (aext (zext x)) -> (zext x)
1121 // fold (aext (sext x)) -> (sext x)
1122 DEBUG(dbgs() << "\nPromoting ";
1123 Op.getNode()->dump(&DAG));
1124 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0));
1129 bool DAGCombiner::PromoteLoad(SDValue Op) {
1130 if (!LegalOperations)
1133 EVT VT = Op.getValueType();
1134 if (VT.isVector() || !VT.isInteger())
1137 // If operation type is 'undesirable', e.g. i16 on x86, consider
1139 unsigned Opc = Op.getOpcode();
1140 if (TLI.isTypeDesirableForOp(Opc, VT))
1144 // Consult target whether it is a good idea to promote this operation and
1145 // what's the right type to promote it to.
1146 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1147 assert(PVT != VT && "Don't know what type to promote to!");
1150 SDNode *N = Op.getNode();
1151 LoadSDNode *LD = cast<LoadSDNode>(N);
1152 EVT MemVT = LD->getMemoryVT();
1153 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
1154 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, PVT, MemVT) ? ISD::ZEXTLOAD
1156 : LD->getExtensionType();
1157 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
1158 LD->getChain(), LD->getBasePtr(),
1159 MemVT, LD->getMemOperand());
1160 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
1162 DEBUG(dbgs() << "\nPromoting ";
1165 Result.getNode()->dump(&DAG);
1167 WorklistRemover DeadNodes(*this);
1168 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
1169 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
1170 deleteAndRecombine(N);
1171 AddToWorklist(Result.getNode());
1177 /// \brief Recursively delete a node which has no uses and any operands for
1178 /// which it is the only use.
1180 /// Note that this both deletes the nodes and removes them from the worklist.
1181 /// It also adds any nodes who have had a user deleted to the worklist as they
1182 /// may now have only one use and subject to other combines.
1183 bool DAGCombiner::recursivelyDeleteUnusedNodes(SDNode *N) {
1184 if (!N->use_empty())
1187 SmallSetVector<SDNode *, 16> Nodes;
1190 N = Nodes.pop_back_val();
1194 if (N->use_empty()) {
1195 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1196 Nodes.insert(N->getOperand(i).getNode());
1198 removeFromWorklist(N);
1203 } while (!Nodes.empty());
1207 //===----------------------------------------------------------------------===//
1208 // Main DAG Combiner implementation
1209 //===----------------------------------------------------------------------===//
1211 void DAGCombiner::Run(CombineLevel AtLevel) {
1212 // set the instance variables, so that the various visit routines may use it.
1214 LegalOperations = Level >= AfterLegalizeVectorOps;
1215 LegalTypes = Level >= AfterLegalizeTypes;
1217 // Add all the dag nodes to the worklist.
1218 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
1219 E = DAG.allnodes_end(); I != E; ++I)
1222 // Create a dummy node (which is not added to allnodes), that adds a reference
1223 // to the root node, preventing it from being deleted, and tracking any
1224 // changes of the root.
1225 HandleSDNode Dummy(DAG.getRoot());
1227 // while the worklist isn't empty, find a node and
1228 // try and combine it.
1229 while (!WorklistMap.empty()) {
1231 // The Worklist holds the SDNodes in order, but it may contain null entries.
1233 N = Worklist.pop_back_val();
1236 bool GoodWorklistEntry = WorklistMap.erase(N);
1237 (void)GoodWorklistEntry;
1238 assert(GoodWorklistEntry &&
1239 "Found a worklist entry without a corresponding map entry!");
1241 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1242 // N is deleted from the DAG, since they too may now be dead or may have a
1243 // reduced number of uses, allowing other xforms.
1244 if (recursivelyDeleteUnusedNodes(N))
1247 WorklistRemover DeadNodes(*this);
1249 // If this combine is running after legalizing the DAG, re-legalize any
1250 // nodes pulled off the worklist.
1251 if (Level == AfterLegalizeDAG) {
1252 SmallSetVector<SDNode *, 16> UpdatedNodes;
1253 bool NIsValid = DAG.LegalizeOp(N, UpdatedNodes);
1255 for (SDNode *LN : UpdatedNodes) {
1257 AddUsersToWorklist(LN);
1263 DEBUG(dbgs() << "\nCombining: "; N->dump(&DAG));
1265 // Add any operands of the new node which have not yet been combined to the
1266 // worklist as well. Because the worklist uniques things already, this
1267 // won't repeatedly process the same operand.
1268 CombinedNodes.insert(N);
1269 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1270 if (!CombinedNodes.count(N->getOperand(i).getNode()))
1271 AddToWorklist(N->getOperand(i).getNode());
1273 SDValue RV = combine(N);
1280 // If we get back the same node we passed in, rather than a new node or
1281 // zero, we know that the node must have defined multiple values and
1282 // CombineTo was used. Since CombineTo takes care of the worklist
1283 // mechanics for us, we have no work to do in this case.
1284 if (RV.getNode() == N)
1287 assert(N->getOpcode() != ISD::DELETED_NODE &&
1288 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1289 "Node was deleted but visit returned new node!");
1291 DEBUG(dbgs() << " ... into: ";
1292 RV.getNode()->dump(&DAG));
1294 // Transfer debug value.
1295 DAG.TransferDbgValues(SDValue(N, 0), RV);
1296 if (N->getNumValues() == RV.getNode()->getNumValues())
1297 DAG.ReplaceAllUsesWith(N, RV.getNode());
1299 assert(N->getValueType(0) == RV.getValueType() &&
1300 N->getNumValues() == 1 && "Type mismatch");
1302 DAG.ReplaceAllUsesWith(N, &OpV);
1305 // Push the new node and any users onto the worklist
1306 AddToWorklist(RV.getNode());
1307 AddUsersToWorklist(RV.getNode());
1309 // Finally, if the node is now dead, remove it from the graph. The node
1310 // may not be dead if the replacement process recursively simplified to
1311 // something else needing this node. This will also take care of adding any
1312 // operands which have lost a user to the worklist.
1313 recursivelyDeleteUnusedNodes(N);
1316 // If the root changed (e.g. it was a dead load, update the root).
1317 DAG.setRoot(Dummy.getValue());
1318 DAG.RemoveDeadNodes();
1321 SDValue DAGCombiner::visit(SDNode *N) {
1322 switch (N->getOpcode()) {
1324 case ISD::TokenFactor: return visitTokenFactor(N);
1325 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1326 case ISD::ADD: return visitADD(N);
1327 case ISD::SUB: return visitSUB(N);
1328 case ISD::ADDC: return visitADDC(N);
1329 case ISD::SUBC: return visitSUBC(N);
1330 case ISD::ADDE: return visitADDE(N);
1331 case ISD::SUBE: return visitSUBE(N);
1332 case ISD::MUL: return visitMUL(N);
1333 case ISD::SDIV: return visitSDIV(N);
1334 case ISD::UDIV: return visitUDIV(N);
1335 case ISD::SREM: return visitSREM(N);
1336 case ISD::UREM: return visitUREM(N);
1337 case ISD::MULHU: return visitMULHU(N);
1338 case ISD::MULHS: return visitMULHS(N);
1339 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1340 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1341 case ISD::SMULO: return visitSMULO(N);
1342 case ISD::UMULO: return visitUMULO(N);
1343 case ISD::SDIVREM: return visitSDIVREM(N);
1344 case ISD::UDIVREM: return visitUDIVREM(N);
1345 case ISD::AND: return visitAND(N);
1346 case ISD::OR: return visitOR(N);
1347 case ISD::XOR: return visitXOR(N);
1348 case ISD::SHL: return visitSHL(N);
1349 case ISD::SRA: return visitSRA(N);
1350 case ISD::SRL: return visitSRL(N);
1352 case ISD::ROTL: return visitRotate(N);
1353 case ISD::BSWAP: return visitBSWAP(N);
1354 case ISD::CTLZ: return visitCTLZ(N);
1355 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1356 case ISD::CTTZ: return visitCTTZ(N);
1357 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1358 case ISD::CTPOP: return visitCTPOP(N);
1359 case ISD::SELECT: return visitSELECT(N);
1360 case ISD::VSELECT: return visitVSELECT(N);
1361 case ISD::SELECT_CC: return visitSELECT_CC(N);
1362 case ISD::SETCC: return visitSETCC(N);
1363 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1364 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1365 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1366 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1367 case ISD::SIGN_EXTEND_VECTOR_INREG: return visitSIGN_EXTEND_VECTOR_INREG(N);
1368 case ISD::TRUNCATE: return visitTRUNCATE(N);
1369 case ISD::BITCAST: return visitBITCAST(N);
1370 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1371 case ISD::FADD: return visitFADD(N);
1372 case ISD::FSUB: return visitFSUB(N);
1373 case ISD::FMUL: return visitFMUL(N);
1374 case ISD::FMA: return visitFMA(N);
1375 case ISD::FDIV: return visitFDIV(N);
1376 case ISD::FREM: return visitFREM(N);
1377 case ISD::FSQRT: return visitFSQRT(N);
1378 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1379 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1380 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1381 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1382 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1383 case ISD::FP_ROUND: return visitFP_ROUND(N);
1384 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1385 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1386 case ISD::FNEG: return visitFNEG(N);
1387 case ISD::FABS: return visitFABS(N);
1388 case ISD::FFLOOR: return visitFFLOOR(N);
1389 case ISD::FMINNUM: return visitFMINNUM(N);
1390 case ISD::FMAXNUM: return visitFMAXNUM(N);
1391 case ISD::FCEIL: return visitFCEIL(N);
1392 case ISD::FTRUNC: return visitFTRUNC(N);
1393 case ISD::BRCOND: return visitBRCOND(N);
1394 case ISD::BR_CC: return visitBR_CC(N);
1395 case ISD::LOAD: return visitLOAD(N);
1396 case ISD::STORE: return visitSTORE(N);
1397 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1398 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1399 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1400 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1401 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1402 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1403 case ISD::SCALAR_TO_VECTOR: return visitSCALAR_TO_VECTOR(N);
1404 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N);
1405 case ISD::MGATHER: return visitMGATHER(N);
1406 case ISD::MLOAD: return visitMLOAD(N);
1407 case ISD::MSCATTER: return visitMSCATTER(N);
1408 case ISD::MSTORE: return visitMSTORE(N);
1409 case ISD::FP_TO_FP16: return visitFP_TO_FP16(N);
1414 SDValue DAGCombiner::combine(SDNode *N) {
1415 SDValue RV = visit(N);
1417 // If nothing happened, try a target-specific DAG combine.
1418 if (!RV.getNode()) {
1419 assert(N->getOpcode() != ISD::DELETED_NODE &&
1420 "Node was deleted but visit returned NULL!");
1422 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1423 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1425 // Expose the DAG combiner to the target combiner impls.
1426 TargetLowering::DAGCombinerInfo
1427 DagCombineInfo(DAG, Level, false, this);
1429 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1433 // If nothing happened still, try promoting the operation.
1434 if (!RV.getNode()) {
1435 switch (N->getOpcode()) {
1443 RV = PromoteIntBinOp(SDValue(N, 0));
1448 RV = PromoteIntShiftOp(SDValue(N, 0));
1450 case ISD::SIGN_EXTEND:
1451 case ISD::ZERO_EXTEND:
1452 case ISD::ANY_EXTEND:
1453 RV = PromoteExtend(SDValue(N, 0));
1456 if (PromoteLoad(SDValue(N, 0)))
1462 // If N is a commutative binary node, try commuting it to enable more
1464 if (!RV.getNode() && SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1465 N->getNumValues() == 1) {
1466 SDValue N0 = N->getOperand(0);
1467 SDValue N1 = N->getOperand(1);
1469 // Constant operands are canonicalized to RHS.
1470 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1471 SDValue Ops[] = {N1, N0};
1473 if (const auto *BinNode = dyn_cast<BinaryWithFlagsSDNode>(N)) {
1474 CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops,
1477 CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops);
1480 return SDValue(CSENode, 0);
1487 /// Given a node, return its input chain if it has one, otherwise return a null
1489 static SDValue getInputChainForNode(SDNode *N) {
1490 if (unsigned NumOps = N->getNumOperands()) {
1491 if (N->getOperand(0).getValueType() == MVT::Other)
1492 return N->getOperand(0);
1493 if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1494 return N->getOperand(NumOps-1);
1495 for (unsigned i = 1; i < NumOps-1; ++i)
1496 if (N->getOperand(i).getValueType() == MVT::Other)
1497 return N->getOperand(i);
1502 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1503 // If N has two operands, where one has an input chain equal to the other,
1504 // the 'other' chain is redundant.
1505 if (N->getNumOperands() == 2) {
1506 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1507 return N->getOperand(0);
1508 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1509 return N->getOperand(1);
1512 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1513 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1514 SmallPtrSet<SDNode*, 16> SeenOps;
1515 bool Changed = false; // If we should replace this token factor.
1517 // Start out with this token factor.
1520 // Iterate through token factors. The TFs grows when new token factors are
1522 for (unsigned i = 0; i < TFs.size(); ++i) {
1523 SDNode *TF = TFs[i];
1525 // Check each of the operands.
1526 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1527 SDValue Op = TF->getOperand(i);
1529 switch (Op.getOpcode()) {
1530 case ISD::EntryToken:
1531 // Entry tokens don't need to be added to the list. They are
1536 case ISD::TokenFactor:
1537 if (Op.hasOneUse() &&
1538 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1539 // Queue up for processing.
1540 TFs.push_back(Op.getNode());
1541 // Clean up in case the token factor is removed.
1542 AddToWorklist(Op.getNode());
1549 // Only add if it isn't already in the list.
1550 if (SeenOps.insert(Op.getNode()).second)
1561 // If we've changed things around then replace token factor.
1564 // The entry token is the only possible outcome.
1565 Result = DAG.getEntryNode();
1567 // New and improved token factor.
1568 Result = DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Ops);
1571 // Add users to worklist if AA is enabled, since it may introduce
1572 // a lot of new chained token factors while removing memory deps.
1573 bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA
1574 : DAG.getSubtarget().useAA();
1575 return CombineTo(N, Result, UseAA /*add to worklist*/);
1581 /// MERGE_VALUES can always be eliminated.
1582 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1583 WorklistRemover DeadNodes(*this);
1584 // Replacing results may cause a different MERGE_VALUES to suddenly
1585 // be CSE'd with N, and carry its uses with it. Iterate until no
1586 // uses remain, to ensure that the node can be safely deleted.
1587 // First add the users of this node to the work list so that they
1588 // can be tried again once they have new operands.
1589 AddUsersToWorklist(N);
1591 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1592 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i));
1593 } while (!N->use_empty());
1594 deleteAndRecombine(N);
1595 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1598 static bool isNullConstant(SDValue V) {
1599 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(V);
1600 return Const != nullptr && Const->isNullValue();
1603 static bool isNullFPConstant(SDValue V) {
1604 ConstantFPSDNode *Const = dyn_cast<ConstantFPSDNode>(V);
1605 return Const != nullptr && Const->isZero() && !Const->isNegative();
1608 static bool isAllOnesConstant(SDValue V) {
1609 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(V);
1610 return Const != nullptr && Const->isAllOnesValue();
1613 static bool isOneConstant(SDValue V) {
1614 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(V);
1615 return Const != nullptr && Const->isOne();
1618 /// If \p N is a ContantSDNode with isOpaque() == false return it casted to a
1619 /// ContantSDNode pointer else nullptr.
1620 static ConstantSDNode *getAsNonOpaqueConstant(SDValue N) {
1621 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N);
1622 return Const != nullptr && !Const->isOpaque() ? Const : nullptr;
1625 SDValue DAGCombiner::visitADD(SDNode *N) {
1626 SDValue N0 = N->getOperand(0);
1627 SDValue N1 = N->getOperand(1);
1628 EVT VT = N0.getValueType();
1631 if (VT.isVector()) {
1632 if (SDValue FoldedVOp = SimplifyVBinOp(N))
1635 // fold (add x, 0) -> x, vector edition
1636 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1638 if (ISD::isBuildVectorAllZeros(N0.getNode()))
1642 // fold (add x, undef) -> undef
1643 if (N0.getOpcode() == ISD::UNDEF)
1645 if (N1.getOpcode() == ISD::UNDEF)
1647 // fold (add c1, c2) -> c1+c2
1648 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
1649 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
1651 return DAG.FoldConstantArithmetic(ISD::ADD, SDLoc(N), VT, N0C, N1C);
1652 // canonicalize constant to RHS
1653 if (isConstantIntBuildVectorOrConstantInt(N0) &&
1654 !isConstantIntBuildVectorOrConstantInt(N1))
1655 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N1, N0);
1656 // fold (add x, 0) -> x
1657 if (isNullConstant(N1))
1659 // fold (add Sym, c) -> Sym+c
1660 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1661 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1662 GA->getOpcode() == ISD::GlobalAddress)
1663 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
1665 (uint64_t)N1C->getSExtValue());
1666 // fold ((c1-A)+c2) -> (c1+c2)-A
1667 if (N1C && N0.getOpcode() == ISD::SUB)
1668 if (ConstantSDNode *N0C = getAsNonOpaqueConstant(N0.getOperand(0))) {
1670 return DAG.getNode(ISD::SUB, DL, VT,
1671 DAG.getConstant(N1C->getAPIntValue()+
1672 N0C->getAPIntValue(), DL, VT),
1676 if (SDValue RADD = ReassociateOps(ISD::ADD, SDLoc(N), N0, N1))
1678 // fold ((0-A) + B) -> B-A
1679 if (N0.getOpcode() == ISD::SUB && isNullConstant(N0.getOperand(0)))
1680 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1, N0.getOperand(1));
1681 // fold (A + (0-B)) -> A-B
1682 if (N1.getOpcode() == ISD::SUB && isNullConstant(N1.getOperand(0)))
1683 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1.getOperand(1));
1684 // fold (A+(B-A)) -> B
1685 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1686 return N1.getOperand(0);
1687 // fold ((B-A)+A) -> B
1688 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1689 return N0.getOperand(0);
1690 // fold (A+(B-(A+C))) to (B-C)
1691 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1692 N0 == N1.getOperand(1).getOperand(0))
1693 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
1694 N1.getOperand(1).getOperand(1));
1695 // fold (A+(B-(C+A))) to (B-C)
1696 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1697 N0 == N1.getOperand(1).getOperand(1))
1698 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
1699 N1.getOperand(1).getOperand(0));
1700 // fold (A+((B-A)+or-C)) to (B+or-C)
1701 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1702 N1.getOperand(0).getOpcode() == ISD::SUB &&
1703 N0 == N1.getOperand(0).getOperand(1))
1704 return DAG.getNode(N1.getOpcode(), SDLoc(N), VT,
1705 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1707 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1708 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1709 SDValue N00 = N0.getOperand(0);
1710 SDValue N01 = N0.getOperand(1);
1711 SDValue N10 = N1.getOperand(0);
1712 SDValue N11 = N1.getOperand(1);
1714 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1715 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1716 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10),
1717 DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11));
1720 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1721 return SDValue(N, 0);
1723 // fold (a+b) -> (a|b) iff a and b share no bits.
1724 if (VT.isInteger() && !VT.isVector()) {
1725 APInt LHSZero, LHSOne;
1726 APInt RHSZero, RHSOne;
1727 DAG.computeKnownBits(N0, LHSZero, LHSOne);
1729 if (LHSZero.getBoolValue()) {
1730 DAG.computeKnownBits(N1, RHSZero, RHSOne);
1732 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1733 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1734 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero){
1735 if (!LegalOperations || TLI.isOperationLegal(ISD::OR, VT))
1736 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1);
1741 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1742 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB &&
1743 isNullConstant(N1.getOperand(0).getOperand(0)))
1744 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0,
1745 DAG.getNode(ISD::SHL, SDLoc(N), VT,
1746 N1.getOperand(0).getOperand(1),
1748 if (N0.getOpcode() == ISD::SHL && N0.getOperand(0).getOpcode() == ISD::SUB &&
1749 isNullConstant(N0.getOperand(0).getOperand(0)))
1750 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1,
1751 DAG.getNode(ISD::SHL, SDLoc(N), VT,
1752 N0.getOperand(0).getOperand(1),
1755 if (N1.getOpcode() == ISD::AND) {
1756 SDValue AndOp0 = N1.getOperand(0);
1757 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1758 unsigned DestBits = VT.getScalarType().getSizeInBits();
1760 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1761 // and similar xforms where the inner op is either ~0 or 0.
1762 if (NumSignBits == DestBits && isOneConstant(N1->getOperand(1))) {
1764 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1768 // add (sext i1), X -> sub X, (zext i1)
1769 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1770 N0.getOperand(0).getValueType() == MVT::i1 &&
1771 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1773 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1774 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1777 // add X, (sextinreg Y i1) -> sub X, (and Y 1)
1778 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
1779 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
1780 if (TN->getVT() == MVT::i1) {
1782 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
1783 DAG.getConstant(1, DL, VT));
1784 return DAG.getNode(ISD::SUB, DL, VT, N0, ZExt);
1791 SDValue DAGCombiner::visitADDC(SDNode *N) {
1792 SDValue N0 = N->getOperand(0);
1793 SDValue N1 = N->getOperand(1);
1794 EVT VT = N0.getValueType();
1796 // If the flag result is dead, turn this into an ADD.
1797 if (!N->hasAnyUseOfValue(1))
1798 return CombineTo(N, DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N1),
1799 DAG.getNode(ISD::CARRY_FALSE,
1800 SDLoc(N), MVT::Glue));
1802 // canonicalize constant to RHS.
1803 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1804 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1806 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N1, N0);
1808 // fold (addc x, 0) -> x + no carry out
1809 if (isNullConstant(N1))
1810 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1811 SDLoc(N), MVT::Glue));
1813 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1814 APInt LHSZero, LHSOne;
1815 APInt RHSZero, RHSOne;
1816 DAG.computeKnownBits(N0, LHSZero, LHSOne);
1818 if (LHSZero.getBoolValue()) {
1819 DAG.computeKnownBits(N1, RHSZero, RHSOne);
1821 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1822 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1823 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1824 return CombineTo(N, DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1),
1825 DAG.getNode(ISD::CARRY_FALSE,
1826 SDLoc(N), MVT::Glue));
1832 SDValue DAGCombiner::visitADDE(SDNode *N) {
1833 SDValue N0 = N->getOperand(0);
1834 SDValue N1 = N->getOperand(1);
1835 SDValue CarryIn = N->getOperand(2);
1837 // canonicalize constant to RHS
1838 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1839 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1841 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
1844 // fold (adde x, y, false) -> (addc x, y)
1845 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1846 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
1851 // Since it may not be valid to emit a fold to zero for vector initializers
1852 // check if we can before folding.
1853 static SDValue tryFoldToZero(SDLoc DL, const TargetLowering &TLI, EVT VT,
1855 bool LegalOperations, bool LegalTypes) {
1857 return DAG.getConstant(0, DL, VT);
1858 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
1859 return DAG.getConstant(0, DL, VT);
1863 SDValue DAGCombiner::visitSUB(SDNode *N) {
1864 SDValue N0 = N->getOperand(0);
1865 SDValue N1 = N->getOperand(1);
1866 EVT VT = N0.getValueType();
1869 if (VT.isVector()) {
1870 if (SDValue FoldedVOp = SimplifyVBinOp(N))
1873 // fold (sub x, 0) -> x, vector edition
1874 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1878 // fold (sub x, x) -> 0
1879 // FIXME: Refactor this and xor and other similar operations together.
1881 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations, LegalTypes);
1882 // fold (sub c1, c2) -> c1-c2
1883 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
1884 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
1886 return DAG.FoldConstantArithmetic(ISD::SUB, SDLoc(N), VT, N0C, N1C);
1887 // fold (sub x, c) -> (add x, -c)
1890 return DAG.getNode(ISD::ADD, DL, VT, N0,
1891 DAG.getConstant(-N1C->getAPIntValue(), DL, VT));
1893 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1894 if (isAllOnesConstant(N0))
1895 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
1896 // fold A-(A-B) -> B
1897 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1898 return N1.getOperand(1);
1899 // fold (A+B)-A -> B
1900 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1901 return N0.getOperand(1);
1902 // fold (A+B)-B -> A
1903 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1904 return N0.getOperand(0);
1905 // fold C2-(A+C1) -> (C2-C1)-A
1906 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? nullptr :
1907 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1908 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1910 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(),
1912 return DAG.getNode(ISD::SUB, DL, VT, NewC,
1915 // fold ((A+(B+or-C))-B) -> A+or-C
1916 if (N0.getOpcode() == ISD::ADD &&
1917 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1918 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1919 N0.getOperand(1).getOperand(0) == N1)
1920 return DAG.getNode(N0.getOperand(1).getOpcode(), SDLoc(N), VT,
1921 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1922 // fold ((A+(C+B))-B) -> A+C
1923 if (N0.getOpcode() == ISD::ADD &&
1924 N0.getOperand(1).getOpcode() == ISD::ADD &&
1925 N0.getOperand(1).getOperand(1) == N1)
1926 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
1927 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1928 // fold ((A-(B-C))-C) -> A-B
1929 if (N0.getOpcode() == ISD::SUB &&
1930 N0.getOperand(1).getOpcode() == ISD::SUB &&
1931 N0.getOperand(1).getOperand(1) == N1)
1932 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1933 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1935 // If either operand of a sub is undef, the result is undef
1936 if (N0.getOpcode() == ISD::UNDEF)
1938 if (N1.getOpcode() == ISD::UNDEF)
1941 // If the relocation model supports it, consider symbol offsets.
1942 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1943 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1944 // fold (sub Sym, c) -> Sym-c
1945 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1946 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
1948 (uint64_t)N1C->getSExtValue());
1949 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1950 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1951 if (GA->getGlobal() == GB->getGlobal())
1952 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1956 // sub X, (sextinreg Y i1) -> add X, (and Y 1)
1957 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
1958 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
1959 if (TN->getVT() == MVT::i1) {
1961 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
1962 DAG.getConstant(1, DL, VT));
1963 return DAG.getNode(ISD::ADD, DL, VT, N0, ZExt);
1970 SDValue DAGCombiner::visitSUBC(SDNode *N) {
1971 SDValue N0 = N->getOperand(0);
1972 SDValue N1 = N->getOperand(1);
1973 EVT VT = N0.getValueType();
1975 // If the flag result is dead, turn this into an SUB.
1976 if (!N->hasAnyUseOfValue(1))
1977 return CombineTo(N, DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1),
1978 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1981 // fold (subc x, x) -> 0 + no borrow
1984 return CombineTo(N, DAG.getConstant(0, DL, VT),
1985 DAG.getNode(ISD::CARRY_FALSE, DL,
1989 // fold (subc x, 0) -> x + no borrow
1990 if (isNullConstant(N1))
1991 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1994 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
1995 if (isAllOnesConstant(N0))
1996 return CombineTo(N, DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0),
1997 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
2003 SDValue DAGCombiner::visitSUBE(SDNode *N) {
2004 SDValue N0 = N->getOperand(0);
2005 SDValue N1 = N->getOperand(1);
2006 SDValue CarryIn = N->getOperand(2);
2008 // fold (sube x, y, false) -> (subc x, y)
2009 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
2010 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);
2015 SDValue DAGCombiner::visitMUL(SDNode *N) {
2016 SDValue N0 = N->getOperand(0);
2017 SDValue N1 = N->getOperand(1);
2018 EVT VT = N0.getValueType();
2020 // fold (mul x, undef) -> 0
2021 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2022 return DAG.getConstant(0, SDLoc(N), VT);
2024 bool N0IsConst = false;
2025 bool N1IsConst = false;
2026 bool N1IsOpaqueConst = false;
2027 bool N0IsOpaqueConst = false;
2028 APInt ConstValue0, ConstValue1;
2030 if (VT.isVector()) {
2031 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2034 N0IsConst = isConstantSplatVector(N0.getNode(), ConstValue0);
2035 N1IsConst = isConstantSplatVector(N1.getNode(), ConstValue1);
2037 N0IsConst = isa<ConstantSDNode>(N0);
2039 ConstValue0 = cast<ConstantSDNode>(N0)->getAPIntValue();
2040 N0IsOpaqueConst = cast<ConstantSDNode>(N0)->isOpaque();
2042 N1IsConst = isa<ConstantSDNode>(N1);
2044 ConstValue1 = cast<ConstantSDNode>(N1)->getAPIntValue();
2045 N1IsOpaqueConst = cast<ConstantSDNode>(N1)->isOpaque();
2049 // fold (mul c1, c2) -> c1*c2
2050 if (N0IsConst && N1IsConst && !N0IsOpaqueConst && !N1IsOpaqueConst)
2051 return DAG.FoldConstantArithmetic(ISD::MUL, SDLoc(N), VT,
2052 N0.getNode(), N1.getNode());
2054 // canonicalize constant to RHS (vector doesn't have to splat)
2055 if (isConstantIntBuildVectorOrConstantInt(N0) &&
2056 !isConstantIntBuildVectorOrConstantInt(N1))
2057 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
2058 // fold (mul x, 0) -> 0
2059 if (N1IsConst && ConstValue1 == 0)
2061 // We require a splat of the entire scalar bit width for non-contiguous
2064 ConstValue1.getBitWidth() == VT.getScalarType().getSizeInBits();
2065 // fold (mul x, 1) -> x
2066 if (N1IsConst && ConstValue1 == 1 && IsFullSplat)
2068 // fold (mul x, -1) -> 0-x
2069 if (N1IsConst && ConstValue1.isAllOnesValue()) {
2071 return DAG.getNode(ISD::SUB, DL, VT,
2072 DAG.getConstant(0, DL, VT), N0);
2074 // fold (mul x, (1 << c)) -> x << c
2075 if (N1IsConst && !N1IsOpaqueConst && ConstValue1.isPowerOf2() &&
2078 return DAG.getNode(ISD::SHL, DL, VT, N0,
2079 DAG.getConstant(ConstValue1.logBase2(), DL,
2080 getShiftAmountTy(N0.getValueType())));
2082 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
2083 if (N1IsConst && !N1IsOpaqueConst && (-ConstValue1).isPowerOf2() &&
2085 unsigned Log2Val = (-ConstValue1).logBase2();
2087 // FIXME: If the input is something that is easily negated (e.g. a
2088 // single-use add), we should put the negate there.
2089 return DAG.getNode(ISD::SUB, DL, VT,
2090 DAG.getConstant(0, DL, VT),
2091 DAG.getNode(ISD::SHL, DL, VT, N0,
2092 DAG.getConstant(Log2Val, DL,
2093 getShiftAmountTy(N0.getValueType()))));
2097 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
2098 if (N1IsConst && N0.getOpcode() == ISD::SHL &&
2099 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
2100 isa<ConstantSDNode>(N0.getOperand(1)))) {
2101 SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT,
2102 N1, N0.getOperand(1));
2103 AddToWorklist(C3.getNode());
2104 return DAG.getNode(ISD::MUL, SDLoc(N), VT,
2105 N0.getOperand(0), C3);
2108 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
2111 SDValue Sh(nullptr,0), Y(nullptr,0);
2112 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
2113 if (N0.getOpcode() == ISD::SHL &&
2114 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
2115 isa<ConstantSDNode>(N0.getOperand(1))) &&
2116 N0.getNode()->hasOneUse()) {
2118 } else if (N1.getOpcode() == ISD::SHL &&
2119 isa<ConstantSDNode>(N1.getOperand(1)) &&
2120 N1.getNode()->hasOneUse()) {
2125 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2126 Sh.getOperand(0), Y);
2127 return DAG.getNode(ISD::SHL, SDLoc(N), VT,
2128 Mul, Sh.getOperand(1));
2132 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
2133 if (N1IsConst && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
2134 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
2135 isa<ConstantSDNode>(N0.getOperand(1))))
2136 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
2137 DAG.getNode(ISD::MUL, SDLoc(N0), VT,
2138 N0.getOperand(0), N1),
2139 DAG.getNode(ISD::MUL, SDLoc(N1), VT,
2140 N0.getOperand(1), N1));
2143 if (SDValue RMUL = ReassociateOps(ISD::MUL, SDLoc(N), N0, N1))
2149 SDValue DAGCombiner::visitSDIV(SDNode *N) {
2150 SDValue N0 = N->getOperand(0);
2151 SDValue N1 = N->getOperand(1);
2152 EVT VT = N->getValueType(0);
2156 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2159 // fold (sdiv c1, c2) -> c1/c2
2160 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2161 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2162 if (N0C && N1C && !N0C->isOpaque() && !N1C->isOpaque())
2163 return DAG.FoldConstantArithmetic(ISD::SDIV, SDLoc(N), VT, N0C, N1C);
2164 // fold (sdiv X, 1) -> X
2165 if (N1C && N1C->isOne())
2167 // fold (sdiv X, -1) -> 0-X
2168 if (N1C && N1C->isAllOnesValue()) {
2170 return DAG.getNode(ISD::SUB, DL, VT,
2171 DAG.getConstant(0, DL, VT), N0);
2173 // If we know the sign bits of both operands are zero, strength reduce to a
2174 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
2175 if (!VT.isVector()) {
2176 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2177 return DAG.getNode(ISD::UDIV, SDLoc(N), N1.getValueType(),
2181 // fold (sdiv X, pow2) -> simple ops after legalize
2182 if (N1C && !N1C->isNullValue() && !N1C->isOpaque() &&
2183 (N1C->getAPIntValue().isPowerOf2() ||
2184 (-N1C->getAPIntValue()).isPowerOf2())) {
2185 // If dividing by powers of two is cheap, then don't perform the following
2187 if (TLI.isPow2SDivCheap())
2190 // Target-specific implementation of sdiv x, pow2.
2191 SDValue Res = BuildSDIVPow2(N);
2195 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
2198 // Splat the sign bit into the register
2200 DAG.getNode(ISD::SRA, DL, VT, N0,
2201 DAG.getConstant(VT.getScalarSizeInBits() - 1, DL,
2202 getShiftAmountTy(N0.getValueType())));
2203 AddToWorklist(SGN.getNode());
2205 // Add (N0 < 0) ? abs2 - 1 : 0;
2207 DAG.getNode(ISD::SRL, DL, VT, SGN,
2208 DAG.getConstant(VT.getScalarSizeInBits() - lg2, DL,
2209 getShiftAmountTy(SGN.getValueType())));
2210 SDValue ADD = DAG.getNode(ISD::ADD, DL, VT, N0, SRL);
2211 AddToWorklist(SRL.getNode());
2212 AddToWorklist(ADD.getNode()); // Divide by pow2
2213 SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, ADD,
2214 DAG.getConstant(lg2, DL,
2215 getShiftAmountTy(ADD.getValueType())));
2217 // If we're dividing by a positive value, we're done. Otherwise, we must
2218 // negate the result.
2219 if (N1C->getAPIntValue().isNonNegative())
2222 AddToWorklist(SRA.getNode());
2223 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA);
2226 // If integer divide is expensive and we satisfy the requirements, emit an
2227 // alternate sequence.
2228 if (N1C && !TLI.isIntDivCheap()) {
2229 SDValue Op = BuildSDIV(N);
2230 if (Op.getNode()) return Op;
2234 if (N0.getOpcode() == ISD::UNDEF)
2235 return DAG.getConstant(0, SDLoc(N), VT);
2236 // X / undef -> undef
2237 if (N1.getOpcode() == ISD::UNDEF)
2243 SDValue DAGCombiner::visitUDIV(SDNode *N) {
2244 SDValue N0 = N->getOperand(0);
2245 SDValue N1 = N->getOperand(1);
2246 EVT VT = N->getValueType(0);
2250 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2253 // fold (udiv c1, c2) -> c1/c2
2254 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2255 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2257 if (SDValue Folded = DAG.FoldConstantArithmetic(ISD::UDIV, SDLoc(N), VT,
2260 // fold (udiv x, (1 << c)) -> x >>u c
2261 if (N1C && !N1C->isOpaque() && N1C->getAPIntValue().isPowerOf2()) {
2263 return DAG.getNode(ISD::SRL, DL, VT, N0,
2264 DAG.getConstant(N1C->getAPIntValue().logBase2(), DL,
2265 getShiftAmountTy(N0.getValueType())));
2267 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
2268 if (N1.getOpcode() == ISD::SHL) {
2269 if (ConstantSDNode *SHC = getAsNonOpaqueConstant(N1.getOperand(0))) {
2270 if (SHC->getAPIntValue().isPowerOf2()) {
2271 EVT ADDVT = N1.getOperand(1).getValueType();
2273 SDValue Add = DAG.getNode(ISD::ADD, DL, ADDVT,
2275 DAG.getConstant(SHC->getAPIntValue()
2278 AddToWorklist(Add.getNode());
2279 return DAG.getNode(ISD::SRL, DL, VT, N0, Add);
2283 // fold (udiv x, c) -> alternate
2284 if (N1C && !TLI.isIntDivCheap()) {
2285 SDValue Op = BuildUDIV(N);
2286 if (Op.getNode()) return Op;
2290 if (N0.getOpcode() == ISD::UNDEF)
2291 return DAG.getConstant(0, SDLoc(N), VT);
2292 // X / undef -> undef
2293 if (N1.getOpcode() == ISD::UNDEF)
2299 SDValue DAGCombiner::visitSREM(SDNode *N) {
2300 SDValue N0 = N->getOperand(0);
2301 SDValue N1 = N->getOperand(1);
2302 EVT VT = N->getValueType(0);
2304 // fold (srem c1, c2) -> c1%c2
2305 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2306 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2308 if (SDValue Folded = DAG.FoldConstantArithmetic(ISD::SREM, SDLoc(N), VT,
2311 // If we know the sign bits of both operands are zero, strength reduce to a
2312 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
2313 if (!VT.isVector()) {
2314 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2315 return DAG.getNode(ISD::UREM, SDLoc(N), VT, N0, N1);
2318 // If X/C can be simplified by the division-by-constant logic, lower
2319 // X%C to the equivalent of X-X/C*C.
2320 if (N1C && !N1C->isNullValue()) {
2321 SDValue Div = DAG.getNode(ISD::SDIV, SDLoc(N), VT, N0, N1);
2322 AddToWorklist(Div.getNode());
2323 SDValue OptimizedDiv = combine(Div.getNode());
2324 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2325 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2327 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2328 AddToWorklist(Mul.getNode());
2334 if (N0.getOpcode() == ISD::UNDEF)
2335 return DAG.getConstant(0, SDLoc(N), VT);
2336 // X % undef -> undef
2337 if (N1.getOpcode() == ISD::UNDEF)
2343 SDValue DAGCombiner::visitUREM(SDNode *N) {
2344 SDValue N0 = N->getOperand(0);
2345 SDValue N1 = N->getOperand(1);
2346 EVT VT = N->getValueType(0);
2348 // fold (urem c1, c2) -> c1%c2
2349 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2350 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2352 if (SDValue Folded = DAG.FoldConstantArithmetic(ISD::UREM, SDLoc(N), VT,
2355 // fold (urem x, pow2) -> (and x, pow2-1)
2356 if (N1C && !N1C->isNullValue() && !N1C->isOpaque() &&
2357 N1C->getAPIntValue().isPowerOf2()) {
2359 return DAG.getNode(ISD::AND, DL, VT, N0,
2360 DAG.getConstant(N1C->getAPIntValue() - 1, DL, VT));
2362 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
2363 if (N1.getOpcode() == ISD::SHL) {
2364 if (ConstantSDNode *SHC = getAsNonOpaqueConstant(N1.getOperand(0))) {
2365 if (SHC->getAPIntValue().isPowerOf2()) {
2368 DAG.getNode(ISD::ADD, DL, VT, N1,
2369 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL,
2371 AddToWorklist(Add.getNode());
2372 return DAG.getNode(ISD::AND, DL, VT, N0, Add);
2377 // If X/C can be simplified by the division-by-constant logic, lower
2378 // X%C to the equivalent of X-X/C*C.
2379 if (N1C && !N1C->isNullValue()) {
2380 SDValue Div = DAG.getNode(ISD::UDIV, SDLoc(N), VT, N0, N1);
2381 AddToWorklist(Div.getNode());
2382 SDValue OptimizedDiv = combine(Div.getNode());
2383 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2384 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2386 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2387 AddToWorklist(Mul.getNode());
2393 if (N0.getOpcode() == ISD::UNDEF)
2394 return DAG.getConstant(0, SDLoc(N), VT);
2395 // X % undef -> undef
2396 if (N1.getOpcode() == ISD::UNDEF)
2402 SDValue DAGCombiner::visitMULHS(SDNode *N) {
2403 SDValue N0 = N->getOperand(0);
2404 SDValue N1 = N->getOperand(1);
2405 EVT VT = N->getValueType(0);
2408 // fold (mulhs x, 0) -> 0
2409 if (isNullConstant(N1))
2411 // fold (mulhs x, 1) -> (sra x, size(x)-1)
2412 if (isOneConstant(N1)) {
2414 return DAG.getNode(ISD::SRA, DL, N0.getValueType(), N0,
2415 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2417 getShiftAmountTy(N0.getValueType())));
2419 // fold (mulhs x, undef) -> 0
2420 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2421 return DAG.getConstant(0, SDLoc(N), VT);
2423 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2425 if (VT.isSimple() && !VT.isVector()) {
2426 MVT Simple = VT.getSimpleVT();
2427 unsigned SimpleSize = Simple.getSizeInBits();
2428 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2429 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2430 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2431 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2432 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2433 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2434 DAG.getConstant(SimpleSize, DL,
2435 getShiftAmountTy(N1.getValueType())));
2436 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2443 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2444 SDValue N0 = N->getOperand(0);
2445 SDValue N1 = N->getOperand(1);
2446 EVT VT = N->getValueType(0);
2449 // fold (mulhu x, 0) -> 0
2450 if (isNullConstant(N1))
2452 // fold (mulhu x, 1) -> 0
2453 if (isOneConstant(N1))
2454 return DAG.getConstant(0, DL, N0.getValueType());
2455 // fold (mulhu x, undef) -> 0
2456 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2457 return DAG.getConstant(0, DL, VT);
2459 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2461 if (VT.isSimple() && !VT.isVector()) {
2462 MVT Simple = VT.getSimpleVT();
2463 unsigned SimpleSize = Simple.getSizeInBits();
2464 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2465 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2466 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2467 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2468 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2469 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2470 DAG.getConstant(SimpleSize, DL,
2471 getShiftAmountTy(N1.getValueType())));
2472 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2479 /// Perform optimizations common to nodes that compute two values. LoOp and HiOp
2480 /// give the opcodes for the two computations that are being performed. Return
2481 /// true if a simplification was made.
2482 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2484 // If the high half is not needed, just compute the low half.
2485 bool HiExists = N->hasAnyUseOfValue(1);
2487 (!LegalOperations ||
2488 TLI.isOperationLegalOrCustom(LoOp, N->getValueType(0)))) {
2489 SDValue Res = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
2490 return CombineTo(N, Res, Res);
2493 // If the low half is not needed, just compute the high half.
2494 bool LoExists = N->hasAnyUseOfValue(0);
2496 (!LegalOperations ||
2497 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2498 SDValue Res = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
2499 return CombineTo(N, Res, Res);
2502 // If both halves are used, return as it is.
2503 if (LoExists && HiExists)
2506 // If the two computed results can be simplified separately, separate them.
2508 SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
2509 AddToWorklist(Lo.getNode());
2510 SDValue LoOpt = combine(Lo.getNode());
2511 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2512 (!LegalOperations ||
2513 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2514 return CombineTo(N, LoOpt, LoOpt);
2518 SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
2519 AddToWorklist(Hi.getNode());
2520 SDValue HiOpt = combine(Hi.getNode());
2521 if (HiOpt.getNode() && HiOpt != Hi &&
2522 (!LegalOperations ||
2523 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2524 return CombineTo(N, HiOpt, HiOpt);
2530 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2531 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2532 if (Res.getNode()) return Res;
2534 EVT VT = N->getValueType(0);
2537 // If the type is twice as wide is legal, transform the mulhu to a wider
2538 // multiply plus a shift.
2539 if (VT.isSimple() && !VT.isVector()) {
2540 MVT Simple = VT.getSimpleVT();
2541 unsigned SimpleSize = Simple.getSizeInBits();
2542 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2543 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2544 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2545 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2546 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2547 // Compute the high part as N1.
2548 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2549 DAG.getConstant(SimpleSize, DL,
2550 getShiftAmountTy(Lo.getValueType())));
2551 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2552 // Compute the low part as N0.
2553 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2554 return CombineTo(N, Lo, Hi);
2561 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2562 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2563 if (Res.getNode()) return Res;
2565 EVT VT = N->getValueType(0);
2568 // If the type is twice as wide is legal, transform the mulhu to a wider
2569 // multiply plus a shift.
2570 if (VT.isSimple() && !VT.isVector()) {
2571 MVT Simple = VT.getSimpleVT();
2572 unsigned SimpleSize = Simple.getSizeInBits();
2573 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2574 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2575 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2576 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2577 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2578 // Compute the high part as N1.
2579 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2580 DAG.getConstant(SimpleSize, DL,
2581 getShiftAmountTy(Lo.getValueType())));
2582 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2583 // Compute the low part as N0.
2584 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2585 return CombineTo(N, Lo, Hi);
2592 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2593 // (smulo x, 2) -> (saddo x, x)
2594 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2595 if (C2->getAPIntValue() == 2)
2596 return DAG.getNode(ISD::SADDO, SDLoc(N), N->getVTList(),
2597 N->getOperand(0), N->getOperand(0));
2602 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2603 // (umulo x, 2) -> (uaddo x, x)
2604 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2605 if (C2->getAPIntValue() == 2)
2606 return DAG.getNode(ISD::UADDO, SDLoc(N), N->getVTList(),
2607 N->getOperand(0), N->getOperand(0));
2612 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2613 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2614 if (Res.getNode()) return Res;
2619 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2620 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2621 if (Res.getNode()) return Res;
2626 /// If this is a binary operator with two operands of the same opcode, try to
2628 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2629 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2630 EVT VT = N0.getValueType();
2631 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2633 // Bail early if none of these transforms apply.
2634 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2636 // For each of OP in AND/OR/XOR:
2637 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2638 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2639 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2640 // fold (OP (bswap x), (bswap y)) -> (bswap (OP x, y))
2641 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2643 // do not sink logical op inside of a vector extend, since it may combine
2645 EVT Op0VT = N0.getOperand(0).getValueType();
2646 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2647 N0.getOpcode() == ISD::SIGN_EXTEND ||
2648 N0.getOpcode() == ISD::BSWAP ||
2649 // Avoid infinite looping with PromoteIntBinOp.
2650 (N0.getOpcode() == ISD::ANY_EXTEND &&
2651 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2652 (N0.getOpcode() == ISD::TRUNCATE &&
2653 (!TLI.isZExtFree(VT, Op0VT) ||
2654 !TLI.isTruncateFree(Op0VT, VT)) &&
2655 TLI.isTypeLegal(Op0VT))) &&
2657 Op0VT == N1.getOperand(0).getValueType() &&
2658 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2659 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2660 N0.getOperand(0).getValueType(),
2661 N0.getOperand(0), N1.getOperand(0));
2662 AddToWorklist(ORNode.getNode());
2663 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, ORNode);
2666 // For each of OP in SHL/SRL/SRA/AND...
2667 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2668 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2669 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2670 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2671 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2672 N0.getOperand(1) == N1.getOperand(1)) {
2673 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2674 N0.getOperand(0).getValueType(),
2675 N0.getOperand(0), N1.getOperand(0));
2676 AddToWorklist(ORNode.getNode());
2677 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
2678 ORNode, N0.getOperand(1));
2681 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
2682 // Only perform this optimization after type legalization and before
2683 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
2684 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
2685 // we don't want to undo this promotion.
2686 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
2688 if ((N0.getOpcode() == ISD::BITCAST ||
2689 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) &&
2690 Level == AfterLegalizeTypes) {
2691 SDValue In0 = N0.getOperand(0);
2692 SDValue In1 = N1.getOperand(0);
2693 EVT In0Ty = In0.getValueType();
2694 EVT In1Ty = In1.getValueType();
2696 // If both incoming values are integers, and the original types are the
2698 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) {
2699 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1);
2700 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op);
2701 AddToWorklist(Op.getNode());
2706 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
2707 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
2708 // If both shuffles use the same mask, and both shuffle within a single
2709 // vector, then it is worthwhile to move the swizzle after the operation.
2710 // The type-legalizer generates this pattern when loading illegal
2711 // vector types from memory. In many cases this allows additional shuffle
2713 // There are other cases where moving the shuffle after the xor/and/or
2714 // is profitable even if shuffles don't perform a swizzle.
2715 // If both shuffles use the same mask, and both shuffles have the same first
2716 // or second operand, then it might still be profitable to move the shuffle
2717 // after the xor/and/or operation.
2718 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) {
2719 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
2720 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
2722 assert(N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType() &&
2723 "Inputs to shuffles are not the same type");
2725 // Check that both shuffles use the same mask. The masks are known to be of
2726 // the same length because the result vector type is the same.
2727 // Check also that shuffles have only one use to avoid introducing extra
2729 if (SVN0->hasOneUse() && SVN1->hasOneUse() &&
2730 SVN0->getMask().equals(SVN1->getMask())) {
2731 SDValue ShOp = N0->getOperand(1);
2733 // Don't try to fold this node if it requires introducing a
2734 // build vector of all zeros that might be illegal at this stage.
2735 if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) {
2737 ShOp = DAG.getConstant(0, SDLoc(N), VT);
2742 // (AND (shuf (A, C), shuf (B, C)) -> shuf (AND (A, B), C)
2743 // (OR (shuf (A, C), shuf (B, C)) -> shuf (OR (A, B), C)
2744 // (XOR (shuf (A, C), shuf (B, C)) -> shuf (XOR (A, B), V_0)
2745 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
2746 SDValue NewNode = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
2747 N0->getOperand(0), N1->getOperand(0));
2748 AddToWorklist(NewNode.getNode());
2749 return DAG.getVectorShuffle(VT, SDLoc(N), NewNode, ShOp,
2750 &SVN0->getMask()[0]);
2753 // Don't try to fold this node if it requires introducing a
2754 // build vector of all zeros that might be illegal at this stage.
2755 ShOp = N0->getOperand(0);
2756 if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) {
2758 ShOp = DAG.getConstant(0, SDLoc(N), VT);
2763 // (AND (shuf (C, A), shuf (C, B)) -> shuf (C, AND (A, B))
2764 // (OR (shuf (C, A), shuf (C, B)) -> shuf (C, OR (A, B))
2765 // (XOR (shuf (C, A), shuf (C, B)) -> shuf (V_0, XOR (A, B))
2766 if (N0->getOperand(0) == N1->getOperand(0) && ShOp.getNode()) {
2767 SDValue NewNode = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
2768 N0->getOperand(1), N1->getOperand(1));
2769 AddToWorklist(NewNode.getNode());
2770 return DAG.getVectorShuffle(VT, SDLoc(N), ShOp, NewNode,
2771 &SVN0->getMask()[0]);
2779 /// This contains all DAGCombine rules which reduce two values combined by
2780 /// an And operation to a single value. This makes them reusable in the context
2781 /// of visitSELECT(). Rules involving constants are not included as
2782 /// visitSELECT() already handles those cases.
2783 SDValue DAGCombiner::visitANDLike(SDValue N0, SDValue N1,
2784 SDNode *LocReference) {
2785 EVT VT = N1.getValueType();
2787 // fold (and x, undef) -> 0
2788 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2789 return DAG.getConstant(0, SDLoc(LocReference), VT);
2790 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2791 SDValue LL, LR, RL, RR, CC0, CC1;
2792 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2793 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2794 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2796 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2797 LL.getValueType().isInteger()) {
2798 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2799 if (isNullConstant(LR) && Op1 == ISD::SETEQ) {
2800 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2801 LR.getValueType(), LL, RL);
2802 AddToWorklist(ORNode.getNode());
2803 return DAG.getSetCC(SDLoc(LocReference), VT, ORNode, LR, Op1);
2805 if (isAllOnesConstant(LR)) {
2806 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2807 if (Op1 == ISD::SETEQ) {
2808 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(N0),
2809 LR.getValueType(), LL, RL);
2810 AddToWorklist(ANDNode.getNode());
2811 return DAG.getSetCC(SDLoc(LocReference), VT, ANDNode, LR, Op1);
2813 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2814 if (Op1 == ISD::SETGT) {
2815 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2816 LR.getValueType(), LL, RL);
2817 AddToWorklist(ORNode.getNode());
2818 return DAG.getSetCC(SDLoc(LocReference), VT, ORNode, LR, Op1);
2822 // Simplify (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2)
2823 if (LL == RL && isa<ConstantSDNode>(LR) && isa<ConstantSDNode>(RR) &&
2824 Op0 == Op1 && LL.getValueType().isInteger() &&
2825 Op0 == ISD::SETNE && ((isNullConstant(LR) && isAllOnesConstant(RR)) ||
2826 (isAllOnesConstant(LR) && isNullConstant(RR)))) {
2828 SDValue ADDNode = DAG.getNode(ISD::ADD, DL, LL.getValueType(),
2829 LL, DAG.getConstant(1, DL,
2830 LL.getValueType()));
2831 AddToWorklist(ADDNode.getNode());
2832 return DAG.getSetCC(SDLoc(LocReference), VT, ADDNode,
2833 DAG.getConstant(2, DL, LL.getValueType()),
2836 // canonicalize equivalent to ll == rl
2837 if (LL == RR && LR == RL) {
2838 Op1 = ISD::getSetCCSwappedOperands(Op1);
2841 if (LL == RL && LR == RR) {
2842 bool isInteger = LL.getValueType().isInteger();
2843 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2844 if (Result != ISD::SETCC_INVALID &&
2845 (!LegalOperations ||
2846 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
2847 TLI.isOperationLegal(ISD::SETCC,
2848 getSetCCResultType(N0.getSimpleValueType())))))
2849 return DAG.getSetCC(SDLoc(LocReference), N0.getValueType(),
2854 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
2855 VT.getSizeInBits() <= 64) {
2856 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2857 APInt ADDC = ADDI->getAPIntValue();
2858 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2859 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
2860 // immediate for an add, but it is legal if its top c2 bits are set,
2861 // transform the ADD so the immediate doesn't need to be materialized
2863 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
2864 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
2865 SRLI->getZExtValue());
2866 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
2868 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2871 DAG.getNode(ISD::ADD, DL, VT,
2872 N0.getOperand(0), DAG.getConstant(ADDC, DL, VT));
2873 CombineTo(N0.getNode(), NewAdd);
2874 // Return N so it doesn't get rechecked!
2875 return SDValue(LocReference, 0);
2886 SDValue DAGCombiner::visitAND(SDNode *N) {
2887 SDValue N0 = N->getOperand(0);
2888 SDValue N1 = N->getOperand(1);
2889 EVT VT = N1.getValueType();
2892 if (VT.isVector()) {
2893 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2896 // fold (and x, 0) -> 0, vector edition
2897 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2898 // do not return N0, because undef node may exist in N0
2899 return DAG.getConstant(
2900 APInt::getNullValue(
2901 N0.getValueType().getScalarType().getSizeInBits()),
2902 SDLoc(N), N0.getValueType());
2903 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2904 // do not return N1, because undef node may exist in N1
2905 return DAG.getConstant(
2906 APInt::getNullValue(
2907 N1.getValueType().getScalarType().getSizeInBits()),
2908 SDLoc(N), N1.getValueType());
2910 // fold (and x, -1) -> x, vector edition
2911 if (ISD::isBuildVectorAllOnes(N0.getNode()))
2913 if (ISD::isBuildVectorAllOnes(N1.getNode()))
2917 // fold (and c1, c2) -> c1&c2
2918 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
2919 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2920 if (N0C && N1C && !N1C->isOpaque())
2921 return DAG.FoldConstantArithmetic(ISD::AND, SDLoc(N), VT, N0C, N1C);
2922 // canonicalize constant to RHS
2923 if (isConstantIntBuildVectorOrConstantInt(N0) &&
2924 !isConstantIntBuildVectorOrConstantInt(N1))
2925 return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
2926 // fold (and x, -1) -> x
2927 if (isAllOnesConstant(N1))
2929 // if (and x, c) is known to be zero, return 0
2930 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2931 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2932 APInt::getAllOnesValue(BitWidth)))
2933 return DAG.getConstant(0, SDLoc(N), VT);
2935 if (SDValue RAND = ReassociateOps(ISD::AND, SDLoc(N), N0, N1))
2937 // fold (and (or x, C), D) -> D if (C & D) == D
2938 if (N1C && N0.getOpcode() == ISD::OR)
2939 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2940 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2942 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2943 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2944 SDValue N0Op0 = N0.getOperand(0);
2945 APInt Mask = ~N1C->getAPIntValue();
2946 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2947 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2948 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
2949 N0.getValueType(), N0Op0);
2951 // Replace uses of the AND with uses of the Zero extend node.
2954 // We actually want to replace all uses of the any_extend with the
2955 // zero_extend, to avoid duplicating things. This will later cause this
2956 // AND to be folded.
2957 CombineTo(N0.getNode(), Zext);
2958 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2961 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
2962 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
2963 // already be zero by virtue of the width of the base type of the load.
2965 // the 'X' node here can either be nothing or an extract_vector_elt to catch
2967 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
2968 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
2969 N0.getOpcode() == ISD::LOAD) {
2970 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
2971 N0 : N0.getOperand(0) );
2973 // Get the constant (if applicable) the zero'th operand is being ANDed with.
2974 // This can be a pure constant or a vector splat, in which case we treat the
2975 // vector as a scalar and use the splat value.
2976 APInt Constant = APInt::getNullValue(1);
2977 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
2978 Constant = C->getAPIntValue();
2979 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
2980 APInt SplatValue, SplatUndef;
2981 unsigned SplatBitSize;
2983 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
2984 SplatBitSize, HasAnyUndefs);
2986 // Undef bits can contribute to a possible optimisation if set, so
2988 SplatValue |= SplatUndef;
2990 // The splat value may be something like "0x00FFFFFF", which means 0 for
2991 // the first vector value and FF for the rest, repeating. We need a mask
2992 // that will apply equally to all members of the vector, so AND all the
2993 // lanes of the constant together.
2994 EVT VT = Vector->getValueType(0);
2995 unsigned BitWidth = VT.getVectorElementType().getSizeInBits();
2997 // If the splat value has been compressed to a bitlength lower
2998 // than the size of the vector lane, we need to re-expand it to
3000 if (BitWidth > SplatBitSize)
3001 for (SplatValue = SplatValue.zextOrTrunc(BitWidth);
3002 SplatBitSize < BitWidth;
3003 SplatBitSize = SplatBitSize * 2)
3004 SplatValue |= SplatValue.shl(SplatBitSize);
3006 // Make sure that variable 'Constant' is only set if 'SplatBitSize' is a
3007 // multiple of 'BitWidth'. Otherwise, we could propagate a wrong value.
3008 if (SplatBitSize % BitWidth == 0) {
3009 Constant = APInt::getAllOnesValue(BitWidth);
3010 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i)
3011 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
3016 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
3017 // actually legal and isn't going to get expanded, else this is a false
3019 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
3020 Load->getValueType(0),
3021 Load->getMemoryVT());
3023 // Resize the constant to the same size as the original memory access before
3024 // extension. If it is still the AllOnesValue then this AND is completely
3027 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits());
3030 switch (Load->getExtensionType()) {
3031 default: B = false; break;
3032 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
3034 case ISD::NON_EXTLOAD: B = true; break;
3037 if (B && Constant.isAllOnesValue()) {
3038 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
3039 // preserve semantics once we get rid of the AND.
3040 SDValue NewLoad(Load, 0);
3041 if (Load->getExtensionType() == ISD::EXTLOAD) {
3042 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
3043 Load->getValueType(0), SDLoc(Load),
3044 Load->getChain(), Load->getBasePtr(),
3045 Load->getOffset(), Load->getMemoryVT(),
3046 Load->getMemOperand());
3047 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
3048 if (Load->getNumValues() == 3) {
3049 // PRE/POST_INC loads have 3 values.
3050 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
3051 NewLoad.getValue(2) };
3052 CombineTo(Load, To, 3, true);
3054 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
3058 // Fold the AND away, taking care not to fold to the old load node if we
3060 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
3062 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3066 // fold (and (load x), 255) -> (zextload x, i8)
3067 // fold (and (extload x, i16), 255) -> (zextload x, i8)
3068 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
3069 if (N1C && (N0.getOpcode() == ISD::LOAD ||
3070 (N0.getOpcode() == ISD::ANY_EXTEND &&
3071 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
3072 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
3073 LoadSDNode *LN0 = HasAnyExt
3074 ? cast<LoadSDNode>(N0.getOperand(0))
3075 : cast<LoadSDNode>(N0);
3076 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
3077 LN0->isUnindexed() && N0.hasOneUse() && SDValue(LN0, 0).hasOneUse()) {
3078 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
3079 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
3080 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
3081 EVT LoadedVT = LN0->getMemoryVT();
3082 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
3084 if (ExtVT == LoadedVT &&
3085 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy,
3089 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
3090 LN0->getChain(), LN0->getBasePtr(), ExtVT,
3091 LN0->getMemOperand());
3093 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
3094 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3097 // Do not change the width of a volatile load.
3098 // Do not generate loads of non-round integer types since these can
3099 // be expensive (and would be wrong if the type is not byte sized).
3100 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
3101 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy,
3103 EVT PtrType = LN0->getOperand(1).getValueType();
3105 unsigned Alignment = LN0->getAlignment();
3106 SDValue NewPtr = LN0->getBasePtr();
3108 // For big endian targets, we need to add an offset to the pointer
3109 // to load the correct bytes. For little endian systems, we merely
3110 // need to read fewer bytes from the same pointer.
3111 if (TLI.isBigEndian()) {
3112 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
3113 unsigned EVTStoreBytes = ExtVT.getStoreSize();
3114 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
3116 NewPtr = DAG.getNode(ISD::ADD, DL, PtrType,
3117 NewPtr, DAG.getConstant(PtrOff, DL, PtrType));
3118 Alignment = MinAlign(Alignment, PtrOff);
3121 AddToWorklist(NewPtr.getNode());
3124 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
3125 LN0->getChain(), NewPtr,
3126 LN0->getPointerInfo(),
3127 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
3128 LN0->isInvariant(), Alignment, LN0->getAAInfo());
3130 CombineTo(LN0, Load, Load.getValue(1));
3131 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3137 if (SDValue Combined = visitANDLike(N0, N1, N))
3140 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
3141 if (N0.getOpcode() == N1.getOpcode()) {
3142 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3143 if (Tmp.getNode()) return Tmp;
3146 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
3147 // fold (and (sra)) -> (and (srl)) when possible.
3148 if (!VT.isVector() &&
3149 SimplifyDemandedBits(SDValue(N, 0)))
3150 return SDValue(N, 0);
3152 // fold (zext_inreg (extload x)) -> (zextload x)
3153 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
3154 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3155 EVT MemVT = LN0->getMemoryVT();
3156 // If we zero all the possible extended bits, then we can turn this into
3157 // a zextload if we are running before legalize or the operation is legal.
3158 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
3159 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
3160 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
3161 ((!LegalOperations && !LN0->isVolatile()) ||
3162 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
3163 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
3164 LN0->getChain(), LN0->getBasePtr(),
3165 MemVT, LN0->getMemOperand());
3167 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3168 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3171 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
3172 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3174 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3175 EVT MemVT = LN0->getMemoryVT();
3176 // If we zero all the possible extended bits, then we can turn this into
3177 // a zextload if we are running before legalize or the operation is legal.
3178 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
3179 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
3180 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
3181 ((!LegalOperations && !LN0->isVolatile()) ||
3182 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
3183 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
3184 LN0->getChain(), LN0->getBasePtr(),
3185 MemVT, LN0->getMemOperand());
3187 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3188 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3191 // fold (and (or (srl N, 8), (shl N, 8)), 0xffff) -> (srl (bswap N), const)
3192 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
3193 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
3194 N0.getOperand(1), false);
3195 if (BSwap.getNode())
3202 /// Match (a >> 8) | (a << 8) as (bswap a) >> 16.
3203 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
3204 bool DemandHighBits) {
3205 if (!LegalOperations)
3208 EVT VT = N->getValueType(0);
3209 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
3211 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
3214 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
3215 bool LookPassAnd0 = false;
3216 bool LookPassAnd1 = false;
3217 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
3219 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
3221 if (N0.getOpcode() == ISD::AND) {
3222 if (!N0.getNode()->hasOneUse())
3224 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3225 if (!N01C || N01C->getZExtValue() != 0xFF00)
3227 N0 = N0.getOperand(0);
3228 LookPassAnd0 = true;
3231 if (N1.getOpcode() == ISD::AND) {
3232 if (!N1.getNode()->hasOneUse())
3234 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
3235 if (!N11C || N11C->getZExtValue() != 0xFF)
3237 N1 = N1.getOperand(0);
3238 LookPassAnd1 = true;
3241 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
3243 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
3245 if (!N0.getNode()->hasOneUse() ||
3246 !N1.getNode()->hasOneUse())
3249 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3250 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
3253 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
3256 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
3257 SDValue N00 = N0->getOperand(0);
3258 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
3259 if (!N00.getNode()->hasOneUse())
3261 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
3262 if (!N001C || N001C->getZExtValue() != 0xFF)
3264 N00 = N00.getOperand(0);
3265 LookPassAnd0 = true;
3268 SDValue N10 = N1->getOperand(0);
3269 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
3270 if (!N10.getNode()->hasOneUse())
3272 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
3273 if (!N101C || N101C->getZExtValue() != 0xFF00)
3275 N10 = N10.getOperand(0);
3276 LookPassAnd1 = true;
3282 // Make sure everything beyond the low halfword gets set to zero since the SRL
3283 // 16 will clear the top bits.
3284 unsigned OpSizeInBits = VT.getSizeInBits();
3285 if (DemandHighBits && OpSizeInBits > 16) {
3286 // If the left-shift isn't masked out then the only way this is a bswap is
3287 // if all bits beyond the low 8 are 0. In that case the entire pattern
3288 // reduces to a left shift anyway: leave it for other parts of the combiner.
3292 // However, if the right shift isn't masked out then it might be because
3293 // it's not needed. See if we can spot that too.
3294 if (!LookPassAnd1 &&
3295 !DAG.MaskedValueIsZero(
3296 N10, APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - 16)))
3300 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00);
3301 if (OpSizeInBits > 16) {
3303 Res = DAG.getNode(ISD::SRL, DL, VT, Res,
3304 DAG.getConstant(OpSizeInBits - 16, DL,
3305 getShiftAmountTy(VT)));
3310 /// Return true if the specified node is an element that makes up a 32-bit
3311 /// packed halfword byteswap.
3312 /// ((x & 0x000000ff) << 8) |
3313 /// ((x & 0x0000ff00) >> 8) |
3314 /// ((x & 0x00ff0000) << 8) |
3315 /// ((x & 0xff000000) >> 8)
3316 static bool isBSwapHWordElement(SDValue N, MutableArrayRef<SDNode *> Parts) {
3317 if (!N.getNode()->hasOneUse())
3320 unsigned Opc = N.getOpcode();
3321 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
3324 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3329 switch (N1C->getZExtValue()) {
3332 case 0xFF: Num = 0; break;
3333 case 0xFF00: Num = 1; break;
3334 case 0xFF0000: Num = 2; break;
3335 case 0xFF000000: Num = 3; break;
3338 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
3339 SDValue N0 = N.getOperand(0);
3340 if (Opc == ISD::AND) {
3341 if (Num == 0 || Num == 2) {
3343 // (x >> 8) & 0xff0000
3344 if (N0.getOpcode() != ISD::SRL)
3346 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3347 if (!C || C->getZExtValue() != 8)
3350 // (x << 8) & 0xff00
3351 // (x << 8) & 0xff000000
3352 if (N0.getOpcode() != ISD::SHL)
3354 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3355 if (!C || C->getZExtValue() != 8)
3358 } else if (Opc == ISD::SHL) {
3360 // (x & 0xff0000) << 8
3361 if (Num != 0 && Num != 2)
3363 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3364 if (!C || C->getZExtValue() != 8)
3366 } else { // Opc == ISD::SRL
3367 // (x & 0xff00) >> 8
3368 // (x & 0xff000000) >> 8
3369 if (Num != 1 && Num != 3)
3371 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3372 if (!C || C->getZExtValue() != 8)
3379 Parts[Num] = N0.getOperand(0).getNode();
3383 /// Match a 32-bit packed halfword bswap. That is
3384 /// ((x & 0x000000ff) << 8) |
3385 /// ((x & 0x0000ff00) >> 8) |
3386 /// ((x & 0x00ff0000) << 8) |
3387 /// ((x & 0xff000000) >> 8)
3388 /// => (rotl (bswap x), 16)
3389 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
3390 if (!LegalOperations)
3393 EVT VT = N->getValueType(0);
3396 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
3400 // (or (or (and), (and)), (or (and), (and)))
3401 // (or (or (or (and), (and)), (and)), (and))
3402 if (N0.getOpcode() != ISD::OR)
3404 SDValue N00 = N0.getOperand(0);
3405 SDValue N01 = N0.getOperand(1);
3406 SDNode *Parts[4] = {};
3408 if (N1.getOpcode() == ISD::OR &&
3409 N00.getNumOperands() == 2 && N01.getNumOperands() == 2) {
3410 // (or (or (and), (and)), (or (and), (and)))
3411 SDValue N000 = N00.getOperand(0);
3412 if (!isBSwapHWordElement(N000, Parts))
3415 SDValue N001 = N00.getOperand(1);
3416 if (!isBSwapHWordElement(N001, Parts))
3418 SDValue N010 = N01.getOperand(0);
3419 if (!isBSwapHWordElement(N010, Parts))
3421 SDValue N011 = N01.getOperand(1);
3422 if (!isBSwapHWordElement(N011, Parts))
3425 // (or (or (or (and), (and)), (and)), (and))
3426 if (!isBSwapHWordElement(N1, Parts))
3428 if (!isBSwapHWordElement(N01, Parts))
3430 if (N00.getOpcode() != ISD::OR)
3432 SDValue N000 = N00.getOperand(0);
3433 if (!isBSwapHWordElement(N000, Parts))
3435 SDValue N001 = N00.getOperand(1);
3436 if (!isBSwapHWordElement(N001, Parts))
3440 // Make sure the parts are all coming from the same node.
3441 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
3445 SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT,
3446 SDValue(Parts[0], 0));
3448 // Result of the bswap should be rotated by 16. If it's not legal, then
3449 // do (x << 16) | (x >> 16).
3450 SDValue ShAmt = DAG.getConstant(16, DL, getShiftAmountTy(VT));
3451 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
3452 return DAG.getNode(ISD::ROTL, DL, VT, BSwap, ShAmt);
3453 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
3454 return DAG.getNode(ISD::ROTR, DL, VT, BSwap, ShAmt);
3455 return DAG.getNode(ISD::OR, DL, VT,
3456 DAG.getNode(ISD::SHL, DL, VT, BSwap, ShAmt),
3457 DAG.getNode(ISD::SRL, DL, VT, BSwap, ShAmt));
3460 /// This contains all DAGCombine rules which reduce two values combined by
3461 /// an Or operation to a single value \see visitANDLike().
3462 SDValue DAGCombiner::visitORLike(SDValue N0, SDValue N1, SDNode *LocReference) {
3463 EVT VT = N1.getValueType();
3464 // fold (or x, undef) -> -1
3465 if (!LegalOperations &&
3466 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
3467 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
3468 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()),
3469 SDLoc(LocReference), VT);
3471 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
3472 SDValue LL, LR, RL, RR, CC0, CC1;
3473 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
3474 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
3475 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
3477 if (LR == RR && Op0 == Op1 && LL.getValueType().isInteger()) {
3478 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
3479 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
3480 if (isNullConstant(LR) && (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
3481 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(LR),
3482 LR.getValueType(), LL, RL);
3483 AddToWorklist(ORNode.getNode());
3484 return DAG.getSetCC(SDLoc(LocReference), VT, ORNode, LR, Op1);
3486 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
3487 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
3488 if (isAllOnesConstant(LR) && (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
3489 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(LR),
3490 LR.getValueType(), LL, RL);
3491 AddToWorklist(ANDNode.getNode());
3492 return DAG.getSetCC(SDLoc(LocReference), VT, ANDNode, LR, Op1);
3495 // canonicalize equivalent to ll == rl
3496 if (LL == RR && LR == RL) {
3497 Op1 = ISD::getSetCCSwappedOperands(Op1);
3500 if (LL == RL && LR == RR) {
3501 bool isInteger = LL.getValueType().isInteger();
3502 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
3503 if (Result != ISD::SETCC_INVALID &&
3504 (!LegalOperations ||
3505 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
3506 TLI.isOperationLegal(ISD::SETCC,
3507 getSetCCResultType(N0.getValueType())))))
3508 return DAG.getSetCC(SDLoc(LocReference), N0.getValueType(),
3513 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
3514 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND &&
3515 // Don't increase # computations.
3516 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3517 // We can only do this xform if we know that bits from X that are set in C2
3518 // but not in C1 are already zero. Likewise for Y.
3519 if (const ConstantSDNode *N0O1C =
3520 getAsNonOpaqueConstant(N0.getOperand(1))) {
3521 if (const ConstantSDNode *N1O1C =
3522 getAsNonOpaqueConstant(N1.getOperand(1))) {
3523 // We can only do this xform if we know that bits from X that are set in
3524 // C2 but not in C1 are already zero. Likewise for Y.
3525 const APInt &LHSMask = N0O1C->getAPIntValue();
3526 const APInt &RHSMask = N1O1C->getAPIntValue();
3528 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
3529 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
3530 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
3531 N0.getOperand(0), N1.getOperand(0));
3532 SDLoc DL(LocReference);
3533 return DAG.getNode(ISD::AND, DL, VT, X,
3534 DAG.getConstant(LHSMask | RHSMask, DL, VT));
3540 // (or (and X, M), (and X, N)) -> (and X, (or M, N))
3541 if (N0.getOpcode() == ISD::AND &&
3542 N1.getOpcode() == ISD::AND &&
3543 N0.getOperand(0) == N1.getOperand(0) &&
3544 // Don't increase # computations.
3545 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3546 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
3547 N0.getOperand(1), N1.getOperand(1));
3548 return DAG.getNode(ISD::AND, SDLoc(LocReference), VT, N0.getOperand(0), X);
3554 SDValue DAGCombiner::visitOR(SDNode *N) {
3555 SDValue N0 = N->getOperand(0);
3556 SDValue N1 = N->getOperand(1);
3557 EVT VT = N1.getValueType();
3560 if (VT.isVector()) {
3561 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3564 // fold (or x, 0) -> x, vector edition
3565 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3567 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3570 // fold (or x, -1) -> -1, vector edition
3571 if (ISD::isBuildVectorAllOnes(N0.getNode()))
3572 // do not return N0, because undef node may exist in N0
3573 return DAG.getConstant(
3574 APInt::getAllOnesValue(
3575 N0.getValueType().getScalarType().getSizeInBits()),
3576 SDLoc(N), N0.getValueType());
3577 if (ISD::isBuildVectorAllOnes(N1.getNode()))
3578 // do not return N1, because undef node may exist in N1
3579 return DAG.getConstant(
3580 APInt::getAllOnesValue(
3581 N1.getValueType().getScalarType().getSizeInBits()),
3582 SDLoc(N), N1.getValueType());
3584 // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
3585 // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
3586 // Do this only if the resulting shuffle is legal.
3587 if (isa<ShuffleVectorSDNode>(N0) &&
3588 isa<ShuffleVectorSDNode>(N1) &&
3589 // Avoid folding a node with illegal type.
3590 TLI.isTypeLegal(VT) &&
3591 N0->getOperand(1) == N1->getOperand(1) &&
3592 ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode())) {
3593 bool CanFold = true;
3594 unsigned NumElts = VT.getVectorNumElements();
3595 const ShuffleVectorSDNode *SV0 = cast<ShuffleVectorSDNode>(N0);
3596 const ShuffleVectorSDNode *SV1 = cast<ShuffleVectorSDNode>(N1);
3597 // We construct two shuffle masks:
3598 // - Mask1 is a shuffle mask for a shuffle with N0 as the first operand
3599 // and N1 as the second operand.
3600 // - Mask2 is a shuffle mask for a shuffle with N1 as the first operand
3601 // and N0 as the second operand.
3602 // We do this because OR is commutable and therefore there might be
3603 // two ways to fold this node into a shuffle.
3604 SmallVector<int,4> Mask1;
3605 SmallVector<int,4> Mask2;
3607 for (unsigned i = 0; i != NumElts && CanFold; ++i) {
3608 int M0 = SV0->getMaskElt(i);
3609 int M1 = SV1->getMaskElt(i);
3611 // Both shuffle indexes are undef. Propagate Undef.
3612 if (M0 < 0 && M1 < 0) {
3613 Mask1.push_back(M0);
3614 Mask2.push_back(M0);
3618 if (M0 < 0 || M1 < 0 ||
3619 (M0 < (int)NumElts && M1 < (int)NumElts) ||
3620 (M0 >= (int)NumElts && M1 >= (int)NumElts)) {
3625 Mask1.push_back(M0 < (int)NumElts ? M0 : M1 + NumElts);
3626 Mask2.push_back(M1 < (int)NumElts ? M1 : M0 + NumElts);
3630 // Fold this sequence only if the resulting shuffle is 'legal'.
3631 if (TLI.isShuffleMaskLegal(Mask1, VT))
3632 return DAG.getVectorShuffle(VT, SDLoc(N), N0->getOperand(0),
3633 N1->getOperand(0), &Mask1[0]);
3634 if (TLI.isShuffleMaskLegal(Mask2, VT))
3635 return DAG.getVectorShuffle(VT, SDLoc(N), N1->getOperand(0),
3636 N0->getOperand(0), &Mask2[0]);
3641 // fold (or c1, c2) -> c1|c2
3642 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
3643 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3644 if (N0C && N1C && !N1C->isOpaque())
3645 return DAG.FoldConstantArithmetic(ISD::OR, SDLoc(N), VT, N0C, N1C);
3646 // canonicalize constant to RHS
3647 if (isConstantIntBuildVectorOrConstantInt(N0) &&
3648 !isConstantIntBuildVectorOrConstantInt(N1))
3649 return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0);
3650 // fold (or x, 0) -> x
3651 if (isNullConstant(N1))
3653 // fold (or x, -1) -> -1
3654 if (isAllOnesConstant(N1))
3656 // fold (or x, c) -> c iff (x & ~c) == 0
3657 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
3660 if (SDValue Combined = visitORLike(N0, N1, N))
3663 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
3664 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
3665 if (BSwap.getNode())
3667 BSwap = MatchBSwapHWordLow(N, N0, N1);
3668 if (BSwap.getNode())
3672 if (SDValue ROR = ReassociateOps(ISD::OR, SDLoc(N), N0, N1))
3674 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
3675 // iff (c1 & c2) == 0.
3676 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3677 isa<ConstantSDNode>(N0.getOperand(1))) {
3678 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
3679 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) {
3680 if (SDValue COR = DAG.FoldConstantArithmetic(ISD::OR, SDLoc(N1), VT,
3683 ISD::AND, SDLoc(N), VT,
3684 DAG.getNode(ISD::OR, SDLoc(N0), VT, N0.getOperand(0), N1), COR);
3688 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
3689 if (N0.getOpcode() == N1.getOpcode()) {
3690 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3691 if (Tmp.getNode()) return Tmp;
3694 // See if this is some rotate idiom.
3695 if (SDNode *Rot = MatchRotate(N0, N1, SDLoc(N)))
3696 return SDValue(Rot, 0);
3698 // Simplify the operands using demanded-bits information.
3699 if (!VT.isVector() &&
3700 SimplifyDemandedBits(SDValue(N, 0)))
3701 return SDValue(N, 0);
3706 /// Match "(X shl/srl V1) & V2" where V2 may not be present.
3707 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
3708 if (Op.getOpcode() == ISD::AND) {
3709 if (isa<ConstantSDNode>(Op.getOperand(1))) {
3710 Mask = Op.getOperand(1);
3711 Op = Op.getOperand(0);
3717 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3725 // Return true if we can prove that, whenever Neg and Pos are both in the
3726 // range [0, OpSize), Neg == (Pos == 0 ? 0 : OpSize - Pos). This means that
3727 // for two opposing shifts shift1 and shift2 and a value X with OpBits bits:
3729 // (or (shift1 X, Neg), (shift2 X, Pos))
3731 // reduces to a rotate in direction shift2 by Pos or (equivalently) a rotate
3732 // in direction shift1 by Neg. The range [0, OpSize) means that we only need
3733 // to consider shift amounts with defined behavior.
3734 static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned OpSize) {
3735 // If OpSize is a power of 2 then:
3737 // (a) (Pos == 0 ? 0 : OpSize - Pos) == (OpSize - Pos) & (OpSize - 1)
3738 // (b) Neg == Neg & (OpSize - 1) whenever Neg is in [0, OpSize).
3740 // So if OpSize is a power of 2 and Neg is (and Neg', OpSize-1), we check
3741 // for the stronger condition:
3743 // Neg & (OpSize - 1) == (OpSize - Pos) & (OpSize - 1) [A]
3745 // for all Neg and Pos. Since Neg & (OpSize - 1) == Neg' & (OpSize - 1)
3746 // we can just replace Neg with Neg' for the rest of the function.
3748 // In other cases we check for the even stronger condition:
3750 // Neg == OpSize - Pos [B]
3752 // for all Neg and Pos. Note that the (or ...) then invokes undefined
3753 // behavior if Pos == 0 (and consequently Neg == OpSize).
3755 // We could actually use [A] whenever OpSize is a power of 2, but the
3756 // only extra cases that it would match are those uninteresting ones
3757 // where Neg and Pos are never in range at the same time. E.g. for
3758 // OpSize == 32, using [A] would allow a Neg of the form (sub 64, Pos)
3759 // as well as (sub 32, Pos), but:
3761 // (or (shift1 X, (sub 64, Pos)), (shift2 X, Pos))
3763 // always invokes undefined behavior for 32-bit X.
3765 // Below, Mask == OpSize - 1 when using [A] and is all-ones otherwise.
3766 unsigned MaskLoBits = 0;
3767 if (Neg.getOpcode() == ISD::AND &&
3768 isPowerOf2_64(OpSize) &&
3769 Neg.getOperand(1).getOpcode() == ISD::Constant &&
3770 cast<ConstantSDNode>(Neg.getOperand(1))->getAPIntValue() == OpSize - 1) {
3771 Neg = Neg.getOperand(0);
3772 MaskLoBits = Log2_64(OpSize);
3775 // Check whether Neg has the form (sub NegC, NegOp1) for some NegC and NegOp1.
3776 if (Neg.getOpcode() != ISD::SUB)
3778 ConstantSDNode *NegC = dyn_cast<ConstantSDNode>(Neg.getOperand(0));
3781 SDValue NegOp1 = Neg.getOperand(1);
3783 // On the RHS of [A], if Pos is Pos' & (OpSize - 1), just replace Pos with
3784 // Pos'. The truncation is redundant for the purpose of the equality.
3786 Pos.getOpcode() == ISD::AND &&
3787 Pos.getOperand(1).getOpcode() == ISD::Constant &&
3788 cast<ConstantSDNode>(Pos.getOperand(1))->getAPIntValue() == OpSize - 1)
3789 Pos = Pos.getOperand(0);
3791 // The condition we need is now:
3793 // (NegC - NegOp1) & Mask == (OpSize - Pos) & Mask
3795 // If NegOp1 == Pos then we need:
3797 // OpSize & Mask == NegC & Mask
3799 // (because "x & Mask" is a truncation and distributes through subtraction).
3802 Width = NegC->getAPIntValue();
3803 // Check for cases where Pos has the form (add NegOp1, PosC) for some PosC.
3804 // Then the condition we want to prove becomes:
3806 // (NegC - NegOp1) & Mask == (OpSize - (NegOp1 + PosC)) & Mask
3808 // which, again because "x & Mask" is a truncation, becomes:
3810 // NegC & Mask == (OpSize - PosC) & Mask
3811 // OpSize & Mask == (NegC + PosC) & Mask
3812 else if (Pos.getOpcode() == ISD::ADD &&
3813 Pos.getOperand(0) == NegOp1 &&
3814 Pos.getOperand(1).getOpcode() == ISD::Constant)
3815 Width = (cast<ConstantSDNode>(Pos.getOperand(1))->getAPIntValue() +
3816 NegC->getAPIntValue());
3820 // Now we just need to check that OpSize & Mask == Width & Mask.
3822 // Opsize & Mask is 0 since Mask is Opsize - 1.
3823 return Width.getLoBits(MaskLoBits) == 0;
3824 return Width == OpSize;
3827 // A subroutine of MatchRotate used once we have found an OR of two opposite
3828 // shifts of Shifted. If Neg == <operand size> - Pos then the OR reduces
3829 // to both (PosOpcode Shifted, Pos) and (NegOpcode Shifted, Neg), with the
3830 // former being preferred if supported. InnerPos and InnerNeg are Pos and
3831 // Neg with outer conversions stripped away.
3832 SDNode *DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos,
3833 SDValue Neg, SDValue InnerPos,
3834 SDValue InnerNeg, unsigned PosOpcode,
3835 unsigned NegOpcode, SDLoc DL) {
3836 // fold (or (shl x, (*ext y)),
3837 // (srl x, (*ext (sub 32, y)))) ->
3838 // (rotl x, y) or (rotr x, (sub 32, y))
3840 // fold (or (shl x, (*ext (sub 32, y))),
3841 // (srl x, (*ext y))) ->
3842 // (rotr x, y) or (rotl x, (sub 32, y))
3843 EVT VT = Shifted.getValueType();
3844 if (matchRotateSub(InnerPos, InnerNeg, VT.getSizeInBits())) {
3845 bool HasPos = TLI.isOperationLegalOrCustom(PosOpcode, VT);
3846 return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, Shifted,
3847 HasPos ? Pos : Neg).getNode();
3853 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
3854 // idioms for rotate, and if the target supports rotation instructions, generate
3856 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL) {
3857 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
3858 EVT VT = LHS.getValueType();
3859 if (!TLI.isTypeLegal(VT)) return nullptr;
3861 // The target must have at least one rotate flavor.
3862 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
3863 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
3864 if (!HasROTL && !HasROTR) return nullptr;
3866 // Match "(X shl/srl V1) & V2" where V2 may not be present.
3867 SDValue LHSShift; // The shift.
3868 SDValue LHSMask; // AND value if any.
3869 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
3870 return nullptr; // Not part of a rotate.
3872 SDValue RHSShift; // The shift.
3873 SDValue RHSMask; // AND value if any.
3874 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
3875 return nullptr; // Not part of a rotate.
3877 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
3878 return nullptr; // Not shifting the same value.
3880 if (LHSShift.getOpcode() == RHSShift.getOpcode())
3881 return nullptr; // Shifts must disagree.
3883 // Canonicalize shl to left side in a shl/srl pair.
3884 if (RHSShift.getOpcode() == ISD::SHL) {
3885 std::swap(LHS, RHS);
3886 std::swap(LHSShift, RHSShift);
3887 std::swap(LHSMask , RHSMask );
3890 unsigned OpSizeInBits = VT.getSizeInBits();
3891 SDValue LHSShiftArg = LHSShift.getOperand(0);
3892 SDValue LHSShiftAmt = LHSShift.getOperand(1);
3893 SDValue RHSShiftArg = RHSShift.getOperand(0);
3894 SDValue RHSShiftAmt = RHSShift.getOperand(1);
3896 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
3897 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
3898 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
3899 RHSShiftAmt.getOpcode() == ISD::Constant) {
3900 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
3901 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
3902 if ((LShVal + RShVal) != OpSizeInBits)
3905 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3906 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt);
3908 // If there is an AND of either shifted operand, apply it to the result.
3909 if (LHSMask.getNode() || RHSMask.getNode()) {
3910 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
3912 if (LHSMask.getNode()) {
3913 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
3914 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
3916 if (RHSMask.getNode()) {
3917 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
3918 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
3921 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, DL, VT));
3924 return Rot.getNode();
3927 // If there is a mask here, and we have a variable shift, we can't be sure
3928 // that we're masking out the right stuff.
3929 if (LHSMask.getNode() || RHSMask.getNode())
3932 // If the shift amount is sign/zext/any-extended just peel it off.
3933 SDValue LExtOp0 = LHSShiftAmt;
3934 SDValue RExtOp0 = RHSShiftAmt;
3935 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3936 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3937 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3938 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3939 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3940 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3941 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3942 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3943 LExtOp0 = LHSShiftAmt.getOperand(0);
3944 RExtOp0 = RHSShiftAmt.getOperand(0);
3947 SDNode *TryL = MatchRotatePosNeg(LHSShiftArg, LHSShiftAmt, RHSShiftAmt,
3948 LExtOp0, RExtOp0, ISD::ROTL, ISD::ROTR, DL);
3952 SDNode *TryR = MatchRotatePosNeg(RHSShiftArg, RHSShiftAmt, LHSShiftAmt,
3953 RExtOp0, LExtOp0, ISD::ROTR, ISD::ROTL, DL);
3960 SDValue DAGCombiner::visitXOR(SDNode *N) {
3961 SDValue N0 = N->getOperand(0);
3962 SDValue N1 = N->getOperand(1);
3963 EVT VT = N0.getValueType();
3966 if (VT.isVector()) {
3967 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3970 // fold (xor x, 0) -> x, vector edition
3971 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3973 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3977 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3978 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3979 return DAG.getConstant(0, SDLoc(N), VT);
3980 // fold (xor x, undef) -> undef
3981 if (N0.getOpcode() == ISD::UNDEF)
3983 if (N1.getOpcode() == ISD::UNDEF)
3985 // fold (xor c1, c2) -> c1^c2
3986 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
3987 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
3989 return DAG.FoldConstantArithmetic(ISD::XOR, SDLoc(N), VT, N0C, N1C);
3990 // canonicalize constant to RHS
3991 if (isConstantIntBuildVectorOrConstantInt(N0) &&
3992 !isConstantIntBuildVectorOrConstantInt(N1))
3993 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
3994 // fold (xor x, 0) -> x
3995 if (isNullConstant(N1))
3998 if (SDValue RXOR = ReassociateOps(ISD::XOR, SDLoc(N), N0, N1))
4001 // fold !(x cc y) -> (x !cc y)
4002 SDValue LHS, RHS, CC;
4003 if (TLI.isConstTrueVal(N1.getNode()) && isSetCCEquivalent(N0, LHS, RHS, CC)) {
4004 bool isInt = LHS.getValueType().isInteger();
4005 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
4008 if (!LegalOperations ||
4009 TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) {
4010 switch (N0.getOpcode()) {
4012 llvm_unreachable("Unhandled SetCC Equivalent!");
4014 return DAG.getSetCC(SDLoc(N), VT, LHS, RHS, NotCC);
4015 case ISD::SELECT_CC:
4016 return DAG.getSelectCC(SDLoc(N), LHS, RHS, N0.getOperand(2),
4017 N0.getOperand(3), NotCC);
4022 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
4023 if (isOneConstant(N1) && N0.getOpcode() == ISD::ZERO_EXTEND &&
4024 N0.getNode()->hasOneUse() &&
4025 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
4026 SDValue V = N0.getOperand(0);
4028 V = DAG.getNode(ISD::XOR, DL, V.getValueType(), V,
4029 DAG.getConstant(1, DL, V.getValueType()));
4030 AddToWorklist(V.getNode());
4031 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, V);
4034 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
4035 if (isOneConstant(N1) && VT == MVT::i1 &&
4036 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
4037 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
4038 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
4039 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
4040 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
4041 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
4042 AddToWorklist(LHS.getNode()); AddToWorklist(RHS.getNode());
4043 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
4046 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
4047 if (isAllOnesConstant(N1) &&
4048 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
4049 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
4050 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
4051 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
4052 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
4053 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
4054 AddToWorklist(LHS.getNode()); AddToWorklist(RHS.getNode());
4055 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
4058 // fold (xor (and x, y), y) -> (and (not x), y)
4059 if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
4060 N0->getOperand(1) == N1) {
4061 SDValue X = N0->getOperand(0);
4062 SDValue NotX = DAG.getNOT(SDLoc(X), X, VT);
4063 AddToWorklist(NotX.getNode());
4064 return DAG.getNode(ISD::AND, SDLoc(N), VT, NotX, N1);
4066 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
4067 if (N1C && N0.getOpcode() == ISD::XOR) {
4068 if (const ConstantSDNode *N00C = getAsNonOpaqueConstant(N0.getOperand(0))) {
4070 return DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(1),
4071 DAG.getConstant(N1C->getAPIntValue() ^
4072 N00C->getAPIntValue(), DL, VT));
4074 if (const ConstantSDNode *N01C = getAsNonOpaqueConstant(N0.getOperand(1))) {
4076 return DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(0),
4077 DAG.getConstant(N1C->getAPIntValue() ^
4078 N01C->getAPIntValue(), DL, VT));
4081 // fold (xor x, x) -> 0
4083 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations, LegalTypes);
4085 // fold (xor (shl 1, x), -1) -> (rotl ~1, x)
4086 // Here is a concrete example of this equivalence:
4088 // i16 shl == 1 << 14 == 16384 == 0b0100000000000000
4089 // i16 xor == ~(1 << 14) == 49151 == 0b1011111111111111
4093 // i16 ~1 == 0b1111111111111110
4094 // i16 rol(~1, 14) == 0b1011111111111111
4096 // Some additional tips to help conceptualize this transform:
4097 // - Try to see the operation as placing a single zero in a value of all ones.
4098 // - There exists no value for x which would allow the result to contain zero.
4099 // - Values of x larger than the bitwidth are undefined and do not require a
4100 // consistent result.
4101 // - Pushing the zero left requires shifting one bits in from the right.
4102 // A rotate left of ~1 is a nice way of achieving the desired result.
4103 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT) && N0.getOpcode() == ISD::SHL
4104 && isAllOnesConstant(N1) && isOneConstant(N0.getOperand(0))) {
4106 return DAG.getNode(ISD::ROTL, DL, VT, DAG.getConstant(~1, DL, VT),
4110 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
4111 if (N0.getOpcode() == N1.getOpcode()) {
4112 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
4113 if (Tmp.getNode()) return Tmp;
4116 // Simplify the expression using non-local knowledge.
4117 if (!VT.isVector() &&
4118 SimplifyDemandedBits(SDValue(N, 0)))
4119 return SDValue(N, 0);
4124 /// Handle transforms common to the three shifts, when the shift amount is a
4126 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, ConstantSDNode *Amt) {
4127 SDNode *LHS = N->getOperand(0).getNode();
4128 if (!LHS->hasOneUse()) return SDValue();
4130 // We want to pull some binops through shifts, so that we have (and (shift))
4131 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
4132 // thing happens with address calculations, so it's important to canonicalize
4134 bool HighBitSet = false; // Can we transform this if the high bit is set?
4136 switch (LHS->getOpcode()) {
4137 default: return SDValue();
4140 HighBitSet = false; // We can only transform sra if the high bit is clear.
4143 HighBitSet = true; // We can only transform sra if the high bit is set.
4146 if (N->getOpcode() != ISD::SHL)
4147 return SDValue(); // only shl(add) not sr[al](add).
4148 HighBitSet = false; // We can only transform sra if the high bit is clear.
4152 // We require the RHS of the binop to be a constant and not opaque as well.
4153 ConstantSDNode *BinOpCst = getAsNonOpaqueConstant(LHS->getOperand(1));
4154 if (!BinOpCst) return SDValue();
4156 // FIXME: disable this unless the input to the binop is a shift by a constant.
4157 // If it is not a shift, it pessimizes some common cases like:
4159 // void foo(int *X, int i) { X[i & 1235] = 1; }
4160 // int bar(int *X, int i) { return X[i & 255]; }
4161 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
4162 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
4163 BinOpLHSVal->getOpcode() != ISD::SRA &&
4164 BinOpLHSVal->getOpcode() != ISD::SRL) ||
4165 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
4168 EVT VT = N->getValueType(0);
4170 // If this is a signed shift right, and the high bit is modified by the
4171 // logical operation, do not perform the transformation. The highBitSet
4172 // boolean indicates the value of the high bit of the constant which would
4173 // cause it to be modified for this operation.
4174 if (N->getOpcode() == ISD::SRA) {
4175 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
4176 if (BinOpRHSSignSet != HighBitSet)
4180 if (!TLI.isDesirableToCommuteWithShift(LHS))
4183 // Fold the constants, shifting the binop RHS by the shift amount.
4184 SDValue NewRHS = DAG.getNode(N->getOpcode(), SDLoc(LHS->getOperand(1)),
4186 LHS->getOperand(1), N->getOperand(1));
4187 assert(isa<ConstantSDNode>(NewRHS) && "Folding was not successful!");
4189 // Create the new shift.
4190 SDValue NewShift = DAG.getNode(N->getOpcode(),
4191 SDLoc(LHS->getOperand(0)),
4192 VT, LHS->getOperand(0), N->getOperand(1));
4194 // Create the new binop.
4195 return DAG.getNode(LHS->getOpcode(), SDLoc(N), VT, NewShift, NewRHS);
4198 SDValue DAGCombiner::distributeTruncateThroughAnd(SDNode *N) {
4199 assert(N->getOpcode() == ISD::TRUNCATE);
4200 assert(N->getOperand(0).getOpcode() == ISD::AND);
4202 // (truncate:TruncVT (and N00, N01C)) -> (and (truncate:TruncVT N00), TruncC)
4203 if (N->hasOneUse() && N->getOperand(0).hasOneUse()) {
4204 SDValue N01 = N->getOperand(0).getOperand(1);
4206 if (ConstantSDNode *N01C = isConstOrConstSplat(N01)) {
4207 if (!N01C->isOpaque()) {
4208 EVT TruncVT = N->getValueType(0);
4209 SDValue N00 = N->getOperand(0).getOperand(0);
4210 APInt TruncC = N01C->getAPIntValue();
4211 TruncC = TruncC.trunc(TruncVT.getScalarSizeInBits());
4214 return DAG.getNode(ISD::AND, DL, TruncVT,
4215 DAG.getNode(ISD::TRUNCATE, DL, TruncVT, N00),
4216 DAG.getConstant(TruncC, DL, TruncVT));
4224 SDValue DAGCombiner::visitRotate(SDNode *N) {
4225 // fold (rot* x, (trunc (and y, c))) -> (rot* x, (and (trunc y), (trunc c))).
4226 if (N->getOperand(1).getOpcode() == ISD::TRUNCATE &&
4227 N->getOperand(1).getOperand(0).getOpcode() == ISD::AND) {
4228 SDValue NewOp1 = distributeTruncateThroughAnd(N->getOperand(1).getNode());
4229 if (NewOp1.getNode())
4230 return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
4231 N->getOperand(0), NewOp1);
4236 SDValue DAGCombiner::visitSHL(SDNode *N) {
4237 SDValue N0 = N->getOperand(0);
4238 SDValue N1 = N->getOperand(1);
4239 EVT VT = N0.getValueType();
4240 unsigned OpSizeInBits = VT.getScalarSizeInBits();
4243 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4244 if (VT.isVector()) {
4245 if (SDValue FoldedVOp = SimplifyVBinOp(N))
4248 BuildVectorSDNode *N1CV = dyn_cast<BuildVectorSDNode>(N1);
4249 // If setcc produces all-one true value then:
4250 // (shl (and (setcc) N01CV) N1CV) -> (and (setcc) N01CV<<N1CV)
4251 if (N1CV && N1CV->isConstant()) {
4252 if (N0.getOpcode() == ISD::AND) {
4253 SDValue N00 = N0->getOperand(0);
4254 SDValue N01 = N0->getOperand(1);
4255 BuildVectorSDNode *N01CV = dyn_cast<BuildVectorSDNode>(N01);
4257 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC &&
4258 TLI.getBooleanContents(N00.getOperand(0).getValueType()) ==
4259 TargetLowering::ZeroOrNegativeOneBooleanContent) {
4260 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N), VT,
4262 return DAG.getNode(ISD::AND, SDLoc(N), VT, N00, C);
4265 N1C = isConstOrConstSplat(N1);
4270 // fold (shl c1, c2) -> c1<<c2
4271 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
4272 if (N0C && N1C && !N1C->isOpaque())
4273 return DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N), VT, N0C, N1C);
4274 // fold (shl 0, x) -> 0
4275 if (isNullConstant(N0))
4277 // fold (shl x, c >= size(x)) -> undef
4278 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
4279 return DAG.getUNDEF(VT);
4280 // fold (shl x, 0) -> x
4281 if (N1C && N1C->isNullValue())
4283 // fold (shl undef, x) -> 0
4284 if (N0.getOpcode() == ISD::UNDEF)
4285 return DAG.getConstant(0, SDLoc(N), VT);
4286 // if (shl x, c) is known to be zero, return 0
4287 if (DAG.MaskedValueIsZero(SDValue(N, 0),
4288 APInt::getAllOnesValue(OpSizeInBits)))
4289 return DAG.getConstant(0, SDLoc(N), VT);
4290 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
4291 if (N1.getOpcode() == ISD::TRUNCATE &&
4292 N1.getOperand(0).getOpcode() == ISD::AND) {
4293 SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode());
4294 if (NewOp1.getNode())
4295 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, NewOp1);
4298 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4299 return SDValue(N, 0);
4301 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
4302 if (N1C && N0.getOpcode() == ISD::SHL) {
4303 if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
4304 uint64_t c1 = N0C1->getZExtValue();
4305 uint64_t c2 = N1C->getZExtValue();
4307 if (c1 + c2 >= OpSizeInBits)
4308 return DAG.getConstant(0, DL, VT);
4309 return DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0),
4310 DAG.getConstant(c1 + c2, DL, N1.getValueType()));
4314 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
4315 // For this to be valid, the second form must not preserve any of the bits
4316 // that are shifted out by the inner shift in the first form. This means
4317 // the outer shift size must be >= the number of bits added by the ext.
4318 // As a corollary, we don't care what kind of ext it is.
4319 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
4320 N0.getOpcode() == ISD::ANY_EXTEND ||
4321 N0.getOpcode() == ISD::SIGN_EXTEND) &&
4322 N0.getOperand(0).getOpcode() == ISD::SHL) {
4323 SDValue N0Op0 = N0.getOperand(0);
4324 if (ConstantSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) {
4325 uint64_t c1 = N0Op0C1->getZExtValue();
4326 uint64_t c2 = N1C->getZExtValue();
4327 EVT InnerShiftVT = N0Op0.getValueType();
4328 uint64_t InnerShiftSize = InnerShiftVT.getScalarSizeInBits();
4329 if (c2 >= OpSizeInBits - InnerShiftSize) {
4331 if (c1 + c2 >= OpSizeInBits)
4332 return DAG.getConstant(0, DL, VT);
4333 return DAG.getNode(ISD::SHL, DL, VT,
4334 DAG.getNode(N0.getOpcode(), DL, VT,
4335 N0Op0->getOperand(0)),
4336 DAG.getConstant(c1 + c2, DL, N1.getValueType()));
4341 // fold (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C))
4342 // Only fold this if the inner zext has no other uses to avoid increasing
4343 // the total number of instructions.
4344 if (N1C && N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
4345 N0.getOperand(0).getOpcode() == ISD::SRL) {
4346 SDValue N0Op0 = N0.getOperand(0);
4347 if (ConstantSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) {
4348 uint64_t c1 = N0Op0C1->getZExtValue();
4349 if (c1 < VT.getScalarSizeInBits()) {
4350 uint64_t c2 = N1C->getZExtValue();
4352 SDValue NewOp0 = N0.getOperand(0);
4353 EVT CountVT = NewOp0.getOperand(1).getValueType();
4355 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, NewOp0.getValueType(),
4357 DAG.getConstant(c2, DL, CountVT));
4358 AddToWorklist(NewSHL.getNode());
4359 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL);
4365 // fold (shl (sr[la] exact X, C1), C2) -> (shl X, (C2-C1)) if C1 <= C2
4366 // fold (shl (sr[la] exact X, C1), C2) -> (sr[la] X, (C2-C1)) if C1 > C2
4367 if (N1C && (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) &&
4368 cast<BinaryWithFlagsSDNode>(N0)->Flags.hasExact()) {
4369 if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
4370 uint64_t C1 = N0C1->getZExtValue();
4371 uint64_t C2 = N1C->getZExtValue();
4374 return DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0),
4375 DAG.getConstant(C2 - C1, DL, N1.getValueType()));
4376 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0),
4377 DAG.getConstant(C1 - C2, DL, N1.getValueType()));
4381 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
4382 // (and (srl x, (sub c1, c2), MASK)
4383 // Only fold this if the inner shift has no other uses -- if it does, folding
4384 // this will increase the total number of instructions.
4385 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4386 if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
4387 uint64_t c1 = N0C1->getZExtValue();
4388 if (c1 < OpSizeInBits) {
4389 uint64_t c2 = N1C->getZExtValue();
4390 APInt Mask = APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - c1);
4393 Mask = Mask.shl(c2 - c1);
4395 Shift = DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0),
4396 DAG.getConstant(c2 - c1, DL, N1.getValueType()));
4398 Mask = Mask.lshr(c1 - c2);
4400 Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0),
4401 DAG.getConstant(c1 - c2, DL, N1.getValueType()));
4404 return DAG.getNode(ISD::AND, DL, VT, Shift,
4405 DAG.getConstant(Mask, DL, VT));
4409 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
4410 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
4411 unsigned BitSize = VT.getScalarSizeInBits();
4413 SDValue HiBitsMask =
4414 DAG.getConstant(APInt::getHighBitsSet(BitSize,
4415 BitSize - N1C->getZExtValue()),
4417 return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0),
4421 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2)
4422 // Variant of version done on multiply, except mul by a power of 2 is turned
4425 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
4426 (isa<ConstantSDNode>(N0.getOperand(1)) ||
4427 isConstantSplatVector(N0.getOperand(1).getNode(), Val))) {
4428 SDValue Shl0 = DAG.getNode(ISD::SHL, SDLoc(N0), VT, N0.getOperand(0), N1);
4429 SDValue Shl1 = DAG.getNode(ISD::SHL, SDLoc(N1), VT, N0.getOperand(1), N1);
4430 return DAG.getNode(ISD::ADD, SDLoc(N), VT, Shl0, Shl1);
4433 if (N1C && !N1C->isOpaque()) {
4434 SDValue NewSHL = visitShiftByConstant(N, N1C);
4435 if (NewSHL.getNode())
4442 SDValue DAGCombiner::visitSRA(SDNode *N) {
4443 SDValue N0 = N->getOperand(0);
4444 SDValue N1 = N->getOperand(1);
4445 EVT VT = N0.getValueType();
4446 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
4449 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4450 if (VT.isVector()) {
4451 if (SDValue FoldedVOp = SimplifyVBinOp(N))
4454 N1C = isConstOrConstSplat(N1);
4457 // fold (sra c1, c2) -> (sra c1, c2)
4458 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
4459 if (N0C && N1C && !N1C->isOpaque())
4460 return DAG.FoldConstantArithmetic(ISD::SRA, SDLoc(N), VT, N0C, N1C);
4461 // fold (sra 0, x) -> 0
4462 if (isNullConstant(N0))
4464 // fold (sra -1, x) -> -1
4465 if (isAllOnesConstant(N0))
4467 // fold (sra x, (setge c, size(x))) -> undef
4468 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
4469 return DAG.getUNDEF(VT);
4470 // fold (sra x, 0) -> x
4471 if (N1C && N1C->isNullValue())
4473 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
4475 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
4476 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
4477 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
4479 ExtVT = EVT::getVectorVT(*DAG.getContext(),
4480 ExtVT, VT.getVectorNumElements());
4481 if ((!LegalOperations ||
4482 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
4483 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
4484 N0.getOperand(0), DAG.getValueType(ExtVT));
4487 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
4488 if (N1C && N0.getOpcode() == ISD::SRA) {
4489 if (ConstantSDNode *C1 = isConstOrConstSplat(N0.getOperand(1))) {
4490 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
4491 if (Sum >= OpSizeInBits)
4492 Sum = OpSizeInBits - 1;
4494 return DAG.getNode(ISD::SRA, DL, VT, N0.getOperand(0),
4495 DAG.getConstant(Sum, DL, N1.getValueType()));
4499 // fold (sra (shl X, m), (sub result_size, n))
4500 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
4501 // result_size - n != m.
4502 // If truncate is free for the target sext(shl) is likely to result in better
4504 if (N0.getOpcode() == ISD::SHL && N1C) {
4505 // Get the two constanst of the shifts, CN0 = m, CN = n.
4506 const ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1));
4508 LLVMContext &Ctx = *DAG.getContext();
4509 // Determine what the truncate's result bitsize and type would be.
4510 EVT TruncVT = EVT::getIntegerVT(Ctx, OpSizeInBits - N1C->getZExtValue());
4513 TruncVT = EVT::getVectorVT(Ctx, TruncVT, VT.getVectorNumElements());
4515 // Determine the residual right-shift amount.
4516 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
4518 // If the shift is not a no-op (in which case this should be just a sign
4519 // extend already), the truncated to type is legal, sign_extend is legal
4520 // on that type, and the truncate to that type is both legal and free,
4521 // perform the transform.
4522 if ((ShiftAmt > 0) &&
4523 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
4524 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
4525 TLI.isTruncateFree(VT, TruncVT)) {
4528 SDValue Amt = DAG.getConstant(ShiftAmt, DL,
4529 getShiftAmountTy(N0.getOperand(0).getValueType()));
4530 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT,
4531 N0.getOperand(0), Amt);
4532 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, TruncVT,
4534 return DAG.getNode(ISD::SIGN_EXTEND, DL,
4535 N->getValueType(0), Trunc);
4540 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
4541 if (N1.getOpcode() == ISD::TRUNCATE &&
4542 N1.getOperand(0).getOpcode() == ISD::AND) {
4543 SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode());
4544 if (NewOp1.getNode())
4545 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0, NewOp1);
4548 // fold (sra (trunc (srl x, c1)), c2) -> (trunc (sra x, c1 + c2))
4549 // if c1 is equal to the number of bits the trunc removes
4550 if (N0.getOpcode() == ISD::TRUNCATE &&
4551 (N0.getOperand(0).getOpcode() == ISD::SRL ||
4552 N0.getOperand(0).getOpcode() == ISD::SRA) &&
4553 N0.getOperand(0).hasOneUse() &&
4554 N0.getOperand(0).getOperand(1).hasOneUse() &&
4556 SDValue N0Op0 = N0.getOperand(0);
4557 if (ConstantSDNode *LargeShift = isConstOrConstSplat(N0Op0.getOperand(1))) {
4558 unsigned LargeShiftVal = LargeShift->getZExtValue();
4559 EVT LargeVT = N0Op0.getValueType();
4561 if (LargeVT.getScalarSizeInBits() - OpSizeInBits == LargeShiftVal) {
4564 DAG.getConstant(LargeShiftVal + N1C->getZExtValue(), DL,
4565 getShiftAmountTy(N0Op0.getOperand(0).getValueType()));
4566 SDValue SRA = DAG.getNode(ISD::SRA, DL, LargeVT,
4567 N0Op0.getOperand(0), Amt);
4568 return DAG.getNode(ISD::TRUNCATE, DL, VT, SRA);
4573 // Simplify, based on bits shifted out of the LHS.
4574 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4575 return SDValue(N, 0);
4578 // If the sign bit is known to be zero, switch this to a SRL.
4579 if (DAG.SignBitIsZero(N0))
4580 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1);
4582 if (N1C && !N1C->isOpaque()) {
4583 SDValue NewSRA = visitShiftByConstant(N, N1C);
4584 if (NewSRA.getNode())
4591 SDValue DAGCombiner::visitSRL(SDNode *N) {
4592 SDValue N0 = N->getOperand(0);
4593 SDValue N1 = N->getOperand(1);
4594 EVT VT = N0.getValueType();
4595 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
4598 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4599 if (VT.isVector()) {
4600 if (SDValue FoldedVOp = SimplifyVBinOp(N))
4603 N1C = isConstOrConstSplat(N1);
4606 // fold (srl c1, c2) -> c1 >>u c2
4607 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
4608 if (N0C && N1C && !N1C->isOpaque())
4609 return DAG.FoldConstantArithmetic(ISD::SRL, SDLoc(N), VT, N0C, N1C);
4610 // fold (srl 0, x) -> 0
4611 if (isNullConstant(N0))
4613 // fold (srl x, c >= size(x)) -> undef
4614 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
4615 return DAG.getUNDEF(VT);
4616 // fold (srl x, 0) -> x
4617 if (N1C && N1C->isNullValue())
4619 // if (srl x, c) is known to be zero, return 0
4620 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
4621 APInt::getAllOnesValue(OpSizeInBits)))
4622 return DAG.getConstant(0, SDLoc(N), VT);
4624 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
4625 if (N1C && N0.getOpcode() == ISD::SRL) {
4626 if (ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1))) {
4627 uint64_t c1 = N01C->getZExtValue();
4628 uint64_t c2 = N1C->getZExtValue();
4630 if (c1 + c2 >= OpSizeInBits)
4631 return DAG.getConstant(0, DL, VT);
4632 return DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0),
4633 DAG.getConstant(c1 + c2, DL, N1.getValueType()));
4637 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
4638 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
4639 N0.getOperand(0).getOpcode() == ISD::SRL &&
4640 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
4642 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
4643 uint64_t c2 = N1C->getZExtValue();
4644 EVT InnerShiftVT = N0.getOperand(0).getValueType();
4645 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
4646 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
4647 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
4648 if (c1 + OpSizeInBits == InnerShiftSize) {
4650 if (c1 + c2 >= InnerShiftSize)
4651 return DAG.getConstant(0, DL, VT);
4652 return DAG.getNode(ISD::TRUNCATE, DL, VT,
4653 DAG.getNode(ISD::SRL, DL, InnerShiftVT,
4654 N0.getOperand(0)->getOperand(0),
4655 DAG.getConstant(c1 + c2, DL,
4660 // fold (srl (shl x, c), c) -> (and x, cst2)
4661 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1) {
4662 unsigned BitSize = N0.getScalarValueSizeInBits();
4663 if (BitSize <= 64) {
4664 uint64_t ShAmt = N1C->getZExtValue() + 64 - BitSize;
4666 return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0),
4667 DAG.getConstant(~0ULL >> ShAmt, DL, VT));
4671 // fold (srl (anyextend x), c) -> (and (anyextend (srl x, c)), mask)
4672 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
4673 // Shifting in all undef bits?
4674 EVT SmallVT = N0.getOperand(0).getValueType();
4675 unsigned BitSize = SmallVT.getScalarSizeInBits();
4676 if (N1C->getZExtValue() >= BitSize)
4677 return DAG.getUNDEF(VT);
4679 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
4680 uint64_t ShiftAmt = N1C->getZExtValue();
4682 SDValue SmallShift = DAG.getNode(ISD::SRL, DL0, SmallVT,
4684 DAG.getConstant(ShiftAmt, DL0,
4685 getShiftAmountTy(SmallVT)));
4686 AddToWorklist(SmallShift.getNode());
4687 APInt Mask = APInt::getAllOnesValue(OpSizeInBits).lshr(ShiftAmt);
4689 return DAG.getNode(ISD::AND, DL, VT,
4690 DAG.getNode(ISD::ANY_EXTEND, DL, VT, SmallShift),
4691 DAG.getConstant(Mask, DL, VT));
4695 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
4696 // bit, which is unmodified by sra.
4697 if (N1C && N1C->getZExtValue() + 1 == OpSizeInBits) {
4698 if (N0.getOpcode() == ISD::SRA)
4699 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1);
4702 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
4703 if (N1C && N0.getOpcode() == ISD::CTLZ &&
4704 N1C->getAPIntValue() == Log2_32(OpSizeInBits)) {
4705 APInt KnownZero, KnownOne;
4706 DAG.computeKnownBits(N0.getOperand(0), KnownZero, KnownOne);
4708 // If any of the input bits are KnownOne, then the input couldn't be all
4709 // zeros, thus the result of the srl will always be zero.
4710 if (KnownOne.getBoolValue()) return DAG.getConstant(0, SDLoc(N0), VT);
4712 // If all of the bits input the to ctlz node are known to be zero, then
4713 // the result of the ctlz is "32" and the result of the shift is one.
4714 APInt UnknownBits = ~KnownZero;
4715 if (UnknownBits == 0) return DAG.getConstant(1, SDLoc(N0), VT);
4717 // Otherwise, check to see if there is exactly one bit input to the ctlz.
4718 if ((UnknownBits & (UnknownBits - 1)) == 0) {
4719 // Okay, we know that only that the single bit specified by UnknownBits
4720 // could be set on input to the CTLZ node. If this bit is set, the SRL
4721 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
4722 // to an SRL/XOR pair, which is likely to simplify more.
4723 unsigned ShAmt = UnknownBits.countTrailingZeros();
4724 SDValue Op = N0.getOperand(0);
4728 Op = DAG.getNode(ISD::SRL, DL, VT, Op,
4729 DAG.getConstant(ShAmt, DL,
4730 getShiftAmountTy(Op.getValueType())));
4731 AddToWorklist(Op.getNode());
4735 return DAG.getNode(ISD::XOR, DL, VT,
4736 Op, DAG.getConstant(1, DL, VT));
4740 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
4741 if (N1.getOpcode() == ISD::TRUNCATE &&
4742 N1.getOperand(0).getOpcode() == ISD::AND) {
4743 SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode());
4744 if (NewOp1.getNode())
4745 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, NewOp1);
4748 // fold operands of srl based on knowledge that the low bits are not
4750 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4751 return SDValue(N, 0);
4753 if (N1C && !N1C->isOpaque()) {
4754 SDValue NewSRL = visitShiftByConstant(N, N1C);
4755 if (NewSRL.getNode())
4759 // Attempt to convert a srl of a load into a narrower zero-extending load.
4760 SDValue NarrowLoad = ReduceLoadWidth(N);
4761 if (NarrowLoad.getNode())
4764 // Here is a common situation. We want to optimize:
4767 // %b = and i32 %a, 2
4768 // %c = srl i32 %b, 1
4769 // brcond i32 %c ...
4775 // %c = setcc eq %b, 0
4778 // However when after the source operand of SRL is optimized into AND, the SRL
4779 // itself may not be optimized further. Look for it and add the BRCOND into
4781 if (N->hasOneUse()) {
4782 SDNode *Use = *N->use_begin();
4783 if (Use->getOpcode() == ISD::BRCOND)
4785 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
4786 // Also look pass the truncate.
4787 Use = *Use->use_begin();
4788 if (Use->getOpcode() == ISD::BRCOND)
4796 SDValue DAGCombiner::visitBSWAP(SDNode *N) {
4797 SDValue N0 = N->getOperand(0);
4798 EVT VT = N->getValueType(0);
4800 // fold (bswap c1) -> c2
4801 if (isConstantIntBuildVectorOrConstantInt(N0))
4802 return DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N0);
4803 // fold (bswap (bswap x)) -> x
4804 if (N0.getOpcode() == ISD::BSWAP)
4805 return N0->getOperand(0);
4809 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
4810 SDValue N0 = N->getOperand(0);
4811 EVT VT = N->getValueType(0);
4813 // fold (ctlz c1) -> c2
4814 if (isConstantIntBuildVectorOrConstantInt(N0))
4815 return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0);
4819 SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) {
4820 SDValue N0 = N->getOperand(0);
4821 EVT VT = N->getValueType(0);
4823 // fold (ctlz_zero_undef c1) -> c2
4824 if (isConstantIntBuildVectorOrConstantInt(N0))
4825 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4829 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
4830 SDValue N0 = N->getOperand(0);
4831 EVT VT = N->getValueType(0);
4833 // fold (cttz c1) -> c2
4834 if (isConstantIntBuildVectorOrConstantInt(N0))
4835 return DAG.getNode(ISD::CTTZ, SDLoc(N), VT, N0);
4839 SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) {
4840 SDValue N0 = N->getOperand(0);
4841 EVT VT = N->getValueType(0);
4843 // fold (cttz_zero_undef c1) -> c2
4844 if (isConstantIntBuildVectorOrConstantInt(N0))
4845 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4849 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
4850 SDValue N0 = N->getOperand(0);
4851 EVT VT = N->getValueType(0);
4853 // fold (ctpop c1) -> c2
4854 if (isConstantIntBuildVectorOrConstantInt(N0))
4855 return DAG.getNode(ISD::CTPOP, SDLoc(N), VT, N0);
4860 /// \brief Generate Min/Max node
4861 static SDValue combineMinNumMaxNum(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS,
4862 SDValue True, SDValue False,
4863 ISD::CondCode CC, const TargetLowering &TLI,
4864 SelectionDAG &DAG) {
4865 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
4875 unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM;
4876 if (TLI.isOperationLegal(Opcode, VT))
4877 return DAG.getNode(Opcode, DL, VT, LHS, RHS);
4886 unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM;
4887 if (TLI.isOperationLegal(Opcode, VT))
4888 return DAG.getNode(Opcode, DL, VT, LHS, RHS);
4896 SDValue DAGCombiner::visitSELECT(SDNode *N) {
4897 SDValue N0 = N->getOperand(0);
4898 SDValue N1 = N->getOperand(1);
4899 SDValue N2 = N->getOperand(2);
4900 EVT VT = N->getValueType(0);
4901 EVT VT0 = N0.getValueType();
4903 // fold (select C, X, X) -> X
4906 if (const ConstantSDNode *N0C = dyn_cast<const ConstantSDNode>(N0)) {
4907 // fold (select true, X, Y) -> X
4908 // fold (select false, X, Y) -> Y
4909 return !N0C->isNullValue() ? N1 : N2;
4911 // fold (select C, 1, X) -> (or C, X)
4912 if (VT == MVT::i1 && isOneConstant(N1))
4913 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
4914 // fold (select C, 0, 1) -> (xor C, 1)
4915 // We can't do this reliably if integer based booleans have different contents
4916 // to floating point based booleans. This is because we can't tell whether we
4917 // have an integer-based boolean or a floating-point-based boolean unless we
4918 // can find the SETCC that produced it and inspect its operands. This is
4919 // fairly easy if C is the SETCC node, but it can potentially be
4920 // undiscoverable (or not reasonably discoverable). For example, it could be
4921 // in another basic block or it could require searching a complicated
4923 if (VT.isInteger() &&
4924 (VT0 == MVT::i1 || (VT0.isInteger() &&
4925 TLI.getBooleanContents(false, false) ==
4926 TLI.getBooleanContents(false, true) &&
4927 TLI.getBooleanContents(false, false) ==
4928 TargetLowering::ZeroOrOneBooleanContent)) &&
4929 isNullConstant(N1) && isOneConstant(N2)) {
4933 return DAG.getNode(ISD::XOR, DL, VT0,
4934 N0, DAG.getConstant(1, DL, VT0));
4937 XORNode = DAG.getNode(ISD::XOR, DL0, VT0,
4938 N0, DAG.getConstant(1, DL0, VT0));
4939 AddToWorklist(XORNode.getNode());
4941 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, XORNode);
4942 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, XORNode);
4944 // fold (select C, 0, X) -> (and (not C), X)
4945 if (VT == VT0 && VT == MVT::i1 && isNullConstant(N1)) {
4946 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
4947 AddToWorklist(NOTNode.getNode());
4948 return DAG.getNode(ISD::AND, SDLoc(N), VT, NOTNode, N2);
4950 // fold (select C, X, 1) -> (or (not C), X)
4951 if (VT == VT0 && VT == MVT::i1 && isOneConstant(N2)) {
4952 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
4953 AddToWorklist(NOTNode.getNode());
4954 return DAG.getNode(ISD::OR, SDLoc(N), VT, NOTNode, N1);
4956 // fold (select C, X, 0) -> (and C, X)
4957 if (VT == MVT::i1 && isNullConstant(N2))
4958 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
4959 // fold (select X, X, Y) -> (or X, Y)
4960 // fold (select X, 1, Y) -> (or X, Y)
4961 if (VT == MVT::i1 && (N0 == N1 || isOneConstant(N1)))
4962 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
4963 // fold (select X, Y, X) -> (and X, Y)
4964 // fold (select X, Y, 0) -> (and X, Y)
4965 if (VT == MVT::i1 && (N0 == N2 || isNullConstant(N2)))
4966 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
4968 // If we can fold this based on the true/false value, do so.
4969 if (SimplifySelectOps(N, N1, N2))
4970 return SDValue(N, 0); // Don't revisit N.
4972 // fold selects based on a setcc into other things, such as min/max/abs
4973 if (N0.getOpcode() == ISD::SETCC) {
4974 // select x, y (fcmp lt x, y) -> fminnum x, y
4975 // select x, y (fcmp gt x, y) -> fmaxnum x, y
4977 // This is OK if we don't care about what happens if either operand is a
4981 // FIXME: Instead of testing for UnsafeFPMath, this should be checking for
4982 // no signed zeros as well as no nans.
4983 const TargetOptions &Options = DAG.getTarget().Options;
4984 if (Options.UnsafeFPMath &&
4985 VT.isFloatingPoint() && N0.hasOneUse() &&
4986 DAG.isKnownNeverNaN(N1) && DAG.isKnownNeverNaN(N2)) {
4987 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
4990 combineMinNumMaxNum(SDLoc(N), VT, N0.getOperand(0), N0.getOperand(1),
4991 N1, N2, CC, TLI, DAG);
4996 if ((!LegalOperations &&
4997 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) ||
4998 TLI.isOperationLegal(ISD::SELECT_CC, VT))
4999 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT,
5000 N0.getOperand(0), N0.getOperand(1),
5001 N1, N2, N0.getOperand(2));
5002 return SimplifySelect(SDLoc(N), N0, N1, N2);
5005 if (VT0 == MVT::i1) {
5006 if (TLI.shouldNormalizeToSelectSequence(*DAG.getContext(), VT)) {
5007 // select (and Cond0, Cond1), X, Y
5008 // -> select Cond0, (select Cond1, X, Y), Y
5009 if (N0->getOpcode() == ISD::AND && N0->hasOneUse()) {
5010 SDValue Cond0 = N0->getOperand(0);
5011 SDValue Cond1 = N0->getOperand(1);
5012 SDValue InnerSelect = DAG.getNode(ISD::SELECT, SDLoc(N),
5013 N1.getValueType(), Cond1, N1, N2);
5014 return DAG.getNode(ISD::SELECT, SDLoc(N), N1.getValueType(), Cond0,
5017 // select (or Cond0, Cond1), X, Y -> select Cond0, X, (select Cond1, X, Y)
5018 if (N0->getOpcode() == ISD::OR && N0->hasOneUse()) {
5019 SDValue Cond0 = N0->getOperand(0);
5020 SDValue Cond1 = N0->getOperand(1);
5021 SDValue InnerSelect = DAG.getNode(ISD::SELECT, SDLoc(N),
5022 N1.getValueType(), Cond1, N1, N2);
5023 return DAG.getNode(ISD::SELECT, SDLoc(N), N1.getValueType(), Cond0, N1,
5028 // select Cond0, (select Cond1, X, Y), Y -> select (and Cond0, Cond1), X, Y
5029 if (N1->getOpcode() == ISD::SELECT) {
5030 SDValue N1_0 = N1->getOperand(0);
5031 SDValue N1_1 = N1->getOperand(1);
5032 SDValue N1_2 = N1->getOperand(2);
5033 if (N1_2 == N2 && N0.getValueType() == N1_0.getValueType()) {
5034 // Create the actual and node if we can generate good code for it.
5035 if (!TLI.shouldNormalizeToSelectSequence(*DAG.getContext(), VT)) {
5036 SDValue And = DAG.getNode(ISD::AND, SDLoc(N), N0.getValueType(),
5038 return DAG.getNode(ISD::SELECT, SDLoc(N), N1.getValueType(), And,
5041 // Otherwise see if we can optimize the "and" to a better pattern.
5042 if (SDValue Combined = visitANDLike(N0, N1_0, N))
5043 return DAG.getNode(ISD::SELECT, SDLoc(N), N1.getValueType(), Combined,
5047 // select Cond0, X, (select Cond1, X, Y) -> select (or Cond0, Cond1), X, Y
5048 if (N2->getOpcode() == ISD::SELECT) {
5049 SDValue N2_0 = N2->getOperand(0);
5050 SDValue N2_1 = N2->getOperand(1);
5051 SDValue N2_2 = N2->getOperand(2);
5052 if (N2_1 == N1 && N0.getValueType() == N2_0.getValueType()) {
5053 // Create the actual or node if we can generate good code for it.
5054 if (!TLI.shouldNormalizeToSelectSequence(*DAG.getContext(), VT)) {
5055 SDValue Or = DAG.getNode(ISD::OR, SDLoc(N), N0.getValueType(),
5057 return DAG.getNode(ISD::SELECT, SDLoc(N), N1.getValueType(), Or,
5060 // Otherwise see if we can optimize to a better pattern.
5061 if (SDValue Combined = visitORLike(N0, N2_0, N))
5062 return DAG.getNode(ISD::SELECT, SDLoc(N), N1.getValueType(), Combined,
5072 std::pair<SDValue, SDValue> SplitVSETCC(const SDNode *N, SelectionDAG &DAG) {
5075 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
5077 // Split the inputs.
5078 SDValue Lo, Hi, LL, LH, RL, RH;
5079 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
5080 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
5082 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
5083 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
5085 return std::make_pair(Lo, Hi);
5088 // This function assumes all the vselect's arguments are CONCAT_VECTOR
5089 // nodes and that the condition is a BV of ConstantSDNodes (or undefs).
5090 static SDValue ConvertSelectToConcatVector(SDNode *N, SelectionDAG &DAG) {
5092 SDValue Cond = N->getOperand(0);
5093 SDValue LHS = N->getOperand(1);
5094 SDValue RHS = N->getOperand(2);
5095 EVT VT = N->getValueType(0);
5096 int NumElems = VT.getVectorNumElements();
5097 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS &&
5098 RHS.getOpcode() == ISD::CONCAT_VECTORS &&
5099 Cond.getOpcode() == ISD::BUILD_VECTOR);
5101 // CONCAT_VECTOR can take an arbitrary number of arguments. We only care about
5102 // binary ones here.
5103 if (LHS->getNumOperands() != 2 || RHS->getNumOperands() != 2)
5106 // We're sure we have an even number of elements due to the
5107 // concat_vectors we have as arguments to vselect.
5108 // Skip BV elements until we find one that's not an UNDEF
5109 // After we find an UNDEF element, keep looping until we get to half the
5110 // length of the BV and see if all the non-undef nodes are the same.
5111 ConstantSDNode *BottomHalf = nullptr;
5112 for (int i = 0; i < NumElems / 2; ++i) {
5113 if (Cond->getOperand(i)->getOpcode() == ISD::UNDEF)
5116 if (BottomHalf == nullptr)
5117 BottomHalf = cast<ConstantSDNode>(Cond.getOperand(i));
5118 else if (Cond->getOperand(i).getNode() != BottomHalf)
5122 // Do the same for the second half of the BuildVector
5123 ConstantSDNode *TopHalf = nullptr;
5124 for (int i = NumElems / 2; i < NumElems; ++i) {
5125 if (Cond->getOperand(i)->getOpcode() == ISD::UNDEF)
5128 if (TopHalf == nullptr)
5129 TopHalf = cast<ConstantSDNode>(Cond.getOperand(i));
5130 else if (Cond->getOperand(i).getNode() != TopHalf)
5134 assert(TopHalf && BottomHalf &&
5135 "One half of the selector was all UNDEFs and the other was all the "
5136 "same value. This should have been addressed before this function.");
5138 ISD::CONCAT_VECTORS, dl, VT,
5139 BottomHalf->isNullValue() ? RHS->getOperand(0) : LHS->getOperand(0),
5140 TopHalf->isNullValue() ? RHS->getOperand(1) : LHS->getOperand(1));
5143 SDValue DAGCombiner::visitMSCATTER(SDNode *N) {
5145 if (Level >= AfterLegalizeTypes)
5148 MaskedScatterSDNode *MSC = cast<MaskedScatterSDNode>(N);
5149 SDValue Mask = MSC->getMask();
5150 SDValue Data = MSC->getValue();
5153 // If the MSCATTER data type requires splitting and the mask is provided by a
5154 // SETCC, then split both nodes and its operands before legalization. This
5155 // prevents the type legalizer from unrolling SETCC into scalar comparisons
5156 // and enables future optimizations (e.g. min/max pattern matching on X86).
5157 if (Mask.getOpcode() != ISD::SETCC)
5160 // Check if any splitting is required.
5161 if (TLI.getTypeAction(*DAG.getContext(), Data.getValueType()) !=
5162 TargetLowering::TypeSplitVector)
5164 SDValue MaskLo, MaskHi, Lo, Hi;
5165 std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
5168 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MSC->getValueType(0));
5170 SDValue Chain = MSC->getChain();
5172 EVT MemoryVT = MSC->getMemoryVT();
5173 unsigned Alignment = MSC->getOriginalAlignment();
5175 EVT LoMemVT, HiMemVT;
5176 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
5178 SDValue DataLo, DataHi;
5179 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
5181 SDValue BasePtr = MSC->getBasePtr();
5182 SDValue IndexLo, IndexHi;
5183 std::tie(IndexLo, IndexHi) = DAG.SplitVector(MSC->getIndex(), DL);
5185 MachineMemOperand *MMO = DAG.getMachineFunction().
5186 getMachineMemOperand(MSC->getPointerInfo(),
5187 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
5188 Alignment, MSC->getAAInfo(), MSC->getRanges());
5190 SDValue OpsLo[] = { Chain, DataLo, MaskLo, BasePtr, IndexLo };
5191 Lo = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataLo.getValueType(),
5194 SDValue OpsHi[] = {Chain, DataHi, MaskHi, BasePtr, IndexHi};
5195 Hi = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataHi.getValueType(),
5198 AddToWorklist(Lo.getNode());
5199 AddToWorklist(Hi.getNode());
5201 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
5204 SDValue DAGCombiner::visitMSTORE(SDNode *N) {
5206 if (Level >= AfterLegalizeTypes)
5209 MaskedStoreSDNode *MST = dyn_cast<MaskedStoreSDNode>(N);
5210 SDValue Mask = MST->getMask();
5211 SDValue Data = MST->getValue();
5214 // If the MSTORE data type requires splitting and the mask is provided by a
5215 // SETCC, then split both nodes and its operands before legalization. This
5216 // prevents the type legalizer from unrolling SETCC into scalar comparisons
5217 // and enables future optimizations (e.g. min/max pattern matching on X86).
5218 if (Mask.getOpcode() == ISD::SETCC) {
5220 // Check if any splitting is required.
5221 if (TLI.getTypeAction(*DAG.getContext(), Data.getValueType()) !=
5222 TargetLowering::TypeSplitVector)
5225 SDValue MaskLo, MaskHi, Lo, Hi;
5226 std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
5229 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MST->getValueType(0));
5231 SDValue Chain = MST->getChain();
5232 SDValue Ptr = MST->getBasePtr();
5234 EVT MemoryVT = MST->getMemoryVT();
5235 unsigned Alignment = MST->getOriginalAlignment();
5237 // if Alignment is equal to the vector size,
5238 // take the half of it for the second part
5239 unsigned SecondHalfAlignment =
5240 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
5241 Alignment/2 : Alignment;
5243 EVT LoMemVT, HiMemVT;
5244 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
5246 SDValue DataLo, DataHi;
5247 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
5249 MachineMemOperand *MMO = DAG.getMachineFunction().
5250 getMachineMemOperand(MST->getPointerInfo(),
5251 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
5252 Alignment, MST->getAAInfo(), MST->getRanges());
5254 Lo = DAG.getMaskedStore(Chain, DL, DataLo, Ptr, MaskLo, LoMemVT, MMO,
5255 MST->isTruncatingStore());
5257 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
5258 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5259 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
5261 MMO = DAG.getMachineFunction().
5262 getMachineMemOperand(MST->getPointerInfo(),
5263 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
5264 SecondHalfAlignment, MST->getAAInfo(),
5267 Hi = DAG.getMaskedStore(Chain, DL, DataHi, Ptr, MaskHi, HiMemVT, MMO,
5268 MST->isTruncatingStore());
5270 AddToWorklist(Lo.getNode());
5271 AddToWorklist(Hi.getNode());
5273 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
5278 SDValue DAGCombiner::visitMGATHER(SDNode *N) {
5280 if (Level >= AfterLegalizeTypes)
5283 MaskedGatherSDNode *MGT = dyn_cast<MaskedGatherSDNode>(N);
5284 SDValue Mask = MGT->getMask();
5287 // If the MGATHER result requires splitting and the mask is provided by a
5288 // SETCC, then split both nodes and its operands before legalization. This
5289 // prevents the type legalizer from unrolling SETCC into scalar comparisons
5290 // and enables future optimizations (e.g. min/max pattern matching on X86).
5292 if (Mask.getOpcode() != ISD::SETCC)
5295 EVT VT = N->getValueType(0);
5297 // Check if any splitting is required.
5298 if (TLI.getTypeAction(*DAG.getContext(), VT) !=
5299 TargetLowering::TypeSplitVector)
5302 SDValue MaskLo, MaskHi, Lo, Hi;
5303 std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
5305 SDValue Src0 = MGT->getValue();
5306 SDValue Src0Lo, Src0Hi;
5307 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, DL);
5310 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
5312 SDValue Chain = MGT->getChain();
5313 EVT MemoryVT = MGT->getMemoryVT();
5314 unsigned Alignment = MGT->getOriginalAlignment();
5316 EVT LoMemVT, HiMemVT;
5317 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
5319 SDValue BasePtr = MGT->getBasePtr();
5320 SDValue Index = MGT->getIndex();
5321 SDValue IndexLo, IndexHi;
5322 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, DL);
5324 MachineMemOperand *MMO = DAG.getMachineFunction().
5325 getMachineMemOperand(MGT->getPointerInfo(),
5326 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
5327 Alignment, MGT->getAAInfo(), MGT->getRanges());
5329 SDValue OpsLo[] = { Chain, Src0Lo, MaskLo, BasePtr, IndexLo };
5330 Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, DL, OpsLo,
5333 SDValue OpsHi[] = {Chain, Src0Hi, MaskHi, BasePtr, IndexHi};
5334 Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, DL, OpsHi,
5337 AddToWorklist(Lo.getNode());
5338 AddToWorklist(Hi.getNode());
5340 // Build a factor node to remember that this load is independent of the
5342 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo.getValue(1),
5345 // Legalized the chain result - switch anything that used the old chain to
5347 DAG.ReplaceAllUsesOfValueWith(SDValue(MGT, 1), Chain);
5349 SDValue GatherRes = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
5351 SDValue RetOps[] = { GatherRes, Chain };
5352 return DAG.getMergeValues(RetOps, DL);
5355 SDValue DAGCombiner::visitMLOAD(SDNode *N) {
5357 if (Level >= AfterLegalizeTypes)
5360 MaskedLoadSDNode *MLD = dyn_cast<MaskedLoadSDNode>(N);
5361 SDValue Mask = MLD->getMask();
5364 // If the MLOAD result requires splitting and the mask is provided by a
5365 // SETCC, then split both nodes and its operands before legalization. This
5366 // prevents the type legalizer from unrolling SETCC into scalar comparisons
5367 // and enables future optimizations (e.g. min/max pattern matching on X86).
5369 if (Mask.getOpcode() == ISD::SETCC) {
5370 EVT VT = N->getValueType(0);
5372 // Check if any splitting is required.
5373 if (TLI.getTypeAction(*DAG.getContext(), VT) !=
5374 TargetLowering::TypeSplitVector)
5377 SDValue MaskLo, MaskHi, Lo, Hi;
5378 std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
5380 SDValue Src0 = MLD->getSrc0();
5381 SDValue Src0Lo, Src0Hi;
5382 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, DL);
5385 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
5387 SDValue Chain = MLD->getChain();
5388 SDValue Ptr = MLD->getBasePtr();
5389 EVT MemoryVT = MLD->getMemoryVT();
5390 unsigned Alignment = MLD->getOriginalAlignment();
5392 // if Alignment is equal to the vector size,
5393 // take the half of it for the second part
5394 unsigned SecondHalfAlignment =
5395 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
5396 Alignment/2 : Alignment;
5398 EVT LoMemVT, HiMemVT;
5399 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
5401 MachineMemOperand *MMO = DAG.getMachineFunction().
5402 getMachineMemOperand(MLD->getPointerInfo(),
5403 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
5404 Alignment, MLD->getAAInfo(), MLD->getRanges());
5406 Lo = DAG.getMaskedLoad(LoVT, DL, Chain, Ptr, MaskLo, Src0Lo, LoMemVT, MMO,
5409 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
5410 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5411 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
5413 MMO = DAG.getMachineFunction().
5414 getMachineMemOperand(MLD->getPointerInfo(),
5415 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
5416 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
5418 Hi = DAG.getMaskedLoad(HiVT, DL, Chain, Ptr, MaskHi, Src0Hi, HiMemVT, MMO,
5421 AddToWorklist(Lo.getNode());
5422 AddToWorklist(Hi.getNode());
5424 // Build a factor node to remember that this load is independent of the
5426 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo.getValue(1),
5429 // Legalized the chain result - switch anything that used the old chain to
5431 DAG.ReplaceAllUsesOfValueWith(SDValue(MLD, 1), Chain);
5433 SDValue LoadRes = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
5435 SDValue RetOps[] = { LoadRes, Chain };
5436 return DAG.getMergeValues(RetOps, DL);
5441 SDValue DAGCombiner::visitVSELECT(SDNode *N) {
5442 SDValue N0 = N->getOperand(0);
5443 SDValue N1 = N->getOperand(1);
5444 SDValue N2 = N->getOperand(2);
5447 // Canonicalize integer abs.
5448 // vselect (setg[te] X, 0), X, -X ->
5449 // vselect (setgt X, -1), X, -X ->
5450 // vselect (setl[te] X, 0), -X, X ->
5451 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5452 if (N0.getOpcode() == ISD::SETCC) {
5453 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
5454 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
5456 bool RHSIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
5458 if (((RHSIsAllZeros && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
5459 (ISD::isBuildVectorAllOnes(RHS.getNode()) && CC == ISD::SETGT)) &&
5460 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1))
5461 isAbs = ISD::isBuildVectorAllZeros(N2.getOperand(0).getNode());
5462 else if ((RHSIsAllZeros && (CC == ISD::SETLT || CC == ISD::SETLE)) &&
5463 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1))
5464 isAbs = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode());
5467 EVT VT = LHS.getValueType();
5468 SDValue Shift = DAG.getNode(
5469 ISD::SRA, DL, VT, LHS,
5470 DAG.getConstant(VT.getScalarType().getSizeInBits() - 1, DL, VT));
5471 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, LHS, Shift);
5472 AddToWorklist(Shift.getNode());
5473 AddToWorklist(Add.getNode());
5474 return DAG.getNode(ISD::XOR, DL, VT, Add, Shift);
5478 if (SimplifySelectOps(N, N1, N2))
5479 return SDValue(N, 0); // Don't revisit N.
5481 // If the VSELECT result requires splitting and the mask is provided by a
5482 // SETCC, then split both nodes and its operands before legalization. This
5483 // prevents the type legalizer from unrolling SETCC into scalar comparisons
5484 // and enables future optimizations (e.g. min/max pattern matching on X86).
5485 if (N0.getOpcode() == ISD::SETCC) {
5486 EVT VT = N->getValueType(0);
5488 // Check if any splitting is required.
5489 if (TLI.getTypeAction(*DAG.getContext(), VT) !=
5490 TargetLowering::TypeSplitVector)
5493 SDValue Lo, Hi, CCLo, CCHi, LL, LH, RL, RH;
5494 std::tie(CCLo, CCHi) = SplitVSETCC(N0.getNode(), DAG);
5495 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 1);
5496 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 2);
5498 Lo = DAG.getNode(N->getOpcode(), DL, LL.getValueType(), CCLo, LL, RL);
5499 Hi = DAG.getNode(N->getOpcode(), DL, LH.getValueType(), CCHi, LH, RH);
5501 // Add the new VSELECT nodes to the work list in case they need to be split
5503 AddToWorklist(Lo.getNode());
5504 AddToWorklist(Hi.getNode());
5506 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
5509 // Fold (vselect (build_vector all_ones), N1, N2) -> N1
5510 if (ISD::isBuildVectorAllOnes(N0.getNode()))
5512 // Fold (vselect (build_vector all_zeros), N1, N2) -> N2
5513 if (ISD::isBuildVectorAllZeros(N0.getNode()))
5516 // The ConvertSelectToConcatVector function is assuming both the above
5517 // checks for (vselect (build_vector all{ones,zeros) ...) have been made
5519 if (N1.getOpcode() == ISD::CONCAT_VECTORS &&
5520 N2.getOpcode() == ISD::CONCAT_VECTORS &&
5521 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
5522 SDValue CV = ConvertSelectToConcatVector(N, DAG);
5530 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
5531 SDValue N0 = N->getOperand(0);
5532 SDValue N1 = N->getOperand(1);
5533 SDValue N2 = N->getOperand(2);
5534 SDValue N3 = N->getOperand(3);
5535 SDValue N4 = N->getOperand(4);
5536 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
5538 // fold select_cc lhs, rhs, x, x, cc -> x
5542 // Determine if the condition we're dealing with is constant
5543 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
5544 N0, N1, CC, SDLoc(N), false);
5545 if (SCC.getNode()) {
5546 AddToWorklist(SCC.getNode());
5548 if (ConstantSDNode *SCCC = dyn_cast<ConstantSDNode>(SCC.getNode())) {
5549 if (!SCCC->isNullValue())
5550 return N2; // cond always true -> true val
5552 return N3; // cond always false -> false val
5553 } else if (SCC->getOpcode() == ISD::UNDEF) {
5554 // When the condition is UNDEF, just return the first operand. This is
5555 // coherent the DAG creation, no setcc node is created in this case
5557 } else if (SCC.getOpcode() == ISD::SETCC) {
5558 // Fold to a simpler select_cc
5559 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N2.getValueType(),
5560 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
5565 // If we can fold this based on the true/false value, do so.
5566 if (SimplifySelectOps(N, N2, N3))
5567 return SDValue(N, 0); // Don't revisit N.
5569 // fold select_cc into other things, such as min/max/abs
5570 return SimplifySelectCC(SDLoc(N), N0, N1, N2, N3, CC);
5573 SDValue DAGCombiner::visitSETCC(SDNode *N) {
5574 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
5575 cast<CondCodeSDNode>(N->getOperand(2))->get(),
5579 // tryToFoldExtendOfConstant - Try to fold a sext/zext/aext
5580 // dag node into a ConstantSDNode or a build_vector of constants.
5581 // This function is called by the DAGCombiner when visiting sext/zext/aext
5582 // dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND).
5583 // Vector extends are not folded if operations are legal; this is to
5584 // avoid introducing illegal build_vector dag nodes.
5585 static SDNode *tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI,
5586 SelectionDAG &DAG, bool LegalTypes,
5587 bool LegalOperations) {
5588 unsigned Opcode = N->getOpcode();
5589 SDValue N0 = N->getOperand(0);
5590 EVT VT = N->getValueType(0);
5592 assert((Opcode == ISD::SIGN_EXTEND || Opcode == ISD::ZERO_EXTEND ||
5593 Opcode == ISD::ANY_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG)
5594 && "Expected EXTEND dag node in input!");
5596 // fold (sext c1) -> c1
5597 // fold (zext c1) -> c1
5598 // fold (aext c1) -> c1
5599 if (isa<ConstantSDNode>(N0))
5600 return DAG.getNode(Opcode, SDLoc(N), VT, N0).getNode();
5602 // fold (sext (build_vector AllConstants) -> (build_vector AllConstants)
5603 // fold (zext (build_vector AllConstants) -> (build_vector AllConstants)
5604 // fold (aext (build_vector AllConstants) -> (build_vector AllConstants)
5605 EVT SVT = VT.getScalarType();
5606 if (!(VT.isVector() &&
5607 (!LegalTypes || (!LegalOperations && TLI.isTypeLegal(SVT))) &&
5608 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())))
5611 // We can fold this node into a build_vector.
5612 unsigned VTBits = SVT.getSizeInBits();
5613 unsigned EVTBits = N0->getValueType(0).getScalarType().getSizeInBits();
5614 unsigned ShAmt = VTBits - EVTBits;
5615 SmallVector<SDValue, 8> Elts;
5616 unsigned NumElts = VT.getVectorNumElements();
5619 for (unsigned i=0; i != NumElts; ++i) {
5620 SDValue Op = N0->getOperand(i);
5621 if (Op->getOpcode() == ISD::UNDEF) {
5622 Elts.push_back(DAG.getUNDEF(SVT));
5627 ConstantSDNode *CurrentND = cast<ConstantSDNode>(Op);
5628 const APInt &C = APInt(VTBits, CurrentND->getAPIntValue().getZExtValue());
5629 if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG)
5630 Elts.push_back(DAG.getConstant(C.shl(ShAmt).ashr(ShAmt).getZExtValue(),
5633 Elts.push_back(DAG.getConstant(C.shl(ShAmt).lshr(ShAmt).getZExtValue(),
5637 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Elts).getNode();
5640 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
5641 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
5642 // transformation. Returns true if extension are possible and the above
5643 // mentioned transformation is profitable.
5644 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
5646 SmallVectorImpl<SDNode *> &ExtendNodes,
5647 const TargetLowering &TLI) {
5648 bool HasCopyToRegUses = false;
5649 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
5650 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
5651 UE = N0.getNode()->use_end();
5656 if (UI.getUse().getResNo() != N0.getResNo())
5658 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
5659 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
5660 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
5661 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
5662 // Sign bits will be lost after a zext.
5665 for (unsigned i = 0; i != 2; ++i) {
5666 SDValue UseOp = User->getOperand(i);
5669 if (!isa<ConstantSDNode>(UseOp))
5674 ExtendNodes.push_back(User);
5677 // If truncates aren't free and there are users we can't
5678 // extend, it isn't worthwhile.
5681 // Remember if this value is live-out.
5682 if (User->getOpcode() == ISD::CopyToReg)
5683 HasCopyToRegUses = true;
5686 if (HasCopyToRegUses) {
5687 bool BothLiveOut = false;
5688 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
5690 SDUse &Use = UI.getUse();
5691 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
5697 // Both unextended and extended values are live out. There had better be
5698 // a good reason for the transformation.
5699 return ExtendNodes.size();
5704 void DAGCombiner::ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
5705 SDValue Trunc, SDValue ExtLoad, SDLoc DL,
5706 ISD::NodeType ExtType) {
5707 // Extend SetCC uses if necessary.
5708 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
5709 SDNode *SetCC = SetCCs[i];
5710 SmallVector<SDValue, 4> Ops;
5712 for (unsigned j = 0; j != 2; ++j) {
5713 SDValue SOp = SetCC->getOperand(j);
5715 Ops.push_back(ExtLoad);
5717 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
5720 Ops.push_back(SetCC->getOperand(2));
5721 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops));
5725 // FIXME: Bring more similar combines here, common to sext/zext (maybe aext?).
5726 SDValue DAGCombiner::CombineExtLoad(SDNode *N) {
5727 SDValue N0 = N->getOperand(0);
5728 EVT DstVT = N->getValueType(0);
5729 EVT SrcVT = N0.getValueType();
5731 assert((N->getOpcode() == ISD::SIGN_EXTEND ||
5732 N->getOpcode() == ISD::ZERO_EXTEND) &&
5733 "Unexpected node type (not an extend)!");
5735 // fold (sext (load x)) to multiple smaller sextloads; same for zext.
5736 // For example, on a target with legal v4i32, but illegal v8i32, turn:
5737 // (v8i32 (sext (v8i16 (load x))))
5739 // (v8i32 (concat_vectors (v4i32 (sextload x)),
5740 // (v4i32 (sextload (x + 16)))))
5741 // Where uses of the original load, i.e.:
5743 // are replaced with:
5745 // (v8i32 (concat_vectors (v4i32 (sextload x)),
5746 // (v4i32 (sextload (x + 16)))))))
5748 // This combine is only applicable to illegal, but splittable, vectors.
5749 // All legal types, and illegal non-vector types, are handled elsewhere.
5750 // This combine is controlled by TargetLowering::isVectorLoadExtDesirable.
5752 if (N0->getOpcode() != ISD::LOAD)
5755 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5757 if (!ISD::isNON_EXTLoad(LN0) || !ISD::isUNINDEXEDLoad(LN0) ||
5758 !N0.hasOneUse() || LN0->isVolatile() || !DstVT.isVector() ||
5759 !DstVT.isPow2VectorType() || !TLI.isVectorLoadExtDesirable(SDValue(N, 0)))
5762 SmallVector<SDNode *, 4> SetCCs;
5763 if (!ExtendUsesToFormExtLoad(N, N0, N->getOpcode(), SetCCs, TLI))
5766 ISD::LoadExtType ExtType =
5767 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
5769 // Try to split the vector types to get down to legal types.
5770 EVT SplitSrcVT = SrcVT;
5771 EVT SplitDstVT = DstVT;
5772 while (!TLI.isLoadExtLegalOrCustom(ExtType, SplitDstVT, SplitSrcVT) &&
5773 SplitSrcVT.getVectorNumElements() > 1) {
5774 SplitDstVT = DAG.GetSplitDestVTs(SplitDstVT).first;
5775 SplitSrcVT = DAG.GetSplitDestVTs(SplitSrcVT).first;
5778 if (!TLI.isLoadExtLegalOrCustom(ExtType, SplitDstVT, SplitSrcVT))
5782 const unsigned NumSplits =
5783 DstVT.getVectorNumElements() / SplitDstVT.getVectorNumElements();
5784 const unsigned Stride = SplitSrcVT.getStoreSize();
5785 SmallVector<SDValue, 4> Loads;
5786 SmallVector<SDValue, 4> Chains;
5788 SDValue BasePtr = LN0->getBasePtr();
5789 for (unsigned Idx = 0; Idx < NumSplits; Idx++) {
5790 const unsigned Offset = Idx * Stride;
5791 const unsigned Align = MinAlign(LN0->getAlignment(), Offset);
5793 SDValue SplitLoad = DAG.getExtLoad(
5794 ExtType, DL, SplitDstVT, LN0->getChain(), BasePtr,
5795 LN0->getPointerInfo().getWithOffset(Offset), SplitSrcVT,
5796 LN0->isVolatile(), LN0->isNonTemporal(), LN0->isInvariant(),
5797 Align, LN0->getAAInfo());
5799 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
5800 DAG.getConstant(Stride, DL, BasePtr.getValueType()));
5802 Loads.push_back(SplitLoad.getValue(0));
5803 Chains.push_back(SplitLoad.getValue(1));
5806 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
5807 SDValue NewValue = DAG.getNode(ISD::CONCAT_VECTORS, DL, DstVT, Loads);
5809 CombineTo(N, NewValue);
5811 // Replace uses of the original load (before extension)
5812 // with a truncate of the concatenated sextloaded vectors.
5814 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(), NewValue);
5815 CombineTo(N0.getNode(), Trunc, NewChain);
5816 ExtendSetCCUses(SetCCs, Trunc, NewValue, DL,
5817 (ISD::NodeType)N->getOpcode());
5818 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5821 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
5822 SDValue N0 = N->getOperand(0);
5823 EVT VT = N->getValueType(0);
5825 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
5827 return SDValue(Res, 0);
5829 // fold (sext (sext x)) -> (sext x)
5830 // fold (sext (aext x)) -> (sext x)
5831 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
5832 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT,
5835 if (N0.getOpcode() == ISD::TRUNCATE) {
5836 // fold (sext (truncate (load x))) -> (sext (smaller load x))
5837 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
5838 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5839 if (NarrowLoad.getNode()) {
5840 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5841 if (NarrowLoad.getNode() != N0.getNode()) {
5842 CombineTo(N0.getNode(), NarrowLoad);
5843 // CombineTo deleted the truncate, if needed, but not what's under it.
5846 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5849 // See if the value being truncated is already sign extended. If so, just
5850 // eliminate the trunc/sext pair.
5851 SDValue Op = N0.getOperand(0);
5852 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
5853 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
5854 unsigned DestBits = VT.getScalarType().getSizeInBits();
5855 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
5857 if (OpBits == DestBits) {
5858 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
5859 // bits, it is already ready.
5860 if (NumSignBits > DestBits-MidBits)
5862 } else if (OpBits < DestBits) {
5863 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
5864 // bits, just sext from i32.
5865 if (NumSignBits > OpBits-MidBits)
5866 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, Op);
5868 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
5869 // bits, just truncate to i32.
5870 if (NumSignBits > OpBits-MidBits)
5871 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
5874 // fold (sext (truncate x)) -> (sextinreg x).
5875 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
5876 N0.getValueType())) {
5877 if (OpBits < DestBits)
5878 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N0), VT, Op);
5879 else if (OpBits > DestBits)
5880 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT, Op);
5881 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, Op,
5882 DAG.getValueType(N0.getValueType()));
5886 // fold (sext (load x)) -> (sext (truncate (sextload x)))
5887 // Only generate vector extloads when 1) they're legal, and 2) they are
5888 // deemed desirable by the target.
5889 if (ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5890 ((!LegalOperations && !VT.isVector() &&
5891 !cast<LoadSDNode>(N0)->isVolatile()) ||
5892 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, N0.getValueType()))) {
5893 bool DoXform = true;
5894 SmallVector<SDNode*, 4> SetCCs;
5895 if (!N0.hasOneUse())
5896 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
5898 DoXform &= TLI.isVectorLoadExtDesirable(SDValue(N, 0));
5900 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5901 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5903 LN0->getBasePtr(), N0.getValueType(),
5904 LN0->getMemOperand());
5905 CombineTo(N, ExtLoad);
5906 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5907 N0.getValueType(), ExtLoad);
5908 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
5909 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5911 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5915 // fold (sext (load x)) to multiple smaller sextloads.
5916 // Only on illegal but splittable vectors.
5917 if (SDValue ExtLoad = CombineExtLoad(N))
5920 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
5921 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
5922 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
5923 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
5924 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5925 EVT MemVT = LN0->getMemoryVT();
5926 if ((!LegalOperations && !LN0->isVolatile()) ||
5927 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, MemVT)) {
5928 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5930 LN0->getBasePtr(), MemVT,
5931 LN0->getMemOperand());
5932 CombineTo(N, ExtLoad);
5933 CombineTo(N0.getNode(),
5934 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5935 N0.getValueType(), ExtLoad),
5936 ExtLoad.getValue(1));
5937 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5941 // fold (sext (and/or/xor (load x), cst)) ->
5942 // (and/or/xor (sextload x), (sext cst))
5943 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
5944 N0.getOpcode() == ISD::XOR) &&
5945 isa<LoadSDNode>(N0.getOperand(0)) &&
5946 N0.getOperand(1).getOpcode() == ISD::Constant &&
5947 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, N0.getValueType()) &&
5948 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
5949 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
5950 if (LN0->getExtensionType() != ISD::ZEXTLOAD && LN0->isUnindexed()) {
5951 bool DoXform = true;
5952 SmallVector<SDNode*, 4> SetCCs;
5953 if (!N0.hasOneUse())
5954 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
5957 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(LN0), VT,
5958 LN0->getChain(), LN0->getBasePtr(),
5960 LN0->getMemOperand());
5961 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5962 Mask = Mask.sext(VT.getSizeInBits());
5964 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT,
5965 ExtLoad, DAG.getConstant(Mask, DL, VT));
5966 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
5967 SDLoc(N0.getOperand(0)),
5968 N0.getOperand(0).getValueType(), ExtLoad);
5970 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
5971 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, DL,
5973 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5978 if (N0.getOpcode() == ISD::SETCC) {
5979 EVT N0VT = N0.getOperand(0).getValueType();
5980 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
5981 // Only do this before legalize for now.
5982 if (VT.isVector() && !LegalOperations &&
5983 TLI.getBooleanContents(N0VT) ==
5984 TargetLowering::ZeroOrNegativeOneBooleanContent) {
5985 // On some architectures (such as SSE/NEON/etc) the SETCC result type is
5986 // of the same size as the compared operands. Only optimize sext(setcc())
5987 // if this is the case.
5988 EVT SVT = getSetCCResultType(N0VT);
5990 // We know that the # elements of the results is the same as the
5991 // # elements of the compare (and the # elements of the compare result
5992 // for that matter). Check to see that they are the same size. If so,
5993 // we know that the element size of the sext'd result matches the
5994 // element size of the compare operands.
5995 if (VT.getSizeInBits() == SVT.getSizeInBits())
5996 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
5998 cast<CondCodeSDNode>(N0.getOperand(2))->get());
6000 // If the desired elements are smaller or larger than the source
6001 // elements we can use a matching integer vector type and then
6002 // truncate/sign extend
6003 EVT MatchingVectorType = N0VT.changeVectorElementTypeToInteger();
6004 if (SVT == MatchingVectorType) {
6005 SDValue VsetCC = DAG.getSetCC(SDLoc(N), MatchingVectorType,
6006 N0.getOperand(0), N0.getOperand(1),
6007 cast<CondCodeSDNode>(N0.getOperand(2))->get());
6008 return DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT);
6012 // sext(setcc x, y, cc) -> (select (setcc x, y, cc), -1, 0)
6013 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
6016 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), DL, VT);
6018 SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1),
6019 NegOne, DAG.getConstant(0, DL, VT),
6020 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
6021 if (SCC.getNode()) return SCC;
6023 if (!VT.isVector()) {
6024 EVT SetCCVT = getSetCCResultType(N0.getOperand(0).getValueType());
6025 if (!LegalOperations || TLI.isOperationLegal(ISD::SETCC, SetCCVT)) {
6027 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
6028 SDValue SetCC = DAG.getSetCC(DL, SetCCVT,
6029 N0.getOperand(0), N0.getOperand(1), CC);
6030 return DAG.getSelect(DL, VT, SetCC,
6031 NegOne, DAG.getConstant(0, DL, VT));
6036 // fold (sext x) -> (zext x) if the sign bit is known zero.
6037 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
6038 DAG.SignBitIsZero(N0))
6039 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0);
6044 // isTruncateOf - If N is a truncate of some other value, return true, record
6045 // the value being truncated in Op and which of Op's bits are zero in KnownZero.
6046 // This function computes KnownZero to avoid a duplicated call to
6047 // computeKnownBits in the caller.
6048 static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
6051 if (N->getOpcode() == ISD::TRUNCATE) {
6052 Op = N->getOperand(0);
6053 DAG.computeKnownBits(Op, KnownZero, KnownOne);
6057 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 ||
6058 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE)
6061 SDValue Op0 = N->getOperand(0);
6062 SDValue Op1 = N->getOperand(1);
6063 assert(Op0.getValueType() == Op1.getValueType());
6065 if (isNullConstant(Op0))
6067 else if (isNullConstant(Op1))
6072 DAG.computeKnownBits(Op, KnownZero, KnownOne);
6074 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue())
6080 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
6081 SDValue N0 = N->getOperand(0);
6082 EVT VT = N->getValueType(0);
6084 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
6086 return SDValue(Res, 0);
6088 // fold (zext (zext x)) -> (zext x)
6089 // fold (zext (aext x)) -> (zext x)
6090 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
6091 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT,
6094 // fold (zext (truncate x)) -> (zext x) or
6095 // (zext (truncate x)) -> (truncate x)
6096 // This is valid when the truncated bits of x are already zero.
6097 // FIXME: We should extend this to work for vectors too.
6100 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) {
6101 APInt TruncatedBits =
6102 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ?
6103 APInt(Op.getValueSizeInBits(), 0) :
6104 APInt::getBitsSet(Op.getValueSizeInBits(),
6105 N0.getValueSizeInBits(),
6106 std::min(Op.getValueSizeInBits(),
6107 VT.getSizeInBits()));
6108 if (TruncatedBits == (KnownZero & TruncatedBits)) {
6109 if (VT.bitsGT(Op.getValueType()))
6110 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, Op);
6111 if (VT.bitsLT(Op.getValueType()))
6112 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
6118 // fold (zext (truncate (load x))) -> (zext (smaller load x))
6119 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
6120 if (N0.getOpcode() == ISD::TRUNCATE) {
6121 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
6122 if (NarrowLoad.getNode()) {
6123 SDNode* oye = N0.getNode()->getOperand(0).getNode();
6124 if (NarrowLoad.getNode() != N0.getNode()) {
6125 CombineTo(N0.getNode(), NarrowLoad);
6126 // CombineTo deleted the truncate, if needed, but not what's under it.
6129 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6133 // fold (zext (truncate x)) -> (and x, mask)
6134 if (N0.getOpcode() == ISD::TRUNCATE &&
6135 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
6137 // fold (zext (truncate (load x))) -> (zext (smaller load x))
6138 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
6139 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
6140 if (NarrowLoad.getNode()) {
6141 SDNode* oye = N0.getNode()->getOperand(0).getNode();
6142 if (NarrowLoad.getNode() != N0.getNode()) {
6143 CombineTo(N0.getNode(), NarrowLoad);
6144 // CombineTo deleted the truncate, if needed, but not what's under it.
6147 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6150 SDValue Op = N0.getOperand(0);
6151 if (Op.getValueType().bitsLT(VT)) {
6152 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, Op);
6153 AddToWorklist(Op.getNode());
6154 } else if (Op.getValueType().bitsGT(VT)) {
6155 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
6156 AddToWorklist(Op.getNode());
6158 return DAG.getZeroExtendInReg(Op, SDLoc(N),
6159 N0.getValueType().getScalarType());
6162 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
6163 // if either of the casts is not free.
6164 if (N0.getOpcode() == ISD::AND &&
6165 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
6166 N0.getOperand(1).getOpcode() == ISD::Constant &&
6167 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
6168 N0.getValueType()) ||
6169 !TLI.isZExtFree(N0.getValueType(), VT))) {
6170 SDValue X = N0.getOperand(0).getOperand(0);
6171 if (X.getValueType().bitsLT(VT)) {
6172 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(X), VT, X);
6173 } else if (X.getValueType().bitsGT(VT)) {
6174 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);
6176 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
6177 Mask = Mask.zext(VT.getSizeInBits());
6179 return DAG.getNode(ISD::AND, DL, VT,
6180 X, DAG.getConstant(Mask, DL, VT));
6183 // fold (zext (load x)) -> (zext (truncate (zextload x)))
6184 // Only generate vector extloads when 1) they're legal, and 2) they are
6185 // deemed desirable by the target.
6186 if (ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
6187 ((!LegalOperations && !VT.isVector() &&
6188 !cast<LoadSDNode>(N0)->isVolatile()) ||
6189 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, N0.getValueType()))) {
6190 bool DoXform = true;
6191 SmallVector<SDNode*, 4> SetCCs;
6192 if (!N0.hasOneUse())
6193 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
6195 DoXform &= TLI.isVectorLoadExtDesirable(SDValue(N, 0));
6197 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6198 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
6200 LN0->getBasePtr(), N0.getValueType(),
6201 LN0->getMemOperand());
6202 CombineTo(N, ExtLoad);
6203 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
6204 N0.getValueType(), ExtLoad);
6205 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
6207 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
6209 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6213 // fold (zext (load x)) to multiple smaller zextloads.
6214 // Only on illegal but splittable vectors.
6215 if (SDValue ExtLoad = CombineExtLoad(N))
6218 // fold (zext (and/or/xor (load x), cst)) ->
6219 // (and/or/xor (zextload x), (zext cst))
6220 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
6221 N0.getOpcode() == ISD::XOR) &&
6222 isa<LoadSDNode>(N0.getOperand(0)) &&
6223 N0.getOperand(1).getOpcode() == ISD::Constant &&
6224 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, N0.getValueType()) &&
6225 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
6226 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
6227 if (LN0->getExtensionType() != ISD::SEXTLOAD && LN0->isUnindexed()) {
6228 bool DoXform = true;
6229 SmallVector<SDNode*, 4> SetCCs;
6230 if (!N0.hasOneUse())
6231 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
6234 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), VT,
6235 LN0->getChain(), LN0->getBasePtr(),
6237 LN0->getMemOperand());
6238 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
6239 Mask = Mask.zext(VT.getSizeInBits());
6241 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT,
6242 ExtLoad, DAG.getConstant(Mask, DL, VT));
6243 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
6244 SDLoc(N0.getOperand(0)),
6245 N0.getOperand(0).getValueType(), ExtLoad);
6247 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
6248 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, DL,
6250 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6255 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
6256 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
6257 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
6258 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
6259 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6260 EVT MemVT = LN0->getMemoryVT();
6261 if ((!LegalOperations && !LN0->isVolatile()) ||
6262 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT)) {
6263 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
6265 LN0->getBasePtr(), MemVT,
6266 LN0->getMemOperand());
6267 CombineTo(N, ExtLoad);
6268 CombineTo(N0.getNode(),
6269 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(),
6271 ExtLoad.getValue(1));
6272 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6276 if (N0.getOpcode() == ISD::SETCC) {
6277 if (!LegalOperations && VT.isVector() &&
6278 N0.getValueType().getVectorElementType() == MVT::i1) {
6279 EVT N0VT = N0.getOperand(0).getValueType();
6280 if (getSetCCResultType(N0VT) == N0.getValueType())
6283 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
6284 // Only do this before legalize for now.
6285 EVT EltVT = VT.getVectorElementType();
6287 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
6288 DAG.getConstant(1, DL, EltVT));
6289 if (VT.getSizeInBits() == N0VT.getSizeInBits())
6290 // We know that the # elements of the results is the same as the
6291 // # elements of the compare (and the # elements of the compare result
6292 // for that matter). Check to see that they are the same size. If so,
6293 // we know that the element size of the sext'd result matches the
6294 // element size of the compare operands.
6295 return DAG.getNode(ISD::AND, DL, VT,
6296 DAG.getSetCC(DL, VT, N0.getOperand(0),
6298 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
6299 DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
6302 // If the desired elements are smaller or larger than the source
6303 // elements we can use a matching integer vector type and then
6304 // truncate/sign extend
6305 EVT MatchingElementType =
6306 EVT::getIntegerVT(*DAG.getContext(),
6307 N0VT.getScalarType().getSizeInBits());
6308 EVT MatchingVectorType =
6309 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
6310 N0VT.getVectorNumElements());
6312 DAG.getSetCC(DL, MatchingVectorType, N0.getOperand(0),
6314 cast<CondCodeSDNode>(N0.getOperand(2))->get());
6315 return DAG.getNode(ISD::AND, DL, VT,
6316 DAG.getSExtOrTrunc(VsetCC, DL, VT),
6317 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, OneOps));
6320 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
6323 SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1),
6324 DAG.getConstant(1, DL, VT), DAG.getConstant(0, DL, VT),
6325 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
6326 if (SCC.getNode()) return SCC;
6329 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
6330 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
6331 isa<ConstantSDNode>(N0.getOperand(1)) &&
6332 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
6334 SDValue ShAmt = N0.getOperand(1);
6335 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
6336 if (N0.getOpcode() == ISD::SHL) {
6337 SDValue InnerZExt = N0.getOperand(0);
6338 // If the original shl may be shifting out bits, do not perform this
6340 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
6341 InnerZExt.getOperand(0).getValueType().getSizeInBits();
6342 if (ShAmtVal > KnownZeroBits)
6348 // Ensure that the shift amount is wide enough for the shifted value.
6349 if (VT.getSizeInBits() >= 256)
6350 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
6352 return DAG.getNode(N0.getOpcode(), DL, VT,
6353 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
6360 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
6361 SDValue N0 = N->getOperand(0);
6362 EVT VT = N->getValueType(0);
6364 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
6366 return SDValue(Res, 0);
6368 // fold (aext (aext x)) -> (aext x)
6369 // fold (aext (zext x)) -> (zext x)
6370 // fold (aext (sext x)) -> (sext x)
6371 if (N0.getOpcode() == ISD::ANY_EXTEND ||
6372 N0.getOpcode() == ISD::ZERO_EXTEND ||
6373 N0.getOpcode() == ISD::SIGN_EXTEND)
6374 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0));
6376 // fold (aext (truncate (load x))) -> (aext (smaller load x))
6377 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
6378 if (N0.getOpcode() == ISD::TRUNCATE) {
6379 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
6380 if (NarrowLoad.getNode()) {
6381 SDNode* oye = N0.getNode()->getOperand(0).getNode();
6382 if (NarrowLoad.getNode() != N0.getNode()) {
6383 CombineTo(N0.getNode(), NarrowLoad);
6384 // CombineTo deleted the truncate, if needed, but not what's under it.
6387 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6391 // fold (aext (truncate x))
6392 if (N0.getOpcode() == ISD::TRUNCATE) {
6393 SDValue TruncOp = N0.getOperand(0);
6394 if (TruncOp.getValueType() == VT)
6395 return TruncOp; // x iff x size == zext size.
6396 if (TruncOp.getValueType().bitsGT(VT))
6397 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, TruncOp);
6398 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, TruncOp);
6401 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
6402 // if the trunc is not free.
6403 if (N0.getOpcode() == ISD::AND &&
6404 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
6405 N0.getOperand(1).getOpcode() == ISD::Constant &&
6406 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
6407 N0.getValueType())) {
6408 SDValue X = N0.getOperand(0).getOperand(0);
6409 if (X.getValueType().bitsLT(VT)) {
6410 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, X);
6411 } else if (X.getValueType().bitsGT(VT)) {
6412 X = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, X);
6414 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
6415 Mask = Mask.zext(VT.getSizeInBits());
6417 return DAG.getNode(ISD::AND, DL, VT,
6418 X, DAG.getConstant(Mask, DL, VT));
6421 // fold (aext (load x)) -> (aext (truncate (extload x)))
6422 // None of the supported targets knows how to perform load and any_ext
6423 // on vectors in one instruction. We only perform this transformation on
6425 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
6426 ISD::isUNINDEXEDLoad(N0.getNode()) &&
6427 TLI.isLoadExtLegal(ISD::EXTLOAD, VT, N0.getValueType())) {
6428 bool DoXform = true;
6429 SmallVector<SDNode*, 4> SetCCs;
6430 if (!N0.hasOneUse())
6431 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
6433 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6434 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
6436 LN0->getBasePtr(), N0.getValueType(),
6437 LN0->getMemOperand());
6438 CombineTo(N, ExtLoad);
6439 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
6440 N0.getValueType(), ExtLoad);
6441 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
6442 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
6444 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6448 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
6449 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
6450 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
6451 if (N0.getOpcode() == ISD::LOAD &&
6452 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
6454 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6455 ISD::LoadExtType ExtType = LN0->getExtensionType();
6456 EVT MemVT = LN0->getMemoryVT();
6457 if (!LegalOperations || TLI.isLoadExtLegal(ExtType, VT, MemVT)) {
6458 SDValue ExtLoad = DAG.getExtLoad(ExtType, SDLoc(N),
6459 VT, LN0->getChain(), LN0->getBasePtr(),
6460 MemVT, LN0->getMemOperand());
6461 CombineTo(N, ExtLoad);
6462 CombineTo(N0.getNode(),
6463 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
6464 N0.getValueType(), ExtLoad),
6465 ExtLoad.getValue(1));
6466 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6470 if (N0.getOpcode() == ISD::SETCC) {
6472 // aext(setcc) -> vsetcc
6473 // aext(setcc) -> truncate(vsetcc)
6474 // aext(setcc) -> aext(vsetcc)
6475 // Only do this before legalize for now.
6476 if (VT.isVector() && !LegalOperations) {
6477 EVT N0VT = N0.getOperand(0).getValueType();
6478 // We know that the # elements of the results is the same as the
6479 // # elements of the compare (and the # elements of the compare result
6480 // for that matter). Check to see that they are the same size. If so,
6481 // we know that the element size of the sext'd result matches the
6482 // element size of the compare operands.
6483 if (VT.getSizeInBits() == N0VT.getSizeInBits())
6484 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
6486 cast<CondCodeSDNode>(N0.getOperand(2))->get());
6487 // If the desired elements are smaller or larger than the source
6488 // elements we can use a matching integer vector type and then
6489 // truncate/any extend
6491 EVT MatchingVectorType = N0VT.changeVectorElementTypeToInteger();
6493 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0),
6495 cast<CondCodeSDNode>(N0.getOperand(2))->get());
6496 return DAG.getAnyExtOrTrunc(VsetCC, SDLoc(N), VT);
6500 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
6503 SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1),
6504 DAG.getConstant(1, DL, VT), DAG.getConstant(0, DL, VT),
6505 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
6513 /// See if the specified operand can be simplified with the knowledge that only
6514 /// the bits specified by Mask are used. If so, return the simpler operand,
6515 /// otherwise return a null SDValue.
6516 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
6517 switch (V.getOpcode()) {
6519 case ISD::Constant: {
6520 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode());
6521 assert(CV && "Const value should be ConstSDNode.");
6522 const APInt &CVal = CV->getAPIntValue();
6523 APInt NewVal = CVal & Mask;
6525 return DAG.getConstant(NewVal, SDLoc(V), V.getValueType());
6530 // If the LHS or RHS don't contribute bits to the or, drop them.
6531 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
6532 return V.getOperand(1);
6533 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
6534 return V.getOperand(0);
6537 // Only look at single-use SRLs.
6538 if (!V.getNode()->hasOneUse())
6540 if (ConstantSDNode *RHSC = getAsNonOpaqueConstant(V.getOperand(1))) {
6541 // See if we can recursively simplify the LHS.
6542 unsigned Amt = RHSC->getZExtValue();
6544 // Watch out for shift count overflow though.
6545 if (Amt >= Mask.getBitWidth()) break;
6546 APInt NewMask = Mask << Amt;
6547 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
6548 if (SimplifyLHS.getNode())
6549 return DAG.getNode(ISD::SRL, SDLoc(V), V.getValueType(),
6550 SimplifyLHS, V.getOperand(1));
6556 /// If the result of a wider load is shifted to right of N bits and then
6557 /// truncated to a narrower type and where N is a multiple of number of bits of
6558 /// the narrower type, transform it to a narrower load from address + N / num of
6559 /// bits of new type. If the result is to be extended, also fold the extension
6560 /// to form a extending load.
6561 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
6562 unsigned Opc = N->getOpcode();
6564 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
6565 SDValue N0 = N->getOperand(0);
6566 EVT VT = N->getValueType(0);
6569 // This transformation isn't valid for vector loads.
6573 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
6575 if (Opc == ISD::SIGN_EXTEND_INREG) {
6576 ExtType = ISD::SEXTLOAD;
6577 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
6578 } else if (Opc == ISD::SRL) {
6579 // Another special-case: SRL is basically zero-extending a narrower value.
6580 ExtType = ISD::ZEXTLOAD;
6582 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
6583 if (!N01) return SDValue();
6584 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
6585 VT.getSizeInBits() - N01->getZExtValue());
6587 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, VT, ExtVT))
6590 unsigned EVTBits = ExtVT.getSizeInBits();
6592 // Do not generate loads of non-round integer types since these can
6593 // be expensive (and would be wrong if the type is not byte sized).
6594 if (!ExtVT.isRound())
6598 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
6599 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
6600 ShAmt = N01->getZExtValue();
6601 // Is the shift amount a multiple of size of VT?
6602 if ((ShAmt & (EVTBits-1)) == 0) {
6603 N0 = N0.getOperand(0);
6604 // Is the load width a multiple of size of VT?
6605 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
6609 // At this point, we must have a load or else we can't do the transform.
6610 if (!isa<LoadSDNode>(N0)) return SDValue();
6612 // Because a SRL must be assumed to *need* to zero-extend the high bits
6613 // (as opposed to anyext the high bits), we can't combine the zextload
6614 // lowering of SRL and an sextload.
6615 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD)
6618 // If the shift amount is larger than the input type then we're not
6619 // accessing any of the loaded bytes. If the load was a zextload/extload
6620 // then the result of the shift+trunc is zero/undef (handled elsewhere).
6621 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
6626 // If the load is shifted left (and the result isn't shifted back right),
6627 // we can fold the truncate through the shift.
6628 unsigned ShLeftAmt = 0;
6629 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
6630 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
6631 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
6632 ShLeftAmt = N01->getZExtValue();
6633 N0 = N0.getOperand(0);
6637 // If we haven't found a load, we can't narrow it. Don't transform one with
6638 // multiple uses, this would require adding a new load.
6639 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse())
6642 // Don't change the width of a volatile load.
6643 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6644 if (LN0->isVolatile())
6647 // Verify that we are actually reducing a load width here.
6648 if (LN0->getMemoryVT().getSizeInBits() < EVTBits)
6651 // For the transform to be legal, the load must produce only two values
6652 // (the value loaded and the chain). Don't transform a pre-increment
6653 // load, for example, which produces an extra value. Otherwise the
6654 // transformation is not equivalent, and the downstream logic to replace
6655 // uses gets things wrong.
6656 if (LN0->getNumValues() > 2)
6659 // If the load that we're shrinking is an extload and we're not just
6660 // discarding the extension we can't simply shrink the load. Bail.
6661 // TODO: It would be possible to merge the extensions in some cases.
6662 if (LN0->getExtensionType() != ISD::NON_EXTLOAD &&
6663 LN0->getMemoryVT().getSizeInBits() < ExtVT.getSizeInBits() + ShAmt)
6666 if (!TLI.shouldReduceLoadWidth(LN0, ExtType, ExtVT))
6669 EVT PtrType = N0.getOperand(1).getValueType();
6671 if (PtrType == MVT::Untyped || PtrType.isExtended())
6672 // It's not possible to generate a constant of extended or untyped type.
6675 // For big endian targets, we need to adjust the offset to the pointer to
6676 // load the correct bytes.
6677 if (TLI.isBigEndian()) {
6678 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
6679 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
6680 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
6683 uint64_t PtrOff = ShAmt / 8;
6684 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
6686 SDValue NewPtr = DAG.getNode(ISD::ADD, DL,
6687 PtrType, LN0->getBasePtr(),
6688 DAG.getConstant(PtrOff, DL, PtrType));
6689 AddToWorklist(NewPtr.getNode());
6692 if (ExtType == ISD::NON_EXTLOAD)
6693 Load = DAG.getLoad(VT, SDLoc(N0), LN0->getChain(), NewPtr,
6694 LN0->getPointerInfo().getWithOffset(PtrOff),
6695 LN0->isVolatile(), LN0->isNonTemporal(),
6696 LN0->isInvariant(), NewAlign, LN0->getAAInfo());
6698 Load = DAG.getExtLoad(ExtType, SDLoc(N0), VT, LN0->getChain(),NewPtr,
6699 LN0->getPointerInfo().getWithOffset(PtrOff),
6700 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
6701 LN0->isInvariant(), NewAlign, LN0->getAAInfo());
6703 // Replace the old load's chain with the new load's chain.
6704 WorklistRemover DeadNodes(*this);
6705 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
6707 // Shift the result left, if we've swallowed a left shift.
6708 SDValue Result = Load;
6709 if (ShLeftAmt != 0) {
6710 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
6711 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
6713 // If the shift amount is as large as the result size (but, presumably,
6714 // no larger than the source) then the useful bits of the result are
6715 // zero; we can't simply return the shortened shift, because the result
6716 // of that operation is undefined.
6718 if (ShLeftAmt >= VT.getSizeInBits())
6719 Result = DAG.getConstant(0, DL, VT);
6721 Result = DAG.getNode(ISD::SHL, DL, VT,
6722 Result, DAG.getConstant(ShLeftAmt, DL, ShImmTy));
6725 // Return the new loaded value.
6729 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
6730 SDValue N0 = N->getOperand(0);
6731 SDValue N1 = N->getOperand(1);
6732 EVT VT = N->getValueType(0);
6733 EVT EVT = cast<VTSDNode>(N1)->getVT();
6734 unsigned VTBits = VT.getScalarType().getSizeInBits();
6735 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
6737 // fold (sext_in_reg c1) -> c1
6738 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
6739 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, N0, N1);
6741 // If the input is already sign extended, just drop the extension.
6742 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
6745 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
6746 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
6747 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT()))
6748 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
6749 N0.getOperand(0), N1);
6751 // fold (sext_in_reg (sext x)) -> (sext x)
6752 // fold (sext_in_reg (aext x)) -> (sext x)
6753 // if x is small enough.
6754 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
6755 SDValue N00 = N0.getOperand(0);
6756 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
6757 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
6758 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00, N1);
6761 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
6762 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
6763 return DAG.getZeroExtendInReg(N0, SDLoc(N), EVT);
6765 // fold operands of sext_in_reg based on knowledge that the top bits are not
6767 if (SimplifyDemandedBits(SDValue(N, 0)))
6768 return SDValue(N, 0);
6770 // fold (sext_in_reg (load x)) -> (smaller sextload x)
6771 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
6772 SDValue NarrowLoad = ReduceLoadWidth(N);
6773 if (NarrowLoad.getNode())
6776 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
6777 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
6778 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
6779 if (N0.getOpcode() == ISD::SRL) {
6780 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
6781 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
6782 // We can turn this into an SRA iff the input to the SRL is already sign
6784 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
6785 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
6786 return DAG.getNode(ISD::SRA, SDLoc(N), VT,
6787 N0.getOperand(0), N0.getOperand(1));
6791 // fold (sext_inreg (extload x)) -> (sextload x)
6792 if (ISD::isEXTLoad(N0.getNode()) &&
6793 ISD::isUNINDEXEDLoad(N0.getNode()) &&
6794 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
6795 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6796 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, EVT))) {
6797 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6798 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
6800 LN0->getBasePtr(), EVT,
6801 LN0->getMemOperand());
6802 CombineTo(N, ExtLoad);
6803 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
6804 AddToWorklist(ExtLoad.getNode());
6805 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6807 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
6808 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
6810 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
6811 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6812 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, EVT))) {
6813 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6814 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
6816 LN0->getBasePtr(), EVT,
6817 LN0->getMemOperand());
6818 CombineTo(N, ExtLoad);
6819 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
6820 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6823 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
6824 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
6825 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
6826 N0.getOperand(1), false);
6827 if (BSwap.getNode())
6828 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
6832 // Fold a sext_inreg of a build_vector of ConstantSDNodes or undefs
6833 // into a build_vector.
6834 if (ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
6835 SmallVector<SDValue, 8> Elts;
6836 unsigned NumElts = N0->getNumOperands();
6837 unsigned ShAmt = VTBits - EVTBits;
6839 for (unsigned i = 0; i != NumElts; ++i) {
6840 SDValue Op = N0->getOperand(i);
6841 if (Op->getOpcode() == ISD::UNDEF) {
6846 ConstantSDNode *CurrentND = cast<ConstantSDNode>(Op);
6847 const APInt &C = APInt(VTBits, CurrentND->getAPIntValue().getZExtValue());
6848 Elts.push_back(DAG.getConstant(C.shl(ShAmt).ashr(ShAmt).getZExtValue(),
6849 SDLoc(Op), Op.getValueType()));
6852 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Elts);
6858 SDValue DAGCombiner::visitSIGN_EXTEND_VECTOR_INREG(SDNode *N) {
6859 SDValue N0 = N->getOperand(0);
6860 EVT VT = N->getValueType(0);
6862 if (N0.getOpcode() == ISD::UNDEF)
6863 return DAG.getUNDEF(VT);
6865 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
6867 return SDValue(Res, 0);
6872 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
6873 SDValue N0 = N->getOperand(0);
6874 EVT VT = N->getValueType(0);
6875 bool isLE = TLI.isLittleEndian();
6878 if (N0.getValueType() == N->getValueType(0))
6880 // fold (truncate c1) -> c1
6881 if (isConstantIntBuildVectorOrConstantInt(N0))
6882 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0);
6883 // fold (truncate (truncate x)) -> (truncate x)
6884 if (N0.getOpcode() == ISD::TRUNCATE)
6885 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
6886 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
6887 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
6888 N0.getOpcode() == ISD::SIGN_EXTEND ||
6889 N0.getOpcode() == ISD::ANY_EXTEND) {
6890 if (N0.getOperand(0).getValueType().bitsLT(VT))
6891 // if the source is smaller than the dest, we still need an extend
6892 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
6894 if (N0.getOperand(0).getValueType().bitsGT(VT))
6895 // if the source is larger than the dest, than we just need the truncate
6896 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
6897 // if the source and dest are the same type, we can drop both the extend
6898 // and the truncate.
6899 return N0.getOperand(0);
6902 // Fold extract-and-trunc into a narrow extract. For example:
6903 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
6904 // i32 y = TRUNCATE(i64 x)
6906 // v16i8 b = BITCAST (v2i64 val)
6907 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8)
6909 // Note: We only run this optimization after type legalization (which often
6910 // creates this pattern) and before operation legalization after which
6911 // we need to be more careful about the vector instructions that we generate.
6912 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6913 LegalTypes && !LegalOperations && N0->hasOneUse() && VT != MVT::i1) {
6915 EVT VecTy = N0.getOperand(0).getValueType();
6916 EVT ExTy = N0.getValueType();
6917 EVT TrTy = N->getValueType(0);
6919 unsigned NumElem = VecTy.getVectorNumElements();
6920 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits();
6922 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem);
6923 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size");
6925 SDValue EltNo = N0->getOperand(1);
6926 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
6927 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6928 EVT IndexTy = TLI.getVectorIdxTy();
6929 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
6931 SDValue V = DAG.getNode(ISD::BITCAST, SDLoc(N),
6932 NVT, N0.getOperand(0));
6935 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
6937 DAG.getConstant(Index, DL, IndexTy));
6941 // trunc (select c, a, b) -> select c, (trunc a), (trunc b)
6942 if (N0.getOpcode() == ISD::SELECT) {
6943 EVT SrcVT = N0.getValueType();
6944 if ((!LegalOperations || TLI.isOperationLegal(ISD::SELECT, SrcVT)) &&
6945 TLI.isTruncateFree(SrcVT, VT)) {
6947 SDValue Cond = N0.getOperand(0);
6948 SDValue TruncOp0 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(1));
6949 SDValue TruncOp1 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(2));
6950 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, Cond, TruncOp0, TruncOp1);
6954 // Fold a series of buildvector, bitcast, and truncate if possible.
6956 // (2xi32 trunc (bitcast ((4xi32)buildvector x, x, y, y) 2xi64)) to
6957 // (2xi32 (buildvector x, y)).
6958 if (Level == AfterLegalizeVectorOps && VT.isVector() &&
6959 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
6960 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
6961 N0.getOperand(0).hasOneUse()) {
6963 SDValue BuildVect = N0.getOperand(0);
6964 EVT BuildVectEltTy = BuildVect.getValueType().getVectorElementType();
6965 EVT TruncVecEltTy = VT.getVectorElementType();
6967 // Check that the element types match.
6968 if (BuildVectEltTy == TruncVecEltTy) {
6969 // Now we only need to compute the offset of the truncated elements.
6970 unsigned BuildVecNumElts = BuildVect.getNumOperands();
6971 unsigned TruncVecNumElts = VT.getVectorNumElements();
6972 unsigned TruncEltOffset = BuildVecNumElts / TruncVecNumElts;
6974 assert((BuildVecNumElts % TruncVecNumElts) == 0 &&
6975 "Invalid number of elements");
6977 SmallVector<SDValue, 8> Opnds;
6978 for (unsigned i = 0, e = BuildVecNumElts; i != e; i += TruncEltOffset)
6979 Opnds.push_back(BuildVect.getOperand(i));
6981 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Opnds);
6985 // See if we can simplify the input to this truncate through knowledge that
6986 // only the low bits are being used.
6987 // For example "trunc (or (shl x, 8), y)" // -> trunc y
6988 // Currently we only perform this optimization on scalars because vectors
6989 // may have different active low bits.
6990 if (!VT.isVector()) {
6992 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
6993 VT.getSizeInBits()));
6994 if (Shorter.getNode())
6995 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Shorter);
6997 // fold (truncate (load x)) -> (smaller load x)
6998 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
6999 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
7000 SDValue Reduced = ReduceLoadWidth(N);
7001 if (Reduced.getNode())
7003 // Handle the case where the load remains an extending load even
7004 // after truncation.
7005 if (N0.hasOneUse() && ISD::isUNINDEXEDLoad(N0.getNode())) {
7006 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7007 if (!LN0->isVolatile() &&
7008 LN0->getMemoryVT().getStoreSizeInBits() < VT.getSizeInBits()) {
7009 SDValue NewLoad = DAG.getExtLoad(LN0->getExtensionType(), SDLoc(LN0),
7010 VT, LN0->getChain(), LN0->getBasePtr(),
7012 LN0->getMemOperand());
7013 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLoad.getValue(1));
7018 // fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)),
7019 // where ... are all 'undef'.
7020 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) {
7021 SmallVector<EVT, 8> VTs;
7024 unsigned NumDefs = 0;
7026 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
7027 SDValue X = N0.getOperand(i);
7028 if (X.getOpcode() != ISD::UNDEF) {
7033 // Stop if more than one members are non-undef.
7036 VTs.push_back(EVT::getVectorVT(*DAG.getContext(),
7037 VT.getVectorElementType(),
7038 X.getValueType().getVectorNumElements()));
7042 return DAG.getUNDEF(VT);
7045 assert(V.getNode() && "The single defined operand is empty!");
7046 SmallVector<SDValue, 8> Opnds;
7047 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
7049 Opnds.push_back(DAG.getUNDEF(VTs[i]));
7052 SDValue NV = DAG.getNode(ISD::TRUNCATE, SDLoc(V), VTs[i], V);
7053 AddToWorklist(NV.getNode());
7054 Opnds.push_back(NV);
7056 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Opnds);
7060 // Simplify the operands using demanded-bits information.
7061 if (!VT.isVector() &&
7062 SimplifyDemandedBits(SDValue(N, 0)))
7063 return SDValue(N, 0);
7068 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
7069 SDValue Elt = N->getOperand(i);
7070 if (Elt.getOpcode() != ISD::MERGE_VALUES)
7071 return Elt.getNode();
7072 return Elt.getOperand(Elt.getResNo()).getNode();
7075 /// build_pair (load, load) -> load
7076 /// if load locations are consecutive.
7077 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
7078 assert(N->getOpcode() == ISD::BUILD_PAIR);
7080 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
7081 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
7082 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
7083 LD1->getAddressSpace() != LD2->getAddressSpace())
7085 EVT LD1VT = LD1->getValueType(0);
7087 if (ISD::isNON_EXTLoad(LD2) &&
7089 // If both are volatile this would reduce the number of volatile loads.
7090 // If one is volatile it might be ok, but play conservative and bail out.
7091 !LD1->isVolatile() &&
7092 !LD2->isVolatile() &&
7093 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
7094 unsigned Align = LD1->getAlignment();
7095 unsigned NewAlign = TLI.getDataLayout()->
7096 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
7098 if (NewAlign <= Align &&
7099 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
7100 return DAG.getLoad(VT, SDLoc(N), LD1->getChain(),
7101 LD1->getBasePtr(), LD1->getPointerInfo(),
7102 false, false, false, Align);
7108 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
7109 SDValue N0 = N->getOperand(0);
7110 EVT VT = N->getValueType(0);
7112 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
7113 // Only do this before legalize, since afterward the target may be depending
7114 // on the bitconvert.
7115 // First check to see if this is all constant.
7117 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
7119 bool isSimple = cast<BuildVectorSDNode>(N0)->isConstant();
7121 EVT DestEltVT = N->getValueType(0).getVectorElementType();
7122 assert(!DestEltVT.isVector() &&
7123 "Element type of vector ValueType must not be vector!");
7125 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
7128 // If the input is a constant, let getNode fold it.
7129 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
7130 // If we can't allow illegal operations, we need to check that this is just
7131 // a fp -> int or int -> conversion and that the resulting operation will
7133 if (!LegalOperations ||
7134 (isa<ConstantSDNode>(N0) && VT.isFloatingPoint() && !VT.isVector() &&
7135 TLI.isOperationLegal(ISD::ConstantFP, VT)) ||
7136 (isa<ConstantFPSDNode>(N0) && VT.isInteger() && !VT.isVector() &&
7137 TLI.isOperationLegal(ISD::Constant, VT)))
7138 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, N0);
7141 // (conv (conv x, t1), t2) -> (conv x, t2)
7142 if (N0.getOpcode() == ISD::BITCAST)
7143 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT,
7146 // fold (conv (load x)) -> (load (conv*)x)
7147 // If the resultant load doesn't need a higher alignment than the original!
7148 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7149 // Do not change the width of a volatile load.
7150 !cast<LoadSDNode>(N0)->isVolatile() &&
7151 // Do not remove the cast if the types differ in endian layout.
7152 TLI.hasBigEndianPartOrdering(N0.getValueType()) ==
7153 TLI.hasBigEndianPartOrdering(VT) &&
7154 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)) &&
7155 TLI.isLoadBitCastBeneficial(N0.getValueType(), VT)) {
7156 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7157 unsigned Align = TLI.getDataLayout()->
7158 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
7159 unsigned OrigAlign = LN0->getAlignment();
7161 if (Align <= OrigAlign) {
7162 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(),
7163 LN0->getBasePtr(), LN0->getPointerInfo(),
7164 LN0->isVolatile(), LN0->isNonTemporal(),
7165 LN0->isInvariant(), OrigAlign,
7167 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
7172 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
7173 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
7174 // This often reduces constant pool loads.
7175 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) ||
7176 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) &&
7177 N0.getNode()->hasOneUse() && VT.isInteger() &&
7178 !VT.isVector() && !N0.getValueType().isVector()) {
7179 SDValue NewConv = DAG.getNode(ISD::BITCAST, SDLoc(N0), VT,
7181 AddToWorklist(NewConv.getNode());
7184 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
7185 if (N0.getOpcode() == ISD::FNEG)
7186 return DAG.getNode(ISD::XOR, DL, VT,
7187 NewConv, DAG.getConstant(SignBit, DL, VT));
7188 assert(N0.getOpcode() == ISD::FABS);
7189 return DAG.getNode(ISD::AND, DL, VT,
7190 NewConv, DAG.getConstant(~SignBit, DL, VT));
7193 // fold (bitconvert (fcopysign cst, x)) ->
7194 // (or (and (bitconvert x), sign), (and cst, (not sign)))
7195 // Note that we don't handle (copysign x, cst) because this can always be
7196 // folded to an fneg or fabs.
7197 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
7198 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
7199 VT.isInteger() && !VT.isVector()) {
7200 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
7201 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
7202 if (isTypeLegal(IntXVT)) {
7203 SDValue X = DAG.getNode(ISD::BITCAST, SDLoc(N0),
7204 IntXVT, N0.getOperand(1));
7205 AddToWorklist(X.getNode());
7207 // If X has a different width than the result/lhs, sext it or truncate it.
7208 unsigned VTWidth = VT.getSizeInBits();
7209 if (OrigXWidth < VTWidth) {
7210 X = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, X);
7211 AddToWorklist(X.getNode());
7212 } else if (OrigXWidth > VTWidth) {
7213 // To get the sign bit in the right place, we have to shift it right
7214 // before truncating.
7216 X = DAG.getNode(ISD::SRL, DL,
7217 X.getValueType(), X,
7218 DAG.getConstant(OrigXWidth-VTWidth, DL,
7220 AddToWorklist(X.getNode());
7221 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);
7222 AddToWorklist(X.getNode());
7225 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
7226 X = DAG.getNode(ISD::AND, SDLoc(X), VT,
7227 X, DAG.getConstant(SignBit, SDLoc(X), VT));
7228 AddToWorklist(X.getNode());
7230 SDValue Cst = DAG.getNode(ISD::BITCAST, SDLoc(N0),
7231 VT, N0.getOperand(0));
7232 Cst = DAG.getNode(ISD::AND, SDLoc(Cst), VT,
7233 Cst, DAG.getConstant(~SignBit, SDLoc(Cst), VT));
7234 AddToWorklist(Cst.getNode());
7236 return DAG.getNode(ISD::OR, SDLoc(N), VT, X, Cst);
7240 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
7241 if (N0.getOpcode() == ISD::BUILD_PAIR) {
7242 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
7243 if (CombineLD.getNode())
7247 // Remove double bitcasts from shuffles - this is often a legacy of
7248 // XformToShuffleWithZero being used to combine bitmaskings (of
7249 // float vectors bitcast to integer vectors) into shuffles.
7250 // bitcast(shuffle(bitcast(s0),bitcast(s1))) -> shuffle(s0,s1)
7251 if (Level < AfterLegalizeDAG && TLI.isTypeLegal(VT) && VT.isVector() &&
7252 N0->getOpcode() == ISD::VECTOR_SHUFFLE &&
7253 VT.getVectorNumElements() >= N0.getValueType().getVectorNumElements() &&
7254 !(VT.getVectorNumElements() % N0.getValueType().getVectorNumElements())) {
7255 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N0);
7257 // If operands are a bitcast, peek through if it casts the original VT.
7258 // If operands are a UNDEF or constant, just bitcast back to original VT.
7259 auto PeekThroughBitcast = [&](SDValue Op) {
7260 if (Op.getOpcode() == ISD::BITCAST &&
7261 Op.getOperand(0)->getValueType(0) == VT)
7262 return SDValue(Op.getOperand(0));
7263 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) ||
7264 ISD::isBuildVectorOfConstantFPSDNodes(Op.getNode()))
7265 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
7269 SDValue SV0 = PeekThroughBitcast(N0->getOperand(0));
7270 SDValue SV1 = PeekThroughBitcast(N0->getOperand(1));
7275 VT.getVectorNumElements() / N0.getValueType().getVectorNumElements();
7276 SmallVector<int, 8> NewMask;
7277 for (int M : SVN->getMask())
7278 for (int i = 0; i != MaskScale; ++i)
7279 NewMask.push_back(M < 0 ? -1 : M * MaskScale + i);
7281 bool LegalMask = TLI.isShuffleMaskLegal(NewMask, VT);
7283 std::swap(SV0, SV1);
7284 ShuffleVectorSDNode::commuteMask(NewMask);
7285 LegalMask = TLI.isShuffleMaskLegal(NewMask, VT);
7289 return DAG.getVectorShuffle(VT, SDLoc(N), SV0, SV1, NewMask);
7295 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
7296 EVT VT = N->getValueType(0);
7297 return CombineConsecutiveLoads(N, VT);
7300 /// We know that BV is a build_vector node with Constant, ConstantFP or Undef
7301 /// operands. DstEltVT indicates the destination element value type.
7302 SDValue DAGCombiner::
7303 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
7304 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
7306 // If this is already the right type, we're done.
7307 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
7309 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
7310 unsigned DstBitSize = DstEltVT.getSizeInBits();
7312 // If this is a conversion of N elements of one type to N elements of another
7313 // type, convert each element. This handles FP<->INT cases.
7314 if (SrcBitSize == DstBitSize) {
7315 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
7316 BV->getValueType(0).getVectorNumElements());
7318 // Due to the FP element handling below calling this routine recursively,
7319 // we can end up with a scalar-to-vector node here.
7320 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
7321 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(BV), VT,
7322 DAG.getNode(ISD::BITCAST, SDLoc(BV),
7323 DstEltVT, BV->getOperand(0)));
7325 SmallVector<SDValue, 8> Ops;
7326 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
7327 SDValue Op = BV->getOperand(i);
7328 // If the vector element type is not legal, the BUILD_VECTOR operands
7329 // are promoted and implicitly truncated. Make that explicit here.
7330 if (Op.getValueType() != SrcEltVT)
7331 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(BV), SrcEltVT, Op);
7332 Ops.push_back(DAG.getNode(ISD::BITCAST, SDLoc(BV),
7334 AddToWorklist(Ops.back().getNode());
7336 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, Ops);
7339 // Otherwise, we're growing or shrinking the elements. To avoid having to
7340 // handle annoying details of growing/shrinking FP values, we convert them to
7342 if (SrcEltVT.isFloatingPoint()) {
7343 // Convert the input float vector to a int vector where the elements are the
7345 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
7346 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
7350 // Now we know the input is an integer vector. If the output is a FP type,
7351 // convert to integer first, then to FP of the right size.
7352 if (DstEltVT.isFloatingPoint()) {
7353 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
7354 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
7356 // Next, convert to FP elements of the same size.
7357 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
7362 // Okay, we know the src/dst types are both integers of differing types.
7363 // Handling growing first.
7364 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
7365 if (SrcBitSize < DstBitSize) {
7366 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
7368 SmallVector<SDValue, 8> Ops;
7369 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
7370 i += NumInputsPerOutput) {
7371 bool isLE = TLI.isLittleEndian();
7372 APInt NewBits = APInt(DstBitSize, 0);
7373 bool EltIsUndef = true;
7374 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
7375 // Shift the previously computed bits over.
7376 NewBits <<= SrcBitSize;
7377 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
7378 if (Op.getOpcode() == ISD::UNDEF) continue;
7381 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
7382 zextOrTrunc(SrcBitSize).zext(DstBitSize);
7386 Ops.push_back(DAG.getUNDEF(DstEltVT));
7388 Ops.push_back(DAG.getConstant(NewBits, DL, DstEltVT));
7391 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
7392 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
7395 // Finally, this must be the case where we are shrinking elements: each input
7396 // turns into multiple outputs.
7397 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
7398 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
7399 NumOutputsPerInput*BV->getNumOperands());
7400 SmallVector<SDValue, 8> Ops;
7402 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
7403 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
7404 Ops.append(NumOutputsPerInput, DAG.getUNDEF(DstEltVT));
7408 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
7409 getAPIntValue().zextOrTrunc(SrcBitSize);
7411 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
7412 APInt ThisVal = OpVal.trunc(DstBitSize);
7413 Ops.push_back(DAG.getConstant(ThisVal, DL, DstEltVT));
7414 OpVal = OpVal.lshr(DstBitSize);
7417 // For big endian targets, swap the order of the pieces of each element.
7418 if (TLI.isBigEndian())
7419 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
7422 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
7425 /// Try to perform FMA combining on a given FADD node.
7426 SDValue DAGCombiner::visitFADDForFMACombine(SDNode *N) {
7427 SDValue N0 = N->getOperand(0);
7428 SDValue N1 = N->getOperand(1);
7429 EVT VT = N->getValueType(0);
7432 const TargetOptions &Options = DAG.getTarget().Options;
7433 bool UnsafeFPMath = (Options.AllowFPOpFusion == FPOpFusion::Fast ||
7434 Options.UnsafeFPMath);
7436 // Floating-point multiply-add with intermediate rounding.
7437 bool HasFMAD = (LegalOperations &&
7438 TLI.isOperationLegal(ISD::FMAD, VT));
7440 // Floating-point multiply-add without intermediate rounding.
7441 bool HasFMA = ((!LegalOperations ||
7442 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) &&
7443 TLI.isFMAFasterThanFMulAndFAdd(VT) &&
7446 // No valid opcode, do not combine.
7447 if (!HasFMAD && !HasFMA)
7450 // Always prefer FMAD to FMA for precision.
7451 unsigned int PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA;
7452 bool Aggressive = TLI.enableAggressiveFMAFusion(VT);
7453 bool LookThroughFPExt = TLI.isFPExtFree(VT);
7455 // fold (fadd (fmul x, y), z) -> (fma x, y, z)
7456 if (N0.getOpcode() == ISD::FMUL &&
7457 (Aggressive || N0->hasOneUse())) {
7458 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7459 N0.getOperand(0), N0.getOperand(1), N1);
7462 // fold (fadd x, (fmul y, z)) -> (fma y, z, x)
7463 // Note: Commutes FADD operands.
7464 if (N1.getOpcode() == ISD::FMUL &&
7465 (Aggressive || N1->hasOneUse())) {
7466 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7467 N1.getOperand(0), N1.getOperand(1), N0);
7470 // Look through FP_EXTEND nodes to do more combining.
7471 if (UnsafeFPMath && LookThroughFPExt) {
7472 // fold (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z)
7473 if (N0.getOpcode() == ISD::FP_EXTEND) {
7474 SDValue N00 = N0.getOperand(0);
7475 if (N00.getOpcode() == ISD::FMUL)
7476 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7477 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7479 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7480 N00.getOperand(1)), N1);
7483 // fold (fadd x, (fpext (fmul y, z))) -> (fma (fpext y), (fpext z), x)
7484 // Note: Commutes FADD operands.
7485 if (N1.getOpcode() == ISD::FP_EXTEND) {
7486 SDValue N10 = N1.getOperand(0);
7487 if (N10.getOpcode() == ISD::FMUL)
7488 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7489 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7491 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7492 N10.getOperand(1)), N0);
7496 // More folding opportunities when target permits.
7497 if ((UnsafeFPMath || HasFMAD) && Aggressive) {
7498 // fold (fadd (fma x, y, (fmul u, v)), z) -> (fma x, y (fma u, v, z))
7499 if (N0.getOpcode() == PreferredFusedOpcode &&
7500 N0.getOperand(2).getOpcode() == ISD::FMUL) {
7501 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7502 N0.getOperand(0), N0.getOperand(1),
7503 DAG.getNode(PreferredFusedOpcode, SL, VT,
7504 N0.getOperand(2).getOperand(0),
7505 N0.getOperand(2).getOperand(1),
7509 // fold (fadd x, (fma y, z, (fmul u, v)) -> (fma y, z (fma u, v, x))
7510 if (N1->getOpcode() == PreferredFusedOpcode &&
7511 N1.getOperand(2).getOpcode() == ISD::FMUL) {
7512 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7513 N1.getOperand(0), N1.getOperand(1),
7514 DAG.getNode(PreferredFusedOpcode, SL, VT,
7515 N1.getOperand(2).getOperand(0),
7516 N1.getOperand(2).getOperand(1),
7520 if (UnsafeFPMath && LookThroughFPExt) {
7521 // fold (fadd (fma x, y, (fpext (fmul u, v))), z)
7522 // -> (fma x, y, (fma (fpext u), (fpext v), z))
7523 auto FoldFAddFMAFPExtFMul = [&] (
7524 SDValue X, SDValue Y, SDValue U, SDValue V, SDValue Z) {
7525 return DAG.getNode(PreferredFusedOpcode, SL, VT, X, Y,
7526 DAG.getNode(PreferredFusedOpcode, SL, VT,
7527 DAG.getNode(ISD::FP_EXTEND, SL, VT, U),
7528 DAG.getNode(ISD::FP_EXTEND, SL, VT, V),
7531 if (N0.getOpcode() == PreferredFusedOpcode) {
7532 SDValue N02 = N0.getOperand(2);
7533 if (N02.getOpcode() == ISD::FP_EXTEND) {
7534 SDValue N020 = N02.getOperand(0);
7535 if (N020.getOpcode() == ISD::FMUL)
7536 return FoldFAddFMAFPExtFMul(N0.getOperand(0), N0.getOperand(1),
7537 N020.getOperand(0), N020.getOperand(1),
7542 // fold (fadd (fpext (fma x, y, (fmul u, v))), z)
7543 // -> (fma (fpext x), (fpext y), (fma (fpext u), (fpext v), z))
7544 // FIXME: This turns two single-precision and one double-precision
7545 // operation into two double-precision operations, which might not be
7546 // interesting for all targets, especially GPUs.
7547 auto FoldFAddFPExtFMAFMul = [&] (
7548 SDValue X, SDValue Y, SDValue U, SDValue V, SDValue Z) {
7549 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7550 DAG.getNode(ISD::FP_EXTEND, SL, VT, X),
7551 DAG.getNode(ISD::FP_EXTEND, SL, VT, Y),
7552 DAG.getNode(PreferredFusedOpcode, SL, VT,
7553 DAG.getNode(ISD::FP_EXTEND, SL, VT, U),
7554 DAG.getNode(ISD::FP_EXTEND, SL, VT, V),
7557 if (N0.getOpcode() == ISD::FP_EXTEND) {
7558 SDValue N00 = N0.getOperand(0);
7559 if (N00.getOpcode() == PreferredFusedOpcode) {
7560 SDValue N002 = N00.getOperand(2);
7561 if (N002.getOpcode() == ISD::FMUL)
7562 return FoldFAddFPExtFMAFMul(N00.getOperand(0), N00.getOperand(1),
7563 N002.getOperand(0), N002.getOperand(1),
7568 // fold (fadd x, (fma y, z, (fpext (fmul u, v)))
7569 // -> (fma y, z, (fma (fpext u), (fpext v), x))
7570 if (N1.getOpcode() == PreferredFusedOpcode) {
7571 SDValue N12 = N1.getOperand(2);
7572 if (N12.getOpcode() == ISD::FP_EXTEND) {
7573 SDValue N120 = N12.getOperand(0);
7574 if (N120.getOpcode() == ISD::FMUL)
7575 return FoldFAddFMAFPExtFMul(N1.getOperand(0), N1.getOperand(1),
7576 N120.getOperand(0), N120.getOperand(1),
7581 // fold (fadd x, (fpext (fma y, z, (fmul u, v)))
7582 // -> (fma (fpext y), (fpext z), (fma (fpext u), (fpext v), x))
7583 // FIXME: This turns two single-precision and one double-precision
7584 // operation into two double-precision operations, which might not be
7585 // interesting for all targets, especially GPUs.
7586 if (N1.getOpcode() == ISD::FP_EXTEND) {
7587 SDValue N10 = N1.getOperand(0);
7588 if (N10.getOpcode() == PreferredFusedOpcode) {
7589 SDValue N102 = N10.getOperand(2);
7590 if (N102.getOpcode() == ISD::FMUL)
7591 return FoldFAddFPExtFMAFMul(N10.getOperand(0), N10.getOperand(1),
7592 N102.getOperand(0), N102.getOperand(1),
7602 /// Try to perform FMA combining on a given FSUB node.
7603 SDValue DAGCombiner::visitFSUBForFMACombine(SDNode *N) {
7604 SDValue N0 = N->getOperand(0);
7605 SDValue N1 = N->getOperand(1);
7606 EVT VT = N->getValueType(0);
7609 const TargetOptions &Options = DAG.getTarget().Options;
7610 bool UnsafeFPMath = (Options.AllowFPOpFusion == FPOpFusion::Fast ||
7611 Options.UnsafeFPMath);
7613 // Floating-point multiply-add with intermediate rounding.
7614 bool HasFMAD = (LegalOperations &&
7615 TLI.isOperationLegal(ISD::FMAD, VT));
7617 // Floating-point multiply-add without intermediate rounding.
7618 bool HasFMA = ((!LegalOperations ||
7619 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) &&
7620 TLI.isFMAFasterThanFMulAndFAdd(VT) &&
7623 // No valid opcode, do not combine.
7624 if (!HasFMAD && !HasFMA)
7627 // Always prefer FMAD to FMA for precision.
7628 unsigned int PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA;
7629 bool Aggressive = TLI.enableAggressiveFMAFusion(VT);
7630 bool LookThroughFPExt = TLI.isFPExtFree(VT);
7632 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
7633 if (N0.getOpcode() == ISD::FMUL &&
7634 (Aggressive || N0->hasOneUse())) {
7635 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7636 N0.getOperand(0), N0.getOperand(1),
7637 DAG.getNode(ISD::FNEG, SL, VT, N1));
7640 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
7641 // Note: Commutes FSUB operands.
7642 if (N1.getOpcode() == ISD::FMUL &&
7643 (Aggressive || N1->hasOneUse()))
7644 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7645 DAG.getNode(ISD::FNEG, SL, VT,
7647 N1.getOperand(1), N0);
7649 // fold (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
7650 if (N0.getOpcode() == ISD::FNEG &&
7651 N0.getOperand(0).getOpcode() == ISD::FMUL &&
7652 (Aggressive || (N0->hasOneUse() && N0.getOperand(0).hasOneUse()))) {
7653 SDValue N00 = N0.getOperand(0).getOperand(0);
7654 SDValue N01 = N0.getOperand(0).getOperand(1);
7655 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7656 DAG.getNode(ISD::FNEG, SL, VT, N00), N01,
7657 DAG.getNode(ISD::FNEG, SL, VT, N1));
7660 // Look through FP_EXTEND nodes to do more combining.
7661 if (UnsafeFPMath && LookThroughFPExt) {
7662 // fold (fsub (fpext (fmul x, y)), z)
7663 // -> (fma (fpext x), (fpext y), (fneg z))
7664 if (N0.getOpcode() == ISD::FP_EXTEND) {
7665 SDValue N00 = N0.getOperand(0);
7666 if (N00.getOpcode() == ISD::FMUL)
7667 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7668 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7670 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7672 DAG.getNode(ISD::FNEG, SL, VT, N1));
7675 // fold (fsub x, (fpext (fmul y, z)))
7676 // -> (fma (fneg (fpext y)), (fpext z), x)
7677 // Note: Commutes FSUB operands.
7678 if (N1.getOpcode() == ISD::FP_EXTEND) {
7679 SDValue N10 = N1.getOperand(0);
7680 if (N10.getOpcode() == ISD::FMUL)
7681 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7682 DAG.getNode(ISD::FNEG, SL, VT,
7683 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7684 N10.getOperand(0))),
7685 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7690 // fold (fsub (fpext (fneg (fmul, x, y))), z)
7691 // -> (fneg (fma (fpext x), (fpext y), z))
7692 // Note: This could be removed with appropriate canonicalization of the
7693 // input expression into (fneg (fadd (fpext (fmul, x, y)), z). However, the
7694 // orthogonal flags -fp-contract=fast and -enable-unsafe-fp-math prevent
7695 // from implementing the canonicalization in visitFSUB.
7696 if (N0.getOpcode() == ISD::FP_EXTEND) {
7697 SDValue N00 = N0.getOperand(0);
7698 if (N00.getOpcode() == ISD::FNEG) {
7699 SDValue N000 = N00.getOperand(0);
7700 if (N000.getOpcode() == ISD::FMUL) {
7701 return DAG.getNode(ISD::FNEG, SL, VT,
7702 DAG.getNode(PreferredFusedOpcode, SL, VT,
7703 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7704 N000.getOperand(0)),
7705 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7706 N000.getOperand(1)),
7712 // fold (fsub (fneg (fpext (fmul, x, y))), z)
7713 // -> (fneg (fma (fpext x)), (fpext y), z)
7714 // Note: This could be removed with appropriate canonicalization of the
7715 // input expression into (fneg (fadd (fpext (fmul, x, y)), z). However, the
7716 // orthogonal flags -fp-contract=fast and -enable-unsafe-fp-math prevent
7717 // from implementing the canonicalization in visitFSUB.
7718 if (N0.getOpcode() == ISD::FNEG) {
7719 SDValue N00 = N0.getOperand(0);
7720 if (N00.getOpcode() == ISD::FP_EXTEND) {
7721 SDValue N000 = N00.getOperand(0);
7722 if (N000.getOpcode() == ISD::FMUL) {
7723 return DAG.getNode(ISD::FNEG, SL, VT,
7724 DAG.getNode(PreferredFusedOpcode, SL, VT,
7725 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7726 N000.getOperand(0)),
7727 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7728 N000.getOperand(1)),
7736 // More folding opportunities when target permits.
7737 if ((UnsafeFPMath || HasFMAD) && Aggressive) {
7738 // fold (fsub (fma x, y, (fmul u, v)), z)
7739 // -> (fma x, y (fma u, v, (fneg z)))
7740 if (N0.getOpcode() == PreferredFusedOpcode &&
7741 N0.getOperand(2).getOpcode() == ISD::FMUL) {
7742 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7743 N0.getOperand(0), N0.getOperand(1),
7744 DAG.getNode(PreferredFusedOpcode, SL, VT,
7745 N0.getOperand(2).getOperand(0),
7746 N0.getOperand(2).getOperand(1),
7747 DAG.getNode(ISD::FNEG, SL, VT,
7751 // fold (fsub x, (fma y, z, (fmul u, v)))
7752 // -> (fma (fneg y), z, (fma (fneg u), v, x))
7753 if (N1.getOpcode() == PreferredFusedOpcode &&
7754 N1.getOperand(2).getOpcode() == ISD::FMUL) {
7755 SDValue N20 = N1.getOperand(2).getOperand(0);
7756 SDValue N21 = N1.getOperand(2).getOperand(1);
7757 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7758 DAG.getNode(ISD::FNEG, SL, VT,
7761 DAG.getNode(PreferredFusedOpcode, SL, VT,
7762 DAG.getNode(ISD::FNEG, SL, VT, N20),
7767 if (UnsafeFPMath && LookThroughFPExt) {
7768 // fold (fsub (fma x, y, (fpext (fmul u, v))), z)
7769 // -> (fma x, y (fma (fpext u), (fpext v), (fneg z)))
7770 if (N0.getOpcode() == PreferredFusedOpcode) {
7771 SDValue N02 = N0.getOperand(2);
7772 if (N02.getOpcode() == ISD::FP_EXTEND) {
7773 SDValue N020 = N02.getOperand(0);
7774 if (N020.getOpcode() == ISD::FMUL)
7775 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7776 N0.getOperand(0), N0.getOperand(1),
7777 DAG.getNode(PreferredFusedOpcode, SL, VT,
7778 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7779 N020.getOperand(0)),
7780 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7781 N020.getOperand(1)),
7782 DAG.getNode(ISD::FNEG, SL, VT,
7787 // fold (fsub (fpext (fma x, y, (fmul u, v))), z)
7788 // -> (fma (fpext x), (fpext y),
7789 // (fma (fpext u), (fpext v), (fneg z)))
7790 // FIXME: This turns two single-precision and one double-precision
7791 // operation into two double-precision operations, which might not be
7792 // interesting for all targets, especially GPUs.
7793 if (N0.getOpcode() == ISD::FP_EXTEND) {
7794 SDValue N00 = N0.getOperand(0);
7795 if (N00.getOpcode() == PreferredFusedOpcode) {
7796 SDValue N002 = N00.getOperand(2);
7797 if (N002.getOpcode() == ISD::FMUL)
7798 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7799 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7801 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7803 DAG.getNode(PreferredFusedOpcode, SL, VT,
7804 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7805 N002.getOperand(0)),
7806 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7807 N002.getOperand(1)),
7808 DAG.getNode(ISD::FNEG, SL, VT,
7813 // fold (fsub x, (fma y, z, (fpext (fmul u, v))))
7814 // -> (fma (fneg y), z, (fma (fneg (fpext u)), (fpext v), x))
7815 if (N1.getOpcode() == PreferredFusedOpcode &&
7816 N1.getOperand(2).getOpcode() == ISD::FP_EXTEND) {
7817 SDValue N120 = N1.getOperand(2).getOperand(0);
7818 if (N120.getOpcode() == ISD::FMUL) {
7819 SDValue N1200 = N120.getOperand(0);
7820 SDValue N1201 = N120.getOperand(1);
7821 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7822 DAG.getNode(ISD::FNEG, SL, VT, N1.getOperand(0)),
7824 DAG.getNode(PreferredFusedOpcode, SL, VT,
7825 DAG.getNode(ISD::FNEG, SL, VT,
7826 DAG.getNode(ISD::FP_EXTEND, SL,
7828 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7834 // fold (fsub x, (fpext (fma y, z, (fmul u, v))))
7835 // -> (fma (fneg (fpext y)), (fpext z),
7836 // (fma (fneg (fpext u)), (fpext v), x))
7837 // FIXME: This turns two single-precision and one double-precision
7838 // operation into two double-precision operations, which might not be
7839 // interesting for all targets, especially GPUs.
7840 if (N1.getOpcode() == ISD::FP_EXTEND &&
7841 N1.getOperand(0).getOpcode() == PreferredFusedOpcode) {
7842 SDValue N100 = N1.getOperand(0).getOperand(0);
7843 SDValue N101 = N1.getOperand(0).getOperand(1);
7844 SDValue N102 = N1.getOperand(0).getOperand(2);
7845 if (N102.getOpcode() == ISD::FMUL) {
7846 SDValue N1020 = N102.getOperand(0);
7847 SDValue N1021 = N102.getOperand(1);
7848 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7849 DAG.getNode(ISD::FNEG, SL, VT,
7850 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7852 DAG.getNode(ISD::FP_EXTEND, SL, VT, N101),
7853 DAG.getNode(PreferredFusedOpcode, SL, VT,
7854 DAG.getNode(ISD::FNEG, SL, VT,
7855 DAG.getNode(ISD::FP_EXTEND, SL,
7857 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7868 SDValue DAGCombiner::visitFADD(SDNode *N) {
7869 SDValue N0 = N->getOperand(0);
7870 SDValue N1 = N->getOperand(1);
7871 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7872 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
7873 EVT VT = N->getValueType(0);
7875 const TargetOptions &Options = DAG.getTarget().Options;
7879 if (SDValue FoldedVOp = SimplifyVBinOp(N))
7882 // fold (fadd c1, c2) -> c1 + c2
7884 return DAG.getNode(ISD::FADD, DL, VT, N0, N1);
7886 // canonicalize constant to RHS
7887 if (N0CFP && !N1CFP)
7888 return DAG.getNode(ISD::FADD, DL, VT, N1, N0);
7890 // fold (fadd A, (fneg B)) -> (fsub A, B)
7891 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
7892 isNegatibleForFree(N1, LegalOperations, TLI, &Options) == 2)
7893 return DAG.getNode(ISD::FSUB, DL, VT, N0,
7894 GetNegatedExpression(N1, DAG, LegalOperations));
7896 // fold (fadd (fneg A), B) -> (fsub B, A)
7897 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
7898 isNegatibleForFree(N0, LegalOperations, TLI, &Options) == 2)
7899 return DAG.getNode(ISD::FSUB, DL, VT, N1,
7900 GetNegatedExpression(N0, DAG, LegalOperations));
7902 // If 'unsafe math' is enabled, fold lots of things.
7903 if (Options.UnsafeFPMath) {
7904 // No FP constant should be created after legalization as Instruction
7905 // Selection pass has a hard time dealing with FP constants.
7906 bool AllowNewConst = (Level < AfterLegalizeDAG);
7908 // fold (fadd A, 0) -> A
7909 if (N1CFP && N1CFP->isZero())
7912 // fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
7913 if (N1CFP && N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
7914 isa<ConstantFPSDNode>(N0.getOperand(1)))
7915 return DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(0),
7916 DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1), N1));
7918 // If allowed, fold (fadd (fneg x), x) -> 0.0
7919 if (AllowNewConst && N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1)
7920 return DAG.getConstantFP(0.0, DL, VT);
7922 // If allowed, fold (fadd x, (fneg x)) -> 0.0
7923 if (AllowNewConst && N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0)
7924 return DAG.getConstantFP(0.0, DL, VT);
7926 // We can fold chains of FADD's of the same value into multiplications.
7927 // This transform is not safe in general because we are reducing the number
7928 // of rounding steps.
7929 if (TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && !N0CFP && !N1CFP) {
7930 if (N0.getOpcode() == ISD::FMUL) {
7931 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
7932 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
7934 // (fadd (fmul x, c), x) -> (fmul x, c+1)
7935 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) {
7936 SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, SDValue(CFP01, 0),
7937 DAG.getConstantFP(1.0, DL, VT));
7938 return DAG.getNode(ISD::FMUL, DL, VT, N1, NewCFP);
7941 // (fadd (fmul x, c), (fadd x, x)) -> (fmul x, c+2)
7942 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD &&
7943 N1.getOperand(0) == N1.getOperand(1) &&
7944 N0.getOperand(0) == N1.getOperand(0)) {
7945 SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, SDValue(CFP01, 0),
7946 DAG.getConstantFP(2.0, DL, VT));
7947 return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), NewCFP);
7951 if (N1.getOpcode() == ISD::FMUL) {
7952 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
7953 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1));
7955 // (fadd x, (fmul x, c)) -> (fmul x, c+1)
7956 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) {
7957 SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, SDValue(CFP11, 0),
7958 DAG.getConstantFP(1.0, DL, VT));
7959 return DAG.getNode(ISD::FMUL, DL, VT, N0, NewCFP);
7962 // (fadd (fadd x, x), (fmul x, c)) -> (fmul x, c+2)
7963 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD &&
7964 N0.getOperand(0) == N0.getOperand(1) &&
7965 N1.getOperand(0) == N0.getOperand(0)) {
7966 SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, SDValue(CFP11, 0),
7967 DAG.getConstantFP(2.0, DL, VT));
7968 return DAG.getNode(ISD::FMUL, DL, VT, N1.getOperand(0), NewCFP);
7972 if (N0.getOpcode() == ISD::FADD && AllowNewConst) {
7973 ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
7974 // (fadd (fadd x, x), x) -> (fmul x, 3.0)
7975 if (!CFP && N0.getOperand(0) == N0.getOperand(1) &&
7976 (N0.getOperand(0) == N1)) {
7977 return DAG.getNode(ISD::FMUL, DL, VT,
7978 N1, DAG.getConstantFP(3.0, DL, VT));
7982 if (N1.getOpcode() == ISD::FADD && AllowNewConst) {
7983 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
7984 // (fadd x, (fadd x, x)) -> (fmul x, 3.0)
7985 if (!CFP10 && N1.getOperand(0) == N1.getOperand(1) &&
7986 N1.getOperand(0) == N0) {
7987 return DAG.getNode(ISD::FMUL, DL, VT,
7988 N0, DAG.getConstantFP(3.0, DL, VT));
7992 // (fadd (fadd x, x), (fadd x, x)) -> (fmul x, 4.0)
7993 if (AllowNewConst &&
7994 N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
7995 N0.getOperand(0) == N0.getOperand(1) &&
7996 N1.getOperand(0) == N1.getOperand(1) &&
7997 N0.getOperand(0) == N1.getOperand(0)) {
7998 return DAG.getNode(ISD::FMUL, DL, VT,
7999 N0.getOperand(0), DAG.getConstantFP(4.0, DL, VT));
8002 } // enable-unsafe-fp-math
8004 // FADD -> FMA combines:
8005 SDValue Fused = visitFADDForFMACombine(N);
8007 AddToWorklist(Fused.getNode());
8014 SDValue DAGCombiner::visitFSUB(SDNode *N) {
8015 SDValue N0 = N->getOperand(0);
8016 SDValue N1 = N->getOperand(1);
8017 ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0);
8018 ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1);
8019 EVT VT = N->getValueType(0);
8021 const TargetOptions &Options = DAG.getTarget().Options;
8025 if (SDValue FoldedVOp = SimplifyVBinOp(N))
8028 // fold (fsub c1, c2) -> c1-c2
8030 return DAG.getNode(ISD::FSUB, dl, VT, N0, N1);
8032 // fold (fsub A, (fneg B)) -> (fadd A, B)
8033 if (isNegatibleForFree(N1, LegalOperations, TLI, &Options))
8034 return DAG.getNode(ISD::FADD, dl, VT, N0,
8035 GetNegatedExpression(N1, DAG, LegalOperations));
8037 // If 'unsafe math' is enabled, fold lots of things.
8038 if (Options.UnsafeFPMath) {
8040 if (N1CFP && N1CFP->isZero())
8043 // (fsub 0, B) -> -B
8044 if (N0CFP && N0CFP->isZero()) {
8045 if (isNegatibleForFree(N1, LegalOperations, TLI, &Options))
8046 return GetNegatedExpression(N1, DAG, LegalOperations);
8047 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
8048 return DAG.getNode(ISD::FNEG, dl, VT, N1);
8051 // (fsub x, x) -> 0.0
8053 return DAG.getConstantFP(0.0f, dl, VT);
8055 // (fsub x, (fadd x, y)) -> (fneg y)
8056 // (fsub x, (fadd y, x)) -> (fneg y)
8057 if (N1.getOpcode() == ISD::FADD) {
8058 SDValue N10 = N1->getOperand(0);
8059 SDValue N11 = N1->getOperand(1);
8061 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, &Options))
8062 return GetNegatedExpression(N11, DAG, LegalOperations);
8064 if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, &Options))
8065 return GetNegatedExpression(N10, DAG, LegalOperations);
8069 // FSUB -> FMA combines:
8070 SDValue Fused = visitFSUBForFMACombine(N);
8072 AddToWorklist(Fused.getNode());
8079 SDValue DAGCombiner::visitFMUL(SDNode *N) {
8080 SDValue N0 = N->getOperand(0);
8081 SDValue N1 = N->getOperand(1);
8082 ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0);
8083 ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1);
8084 EVT VT = N->getValueType(0);
8086 const TargetOptions &Options = DAG.getTarget().Options;
8089 if (VT.isVector()) {
8090 // This just handles C1 * C2 for vectors. Other vector folds are below.
8091 if (SDValue FoldedVOp = SimplifyVBinOp(N))
8095 // fold (fmul c1, c2) -> c1*c2
8097 return DAG.getNode(ISD::FMUL, DL, VT, N0, N1);
8099 // canonicalize constant to RHS
8100 if (isConstantFPBuildVectorOrConstantFP(N0) &&
8101 !isConstantFPBuildVectorOrConstantFP(N1))
8102 return DAG.getNode(ISD::FMUL, DL, VT, N1, N0);
8104 // fold (fmul A, 1.0) -> A
8105 if (N1CFP && N1CFP->isExactlyValue(1.0))
8108 if (Options.UnsafeFPMath) {
8109 // fold (fmul A, 0) -> 0
8110 if (N1CFP && N1CFP->isZero())
8113 // fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
8114 if (N0.getOpcode() == ISD::FMUL) {
8115 // Fold scalars or any vector constants (not just splats).
8116 // This fold is done in general by InstCombine, but extra fmul insts
8117 // may have been generated during lowering.
8118 SDValue N00 = N0.getOperand(0);
8119 SDValue N01 = N0.getOperand(1);
8120 auto *BV1 = dyn_cast<BuildVectorSDNode>(N1);
8121 auto *BV00 = dyn_cast<BuildVectorSDNode>(N00);
8122 auto *BV01 = dyn_cast<BuildVectorSDNode>(N01);
8124 // Check 1: Make sure that the first operand of the inner multiply is NOT
8125 // a constant. Otherwise, we may induce infinite looping.
8126 if (!(isConstOrConstSplatFP(N00) || (BV00 && BV00->isConstant()))) {
8127 // Check 2: Make sure that the second operand of the inner multiply and
8128 // the second operand of the outer multiply are constants.
8129 if ((N1CFP && isConstOrConstSplatFP(N01)) ||
8130 (BV1 && BV01 && BV1->isConstant() && BV01->isConstant())) {
8131 SDValue MulConsts = DAG.getNode(ISD::FMUL, DL, VT, N01, N1);
8132 return DAG.getNode(ISD::FMUL, DL, VT, N00, MulConsts);
8137 // fold (fmul (fadd x, x), c) -> (fmul x, (fmul 2.0, c))
8138 // Undo the fmul 2.0, x -> fadd x, x transformation, since if it occurs
8139 // during an early run of DAGCombiner can prevent folding with fmuls
8140 // inserted during lowering.
8141 if (N0.getOpcode() == ISD::FADD && N0.getOperand(0) == N0.getOperand(1)) {
8142 const SDValue Two = DAG.getConstantFP(2.0, DL, VT);
8143 SDValue MulConsts = DAG.getNode(ISD::FMUL, DL, VT, Two, N1);
8144 return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), MulConsts);
8148 // fold (fmul X, 2.0) -> (fadd X, X)
8149 if (N1CFP && N1CFP->isExactlyValue(+2.0))
8150 return DAG.getNode(ISD::FADD, DL, VT, N0, N0);
8152 // fold (fmul X, -1.0) -> (fneg X)
8153 if (N1CFP && N1CFP->isExactlyValue(-1.0))
8154 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
8155 return DAG.getNode(ISD::FNEG, DL, VT, N0);
8157 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
8158 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, &Options)) {
8159 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, &Options)) {
8160 // Both can be negated for free, check to see if at least one is cheaper
8162 if (LHSNeg == 2 || RHSNeg == 2)
8163 return DAG.getNode(ISD::FMUL, DL, VT,
8164 GetNegatedExpression(N0, DAG, LegalOperations),
8165 GetNegatedExpression(N1, DAG, LegalOperations));
8172 SDValue DAGCombiner::visitFMA(SDNode *N) {
8173 SDValue N0 = N->getOperand(0);
8174 SDValue N1 = N->getOperand(1);
8175 SDValue N2 = N->getOperand(2);
8176 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8177 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
8178 EVT VT = N->getValueType(0);
8180 const TargetOptions &Options = DAG.getTarget().Options;
8182 // Constant fold FMA.
8183 if (isa<ConstantFPSDNode>(N0) &&
8184 isa<ConstantFPSDNode>(N1) &&
8185 isa<ConstantFPSDNode>(N2)) {
8186 return DAG.getNode(ISD::FMA, dl, VT, N0, N1, N2);
8189 if (Options.UnsafeFPMath) {
8190 if (N0CFP && N0CFP->isZero())
8192 if (N1CFP && N1CFP->isZero())
8195 if (N0CFP && N0CFP->isExactlyValue(1.0))
8196 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N2);
8197 if (N1CFP && N1CFP->isExactlyValue(1.0))
8198 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N2);
8200 // Canonicalize (fma c, x, y) -> (fma x, c, y)
8201 if (N0CFP && !N1CFP)
8202 return DAG.getNode(ISD::FMA, SDLoc(N), VT, N1, N0, N2);
8204 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2)
8205 if (Options.UnsafeFPMath && N1CFP &&
8206 N2.getOpcode() == ISD::FMUL &&
8207 N0 == N2.getOperand(0) &&
8208 N2.getOperand(1).getOpcode() == ISD::ConstantFP) {
8209 return DAG.getNode(ISD::FMUL, dl, VT, N0,
8210 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1)));
8214 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y)
8215 if (Options.UnsafeFPMath &&
8216 N0.getOpcode() == ISD::FMUL && N1CFP &&
8217 N0.getOperand(1).getOpcode() == ISD::ConstantFP) {
8218 return DAG.getNode(ISD::FMA, dl, VT,
8220 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)),
8224 // (fma x, 1, y) -> (fadd x, y)
8225 // (fma x, -1, y) -> (fadd (fneg x), y)
8227 if (N1CFP->isExactlyValue(1.0))
8228 return DAG.getNode(ISD::FADD, dl, VT, N0, N2);
8230 if (N1CFP->isExactlyValue(-1.0) &&
8231 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) {
8232 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0);
8233 AddToWorklist(RHSNeg.getNode());
8234 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg);
8238 // (fma x, c, x) -> (fmul x, (c+1))
8239 if (Options.UnsafeFPMath && N1CFP && N0 == N2)
8240 return DAG.getNode(ISD::FMUL, dl, VT, N0,
8241 DAG.getNode(ISD::FADD, dl, VT,
8242 N1, DAG.getConstantFP(1.0, dl, VT)));
8244 // (fma x, c, (fneg x)) -> (fmul x, (c-1))
8245 if (Options.UnsafeFPMath && N1CFP &&
8246 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0)
8247 return DAG.getNode(ISD::FMUL, dl, VT, N0,
8248 DAG.getNode(ISD::FADD, dl, VT,
8249 N1, DAG.getConstantFP(-1.0, dl, VT)));
8255 SDValue DAGCombiner::visitFDIV(SDNode *N) {
8256 SDValue N0 = N->getOperand(0);
8257 SDValue N1 = N->getOperand(1);
8258 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8259 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
8260 EVT VT = N->getValueType(0);
8262 const TargetOptions &Options = DAG.getTarget().Options;
8266 if (SDValue FoldedVOp = SimplifyVBinOp(N))
8269 // fold (fdiv c1, c2) -> c1/c2
8271 return DAG.getNode(ISD::FDIV, SDLoc(N), VT, N0, N1);
8273 if (Options.UnsafeFPMath) {
8274 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable.
8276 // Compute the reciprocal 1.0 / c2.
8277 APFloat N1APF = N1CFP->getValueAPF();
8278 APFloat Recip(N1APF.getSemantics(), 1); // 1.0
8279 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven);
8280 // Only do the transform if the reciprocal is a legal fp immediate that
8281 // isn't too nasty (eg NaN, denormal, ...).
8282 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty
8283 (!LegalOperations ||
8284 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM
8285 // backend)... we should handle this gracefully after Legalize.
8286 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) ||
8287 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) ||
8288 TLI.isFPImmLegal(Recip, VT)))
8289 return DAG.getNode(ISD::FMUL, DL, VT, N0,
8290 DAG.getConstantFP(Recip, DL, VT));
8293 // If this FDIV is part of a reciprocal square root, it may be folded
8294 // into a target-specific square root estimate instruction.
8295 if (N1.getOpcode() == ISD::FSQRT) {
8296 if (SDValue RV = BuildRsqrtEstimate(N1.getOperand(0))) {
8297 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
8299 } else if (N1.getOpcode() == ISD::FP_EXTEND &&
8300 N1.getOperand(0).getOpcode() == ISD::FSQRT) {
8301 if (SDValue RV = BuildRsqrtEstimate(N1.getOperand(0).getOperand(0))) {
8302 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N1), VT, RV);
8303 AddToWorklist(RV.getNode());
8304 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
8306 } else if (N1.getOpcode() == ISD::FP_ROUND &&
8307 N1.getOperand(0).getOpcode() == ISD::FSQRT) {
8308 if (SDValue RV = BuildRsqrtEstimate(N1.getOperand(0).getOperand(0))) {
8309 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N1), VT, RV, N1.getOperand(1));
8310 AddToWorklist(RV.getNode());
8311 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
8313 } else if (N1.getOpcode() == ISD::FMUL) {
8314 // Look through an FMUL. Even though this won't remove the FDIV directly,
8315 // it's still worthwhile to get rid of the FSQRT if possible.
8318 if (N1.getOperand(0).getOpcode() == ISD::FSQRT) {
8319 SqrtOp = N1.getOperand(0);
8320 OtherOp = N1.getOperand(1);
8321 } else if (N1.getOperand(1).getOpcode() == ISD::FSQRT) {
8322 SqrtOp = N1.getOperand(1);
8323 OtherOp = N1.getOperand(0);
8325 if (SqrtOp.getNode()) {
8326 // We found a FSQRT, so try to make this fold:
8327 // x / (y * sqrt(z)) -> x * (rsqrt(z) / y)
8328 if (SDValue RV = BuildRsqrtEstimate(SqrtOp.getOperand(0))) {
8329 RV = DAG.getNode(ISD::FDIV, SDLoc(N1), VT, RV, OtherOp);
8330 AddToWorklist(RV.getNode());
8331 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
8336 // Fold into a reciprocal estimate and multiply instead of a real divide.
8337 if (SDValue RV = BuildReciprocalEstimate(N1)) {
8338 AddToWorklist(RV.getNode());
8339 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
8343 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
8344 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, &Options)) {
8345 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, &Options)) {
8346 // Both can be negated for free, check to see if at least one is cheaper
8348 if (LHSNeg == 2 || RHSNeg == 2)
8349 return DAG.getNode(ISD::FDIV, SDLoc(N), VT,
8350 GetNegatedExpression(N0, DAG, LegalOperations),
8351 GetNegatedExpression(N1, DAG, LegalOperations));
8355 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
8357 // E.g., (a / D; b / D;) -> (recip = 1.0 / D; a * recip; b * recip)
8358 // Notice that this is not always beneficial. One reason is different target
8359 // may have different costs for FDIV and FMUL, so sometimes the cost of two
8360 // FDIVs may be lower than the cost of one FDIV and two FMULs. Another reason
8361 // is the critical path is increased from "one FDIV" to "one FDIV + one FMUL".
8362 if (Options.UnsafeFPMath) {
8363 // Skip if current node is a reciprocal.
8364 if (N0CFP && N0CFP->isExactlyValue(1.0))
8367 SmallVector<SDNode *, 4> Users;
8368 // Find all FDIV users of the same divisor.
8369 for (auto *U : N1->uses()) {
8370 if (U->getOpcode() == ISD::FDIV && U->getOperand(1) == N1)
8374 if (TLI.combineRepeatedFPDivisors(Users.size())) {
8375 SDValue FPOne = DAG.getConstantFP(1.0, DL, VT);
8376 SDValue Reciprocal = DAG.getNode(ISD::FDIV, DL, VT, FPOne, N1);
8378 // Dividend / Divisor -> Dividend * Reciprocal
8379 for (auto *U : Users) {
8380 SDValue Dividend = U->getOperand(0);
8381 if (Dividend != FPOne) {
8382 SDValue NewNode = DAG.getNode(ISD::FMUL, SDLoc(U), VT, Dividend,
8384 DAG.ReplaceAllUsesWith(U, NewNode.getNode());
8394 SDValue DAGCombiner::visitFREM(SDNode *N) {
8395 SDValue N0 = N->getOperand(0);
8396 SDValue N1 = N->getOperand(1);
8397 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8398 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
8399 EVT VT = N->getValueType(0);
8401 // fold (frem c1, c2) -> fmod(c1,c2)
8403 return DAG.getNode(ISD::FREM, SDLoc(N), VT, N0, N1);
8408 SDValue DAGCombiner::visitFSQRT(SDNode *N) {
8409 if (DAG.getTarget().Options.UnsafeFPMath &&
8410 !TLI.isFsqrtCheap()) {
8411 // Compute this as X * (1/sqrt(X)) = X * (X ** -0.5)
8412 if (SDValue RV = BuildRsqrtEstimate(N->getOperand(0))) {
8413 EVT VT = RV.getValueType();
8415 RV = DAG.getNode(ISD::FMUL, DL, VT, N->getOperand(0), RV);
8416 AddToWorklist(RV.getNode());
8418 // Unfortunately, RV is now NaN if the input was exactly 0.
8419 // Select out this case and force the answer to 0.
8420 SDValue Zero = DAG.getConstantFP(0.0, DL, VT);
8422 DAG.getSetCC(DL, TLI.getSetCCResultType(*DAG.getContext(), VT),
8423 N->getOperand(0), Zero, ISD::SETEQ);
8424 AddToWorklist(ZeroCmp.getNode());
8425 AddToWorklist(RV.getNode());
8427 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT,
8428 DL, VT, ZeroCmp, Zero, RV);
8435 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
8436 SDValue N0 = N->getOperand(0);
8437 SDValue N1 = N->getOperand(1);
8438 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8439 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
8440 EVT VT = N->getValueType(0);
8442 if (N0CFP && N1CFP) // Constant fold
8443 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1);
8446 const APFloat& V = N1CFP->getValueAPF();
8447 // copysign(x, c1) -> fabs(x) iff ispos(c1)
8448 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
8449 if (!V.isNegative()) {
8450 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
8451 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
8453 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
8454 return DAG.getNode(ISD::FNEG, SDLoc(N), VT,
8455 DAG.getNode(ISD::FABS, SDLoc(N0), VT, N0));
8459 // copysign(fabs(x), y) -> copysign(x, y)
8460 // copysign(fneg(x), y) -> copysign(x, y)
8461 // copysign(copysign(x,z), y) -> copysign(x, y)
8462 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
8463 N0.getOpcode() == ISD::FCOPYSIGN)
8464 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
8465 N0.getOperand(0), N1);
8467 // copysign(x, abs(y)) -> abs(x)
8468 if (N1.getOpcode() == ISD::FABS)
8469 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
8471 // copysign(x, copysign(y,z)) -> copysign(x, z)
8472 if (N1.getOpcode() == ISD::FCOPYSIGN)
8473 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
8474 N0, N1.getOperand(1));
8476 // copysign(x, fp_extend(y)) -> copysign(x, y)
8477 // copysign(x, fp_round(y)) -> copysign(x, y)
8478 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
8479 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
8480 N0, N1.getOperand(0));
8485 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
8486 SDValue N0 = N->getOperand(0);
8487 EVT VT = N->getValueType(0);
8488 EVT OpVT = N0.getValueType();
8490 // fold (sint_to_fp c1) -> c1fp
8491 if (isConstantIntBuildVectorOrConstantInt(N0) &&
8492 // ...but only if the target supports immediate floating-point values
8493 (!LegalOperations ||
8494 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
8495 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
8497 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
8498 // but UINT_TO_FP is legal on this target, try to convert.
8499 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
8500 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
8501 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
8502 if (DAG.SignBitIsZero(N0))
8503 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
8506 // The next optimizations are desirable only if SELECT_CC can be lowered.
8507 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) {
8508 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
8509 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
8511 (!LegalOperations ||
8512 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
8515 { N0.getOperand(0), N0.getOperand(1),
8516 DAG.getConstantFP(-1.0, DL, VT), DAG.getConstantFP(0.0, DL, VT),
8518 return DAG.getNode(ISD::SELECT_CC, DL, VT, Ops);
8521 // fold (sint_to_fp (zext (setcc x, y, cc))) ->
8522 // (select_cc x, y, 1.0, 0.0,, cc)
8523 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
8524 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
8525 (!LegalOperations ||
8526 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
8529 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1),
8530 DAG.getConstantFP(1.0, DL, VT), DAG.getConstantFP(0.0, DL, VT),
8531 N0.getOperand(0).getOperand(2) };
8532 return DAG.getNode(ISD::SELECT_CC, DL, VT, Ops);
8539 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
8540 SDValue N0 = N->getOperand(0);
8541 EVT VT = N->getValueType(0);
8542 EVT OpVT = N0.getValueType();
8544 // fold (uint_to_fp c1) -> c1fp
8545 if (isConstantIntBuildVectorOrConstantInt(N0) &&
8546 // ...but only if the target supports immediate floating-point values
8547 (!LegalOperations ||
8548 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
8549 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
8551 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
8552 // but SINT_TO_FP is legal on this target, try to convert.
8553 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
8554 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
8555 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
8556 if (DAG.SignBitIsZero(N0))
8557 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
8560 // The next optimizations are desirable only if SELECT_CC can be lowered.
8561 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) {
8562 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
8564 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
8565 (!LegalOperations ||
8566 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
8569 { N0.getOperand(0), N0.getOperand(1),
8570 DAG.getConstantFP(1.0, DL, VT), DAG.getConstantFP(0.0, DL, VT),
8572 return DAG.getNode(ISD::SELECT_CC, DL, VT, Ops);
8579 // Fold (fp_to_{s/u}int ({s/u}int_to_fpx)) -> zext x, sext x, trunc x, or x
8580 static SDValue FoldIntToFPToInt(SDNode *N, SelectionDAG &DAG) {
8581 SDValue N0 = N->getOperand(0);
8582 EVT VT = N->getValueType(0);
8584 if (N0.getOpcode() != ISD::UINT_TO_FP && N0.getOpcode() != ISD::SINT_TO_FP)
8587 SDValue Src = N0.getOperand(0);
8588 EVT SrcVT = Src.getValueType();
8589 bool IsInputSigned = N0.getOpcode() == ISD::SINT_TO_FP;
8590 bool IsOutputSigned = N->getOpcode() == ISD::FP_TO_SINT;
8592 // We can safely assume the conversion won't overflow the output range,
8593 // because (for example) (uint8_t)18293.f is undefined behavior.
8595 // Since we can assume the conversion won't overflow, our decision as to
8596 // whether the input will fit in the float should depend on the minimum
8597 // of the input range and output range.
8599 // This means this is also safe for a signed input and unsigned output, since
8600 // a negative input would lead to undefined behavior.
8601 unsigned InputSize = (int)SrcVT.getScalarSizeInBits() - IsInputSigned;
8602 unsigned OutputSize = (int)VT.getScalarSizeInBits() - IsOutputSigned;
8603 unsigned ActualSize = std::min(InputSize, OutputSize);
8604 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(N0.getValueType());
8606 // We can only fold away the float conversion if the input range can be
8607 // represented exactly in the float range.
8608 if (APFloat::semanticsPrecision(sem) >= ActualSize) {
8609 if (VT.getScalarSizeInBits() > SrcVT.getScalarSizeInBits()) {
8610 unsigned ExtOp = IsInputSigned && IsOutputSigned ? ISD::SIGN_EXTEND
8612 return DAG.getNode(ExtOp, SDLoc(N), VT, Src);
8614 if (VT.getScalarSizeInBits() < SrcVT.getScalarSizeInBits())
8615 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Src);
8618 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Src);
8623 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
8624 SDValue N0 = N->getOperand(0);
8625 EVT VT = N->getValueType(0);
8627 // fold (fp_to_sint c1fp) -> c1
8628 if (isConstantFPBuildVectorOrConstantFP(N0))
8629 return DAG.getNode(ISD::FP_TO_SINT, SDLoc(N), VT, N0);
8631 return FoldIntToFPToInt(N, DAG);
8634 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
8635 SDValue N0 = N->getOperand(0);
8636 EVT VT = N->getValueType(0);
8638 // fold (fp_to_uint c1fp) -> c1
8639 if (isConstantFPBuildVectorOrConstantFP(N0))
8640 return DAG.getNode(ISD::FP_TO_UINT, SDLoc(N), VT, N0);
8642 return FoldIntToFPToInt(N, DAG);
8645 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
8646 SDValue N0 = N->getOperand(0);
8647 SDValue N1 = N->getOperand(1);
8648 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8649 EVT VT = N->getValueType(0);
8651 // fold (fp_round c1fp) -> c1fp
8653 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0, N1);
8655 // fold (fp_round (fp_extend x)) -> x
8656 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
8657 return N0.getOperand(0);
8659 // fold (fp_round (fp_round x)) -> (fp_round x)
8660 if (N0.getOpcode() == ISD::FP_ROUND) {
8661 const bool NIsTrunc = N->getConstantOperandVal(1) == 1;
8662 const bool N0IsTrunc = N0.getNode()->getConstantOperandVal(1) == 1;
8663 // If the first fp_round isn't a value preserving truncation, it might
8664 // introduce a tie in the second fp_round, that wouldn't occur in the
8665 // single-step fp_round we want to fold to.
8666 // In other words, double rounding isn't the same as rounding.
8667 // Also, this is a value preserving truncation iff both fp_round's are.
8668 if (DAG.getTarget().Options.UnsafeFPMath || N0IsTrunc) {
8670 return DAG.getNode(ISD::FP_ROUND, DL, VT, N0.getOperand(0),
8671 DAG.getIntPtrConstant(NIsTrunc && N0IsTrunc, DL));
8675 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
8676 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
8677 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, SDLoc(N0), VT,
8678 N0.getOperand(0), N1);
8679 AddToWorklist(Tmp.getNode());
8680 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
8681 Tmp, N0.getOperand(1));
8687 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
8688 SDValue N0 = N->getOperand(0);
8689 EVT VT = N->getValueType(0);
8690 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
8691 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8693 // fold (fp_round_inreg c1fp) -> c1fp
8694 if (N0CFP && isTypeLegal(EVT)) {
8696 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), DL, EVT);
8697 return DAG.getNode(ISD::FP_EXTEND, DL, VT, Round);
8703 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
8704 SDValue N0 = N->getOperand(0);
8705 EVT VT = N->getValueType(0);
8707 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
8708 if (N->hasOneUse() &&
8709 N->use_begin()->getOpcode() == ISD::FP_ROUND)
8712 // fold (fp_extend c1fp) -> c1fp
8713 if (isConstantFPBuildVectorOrConstantFP(N0))
8714 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, N0);
8716 // fold (fp_extend (fp16_to_fp op)) -> (fp16_to_fp op)
8717 if (N0.getOpcode() == ISD::FP16_TO_FP &&
8718 TLI.getOperationAction(ISD::FP16_TO_FP, VT) == TargetLowering::Legal)
8719 return DAG.getNode(ISD::FP16_TO_FP, SDLoc(N), VT, N0.getOperand(0));
8721 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
8723 if (N0.getOpcode() == ISD::FP_ROUND
8724 && N0.getNode()->getConstantOperandVal(1) == 1) {
8725 SDValue In = N0.getOperand(0);
8726 if (In.getValueType() == VT) return In;
8727 if (VT.bitsLT(In.getValueType()))
8728 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT,
8729 In, N0.getOperand(1));
8730 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, In);
8733 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
8734 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
8735 TLI.isLoadExtLegal(ISD::EXTLOAD, VT, N0.getValueType())) {
8736 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
8737 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
8739 LN0->getBasePtr(), N0.getValueType(),
8740 LN0->getMemOperand());
8741 CombineTo(N, ExtLoad);
8742 CombineTo(N0.getNode(),
8743 DAG.getNode(ISD::FP_ROUND, SDLoc(N0),
8744 N0.getValueType(), ExtLoad,
8745 DAG.getIntPtrConstant(1, SDLoc(N0))),
8746 ExtLoad.getValue(1));
8747 return SDValue(N, 0); // Return N so it doesn't get rechecked!
8753 SDValue DAGCombiner::visitFCEIL(SDNode *N) {
8754 SDValue N0 = N->getOperand(0);
8755 EVT VT = N->getValueType(0);
8757 // fold (fceil c1) -> fceil(c1)
8758 if (isConstantFPBuildVectorOrConstantFP(N0))
8759 return DAG.getNode(ISD::FCEIL, SDLoc(N), VT, N0);
8764 SDValue DAGCombiner::visitFTRUNC(SDNode *N) {
8765 SDValue N0 = N->getOperand(0);
8766 EVT VT = N->getValueType(0);
8768 // fold (ftrunc c1) -> ftrunc(c1)
8769 if (isConstantFPBuildVectorOrConstantFP(N0))
8770 return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0);
8775 SDValue DAGCombiner::visitFFLOOR(SDNode *N) {
8776 SDValue N0 = N->getOperand(0);
8777 EVT VT = N->getValueType(0);
8779 // fold (ffloor c1) -> ffloor(c1)
8780 if (isConstantFPBuildVectorOrConstantFP(N0))
8781 return DAG.getNode(ISD::FFLOOR, SDLoc(N), VT, N0);
8786 // FIXME: FNEG and FABS have a lot in common; refactor.
8787 SDValue DAGCombiner::visitFNEG(SDNode *N) {
8788 SDValue N0 = N->getOperand(0);
8789 EVT VT = N->getValueType(0);
8791 // Constant fold FNEG.
8792 if (isConstantFPBuildVectorOrConstantFP(N0))
8793 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0);
8795 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(),
8796 &DAG.getTarget().Options))
8797 return GetNegatedExpression(N0, DAG, LegalOperations);
8799 // Transform fneg(bitconvert(x)) -> bitconvert(x ^ sign) to avoid loading
8800 // constant pool values.
8801 if (!TLI.isFNegFree(VT) &&
8802 N0.getOpcode() == ISD::BITCAST &&
8803 N0.getNode()->hasOneUse()) {
8804 SDValue Int = N0.getOperand(0);
8805 EVT IntVT = Int.getValueType();
8806 if (IntVT.isInteger() && !IntVT.isVector()) {
8808 if (N0.getValueType().isVector()) {
8809 // For a vector, get a mask such as 0x80... per scalar element
8811 SignMask = APInt::getSignBit(N0.getValueType().getScalarSizeInBits());
8812 SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask);
8814 // For a scalar, just generate 0x80...
8815 SignMask = APInt::getSignBit(IntVT.getSizeInBits());
8818 Int = DAG.getNode(ISD::XOR, DL0, IntVT, Int,
8819 DAG.getConstant(SignMask, DL0, IntVT));
8820 AddToWorklist(Int.getNode());
8821 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Int);
8825 // (fneg (fmul c, x)) -> (fmul -c, x)
8826 if (N0.getOpcode() == ISD::FMUL &&
8827 (N0.getNode()->hasOneUse() || !TLI.isFNegFree(VT))) {
8828 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
8830 APFloat CVal = CFP1->getValueAPF();
8832 if (Level >= AfterLegalizeDAG &&
8833 (TLI.isFPImmLegal(CVal, N->getValueType(0)) ||
8834 TLI.isOperationLegal(ISD::ConstantFP, N->getValueType(0))))
8836 ISD::FMUL, SDLoc(N), VT, N0.getOperand(0),
8837 DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0.getOperand(1)));
8844 SDValue DAGCombiner::visitFMINNUM(SDNode *N) {
8845 SDValue N0 = N->getOperand(0);
8846 SDValue N1 = N->getOperand(1);
8847 const ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8848 const ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
8850 if (N0CFP && N1CFP) {
8851 const APFloat &C0 = N0CFP->getValueAPF();
8852 const APFloat &C1 = N1CFP->getValueAPF();
8853 return DAG.getConstantFP(minnum(C0, C1), SDLoc(N), N->getValueType(0));
8857 EVT VT = N->getValueType(0);
8858 // Canonicalize to constant on RHS.
8859 return DAG.getNode(ISD::FMINNUM, SDLoc(N), VT, N1, N0);
8865 SDValue DAGCombiner::visitFMAXNUM(SDNode *N) {
8866 SDValue N0 = N->getOperand(0);
8867 SDValue N1 = N->getOperand(1);
8868 const ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8869 const ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
8871 if (N0CFP && N1CFP) {
8872 const APFloat &C0 = N0CFP->getValueAPF();
8873 const APFloat &C1 = N1CFP->getValueAPF();
8874 return DAG.getConstantFP(maxnum(C0, C1), SDLoc(N), N->getValueType(0));
8878 EVT VT = N->getValueType(0);
8879 // Canonicalize to constant on RHS.
8880 return DAG.getNode(ISD::FMAXNUM, SDLoc(N), VT, N1, N0);
8886 SDValue DAGCombiner::visitFABS(SDNode *N) {
8887 SDValue N0 = N->getOperand(0);
8888 EVT VT = N->getValueType(0);
8890 // fold (fabs c1) -> fabs(c1)
8891 if (isConstantFPBuildVectorOrConstantFP(N0))
8892 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
8894 // fold (fabs (fabs x)) -> (fabs x)
8895 if (N0.getOpcode() == ISD::FABS)
8896 return N->getOperand(0);
8898 // fold (fabs (fneg x)) -> (fabs x)
8899 // fold (fabs (fcopysign x, y)) -> (fabs x)
8900 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
8901 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0.getOperand(0));
8903 // Transform fabs(bitconvert(x)) -> bitconvert(x & ~sign) to avoid loading
8904 // constant pool values.
8905 if (!TLI.isFAbsFree(VT) &&
8906 N0.getOpcode() == ISD::BITCAST &&
8907 N0.getNode()->hasOneUse()) {
8908 SDValue Int = N0.getOperand(0);
8909 EVT IntVT = Int.getValueType();
8910 if (IntVT.isInteger() && !IntVT.isVector()) {
8912 if (N0.getValueType().isVector()) {
8913 // For a vector, get a mask such as 0x7f... per scalar element
8915 SignMask = ~APInt::getSignBit(N0.getValueType().getScalarSizeInBits());
8916 SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask);
8918 // For a scalar, just generate 0x7f...
8919 SignMask = ~APInt::getSignBit(IntVT.getSizeInBits());
8922 Int = DAG.getNode(ISD::AND, DL, IntVT, Int,
8923 DAG.getConstant(SignMask, DL, IntVT));
8924 AddToWorklist(Int.getNode());
8925 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0), Int);
8932 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
8933 SDValue Chain = N->getOperand(0);
8934 SDValue N1 = N->getOperand(1);
8935 SDValue N2 = N->getOperand(2);
8937 // If N is a constant we could fold this into a fallthrough or unconditional
8938 // branch. However that doesn't happen very often in normal code, because
8939 // Instcombine/SimplifyCFG should have handled the available opportunities.
8940 // If we did this folding here, it would be necessary to update the
8941 // MachineBasicBlock CFG, which is awkward.
8943 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
8945 if (N1.getOpcode() == ISD::SETCC &&
8946 TLI.isOperationLegalOrCustom(ISD::BR_CC,
8947 N1.getOperand(0).getValueType())) {
8948 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
8949 Chain, N1.getOperand(2),
8950 N1.getOperand(0), N1.getOperand(1), N2);
8953 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
8954 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
8955 (N1.getOperand(0).hasOneUse() &&
8956 N1.getOperand(0).getOpcode() == ISD::SRL))) {
8957 SDNode *Trunc = nullptr;
8958 if (N1.getOpcode() == ISD::TRUNCATE) {
8959 // Look pass the truncate.
8960 Trunc = N1.getNode();
8961 N1 = N1.getOperand(0);
8964 // Match this pattern so that we can generate simpler code:
8967 // %b = and i32 %a, 2
8968 // %c = srl i32 %b, 1
8969 // brcond i32 %c ...
8974 // %b = and i32 %a, 2
8975 // %c = setcc eq %b, 0
8978 // This applies only when the AND constant value has one bit set and the
8979 // SRL constant is equal to the log2 of the AND constant. The back-end is
8980 // smart enough to convert the result into a TEST/JMP sequence.
8981 SDValue Op0 = N1.getOperand(0);
8982 SDValue Op1 = N1.getOperand(1);
8984 if (Op0.getOpcode() == ISD::AND &&
8985 Op1.getOpcode() == ISD::Constant) {
8986 SDValue AndOp1 = Op0.getOperand(1);
8988 if (AndOp1.getOpcode() == ISD::Constant) {
8989 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
8991 if (AndConst.isPowerOf2() &&
8992 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
8996 getSetCCResultType(Op0.getValueType()),
8997 Op0, DAG.getConstant(0, DL, Op0.getValueType()),
9000 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, DL,
9001 MVT::Other, Chain, SetCC, N2);
9002 // Don't add the new BRCond into the worklist or else SimplifySelectCC
9003 // will convert it back to (X & C1) >> C2.
9004 CombineTo(N, NewBRCond, false);
9005 // Truncate is dead.
9007 deleteAndRecombine(Trunc);
9008 // Replace the uses of SRL with SETCC
9009 WorklistRemover DeadNodes(*this);
9010 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
9011 deleteAndRecombine(N1.getNode());
9012 return SDValue(N, 0); // Return N so it doesn't get rechecked!
9018 // Restore N1 if the above transformation doesn't match.
9019 N1 = N->getOperand(1);
9022 // Transform br(xor(x, y)) -> br(x != y)
9023 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
9024 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
9025 SDNode *TheXor = N1.getNode();
9026 SDValue Op0 = TheXor->getOperand(0);
9027 SDValue Op1 = TheXor->getOperand(1);
9028 if (Op0.getOpcode() == Op1.getOpcode()) {
9029 // Avoid missing important xor optimizations.
9030 SDValue Tmp = visitXOR(TheXor);
9031 if (Tmp.getNode()) {
9032 if (Tmp.getNode() != TheXor) {
9033 DEBUG(dbgs() << "\nReplacing.8 ";
9035 dbgs() << "\nWith: ";
9036 Tmp.getNode()->dump(&DAG);
9038 WorklistRemover DeadNodes(*this);
9039 DAG.ReplaceAllUsesOfValueWith(N1, Tmp);
9040 deleteAndRecombine(TheXor);
9041 return DAG.getNode(ISD::BRCOND, SDLoc(N),
9042 MVT::Other, Chain, Tmp, N2);
9045 // visitXOR has changed XOR's operands or replaced the XOR completely,
9047 return SDValue(N, 0);
9051 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
9053 if (isOneConstant(Op0) && Op0.hasOneUse() &&
9054 Op0.getOpcode() == ISD::XOR) {
9055 TheXor = Op0.getNode();
9059 EVT SetCCVT = N1.getValueType();
9061 SetCCVT = getSetCCResultType(SetCCVT);
9062 SDValue SetCC = DAG.getSetCC(SDLoc(TheXor),
9065 Equal ? ISD::SETEQ : ISD::SETNE);
9066 // Replace the uses of XOR with SETCC
9067 WorklistRemover DeadNodes(*this);
9068 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
9069 deleteAndRecombine(N1.getNode());
9070 return DAG.getNode(ISD::BRCOND, SDLoc(N),
9071 MVT::Other, Chain, SetCC, N2);
9078 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
9080 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
9081 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
9082 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
9084 // If N is a constant we could fold this into a fallthrough or unconditional
9085 // branch. However that doesn't happen very often in normal code, because
9086 // Instcombine/SimplifyCFG should have handled the available opportunities.
9087 // If we did this folding here, it would be necessary to update the
9088 // MachineBasicBlock CFG, which is awkward.
9090 // Use SimplifySetCC to simplify SETCC's.
9091 SDValue Simp = SimplifySetCC(getSetCCResultType(CondLHS.getValueType()),
9092 CondLHS, CondRHS, CC->get(), SDLoc(N),
9094 if (Simp.getNode()) AddToWorklist(Simp.getNode());
9096 // fold to a simpler setcc
9097 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
9098 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
9099 N->getOperand(0), Simp.getOperand(2),
9100 Simp.getOperand(0), Simp.getOperand(1),
9106 /// Return true if 'Use' is a load or a store that uses N as its base pointer
9107 /// and that N may be folded in the load / store addressing mode.
9108 static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
9110 const TargetLowering &TLI) {
9114 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) {
9115 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
9117 VT = LD->getMemoryVT();
9118 AS = LD->getAddressSpace();
9119 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) {
9120 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
9122 VT = ST->getMemoryVT();
9123 AS = ST->getAddressSpace();
9127 TargetLowering::AddrMode AM;
9128 if (N->getOpcode() == ISD::ADD) {
9129 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
9132 AM.BaseOffs = Offset->getSExtValue();
9136 } else if (N->getOpcode() == ISD::SUB) {
9137 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
9140 AM.BaseOffs = -Offset->getSExtValue();
9147 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext()), AS);
9150 /// Try turning a load/store into a pre-indexed load/store when the base
9151 /// pointer is an add or subtract and it has other uses besides the load/store.
9152 /// After the transformation, the new indexed load/store has effectively folded
9153 /// the add/subtract in and all of its other uses are redirected to the
9155 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
9156 if (Level < AfterLegalizeDAG)
9162 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9163 if (LD->isIndexed())
9165 VT = LD->getMemoryVT();
9166 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
9167 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
9169 Ptr = LD->getBasePtr();
9170 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9171 if (ST->isIndexed())
9173 VT = ST->getMemoryVT();
9174 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
9175 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
9177 Ptr = ST->getBasePtr();
9183 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
9184 // out. There is no reason to make this a preinc/predec.
9185 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
9186 Ptr.getNode()->hasOneUse())
9189 // Ask the target to do addressing mode selection.
9192 ISD::MemIndexedMode AM = ISD::UNINDEXED;
9193 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
9196 // Backends without true r+i pre-indexed forms may need to pass a
9197 // constant base with a variable offset so that constant coercion
9198 // will work with the patterns in canonical form.
9199 bool Swapped = false;
9200 if (isa<ConstantSDNode>(BasePtr)) {
9201 std::swap(BasePtr, Offset);
9205 // Don't create a indexed load / store with zero offset.
9206 if (isNullConstant(Offset))
9209 // Try turning it into a pre-indexed load / store except when:
9210 // 1) The new base ptr is a frame index.
9211 // 2) If N is a store and the new base ptr is either the same as or is a
9212 // predecessor of the value being stored.
9213 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
9214 // that would create a cycle.
9215 // 4) All uses are load / store ops that use it as old base ptr.
9217 // Check #1. Preinc'ing a frame index would require copying the stack pointer
9218 // (plus the implicit offset) to a register to preinc anyway.
9219 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
9224 SDValue Val = cast<StoreSDNode>(N)->getValue();
9225 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
9229 // If the offset is a constant, there may be other adds of constants that
9230 // can be folded with this one. We should do this to avoid having to keep
9231 // a copy of the original base pointer.
9232 SmallVector<SDNode *, 16> OtherUses;
9233 if (isa<ConstantSDNode>(Offset))
9234 for (SDNode::use_iterator UI = BasePtr.getNode()->use_begin(),
9235 UE = BasePtr.getNode()->use_end();
9237 SDUse &Use = UI.getUse();
9238 // Skip the use that is Ptr and uses of other results from BasePtr's
9239 // node (important for nodes that return multiple results).
9240 if (Use.getUser() == Ptr.getNode() || Use != BasePtr)
9243 if (Use.getUser()->isPredecessorOf(N))
9246 if (Use.getUser()->getOpcode() != ISD::ADD &&
9247 Use.getUser()->getOpcode() != ISD::SUB) {
9252 SDValue Op1 = Use.getUser()->getOperand((UI.getOperandNo() + 1) & 1);
9253 if (!isa<ConstantSDNode>(Op1)) {
9258 // FIXME: In some cases, we can be smarter about this.
9259 if (Op1.getValueType() != Offset.getValueType()) {
9264 OtherUses.push_back(Use.getUser());
9268 std::swap(BasePtr, Offset);
9270 // Now check for #3 and #4.
9271 bool RealUse = false;
9273 // Caches for hasPredecessorHelper
9274 SmallPtrSet<const SDNode *, 32> Visited;
9275 SmallVector<const SDNode *, 16> Worklist;
9277 for (SDNode *Use : Ptr.getNode()->uses()) {
9280 if (N->hasPredecessorHelper(Use, Visited, Worklist))
9283 // If Ptr may be folded in addressing mode of other use, then it's
9284 // not profitable to do this transformation.
9285 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI))
9294 Result = DAG.getIndexedLoad(SDValue(N,0), SDLoc(N),
9295 BasePtr, Offset, AM);
9297 Result = DAG.getIndexedStore(SDValue(N,0), SDLoc(N),
9298 BasePtr, Offset, AM);
9301 DEBUG(dbgs() << "\nReplacing.4 ";
9303 dbgs() << "\nWith: ";
9304 Result.getNode()->dump(&DAG);
9306 WorklistRemover DeadNodes(*this);
9308 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
9309 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
9311 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
9314 // Finally, since the node is now dead, remove it from the graph.
9315 deleteAndRecombine(N);
9318 std::swap(BasePtr, Offset);
9320 // Replace other uses of BasePtr that can be updated to use Ptr
9321 for (unsigned i = 0, e = OtherUses.size(); i != e; ++i) {
9322 unsigned OffsetIdx = 1;
9323 if (OtherUses[i]->getOperand(OffsetIdx).getNode() == BasePtr.getNode())
9325 assert(OtherUses[i]->getOperand(!OffsetIdx).getNode() ==
9326 BasePtr.getNode() && "Expected BasePtr operand");
9328 // We need to replace ptr0 in the following expression:
9329 // x0 * offset0 + y0 * ptr0 = t0
9331 // x1 * offset1 + y1 * ptr0 = t1 (the indexed load/store)
9333 // where x0, x1, y0 and y1 in {-1, 1} are given by the types of the
9334 // indexed load/store and the expresion that needs to be re-written.
9336 // Therefore, we have:
9337 // t0 = (x0 * offset0 - x1 * y0 * y1 *offset1) + (y0 * y1) * t1
9339 ConstantSDNode *CN =
9340 cast<ConstantSDNode>(OtherUses[i]->getOperand(OffsetIdx));
9342 APInt Offset0 = CN->getAPIntValue();
9343 APInt Offset1 = cast<ConstantSDNode>(Offset)->getAPIntValue();
9345 X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1;
9346 Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1;
9347 X1 = (AM == ISD::PRE_DEC && !Swapped) ? -1 : 1;
9348 Y1 = (AM == ISD::PRE_DEC && Swapped) ? -1 : 1;
9350 unsigned Opcode = (Y0 * Y1 < 0) ? ISD::SUB : ISD::ADD;
9352 APInt CNV = Offset0;
9353 if (X0 < 0) CNV = -CNV;
9354 if (X1 * Y0 * Y1 < 0) CNV = CNV + Offset1;
9355 else CNV = CNV - Offset1;
9357 SDLoc DL(OtherUses[i]);
9359 // We can now generate the new expression.
9360 SDValue NewOp1 = DAG.getConstant(CNV, DL, CN->getValueType(0));
9361 SDValue NewOp2 = Result.getValue(isLoad ? 1 : 0);
9363 SDValue NewUse = DAG.getNode(Opcode,
9365 OtherUses[i]->getValueType(0), NewOp1, NewOp2);
9366 DAG.ReplaceAllUsesOfValueWith(SDValue(OtherUses[i], 0), NewUse);
9367 deleteAndRecombine(OtherUses[i]);
9370 // Replace the uses of Ptr with uses of the updated base value.
9371 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0));
9372 deleteAndRecombine(Ptr.getNode());
9377 /// Try to combine a load/store with a add/sub of the base pointer node into a
9378 /// post-indexed load/store. The transformation folded the add/subtract into the
9379 /// new indexed load/store effectively and all of its uses are redirected to the
9381 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
9382 if (Level < AfterLegalizeDAG)
9388 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9389 if (LD->isIndexed())
9391 VT = LD->getMemoryVT();
9392 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
9393 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
9395 Ptr = LD->getBasePtr();
9396 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9397 if (ST->isIndexed())
9399 VT = ST->getMemoryVT();
9400 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
9401 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
9403 Ptr = ST->getBasePtr();
9409 if (Ptr.getNode()->hasOneUse())
9412 for (SDNode *Op : Ptr.getNode()->uses()) {
9414 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
9419 ISD::MemIndexedMode AM = ISD::UNINDEXED;
9420 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
9421 // Don't create a indexed load / store with zero offset.
9422 if (isNullConstant(Offset))
9425 // Try turning it into a post-indexed load / store except when
9426 // 1) All uses are load / store ops that use it as base ptr (and
9427 // it may be folded as addressing mmode).
9428 // 2) Op must be independent of N, i.e. Op is neither a predecessor
9429 // nor a successor of N. Otherwise, if Op is folded that would
9432 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
9436 bool TryNext = false;
9437 for (SDNode *Use : BasePtr.getNode()->uses()) {
9438 if (Use == Ptr.getNode())
9441 // If all the uses are load / store addresses, then don't do the
9443 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
9444 bool RealUse = false;
9445 for (SDNode *UseUse : Use->uses()) {
9446 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI))
9461 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
9462 SDValue Result = isLoad
9463 ? DAG.getIndexedLoad(SDValue(N,0), SDLoc(N),
9464 BasePtr, Offset, AM)
9465 : DAG.getIndexedStore(SDValue(N,0), SDLoc(N),
9466 BasePtr, Offset, AM);
9469 DEBUG(dbgs() << "\nReplacing.5 ";
9471 dbgs() << "\nWith: ";
9472 Result.getNode()->dump(&DAG);
9474 WorklistRemover DeadNodes(*this);
9476 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
9477 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
9479 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
9482 // Finally, since the node is now dead, remove it from the graph.
9483 deleteAndRecombine(N);
9485 // Replace the uses of Use with uses of the updated base value.
9486 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
9487 Result.getValue(isLoad ? 1 : 0));
9488 deleteAndRecombine(Op);
9497 /// \brief Return the base-pointer arithmetic from an indexed \p LD.
9498 SDValue DAGCombiner::SplitIndexingFromLoad(LoadSDNode *LD) {
9499 ISD::MemIndexedMode AM = LD->getAddressingMode();
9500 assert(AM != ISD::UNINDEXED);
9501 SDValue BP = LD->getOperand(1);
9502 SDValue Inc = LD->getOperand(2);
9504 // Some backends use TargetConstants for load offsets, but don't expect
9505 // TargetConstants in general ADD nodes. We can convert these constants into
9506 // regular Constants (if the constant is not opaque).
9507 assert((Inc.getOpcode() != ISD::TargetConstant ||
9508 !cast<ConstantSDNode>(Inc)->isOpaque()) &&
9509 "Cannot split out indexing using opaque target constants");
9510 if (Inc.getOpcode() == ISD::TargetConstant) {
9511 ConstantSDNode *ConstInc = cast<ConstantSDNode>(Inc);
9512 Inc = DAG.getConstant(*ConstInc->getConstantIntValue(), SDLoc(Inc),
9513 ConstInc->getValueType(0));
9517 (AM == ISD::PRE_INC || AM == ISD::POST_INC ? ISD::ADD : ISD::SUB);
9518 return DAG.getNode(Opc, SDLoc(LD), BP.getSimpleValueType(), BP, Inc);
9521 SDValue DAGCombiner::visitLOAD(SDNode *N) {
9522 LoadSDNode *LD = cast<LoadSDNode>(N);
9523 SDValue Chain = LD->getChain();
9524 SDValue Ptr = LD->getBasePtr();
9526 // If load is not volatile and there are no uses of the loaded value (and
9527 // the updated indexed value in case of indexed loads), change uses of the
9528 // chain value into uses of the chain input (i.e. delete the dead load).
9529 if (!LD->isVolatile()) {
9530 if (N->getValueType(1) == MVT::Other) {
9532 if (!N->hasAnyUseOfValue(0)) {
9533 // It's not safe to use the two value CombineTo variant here. e.g.
9534 // v1, chain2 = load chain1, loc
9535 // v2, chain3 = load chain2, loc
9537 // Now we replace use of chain2 with chain1. This makes the second load
9538 // isomorphic to the one we are deleting, and thus makes this load live.
9539 DEBUG(dbgs() << "\nReplacing.6 ";
9541 dbgs() << "\nWith chain: ";
9542 Chain.getNode()->dump(&DAG);
9544 WorklistRemover DeadNodes(*this);
9545 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
9548 deleteAndRecombine(N);
9550 return SDValue(N, 0); // Return N so it doesn't get rechecked!
9554 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
9556 // If this load has an opaque TargetConstant offset, then we cannot split
9557 // the indexing into an add/sub directly (that TargetConstant may not be
9558 // valid for a different type of node, and we cannot convert an opaque
9559 // target constant into a regular constant).
9560 bool HasOTCInc = LD->getOperand(2).getOpcode() == ISD::TargetConstant &&
9561 cast<ConstantSDNode>(LD->getOperand(2))->isOpaque();
9563 if (!N->hasAnyUseOfValue(0) &&
9564 ((MaySplitLoadIndex && !HasOTCInc) || !N->hasAnyUseOfValue(1))) {
9565 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
9567 if (N->hasAnyUseOfValue(1) && MaySplitLoadIndex && !HasOTCInc) {
9568 Index = SplitIndexingFromLoad(LD);
9569 // Try to fold the base pointer arithmetic into subsequent loads and
9571 AddUsersToWorklist(N);
9573 Index = DAG.getUNDEF(N->getValueType(1));
9574 DEBUG(dbgs() << "\nReplacing.7 ";
9576 dbgs() << "\nWith: ";
9577 Undef.getNode()->dump(&DAG);
9578 dbgs() << " and 2 other values\n");
9579 WorklistRemover DeadNodes(*this);
9580 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef);
9581 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Index);
9582 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain);
9583 deleteAndRecombine(N);
9584 return SDValue(N, 0); // Return N so it doesn't get rechecked!
9589 // If this load is directly stored, replace the load value with the stored
9591 // TODO: Handle store large -> read small portion.
9592 // TODO: Handle TRUNCSTORE/LOADEXT
9593 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
9594 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
9595 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
9596 if (PrevST->getBasePtr() == Ptr &&
9597 PrevST->getValue().getValueType() == N->getValueType(0))
9598 return CombineTo(N, Chain.getOperand(1), Chain);
9602 // Try to infer better alignment information than the load already has.
9603 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
9604 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
9605 if (Align > LD->getMemOperand()->getBaseAlignment()) {
9607 DAG.getExtLoad(LD->getExtensionType(), SDLoc(N),
9608 LD->getValueType(0),
9609 Chain, Ptr, LD->getPointerInfo(),
9611 LD->isVolatile(), LD->isNonTemporal(),
9612 LD->isInvariant(), Align, LD->getAAInfo());
9613 if (NewLoad.getNode() != N)
9614 return CombineTo(N, NewLoad, SDValue(NewLoad.getNode(), 1), true);
9619 bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA
9620 : DAG.getSubtarget().useAA();
9622 if (CombinerAAOnlyFunc.getNumOccurrences() &&
9623 CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
9626 if (UseAA && LD->isUnindexed()) {
9627 // Walk up chain skipping non-aliasing memory nodes.
9628 SDValue BetterChain = FindBetterChain(N, Chain);
9630 // If there is a better chain.
9631 if (Chain != BetterChain) {
9634 // Replace the chain to void dependency.
9635 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
9636 ReplLoad = DAG.getLoad(N->getValueType(0), SDLoc(LD),
9637 BetterChain, Ptr, LD->getMemOperand());
9639 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD),
9640 LD->getValueType(0),
9641 BetterChain, Ptr, LD->getMemoryVT(),
9642 LD->getMemOperand());
9645 // Create token factor to keep old chain connected.
9646 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N),
9647 MVT::Other, Chain, ReplLoad.getValue(1));
9649 // Make sure the new and old chains are cleaned up.
9650 AddToWorklist(Token.getNode());
9652 // Replace uses with load result and token factor. Don't add users
9654 return CombineTo(N, ReplLoad.getValue(0), Token, false);
9658 // Try transforming N to an indexed load.
9659 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
9660 return SDValue(N, 0);
9662 // Try to slice up N to more direct loads if the slices are mapped to
9663 // different register banks or pairing can take place.
9665 return SDValue(N, 0);
9671 /// \brief Helper structure used to slice a load in smaller loads.
9672 /// Basically a slice is obtained from the following sequence:
9673 /// Origin = load Ty1, Base
9674 /// Shift = srl Ty1 Origin, CstTy Amount
9675 /// Inst = trunc Shift to Ty2
9677 /// Then, it will be rewriten into:
9678 /// Slice = load SliceTy, Base + SliceOffset
9679 /// [Inst = zext Slice to Ty2], only if SliceTy <> Ty2
9681 /// SliceTy is deduced from the number of bits that are actually used to
9683 struct LoadedSlice {
9684 /// \brief Helper structure used to compute the cost of a slice.
9686 /// Are we optimizing for code size.
9691 unsigned CrossRegisterBanksCopies;
9695 Cost(bool ForCodeSize = false)
9696 : ForCodeSize(ForCodeSize), Loads(0), Truncates(0),
9697 CrossRegisterBanksCopies(0), ZExts(0), Shift(0) {}
9699 /// \brief Get the cost of one isolated slice.
9700 Cost(const LoadedSlice &LS, bool ForCodeSize = false)
9701 : ForCodeSize(ForCodeSize), Loads(1), Truncates(0),
9702 CrossRegisterBanksCopies(0), ZExts(0), Shift(0) {
9703 EVT TruncType = LS.Inst->getValueType(0);
9704 EVT LoadedType = LS.getLoadedType();
9705 if (TruncType != LoadedType &&
9706 !LS.DAG->getTargetLoweringInfo().isZExtFree(LoadedType, TruncType))
9710 /// \brief Account for slicing gain in the current cost.
9711 /// Slicing provide a few gains like removing a shift or a
9712 /// truncate. This method allows to grow the cost of the original
9713 /// load with the gain from this slice.
9714 void addSliceGain(const LoadedSlice &LS) {
9715 // Each slice saves a truncate.
9716 const TargetLowering &TLI = LS.DAG->getTargetLoweringInfo();
9717 if (!TLI.isTruncateFree(LS.Inst->getValueType(0),
9718 LS.Inst->getOperand(0).getValueType()))
9720 // If there is a shift amount, this slice gets rid of it.
9723 // If this slice can merge a cross register bank copy, account for it.
9724 if (LS.canMergeExpensiveCrossRegisterBankCopy())
9725 ++CrossRegisterBanksCopies;
9728 Cost &operator+=(const Cost &RHS) {
9730 Truncates += RHS.Truncates;
9731 CrossRegisterBanksCopies += RHS.CrossRegisterBanksCopies;
9737 bool operator==(const Cost &RHS) const {
9738 return Loads == RHS.Loads && Truncates == RHS.Truncates &&
9739 CrossRegisterBanksCopies == RHS.CrossRegisterBanksCopies &&
9740 ZExts == RHS.ZExts && Shift == RHS.Shift;
9743 bool operator!=(const Cost &RHS) const { return !(*this == RHS); }
9745 bool operator<(const Cost &RHS) const {
9746 // Assume cross register banks copies are as expensive as loads.
9747 // FIXME: Do we want some more target hooks?
9748 unsigned ExpensiveOpsLHS = Loads + CrossRegisterBanksCopies;
9749 unsigned ExpensiveOpsRHS = RHS.Loads + RHS.CrossRegisterBanksCopies;
9750 // Unless we are optimizing for code size, consider the
9751 // expensive operation first.
9752 if (!ForCodeSize && ExpensiveOpsLHS != ExpensiveOpsRHS)
9753 return ExpensiveOpsLHS < ExpensiveOpsRHS;
9754 return (Truncates + ZExts + Shift + ExpensiveOpsLHS) <
9755 (RHS.Truncates + RHS.ZExts + RHS.Shift + ExpensiveOpsRHS);
9758 bool operator>(const Cost &RHS) const { return RHS < *this; }
9760 bool operator<=(const Cost &RHS) const { return !(RHS < *this); }
9762 bool operator>=(const Cost &RHS) const { return !(*this < RHS); }
9764 // The last instruction that represent the slice. This should be a
9765 // truncate instruction.
9767 // The original load instruction.
9769 // The right shift amount in bits from the original load.
9771 // The DAG from which Origin came from.
9772 // This is used to get some contextual information about legal types, etc.
9775 LoadedSlice(SDNode *Inst = nullptr, LoadSDNode *Origin = nullptr,
9776 unsigned Shift = 0, SelectionDAG *DAG = nullptr)
9777 : Inst(Inst), Origin(Origin), Shift(Shift), DAG(DAG) {}
9779 /// \brief Get the bits used in a chunk of bits \p BitWidth large.
9780 /// \return Result is \p BitWidth and has used bits set to 1 and
9781 /// not used bits set to 0.
9782 APInt getUsedBits() const {
9783 // Reproduce the trunc(lshr) sequence:
9784 // - Start from the truncated value.
9785 // - Zero extend to the desired bit width.
9787 assert(Origin && "No original load to compare against.");
9788 unsigned BitWidth = Origin->getValueSizeInBits(0);
9789 assert(Inst && "This slice is not bound to an instruction");
9790 assert(Inst->getValueSizeInBits(0) <= BitWidth &&
9791 "Extracted slice is bigger than the whole type!");
9792 APInt UsedBits(Inst->getValueSizeInBits(0), 0);
9793 UsedBits.setAllBits();
9794 UsedBits = UsedBits.zext(BitWidth);
9799 /// \brief Get the size of the slice to be loaded in bytes.
9800 unsigned getLoadedSize() const {
9801 unsigned SliceSize = getUsedBits().countPopulation();
9802 assert(!(SliceSize & 0x7) && "Size is not a multiple of a byte.");
9803 return SliceSize / 8;
9806 /// \brief Get the type that will be loaded for this slice.
9807 /// Note: This may not be the final type for the slice.
9808 EVT getLoadedType() const {
9809 assert(DAG && "Missing context");
9810 LLVMContext &Ctxt = *DAG->getContext();
9811 return EVT::getIntegerVT(Ctxt, getLoadedSize() * 8);
9814 /// \brief Get the alignment of the load used for this slice.
9815 unsigned getAlignment() const {
9816 unsigned Alignment = Origin->getAlignment();
9817 unsigned Offset = getOffsetFromBase();
9819 Alignment = MinAlign(Alignment, Alignment + Offset);
9823 /// \brief Check if this slice can be rewritten with legal operations.
9824 bool isLegal() const {
9825 // An invalid slice is not legal.
9826 if (!Origin || !Inst || !DAG)
9829 // Offsets are for indexed load only, we do not handle that.
9830 if (Origin->getOffset().getOpcode() != ISD::UNDEF)
9833 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
9835 // Check that the type is legal.
9836 EVT SliceType = getLoadedType();
9837 if (!TLI.isTypeLegal(SliceType))
9840 // Check that the load is legal for this type.
9841 if (!TLI.isOperationLegal(ISD::LOAD, SliceType))
9844 // Check that the offset can be computed.
9845 // 1. Check its type.
9846 EVT PtrType = Origin->getBasePtr().getValueType();
9847 if (PtrType == MVT::Untyped || PtrType.isExtended())
9850 // 2. Check that it fits in the immediate.
9851 if (!TLI.isLegalAddImmediate(getOffsetFromBase()))
9854 // 3. Check that the computation is legal.
9855 if (!TLI.isOperationLegal(ISD::ADD, PtrType))
9858 // Check that the zext is legal if it needs one.
9859 EVT TruncateType = Inst->getValueType(0);
9860 if (TruncateType != SliceType &&
9861 !TLI.isOperationLegal(ISD::ZERO_EXTEND, TruncateType))
9867 /// \brief Get the offset in bytes of this slice in the original chunk of
9869 /// \pre DAG != nullptr.
9870 uint64_t getOffsetFromBase() const {
9871 assert(DAG && "Missing context.");
9873 DAG->getTargetLoweringInfo().getDataLayout()->isBigEndian();
9874 assert(!(Shift & 0x7) && "Shifts not aligned on Bytes are not supported.");
9875 uint64_t Offset = Shift / 8;
9876 unsigned TySizeInBytes = Origin->getValueSizeInBits(0) / 8;
9877 assert(!(Origin->getValueSizeInBits(0) & 0x7) &&
9878 "The size of the original loaded type is not a multiple of a"
9880 // If Offset is bigger than TySizeInBytes, it means we are loading all
9881 // zeros. This should have been optimized before in the process.
9882 assert(TySizeInBytes > Offset &&
9883 "Invalid shift amount for given loaded size");
9885 Offset = TySizeInBytes - Offset - getLoadedSize();
9889 /// \brief Generate the sequence of instructions to load the slice
9890 /// represented by this object and redirect the uses of this slice to
9891 /// this new sequence of instructions.
9892 /// \pre this->Inst && this->Origin are valid Instructions and this
9893 /// object passed the legal check: LoadedSlice::isLegal returned true.
9894 /// \return The last instruction of the sequence used to load the slice.
9895 SDValue loadSlice() const {
9896 assert(Inst && Origin && "Unable to replace a non-existing slice.");
9897 const SDValue &OldBaseAddr = Origin->getBasePtr();
9898 SDValue BaseAddr = OldBaseAddr;
9899 // Get the offset in that chunk of bytes w.r.t. the endianess.
9900 int64_t Offset = static_cast<int64_t>(getOffsetFromBase());
9901 assert(Offset >= 0 && "Offset too big to fit in int64_t!");
9903 // BaseAddr = BaseAddr + Offset.
9904 EVT ArithType = BaseAddr.getValueType();
9906 BaseAddr = DAG->getNode(ISD::ADD, DL, ArithType, BaseAddr,
9907 DAG->getConstant(Offset, DL, ArithType));
9910 // Create the type of the loaded slice according to its size.
9911 EVT SliceType = getLoadedType();
9913 // Create the load for the slice.
9914 SDValue LastInst = DAG->getLoad(
9915 SliceType, SDLoc(Origin), Origin->getChain(), BaseAddr,
9916 Origin->getPointerInfo().getWithOffset(Offset), Origin->isVolatile(),
9917 Origin->isNonTemporal(), Origin->isInvariant(), getAlignment());
9918 // If the final type is not the same as the loaded type, this means that
9919 // we have to pad with zero. Create a zero extend for that.
9920 EVT FinalType = Inst->getValueType(0);
9921 if (SliceType != FinalType)
9923 DAG->getNode(ISD::ZERO_EXTEND, SDLoc(LastInst), FinalType, LastInst);
9927 /// \brief Check if this slice can be merged with an expensive cross register
9928 /// bank copy. E.g.,
9930 /// f = bitcast i32 i to float
9931 bool canMergeExpensiveCrossRegisterBankCopy() const {
9932 if (!Inst || !Inst->hasOneUse())
9934 SDNode *Use = *Inst->use_begin();
9935 if (Use->getOpcode() != ISD::BITCAST)
9937 assert(DAG && "Missing context");
9938 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
9939 EVT ResVT = Use->getValueType(0);
9940 const TargetRegisterClass *ResRC = TLI.getRegClassFor(ResVT.getSimpleVT());
9941 const TargetRegisterClass *ArgRC =
9942 TLI.getRegClassFor(Use->getOperand(0).getValueType().getSimpleVT());
9943 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT))
9946 // At this point, we know that we perform a cross-register-bank copy.
9947 // Check if it is expensive.
9948 const TargetRegisterInfo *TRI = DAG->getSubtarget().getRegisterInfo();
9949 // Assume bitcasts are cheap, unless both register classes do not
9950 // explicitly share a common sub class.
9951 if (!TRI || TRI->getCommonSubClass(ArgRC, ResRC))
9954 // Check if it will be merged with the load.
9955 // 1. Check the alignment constraint.
9956 unsigned RequiredAlignment = TLI.getDataLayout()->getABITypeAlignment(
9957 ResVT.getTypeForEVT(*DAG->getContext()));
9959 if (RequiredAlignment > getAlignment())
9962 // 2. Check that the load is a legal operation for that type.
9963 if (!TLI.isOperationLegal(ISD::LOAD, ResVT))
9966 // 3. Check that we do not have a zext in the way.
9967 if (Inst->getValueType(0) != getLoadedType())
9975 /// \brief Check that all bits set in \p UsedBits form a dense region, i.e.,
9976 /// \p UsedBits looks like 0..0 1..1 0..0.
9977 static bool areUsedBitsDense(const APInt &UsedBits) {
9978 // If all the bits are one, this is dense!
9979 if (UsedBits.isAllOnesValue())
9982 // Get rid of the unused bits on the right.
9983 APInt NarrowedUsedBits = UsedBits.lshr(UsedBits.countTrailingZeros());
9984 // Get rid of the unused bits on the left.
9985 if (NarrowedUsedBits.countLeadingZeros())
9986 NarrowedUsedBits = NarrowedUsedBits.trunc(NarrowedUsedBits.getActiveBits());
9987 // Check that the chunk of bits is completely used.
9988 return NarrowedUsedBits.isAllOnesValue();
9991 /// \brief Check whether or not \p First and \p Second are next to each other
9992 /// in memory. This means that there is no hole between the bits loaded
9993 /// by \p First and the bits loaded by \p Second.
9994 static bool areSlicesNextToEachOther(const LoadedSlice &First,
9995 const LoadedSlice &Second) {
9996 assert(First.Origin == Second.Origin && First.Origin &&
9997 "Unable to match different memory origins.");
9998 APInt UsedBits = First.getUsedBits();
9999 assert((UsedBits & Second.getUsedBits()) == 0 &&
10000 "Slices are not supposed to overlap.");
10001 UsedBits |= Second.getUsedBits();
10002 return areUsedBitsDense(UsedBits);
10005 /// \brief Adjust the \p GlobalLSCost according to the target
10006 /// paring capabilities and the layout of the slices.
10007 /// \pre \p GlobalLSCost should account for at least as many loads as
10008 /// there is in the slices in \p LoadedSlices.
10009 static void adjustCostForPairing(SmallVectorImpl<LoadedSlice> &LoadedSlices,
10010 LoadedSlice::Cost &GlobalLSCost) {
10011 unsigned NumberOfSlices = LoadedSlices.size();
10012 // If there is less than 2 elements, no pairing is possible.
10013 if (NumberOfSlices < 2)
10016 // Sort the slices so that elements that are likely to be next to each
10017 // other in memory are next to each other in the list.
10018 std::sort(LoadedSlices.begin(), LoadedSlices.end(),
10019 [](const LoadedSlice &LHS, const LoadedSlice &RHS) {
10020 assert(LHS.Origin == RHS.Origin && "Different bases not implemented.");
10021 return LHS.getOffsetFromBase() < RHS.getOffsetFromBase();
10023 const TargetLowering &TLI = LoadedSlices[0].DAG->getTargetLoweringInfo();
10024 // First (resp. Second) is the first (resp. Second) potentially candidate
10025 // to be placed in a paired load.
10026 const LoadedSlice *First = nullptr;
10027 const LoadedSlice *Second = nullptr;
10028 for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice,
10029 // Set the beginning of the pair.
10032 Second = &LoadedSlices[CurrSlice];
10034 // If First is NULL, it means we start a new pair.
10035 // Get to the next slice.
10039 EVT LoadedType = First->getLoadedType();
10041 // If the types of the slices are different, we cannot pair them.
10042 if (LoadedType != Second->getLoadedType())
10045 // Check if the target supplies paired loads for this type.
10046 unsigned RequiredAlignment = 0;
10047 if (!TLI.hasPairedLoad(LoadedType, RequiredAlignment)) {
10048 // move to the next pair, this type is hopeless.
10052 // Check if we meet the alignment requirement.
10053 if (RequiredAlignment > First->getAlignment())
10056 // Check that both loads are next to each other in memory.
10057 if (!areSlicesNextToEachOther(*First, *Second))
10060 assert(GlobalLSCost.Loads > 0 && "We save more loads than we created!");
10061 --GlobalLSCost.Loads;
10062 // Move to the next pair.
10067 /// \brief Check the profitability of all involved LoadedSlice.
10068 /// Currently, it is considered profitable if there is exactly two
10069 /// involved slices (1) which are (2) next to each other in memory, and
10070 /// whose cost (\see LoadedSlice::Cost) is smaller than the original load (3).
10072 /// Note: The order of the elements in \p LoadedSlices may be modified, but not
10073 /// the elements themselves.
10075 /// FIXME: When the cost model will be mature enough, we can relax
10076 /// constraints (1) and (2).
10077 static bool isSlicingProfitable(SmallVectorImpl<LoadedSlice> &LoadedSlices,
10078 const APInt &UsedBits, bool ForCodeSize) {
10079 unsigned NumberOfSlices = LoadedSlices.size();
10080 if (StressLoadSlicing)
10081 return NumberOfSlices > 1;
10084 if (NumberOfSlices != 2)
10088 if (!areUsedBitsDense(UsedBits))
10092 LoadedSlice::Cost OrigCost(ForCodeSize), GlobalSlicingCost(ForCodeSize);
10093 // The original code has one big load.
10094 OrigCost.Loads = 1;
10095 for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice) {
10096 const LoadedSlice &LS = LoadedSlices[CurrSlice];
10097 // Accumulate the cost of all the slices.
10098 LoadedSlice::Cost SliceCost(LS, ForCodeSize);
10099 GlobalSlicingCost += SliceCost;
10101 // Account as cost in the original configuration the gain obtained
10102 // with the current slices.
10103 OrigCost.addSliceGain(LS);
10106 // If the target supports paired load, adjust the cost accordingly.
10107 adjustCostForPairing(LoadedSlices, GlobalSlicingCost);
10108 return OrigCost > GlobalSlicingCost;
10111 /// \brief If the given load, \p LI, is used only by trunc or trunc(lshr)
10112 /// operations, split it in the various pieces being extracted.
10114 /// This sort of thing is introduced by SROA.
10115 /// This slicing takes care not to insert overlapping loads.
10116 /// \pre LI is a simple load (i.e., not an atomic or volatile load).
10117 bool DAGCombiner::SliceUpLoad(SDNode *N) {
10118 if (Level < AfterLegalizeDAG)
10121 LoadSDNode *LD = cast<LoadSDNode>(N);
10122 if (LD->isVolatile() || !ISD::isNormalLoad(LD) ||
10123 !LD->getValueType(0).isInteger())
10126 // Keep track of already used bits to detect overlapping values.
10127 // In that case, we will just abort the transformation.
10128 APInt UsedBits(LD->getValueSizeInBits(0), 0);
10130 SmallVector<LoadedSlice, 4> LoadedSlices;
10132 // Check if this load is used as several smaller chunks of bits.
10133 // Basically, look for uses in trunc or trunc(lshr) and record a new chain
10134 // of computation for each trunc.
10135 for (SDNode::use_iterator UI = LD->use_begin(), UIEnd = LD->use_end();
10136 UI != UIEnd; ++UI) {
10137 // Skip the uses of the chain.
10138 if (UI.getUse().getResNo() != 0)
10141 SDNode *User = *UI;
10142 unsigned Shift = 0;
10144 // Check if this is a trunc(lshr).
10145 if (User->getOpcode() == ISD::SRL && User->hasOneUse() &&
10146 isa<ConstantSDNode>(User->getOperand(1))) {
10147 Shift = cast<ConstantSDNode>(User->getOperand(1))->getZExtValue();
10148 User = *User->use_begin();
10151 // At this point, User is a Truncate, iff we encountered, trunc or
10153 if (User->getOpcode() != ISD::TRUNCATE)
10156 // The width of the type must be a power of 2 and greater than 8-bits.
10157 // Otherwise the load cannot be represented in LLVM IR.
10158 // Moreover, if we shifted with a non-8-bits multiple, the slice
10159 // will be across several bytes. We do not support that.
10160 unsigned Width = User->getValueSizeInBits(0);
10161 if (Width < 8 || !isPowerOf2_32(Width) || (Shift & 0x7))
10164 // Build the slice for this chain of computations.
10165 LoadedSlice LS(User, LD, Shift, &DAG);
10166 APInt CurrentUsedBits = LS.getUsedBits();
10168 // Check if this slice overlaps with another.
10169 if ((CurrentUsedBits & UsedBits) != 0)
10171 // Update the bits used globally.
10172 UsedBits |= CurrentUsedBits;
10174 // Check if the new slice would be legal.
10178 // Record the slice.
10179 LoadedSlices.push_back(LS);
10182 // Abort slicing if it does not seem to be profitable.
10183 if (!isSlicingProfitable(LoadedSlices, UsedBits, ForCodeSize))
10188 // Rewrite each chain to use an independent load.
10189 // By construction, each chain can be represented by a unique load.
10191 // Prepare the argument for the new token factor for all the slices.
10192 SmallVector<SDValue, 8> ArgChains;
10193 for (SmallVectorImpl<LoadedSlice>::const_iterator
10194 LSIt = LoadedSlices.begin(),
10195 LSItEnd = LoadedSlices.end();
10196 LSIt != LSItEnd; ++LSIt) {
10197 SDValue SliceInst = LSIt->loadSlice();
10198 CombineTo(LSIt->Inst, SliceInst, true);
10199 if (SliceInst.getNode()->getOpcode() != ISD::LOAD)
10200 SliceInst = SliceInst.getOperand(0);
10201 assert(SliceInst->getOpcode() == ISD::LOAD &&
10202 "It takes more than a zext to get to the loaded slice!!");
10203 ArgChains.push_back(SliceInst.getValue(1));
10206 SDValue Chain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other,
10208 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
10212 /// Check to see if V is (and load (ptr), imm), where the load is having
10213 /// specific bytes cleared out. If so, return the byte size being masked out
10214 /// and the shift amount.
10215 static std::pair<unsigned, unsigned>
10216 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
10217 std::pair<unsigned, unsigned> Result(0, 0);
10219 // Check for the structure we're looking for.
10220 if (V->getOpcode() != ISD::AND ||
10221 !isa<ConstantSDNode>(V->getOperand(1)) ||
10222 !ISD::isNormalLoad(V->getOperand(0).getNode()))
10225 // Check the chain and pointer.
10226 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
10227 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
10229 // The store should be chained directly to the load or be an operand of a
10231 if (LD == Chain.getNode())
10233 else if (Chain->getOpcode() != ISD::TokenFactor)
10234 return Result; // Fail.
10237 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
10238 if (Chain->getOperand(i).getNode() == LD) {
10242 if (!isOk) return Result;
10245 // This only handles simple types.
10246 if (V.getValueType() != MVT::i16 &&
10247 V.getValueType() != MVT::i32 &&
10248 V.getValueType() != MVT::i64)
10251 // Check the constant mask. Invert it so that the bits being masked out are
10252 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
10253 // follow the sign bit for uniformity.
10254 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
10255 unsigned NotMaskLZ = countLeadingZeros(NotMask);
10256 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
10257 unsigned NotMaskTZ = countTrailingZeros(NotMask);
10258 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
10259 if (NotMaskLZ == 64) return Result; // All zero mask.
10261 // See if we have a continuous run of bits. If so, we have 0*1+0*
10262 if (countTrailingOnes(NotMask >> NotMaskTZ) + NotMaskTZ + NotMaskLZ != 64)
10265 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
10266 if (V.getValueType() != MVT::i64 && NotMaskLZ)
10267 NotMaskLZ -= 64-V.getValueSizeInBits();
10269 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
10270 switch (MaskedBytes) {
10274 default: return Result; // All one mask, or 5-byte mask.
10277 // Verify that the first bit starts at a multiple of mask so that the access
10278 // is aligned the same as the access width.
10279 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
10281 Result.first = MaskedBytes;
10282 Result.second = NotMaskTZ/8;
10287 /// Check to see if IVal is something that provides a value as specified by
10288 /// MaskInfo. If so, replace the specified store with a narrower store of
10289 /// truncated IVal.
10291 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
10292 SDValue IVal, StoreSDNode *St,
10294 unsigned NumBytes = MaskInfo.first;
10295 unsigned ByteShift = MaskInfo.second;
10296 SelectionDAG &DAG = DC->getDAG();
10298 // Check to see if IVal is all zeros in the part being masked in by the 'or'
10299 // that uses this. If not, this is not a replacement.
10300 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
10301 ByteShift*8, (ByteShift+NumBytes)*8);
10302 if (!DAG.MaskedValueIsZero(IVal, Mask)) return nullptr;
10304 // Check that it is legal on the target to do this. It is legal if the new
10305 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
10307 MVT VT = MVT::getIntegerVT(NumBytes*8);
10308 if (!DC->isTypeLegal(VT))
10311 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
10312 // shifted by ByteShift and truncated down to NumBytes.
10315 IVal = DAG.getNode(ISD::SRL, DL, IVal.getValueType(), IVal,
10316 DAG.getConstant(ByteShift*8, DL,
10317 DC->getShiftAmountTy(IVal.getValueType())));
10320 // Figure out the offset for the store and the alignment of the access.
10322 unsigned NewAlign = St->getAlignment();
10324 if (DAG.getTargetLoweringInfo().isLittleEndian())
10325 StOffset = ByteShift;
10327 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
10329 SDValue Ptr = St->getBasePtr();
10332 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(),
10333 Ptr, DAG.getConstant(StOffset, DL, Ptr.getValueType()));
10334 NewAlign = MinAlign(NewAlign, StOffset);
10337 // Truncate down to the new size.
10338 IVal = DAG.getNode(ISD::TRUNCATE, SDLoc(IVal), VT, IVal);
10341 return DAG.getStore(St->getChain(), SDLoc(St), IVal, Ptr,
10342 St->getPointerInfo().getWithOffset(StOffset),
10343 false, false, NewAlign).getNode();
10347 /// Look for sequence of load / op / store where op is one of 'or', 'xor', and
10348 /// 'and' of immediates. If 'op' is only touching some of the loaded bits, try
10349 /// narrowing the load and store if it would end up being a win for performance
10351 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
10352 StoreSDNode *ST = cast<StoreSDNode>(N);
10353 if (ST->isVolatile())
10356 SDValue Chain = ST->getChain();
10357 SDValue Value = ST->getValue();
10358 SDValue Ptr = ST->getBasePtr();
10359 EVT VT = Value.getValueType();
10361 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
10364 unsigned Opc = Value.getOpcode();
10366 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
10367 // is a byte mask indicating a consecutive number of bytes, check to see if
10368 // Y is known to provide just those bytes. If so, we try to replace the
10369 // load + replace + store sequence with a single (narrower) store, which makes
10371 if (Opc == ISD::OR) {
10372 std::pair<unsigned, unsigned> MaskedLoad;
10373 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
10374 if (MaskedLoad.first)
10375 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
10376 Value.getOperand(1), ST,this))
10377 return SDValue(NewST, 0);
10379 // Or is commutative, so try swapping X and Y.
10380 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
10381 if (MaskedLoad.first)
10382 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
10383 Value.getOperand(0), ST,this))
10384 return SDValue(NewST, 0);
10387 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
10388 Value.getOperand(1).getOpcode() != ISD::Constant)
10391 SDValue N0 = Value.getOperand(0);
10392 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
10393 Chain == SDValue(N0.getNode(), 1)) {
10394 LoadSDNode *LD = cast<LoadSDNode>(N0);
10395 if (LD->getBasePtr() != Ptr ||
10396 LD->getPointerInfo().getAddrSpace() !=
10397 ST->getPointerInfo().getAddrSpace())
10400 // Find the type to narrow it the load / op / store to.
10401 SDValue N1 = Value.getOperand(1);
10402 unsigned BitWidth = N1.getValueSizeInBits();
10403 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
10404 if (Opc == ISD::AND)
10405 Imm ^= APInt::getAllOnesValue(BitWidth);
10406 if (Imm == 0 || Imm.isAllOnesValue())
10408 unsigned ShAmt = Imm.countTrailingZeros();
10409 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
10410 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
10411 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
10412 // The narrowing should be profitable, the load/store operation should be
10413 // legal (or custom) and the store size should be equal to the NewVT width.
10414 while (NewBW < BitWidth &&
10415 (NewVT.getStoreSizeInBits() != NewBW ||
10416 !TLI.isOperationLegalOrCustom(Opc, NewVT) ||
10417 !TLI.isNarrowingProfitable(VT, NewVT))) {
10418 NewBW = NextPowerOf2(NewBW);
10419 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
10421 if (NewBW >= BitWidth)
10424 // If the lsb changed does not start at the type bitwidth boundary,
10425 // start at the previous one.
10427 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
10428 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt,
10429 std::min(BitWidth, ShAmt + NewBW));
10430 if ((Imm & Mask) == Imm) {
10431 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
10432 if (Opc == ISD::AND)
10433 NewImm ^= APInt::getAllOnesValue(NewBW);
10434 uint64_t PtrOff = ShAmt / 8;
10435 // For big endian targets, we need to adjust the offset to the pointer to
10436 // load the correct bytes.
10437 if (TLI.isBigEndian())
10438 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
10440 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
10441 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
10442 if (NewAlign < TLI.getDataLayout()->getABITypeAlignment(NewVTTy))
10445 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LD),
10446 Ptr.getValueType(), Ptr,
10447 DAG.getConstant(PtrOff, SDLoc(LD),
10448 Ptr.getValueType()));
10449 SDValue NewLD = DAG.getLoad(NewVT, SDLoc(N0),
10450 LD->getChain(), NewPtr,
10451 LD->getPointerInfo().getWithOffset(PtrOff),
10452 LD->isVolatile(), LD->isNonTemporal(),
10453 LD->isInvariant(), NewAlign,
10455 SDValue NewVal = DAG.getNode(Opc, SDLoc(Value), NewVT, NewLD,
10456 DAG.getConstant(NewImm, SDLoc(Value),
10458 SDValue NewST = DAG.getStore(Chain, SDLoc(N),
10460 ST->getPointerInfo().getWithOffset(PtrOff),
10461 false, false, NewAlign);
10463 AddToWorklist(NewPtr.getNode());
10464 AddToWorklist(NewLD.getNode());
10465 AddToWorklist(NewVal.getNode());
10466 WorklistRemover DeadNodes(*this);
10467 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1));
10476 /// For a given floating point load / store pair, if the load value isn't used
10477 /// by any other operations, then consider transforming the pair to integer
10478 /// load / store operations if the target deems the transformation profitable.
10479 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
10480 StoreSDNode *ST = cast<StoreSDNode>(N);
10481 SDValue Chain = ST->getChain();
10482 SDValue Value = ST->getValue();
10483 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
10484 Value.hasOneUse() &&
10485 Chain == SDValue(Value.getNode(), 1)) {
10486 LoadSDNode *LD = cast<LoadSDNode>(Value);
10487 EVT VT = LD->getMemoryVT();
10488 if (!VT.isFloatingPoint() ||
10489 VT != ST->getMemoryVT() ||
10490 LD->isNonTemporal() ||
10491 ST->isNonTemporal() ||
10492 LD->getPointerInfo().getAddrSpace() != 0 ||
10493 ST->getPointerInfo().getAddrSpace() != 0)
10496 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
10497 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
10498 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
10499 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
10500 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
10503 unsigned LDAlign = LD->getAlignment();
10504 unsigned STAlign = ST->getAlignment();
10505 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
10506 unsigned ABIAlign = TLI.getDataLayout()->getABITypeAlignment(IntVTTy);
10507 if (LDAlign < ABIAlign || STAlign < ABIAlign)
10510 SDValue NewLD = DAG.getLoad(IntVT, SDLoc(Value),
10511 LD->getChain(), LD->getBasePtr(),
10512 LD->getPointerInfo(),
10513 false, false, false, LDAlign);
10515 SDValue NewST = DAG.getStore(NewLD.getValue(1), SDLoc(N),
10516 NewLD, ST->getBasePtr(),
10517 ST->getPointerInfo(),
10518 false, false, STAlign);
10520 AddToWorklist(NewLD.getNode());
10521 AddToWorklist(NewST.getNode());
10522 WorklistRemover DeadNodes(*this);
10523 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1));
10532 /// Helper struct to parse and store a memory address as base + index + offset.
10533 /// We ignore sign extensions when it is safe to do so.
10534 /// The following two expressions are not equivalent. To differentiate we need
10535 /// to store whether there was a sign extension involved in the index
10537 /// (load (i64 add (i64 copyfromreg %c)
10538 /// (i64 signextend (add (i8 load %index)
10542 /// (load (i64 add (i64 copyfromreg %c)
10543 /// (i64 signextend (i32 add (i32 signextend (i8 load %index))
10545 struct BaseIndexOffset {
10549 bool IsIndexSignExt;
10551 BaseIndexOffset() : Offset(0), IsIndexSignExt(false) {}
10553 BaseIndexOffset(SDValue Base, SDValue Index, int64_t Offset,
10554 bool IsIndexSignExt) :
10555 Base(Base), Index(Index), Offset(Offset), IsIndexSignExt(IsIndexSignExt) {}
10557 bool equalBaseIndex(const BaseIndexOffset &Other) {
10558 return Other.Base == Base && Other.Index == Index &&
10559 Other.IsIndexSignExt == IsIndexSignExt;
10562 /// Parses tree in Ptr for base, index, offset addresses.
10563 static BaseIndexOffset match(SDValue Ptr) {
10564 bool IsIndexSignExt = false;
10566 // We only can pattern match BASE + INDEX + OFFSET. If Ptr is not an ADD
10567 // instruction, then it could be just the BASE or everything else we don't
10568 // know how to handle. Just use Ptr as BASE and give up.
10569 if (Ptr->getOpcode() != ISD::ADD)
10570 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
10572 // We know that we have at least an ADD instruction. Try to pattern match
10573 // the simple case of BASE + OFFSET.
10574 if (isa<ConstantSDNode>(Ptr->getOperand(1))) {
10575 int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue();
10576 return BaseIndexOffset(Ptr->getOperand(0), SDValue(), Offset,
10580 // Inside a loop the current BASE pointer is calculated using an ADD and a
10581 // MUL instruction. In this case Ptr is the actual BASE pointer.
10582 // (i64 add (i64 %array_ptr)
10583 // (i64 mul (i64 %induction_var)
10584 // (i64 %element_size)))
10585 if (Ptr->getOperand(1)->getOpcode() == ISD::MUL)
10586 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
10588 // Look at Base + Index + Offset cases.
10589 SDValue Base = Ptr->getOperand(0);
10590 SDValue IndexOffset = Ptr->getOperand(1);
10592 // Skip signextends.
10593 if (IndexOffset->getOpcode() == ISD::SIGN_EXTEND) {
10594 IndexOffset = IndexOffset->getOperand(0);
10595 IsIndexSignExt = true;
10598 // Either the case of Base + Index (no offset) or something else.
10599 if (IndexOffset->getOpcode() != ISD::ADD)
10600 return BaseIndexOffset(Base, IndexOffset, 0, IsIndexSignExt);
10602 // Now we have the case of Base + Index + offset.
10603 SDValue Index = IndexOffset->getOperand(0);
10604 SDValue Offset = IndexOffset->getOperand(1);
10606 if (!isa<ConstantSDNode>(Offset))
10607 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
10609 // Ignore signextends.
10610 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
10611 Index = Index->getOperand(0);
10612 IsIndexSignExt = true;
10613 } else IsIndexSignExt = false;
10615 int64_t Off = cast<ConstantSDNode>(Offset)->getSExtValue();
10616 return BaseIndexOffset(Base, Index, Off, IsIndexSignExt);
10621 SDValue DAGCombiner::getMergedConstantVectorStore(SelectionDAG &DAG,
10623 ArrayRef<MemOpLink> Stores,
10625 SmallVector<SDValue, 8> BuildVector;
10627 for (unsigned I = 0, E = Ty.getVectorNumElements(); I != E; ++I)
10628 BuildVector.push_back(cast<StoreSDNode>(Stores[I].MemNode)->getValue());
10630 return DAG.getNode(ISD::BUILD_VECTOR, SL, Ty, BuildVector);
10633 bool DAGCombiner::MergeStoresOfConstantsOrVecElts(
10634 SmallVectorImpl<MemOpLink> &StoreNodes, EVT MemVT,
10635 unsigned NumElem, bool IsConstantSrc, bool UseVector) {
10636 // Make sure we have something to merge.
10640 int64_t ElementSizeBytes = MemVT.getSizeInBits() / 8;
10641 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;
10642 unsigned LatestNodeUsed = 0;
10644 for (unsigned i=0; i < NumElem; ++i) {
10645 // Find a chain for the new wide-store operand. Notice that some
10646 // of the store nodes that we found may not be selected for inclusion
10647 // in the wide store. The chain we use needs to be the chain of the
10648 // latest store node which is *used* and replaced by the wide store.
10649 if (StoreNodes[i].SequenceNum < StoreNodes[LatestNodeUsed].SequenceNum)
10650 LatestNodeUsed = i;
10653 // The latest Node in the DAG.
10654 LSBaseSDNode *LatestOp = StoreNodes[LatestNodeUsed].MemNode;
10655 SDLoc DL(StoreNodes[0].MemNode);
10659 // Find a legal type for the vector store.
10660 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
10661 assert(TLI.isTypeLegal(Ty) && "Illegal vector store");
10662 if (IsConstantSrc) {
10663 StoredVal = getMergedConstantVectorStore(DAG, DL, StoreNodes, Ty);
10665 SmallVector<SDValue, 8> Ops;
10666 for (unsigned i = 0; i < NumElem ; ++i) {
10667 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
10668 SDValue Val = St->getValue();
10669 // All of the operands of a BUILD_VECTOR must have the same type.
10670 if (Val.getValueType() != MemVT)
10672 Ops.push_back(Val);
10675 // Build the extracted vector elements back into a vector.
10676 StoredVal = DAG.getNode(ISD::BUILD_VECTOR, DL, Ty, Ops);
10679 // We should always use a vector store when merging extracted vector
10680 // elements, so this path implies a store of constants.
10681 assert(IsConstantSrc && "Merged vector elements should use vector store");
10683 unsigned SizeInBits = NumElem * ElementSizeBytes * 8;
10684 APInt StoreInt(SizeInBits, 0);
10686 // Construct a single integer constant which is made of the smaller
10687 // constant inputs.
10688 bool IsLE = TLI.isLittleEndian();
10689 for (unsigned i = 0; i < NumElem ; ++i) {
10690 unsigned Idx = IsLE ? (NumElem - 1 - i) : i;
10691 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[Idx].MemNode);
10692 SDValue Val = St->getValue();
10693 StoreInt <<= ElementSizeBytes * 8;
10694 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val)) {
10695 StoreInt |= C->getAPIntValue().zext(SizeInBits);
10696 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) {
10697 StoreInt |= C->getValueAPF().bitcastToAPInt().zext(SizeInBits);
10699 llvm_unreachable("Invalid constant element type");
10703 // Create the new Load and Store operations.
10704 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), SizeInBits);
10705 StoredVal = DAG.getConstant(StoreInt, DL, StoreTy);
10708 SDValue NewStore = DAG.getStore(LatestOp->getChain(), DL, StoredVal,
10709 FirstInChain->getBasePtr(),
10710 FirstInChain->getPointerInfo(),
10712 FirstInChain->getAlignment());
10714 // Replace the last store with the new store
10715 CombineTo(LatestOp, NewStore);
10716 // Erase all other stores.
10717 for (unsigned i = 0; i < NumElem ; ++i) {
10718 if (StoreNodes[i].MemNode == LatestOp)
10720 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
10721 // ReplaceAllUsesWith will replace all uses that existed when it was
10722 // called, but graph optimizations may cause new ones to appear. For
10723 // example, the case in pr14333 looks like
10725 // St's chain -> St -> another store -> X
10727 // And the only difference from St to the other store is the chain.
10728 // When we change it's chain to be St's chain they become identical,
10729 // get CSEed and the net result is that X is now a use of St.
10730 // Since we know that St is redundant, just iterate.
10731 while (!St->use_empty())
10732 DAG.ReplaceAllUsesWith(SDValue(St, 0), St->getChain());
10733 deleteAndRecombine(St);
10739 static bool allowableAlignment(const SelectionDAG &DAG,
10740 const TargetLowering &TLI, EVT EVTTy,
10741 unsigned AS, unsigned Align) {
10742 if (TLI.allowsMisalignedMemoryAccesses(EVTTy, AS, Align))
10745 Type *Ty = EVTTy.getTypeForEVT(*DAG.getContext());
10746 unsigned ABIAlignment = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
10747 return (Align >= ABIAlignment);
10750 void DAGCombiner::getStoreMergeAndAliasCandidates(
10751 StoreSDNode* St, SmallVectorImpl<MemOpLink> &StoreNodes,
10752 SmallVectorImpl<LSBaseSDNode*> &AliasLoadNodes) {
10753 // This holds the base pointer, index, and the offset in bytes from the base
10755 BaseIndexOffset BasePtr = BaseIndexOffset::match(St->getBasePtr());
10757 // We must have a base and an offset.
10758 if (!BasePtr.Base.getNode())
10761 // Do not handle stores to undef base pointers.
10762 if (BasePtr.Base.getOpcode() == ISD::UNDEF)
10765 // Walk up the chain and look for nodes with offsets from the same
10766 // base pointer. Stop when reaching an instruction with a different kind
10767 // or instruction which has a different base pointer.
10768 EVT MemVT = St->getMemoryVT();
10770 StoreSDNode *Index = St;
10772 // If the chain has more than one use, then we can't reorder the mem ops.
10773 if (Index != St && !SDValue(Index, 0)->hasOneUse())
10776 // Find the base pointer and offset for this memory node.
10777 BaseIndexOffset Ptr = BaseIndexOffset::match(Index->getBasePtr());
10779 // Check that the base pointer is the same as the original one.
10780 if (!Ptr.equalBaseIndex(BasePtr))
10783 // The memory operands must not be volatile.
10784 if (Index->isVolatile() || Index->isIndexed())
10788 if (StoreSDNode *St = dyn_cast<StoreSDNode>(Index))
10789 if (St->isTruncatingStore())
10792 // The stored memory type must be the same.
10793 if (Index->getMemoryVT() != MemVT)
10796 // We found a potential memory operand to merge.
10797 StoreNodes.push_back(MemOpLink(Index, Ptr.Offset, Seq++));
10799 // Find the next memory operand in the chain. If the next operand in the
10800 // chain is a store then move up and continue the scan with the next
10801 // memory operand. If the next operand is a load save it and use alias
10802 // information to check if it interferes with anything.
10803 SDNode *NextInChain = Index->getChain().getNode();
10805 if (StoreSDNode *STn = dyn_cast<StoreSDNode>(NextInChain)) {
10806 // We found a store node. Use it for the next iteration.
10809 } else if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(NextInChain)) {
10810 if (Ldn->isVolatile()) {
10815 // Save the load node for later. Continue the scan.
10816 AliasLoadNodes.push_back(Ldn);
10817 NextInChain = Ldn->getChain().getNode();
10827 bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
10828 if (OptLevel == CodeGenOpt::None)
10831 EVT MemVT = St->getMemoryVT();
10832 int64_t ElementSizeBytes = MemVT.getSizeInBits() / 8;
10833 bool NoVectors = DAG.getMachineFunction().getFunction()->hasFnAttribute(
10834 Attribute::NoImplicitFloat);
10836 // This function cannot currently deal with non-byte-sized memory sizes.
10837 if (ElementSizeBytes * 8 != MemVT.getSizeInBits())
10840 // Don't merge vectors into wider inputs.
10841 if (MemVT.isVector() || !MemVT.isSimple())
10844 // Perform an early exit check. Do not bother looking at stored values that
10845 // are not constants, loads, or extracted vector elements.
10846 SDValue StoredVal = St->getValue();
10847 bool IsLoadSrc = isa<LoadSDNode>(StoredVal);
10848 bool IsConstantSrc = isa<ConstantSDNode>(StoredVal) ||
10849 isa<ConstantFPSDNode>(StoredVal);
10850 bool IsExtractVecEltSrc = (StoredVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT);
10852 if (!IsConstantSrc && !IsLoadSrc && !IsExtractVecEltSrc)
10855 // Only look at ends of store sequences.
10856 SDValue Chain = SDValue(St, 0);
10857 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE)
10860 // Save the LoadSDNodes that we find in the chain.
10861 // We need to make sure that these nodes do not interfere with
10862 // any of the store nodes.
10863 SmallVector<LSBaseSDNode*, 8> AliasLoadNodes;
10865 // Save the StoreSDNodes that we find in the chain.
10866 SmallVector<MemOpLink, 8> StoreNodes;
10868 getStoreMergeAndAliasCandidates(St, StoreNodes, AliasLoadNodes);
10870 // Check if there is anything to merge.
10871 if (StoreNodes.size() < 2)
10874 // Sort the memory operands according to their distance from the base pointer.
10875 std::sort(StoreNodes.begin(), StoreNodes.end(),
10876 [](MemOpLink LHS, MemOpLink RHS) {
10877 return LHS.OffsetFromBase < RHS.OffsetFromBase ||
10878 (LHS.OffsetFromBase == RHS.OffsetFromBase &&
10879 LHS.SequenceNum > RHS.SequenceNum);
10882 // Scan the memory operations on the chain and find the first non-consecutive
10883 // store memory address.
10884 unsigned LastConsecutiveStore = 0;
10885 int64_t StartAddress = StoreNodes[0].OffsetFromBase;
10886 for (unsigned i = 0, e = StoreNodes.size(); i < e; ++i) {
10888 // Check that the addresses are consecutive starting from the second
10889 // element in the list of stores.
10891 int64_t CurrAddress = StoreNodes[i].OffsetFromBase;
10892 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
10896 bool Alias = false;
10897 // Check if this store interferes with any of the loads that we found.
10898 for (unsigned ld = 0, lde = AliasLoadNodes.size(); ld < lde; ++ld)
10899 if (isAlias(AliasLoadNodes[ld], StoreNodes[i].MemNode)) {
10903 // We found a load that alias with this store. Stop the sequence.
10907 // Mark this node as useful.
10908 LastConsecutiveStore = i;
10911 // The node with the lowest store address.
10912 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;
10913 unsigned FirstStoreAS = FirstInChain->getAddressSpace();
10914 unsigned FirstStoreAlign = FirstInChain->getAlignment();
10916 // Store the constants into memory as one consecutive store.
10917 if (IsConstantSrc) {
10918 unsigned LastLegalType = 0;
10919 unsigned LastLegalVectorType = 0;
10920 bool NonZero = false;
10921 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
10922 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
10923 SDValue StoredVal = St->getValue();
10925 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(StoredVal)) {
10926 NonZero |= !C->isNullValue();
10927 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) {
10928 NonZero |= !C->getConstantFPValue()->isNullValue();
10934 // Find a legal type for the constant store.
10935 unsigned SizeInBits = (i+1) * ElementSizeBytes * 8;
10936 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), SizeInBits);
10937 if (TLI.isTypeLegal(StoreTy) &&
10938 allowableAlignment(DAG, TLI, StoreTy, FirstStoreAS,
10939 FirstStoreAlign)) {
10940 LastLegalType = i+1;
10941 // Or check whether a truncstore is legal.
10942 } else if (TLI.getTypeAction(*DAG.getContext(), StoreTy) ==
10943 TargetLowering::TypePromoteInteger) {
10944 EVT LegalizedStoredValueTy =
10945 TLI.getTypeToTransformTo(*DAG.getContext(), StoredVal.getValueType());
10946 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy) &&
10947 allowableAlignment(DAG, TLI, LegalizedStoredValueTy, FirstStoreAS,
10948 FirstStoreAlign)) {
10949 LastLegalType = i + 1;
10953 // Find a legal type for the vector store.
10954 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
10955 if (TLI.isTypeLegal(Ty) &&
10956 allowableAlignment(DAG, TLI, Ty, FirstStoreAS, FirstStoreAlign)) {
10957 LastLegalVectorType = i + 1;
10962 // We only use vectors if the constant is known to be zero or the target
10963 // allows it and the function is not marked with the noimplicitfloat
10966 LastLegalVectorType = 0;
10967 } else if (NonZero && !TLI.storeOfVectorConstantIsCheap(MemVT,
10968 LastLegalVectorType,
10970 LastLegalVectorType = 0;
10973 // Check if we found a legal integer type to store.
10974 if (LastLegalType == 0 && LastLegalVectorType == 0)
10977 bool UseVector = (LastLegalVectorType > LastLegalType) && !NoVectors;
10978 unsigned NumElem = UseVector ? LastLegalVectorType : LastLegalType;
10980 return MergeStoresOfConstantsOrVecElts(StoreNodes, MemVT, NumElem,
10984 // When extracting multiple vector elements, try to store them
10985 // in one vector store rather than a sequence of scalar stores.
10986 if (IsExtractVecEltSrc) {
10987 unsigned NumElem = 0;
10988 for (unsigned i = 0; i < LastConsecutiveStore + 1; ++i) {
10989 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
10990 SDValue StoredVal = St->getValue();
10991 // This restriction could be loosened.
10992 // Bail out if any stored values are not elements extracted from a vector.
10993 // It should be possible to handle mixed sources, but load sources need
10994 // more careful handling (see the block of code below that handles
10995 // consecutive loads).
10996 if (StoredVal.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
10999 // Find a legal type for the vector store.
11000 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
11001 if (TLI.isTypeLegal(Ty) &&
11002 allowableAlignment(DAG, TLI, Ty, FirstStoreAS, FirstStoreAlign))
11006 return MergeStoresOfConstantsOrVecElts(StoreNodes, MemVT, NumElem,
11010 // Below we handle the case of multiple consecutive stores that
11011 // come from multiple consecutive loads. We merge them into a single
11012 // wide load and a single wide store.
11014 // Look for load nodes which are used by the stored values.
11015 SmallVector<MemOpLink, 8> LoadNodes;
11017 // Find acceptable loads. Loads need to have the same chain (token factor),
11018 // must not be zext, volatile, indexed, and they must be consecutive.
11019 BaseIndexOffset LdBasePtr;
11020 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
11021 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
11022 LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue());
11025 // Loads must only have one use.
11026 if (!Ld->hasNUsesOfValue(1, 0))
11029 // The memory operands must not be volatile.
11030 if (Ld->isVolatile() || Ld->isIndexed())
11033 // We do not accept ext loads.
11034 if (Ld->getExtensionType() != ISD::NON_EXTLOAD)
11037 // The stored memory type must be the same.
11038 if (Ld->getMemoryVT() != MemVT)
11041 BaseIndexOffset LdPtr = BaseIndexOffset::match(Ld->getBasePtr());
11042 // If this is not the first ptr that we check.
11043 if (LdBasePtr.Base.getNode()) {
11044 // The base ptr must be the same.
11045 if (!LdPtr.equalBaseIndex(LdBasePtr))
11048 // Check that all other base pointers are the same as this one.
11052 // We found a potential memory operand to merge.
11053 LoadNodes.push_back(MemOpLink(Ld, LdPtr.Offset, 0));
11056 if (LoadNodes.size() < 2)
11059 // If we have load/store pair instructions and we only have two values,
11061 unsigned RequiredAlignment;
11062 if (LoadNodes.size() == 2 && TLI.hasPairedLoad(MemVT, RequiredAlignment) &&
11063 St->getAlignment() >= RequiredAlignment)
11066 LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode);
11067 unsigned FirstLoadAS = FirstLoad->getAddressSpace();
11068 unsigned FirstLoadAlign = FirstLoad->getAlignment();
11070 // Scan the memory operations on the chain and find the first non-consecutive
11071 // load memory address. These variables hold the index in the store node
11073 unsigned LastConsecutiveLoad = 0;
11074 // This variable refers to the size and not index in the array.
11075 unsigned LastLegalVectorType = 0;
11076 unsigned LastLegalIntegerType = 0;
11077 StartAddress = LoadNodes[0].OffsetFromBase;
11078 SDValue FirstChain = FirstLoad->getChain();
11079 for (unsigned i = 1; i < LoadNodes.size(); ++i) {
11080 // All loads much share the same chain.
11081 if (LoadNodes[i].MemNode->getChain() != FirstChain)
11084 int64_t CurrAddress = LoadNodes[i].OffsetFromBase;
11085 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
11087 LastConsecutiveLoad = i;
11089 // Find a legal type for the vector store.
11090 EVT StoreTy = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
11091 if (TLI.isTypeLegal(StoreTy) &&
11092 allowableAlignment(DAG, TLI, StoreTy, FirstStoreAS, FirstStoreAlign) &&
11093 allowableAlignment(DAG, TLI, StoreTy, FirstLoadAS, FirstLoadAlign)) {
11094 LastLegalVectorType = i + 1;
11097 // Find a legal type for the integer store.
11098 unsigned SizeInBits = (i+1) * ElementSizeBytes * 8;
11099 StoreTy = EVT::getIntegerVT(*DAG.getContext(), SizeInBits);
11100 if (TLI.isTypeLegal(StoreTy) &&
11101 allowableAlignment(DAG, TLI, StoreTy, FirstStoreAS, FirstStoreAlign) &&
11102 allowableAlignment(DAG, TLI, StoreTy, FirstLoadAS, FirstLoadAlign))
11103 LastLegalIntegerType = i + 1;
11104 // Or check whether a truncstore and extload is legal.
11105 else if (TLI.getTypeAction(*DAG.getContext(), StoreTy) ==
11106 TargetLowering::TypePromoteInteger) {
11107 EVT LegalizedStoredValueTy =
11108 TLI.getTypeToTransformTo(*DAG.getContext(), StoreTy);
11109 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy) &&
11110 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LegalizedStoredValueTy, StoreTy) &&
11111 TLI.isLoadExtLegal(ISD::SEXTLOAD, LegalizedStoredValueTy, StoreTy) &&
11112 TLI.isLoadExtLegal(ISD::EXTLOAD, LegalizedStoredValueTy, StoreTy) &&
11113 allowableAlignment(DAG, TLI, LegalizedStoredValueTy, FirstStoreAS,
11114 FirstStoreAlign) &&
11115 allowableAlignment(DAG, TLI, LegalizedStoredValueTy, FirstLoadAS,
11117 LastLegalIntegerType = i+1;
11121 // Only use vector types if the vector type is larger than the integer type.
11122 // If they are the same, use integers.
11123 bool UseVectorTy = LastLegalVectorType > LastLegalIntegerType && !NoVectors;
11124 unsigned LastLegalType = std::max(LastLegalVectorType, LastLegalIntegerType);
11126 // We add +1 here because the LastXXX variables refer to location while
11127 // the NumElem refers to array/index size.
11128 unsigned NumElem = std::min(LastConsecutiveStore, LastConsecutiveLoad) + 1;
11129 NumElem = std::min(LastLegalType, NumElem);
11134 // The latest Node in the DAG.
11135 unsigned LatestNodeUsed = 0;
11136 for (unsigned i=1; i<NumElem; ++i) {
11137 // Find a chain for the new wide-store operand. Notice that some
11138 // of the store nodes that we found may not be selected for inclusion
11139 // in the wide store. The chain we use needs to be the chain of the
11140 // latest store node which is *used* and replaced by the wide store.
11141 if (StoreNodes[i].SequenceNum < StoreNodes[LatestNodeUsed].SequenceNum)
11142 LatestNodeUsed = i;
11145 LSBaseSDNode *LatestOp = StoreNodes[LatestNodeUsed].MemNode;
11147 // Find if it is better to use vectors or integers to load and store
11151 JointMemOpVT = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
11153 unsigned SizeInBits = NumElem * ElementSizeBytes * 8;
11154 JointMemOpVT = EVT::getIntegerVT(*DAG.getContext(), SizeInBits);
11157 SDLoc LoadDL(LoadNodes[0].MemNode);
11158 SDLoc StoreDL(StoreNodes[0].MemNode);
11160 SDValue NewLoad = DAG.getLoad(
11161 JointMemOpVT, LoadDL, FirstLoad->getChain(), FirstLoad->getBasePtr(),
11162 FirstLoad->getPointerInfo(), false, false, false, FirstLoadAlign);
11164 SDValue NewStore = DAG.getStore(
11165 LatestOp->getChain(), StoreDL, NewLoad, FirstInChain->getBasePtr(),
11166 FirstInChain->getPointerInfo(), false, false, FirstStoreAlign);
11168 // Replace one of the loads with the new load.
11169 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[0].MemNode);
11170 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1),
11171 SDValue(NewLoad.getNode(), 1));
11173 // Remove the rest of the load chains.
11174 for (unsigned i = 1; i < NumElem ; ++i) {
11175 // Replace all chain users of the old load nodes with the chain of the new
11177 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[i].MemNode);
11178 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Ld->getChain());
11181 // Replace the last store with the new store.
11182 CombineTo(LatestOp, NewStore);
11183 // Erase all other stores.
11184 for (unsigned i = 0; i < NumElem ; ++i) {
11185 // Remove all Store nodes.
11186 if (StoreNodes[i].MemNode == LatestOp)
11188 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
11189 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain());
11190 deleteAndRecombine(St);
11196 SDValue DAGCombiner::visitSTORE(SDNode *N) {
11197 StoreSDNode *ST = cast<StoreSDNode>(N);
11198 SDValue Chain = ST->getChain();
11199 SDValue Value = ST->getValue();
11200 SDValue Ptr = ST->getBasePtr();
11202 // If this is a store of a bit convert, store the input value if the
11203 // resultant store does not need a higher alignment than the original.
11204 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
11205 ST->isUnindexed()) {
11206 unsigned OrigAlign = ST->getAlignment();
11207 EVT SVT = Value.getOperand(0).getValueType();
11208 unsigned Align = TLI.getDataLayout()->
11209 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
11210 if (Align <= OrigAlign &&
11211 ((!LegalOperations && !ST->isVolatile()) ||
11212 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
11213 return DAG.getStore(Chain, SDLoc(N), Value.getOperand(0),
11214 Ptr, ST->getPointerInfo(), ST->isVolatile(),
11215 ST->isNonTemporal(), OrigAlign,
11219 // Turn 'store undef, Ptr' -> nothing.
11220 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
11223 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
11224 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
11225 // NOTE: If the original store is volatile, this transform must not increase
11226 // the number of stores. For example, on x86-32 an f64 can be stored in one
11227 // processor operation but an i64 (which is not legal) requires two. So the
11228 // transform should not be done in this case.
11229 if (Value.getOpcode() != ISD::TargetConstantFP) {
11231 switch (CFP->getSimpleValueType(0).SimpleTy) {
11232 default: llvm_unreachable("Unknown FP type");
11233 case MVT::f16: // We don't do this for these yet.
11239 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
11240 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
11242 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
11243 bitcastToAPInt().getZExtValue(), SDLoc(CFP),
11245 return DAG.getStore(Chain, SDLoc(N), Tmp,
11246 Ptr, ST->getMemOperand());
11250 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
11251 !ST->isVolatile()) ||
11252 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
11254 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
11255 getZExtValue(), SDLoc(CFP), MVT::i64);
11256 return DAG.getStore(Chain, SDLoc(N), Tmp,
11257 Ptr, ST->getMemOperand());
11260 if (!ST->isVolatile() &&
11261 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
11262 // Many FP stores are not made apparent until after legalize, e.g. for
11263 // argument passing. Since this is so common, custom legalize the
11264 // 64-bit integer store into two 32-bit stores.
11265 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
11266 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, SDLoc(CFP), MVT::i32);
11267 SDValue Hi = DAG.getConstant(Val >> 32, SDLoc(CFP), MVT::i32);
11268 if (TLI.isBigEndian()) std::swap(Lo, Hi);
11270 unsigned Alignment = ST->getAlignment();
11271 bool isVolatile = ST->isVolatile();
11272 bool isNonTemporal = ST->isNonTemporal();
11273 AAMDNodes AAInfo = ST->getAAInfo();
11277 SDValue St0 = DAG.getStore(Chain, SDLoc(ST), Lo,
11278 Ptr, ST->getPointerInfo(),
11279 isVolatile, isNonTemporal,
11280 ST->getAlignment(), AAInfo);
11281 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
11282 DAG.getConstant(4, DL, Ptr.getValueType()));
11283 Alignment = MinAlign(Alignment, 4U);
11284 SDValue St1 = DAG.getStore(Chain, SDLoc(ST), Hi,
11285 Ptr, ST->getPointerInfo().getWithOffset(4),
11286 isVolatile, isNonTemporal,
11287 Alignment, AAInfo);
11288 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
11297 // Try to infer better alignment information than the store already has.
11298 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
11299 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
11300 if (Align > ST->getAlignment()) {
11302 DAG.getTruncStore(Chain, SDLoc(N), Value,
11303 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
11304 ST->isVolatile(), ST->isNonTemporal(), Align,
11306 if (NewStore.getNode() != N)
11307 return CombineTo(ST, NewStore, true);
11312 // Try transforming a pair floating point load / store ops to integer
11313 // load / store ops.
11314 SDValue NewST = TransformFPLoadStorePair(N);
11315 if (NewST.getNode())
11318 bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA
11319 : DAG.getSubtarget().useAA();
11321 if (CombinerAAOnlyFunc.getNumOccurrences() &&
11322 CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
11325 if (UseAA && ST->isUnindexed()) {
11326 // Walk up chain skipping non-aliasing memory nodes.
11327 SDValue BetterChain = FindBetterChain(N, Chain);
11329 // If there is a better chain.
11330 if (Chain != BetterChain) {
11333 // Replace the chain to avoid dependency.
11334 if (ST->isTruncatingStore()) {
11335 ReplStore = DAG.getTruncStore(BetterChain, SDLoc(N), Value, Ptr,
11336 ST->getMemoryVT(), ST->getMemOperand());
11338 ReplStore = DAG.getStore(BetterChain, SDLoc(N), Value, Ptr,
11339 ST->getMemOperand());
11342 // Create token to keep both nodes around.
11343 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N),
11344 MVT::Other, Chain, ReplStore);
11346 // Make sure the new and old chains are cleaned up.
11347 AddToWorklist(Token.getNode());
11349 // Don't add users to work list.
11350 return CombineTo(N, Token, false);
11354 // Try transforming N to an indexed store.
11355 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
11356 return SDValue(N, 0);
11358 // FIXME: is there such a thing as a truncating indexed store?
11359 if (ST->isTruncatingStore() && ST->isUnindexed() &&
11360 Value.getValueType().isInteger()) {
11361 // See if we can simplify the input to this truncstore with knowledge that
11362 // only the low bits are being used. For example:
11363 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
11365 GetDemandedBits(Value,
11366 APInt::getLowBitsSet(
11367 Value.getValueType().getScalarType().getSizeInBits(),
11368 ST->getMemoryVT().getScalarType().getSizeInBits()));
11369 AddToWorklist(Value.getNode());
11370 if (Shorter.getNode())
11371 return DAG.getTruncStore(Chain, SDLoc(N), Shorter,
11372 Ptr, ST->getMemoryVT(), ST->getMemOperand());
11374 // Otherwise, see if we can simplify the operation with
11375 // SimplifyDemandedBits, which only works if the value has a single use.
11376 if (SimplifyDemandedBits(Value,
11377 APInt::getLowBitsSet(
11378 Value.getValueType().getScalarType().getSizeInBits(),
11379 ST->getMemoryVT().getScalarType().getSizeInBits())))
11380 return SDValue(N, 0);
11383 // If this is a load followed by a store to the same location, then the store
11385 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
11386 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
11387 ST->isUnindexed() && !ST->isVolatile() &&
11388 // There can't be any side effects between the load and store, such as
11389 // a call or store.
11390 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
11391 // The store is dead, remove it.
11396 // If this is a store followed by a store with the same value to the same
11397 // location, then the store is dead/noop.
11398 if (StoreSDNode *ST1 = dyn_cast<StoreSDNode>(Chain)) {
11399 if (ST1->getBasePtr() == Ptr && ST->getMemoryVT() == ST1->getMemoryVT() &&
11400 ST1->getValue() == Value && ST->isUnindexed() && !ST->isVolatile() &&
11401 ST1->isUnindexed() && !ST1->isVolatile()) {
11402 // The store is dead, remove it.
11407 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
11408 // truncating store. We can do this even if this is already a truncstore.
11409 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
11410 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
11411 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
11412 ST->getMemoryVT())) {
11413 return DAG.getTruncStore(Chain, SDLoc(N), Value.getOperand(0),
11414 Ptr, ST->getMemoryVT(), ST->getMemOperand());
11417 // Only perform this optimization before the types are legal, because we
11418 // don't want to perform this optimization on every DAGCombine invocation.
11420 bool EverChanged = false;
11423 // There can be multiple store sequences on the same chain.
11424 // Keep trying to merge store sequences until we are unable to do so
11425 // or until we merge the last store on the chain.
11426 bool Changed = MergeConsecutiveStores(ST);
11427 EverChanged |= Changed;
11428 if (!Changed) break;
11429 } while (ST->getOpcode() != ISD::DELETED_NODE);
11432 return SDValue(N, 0);
11435 return ReduceLoadOpStoreWidth(N);
11438 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
11439 SDValue InVec = N->getOperand(0);
11440 SDValue InVal = N->getOperand(1);
11441 SDValue EltNo = N->getOperand(2);
11444 // If the inserted element is an UNDEF, just use the input vector.
11445 if (InVal.getOpcode() == ISD::UNDEF)
11448 EVT VT = InVec.getValueType();
11450 // If we can't generate a legal BUILD_VECTOR, exit
11451 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
11454 // Check that we know which element is being inserted
11455 if (!isa<ConstantSDNode>(EltNo))
11457 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
11459 // Canonicalize insert_vector_elt dag nodes.
11461 // (insert_vector_elt (insert_vector_elt A, Idx0), Idx1)
11462 // -> (insert_vector_elt (insert_vector_elt A, Idx1), Idx0)
11464 // Do this only if the child insert_vector node has one use; also
11465 // do this only if indices are both constants and Idx1 < Idx0.
11466 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse()
11467 && isa<ConstantSDNode>(InVec.getOperand(2))) {
11468 unsigned OtherElt =
11469 cast<ConstantSDNode>(InVec.getOperand(2))->getZExtValue();
11470 if (Elt < OtherElt) {
11472 SDValue NewOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), VT,
11473 InVec.getOperand(0), InVal, EltNo);
11474 AddToWorklist(NewOp.getNode());
11475 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(InVec.getNode()),
11476 VT, NewOp, InVec.getOperand(1), InVec.getOperand(2));
11480 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
11481 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
11482 // vector elements.
11483 SmallVector<SDValue, 8> Ops;
11484 // Do not combine these two vectors if the output vector will not replace
11485 // the input vector.
11486 if (InVec.getOpcode() == ISD::BUILD_VECTOR && InVec.hasOneUse()) {
11487 Ops.append(InVec.getNode()->op_begin(),
11488 InVec.getNode()->op_end());
11489 } else if (InVec.getOpcode() == ISD::UNDEF) {
11490 unsigned NElts = VT.getVectorNumElements();
11491 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
11496 // Insert the element
11497 if (Elt < Ops.size()) {
11498 // All the operands of BUILD_VECTOR must have the same type;
11499 // we enforce that here.
11500 EVT OpVT = Ops[0].getValueType();
11501 if (InVal.getValueType() != OpVT)
11502 InVal = OpVT.bitsGT(InVal.getValueType()) ?
11503 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
11504 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
11508 // Return the new vector
11509 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
11512 SDValue DAGCombiner::ReplaceExtractVectorEltOfLoadWithNarrowedLoad(
11513 SDNode *EVE, EVT InVecVT, SDValue EltNo, LoadSDNode *OriginalLoad) {
11514 EVT ResultVT = EVE->getValueType(0);
11515 EVT VecEltVT = InVecVT.getVectorElementType();
11516 unsigned Align = OriginalLoad->getAlignment();
11517 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
11518 VecEltVT.getTypeForEVT(*DAG.getContext()));
11520 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VecEltVT))
11525 SDValue NewPtr = OriginalLoad->getBasePtr();
11527 EVT PtrType = NewPtr.getValueType();
11528 MachinePointerInfo MPI;
11530 if (auto *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo)) {
11531 int Elt = ConstEltNo->getZExtValue();
11532 unsigned PtrOff = VecEltVT.getSizeInBits() * Elt / 8;
11533 Offset = DAG.getConstant(PtrOff, DL, PtrType);
11534 MPI = OriginalLoad->getPointerInfo().getWithOffset(PtrOff);
11536 Offset = DAG.getZExtOrTrunc(EltNo, DL, PtrType);
11537 Offset = DAG.getNode(
11538 ISD::MUL, DL, PtrType, Offset,
11539 DAG.getConstant(VecEltVT.getStoreSize(), DL, PtrType));
11540 MPI = OriginalLoad->getPointerInfo();
11542 NewPtr = DAG.getNode(ISD::ADD, DL, PtrType, NewPtr, Offset);
11544 // The replacement we need to do here is a little tricky: we need to
11545 // replace an extractelement of a load with a load.
11546 // Use ReplaceAllUsesOfValuesWith to do the replacement.
11547 // Note that this replacement assumes that the extractvalue is the only
11548 // use of the load; that's okay because we don't want to perform this
11549 // transformation in other cases anyway.
11552 if (ResultVT.bitsGT(VecEltVT)) {
11553 // If the result type of vextract is wider than the load, then issue an
11554 // extending load instead.
11555 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, ResultVT,
11559 Load = DAG.getExtLoad(
11560 ExtType, SDLoc(EVE), ResultVT, OriginalLoad->getChain(), NewPtr, MPI,
11561 VecEltVT, OriginalLoad->isVolatile(), OriginalLoad->isNonTemporal(),
11562 OriginalLoad->isInvariant(), Align, OriginalLoad->getAAInfo());
11563 Chain = Load.getValue(1);
11565 Load = DAG.getLoad(
11566 VecEltVT, SDLoc(EVE), OriginalLoad->getChain(), NewPtr, MPI,
11567 OriginalLoad->isVolatile(), OriginalLoad->isNonTemporal(),
11568 OriginalLoad->isInvariant(), Align, OriginalLoad->getAAInfo());
11569 Chain = Load.getValue(1);
11570 if (ResultVT.bitsLT(VecEltVT))
11571 Load = DAG.getNode(ISD::TRUNCATE, SDLoc(EVE), ResultVT, Load);
11573 Load = DAG.getNode(ISD::BITCAST, SDLoc(EVE), ResultVT, Load);
11575 WorklistRemover DeadNodes(*this);
11576 SDValue From[] = { SDValue(EVE, 0), SDValue(OriginalLoad, 1) };
11577 SDValue To[] = { Load, Chain };
11578 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
11579 // Since we're explicitly calling ReplaceAllUses, add the new node to the
11580 // worklist explicitly as well.
11581 AddToWorklist(Load.getNode());
11582 AddUsersToWorklist(Load.getNode()); // Add users too
11583 // Make sure to revisit this node to clean it up; it will usually be dead.
11584 AddToWorklist(EVE);
11586 return SDValue(EVE, 0);
11589 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
11590 // (vextract (scalar_to_vector val, 0) -> val
11591 SDValue InVec = N->getOperand(0);
11592 EVT VT = InVec.getValueType();
11593 EVT NVT = N->getValueType(0);
11595 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
11596 // Check if the result type doesn't match the inserted element type. A
11597 // SCALAR_TO_VECTOR may truncate the inserted element and the
11598 // EXTRACT_VECTOR_ELT may widen the extracted vector.
11599 SDValue InOp = InVec.getOperand(0);
11600 if (InOp.getValueType() != NVT) {
11601 assert(InOp.getValueType().isInteger() && NVT.isInteger());
11602 return DAG.getSExtOrTrunc(InOp, SDLoc(InVec), NVT);
11607 SDValue EltNo = N->getOperand(1);
11608 bool ConstEltNo = isa<ConstantSDNode>(EltNo);
11610 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
11611 // We only perform this optimization before the op legalization phase because
11612 // we may introduce new vector instructions which are not backed by TD
11613 // patterns. For example on AVX, extracting elements from a wide vector
11614 // without using extract_subvector. However, if we can find an underlying
11615 // scalar value, then we can always use that.
11616 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
11618 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
11619 int NumElem = VT.getVectorNumElements();
11620 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
11621 // Find the new index to extract from.
11622 int OrigElt = SVOp->getMaskElt(Elt);
11624 // Extracting an undef index is undef.
11626 return DAG.getUNDEF(NVT);
11628 // Select the right vector half to extract from.
11630 if (OrigElt < NumElem) {
11631 SVInVec = InVec->getOperand(0);
11633 SVInVec = InVec->getOperand(1);
11634 OrigElt -= NumElem;
11637 if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) {
11638 SDValue InOp = SVInVec.getOperand(OrigElt);
11639 if (InOp.getValueType() != NVT) {
11640 assert(InOp.getValueType().isInteger() && NVT.isInteger());
11641 InOp = DAG.getSExtOrTrunc(InOp, SDLoc(SVInVec), NVT);
11647 // FIXME: We should handle recursing on other vector shuffles and
11648 // scalar_to_vector here as well.
11650 if (!LegalOperations) {
11651 EVT IndexTy = TLI.getVectorIdxTy();
11652 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), NVT, SVInVec,
11653 DAG.getConstant(OrigElt, SDLoc(SVOp), IndexTy));
11657 bool BCNumEltsChanged = false;
11658 EVT ExtVT = VT.getVectorElementType();
11661 // If the result of load has to be truncated, then it's not necessarily
11663 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT))
11666 if (InVec.getOpcode() == ISD::BITCAST) {
11667 // Don't duplicate a load with other uses.
11668 if (!InVec.hasOneUse())
11671 EVT BCVT = InVec.getOperand(0).getValueType();
11672 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
11674 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
11675 BCNumEltsChanged = true;
11676 InVec = InVec.getOperand(0);
11677 ExtVT = BCVT.getVectorElementType();
11680 // (vextract (vN[if]M load $addr), i) -> ([if]M load $addr + i * size)
11681 if (!LegalOperations && !ConstEltNo && InVec.hasOneUse() &&
11682 ISD::isNormalLoad(InVec.getNode()) &&
11683 !N->getOperand(1)->hasPredecessor(InVec.getNode())) {
11684 SDValue Index = N->getOperand(1);
11685 if (LoadSDNode *OrigLoad = dyn_cast<LoadSDNode>(InVec))
11686 return ReplaceExtractVectorEltOfLoadWithNarrowedLoad(N, VT, Index,
11690 // Perform only after legalization to ensure build_vector / vector_shuffle
11691 // optimizations have already been done.
11692 if (!LegalOperations) return SDValue();
11694 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
11695 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
11696 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
11699 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
11701 LoadSDNode *LN0 = nullptr;
11702 const ShuffleVectorSDNode *SVN = nullptr;
11703 if (ISD::isNormalLoad(InVec.getNode())) {
11704 LN0 = cast<LoadSDNode>(InVec);
11705 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11706 InVec.getOperand(0).getValueType() == ExtVT &&
11707 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
11708 // Don't duplicate a load with other uses.
11709 if (!InVec.hasOneUse())
11712 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
11713 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
11714 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
11716 // (load $addr+1*size)
11718 // Don't duplicate a load with other uses.
11719 if (!InVec.hasOneUse())
11722 // If the bit convert changed the number of elements, it is unsafe
11723 // to examine the mask.
11724 if (BCNumEltsChanged)
11727 // Select the input vector, guarding against out of range extract vector.
11728 unsigned NumElems = VT.getVectorNumElements();
11729 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
11730 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
11732 if (InVec.getOpcode() == ISD::BITCAST) {
11733 // Don't duplicate a load with other uses.
11734 if (!InVec.hasOneUse())
11737 InVec = InVec.getOperand(0);
11739 if (ISD::isNormalLoad(InVec.getNode())) {
11740 LN0 = cast<LoadSDNode>(InVec);
11741 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
11742 EltNo = DAG.getConstant(Elt, SDLoc(EltNo), EltNo.getValueType());
11746 // Make sure we found a non-volatile load and the extractelement is
11748 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
11751 // If Idx was -1 above, Elt is going to be -1, so just return undef.
11753 return DAG.getUNDEF(LVT);
11755 return ReplaceExtractVectorEltOfLoadWithNarrowedLoad(N, VT, EltNo, LN0);
11761 // Simplify (build_vec (ext )) to (bitcast (build_vec ))
11762 SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) {
11763 // We perform this optimization post type-legalization because
11764 // the type-legalizer often scalarizes integer-promoted vectors.
11765 // Performing this optimization before may create bit-casts which
11766 // will be type-legalized to complex code sequences.
11767 // We perform this optimization only before the operation legalizer because we
11768 // may introduce illegal operations.
11769 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes)
11772 unsigned NumInScalars = N->getNumOperands();
11774 EVT VT = N->getValueType(0);
11776 // Check to see if this is a BUILD_VECTOR of a bunch of values
11777 // which come from any_extend or zero_extend nodes. If so, we can create
11778 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR
11779 // optimizations. We do not handle sign-extend because we can't fill the sign
11781 EVT SourceType = MVT::Other;
11782 bool AllAnyExt = true;
11784 for (unsigned i = 0; i != NumInScalars; ++i) {
11785 SDValue In = N->getOperand(i);
11786 // Ignore undef inputs.
11787 if (In.getOpcode() == ISD::UNDEF) continue;
11789 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
11790 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
11792 // Abort if the element is not an extension.
11793 if (!ZeroExt && !AnyExt) {
11794 SourceType = MVT::Other;
11798 // The input is a ZeroExt or AnyExt. Check the original type.
11799 EVT InTy = In.getOperand(0).getValueType();
11801 // Check that all of the widened source types are the same.
11802 if (SourceType == MVT::Other)
11805 else if (InTy != SourceType) {
11806 // Multiple income types. Abort.
11807 SourceType = MVT::Other;
11811 // Check if all of the extends are ANY_EXTENDs.
11812 AllAnyExt &= AnyExt;
11815 // In order to have valid types, all of the inputs must be extended from the
11816 // same source type and all of the inputs must be any or zero extend.
11817 // Scalar sizes must be a power of two.
11818 EVT OutScalarTy = VT.getScalarType();
11819 bool ValidTypes = SourceType != MVT::Other &&
11820 isPowerOf2_32(OutScalarTy.getSizeInBits()) &&
11821 isPowerOf2_32(SourceType.getSizeInBits());
11823 // Create a new simpler BUILD_VECTOR sequence which other optimizations can
11824 // turn into a single shuffle instruction.
11828 bool isLE = TLI.isLittleEndian();
11829 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits();
11830 assert(ElemRatio > 1 && "Invalid element size ratio");
11831 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType):
11832 DAG.getConstant(0, SDLoc(N), SourceType);
11834 unsigned NewBVElems = ElemRatio * VT.getVectorNumElements();
11835 SmallVector<SDValue, 8> Ops(NewBVElems, Filler);
11837 // Populate the new build_vector
11838 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
11839 SDValue Cast = N->getOperand(i);
11840 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
11841 Cast.getOpcode() == ISD::ZERO_EXTEND ||
11842 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
11844 if (Cast.getOpcode() == ISD::UNDEF)
11845 In = DAG.getUNDEF(SourceType);
11847 In = Cast->getOperand(0);
11848 unsigned Index = isLE ? (i * ElemRatio) :
11849 (i * ElemRatio + (ElemRatio - 1));
11851 assert(Index < Ops.size() && "Invalid index");
11855 // The type of the new BUILD_VECTOR node.
11856 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems);
11857 assert(VecVT.getSizeInBits() == VT.getSizeInBits() &&
11858 "Invalid vector size");
11859 // Check if the new vector type is legal.
11860 if (!isTypeLegal(VecVT)) return SDValue();
11862 // Make the new BUILD_VECTOR.
11863 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
11865 // The new BUILD_VECTOR node has the potential to be further optimized.
11866 AddToWorklist(BV.getNode());
11867 // Bitcast to the desired type.
11868 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
11871 SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) {
11872 EVT VT = N->getValueType(0);
11874 unsigned NumInScalars = N->getNumOperands();
11877 EVT SrcVT = MVT::Other;
11878 unsigned Opcode = ISD::DELETED_NODE;
11879 unsigned NumDefs = 0;
11881 for (unsigned i = 0; i != NumInScalars; ++i) {
11882 SDValue In = N->getOperand(i);
11883 unsigned Opc = In.getOpcode();
11885 if (Opc == ISD::UNDEF)
11888 // If all scalar values are floats and converted from integers.
11889 if (Opcode == ISD::DELETED_NODE &&
11890 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) {
11897 EVT InVT = In.getOperand(0).getValueType();
11899 // If all scalar values are typed differently, bail out. It's chosen to
11900 // simplify BUILD_VECTOR of integer types.
11901 if (SrcVT == MVT::Other)
11908 // If the vector has just one element defined, it's not worth to fold it into
11909 // a vectorized one.
11913 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP)
11914 && "Should only handle conversion from integer to float.");
11915 assert(SrcVT != MVT::Other && "Cannot determine source type!");
11917 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars);
11919 if (!TLI.isOperationLegalOrCustom(Opcode, NVT))
11922 // Just because the floating-point vector type is legal does not necessarily
11923 // mean that the corresponding integer vector type is.
11924 if (!isTypeLegal(NVT))
11927 SmallVector<SDValue, 8> Opnds;
11928 for (unsigned i = 0; i != NumInScalars; ++i) {
11929 SDValue In = N->getOperand(i);
11931 if (In.getOpcode() == ISD::UNDEF)
11932 Opnds.push_back(DAG.getUNDEF(SrcVT));
11934 Opnds.push_back(In.getOperand(0));
11936 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Opnds);
11937 AddToWorklist(BV.getNode());
11939 return DAG.getNode(Opcode, dl, VT, BV);
11942 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
11943 unsigned NumInScalars = N->getNumOperands();
11945 EVT VT = N->getValueType(0);
11947 // A vector built entirely of undefs is undef.
11948 if (ISD::allOperandsUndef(N))
11949 return DAG.getUNDEF(VT);
11951 if (SDValue V = reduceBuildVecExtToExtBuildVec(N))
11954 if (SDValue V = reduceBuildVecConvertToConvertBuildVec(N))
11957 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
11958 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
11959 // at most two distinct vectors, turn this into a shuffle node.
11961 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes.
11962 if (!isTypeLegal(VT))
11965 // May only combine to shuffle after legalize if shuffle is legal.
11966 if (LegalOperations && !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, VT))
11969 SDValue VecIn1, VecIn2;
11970 bool UsesZeroVector = false;
11971 for (unsigned i = 0; i != NumInScalars; ++i) {
11972 SDValue Op = N->getOperand(i);
11973 // Ignore undef inputs.
11974 if (Op.getOpcode() == ISD::UNDEF) continue;
11976 // See if we can combine this build_vector into a blend with a zero vector.
11977 if (!VecIn2.getNode() && (isNullConstant(Op) || isNullFPConstant(Op))) {
11978 UsesZeroVector = true;
11982 // If this input is something other than a EXTRACT_VECTOR_ELT with a
11983 // constant index, bail out.
11984 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
11985 !isa<ConstantSDNode>(Op.getOperand(1))) {
11986 VecIn1 = VecIn2 = SDValue(nullptr, 0);
11990 // We allow up to two distinct input vectors.
11991 SDValue ExtractedFromVec = Op.getOperand(0);
11992 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
11995 if (!VecIn1.getNode()) {
11996 VecIn1 = ExtractedFromVec;
11997 } else if (!VecIn2.getNode() && !UsesZeroVector) {
11998 VecIn2 = ExtractedFromVec;
12000 // Too many inputs.
12001 VecIn1 = VecIn2 = SDValue(nullptr, 0);
12006 // If everything is good, we can make a shuffle operation.
12007 if (VecIn1.getNode()) {
12008 unsigned InNumElements = VecIn1.getValueType().getVectorNumElements();
12009 SmallVector<int, 8> Mask;
12010 for (unsigned i = 0; i != NumInScalars; ++i) {
12011 unsigned Opcode = N->getOperand(i).getOpcode();
12012 if (Opcode == ISD::UNDEF) {
12013 Mask.push_back(-1);
12017 // Operands can also be zero.
12018 if (Opcode != ISD::EXTRACT_VECTOR_ELT) {
12019 assert(UsesZeroVector &&
12020 (Opcode == ISD::Constant || Opcode == ISD::ConstantFP) &&
12021 "Unexpected node found!");
12022 Mask.push_back(NumInScalars+i);
12026 // If extracting from the first vector, just use the index directly.
12027 SDValue Extract = N->getOperand(i);
12028 SDValue ExtVal = Extract.getOperand(1);
12029 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
12030 if (Extract.getOperand(0) == VecIn1) {
12031 Mask.push_back(ExtIndex);
12035 // Otherwise, use InIdx + InputVecSize
12036 Mask.push_back(InNumElements + ExtIndex);
12039 // Avoid introducing illegal shuffles with zero.
12040 if (UsesZeroVector && !TLI.isVectorClearMaskLegal(Mask, VT))
12043 // We can't generate a shuffle node with mismatched input and output types.
12044 // Attempt to transform a single input vector to the correct type.
12045 if ((VT != VecIn1.getValueType())) {
12046 // If the input vector type has a different base type to the output
12047 // vector type, bail out.
12048 EVT VTElemType = VT.getVectorElementType();
12049 if ((VecIn1.getValueType().getVectorElementType() != VTElemType) ||
12050 (VecIn2.getNode() &&
12051 (VecIn2.getValueType().getVectorElementType() != VTElemType)))
12054 // If the input vector is too small, widen it.
12055 // We only support widening of vectors which are half the size of the
12056 // output registers. For example XMM->YMM widening on X86 with AVX.
12057 EVT VecInT = VecIn1.getValueType();
12058 if (VecInT.getSizeInBits() * 2 == VT.getSizeInBits()) {
12059 // If we only have one small input, widen it by adding undef values.
12060 if (!VecIn2.getNode())
12061 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, VecIn1,
12062 DAG.getUNDEF(VecIn1.getValueType()));
12063 else if (VecIn1.getValueType() == VecIn2.getValueType()) {
12064 // If we have two small inputs of the same type, try to concat them.
12065 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, VecIn1, VecIn2);
12066 VecIn2 = SDValue(nullptr, 0);
12069 } else if (VecInT.getSizeInBits() == VT.getSizeInBits() * 2) {
12070 // If the input vector is too large, try to split it.
12071 // We don't support having two input vectors that are too large.
12072 // If the zero vector was used, we can not split the vector,
12073 // since we'd need 3 inputs.
12074 if (UsesZeroVector || VecIn2.getNode())
12077 if (!TLI.isExtractSubvectorCheap(VT, VT.getVectorNumElements()))
12080 // Try to replace VecIn1 with two extract_subvectors
12081 // No need to update the masks, they should still be correct.
12082 VecIn2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, VecIn1,
12083 DAG.getConstant(VT.getVectorNumElements(), dl, TLI.getVectorIdxTy()));
12084 VecIn1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, VecIn1,
12085 DAG.getConstant(0, dl, TLI.getVectorIdxTy()));
12090 if (UsesZeroVector)
12091 VecIn2 = VT.isInteger() ? DAG.getConstant(0, dl, VT) :
12092 DAG.getConstantFP(0.0, dl, VT);
12094 // If VecIn2 is unused then change it to undef.
12095 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
12097 // Check that we were able to transform all incoming values to the same
12099 if (VecIn2.getValueType() != VecIn1.getValueType() ||
12100 VecIn1.getValueType() != VT)
12103 // Return the new VECTOR_SHUFFLE node.
12107 return DAG.getVectorShuffle(VT, dl, Ops[0], Ops[1], &Mask[0]);
12113 static SDValue combineConcatVectorOfScalars(SDNode *N, SelectionDAG &DAG) {
12114 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12115 EVT OpVT = N->getOperand(0).getValueType();
12117 // If the operands are legal vectors, leave them alone.
12118 if (TLI.isTypeLegal(OpVT))
12122 EVT VT = N->getValueType(0);
12123 SmallVector<SDValue, 8> Ops;
12125 EVT SVT = EVT::getIntegerVT(*DAG.getContext(), OpVT.getSizeInBits());
12126 SDValue ScalarUndef = DAG.getNode(ISD::UNDEF, DL, SVT);
12128 // Keep track of what we encounter.
12129 bool AnyInteger = false;
12130 bool AnyFP = false;
12131 for (const SDValue &Op : N->ops()) {
12132 if (ISD::BITCAST == Op.getOpcode() &&
12133 !Op.getOperand(0).getValueType().isVector())
12134 Ops.push_back(Op.getOperand(0));
12135 else if (ISD::UNDEF == Op.getOpcode())
12136 Ops.push_back(ScalarUndef);
12140 // Note whether we encounter an integer or floating point scalar.
12141 // If it's neither, bail out, it could be something weird like x86mmx.
12142 EVT LastOpVT = Ops.back().getValueType();
12143 if (LastOpVT.isFloatingPoint())
12145 else if (LastOpVT.isInteger())
12151 // If any of the operands is a floating point scalar bitcast to a vector,
12152 // use floating point types throughout, and bitcast everything.
12153 // Replace UNDEFs by another scalar UNDEF node, of the final desired type.
12155 SVT = EVT::getFloatingPointVT(OpVT.getSizeInBits());
12156 ScalarUndef = DAG.getNode(ISD::UNDEF, DL, SVT);
12158 for (SDValue &Op : Ops) {
12159 if (Op.getValueType() == SVT)
12161 if (Op.getOpcode() == ISD::UNDEF)
12164 Op = DAG.getNode(ISD::BITCAST, DL, SVT, Op);
12169 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SVT,
12170 VT.getSizeInBits() / SVT.getSizeInBits());
12171 return DAG.getNode(ISD::BITCAST, DL, VT,
12172 DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, Ops));
12175 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
12176 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
12177 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
12178 // inputs come from at most two distinct vectors, turn this into a shuffle
12181 // If we only have one input vector, we don't need to do any concatenation.
12182 if (N->getNumOperands() == 1)
12183 return N->getOperand(0);
12185 // Check if all of the operands are undefs.
12186 EVT VT = N->getValueType(0);
12187 if (ISD::allOperandsUndef(N))
12188 return DAG.getUNDEF(VT);
12190 // Optimize concat_vectors where all but the first of the vectors are undef.
12191 if (std::all_of(std::next(N->op_begin()), N->op_end(), [](const SDValue &Op) {
12192 return Op.getOpcode() == ISD::UNDEF;
12194 SDValue In = N->getOperand(0);
12195 assert(In.getValueType().isVector() && "Must concat vectors");
12197 // Transform: concat_vectors(scalar, undef) -> scalar_to_vector(sclr).
12198 if (In->getOpcode() == ISD::BITCAST &&
12199 !In->getOperand(0)->getValueType(0).isVector()) {
12200 SDValue Scalar = In->getOperand(0);
12202 // If the bitcast type isn't legal, it might be a trunc of a legal type;
12203 // look through the trunc so we can still do the transform:
12204 // concat_vectors(trunc(scalar), undef) -> scalar_to_vector(scalar)
12205 if (Scalar->getOpcode() == ISD::TRUNCATE &&
12206 !TLI.isTypeLegal(Scalar.getValueType()) &&
12207 TLI.isTypeLegal(Scalar->getOperand(0).getValueType()))
12208 Scalar = Scalar->getOperand(0);
12210 EVT SclTy = Scalar->getValueType(0);
12212 if (!SclTy.isFloatingPoint() && !SclTy.isInteger())
12215 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SclTy,
12216 VT.getSizeInBits() / SclTy.getSizeInBits());
12217 if (!TLI.isTypeLegal(NVT) || !TLI.isTypeLegal(Scalar.getValueType()))
12220 SDLoc dl = SDLoc(N);
12221 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NVT, Scalar);
12222 return DAG.getNode(ISD::BITCAST, dl, VT, Res);
12226 // Fold any combination of BUILD_VECTOR or UNDEF nodes into one BUILD_VECTOR.
12227 // We have already tested above for an UNDEF only concatenation.
12228 // fold (concat_vectors (BUILD_VECTOR A, B, ...), (BUILD_VECTOR C, D, ...))
12229 // -> (BUILD_VECTOR A, B, ..., C, D, ...)
12230 auto IsBuildVectorOrUndef = [](const SDValue &Op) {
12231 return ISD::UNDEF == Op.getOpcode() || ISD::BUILD_VECTOR == Op.getOpcode();
12233 bool AllBuildVectorsOrUndefs =
12234 std::all_of(N->op_begin(), N->op_end(), IsBuildVectorOrUndef);
12235 if (AllBuildVectorsOrUndefs) {
12236 SmallVector<SDValue, 8> Opnds;
12237 EVT SVT = VT.getScalarType();
12240 if (!SVT.isFloatingPoint()) {
12241 // If BUILD_VECTOR are from built from integer, they may have different
12242 // operand types. Get the smallest type and truncate all operands to it.
12243 bool FoundMinVT = false;
12244 for (const SDValue &Op : N->ops())
12245 if (ISD::BUILD_VECTOR == Op.getOpcode()) {
12246 EVT OpSVT = Op.getOperand(0)->getValueType(0);
12247 MinVT = (!FoundMinVT || OpSVT.bitsLE(MinVT)) ? OpSVT : MinVT;
12250 assert(FoundMinVT && "Concat vector type mismatch");
12253 for (const SDValue &Op : N->ops()) {
12254 EVT OpVT = Op.getValueType();
12255 unsigned NumElts = OpVT.getVectorNumElements();
12257 if (ISD::UNDEF == Op.getOpcode())
12258 Opnds.append(NumElts, DAG.getUNDEF(MinVT));
12260 if (ISD::BUILD_VECTOR == Op.getOpcode()) {
12261 if (SVT.isFloatingPoint()) {
12262 assert(SVT == OpVT.getScalarType() && "Concat vector type mismatch");
12263 Opnds.append(Op->op_begin(), Op->op_begin() + NumElts);
12265 for (unsigned i = 0; i != NumElts; ++i)
12267 DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinVT, Op.getOperand(i)));
12272 assert(VT.getVectorNumElements() == Opnds.size() &&
12273 "Concat vector type mismatch");
12274 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Opnds);
12277 // Fold CONCAT_VECTORS of only bitcast scalars (or undef) to BUILD_VECTOR.
12278 if (SDValue V = combineConcatVectorOfScalars(N, DAG))
12281 // Type legalization of vectors and DAG canonicalization of SHUFFLE_VECTOR
12282 // nodes often generate nop CONCAT_VECTOR nodes.
12283 // Scan the CONCAT_VECTOR operands and look for a CONCAT operations that
12284 // place the incoming vectors at the exact same location.
12285 SDValue SingleSource = SDValue();
12286 unsigned PartNumElem = N->getOperand(0).getValueType().getVectorNumElements();
12288 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
12289 SDValue Op = N->getOperand(i);
12291 if (Op.getOpcode() == ISD::UNDEF)
12294 // Check if this is the identity extract:
12295 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR)
12298 // Find the single incoming vector for the extract_subvector.
12299 if (SingleSource.getNode()) {
12300 if (Op.getOperand(0) != SingleSource)
12303 SingleSource = Op.getOperand(0);
12305 // Check the source type is the same as the type of the result.
12306 // If not, this concat may extend the vector, so we can not
12307 // optimize it away.
12308 if (SingleSource.getValueType() != N->getValueType(0))
12312 unsigned IdentityIndex = i * PartNumElem;
12313 ConstantSDNode *CS = dyn_cast<ConstantSDNode>(Op.getOperand(1));
12314 // The extract index must be constant.
12318 // Check that we are reading from the identity index.
12319 if (CS->getZExtValue() != IdentityIndex)
12323 if (SingleSource.getNode())
12324 return SingleSource;
12329 SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
12330 EVT NVT = N->getValueType(0);
12331 SDValue V = N->getOperand(0);
12333 if (V->getOpcode() == ISD::CONCAT_VECTORS) {
12335 // (extract_subvec (concat V1, V2, ...), i)
12338 // Only operand 0 is checked as 'concat' assumes all inputs of the same
12340 if (V->getOperand(0).getValueType() != NVT)
12342 unsigned Idx = N->getConstantOperandVal(1);
12343 unsigned NumElems = NVT.getVectorNumElements();
12344 assert((Idx % NumElems) == 0 &&
12345 "IDX in concat is not a multiple of the result vector length.");
12346 return V->getOperand(Idx / NumElems);
12350 if (V->getOpcode() == ISD::BITCAST)
12351 V = V.getOperand(0);
12353 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
12355 // Handle only simple case where vector being inserted and vector
12356 // being extracted are of same type, and are half size of larger vectors.
12357 EVT BigVT = V->getOperand(0).getValueType();
12358 EVT SmallVT = V->getOperand(1).getValueType();
12359 if (!NVT.bitsEq(SmallVT) || NVT.getSizeInBits()*2 != BigVT.getSizeInBits())
12362 // Only handle cases where both indexes are constants with the same type.
12363 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
12364 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2));
12366 if (InsIdx && ExtIdx &&
12367 InsIdx->getValueType(0).getSizeInBits() <= 64 &&
12368 ExtIdx->getValueType(0).getSizeInBits() <= 64) {
12370 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx)
12372 // indices are equal or bit offsets are equal => V1
12373 // otherwise => (extract_subvec V1, ExtIdx)
12374 if (InsIdx->getZExtValue() * SmallVT.getScalarType().getSizeInBits() ==
12375 ExtIdx->getZExtValue() * NVT.getScalarType().getSizeInBits())
12376 return DAG.getNode(ISD::BITCAST, dl, NVT, V->getOperand(1));
12377 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT,
12378 DAG.getNode(ISD::BITCAST, dl,
12379 N->getOperand(0).getValueType(),
12380 V->getOperand(0)), N->getOperand(1));
12387 static SDValue simplifyShuffleOperandRecursively(SmallBitVector &UsedElements,
12388 SDValue V, SelectionDAG &DAG) {
12390 EVT VT = V.getValueType();
12392 switch (V.getOpcode()) {
12396 case ISD::CONCAT_VECTORS: {
12397 EVT OpVT = V->getOperand(0).getValueType();
12398 int OpSize = OpVT.getVectorNumElements();
12399 SmallBitVector OpUsedElements(OpSize, false);
12400 bool FoundSimplification = false;
12401 SmallVector<SDValue, 4> NewOps;
12402 NewOps.reserve(V->getNumOperands());
12403 for (int i = 0, NumOps = V->getNumOperands(); i < NumOps; ++i) {
12404 SDValue Op = V->getOperand(i);
12405 bool OpUsed = false;
12406 for (int j = 0; j < OpSize; ++j)
12407 if (UsedElements[i * OpSize + j]) {
12408 OpUsedElements[j] = true;
12412 OpUsed ? simplifyShuffleOperandRecursively(OpUsedElements, Op, DAG)
12413 : DAG.getUNDEF(OpVT));
12414 FoundSimplification |= Op == NewOps.back();
12415 OpUsedElements.reset();
12417 if (FoundSimplification)
12418 V = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, NewOps);
12422 case ISD::INSERT_SUBVECTOR: {
12423 SDValue BaseV = V->getOperand(0);
12424 SDValue SubV = V->getOperand(1);
12425 auto *IdxN = dyn_cast<ConstantSDNode>(V->getOperand(2));
12429 int SubSize = SubV.getValueType().getVectorNumElements();
12430 int Idx = IdxN->getZExtValue();
12431 bool SubVectorUsed = false;
12432 SmallBitVector SubUsedElements(SubSize, false);
12433 for (int i = 0; i < SubSize; ++i)
12434 if (UsedElements[i + Idx]) {
12435 SubVectorUsed = true;
12436 SubUsedElements[i] = true;
12437 UsedElements[i + Idx] = false;
12440 // Now recurse on both the base and sub vectors.
12441 SDValue SimplifiedSubV =
12443 ? simplifyShuffleOperandRecursively(SubUsedElements, SubV, DAG)
12444 : DAG.getUNDEF(SubV.getValueType());
12445 SDValue SimplifiedBaseV = simplifyShuffleOperandRecursively(UsedElements, BaseV, DAG);
12446 if (SimplifiedSubV != SubV || SimplifiedBaseV != BaseV)
12447 V = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT,
12448 SimplifiedBaseV, SimplifiedSubV, V->getOperand(2));
12454 static SDValue simplifyShuffleOperands(ShuffleVectorSDNode *SVN, SDValue N0,
12455 SDValue N1, SelectionDAG &DAG) {
12456 EVT VT = SVN->getValueType(0);
12457 int NumElts = VT.getVectorNumElements();
12458 SmallBitVector N0UsedElements(NumElts, false), N1UsedElements(NumElts, false);
12459 for (int M : SVN->getMask())
12460 if (M >= 0 && M < NumElts)
12461 N0UsedElements[M] = true;
12462 else if (M >= NumElts)
12463 N1UsedElements[M - NumElts] = true;
12465 SDValue S0 = simplifyShuffleOperandRecursively(N0UsedElements, N0, DAG);
12466 SDValue S1 = simplifyShuffleOperandRecursively(N1UsedElements, N1, DAG);
12467 if (S0 == N0 && S1 == N1)
12470 return DAG.getVectorShuffle(VT, SDLoc(SVN), S0, S1, SVN->getMask());
12473 // Tries to turn a shuffle of two CONCAT_VECTORS into a single concat,
12474 // or turn a shuffle of a single concat into simpler shuffle then concat.
12475 static SDValue partitionShuffleOfConcats(SDNode *N, SelectionDAG &DAG) {
12476 EVT VT = N->getValueType(0);
12477 unsigned NumElts = VT.getVectorNumElements();
12479 SDValue N0 = N->getOperand(0);
12480 SDValue N1 = N->getOperand(1);
12481 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
12483 SmallVector<SDValue, 4> Ops;
12484 EVT ConcatVT = N0.getOperand(0).getValueType();
12485 unsigned NumElemsPerConcat = ConcatVT.getVectorNumElements();
12486 unsigned NumConcats = NumElts / NumElemsPerConcat;
12488 // Special case: shuffle(concat(A,B)) can be more efficiently represented
12489 // as concat(shuffle(A,B),UNDEF) if the shuffle doesn't set any of the high
12490 // half vector elements.
12491 if (NumElemsPerConcat * 2 == NumElts && N1.getOpcode() == ISD::UNDEF &&
12492 std::all_of(SVN->getMask().begin() + NumElemsPerConcat,
12493 SVN->getMask().end(), [](int i) { return i == -1; })) {
12494 N0 = DAG.getVectorShuffle(ConcatVT, SDLoc(N), N0.getOperand(0), N0.getOperand(1),
12495 ArrayRef<int>(SVN->getMask().begin(), NumElemsPerConcat));
12496 N1 = DAG.getUNDEF(ConcatVT);
12497 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, N0, N1);
12500 // Look at every vector that's inserted. We're looking for exact
12501 // subvector-sized copies from a concatenated vector
12502 for (unsigned I = 0; I != NumConcats; ++I) {
12503 // Make sure we're dealing with a copy.
12504 unsigned Begin = I * NumElemsPerConcat;
12505 bool AllUndef = true, NoUndef = true;
12506 for (unsigned J = Begin; J != Begin + NumElemsPerConcat; ++J) {
12507 if (SVN->getMaskElt(J) >= 0)
12514 if (SVN->getMaskElt(Begin) % NumElemsPerConcat != 0)
12517 for (unsigned J = 1; J != NumElemsPerConcat; ++J)
12518 if (SVN->getMaskElt(Begin + J - 1) + 1 != SVN->getMaskElt(Begin + J))
12521 unsigned FirstElt = SVN->getMaskElt(Begin) / NumElemsPerConcat;
12522 if (FirstElt < N0.getNumOperands())
12523 Ops.push_back(N0.getOperand(FirstElt));
12525 Ops.push_back(N1.getOperand(FirstElt - N0.getNumOperands()));
12527 } else if (AllUndef) {
12528 Ops.push_back(DAG.getUNDEF(N0.getOperand(0).getValueType()));
12529 } else { // Mixed with general masks and undefs, can't do optimization.
12534 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops);
12537 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
12538 EVT VT = N->getValueType(0);
12539 unsigned NumElts = VT.getVectorNumElements();
12541 SDValue N0 = N->getOperand(0);
12542 SDValue N1 = N->getOperand(1);
12544 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG");
12546 // Canonicalize shuffle undef, undef -> undef
12547 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
12548 return DAG.getUNDEF(VT);
12550 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
12552 // Canonicalize shuffle v, v -> v, undef
12554 SmallVector<int, 8> NewMask;
12555 for (unsigned i = 0; i != NumElts; ++i) {
12556 int Idx = SVN->getMaskElt(i);
12557 if (Idx >= (int)NumElts) Idx -= NumElts;
12558 NewMask.push_back(Idx);
12560 return DAG.getVectorShuffle(VT, SDLoc(N), N0, DAG.getUNDEF(VT),
12564 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
12565 if (N0.getOpcode() == ISD::UNDEF) {
12566 SmallVector<int, 8> NewMask;
12567 for (unsigned i = 0; i != NumElts; ++i) {
12568 int Idx = SVN->getMaskElt(i);
12570 if (Idx >= (int)NumElts)
12573 Idx = -1; // remove reference to lhs
12575 NewMask.push_back(Idx);
12577 return DAG.getVectorShuffle(VT, SDLoc(N), N1, DAG.getUNDEF(VT),
12581 // Remove references to rhs if it is undef
12582 if (N1.getOpcode() == ISD::UNDEF) {
12583 bool Changed = false;
12584 SmallVector<int, 8> NewMask;
12585 for (unsigned i = 0; i != NumElts; ++i) {
12586 int Idx = SVN->getMaskElt(i);
12587 if (Idx >= (int)NumElts) {
12591 NewMask.push_back(Idx);
12594 return DAG.getVectorShuffle(VT, SDLoc(N), N0, N1, &NewMask[0]);
12597 // If it is a splat, check if the argument vector is another splat or a
12599 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
12600 SDNode *V = N0.getNode();
12602 // If this is a bit convert that changes the element type of the vector but
12603 // not the number of vector elements, look through it. Be careful not to
12604 // look though conversions that change things like v4f32 to v2f64.
12605 if (V->getOpcode() == ISD::BITCAST) {
12606 SDValue ConvInput = V->getOperand(0);
12607 if (ConvInput.getValueType().isVector() &&
12608 ConvInput.getValueType().getVectorNumElements() == NumElts)
12609 V = ConvInput.getNode();
12612 if (V->getOpcode() == ISD::BUILD_VECTOR) {
12613 assert(V->getNumOperands() == NumElts &&
12614 "BUILD_VECTOR has wrong number of operands");
12616 bool AllSame = true;
12617 for (unsigned i = 0; i != NumElts; ++i) {
12618 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
12619 Base = V->getOperand(i);
12623 // Splat of <u, u, u, u>, return <u, u, u, u>
12624 if (!Base.getNode())
12626 for (unsigned i = 0; i != NumElts; ++i) {
12627 if (V->getOperand(i) != Base) {
12632 // Splat of <x, x, x, x>, return <x, x, x, x>
12636 // Canonicalize any other splat as a build_vector.
12637 const SDValue &Splatted = V->getOperand(SVN->getSplatIndex());
12638 SmallVector<SDValue, 8> Ops(NumElts, Splatted);
12639 SDValue NewBV = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
12640 V->getValueType(0), Ops);
12642 // We may have jumped through bitcasts, so the type of the
12643 // BUILD_VECTOR may not match the type of the shuffle.
12644 if (V->getValueType(0) != VT)
12645 NewBV = DAG.getNode(ISD::BITCAST, SDLoc(N), VT, NewBV);
12650 // There are various patterns used to build up a vector from smaller vectors,
12651 // subvectors, or elements. Scan chains of these and replace unused insertions
12652 // or components with undef.
12653 if (SDValue S = simplifyShuffleOperands(SVN, N0, N1, DAG))
12656 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
12657 Level < AfterLegalizeVectorOps &&
12658 (N1.getOpcode() == ISD::UNDEF ||
12659 (N1.getOpcode() == ISD::CONCAT_VECTORS &&
12660 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()))) {
12661 SDValue V = partitionShuffleOfConcats(N, DAG);
12667 // Attempt to combine a shuffle of 2 inputs of 'scalar sources' -
12668 // BUILD_VECTOR or SCALAR_TO_VECTOR into a single BUILD_VECTOR.
12669 if (Level < AfterLegalizeVectorOps && TLI.isTypeLegal(VT)) {
12670 SmallVector<SDValue, 8> Ops;
12671 for (int M : SVN->getMask()) {
12672 SDValue Op = DAG.getUNDEF(VT.getScalarType());
12674 int Idx = M % NumElts;
12675 SDValue &S = (M < (int)NumElts ? N0 : N1);
12676 if (S.getOpcode() == ISD::BUILD_VECTOR && S.hasOneUse()) {
12677 Op = S.getOperand(Idx);
12678 } else if (S.getOpcode() == ISD::SCALAR_TO_VECTOR && S.hasOneUse()) {
12680 Op = S.getOperand(0);
12682 // Operand can't be combined - bail out.
12688 if (Ops.size() == VT.getVectorNumElements()) {
12689 // BUILD_VECTOR requires all inputs to be of the same type, find the
12690 // maximum type and extend them all.
12691 EVT SVT = VT.getScalarType();
12692 if (SVT.isInteger())
12693 for (SDValue &Op : Ops)
12694 SVT = (SVT.bitsLT(Op.getValueType()) ? Op.getValueType() : SVT);
12695 if (SVT != VT.getScalarType())
12696 for (SDValue &Op : Ops)
12697 Op = TLI.isZExtFree(Op.getValueType(), SVT)
12698 ? DAG.getZExtOrTrunc(Op, SDLoc(N), SVT)
12699 : DAG.getSExtOrTrunc(Op, SDLoc(N), SVT);
12700 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Ops);
12704 // If this shuffle only has a single input that is a bitcasted shuffle,
12705 // attempt to merge the 2 shuffles and suitably bitcast the inputs/output
12706 // back to their original types.
12707 if (N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
12708 N1.getOpcode() == ISD::UNDEF && Level < AfterLegalizeVectorOps &&
12709 TLI.isTypeLegal(VT)) {
12711 // Peek through the bitcast only if there is one user.
12713 while (BC0.getOpcode() == ISD::BITCAST) {
12714 if (!BC0.hasOneUse())
12716 BC0 = BC0.getOperand(0);
12719 auto ScaleShuffleMask = [](ArrayRef<int> Mask, int Scale) {
12721 return SmallVector<int, 8>(Mask.begin(), Mask.end());
12723 SmallVector<int, 8> NewMask;
12725 for (int s = 0; s != Scale; ++s)
12726 NewMask.push_back(M < 0 ? -1 : Scale * M + s);
12730 if (BC0.getOpcode() == ISD::VECTOR_SHUFFLE && BC0.hasOneUse()) {
12731 EVT SVT = VT.getScalarType();
12732 EVT InnerVT = BC0->getValueType(0);
12733 EVT InnerSVT = InnerVT.getScalarType();
12735 // Determine which shuffle works with the smaller scalar type.
12736 EVT ScaleVT = SVT.bitsLT(InnerSVT) ? VT : InnerVT;
12737 EVT ScaleSVT = ScaleVT.getScalarType();
12739 if (TLI.isTypeLegal(ScaleVT) &&
12740 0 == (InnerSVT.getSizeInBits() % ScaleSVT.getSizeInBits()) &&
12741 0 == (SVT.getSizeInBits() % ScaleSVT.getSizeInBits())) {
12743 int InnerScale = InnerSVT.getSizeInBits() / ScaleSVT.getSizeInBits();
12744 int OuterScale = SVT.getSizeInBits() / ScaleSVT.getSizeInBits();
12746 // Scale the shuffle masks to the smaller scalar type.
12747 ShuffleVectorSDNode *InnerSVN = cast<ShuffleVectorSDNode>(BC0);
12748 SmallVector<int, 8> InnerMask =
12749 ScaleShuffleMask(InnerSVN->getMask(), InnerScale);
12750 SmallVector<int, 8> OuterMask =
12751 ScaleShuffleMask(SVN->getMask(), OuterScale);
12753 // Merge the shuffle masks.
12754 SmallVector<int, 8> NewMask;
12755 for (int M : OuterMask)
12756 NewMask.push_back(M < 0 ? -1 : InnerMask[M]);
12758 // Test for shuffle mask legality over both commutations.
12759 SDValue SV0 = BC0->getOperand(0);
12760 SDValue SV1 = BC0->getOperand(1);
12761 bool LegalMask = TLI.isShuffleMaskLegal(NewMask, ScaleVT);
12763 std::swap(SV0, SV1);
12764 ShuffleVectorSDNode::commuteMask(NewMask);
12765 LegalMask = TLI.isShuffleMaskLegal(NewMask, ScaleVT);
12769 SV0 = DAG.getNode(ISD::BITCAST, SDLoc(N), ScaleVT, SV0);
12770 SV1 = DAG.getNode(ISD::BITCAST, SDLoc(N), ScaleVT, SV1);
12771 return DAG.getNode(
12772 ISD::BITCAST, SDLoc(N), VT,
12773 DAG.getVectorShuffle(ScaleVT, SDLoc(N), SV0, SV1, NewMask));
12779 // Canonicalize shuffles according to rules:
12780 // shuffle(A, shuffle(A, B)) -> shuffle(shuffle(A,B), A)
12781 // shuffle(B, shuffle(A, B)) -> shuffle(shuffle(A,B), B)
12782 // shuffle(B, shuffle(A, Undef)) -> shuffle(shuffle(A, Undef), B)
12783 if (N1.getOpcode() == ISD::VECTOR_SHUFFLE &&
12784 N0.getOpcode() != ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
12785 TLI.isTypeLegal(VT)) {
12786 // The incoming shuffle must be of the same type as the result of the
12787 // current shuffle.
12788 assert(N1->getOperand(0).getValueType() == VT &&
12789 "Shuffle types don't match");
12791 SDValue SV0 = N1->getOperand(0);
12792 SDValue SV1 = N1->getOperand(1);
12793 bool HasSameOp0 = N0 == SV0;
12794 bool IsSV1Undef = SV1.getOpcode() == ISD::UNDEF;
12795 if (HasSameOp0 || IsSV1Undef || N0 == SV1)
12796 // Commute the operands of this shuffle so that next rule
12798 return DAG.getCommutedVectorShuffle(*SVN);
12801 // Try to fold according to rules:
12802 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, B, M2)
12803 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, C, M2)
12804 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(B, C, M2)
12805 // Don't try to fold shuffles with illegal type.
12806 // Only fold if this shuffle is the only user of the other shuffle.
12807 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && N->isOnlyUserOf(N0.getNode()) &&
12808 Level < AfterLegalizeDAG && TLI.isTypeLegal(VT)) {
12809 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
12811 // The incoming shuffle must be of the same type as the result of the
12812 // current shuffle.
12813 assert(OtherSV->getOperand(0).getValueType() == VT &&
12814 "Shuffle types don't match");
12817 SmallVector<int, 4> Mask;
12818 // Compute the combined shuffle mask for a shuffle with SV0 as the first
12819 // operand, and SV1 as the second operand.
12820 for (unsigned i = 0; i != NumElts; ++i) {
12821 int Idx = SVN->getMaskElt(i);
12823 // Propagate Undef.
12824 Mask.push_back(Idx);
12828 SDValue CurrentVec;
12829 if (Idx < (int)NumElts) {
12830 // This shuffle index refers to the inner shuffle N0. Lookup the inner
12831 // shuffle mask to identify which vector is actually referenced.
12832 Idx = OtherSV->getMaskElt(Idx);
12834 // Propagate Undef.
12835 Mask.push_back(Idx);
12839 CurrentVec = (Idx < (int) NumElts) ? OtherSV->getOperand(0)
12840 : OtherSV->getOperand(1);
12842 // This shuffle index references an element within N1.
12846 // Simple case where 'CurrentVec' is UNDEF.
12847 if (CurrentVec.getOpcode() == ISD::UNDEF) {
12848 Mask.push_back(-1);
12852 // Canonicalize the shuffle index. We don't know yet if CurrentVec
12853 // will be the first or second operand of the combined shuffle.
12854 Idx = Idx % NumElts;
12855 if (!SV0.getNode() || SV0 == CurrentVec) {
12856 // Ok. CurrentVec is the left hand side.
12857 // Update the mask accordingly.
12859 Mask.push_back(Idx);
12863 // Bail out if we cannot convert the shuffle pair into a single shuffle.
12864 if (SV1.getNode() && SV1 != CurrentVec)
12867 // Ok. CurrentVec is the right hand side.
12868 // Update the mask accordingly.
12870 Mask.push_back(Idx + NumElts);
12873 // Check if all indices in Mask are Undef. In case, propagate Undef.
12874 bool isUndefMask = true;
12875 for (unsigned i = 0; i != NumElts && isUndefMask; ++i)
12876 isUndefMask &= Mask[i] < 0;
12879 return DAG.getUNDEF(VT);
12881 if (!SV0.getNode())
12882 SV0 = DAG.getUNDEF(VT);
12883 if (!SV1.getNode())
12884 SV1 = DAG.getUNDEF(VT);
12886 // Avoid introducing shuffles with illegal mask.
12887 if (!TLI.isShuffleMaskLegal(Mask, VT)) {
12888 ShuffleVectorSDNode::commuteMask(Mask);
12890 if (!TLI.isShuffleMaskLegal(Mask, VT))
12893 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(B, A, M2)
12894 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(C, A, M2)
12895 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(C, B, M2)
12896 std::swap(SV0, SV1);
12899 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, B, M2)
12900 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, C, M2)
12901 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(B, C, M2)
12902 return DAG.getVectorShuffle(VT, SDLoc(N), SV0, SV1, &Mask[0]);
12908 SDValue DAGCombiner::visitSCALAR_TO_VECTOR(SDNode *N) {
12909 SDValue InVal = N->getOperand(0);
12910 EVT VT = N->getValueType(0);
12912 // Replace a SCALAR_TO_VECTOR(EXTRACT_VECTOR_ELT(V,C0)) pattern
12913 // with a VECTOR_SHUFFLE.
12914 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
12915 SDValue InVec = InVal->getOperand(0);
12916 SDValue EltNo = InVal->getOperand(1);
12918 // FIXME: We could support implicit truncation if the shuffle can be
12919 // scaled to a smaller vector scalar type.
12920 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(EltNo);
12921 if (C0 && VT == InVec.getValueType() &&
12922 VT.getScalarType() == InVal.getValueType()) {
12923 SmallVector<int, 8> NewMask(VT.getVectorNumElements(), -1);
12924 int Elt = C0->getZExtValue();
12927 if (TLI.isShuffleMaskLegal(NewMask, VT))
12928 return DAG.getVectorShuffle(VT, SDLoc(N), InVec, DAG.getUNDEF(VT),
12936 SDValue DAGCombiner::visitINSERT_SUBVECTOR(SDNode *N) {
12937 SDValue N0 = N->getOperand(0);
12938 SDValue N2 = N->getOperand(2);
12940 // If the input vector is a concatenation, and the insert replaces
12941 // one of the halves, we can optimize into a single concat_vectors.
12942 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
12943 N0->getNumOperands() == 2 && N2.getOpcode() == ISD::Constant) {
12944 APInt InsIdx = cast<ConstantSDNode>(N2)->getAPIntValue();
12945 EVT VT = N->getValueType(0);
12947 // Lower half: fold (insert_subvector (concat_vectors X, Y), Z) ->
12948 // (concat_vectors Z, Y)
12950 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
12951 N->getOperand(1), N0.getOperand(1));
12953 // Upper half: fold (insert_subvector (concat_vectors X, Y), Z) ->
12954 // (concat_vectors X, Z)
12955 if (InsIdx == VT.getVectorNumElements()/2)
12956 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
12957 N0.getOperand(0), N->getOperand(1));
12963 SDValue DAGCombiner::visitFP_TO_FP16(SDNode *N) {
12964 SDValue N0 = N->getOperand(0);
12966 // fold (fp_to_fp16 (fp16_to_fp op)) -> op
12967 if (N0->getOpcode() == ISD::FP16_TO_FP)
12968 return N0->getOperand(0);
12973 /// Returns a vector_shuffle if it able to transform an AND to a vector_shuffle
12974 /// with the destination vector and a zero vector.
12975 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
12976 /// vector_shuffle V, Zero, <0, 4, 2, 4>
12977 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
12978 EVT VT = N->getValueType(0);
12979 SDValue LHS = N->getOperand(0);
12980 SDValue RHS = N->getOperand(1);
12983 // Make sure we're not running after operation legalization where it
12984 // may have custom lowered the vector shuffles.
12985 if (LegalOperations)
12988 if (N->getOpcode() != ISD::AND)
12991 if (RHS.getOpcode() == ISD::BITCAST)
12992 RHS = RHS.getOperand(0);
12994 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
12995 SmallVector<int, 8> Indices;
12996 unsigned NumElts = RHS.getNumOperands();
12998 for (unsigned i = 0; i != NumElts; ++i) {
12999 SDValue Elt = RHS.getOperand(i);
13000 if (isAllOnesConstant(Elt))
13001 Indices.push_back(i);
13002 else if (isNullConstant(Elt))
13003 Indices.push_back(NumElts+i);
13008 // Let's see if the target supports this vector_shuffle.
13009 EVT RVT = RHS.getValueType();
13010 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
13013 // Return the new VECTOR_SHUFFLE node.
13014 EVT EltVT = RVT.getVectorElementType();
13015 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
13016 DAG.getConstant(0, dl, EltVT));
13017 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, RVT, ZeroOps);
13018 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
13019 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
13020 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
13026 /// Visit a binary vector operation, like ADD.
13027 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
13028 assert(N->getValueType(0).isVector() &&
13029 "SimplifyVBinOp only works on vectors!");
13031 SDValue LHS = N->getOperand(0);
13032 SDValue RHS = N->getOperand(1);
13034 if (SDValue Shuffle = XformToShuffleWithZero(N))
13037 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
13039 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
13040 RHS.getOpcode() == ISD::BUILD_VECTOR) {
13041 // Check if both vectors are constants. If not bail out.
13042 if (!(cast<BuildVectorSDNode>(LHS)->isConstant() &&
13043 cast<BuildVectorSDNode>(RHS)->isConstant()))
13046 SmallVector<SDValue, 8> Ops;
13047 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
13048 SDValue LHSOp = LHS.getOperand(i);
13049 SDValue RHSOp = RHS.getOperand(i);
13051 // Can't fold divide by zero.
13052 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
13053 N->getOpcode() == ISD::FDIV) {
13054 if (isNullConstant(RHSOp) || (RHSOp.getOpcode() == ISD::ConstantFP &&
13055 cast<ConstantFPSDNode>(RHSOp.getNode())->isZero()))
13059 EVT VT = LHSOp.getValueType();
13060 EVT RVT = RHSOp.getValueType();
13062 // Integer BUILD_VECTOR operands may have types larger than the element
13063 // size (e.g., when the element type is not legal). Prior to type
13064 // legalization, the types may not match between the two BUILD_VECTORS.
13065 // Truncate one of the operands to make them match.
13066 if (RVT.getSizeInBits() > VT.getSizeInBits()) {
13067 RHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, RHSOp);
13069 LHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), RVT, LHSOp);
13073 SDValue FoldOp = DAG.getNode(N->getOpcode(), SDLoc(LHS), VT,
13075 if (FoldOp.getOpcode() != ISD::UNDEF &&
13076 FoldOp.getOpcode() != ISD::Constant &&
13077 FoldOp.getOpcode() != ISD::ConstantFP)
13079 Ops.push_back(FoldOp);
13080 AddToWorklist(FoldOp.getNode());
13083 if (Ops.size() == LHS.getNumOperands())
13084 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), LHS.getValueType(), Ops);
13087 // Type legalization might introduce new shuffles in the DAG.
13088 // Fold (VBinOp (shuffle (A, Undef, Mask)), (shuffle (B, Undef, Mask)))
13089 // -> (shuffle (VBinOp (A, B)), Undef, Mask).
13090 if (LegalTypes && isa<ShuffleVectorSDNode>(LHS) &&
13091 isa<ShuffleVectorSDNode>(RHS) && LHS.hasOneUse() && RHS.hasOneUse() &&
13092 LHS.getOperand(1).getOpcode() == ISD::UNDEF &&
13093 RHS.getOperand(1).getOpcode() == ISD::UNDEF) {
13094 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(LHS);
13095 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(RHS);
13097 if (SVN0->getMask().equals(SVN1->getMask())) {
13098 EVT VT = N->getValueType(0);
13099 SDValue UndefVector = LHS.getOperand(1);
13100 SDValue NewBinOp = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
13101 LHS.getOperand(0), RHS.getOperand(0));
13102 AddUsersToWorklist(N);
13103 return DAG.getVectorShuffle(VT, SDLoc(N), NewBinOp, UndefVector,
13104 &SVN0->getMask()[0]);
13111 SDValue DAGCombiner::SimplifySelect(SDLoc DL, SDValue N0,
13112 SDValue N1, SDValue N2){
13113 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
13115 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
13116 cast<CondCodeSDNode>(N0.getOperand(2))->get());
13118 // If we got a simplified select_cc node back from SimplifySelectCC, then
13119 // break it down into a new SETCC node, and a new SELECT node, and then return
13120 // the SELECT node, since we were called with a SELECT node.
13121 if (SCC.getNode()) {
13122 // Check to see if we got a select_cc back (to turn into setcc/select).
13123 // Otherwise, just return whatever node we got back, like fabs.
13124 if (SCC.getOpcode() == ISD::SELECT_CC) {
13125 SDValue SETCC = DAG.getNode(ISD::SETCC, SDLoc(N0),
13127 SCC.getOperand(0), SCC.getOperand(1),
13128 SCC.getOperand(4));
13129 AddToWorklist(SETCC.getNode());
13130 return DAG.getSelect(SDLoc(SCC), SCC.getValueType(), SETCC,
13131 SCC.getOperand(2), SCC.getOperand(3));
13139 /// Given a SELECT or a SELECT_CC node, where LHS and RHS are the two values
13140 /// being selected between, see if we can simplify the select. Callers of this
13141 /// should assume that TheSelect is deleted if this returns true. As such, they
13142 /// should return the appropriate thing (e.g. the node) back to the top-level of
13143 /// the DAG combiner loop to avoid it being looked at.
13144 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
13147 // fold (select (setcc x, -0.0, *lt), NaN, (fsqrt x))
13148 // The select + setcc is redundant, because fsqrt returns NaN for X < -0.
13149 if (const ConstantFPSDNode *NaN = isConstOrConstSplatFP(LHS)) {
13150 if (NaN->isNaN() && RHS.getOpcode() == ISD::FSQRT) {
13151 // We have: (select (setcc ?, ?, ?), NaN, (fsqrt ?))
13152 SDValue Sqrt = RHS;
13155 const ConstantFPSDNode *NegZero = nullptr;
13157 if (TheSelect->getOpcode() == ISD::SELECT_CC) {
13158 CC = dyn_cast<CondCodeSDNode>(TheSelect->getOperand(4))->get();
13159 CmpLHS = TheSelect->getOperand(0);
13160 NegZero = isConstOrConstSplatFP(TheSelect->getOperand(1));
13162 // SELECT or VSELECT
13163 SDValue Cmp = TheSelect->getOperand(0);
13164 if (Cmp.getOpcode() == ISD::SETCC) {
13165 CC = dyn_cast<CondCodeSDNode>(Cmp.getOperand(2))->get();
13166 CmpLHS = Cmp.getOperand(0);
13167 NegZero = isConstOrConstSplatFP(Cmp.getOperand(1));
13170 if (NegZero && NegZero->isNegative() && NegZero->isZero() &&
13171 Sqrt.getOperand(0) == CmpLHS && (CC == ISD::SETOLT ||
13172 CC == ISD::SETULT || CC == ISD::SETLT)) {
13173 // We have: (select (setcc x, -0.0, *lt), NaN, (fsqrt x))
13174 CombineTo(TheSelect, Sqrt);
13179 // Cannot simplify select with vector condition
13180 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
13182 // If this is a select from two identical things, try to pull the operation
13183 // through the select.
13184 if (LHS.getOpcode() != RHS.getOpcode() ||
13185 !LHS.hasOneUse() || !RHS.hasOneUse())
13188 // If this is a load and the token chain is identical, replace the select
13189 // of two loads with a load through a select of the address to load from.
13190 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
13191 // constants have been dropped into the constant pool.
13192 if (LHS.getOpcode() == ISD::LOAD) {
13193 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
13194 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
13196 // Token chains must be identical.
13197 if (LHS.getOperand(0) != RHS.getOperand(0) ||
13198 // Do not let this transformation reduce the number of volatile loads.
13199 LLD->isVolatile() || RLD->isVolatile() ||
13200 // FIXME: If either is a pre/post inc/dec load,
13201 // we'd need to split out the address adjustment.
13202 LLD->isIndexed() || RLD->isIndexed() ||
13203 // If this is an EXTLOAD, the VT's must match.
13204 LLD->getMemoryVT() != RLD->getMemoryVT() ||
13205 // If this is an EXTLOAD, the kind of extension must match.
13206 (LLD->getExtensionType() != RLD->getExtensionType() &&
13207 // The only exception is if one of the extensions is anyext.
13208 LLD->getExtensionType() != ISD::EXTLOAD &&
13209 RLD->getExtensionType() != ISD::EXTLOAD) ||
13210 // FIXME: this discards src value information. This is
13211 // over-conservative. It would be beneficial to be able to remember
13212 // both potential memory locations. Since we are discarding
13213 // src value info, don't do the transformation if the memory
13214 // locations are not in the default address space.
13215 LLD->getPointerInfo().getAddrSpace() != 0 ||
13216 RLD->getPointerInfo().getAddrSpace() != 0 ||
13217 !TLI.isOperationLegalOrCustom(TheSelect->getOpcode(),
13218 LLD->getBasePtr().getValueType()))
13221 // Check that the select condition doesn't reach either load. If so,
13222 // folding this will induce a cycle into the DAG. If not, this is safe to
13223 // xform, so create a select of the addresses.
13225 if (TheSelect->getOpcode() == ISD::SELECT) {
13226 SDNode *CondNode = TheSelect->getOperand(0).getNode();
13227 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
13228 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
13230 // The loads must not depend on one another.
13231 if (LLD->isPredecessorOf(RLD) ||
13232 RLD->isPredecessorOf(LLD))
13234 Addr = DAG.getSelect(SDLoc(TheSelect),
13235 LLD->getBasePtr().getValueType(),
13236 TheSelect->getOperand(0), LLD->getBasePtr(),
13237 RLD->getBasePtr());
13238 } else { // Otherwise SELECT_CC
13239 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
13240 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
13242 if ((LLD->hasAnyUseOfValue(1) &&
13243 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
13244 (RLD->hasAnyUseOfValue(1) &&
13245 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS))))
13248 Addr = DAG.getNode(ISD::SELECT_CC, SDLoc(TheSelect),
13249 LLD->getBasePtr().getValueType(),
13250 TheSelect->getOperand(0),
13251 TheSelect->getOperand(1),
13252 LLD->getBasePtr(), RLD->getBasePtr(),
13253 TheSelect->getOperand(4));
13257 // It is safe to replace the two loads if they have different alignments,
13258 // but the new load must be the minimum (most restrictive) alignment of the
13260 bool isInvariant = LLD->isInvariant() & RLD->isInvariant();
13261 unsigned Alignment = std::min(LLD->getAlignment(), RLD->getAlignment());
13262 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
13263 Load = DAG.getLoad(TheSelect->getValueType(0),
13265 // FIXME: Discards pointer and AA info.
13266 LLD->getChain(), Addr, MachinePointerInfo(),
13267 LLD->isVolatile(), LLD->isNonTemporal(),
13268 isInvariant, Alignment);
13270 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
13271 RLD->getExtensionType() : LLD->getExtensionType(),
13273 TheSelect->getValueType(0),
13274 // FIXME: Discards pointer and AA info.
13275 LLD->getChain(), Addr, MachinePointerInfo(),
13276 LLD->getMemoryVT(), LLD->isVolatile(),
13277 LLD->isNonTemporal(), isInvariant, Alignment);
13280 // Users of the select now use the result of the load.
13281 CombineTo(TheSelect, Load);
13283 // Users of the old loads now use the new load's chain. We know the
13284 // old-load value is dead now.
13285 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
13286 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
13293 /// Simplify an expression of the form (N0 cond N1) ? N2 : N3
13294 /// where 'cond' is the comparison specified by CC.
13295 SDValue DAGCombiner::SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1,
13296 SDValue N2, SDValue N3,
13297 ISD::CondCode CC, bool NotExtCompare) {
13298 // (x ? y : y) -> y.
13299 if (N2 == N3) return N2;
13301 EVT VT = N2.getValueType();
13302 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
13303 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
13305 // Determine if the condition we're dealing with is constant
13306 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
13307 N0, N1, CC, DL, false);
13308 if (SCC.getNode()) AddToWorklist(SCC.getNode());
13310 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
13311 // fold select_cc true, x, y -> x
13312 // fold select_cc false, x, y -> y
13313 return !SCCC->isNullValue() ? N2 : N3;
13316 // Check to see if we can simplify the select into an fabs node
13317 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
13318 // Allow either -0.0 or 0.0
13319 if (CFP->isZero()) {
13320 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
13321 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
13322 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
13323 N2 == N3.getOperand(0))
13324 return DAG.getNode(ISD::FABS, DL, VT, N0);
13326 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
13327 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
13328 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
13329 N2.getOperand(0) == N3)
13330 return DAG.getNode(ISD::FABS, DL, VT, N3);
13334 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
13335 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
13336 // in it. This is a win when the constant is not otherwise available because
13337 // it replaces two constant pool loads with one. We only do this if the FP
13338 // type is known to be legal, because if it isn't, then we are before legalize
13339 // types an we want the other legalization to happen first (e.g. to avoid
13340 // messing with soft float) and if the ConstantFP is not legal, because if
13341 // it is legal, we may not need to store the FP constant in a constant pool.
13342 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
13343 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
13344 if (TLI.isTypeLegal(N2.getValueType()) &&
13345 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
13346 TargetLowering::Legal &&
13347 !TLI.isFPImmLegal(TV->getValueAPF(), TV->getValueType(0)) &&
13348 !TLI.isFPImmLegal(FV->getValueAPF(), FV->getValueType(0))) &&
13349 // If both constants have multiple uses, then we won't need to do an
13350 // extra load, they are likely around in registers for other users.
13351 (TV->hasOneUse() || FV->hasOneUse())) {
13352 Constant *Elts[] = {
13353 const_cast<ConstantFP*>(FV->getConstantFPValue()),
13354 const_cast<ConstantFP*>(TV->getConstantFPValue())
13356 Type *FPTy = Elts[0]->getType();
13357 const DataLayout &TD = *TLI.getDataLayout();
13359 // Create a ConstantArray of the two constants.
13360 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
13361 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
13362 TD.getPrefTypeAlignment(FPTy));
13363 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13365 // Get the offsets to the 0 and 1 element of the array so that we can
13366 // select between them.
13367 SDValue Zero = DAG.getIntPtrConstant(0, DL);
13368 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
13369 SDValue One = DAG.getIntPtrConstant(EltSize, SDLoc(FV));
13371 SDValue Cond = DAG.getSetCC(DL,
13372 getSetCCResultType(N0.getValueType()),
13374 AddToWorklist(Cond.getNode());
13375 SDValue CstOffset = DAG.getSelect(DL, Zero.getValueType(),
13377 AddToWorklist(CstOffset.getNode());
13378 CPIdx = DAG.getNode(ISD::ADD, DL, CPIdx.getValueType(), CPIdx,
13380 AddToWorklist(CPIdx.getNode());
13381 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
13382 MachinePointerInfo::getConstantPool(), false,
13383 false, false, Alignment);
13387 // Check to see if we can perform the "gzip trick", transforming
13388 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
13389 if (isNullConstant(N3) && CC == ISD::SETLT &&
13390 (isNullConstant(N1) || // (a < 0) ? b : 0
13391 (isOneConstant(N1) && N0 == N2))) { // (a < 1) ? a : 0
13392 EVT XType = N0.getValueType();
13393 EVT AType = N2.getValueType();
13394 if (XType.bitsGE(AType)) {
13395 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
13396 // single-bit constant.
13397 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue() - 1)) == 0)) {
13398 unsigned ShCtV = N2C->getAPIntValue().logBase2();
13399 ShCtV = XType.getSizeInBits() - ShCtV - 1;
13400 SDValue ShCt = DAG.getConstant(ShCtV, SDLoc(N0),
13401 getShiftAmountTy(N0.getValueType()));
13402 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0),
13404 AddToWorklist(Shift.getNode());
13406 if (XType.bitsGT(AType)) {
13407 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
13408 AddToWorklist(Shift.getNode());
13411 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
13414 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0),
13416 DAG.getConstant(XType.getSizeInBits() - 1,
13418 getShiftAmountTy(N0.getValueType())));
13419 AddToWorklist(Shift.getNode());
13421 if (XType.bitsGT(AType)) {
13422 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
13423 AddToWorklist(Shift.getNode());
13426 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
13430 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
13431 // where y is has a single bit set.
13432 // A plaintext description would be, we can turn the SELECT_CC into an AND
13433 // when the condition can be materialized as an all-ones register. Any
13434 // single bit-test can be materialized as an all-ones register with
13435 // shift-left and shift-right-arith.
13436 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
13437 N0->getValueType(0) == VT && isNullConstant(N1) && isNullConstant(N2)) {
13438 SDValue AndLHS = N0->getOperand(0);
13439 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
13440 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
13441 // Shift the tested bit over the sign bit.
13442 APInt AndMask = ConstAndRHS->getAPIntValue();
13444 DAG.getConstant(AndMask.countLeadingZeros(), SDLoc(AndLHS),
13445 getShiftAmountTy(AndLHS.getValueType()));
13446 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt);
13448 // Now arithmetic right shift it all the way over, so the result is either
13449 // all-ones, or zero.
13451 DAG.getConstant(AndMask.getBitWidth() - 1, SDLoc(Shl),
13452 getShiftAmountTy(Shl.getValueType()));
13453 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt);
13455 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
13459 // fold select C, 16, 0 -> shl C, 4
13460 if (N2C && isNullConstant(N3) && N2C->getAPIntValue().isPowerOf2() &&
13461 TLI.getBooleanContents(N0.getValueType()) ==
13462 TargetLowering::ZeroOrOneBooleanContent) {
13464 // If the caller doesn't want us to simplify this into a zext of a compare,
13466 if (NotExtCompare && N2C->isOne())
13469 // Get a SetCC of the condition
13470 // NOTE: Don't create a SETCC if it's not legal on this target.
13471 if (!LegalOperations ||
13472 TLI.isOperationLegal(ISD::SETCC,
13473 LegalTypes ? getSetCCResultType(N0.getValueType()) : MVT::i1)) {
13475 // cast from setcc result type to select result type
13477 SCC = DAG.getSetCC(DL, getSetCCResultType(N0.getValueType()),
13479 if (N2.getValueType().bitsLT(SCC.getValueType()))
13480 Temp = DAG.getZeroExtendInReg(SCC, SDLoc(N2),
13481 N2.getValueType());
13483 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
13484 N2.getValueType(), SCC);
13486 SCC = DAG.getSetCC(SDLoc(N0), MVT::i1, N0, N1, CC);
13487 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
13488 N2.getValueType(), SCC);
13491 AddToWorklist(SCC.getNode());
13492 AddToWorklist(Temp.getNode());
13497 // shl setcc result by log2 n2c
13498 return DAG.getNode(
13499 ISD::SHL, DL, N2.getValueType(), Temp,
13500 DAG.getConstant(N2C->getAPIntValue().logBase2(), SDLoc(Temp),
13501 getShiftAmountTy(Temp.getValueType())));
13505 // Check to see if this is the equivalent of setcc
13506 // FIXME: Turn all of these into setcc if setcc if setcc is legal
13507 // otherwise, go ahead with the folds.
13508 if (0 && isNullConstant(N3) && isOneConstant(N2)) {
13509 EVT XType = N0.getValueType();
13510 if (!LegalOperations ||
13511 TLI.isOperationLegal(ISD::SETCC, getSetCCResultType(XType))) {
13512 SDValue Res = DAG.getSetCC(DL, getSetCCResultType(XType), N0, N1, CC);
13513 if (Res.getValueType() != VT)
13514 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
13518 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
13519 if (isNullConstant(N1) && CC == ISD::SETEQ &&
13520 (!LegalOperations ||
13521 TLI.isOperationLegal(ISD::CTLZ, XType))) {
13522 SDValue Ctlz = DAG.getNode(ISD::CTLZ, SDLoc(N0), XType, N0);
13523 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
13524 DAG.getConstant(Log2_32(XType.getSizeInBits()),
13526 getShiftAmountTy(Ctlz.getValueType())));
13528 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
13529 if (isNullConstant(N1) && CC == ISD::SETGT) {
13531 SDValue NegN0 = DAG.getNode(ISD::SUB, DL,
13532 XType, DAG.getConstant(0, DL, XType), N0);
13533 SDValue NotN0 = DAG.getNOT(DL, N0, XType);
13534 return DAG.getNode(ISD::SRL, DL, XType,
13535 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
13536 DAG.getConstant(XType.getSizeInBits() - 1, DL,
13537 getShiftAmountTy(XType)));
13539 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
13540 if (isAllOnesConstant(N1) && CC == ISD::SETGT) {
13542 SDValue Sign = DAG.getNode(ISD::SRL, DL, XType, N0,
13543 DAG.getConstant(XType.getSizeInBits() - 1, DL,
13544 getShiftAmountTy(N0.getValueType())));
13545 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, DL,
13550 // Check to see if this is an integer abs.
13551 // select_cc setg[te] X, 0, X, -X ->
13552 // select_cc setgt X, -1, X, -X ->
13553 // select_cc setl[te] X, 0, -X, X ->
13554 // select_cc setlt X, 1, -X, X ->
13555 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
13557 ConstantSDNode *SubC = nullptr;
13558 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
13559 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
13560 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
13561 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
13562 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
13563 (N1C->isOne() && CC == ISD::SETLT)) &&
13564 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
13565 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
13567 EVT XType = N0.getValueType();
13568 if (SubC && SubC->isNullValue() && XType.isInteger()) {
13570 SDValue Shift = DAG.getNode(ISD::SRA, DL, XType,
13572 DAG.getConstant(XType.getSizeInBits() - 1, DL,
13573 getShiftAmountTy(N0.getValueType())));
13574 SDValue Add = DAG.getNode(ISD::ADD, DL,
13576 AddToWorklist(Shift.getNode());
13577 AddToWorklist(Add.getNode());
13578 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
13585 /// This is a stub for TargetLowering::SimplifySetCC.
13586 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
13587 SDValue N1, ISD::CondCode Cond,
13588 SDLoc DL, bool foldBooleans) {
13589 TargetLowering::DAGCombinerInfo
13590 DagCombineInfo(DAG, Level, false, this);
13591 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
13594 /// Given an ISD::SDIV node expressing a divide by constant, return
13595 /// a DAG expression to select that will generate the same value by multiplying
13596 /// by a magic number.
13597 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
13598 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
13599 ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
13603 // Avoid division by zero.
13604 if (C->isNullValue())
13607 std::vector<SDNode*> Built;
13609 TLI.BuildSDIV(N, C->getAPIntValue(), DAG, LegalOperations, &Built);
13611 for (SDNode *N : Built)
13616 /// Given an ISD::SDIV node expressing a divide by constant power of 2, return a
13617 /// DAG expression that will generate the same value by right shifting.
13618 SDValue DAGCombiner::BuildSDIVPow2(SDNode *N) {
13619 ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
13623 // Avoid division by zero.
13624 if (C->isNullValue())
13627 std::vector<SDNode *> Built;
13628 SDValue S = TLI.BuildSDIVPow2(N, C->getAPIntValue(), DAG, &Built);
13630 for (SDNode *N : Built)
13635 /// Given an ISD::UDIV node expressing a divide by constant, return a DAG
13636 /// expression that will generate the same value by multiplying by a magic
13638 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
13639 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
13640 ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
13644 // Avoid division by zero.
13645 if (C->isNullValue())
13648 std::vector<SDNode*> Built;
13650 TLI.BuildUDIV(N, C->getAPIntValue(), DAG, LegalOperations, &Built);
13652 for (SDNode *N : Built)
13657 SDValue DAGCombiner::BuildReciprocalEstimate(SDValue Op) {
13658 if (Level >= AfterLegalizeDAG)
13661 // Expose the DAG combiner to the target combiner implementations.
13662 TargetLowering::DAGCombinerInfo DCI(DAG, Level, false, this);
13664 unsigned Iterations = 0;
13665 if (SDValue Est = TLI.getRecipEstimate(Op, DCI, Iterations)) {
13667 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
13668 // For the reciprocal, we need to find the zero of the function:
13669 // F(X) = A X - 1 [which has a zero at X = 1/A]
13671 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
13672 // does not require additional intermediate precision]
13673 EVT VT = Op.getValueType();
13675 SDValue FPOne = DAG.getConstantFP(1.0, DL, VT);
13677 AddToWorklist(Est.getNode());
13679 // Newton iterations: Est = Est + Est (1 - Arg * Est)
13680 for (unsigned i = 0; i < Iterations; ++i) {
13681 SDValue NewEst = DAG.getNode(ISD::FMUL, DL, VT, Op, Est);
13682 AddToWorklist(NewEst.getNode());
13684 NewEst = DAG.getNode(ISD::FSUB, DL, VT, FPOne, NewEst);
13685 AddToWorklist(NewEst.getNode());
13687 NewEst = DAG.getNode(ISD::FMUL, DL, VT, Est, NewEst);
13688 AddToWorklist(NewEst.getNode());
13690 Est = DAG.getNode(ISD::FADD, DL, VT, Est, NewEst);
13691 AddToWorklist(Est.getNode());
13700 /// Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
13701 /// For the reciprocal sqrt, we need to find the zero of the function:
13702 /// F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
13704 /// X_{i+1} = X_i (1.5 - A X_i^2 / 2)
13705 /// As a result, we precompute A/2 prior to the iteration loop.
13706 SDValue DAGCombiner::BuildRsqrtNROneConst(SDValue Arg, SDValue Est,
13707 unsigned Iterations) {
13708 EVT VT = Arg.getValueType();
13710 SDValue ThreeHalves = DAG.getConstantFP(1.5, DL, VT);
13712 // We now need 0.5 * Arg which we can write as (1.5 * Arg - Arg) so that
13713 // this entire sequence requires only one FP constant.
13714 SDValue HalfArg = DAG.getNode(ISD::FMUL, DL, VT, ThreeHalves, Arg);
13715 AddToWorklist(HalfArg.getNode());
13717 HalfArg = DAG.getNode(ISD::FSUB, DL, VT, HalfArg, Arg);
13718 AddToWorklist(HalfArg.getNode());
13720 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
13721 for (unsigned i = 0; i < Iterations; ++i) {
13722 SDValue NewEst = DAG.getNode(ISD::FMUL, DL, VT, Est, Est);
13723 AddToWorklist(NewEst.getNode());
13725 NewEst = DAG.getNode(ISD::FMUL, DL, VT, HalfArg, NewEst);
13726 AddToWorklist(NewEst.getNode());
13728 NewEst = DAG.getNode(ISD::FSUB, DL, VT, ThreeHalves, NewEst);
13729 AddToWorklist(NewEst.getNode());
13731 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, NewEst);
13732 AddToWorklist(Est.getNode());
13737 /// Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
13738 /// For the reciprocal sqrt, we need to find the zero of the function:
13739 /// F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
13741 /// X_{i+1} = (-0.5 * X_i) * (A * X_i * X_i + (-3.0))
13742 SDValue DAGCombiner::BuildRsqrtNRTwoConst(SDValue Arg, SDValue Est,
13743 unsigned Iterations) {
13744 EVT VT = Arg.getValueType();
13746 SDValue MinusThree = DAG.getConstantFP(-3.0, DL, VT);
13747 SDValue MinusHalf = DAG.getConstantFP(-0.5, DL, VT);
13749 // Newton iterations: Est = -0.5 * Est * (-3.0 + Arg * Est * Est)
13750 for (unsigned i = 0; i < Iterations; ++i) {
13751 SDValue HalfEst = DAG.getNode(ISD::FMUL, DL, VT, Est, MinusHalf);
13752 AddToWorklist(HalfEst.getNode());
13754 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, Est);
13755 AddToWorklist(Est.getNode());
13757 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, Arg);
13758 AddToWorklist(Est.getNode());
13760 Est = DAG.getNode(ISD::FADD, DL, VT, Est, MinusThree);
13761 AddToWorklist(Est.getNode());
13763 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, HalfEst);
13764 AddToWorklist(Est.getNode());
13769 SDValue DAGCombiner::BuildRsqrtEstimate(SDValue Op) {
13770 if (Level >= AfterLegalizeDAG)
13773 // Expose the DAG combiner to the target combiner implementations.
13774 TargetLowering::DAGCombinerInfo DCI(DAG, Level, false, this);
13775 unsigned Iterations = 0;
13776 bool UseOneConstNR = false;
13777 if (SDValue Est = TLI.getRsqrtEstimate(Op, DCI, Iterations, UseOneConstNR)) {
13778 AddToWorklist(Est.getNode());
13780 Est = UseOneConstNR ?
13781 BuildRsqrtNROneConst(Op, Est, Iterations) :
13782 BuildRsqrtNRTwoConst(Op, Est, Iterations);
13790 /// Return true if base is a frame index, which is known not to alias with
13791 /// anything but itself. Provides base object and offset as results.
13792 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
13793 const GlobalValue *&GV, const void *&CV) {
13794 // Assume it is a primitive operation.
13795 Base = Ptr; Offset = 0; GV = nullptr; CV = nullptr;
13797 // If it's an adding a simple constant then integrate the offset.
13798 if (Base.getOpcode() == ISD::ADD) {
13799 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
13800 Base = Base.getOperand(0);
13801 Offset += C->getZExtValue();
13805 // Return the underlying GlobalValue, and update the Offset. Return false
13806 // for GlobalAddressSDNode since the same GlobalAddress may be represented
13807 // by multiple nodes with different offsets.
13808 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
13809 GV = G->getGlobal();
13810 Offset += G->getOffset();
13814 // Return the underlying Constant value, and update the Offset. Return false
13815 // for ConstantSDNodes since the same constant pool entry may be represented
13816 // by multiple nodes with different offsets.
13817 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
13818 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal()
13819 : (const void *)C->getConstVal();
13820 Offset += C->getOffset();
13823 // If it's any of the following then it can't alias with anything but itself.
13824 return isa<FrameIndexSDNode>(Base);
13827 /// Return true if there is any possibility that the two addresses overlap.
13828 bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const {
13829 // If they are the same then they must be aliases.
13830 if (Op0->getBasePtr() == Op1->getBasePtr()) return true;
13832 // If they are both volatile then they cannot be reordered.
13833 if (Op0->isVolatile() && Op1->isVolatile()) return true;
13835 // Gather base node and offset information.
13836 SDValue Base1, Base2;
13837 int64_t Offset1, Offset2;
13838 const GlobalValue *GV1, *GV2;
13839 const void *CV1, *CV2;
13840 bool isFrameIndex1 = FindBaseOffset(Op0->getBasePtr(),
13841 Base1, Offset1, GV1, CV1);
13842 bool isFrameIndex2 = FindBaseOffset(Op1->getBasePtr(),
13843 Base2, Offset2, GV2, CV2);
13845 // If they have a same base address then check to see if they overlap.
13846 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
13847 return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 ||
13848 (Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1);
13850 // It is possible for different frame indices to alias each other, mostly
13851 // when tail call optimization reuses return address slots for arguments.
13852 // To catch this case, look up the actual index of frame indices to compute
13853 // the real alias relationship.
13854 if (isFrameIndex1 && isFrameIndex2) {
13855 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13856 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
13857 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
13858 return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 ||
13859 (Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1);
13862 // Otherwise, if we know what the bases are, and they aren't identical, then
13863 // we know they cannot alias.
13864 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
13867 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
13868 // compared to the size and offset of the access, we may be able to prove they
13869 // do not alias. This check is conservative for now to catch cases created by
13870 // splitting vector types.
13871 if ((Op0->getOriginalAlignment() == Op1->getOriginalAlignment()) &&
13872 (Op0->getSrcValueOffset() != Op1->getSrcValueOffset()) &&
13873 (Op0->getMemoryVT().getSizeInBits() >> 3 ==
13874 Op1->getMemoryVT().getSizeInBits() >> 3) &&
13875 (Op0->getOriginalAlignment() > Op0->getMemoryVT().getSizeInBits()) >> 3) {
13876 int64_t OffAlign1 = Op0->getSrcValueOffset() % Op0->getOriginalAlignment();
13877 int64_t OffAlign2 = Op1->getSrcValueOffset() % Op1->getOriginalAlignment();
13879 // There is no overlap between these relatively aligned accesses of similar
13880 // size, return no alias.
13881 if ((OffAlign1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= OffAlign2 ||
13882 (OffAlign2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= OffAlign1)
13886 bool UseAA = CombinerGlobalAA.getNumOccurrences() > 0
13888 : DAG.getSubtarget().useAA();
13890 if (CombinerAAOnlyFunc.getNumOccurrences() &&
13891 CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
13895 Op0->getMemOperand()->getValue() && Op1->getMemOperand()->getValue()) {
13896 // Use alias analysis information.
13897 int64_t MinOffset = std::min(Op0->getSrcValueOffset(),
13898 Op1->getSrcValueOffset());
13899 int64_t Overlap1 = (Op0->getMemoryVT().getSizeInBits() >> 3) +
13900 Op0->getSrcValueOffset() - MinOffset;
13901 int64_t Overlap2 = (Op1->getMemoryVT().getSizeInBits() >> 3) +
13902 Op1->getSrcValueOffset() - MinOffset;
13903 AliasResult AAResult =
13904 AA.alias(MemoryLocation(Op0->getMemOperand()->getValue(), Overlap1,
13905 UseTBAA ? Op0->getAAInfo() : AAMDNodes()),
13906 MemoryLocation(Op1->getMemOperand()->getValue(), Overlap2,
13907 UseTBAA ? Op1->getAAInfo() : AAMDNodes()));
13908 if (AAResult == NoAlias)
13912 // Otherwise we have to assume they alias.
13916 /// Walk up chain skipping non-aliasing memory nodes,
13917 /// looking for aliasing nodes and adding them to the Aliases vector.
13918 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
13919 SmallVectorImpl<SDValue> &Aliases) {
13920 SmallVector<SDValue, 8> Chains; // List of chains to visit.
13921 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
13923 // Get alias information for node.
13924 bool IsLoad = isa<LoadSDNode>(N) && !cast<LSBaseSDNode>(N)->isVolatile();
13927 Chains.push_back(OriginalChain);
13928 unsigned Depth = 0;
13930 // Look at each chain and determine if it is an alias. If so, add it to the
13931 // aliases list. If not, then continue up the chain looking for the next
13933 while (!Chains.empty()) {
13934 SDValue Chain = Chains.pop_back_val();
13936 // For TokenFactor nodes, look at each operand and only continue up the
13937 // chain until we find two aliases. If we've seen two aliases, assume we'll
13938 // find more and revert to original chain since the xform is unlikely to be
13941 // FIXME: The depth check could be made to return the last non-aliasing
13942 // chain we found before we hit a tokenfactor rather than the original
13944 if (Depth > 6 || Aliases.size() == 2) {
13946 Aliases.push_back(OriginalChain);
13950 // Don't bother if we've been before.
13951 if (!Visited.insert(Chain.getNode()).second)
13954 switch (Chain.getOpcode()) {
13955 case ISD::EntryToken:
13956 // Entry token is ideal chain operand, but handled in FindBetterChain.
13961 // Get alias information for Chain.
13962 bool IsOpLoad = isa<LoadSDNode>(Chain.getNode()) &&
13963 !cast<LSBaseSDNode>(Chain.getNode())->isVolatile();
13965 // If chain is alias then stop here.
13966 if (!(IsLoad && IsOpLoad) &&
13967 isAlias(cast<LSBaseSDNode>(N), cast<LSBaseSDNode>(Chain.getNode()))) {
13968 Aliases.push_back(Chain);
13970 // Look further up the chain.
13971 Chains.push_back(Chain.getOperand(0));
13977 case ISD::TokenFactor:
13978 // We have to check each of the operands of the token factor for "small"
13979 // token factors, so we queue them up. Adding the operands to the queue
13980 // (stack) in reverse order maintains the original order and increases the
13981 // likelihood that getNode will find a matching token factor (CSE.)
13982 if (Chain.getNumOperands() > 16) {
13983 Aliases.push_back(Chain);
13986 for (unsigned n = Chain.getNumOperands(); n;)
13987 Chains.push_back(Chain.getOperand(--n));
13992 // For all other instructions we will just have to take what we can get.
13993 Aliases.push_back(Chain);
13998 // We need to be careful here to also search for aliases through the
13999 // value operand of a store, etc. Consider the following situation:
14001 // L1 = load Token1, %52
14002 // S1 = store Token1, L1, %51
14003 // L2 = load Token1, %52+8
14004 // S2 = store Token1, L2, %51+8
14005 // Token2 = Token(S1, S2)
14006 // L3 = load Token2, %53
14007 // S3 = store Token2, L3, %52
14008 // L4 = load Token2, %53+8
14009 // S4 = store Token2, L4, %52+8
14010 // If we search for aliases of S3 (which loads address %52), and we look
14011 // only through the chain, then we'll miss the trivial dependence on L1
14012 // (which also loads from %52). We then might change all loads and
14013 // stores to use Token1 as their chain operand, which could result in
14014 // copying %53 into %52 before copying %52 into %51 (which should
14017 // The problem is, however, that searching for such data dependencies
14018 // can become expensive, and the cost is not directly related to the
14019 // chain depth. Instead, we'll rule out such configurations here by
14020 // insisting that we've visited all chain users (except for users
14021 // of the original chain, which is not necessary). When doing this,
14022 // we need to look through nodes we don't care about (otherwise, things
14023 // like register copies will interfere with trivial cases).
14025 SmallVector<const SDNode *, 16> Worklist;
14026 for (const SDNode *N : Visited)
14027 if (N != OriginalChain.getNode())
14028 Worklist.push_back(N);
14030 while (!Worklist.empty()) {
14031 const SDNode *M = Worklist.pop_back_val();
14033 // We have already visited M, and want to make sure we've visited any uses
14034 // of M that we care about. For uses that we've not visisted, and don't
14035 // care about, queue them to the worklist.
14037 for (SDNode::use_iterator UI = M->use_begin(),
14038 UIE = M->use_end(); UI != UIE; ++UI)
14039 if (UI.getUse().getValueType() == MVT::Other &&
14040 Visited.insert(*UI).second) {
14041 if (isa<MemSDNode>(*UI)) {
14042 // We've not visited this use, and we care about it (it could have an
14043 // ordering dependency with the original node).
14045 Aliases.push_back(OriginalChain);
14049 // We've not visited this use, but we don't care about it. Mark it as
14050 // visited and enqueue it to the worklist.
14051 Worklist.push_back(*UI);
14056 /// Walk up chain skipping non-aliasing memory nodes, looking for a better chain
14057 /// (aliasing node.)
14058 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
14059 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
14061 // Accumulate all the aliases to this node.
14062 GatherAllAliases(N, OldChain, Aliases);
14064 // If no operands then chain to entry token.
14065 if (Aliases.size() == 0)
14066 return DAG.getEntryNode();
14068 // If a single operand then chain to it. We don't need to revisit it.
14069 if (Aliases.size() == 1)
14072 // Construct a custom tailored token factor.
14073 return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Aliases);
14076 /// This is the entry point for the file.
14077 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
14078 CodeGenOpt::Level OptLevel) {
14079 /// This is the main entry point to this class.
14080 DAGCombiner(*this, AA, OptLevel).Run(Level);