1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: divide by zero is currently left unfolded. do we want to turn this
27 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "dagcombine"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Target/TargetLowering.h"
37 #include "llvm/Support/Compiler.h"
38 #include "llvm/Support/CommandLine.h"
46 static Statistic<> NodesCombined ("dagcombiner",
47 "Number of dag nodes combined");
51 CombinerAA("combiner-alias-analysis", cl::Hidden,
52 cl::desc("Turn on alias analysis turning testing"));
54 class VISIBILITY_HIDDEN DAGCombiner {
59 // Worklist of all of the nodes that need to be simplified.
60 std::vector<SDNode*> WorkList;
62 /// AddUsersToWorkList - When an instruction is simplified, add all users of
63 /// the instruction to the work lists because they might get more simplified
66 void AddUsersToWorkList(SDNode *N) {
67 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
69 WorkList.push_back(*UI);
72 /// removeFromWorkList - remove all instances of N from the worklist.
74 void removeFromWorkList(SDNode *N) {
75 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
80 void AddToWorkList(SDNode *N) {
81 WorkList.push_back(N);
84 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo) {
85 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
87 DEBUG(std::cerr << "\nReplacing "; N->dump();
88 std::cerr << "\nWith: "; To[0].Val->dump(&DAG);
89 std::cerr << " and " << NumTo-1 << " other values\n");
90 std::vector<SDNode*> NowDead;
91 DAG.ReplaceAllUsesWith(N, To, &NowDead);
93 // Push the new nodes and any users onto the worklist
94 for (unsigned i = 0, e = NumTo; i != e; ++i) {
95 WorkList.push_back(To[i].Val);
96 AddUsersToWorkList(To[i].Val);
99 // Nodes can end up on the worklist more than once. Make sure we do
100 // not process a node that has been replaced.
101 removeFromWorkList(N);
102 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
103 removeFromWorkList(NowDead[i]);
105 // Finally, since the node is now dead, remove it from the graph.
107 return SDOperand(N, 0);
110 SDOperand CombineTo(SDNode *N, SDOperand Res) {
111 return CombineTo(N, &Res, 1);
114 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
115 SDOperand To[] = { Res0, Res1 };
116 return CombineTo(N, To, 2);
120 /// SimplifyDemandedBits - Check the specified integer node value to see if
121 /// it can be simplified or if things it uses can be simplified by bit
122 /// propagation. If so, return true.
123 bool SimplifyDemandedBits(SDOperand Op) {
124 TargetLowering::TargetLoweringOpt TLO(DAG);
125 uint64_t KnownZero, KnownOne;
126 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
127 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
131 WorkList.push_back(Op.Val);
133 // Replace the old value with the new one.
135 DEBUG(std::cerr << "\nReplacing "; TLO.Old.Val->dump();
136 std::cerr << "\nWith: "; TLO.New.Val->dump(&DAG);
139 std::vector<SDNode*> NowDead;
140 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
142 // Push the new node and any (possibly new) users onto the worklist.
143 WorkList.push_back(TLO.New.Val);
144 AddUsersToWorkList(TLO.New.Val);
146 // Nodes can end up on the worklist more than once. Make sure we do
147 // not process a node that has been replaced.
148 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
149 removeFromWorkList(NowDead[i]);
151 // Finally, if the node is now dead, remove it from the graph. The node
152 // may not be dead if the replacement process recursively simplified to
153 // something else needing this node.
154 if (TLO.Old.Val->use_empty()) {
155 removeFromWorkList(TLO.Old.Val);
156 DAG.DeleteNode(TLO.Old.Val);
161 /// visit - call the node-specific routine that knows how to fold each
162 /// particular type of node.
163 SDOperand visit(SDNode *N);
165 // Visitation implementation - Implement dag node combining for different
166 // node types. The semantics are as follows:
168 // SDOperand.Val == 0 - No change was made
169 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
170 // otherwise - N should be replaced by the returned Operand.
172 SDOperand visitTokenFactor(SDNode *N);
173 SDOperand visitADD(SDNode *N);
174 SDOperand visitSUB(SDNode *N);
175 SDOperand visitMUL(SDNode *N);
176 SDOperand visitSDIV(SDNode *N);
177 SDOperand visitUDIV(SDNode *N);
178 SDOperand visitSREM(SDNode *N);
179 SDOperand visitUREM(SDNode *N);
180 SDOperand visitMULHU(SDNode *N);
181 SDOperand visitMULHS(SDNode *N);
182 SDOperand visitAND(SDNode *N);
183 SDOperand visitOR(SDNode *N);
184 SDOperand visitXOR(SDNode *N);
185 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp);
186 SDOperand visitSHL(SDNode *N);
187 SDOperand visitSRA(SDNode *N);
188 SDOperand visitSRL(SDNode *N);
189 SDOperand visitCTLZ(SDNode *N);
190 SDOperand visitCTTZ(SDNode *N);
191 SDOperand visitCTPOP(SDNode *N);
192 SDOperand visitSELECT(SDNode *N);
193 SDOperand visitSELECT_CC(SDNode *N);
194 SDOperand visitSETCC(SDNode *N);
195 SDOperand visitSIGN_EXTEND(SDNode *N);
196 SDOperand visitZERO_EXTEND(SDNode *N);
197 SDOperand visitANY_EXTEND(SDNode *N);
198 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
199 SDOperand visitTRUNCATE(SDNode *N);
200 SDOperand visitBIT_CONVERT(SDNode *N);
201 SDOperand visitVBIT_CONVERT(SDNode *N);
202 SDOperand visitFADD(SDNode *N);
203 SDOperand visitFSUB(SDNode *N);
204 SDOperand visitFMUL(SDNode *N);
205 SDOperand visitFDIV(SDNode *N);
206 SDOperand visitFREM(SDNode *N);
207 SDOperand visitFCOPYSIGN(SDNode *N);
208 SDOperand visitSINT_TO_FP(SDNode *N);
209 SDOperand visitUINT_TO_FP(SDNode *N);
210 SDOperand visitFP_TO_SINT(SDNode *N);
211 SDOperand visitFP_TO_UINT(SDNode *N);
212 SDOperand visitFP_ROUND(SDNode *N);
213 SDOperand visitFP_ROUND_INREG(SDNode *N);
214 SDOperand visitFP_EXTEND(SDNode *N);
215 SDOperand visitFNEG(SDNode *N);
216 SDOperand visitFABS(SDNode *N);
217 SDOperand visitBRCOND(SDNode *N);
218 SDOperand visitBR_CC(SDNode *N);
219 SDOperand visitLOAD(SDNode *N);
220 SDOperand visitXEXTLOAD(SDNode *N);
221 SDOperand visitSTORE(SDNode *N);
222 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
223 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
224 SDOperand visitVBUILD_VECTOR(SDNode *N);
225 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
226 SDOperand visitVVECTOR_SHUFFLE(SDNode *N);
228 SDOperand XformToShuffleWithZero(SDNode *N);
229 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
231 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
232 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
233 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
234 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
235 SDOperand N3, ISD::CondCode CC);
236 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
237 ISD::CondCode Cond, bool foldBooleans = true);
238 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType);
239 SDOperand BuildSDIV(SDNode *N);
240 SDOperand BuildUDIV(SDNode *N);
241 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
243 /// hasChainUsers - Returns true if one of the users of a load node has the
244 /// chain result as an operand.
245 bool hasChainUsers(SDNode *Load);
247 /// FindBaseOffset - Return true if we can determine base and offset
248 /// information from a given pointer operand. Provides base and offset as a
250 static bool FindBaseOffset(SDOperand Ptr,
251 SDOperand &Object, int64_t &Offset);
253 /// isAlias - Return true if there is the possibility that the two addresses
255 static bool isAlias(SDOperand Ptr1, int64_t Size1, SDOperand SrcValue1,
256 SDOperand Ptr2, int64_t Size2, SDOperand SrcValue2);
258 /// FindAliasInfo - Extracts the relevant alias information from the memory
260 static void FindAliasInfo(SDNode *N,
261 SDOperand &Ptr, int64_t &Size, SDOperand &SrcValue);
263 /// hasChain - Return true if Op has a chain. Provides chain if present.
265 static bool hasChain(SDOperand Op, SDOperand &Chain);
267 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
268 /// looking for a better chain.
269 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
272 DAGCombiner(SelectionDAG &D)
273 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
275 /// Run - runs the dag combiner on all nodes in the work list
276 void Run(bool RunningAfterLegalize);
280 //===----------------------------------------------------------------------===//
281 // TargetLowering::DAGCombinerInfo implementation
282 //===----------------------------------------------------------------------===//
284 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
285 ((DAGCombiner*)DC)->AddToWorkList(N);
288 SDOperand TargetLowering::DAGCombinerInfo::
289 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
290 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
293 SDOperand TargetLowering::DAGCombinerInfo::
294 CombineTo(SDNode *N, SDOperand Res) {
295 return ((DAGCombiner*)DC)->CombineTo(N, Res);
299 SDOperand TargetLowering::DAGCombinerInfo::
300 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
301 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
307 //===----------------------------------------------------------------------===//
310 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
311 // that selects between the values 1 and 0, making it equivalent to a setcc.
312 // Also, set the incoming LHS, RHS, and CC references to the appropriate
313 // nodes based on the type of node we are checking. This simplifies life a
314 // bit for the callers.
315 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
317 if (N.getOpcode() == ISD::SETCC) {
318 LHS = N.getOperand(0);
319 RHS = N.getOperand(1);
320 CC = N.getOperand(2);
323 if (N.getOpcode() == ISD::SELECT_CC &&
324 N.getOperand(2).getOpcode() == ISD::Constant &&
325 N.getOperand(3).getOpcode() == ISD::Constant &&
326 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
327 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
328 LHS = N.getOperand(0);
329 RHS = N.getOperand(1);
330 CC = N.getOperand(4);
336 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
337 // one use. If this is true, it allows the users to invert the operation for
338 // free when it is profitable to do so.
339 static bool isOneUseSetCC(SDOperand N) {
340 SDOperand N0, N1, N2;
341 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
346 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
347 MVT::ValueType VT = N0.getValueType();
348 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
349 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
350 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
351 if (isa<ConstantSDNode>(N1)) {
352 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
353 AddToWorkList(OpNode.Val);
354 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
355 } else if (N0.hasOneUse()) {
356 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
357 AddToWorkList(OpNode.Val);
358 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
361 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
362 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
363 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
364 if (isa<ConstantSDNode>(N0)) {
365 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
366 AddToWorkList(OpNode.Val);
367 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
368 } else if (N1.hasOneUse()) {
369 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
370 AddToWorkList(OpNode.Val);
371 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
377 void DAGCombiner::Run(bool RunningAfterLegalize) {
378 // set the instance variable, so that the various visit routines may use it.
379 AfterLegalize = RunningAfterLegalize;
381 // Add all the dag nodes to the worklist.
382 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
383 E = DAG.allnodes_end(); I != E; ++I)
384 WorkList.push_back(I);
386 // Create a dummy node (which is not added to allnodes), that adds a reference
387 // to the root node, preventing it from being deleted, and tracking any
388 // changes of the root.
389 HandleSDNode Dummy(DAG.getRoot());
392 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
393 TargetLowering::DAGCombinerInfo
394 DagCombineInfo(DAG, !RunningAfterLegalize, this);
396 // while the worklist isn't empty, inspect the node on the end of it and
397 // try and combine it.
398 while (!WorkList.empty()) {
399 SDNode *N = WorkList.back();
402 // If N has no uses, it is dead. Make sure to revisit all N's operands once
403 // N is deleted from the DAG, since they too may now be dead or may have a
404 // reduced number of uses, allowing other xforms.
405 if (N->use_empty() && N != &Dummy) {
406 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
407 WorkList.push_back(N->getOperand(i).Val);
409 removeFromWorkList(N);
414 SDOperand RV = visit(N);
416 // If nothing happened, try a target-specific DAG combine.
418 assert(N->getOpcode() != ISD::DELETED_NODE &&
419 "Node was deleted but visit returned NULL!");
420 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
421 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
422 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
427 // If we get back the same node we passed in, rather than a new node or
428 // zero, we know that the node must have defined multiple values and
429 // CombineTo was used. Since CombineTo takes care of the worklist
430 // mechanics for us, we have no work to do in this case.
432 assert(N->getOpcode() != ISD::DELETED_NODE &&
433 RV.Val->getOpcode() != ISD::DELETED_NODE &&
434 "Node was deleted but visit returned new node!");
436 DEBUG(std::cerr << "\nReplacing "; N->dump();
437 std::cerr << "\nWith: "; RV.Val->dump(&DAG);
439 std::vector<SDNode*> NowDead;
440 if (N->getNumValues() == RV.Val->getNumValues())
441 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
443 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
445 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
448 // Push the new node and any users onto the worklist
449 WorkList.push_back(RV.Val);
450 AddUsersToWorkList(RV.Val);
452 // Nodes can end up on the worklist more than once. Make sure we do
453 // not process a node that has been replaced.
454 removeFromWorkList(N);
455 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
456 removeFromWorkList(NowDead[i]);
458 // Finally, since the node is now dead, remove it from the graph.
464 // If the root changed (e.g. it was a dead load, update the root).
465 DAG.setRoot(Dummy.getValue());
468 SDOperand DAGCombiner::visit(SDNode *N) {
469 switch(N->getOpcode()) {
471 case ISD::TokenFactor: return visitTokenFactor(N);
472 case ISD::ADD: return visitADD(N);
473 case ISD::SUB: return visitSUB(N);
474 case ISD::MUL: return visitMUL(N);
475 case ISD::SDIV: return visitSDIV(N);
476 case ISD::UDIV: return visitUDIV(N);
477 case ISD::SREM: return visitSREM(N);
478 case ISD::UREM: return visitUREM(N);
479 case ISD::MULHU: return visitMULHU(N);
480 case ISD::MULHS: return visitMULHS(N);
481 case ISD::AND: return visitAND(N);
482 case ISD::OR: return visitOR(N);
483 case ISD::XOR: return visitXOR(N);
484 case ISD::SHL: return visitSHL(N);
485 case ISD::SRA: return visitSRA(N);
486 case ISD::SRL: return visitSRL(N);
487 case ISD::CTLZ: return visitCTLZ(N);
488 case ISD::CTTZ: return visitCTTZ(N);
489 case ISD::CTPOP: return visitCTPOP(N);
490 case ISD::SELECT: return visitSELECT(N);
491 case ISD::SELECT_CC: return visitSELECT_CC(N);
492 case ISD::SETCC: return visitSETCC(N);
493 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
494 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
495 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
496 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
497 case ISD::TRUNCATE: return visitTRUNCATE(N);
498 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
499 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N);
500 case ISD::FADD: return visitFADD(N);
501 case ISD::FSUB: return visitFSUB(N);
502 case ISD::FMUL: return visitFMUL(N);
503 case ISD::FDIV: return visitFDIV(N);
504 case ISD::FREM: return visitFREM(N);
505 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
506 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
507 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
508 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
509 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
510 case ISD::FP_ROUND: return visitFP_ROUND(N);
511 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
512 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
513 case ISD::FNEG: return visitFNEG(N);
514 case ISD::FABS: return visitFABS(N);
515 case ISD::BRCOND: return visitBRCOND(N);
516 case ISD::BR_CC: return visitBR_CC(N);
517 case ISD::LOAD: return visitLOAD(N);
520 case ISD::ZEXTLOAD: return visitXEXTLOAD(N);
521 case ISD::STORE: return visitSTORE(N);
522 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
523 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
524 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N);
525 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
526 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N);
527 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD);
528 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB);
529 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL);
530 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV);
531 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV);
532 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND);
533 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR);
534 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR);
539 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
540 // If the token factor has two operands and one is the entry token, replace
541 // the token factor with the other operand.
542 if (N->getNumOperands() == 2) {
543 if (N->getOperand(0).getOpcode() == ISD::EntryToken ||
544 N->getOperand(0) == N->getOperand(1))
545 return N->getOperand(1);
546 if (N->getOperand(1).getOpcode() == ISD::EntryToken)
547 return N->getOperand(0);
550 SmallVector<SDNode *, 8> TFs; // Set of token factor nodes.
551 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
553 // Add this ndoe to the token factor set.
556 // Separate token factors from other operands.
557 for (unsigned i = 0, ie = N->getNumOperands(); i != ie; ++i) {
558 SDOperand Op = N->getOperand(i);
559 if (Op.getOpcode() == ISD::TokenFactor)
560 TFs.push_back(Op.Val);
561 else if (Op.getOpcode() != ISD::EntryToken)
565 // If there are token factor operands.
566 if (TFs.size() > 1) {
567 bool Changed = false; // If we should replace this token factor.
569 // For each token factor.
570 for (unsigned j = 1, je = TFs.size(); j != je; ++j) {
572 bool CanMerge = true; // Can we merge this token factor.
575 if (!TF->hasOneUse()) {
576 // Check to see if all users point to members of the token factor set.
577 for (SDNode::use_iterator UI = TF->use_begin(), UE = TF->use_end();
578 CanMerge && UI != UE; ++UI) {
580 CanMerge = User->getOpcode() == ISD::TokenFactor &&
581 std::find(TFs.begin(), TFs.end(), User) != TFs.end();
585 CanMerge = TF->hasOneUse();
588 // If it's valid to merge.
590 // Remove dead token factor node.
593 // Make sure we don't duplicate operands.
594 unsigned m = Ops.size(); // Number of prior operands.
595 for (unsigned l = 0, le = TF->getNumOperands(); l != le; ++l) {
596 SDOperand Op = TF->getOperand(l);
597 if (std::find(Ops.begin(), Ops.end(), Op) == Ops.end())
602 // Can't merge this token factor.
603 Ops.push_back(SDOperand(TF, 0));
607 // If we've change things around then replace token factor.
609 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
616 SDOperand DAGCombiner::visitADD(SDNode *N) {
617 SDOperand N0 = N->getOperand(0);
618 SDOperand N1 = N->getOperand(1);
619 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
620 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
621 MVT::ValueType VT = N0.getValueType();
623 // fold (add c1, c2) -> c1+c2
625 return DAG.getNode(ISD::ADD, VT, N0, N1);
626 // canonicalize constant to RHS
628 return DAG.getNode(ISD::ADD, VT, N1, N0);
629 // fold (add x, 0) -> x
630 if (N1C && N1C->isNullValue())
632 // fold ((c1-A)+c2) -> (c1+c2)-A
633 if (N1C && N0.getOpcode() == ISD::SUB)
634 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
635 return DAG.getNode(ISD::SUB, VT,
636 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
639 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
642 // fold ((0-A) + B) -> B-A
643 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
644 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
645 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
646 // fold (A + (0-B)) -> A-B
647 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
648 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
649 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
650 // fold (A+(B-A)) -> B
651 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
652 return N1.getOperand(0);
654 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
655 return SDOperand(N, 0);
657 // fold (a+b) -> (a|b) iff a and b share no bits.
658 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
659 uint64_t LHSZero, LHSOne;
660 uint64_t RHSZero, RHSOne;
661 uint64_t Mask = MVT::getIntVTBitMask(VT);
662 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
664 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
666 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
667 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
668 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
669 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
670 return DAG.getNode(ISD::OR, VT, N0, N1);
677 SDOperand DAGCombiner::visitSUB(SDNode *N) {
678 SDOperand N0 = N->getOperand(0);
679 SDOperand N1 = N->getOperand(1);
680 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
681 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
682 MVT::ValueType VT = N0.getValueType();
684 // fold (sub x, x) -> 0
686 return DAG.getConstant(0, N->getValueType(0));
687 // fold (sub c1, c2) -> c1-c2
689 return DAG.getNode(ISD::SUB, VT, N0, N1);
690 // fold (sub x, c) -> (add x, -c)
692 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
694 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
695 return N0.getOperand(1);
697 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
698 return N0.getOperand(0);
702 SDOperand DAGCombiner::visitMUL(SDNode *N) {
703 SDOperand N0 = N->getOperand(0);
704 SDOperand N1 = N->getOperand(1);
705 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
706 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
707 MVT::ValueType VT = N0.getValueType();
709 // fold (mul c1, c2) -> c1*c2
711 return DAG.getNode(ISD::MUL, VT, N0, N1);
712 // canonicalize constant to RHS
714 return DAG.getNode(ISD::MUL, VT, N1, N0);
715 // fold (mul x, 0) -> 0
716 if (N1C && N1C->isNullValue())
718 // fold (mul x, -1) -> 0-x
719 if (N1C && N1C->isAllOnesValue())
720 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
721 // fold (mul x, (1 << c)) -> x << c
722 if (N1C && isPowerOf2_64(N1C->getValue()))
723 return DAG.getNode(ISD::SHL, VT, N0,
724 DAG.getConstant(Log2_64(N1C->getValue()),
725 TLI.getShiftAmountTy()));
726 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
727 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
728 // FIXME: If the input is something that is easily negated (e.g. a
729 // single-use add), we should put the negate there.
730 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
731 DAG.getNode(ISD::SHL, VT, N0,
732 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
733 TLI.getShiftAmountTy())));
736 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
737 if (N1C && N0.getOpcode() == ISD::SHL &&
738 isa<ConstantSDNode>(N0.getOperand(1))) {
739 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
740 AddToWorkList(C3.Val);
741 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
744 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
747 SDOperand Sh(0,0), Y(0,0);
748 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
749 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
750 N0.Val->hasOneUse()) {
752 } else if (N1.getOpcode() == ISD::SHL &&
753 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
757 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
758 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
761 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
762 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
763 isa<ConstantSDNode>(N0.getOperand(1))) {
764 return DAG.getNode(ISD::ADD, VT,
765 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
766 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
770 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
776 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
777 SDOperand N0 = N->getOperand(0);
778 SDOperand N1 = N->getOperand(1);
779 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
780 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
781 MVT::ValueType VT = N->getValueType(0);
783 // fold (sdiv c1, c2) -> c1/c2
784 if (N0C && N1C && !N1C->isNullValue())
785 return DAG.getNode(ISD::SDIV, VT, N0, N1);
786 // fold (sdiv X, 1) -> X
787 if (N1C && N1C->getSignExtended() == 1LL)
789 // fold (sdiv X, -1) -> 0-X
790 if (N1C && N1C->isAllOnesValue())
791 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
792 // If we know the sign bits of both operands are zero, strength reduce to a
793 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
794 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
795 if (TLI.MaskedValueIsZero(N1, SignBit) &&
796 TLI.MaskedValueIsZero(N0, SignBit))
797 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
798 // fold (sdiv X, pow2) -> simple ops after legalize
799 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
800 (isPowerOf2_64(N1C->getSignExtended()) ||
801 isPowerOf2_64(-N1C->getSignExtended()))) {
802 // If dividing by powers of two is cheap, then don't perform the following
804 if (TLI.isPow2DivCheap())
806 int64_t pow2 = N1C->getSignExtended();
807 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
808 unsigned lg2 = Log2_64(abs2);
809 // Splat the sign bit into the register
810 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
811 DAG.getConstant(MVT::getSizeInBits(VT)-1,
812 TLI.getShiftAmountTy()));
813 AddToWorkList(SGN.Val);
814 // Add (N0 < 0) ? abs2 - 1 : 0;
815 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
816 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
817 TLI.getShiftAmountTy()));
818 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
819 AddToWorkList(SRL.Val);
820 AddToWorkList(ADD.Val); // Divide by pow2
821 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
822 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
823 // If we're dividing by a positive value, we're done. Otherwise, we must
824 // negate the result.
827 AddToWorkList(SRA.Val);
828 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
830 // if integer divide is expensive and we satisfy the requirements, emit an
831 // alternate sequence.
832 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
833 !TLI.isIntDivCheap()) {
834 SDOperand Op = BuildSDIV(N);
835 if (Op.Val) return Op;
840 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
841 SDOperand N0 = N->getOperand(0);
842 SDOperand N1 = N->getOperand(1);
843 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
844 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
845 MVT::ValueType VT = N->getValueType(0);
847 // fold (udiv c1, c2) -> c1/c2
848 if (N0C && N1C && !N1C->isNullValue())
849 return DAG.getNode(ISD::UDIV, VT, N0, N1);
850 // fold (udiv x, (1 << c)) -> x >>u c
851 if (N1C && isPowerOf2_64(N1C->getValue()))
852 return DAG.getNode(ISD::SRL, VT, N0,
853 DAG.getConstant(Log2_64(N1C->getValue()),
854 TLI.getShiftAmountTy()));
855 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
856 if (N1.getOpcode() == ISD::SHL) {
857 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
858 if (isPowerOf2_64(SHC->getValue())) {
859 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
860 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
861 DAG.getConstant(Log2_64(SHC->getValue()),
863 AddToWorkList(Add.Val);
864 return DAG.getNode(ISD::SRL, VT, N0, Add);
868 // fold (udiv x, c) -> alternate
869 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
870 SDOperand Op = BuildUDIV(N);
871 if (Op.Val) return Op;
876 SDOperand DAGCombiner::visitSREM(SDNode *N) {
877 SDOperand N0 = N->getOperand(0);
878 SDOperand N1 = N->getOperand(1);
879 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
880 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
881 MVT::ValueType VT = N->getValueType(0);
883 // fold (srem c1, c2) -> c1%c2
884 if (N0C && N1C && !N1C->isNullValue())
885 return DAG.getNode(ISD::SREM, VT, N0, N1);
886 // If we know the sign bits of both operands are zero, strength reduce to a
887 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
888 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
889 if (TLI.MaskedValueIsZero(N1, SignBit) &&
890 TLI.MaskedValueIsZero(N0, SignBit))
891 return DAG.getNode(ISD::UREM, VT, N0, N1);
895 SDOperand DAGCombiner::visitUREM(SDNode *N) {
896 SDOperand N0 = N->getOperand(0);
897 SDOperand N1 = N->getOperand(1);
898 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
899 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
900 MVT::ValueType VT = N->getValueType(0);
902 // fold (urem c1, c2) -> c1%c2
903 if (N0C && N1C && !N1C->isNullValue())
904 return DAG.getNode(ISD::UREM, VT, N0, N1);
905 // fold (urem x, pow2) -> (and x, pow2-1)
906 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
907 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
908 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
909 if (N1.getOpcode() == ISD::SHL) {
910 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
911 if (isPowerOf2_64(SHC->getValue())) {
912 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
913 AddToWorkList(Add.Val);
914 return DAG.getNode(ISD::AND, VT, N0, Add);
921 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
922 SDOperand N0 = N->getOperand(0);
923 SDOperand N1 = N->getOperand(1);
924 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
926 // fold (mulhs x, 0) -> 0
927 if (N1C && N1C->isNullValue())
929 // fold (mulhs x, 1) -> (sra x, size(x)-1)
930 if (N1C && N1C->getValue() == 1)
931 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
932 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
933 TLI.getShiftAmountTy()));
937 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
938 SDOperand N0 = N->getOperand(0);
939 SDOperand N1 = N->getOperand(1);
940 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
942 // fold (mulhu x, 0) -> 0
943 if (N1C && N1C->isNullValue())
945 // fold (mulhu x, 1) -> 0
946 if (N1C && N1C->getValue() == 1)
947 return DAG.getConstant(0, N0.getValueType());
951 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
952 /// two operands of the same opcode, try to simplify it.
953 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
954 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
955 MVT::ValueType VT = N0.getValueType();
956 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
958 // For each of OP in AND/OR/XOR:
959 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
960 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
961 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
962 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
963 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
964 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
965 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
966 SDOperand ORNode = DAG.getNode(N->getOpcode(),
967 N0.getOperand(0).getValueType(),
968 N0.getOperand(0), N1.getOperand(0));
969 AddToWorkList(ORNode.Val);
970 return DAG.getNode(N0.getOpcode(), VT, ORNode);
973 // For each of OP in SHL/SRL/SRA/AND...
974 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
975 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
976 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
977 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
978 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
979 N0.getOperand(1) == N1.getOperand(1)) {
980 SDOperand ORNode = DAG.getNode(N->getOpcode(),
981 N0.getOperand(0).getValueType(),
982 N0.getOperand(0), N1.getOperand(0));
983 AddToWorkList(ORNode.Val);
984 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
990 SDOperand DAGCombiner::visitAND(SDNode *N) {
991 SDOperand N0 = N->getOperand(0);
992 SDOperand N1 = N->getOperand(1);
993 SDOperand LL, LR, RL, RR, CC0, CC1;
994 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
995 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
996 MVT::ValueType VT = N1.getValueType();
997 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
999 // fold (and c1, c2) -> c1&c2
1001 return DAG.getNode(ISD::AND, VT, N0, N1);
1002 // canonicalize constant to RHS
1004 return DAG.getNode(ISD::AND, VT, N1, N0);
1005 // fold (and x, -1) -> x
1006 if (N1C && N1C->isAllOnesValue())
1008 // if (and x, c) is known to be zero, return 0
1009 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1010 return DAG.getConstant(0, VT);
1012 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1015 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1016 if (N1C && N0.getOpcode() == ISD::OR)
1017 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1018 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1020 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1021 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1022 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1023 if (TLI.MaskedValueIsZero(N0.getOperand(0),
1024 ~N1C->getValue() & InMask)) {
1025 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1028 // Replace uses of the AND with uses of the Zero extend node.
1031 // We actually want to replace all uses of the any_extend with the
1032 // zero_extend, to avoid duplicating things. This will later cause this
1033 // AND to be folded.
1034 CombineTo(N0.Val, Zext);
1035 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1038 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1039 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1040 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1041 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1043 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1044 MVT::isInteger(LL.getValueType())) {
1045 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1046 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1047 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1048 AddToWorkList(ORNode.Val);
1049 return DAG.getSetCC(VT, ORNode, LR, Op1);
1051 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1052 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1053 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1054 AddToWorkList(ANDNode.Val);
1055 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1057 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1058 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1059 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1060 AddToWorkList(ORNode.Val);
1061 return DAG.getSetCC(VT, ORNode, LR, Op1);
1064 // canonicalize equivalent to ll == rl
1065 if (LL == RR && LR == RL) {
1066 Op1 = ISD::getSetCCSwappedOperands(Op1);
1069 if (LL == RL && LR == RR) {
1070 bool isInteger = MVT::isInteger(LL.getValueType());
1071 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1072 if (Result != ISD::SETCC_INVALID)
1073 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1077 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1078 if (N0.getOpcode() == N1.getOpcode()) {
1079 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1080 if (Tmp.Val) return Tmp;
1083 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1084 // fold (and (sra)) -> (and (srl)) when possible.
1085 if (!MVT::isVector(VT) &&
1086 SimplifyDemandedBits(SDOperand(N, 0)))
1087 return SDOperand(N, 0);
1088 // fold (zext_inreg (extload x)) -> (zextload x)
1089 if (N0.getOpcode() == ISD::EXTLOAD) {
1090 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1091 // If we zero all the possible extended bits, then we can turn this into
1092 // a zextload if we are running before legalize or the operation is legal.
1093 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1094 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1095 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1096 N0.getOperand(1), N0.getOperand(2),
1099 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1100 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1103 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1104 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) {
1105 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1106 // If we zero all the possible extended bits, then we can turn this into
1107 // a zextload if we are running before legalize or the operation is legal.
1108 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1109 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1110 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1111 N0.getOperand(1), N0.getOperand(2),
1114 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1115 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1119 // fold (and (load x), 255) -> (zextload x, i8)
1120 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1122 (N0.getOpcode() == ISD::LOAD || N0.getOpcode() == ISD::EXTLOAD ||
1123 N0.getOpcode() == ISD::ZEXTLOAD) &&
1125 MVT::ValueType EVT, LoadedVT;
1126 if (N1C->getValue() == 255)
1128 else if (N1C->getValue() == 65535)
1130 else if (N1C->getValue() == ~0U)
1135 LoadedVT = N0.getOpcode() == ISD::LOAD ? VT :
1136 cast<VTSDNode>(N0.getOperand(3))->getVT();
1137 if (EVT != MVT::Other && LoadedVT > EVT &&
1138 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1139 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1140 // For big endian targets, we need to add an offset to the pointer to load
1141 // the correct bytes. For little endian systems, we merely need to read
1142 // fewer bytes from the same pointer.
1144 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1145 SDOperand NewPtr = N0.getOperand(1);
1146 if (!TLI.isLittleEndian())
1147 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1148 DAG.getConstant(PtrOff, PtrType));
1149 AddToWorkList(NewPtr.Val);
1151 DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), NewPtr,
1152 N0.getOperand(2), EVT);
1154 CombineTo(N0.Val, Load, Load.getValue(1));
1155 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1162 SDOperand DAGCombiner::visitOR(SDNode *N) {
1163 SDOperand N0 = N->getOperand(0);
1164 SDOperand N1 = N->getOperand(1);
1165 SDOperand LL, LR, RL, RR, CC0, CC1;
1166 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1167 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1168 MVT::ValueType VT = N1.getValueType();
1169 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1171 // fold (or c1, c2) -> c1|c2
1173 return DAG.getNode(ISD::OR, VT, N0, N1);
1174 // canonicalize constant to RHS
1176 return DAG.getNode(ISD::OR, VT, N1, N0);
1177 // fold (or x, 0) -> x
1178 if (N1C && N1C->isNullValue())
1180 // fold (or x, -1) -> -1
1181 if (N1C && N1C->isAllOnesValue())
1183 // fold (or x, c) -> c iff (x & ~c) == 0
1185 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1188 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1191 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1192 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1193 isa<ConstantSDNode>(N0.getOperand(1))) {
1194 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1195 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1197 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1199 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1200 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1201 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1202 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1204 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1205 MVT::isInteger(LL.getValueType())) {
1206 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1207 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1208 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1209 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1210 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1211 AddToWorkList(ORNode.Val);
1212 return DAG.getSetCC(VT, ORNode, LR, Op1);
1214 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1215 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1216 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1217 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1218 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1219 AddToWorkList(ANDNode.Val);
1220 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1223 // canonicalize equivalent to ll == rl
1224 if (LL == RR && LR == RL) {
1225 Op1 = ISD::getSetCCSwappedOperands(Op1);
1228 if (LL == RL && LR == RR) {
1229 bool isInteger = MVT::isInteger(LL.getValueType());
1230 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1231 if (Result != ISD::SETCC_INVALID)
1232 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1236 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1237 if (N0.getOpcode() == N1.getOpcode()) {
1238 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1239 if (Tmp.Val) return Tmp;
1242 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1243 if (N0.getOpcode() == ISD::AND &&
1244 N1.getOpcode() == ISD::AND &&
1245 N0.getOperand(1).getOpcode() == ISD::Constant &&
1246 N1.getOperand(1).getOpcode() == ISD::Constant &&
1247 // Don't increase # computations.
1248 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1249 // We can only do this xform if we know that bits from X that are set in C2
1250 // but not in C1 are already zero. Likewise for Y.
1251 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1252 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1254 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1255 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1256 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1257 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1262 // See if this is some rotate idiom.
1263 if (SDNode *Rot = MatchRotate(N0, N1))
1264 return SDOperand(Rot, 0);
1270 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1271 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1272 if (Op.getOpcode() == ISD::AND) {
1273 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1274 Mask = Op.getOperand(1);
1275 Op = Op.getOperand(0);
1281 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1289 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1290 // idioms for rotate, and if the target supports rotation instructions, generate
1292 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1293 // Must be a legal type. Expanded an promoted things won't work with rotates.
1294 MVT::ValueType VT = LHS.getValueType();
1295 if (!TLI.isTypeLegal(VT)) return 0;
1297 // The target must have at least one rotate flavor.
1298 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1299 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1300 if (!HasROTL && !HasROTR) return 0;
1302 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1303 SDOperand LHSShift; // The shift.
1304 SDOperand LHSMask; // AND value if any.
1305 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1306 return 0; // Not part of a rotate.
1308 SDOperand RHSShift; // The shift.
1309 SDOperand RHSMask; // AND value if any.
1310 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1311 return 0; // Not part of a rotate.
1313 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1314 return 0; // Not shifting the same value.
1316 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1317 return 0; // Shifts must disagree.
1319 // Canonicalize shl to left side in a shl/srl pair.
1320 if (RHSShift.getOpcode() == ISD::SHL) {
1321 std::swap(LHS, RHS);
1322 std::swap(LHSShift, RHSShift);
1323 std::swap(LHSMask , RHSMask );
1326 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1328 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1329 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1330 if (LHSShift.getOperand(1).getOpcode() == ISD::Constant &&
1331 RHSShift.getOperand(1).getOpcode() == ISD::Constant) {
1332 uint64_t LShVal = cast<ConstantSDNode>(LHSShift.getOperand(1))->getValue();
1333 uint64_t RShVal = cast<ConstantSDNode>(RHSShift.getOperand(1))->getValue();
1334 if ((LShVal + RShVal) != OpSizeInBits)
1339 Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1340 LHSShift.getOperand(1));
1342 Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1343 RHSShift.getOperand(1));
1345 // If there is an AND of either shifted operand, apply it to the result.
1346 if (LHSMask.Val || RHSMask.Val) {
1347 uint64_t Mask = MVT::getIntVTBitMask(VT);
1350 uint64_t RHSBits = (1ULL << LShVal)-1;
1351 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1354 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1355 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1358 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1364 // If there is a mask here, and we have a variable shift, we can't be sure
1365 // that we're masking out the right stuff.
1366 if (LHSMask.Val || RHSMask.Val)
1369 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1370 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1371 if (RHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1372 LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) {
1373 if (ConstantSDNode *SUBC =
1374 dyn_cast<ConstantSDNode>(RHSShift.getOperand(1).getOperand(0))) {
1375 if (SUBC->getValue() == OpSizeInBits)
1377 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1378 LHSShift.getOperand(1)).Val;
1380 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1381 LHSShift.getOperand(1)).Val;
1385 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1386 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1387 if (LHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1388 RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) {
1389 if (ConstantSDNode *SUBC =
1390 dyn_cast<ConstantSDNode>(LHSShift.getOperand(1).getOperand(0))) {
1391 if (SUBC->getValue() == OpSizeInBits)
1393 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1394 LHSShift.getOperand(1)).Val;
1396 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1397 RHSShift.getOperand(1)).Val;
1405 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1406 SDOperand N0 = N->getOperand(0);
1407 SDOperand N1 = N->getOperand(1);
1408 SDOperand LHS, RHS, CC;
1409 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1410 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1411 MVT::ValueType VT = N0.getValueType();
1413 // fold (xor c1, c2) -> c1^c2
1415 return DAG.getNode(ISD::XOR, VT, N0, N1);
1416 // canonicalize constant to RHS
1418 return DAG.getNode(ISD::XOR, VT, N1, N0);
1419 // fold (xor x, 0) -> x
1420 if (N1C && N1C->isNullValue())
1423 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1426 // fold !(x cc y) -> (x !cc y)
1427 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1428 bool isInt = MVT::isInteger(LHS.getValueType());
1429 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1431 if (N0.getOpcode() == ISD::SETCC)
1432 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1433 if (N0.getOpcode() == ISD::SELECT_CC)
1434 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1435 assert(0 && "Unhandled SetCC Equivalent!");
1438 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1439 if (N1C && N1C->getValue() == 1 &&
1440 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1441 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1442 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1443 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1444 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1445 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1446 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1447 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1450 // fold !(x or y) -> (!x and !y) iff x or y are constants
1451 if (N1C && N1C->isAllOnesValue() &&
1452 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1453 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1454 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1455 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1456 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1457 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1458 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1459 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1462 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1463 if (N1C && N0.getOpcode() == ISD::XOR) {
1464 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1465 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1467 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1468 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1470 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1471 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1473 // fold (xor x, x) -> 0
1475 if (!MVT::isVector(VT)) {
1476 return DAG.getConstant(0, VT);
1477 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1478 // Produce a vector of zeros.
1479 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
1480 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
1481 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1485 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
1486 if (N0.getOpcode() == N1.getOpcode()) {
1487 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1488 if (Tmp.Val) return Tmp;
1491 // Simplify the expression using non-local knowledge.
1492 if (!MVT::isVector(VT) &&
1493 SimplifyDemandedBits(SDOperand(N, 0)))
1494 return SDOperand(N, 0);
1499 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1500 SDOperand N0 = N->getOperand(0);
1501 SDOperand N1 = N->getOperand(1);
1502 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1503 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1504 MVT::ValueType VT = N0.getValueType();
1505 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1507 // fold (shl c1, c2) -> c1<<c2
1509 return DAG.getNode(ISD::SHL, VT, N0, N1);
1510 // fold (shl 0, x) -> 0
1511 if (N0C && N0C->isNullValue())
1513 // fold (shl x, c >= size(x)) -> undef
1514 if (N1C && N1C->getValue() >= OpSizeInBits)
1515 return DAG.getNode(ISD::UNDEF, VT);
1516 // fold (shl x, 0) -> x
1517 if (N1C && N1C->isNullValue())
1519 // if (shl x, c) is known to be zero, return 0
1520 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1521 return DAG.getConstant(0, VT);
1522 if (SimplifyDemandedBits(SDOperand(N, 0)))
1523 return SDOperand(N, 0);
1524 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1525 if (N1C && N0.getOpcode() == ISD::SHL &&
1526 N0.getOperand(1).getOpcode() == ISD::Constant) {
1527 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1528 uint64_t c2 = N1C->getValue();
1529 if (c1 + c2 > OpSizeInBits)
1530 return DAG.getConstant(0, VT);
1531 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1532 DAG.getConstant(c1 + c2, N1.getValueType()));
1534 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1535 // (srl (and x, -1 << c1), c1-c2)
1536 if (N1C && N0.getOpcode() == ISD::SRL &&
1537 N0.getOperand(1).getOpcode() == ISD::Constant) {
1538 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1539 uint64_t c2 = N1C->getValue();
1540 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1541 DAG.getConstant(~0ULL << c1, VT));
1543 return DAG.getNode(ISD::SHL, VT, Mask,
1544 DAG.getConstant(c2-c1, N1.getValueType()));
1546 return DAG.getNode(ISD::SRL, VT, Mask,
1547 DAG.getConstant(c1-c2, N1.getValueType()));
1549 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1550 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1551 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1552 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1553 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
1554 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1555 isa<ConstantSDNode>(N0.getOperand(1))) {
1556 return DAG.getNode(ISD::ADD, VT,
1557 DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1),
1558 DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1));
1563 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1564 SDOperand N0 = N->getOperand(0);
1565 SDOperand N1 = N->getOperand(1);
1566 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1567 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1568 MVT::ValueType VT = N0.getValueType();
1570 // fold (sra c1, c2) -> c1>>c2
1572 return DAG.getNode(ISD::SRA, VT, N0, N1);
1573 // fold (sra 0, x) -> 0
1574 if (N0C && N0C->isNullValue())
1576 // fold (sra -1, x) -> -1
1577 if (N0C && N0C->isAllOnesValue())
1579 // fold (sra x, c >= size(x)) -> undef
1580 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
1581 return DAG.getNode(ISD::UNDEF, VT);
1582 // fold (sra x, 0) -> x
1583 if (N1C && N1C->isNullValue())
1585 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
1587 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
1588 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
1591 default: EVT = MVT::Other; break;
1592 case 1: EVT = MVT::i1; break;
1593 case 8: EVT = MVT::i8; break;
1594 case 16: EVT = MVT::i16; break;
1595 case 32: EVT = MVT::i32; break;
1597 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
1598 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1599 DAG.getValueType(EVT));
1602 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
1603 if (N1C && N0.getOpcode() == ISD::SRA) {
1604 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1605 unsigned Sum = N1C->getValue() + C1->getValue();
1606 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
1607 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
1608 DAG.getConstant(Sum, N1C->getValueType(0)));
1612 // Simplify, based on bits shifted out of the LHS.
1613 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
1614 return SDOperand(N, 0);
1617 // If the sign bit is known to be zero, switch this to a SRL.
1618 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
1619 return DAG.getNode(ISD::SRL, VT, N0, N1);
1623 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1624 SDOperand N0 = N->getOperand(0);
1625 SDOperand N1 = N->getOperand(1);
1626 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1627 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1628 MVT::ValueType VT = N0.getValueType();
1629 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1631 // fold (srl c1, c2) -> c1 >>u c2
1633 return DAG.getNode(ISD::SRL, VT, N0, N1);
1634 // fold (srl 0, x) -> 0
1635 if (N0C && N0C->isNullValue())
1637 // fold (srl x, c >= size(x)) -> undef
1638 if (N1C && N1C->getValue() >= OpSizeInBits)
1639 return DAG.getNode(ISD::UNDEF, VT);
1640 // fold (srl x, 0) -> x
1641 if (N1C && N1C->isNullValue())
1643 // if (srl x, c) is known to be zero, return 0
1644 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1645 return DAG.getConstant(0, VT);
1646 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1647 if (N1C && N0.getOpcode() == ISD::SRL &&
1648 N0.getOperand(1).getOpcode() == ISD::Constant) {
1649 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1650 uint64_t c2 = N1C->getValue();
1651 if (c1 + c2 > OpSizeInBits)
1652 return DAG.getConstant(0, VT);
1653 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1654 DAG.getConstant(c1 + c2, N1.getValueType()));
1657 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
1658 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1659 // Shifting in all undef bits?
1660 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
1661 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
1662 return DAG.getNode(ISD::UNDEF, VT);
1664 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
1665 AddToWorkList(SmallShift.Val);
1666 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
1669 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
1670 if (N1C && N0.getOpcode() == ISD::CTLZ &&
1671 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
1672 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
1673 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
1675 // If any of the input bits are KnownOne, then the input couldn't be all
1676 // zeros, thus the result of the srl will always be zero.
1677 if (KnownOne) return DAG.getConstant(0, VT);
1679 // If all of the bits input the to ctlz node are known to be zero, then
1680 // the result of the ctlz is "32" and the result of the shift is one.
1681 uint64_t UnknownBits = ~KnownZero & Mask;
1682 if (UnknownBits == 0) return DAG.getConstant(1, VT);
1684 // Otherwise, check to see if there is exactly one bit input to the ctlz.
1685 if ((UnknownBits & (UnknownBits-1)) == 0) {
1686 // Okay, we know that only that the single bit specified by UnknownBits
1687 // could be set on input to the CTLZ node. If this bit is set, the SRL
1688 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
1689 // to an SRL,XOR pair, which is likely to simplify more.
1690 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
1691 SDOperand Op = N0.getOperand(0);
1693 Op = DAG.getNode(ISD::SRL, VT, Op,
1694 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
1695 AddToWorkList(Op.Val);
1697 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
1704 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1705 SDOperand N0 = N->getOperand(0);
1706 MVT::ValueType VT = N->getValueType(0);
1708 // fold (ctlz c1) -> c2
1709 if (isa<ConstantSDNode>(N0))
1710 return DAG.getNode(ISD::CTLZ, VT, N0);
1714 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1715 SDOperand N0 = N->getOperand(0);
1716 MVT::ValueType VT = N->getValueType(0);
1718 // fold (cttz c1) -> c2
1719 if (isa<ConstantSDNode>(N0))
1720 return DAG.getNode(ISD::CTTZ, VT, N0);
1724 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1725 SDOperand N0 = N->getOperand(0);
1726 MVT::ValueType VT = N->getValueType(0);
1728 // fold (ctpop c1) -> c2
1729 if (isa<ConstantSDNode>(N0))
1730 return DAG.getNode(ISD::CTPOP, VT, N0);
1734 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1735 SDOperand N0 = N->getOperand(0);
1736 SDOperand N1 = N->getOperand(1);
1737 SDOperand N2 = N->getOperand(2);
1738 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1739 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1740 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1741 MVT::ValueType VT = N->getValueType(0);
1743 // fold select C, X, X -> X
1746 // fold select true, X, Y -> X
1747 if (N0C && !N0C->isNullValue())
1749 // fold select false, X, Y -> Y
1750 if (N0C && N0C->isNullValue())
1752 // fold select C, 1, X -> C | X
1753 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1754 return DAG.getNode(ISD::OR, VT, N0, N2);
1755 // fold select C, 0, X -> ~C & X
1756 // FIXME: this should check for C type == X type, not i1?
1757 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1758 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1759 AddToWorkList(XORNode.Val);
1760 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1762 // fold select C, X, 1 -> ~C | X
1763 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1764 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1765 AddToWorkList(XORNode.Val);
1766 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1768 // fold select C, X, 0 -> C & X
1769 // FIXME: this should check for C type == X type, not i1?
1770 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1771 return DAG.getNode(ISD::AND, VT, N0, N1);
1772 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1773 if (MVT::i1 == VT && N0 == N1)
1774 return DAG.getNode(ISD::OR, VT, N0, N2);
1775 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1776 if (MVT::i1 == VT && N0 == N2)
1777 return DAG.getNode(ISD::AND, VT, N0, N1);
1779 // If we can fold this based on the true/false value, do so.
1780 if (SimplifySelectOps(N, N1, N2))
1781 return SDOperand(N, 0); // Don't revisit N.
1783 // fold selects based on a setcc into other things, such as min/max/abs
1784 if (N0.getOpcode() == ISD::SETCC)
1786 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1787 // having to say they don't support SELECT_CC on every type the DAG knows
1788 // about, since there is no way to mark an opcode illegal at all value types
1789 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1790 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1791 N1, N2, N0.getOperand(2));
1793 return SimplifySelect(N0, N1, N2);
1797 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1798 SDOperand N0 = N->getOperand(0);
1799 SDOperand N1 = N->getOperand(1);
1800 SDOperand N2 = N->getOperand(2);
1801 SDOperand N3 = N->getOperand(3);
1802 SDOperand N4 = N->getOperand(4);
1803 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1804 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1805 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1806 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1808 // fold select_cc lhs, rhs, x, x, cc -> x
1812 // Determine if the condition we're dealing with is constant
1813 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1815 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
1816 if (SCCC->getValue())
1817 return N2; // cond always true -> true val
1819 return N3; // cond always false -> false val
1822 // Fold to a simpler select_cc
1823 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
1824 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
1825 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
1828 // If we can fold this based on the true/false value, do so.
1829 if (SimplifySelectOps(N, N2, N3))
1830 return SDOperand(N, 0); // Don't revisit N.
1832 // fold select_cc into other things, such as min/max/abs
1833 return SimplifySelectCC(N0, N1, N2, N3, CC);
1836 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1837 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1838 cast<CondCodeSDNode>(N->getOperand(2))->get());
1841 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1842 SDOperand N0 = N->getOperand(0);
1843 MVT::ValueType VT = N->getValueType(0);
1845 // fold (sext c1) -> c1
1846 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
1847 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
1849 // fold (sext (sext x)) -> (sext x)
1850 // fold (sext (aext x)) -> (sext x)
1851 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1852 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1854 // fold (sext (truncate x)) -> (sextinreg x).
1855 if (N0.getOpcode() == ISD::TRUNCATE &&
1856 (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
1857 N0.getValueType()))) {
1858 SDOperand Op = N0.getOperand(0);
1859 if (Op.getValueType() < VT) {
1860 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
1861 } else if (Op.getValueType() > VT) {
1862 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
1864 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
1865 DAG.getValueType(N0.getValueType()));
1868 // fold (sext (load x)) -> (sext (truncate (sextload x)))
1869 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1870 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){
1871 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1872 N0.getOperand(1), N0.getOperand(2),
1874 CombineTo(N, ExtLoad);
1875 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1876 ExtLoad.getValue(1));
1877 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1880 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
1881 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
1882 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
1884 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1885 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1886 N0.getOperand(1), N0.getOperand(2), EVT);
1887 CombineTo(N, ExtLoad);
1888 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1889 ExtLoad.getValue(1));
1890 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1896 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1897 SDOperand N0 = N->getOperand(0);
1898 MVT::ValueType VT = N->getValueType(0);
1900 // fold (zext c1) -> c1
1901 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
1902 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1903 // fold (zext (zext x)) -> (zext x)
1904 // fold (zext (aext x)) -> (zext x)
1905 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1906 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1908 // fold (zext (truncate x)) -> (and x, mask)
1909 if (N0.getOpcode() == ISD::TRUNCATE &&
1910 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
1911 SDOperand Op = N0.getOperand(0);
1912 if (Op.getValueType() < VT) {
1913 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
1914 } else if (Op.getValueType() > VT) {
1915 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
1917 return DAG.getZeroExtendInReg(Op, N0.getValueType());
1920 // fold (zext (and (trunc x), cst)) -> (and x, cst).
1921 if (N0.getOpcode() == ISD::AND &&
1922 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
1923 N0.getOperand(1).getOpcode() == ISD::Constant) {
1924 SDOperand X = N0.getOperand(0).getOperand(0);
1925 if (X.getValueType() < VT) {
1926 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
1927 } else if (X.getValueType() > VT) {
1928 X = DAG.getNode(ISD::TRUNCATE, VT, X);
1930 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1931 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
1934 // fold (zext (load x)) -> (zext (truncate (zextload x)))
1935 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1936 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){
1937 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1938 N0.getOperand(1), N0.getOperand(2),
1940 CombineTo(N, ExtLoad);
1941 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1942 ExtLoad.getValue(1));
1943 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1946 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
1947 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
1948 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
1950 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1951 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1952 N0.getOperand(1), N0.getOperand(2), EVT);
1953 CombineTo(N, ExtLoad);
1954 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1955 ExtLoad.getValue(1));
1956 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1961 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
1962 SDOperand N0 = N->getOperand(0);
1963 MVT::ValueType VT = N->getValueType(0);
1965 // fold (aext c1) -> c1
1966 if (isa<ConstantSDNode>(N0))
1967 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
1968 // fold (aext (aext x)) -> (aext x)
1969 // fold (aext (zext x)) -> (zext x)
1970 // fold (aext (sext x)) -> (sext x)
1971 if (N0.getOpcode() == ISD::ANY_EXTEND ||
1972 N0.getOpcode() == ISD::ZERO_EXTEND ||
1973 N0.getOpcode() == ISD::SIGN_EXTEND)
1974 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
1976 // fold (aext (truncate x))
1977 if (N0.getOpcode() == ISD::TRUNCATE) {
1978 SDOperand TruncOp = N0.getOperand(0);
1979 if (TruncOp.getValueType() == VT)
1980 return TruncOp; // x iff x size == zext size.
1981 if (TruncOp.getValueType() > VT)
1982 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
1983 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
1986 // fold (aext (and (trunc x), cst)) -> (and x, cst).
1987 if (N0.getOpcode() == ISD::AND &&
1988 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
1989 N0.getOperand(1).getOpcode() == ISD::Constant) {
1990 SDOperand X = N0.getOperand(0).getOperand(0);
1991 if (X.getValueType() < VT) {
1992 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
1993 } else if (X.getValueType() > VT) {
1994 X = DAG.getNode(ISD::TRUNCATE, VT, X);
1996 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1997 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2000 // fold (aext (load x)) -> (aext (truncate (extload x)))
2001 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
2002 (!AfterLegalize||TLI.isOperationLegal(ISD::EXTLOAD, N0.getValueType()))) {
2003 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0),
2004 N0.getOperand(1), N0.getOperand(2),
2006 CombineTo(N, ExtLoad);
2007 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2008 ExtLoad.getValue(1));
2009 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2012 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2013 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2014 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2015 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD ||
2016 N0.getOpcode() == ISD::SEXTLOAD) &&
2018 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
2019 SDOperand ExtLoad = DAG.getExtLoad(N0.getOpcode(), VT, N0.getOperand(0),
2020 N0.getOperand(1), N0.getOperand(2), EVT);
2021 CombineTo(N, ExtLoad);
2022 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2023 ExtLoad.getValue(1));
2024 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2030 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
2031 SDOperand N0 = N->getOperand(0);
2032 SDOperand N1 = N->getOperand(1);
2033 MVT::ValueType VT = N->getValueType(0);
2034 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
2035 unsigned EVTBits = MVT::getSizeInBits(EVT);
2037 // fold (sext_in_reg c1) -> c1
2038 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
2039 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
2041 // If the input is already sign extended, just drop the extension.
2042 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
2045 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
2046 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2047 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
2048 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
2051 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
2052 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
2053 return DAG.getZeroExtendInReg(N0, EVT);
2055 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
2056 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
2057 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
2058 if (N0.getOpcode() == ISD::SRL) {
2059 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2060 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
2061 // We can turn this into an SRA iff the input to the SRL is already sign
2063 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0));
2064 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
2065 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
2069 // fold (sext_inreg (extload x)) -> (sextload x)
2070 if (N0.getOpcode() == ISD::EXTLOAD &&
2071 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
2072 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
2073 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
2074 N0.getOperand(1), N0.getOperand(2),
2076 CombineTo(N, ExtLoad);
2077 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2078 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2080 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
2081 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() &&
2082 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
2083 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
2084 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
2085 N0.getOperand(1), N0.getOperand(2),
2087 CombineTo(N, ExtLoad);
2088 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2089 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2094 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
2095 SDOperand N0 = N->getOperand(0);
2096 MVT::ValueType VT = N->getValueType(0);
2099 if (N0.getValueType() == N->getValueType(0))
2101 // fold (truncate c1) -> c1
2102 if (isa<ConstantSDNode>(N0))
2103 return DAG.getNode(ISD::TRUNCATE, VT, N0);
2104 // fold (truncate (truncate x)) -> (truncate x)
2105 if (N0.getOpcode() == ISD::TRUNCATE)
2106 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2107 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
2108 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
2109 N0.getOpcode() == ISD::ANY_EXTEND) {
2110 if (N0.getValueType() < VT)
2111 // if the source is smaller than the dest, we still need an extend
2112 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2113 else if (N0.getValueType() > VT)
2114 // if the source is larger than the dest, than we just need the truncate
2115 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2117 // if the source and dest are the same type, we can drop both the extend
2119 return N0.getOperand(0);
2121 // fold (truncate (load x)) -> (smaller load x)
2122 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
2123 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
2124 "Cannot truncate to larger type!");
2125 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2126 // For big endian targets, we need to add an offset to the pointer to load
2127 // the correct bytes. For little endian systems, we merely need to read
2128 // fewer bytes from the same pointer.
2130 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
2131 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) :
2132 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1),
2133 DAG.getConstant(PtrOff, PtrType));
2134 AddToWorkList(NewPtr.Val);
2135 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2));
2137 CombineTo(N0.Val, Load, Load.getValue(1));
2138 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2143 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
2144 SDOperand N0 = N->getOperand(0);
2145 MVT::ValueType VT = N->getValueType(0);
2147 // If the input is a constant, let getNode() fold it.
2148 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
2149 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2150 if (Res.Val != N) return Res;
2153 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
2154 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
2156 // fold (conv (load x)) -> (load (conv*)x)
2157 // FIXME: These xforms need to know that the resultant load doesn't need a
2158 // higher alignment than the original!
2159 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
2160 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1),
2163 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
2171 SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) {
2172 SDOperand N0 = N->getOperand(0);
2173 MVT::ValueType VT = N->getValueType(0);
2175 // If the input is a VBUILD_VECTOR with all constant elements, fold this now.
2176 // First check to see if this is all constant.
2177 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() &&
2178 VT == MVT::Vector) {
2179 bool isSimple = true;
2180 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i)
2181 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
2182 N0.getOperand(i).getOpcode() != ISD::Constant &&
2183 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
2188 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT();
2189 if (isSimple && !MVT::isVector(DestEltVT)) {
2190 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT);
2197 /// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector
2198 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
2199 /// destination element value type.
2200 SDOperand DAGCombiner::
2201 ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
2202 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
2204 // If this is already the right type, we're done.
2205 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
2207 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
2208 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
2210 // If this is a conversion of N elements of one type to N elements of another
2211 // type, convert each element. This handles FP<->INT cases.
2212 if (SrcBitSize == DstBitSize) {
2213 SmallVector<SDOperand, 8> Ops;
2214 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2215 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
2216 AddToWorkList(Ops.back().Val);
2218 Ops.push_back(*(BV->op_end()-2)); // Add num elements.
2219 Ops.push_back(DAG.getValueType(DstEltVT));
2220 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2223 // Otherwise, we're growing or shrinking the elements. To avoid having to
2224 // handle annoying details of growing/shrinking FP values, we convert them to
2226 if (MVT::isFloatingPoint(SrcEltVT)) {
2227 // Convert the input float vector to a int vector where the elements are the
2229 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
2230 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2231 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val;
2235 // Now we know the input is an integer vector. If the output is a FP type,
2236 // convert to integer first, then to FP of the right size.
2237 if (MVT::isFloatingPoint(DstEltVT)) {
2238 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
2239 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2240 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val;
2242 // Next, convert to FP elements of the same size.
2243 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT);
2246 // Okay, we know the src/dst types are both integers of differing types.
2247 // Handling growing first.
2248 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
2249 if (SrcBitSize < DstBitSize) {
2250 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
2252 SmallVector<SDOperand, 8> Ops;
2253 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e;
2254 i += NumInputsPerOutput) {
2255 bool isLE = TLI.isLittleEndian();
2256 uint64_t NewBits = 0;
2257 bool EltIsUndef = true;
2258 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
2259 // Shift the previously computed bits over.
2260 NewBits <<= SrcBitSize;
2261 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
2262 if (Op.getOpcode() == ISD::UNDEF) continue;
2265 NewBits |= cast<ConstantSDNode>(Op)->getValue();
2269 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2271 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
2274 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2275 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2276 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2279 // Finally, this must be the case where we are shrinking elements: each input
2280 // turns into multiple outputs.
2281 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
2282 SmallVector<SDOperand, 8> Ops;
2283 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2284 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
2285 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
2286 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2289 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
2291 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
2292 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
2293 OpVal >>= DstBitSize;
2294 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
2297 // For big endian targets, swap the order of the pieces of each element.
2298 if (!TLI.isLittleEndian())
2299 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
2301 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2302 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2303 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2308 SDOperand DAGCombiner::visitFADD(SDNode *N) {
2309 SDOperand N0 = N->getOperand(0);
2310 SDOperand N1 = N->getOperand(1);
2311 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2312 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2313 MVT::ValueType VT = N->getValueType(0);
2315 // fold (fadd c1, c2) -> c1+c2
2317 return DAG.getNode(ISD::FADD, VT, N0, N1);
2318 // canonicalize constant to RHS
2319 if (N0CFP && !N1CFP)
2320 return DAG.getNode(ISD::FADD, VT, N1, N0);
2321 // fold (A + (-B)) -> A-B
2322 if (N1.getOpcode() == ISD::FNEG)
2323 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
2324 // fold ((-A) + B) -> B-A
2325 if (N0.getOpcode() == ISD::FNEG)
2326 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
2330 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
2331 SDOperand N0 = N->getOperand(0);
2332 SDOperand N1 = N->getOperand(1);
2333 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2334 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2335 MVT::ValueType VT = N->getValueType(0);
2337 // fold (fsub c1, c2) -> c1-c2
2339 return DAG.getNode(ISD::FSUB, VT, N0, N1);
2340 // fold (A-(-B)) -> A+B
2341 if (N1.getOpcode() == ISD::FNEG)
2342 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
2346 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
2347 SDOperand N0 = N->getOperand(0);
2348 SDOperand N1 = N->getOperand(1);
2349 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2350 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2351 MVT::ValueType VT = N->getValueType(0);
2353 // fold (fmul c1, c2) -> c1*c2
2355 return DAG.getNode(ISD::FMUL, VT, N0, N1);
2356 // canonicalize constant to RHS
2357 if (N0CFP && !N1CFP)
2358 return DAG.getNode(ISD::FMUL, VT, N1, N0);
2359 // fold (fmul X, 2.0) -> (fadd X, X)
2360 if (N1CFP && N1CFP->isExactlyValue(+2.0))
2361 return DAG.getNode(ISD::FADD, VT, N0, N0);
2365 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
2366 SDOperand N0 = N->getOperand(0);
2367 SDOperand N1 = N->getOperand(1);
2368 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2369 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2370 MVT::ValueType VT = N->getValueType(0);
2372 // fold (fdiv c1, c2) -> c1/c2
2374 return DAG.getNode(ISD::FDIV, VT, N0, N1);
2378 SDOperand DAGCombiner::visitFREM(SDNode *N) {
2379 SDOperand N0 = N->getOperand(0);
2380 SDOperand N1 = N->getOperand(1);
2381 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2382 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2383 MVT::ValueType VT = N->getValueType(0);
2385 // fold (frem c1, c2) -> fmod(c1,c2)
2387 return DAG.getNode(ISD::FREM, VT, N0, N1);
2391 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
2392 SDOperand N0 = N->getOperand(0);
2393 SDOperand N1 = N->getOperand(1);
2394 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2395 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2396 MVT::ValueType VT = N->getValueType(0);
2398 if (N0CFP && N1CFP) // Constant fold
2399 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
2402 // copysign(x, c1) -> fabs(x) iff ispos(c1)
2403 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
2408 u.d = N1CFP->getValue();
2410 return DAG.getNode(ISD::FABS, VT, N0);
2412 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
2415 // copysign(fabs(x), y) -> copysign(x, y)
2416 // copysign(fneg(x), y) -> copysign(x, y)
2417 // copysign(copysign(x,z), y) -> copysign(x, y)
2418 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
2419 N0.getOpcode() == ISD::FCOPYSIGN)
2420 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
2422 // copysign(x, abs(y)) -> abs(x)
2423 if (N1.getOpcode() == ISD::FABS)
2424 return DAG.getNode(ISD::FABS, VT, N0);
2426 // copysign(x, copysign(y,z)) -> copysign(x, z)
2427 if (N1.getOpcode() == ISD::FCOPYSIGN)
2428 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
2430 // copysign(x, fp_extend(y)) -> copysign(x, y)
2431 // copysign(x, fp_round(y)) -> copysign(x, y)
2432 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
2433 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
2440 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
2441 SDOperand N0 = N->getOperand(0);
2442 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2443 MVT::ValueType VT = N->getValueType(0);
2445 // fold (sint_to_fp c1) -> c1fp
2447 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
2451 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
2452 SDOperand N0 = N->getOperand(0);
2453 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2454 MVT::ValueType VT = N->getValueType(0);
2456 // fold (uint_to_fp c1) -> c1fp
2458 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
2462 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
2463 SDOperand N0 = N->getOperand(0);
2464 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2465 MVT::ValueType VT = N->getValueType(0);
2467 // fold (fp_to_sint c1fp) -> c1
2469 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
2473 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
2474 SDOperand N0 = N->getOperand(0);
2475 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2476 MVT::ValueType VT = N->getValueType(0);
2478 // fold (fp_to_uint c1fp) -> c1
2480 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
2484 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
2485 SDOperand N0 = N->getOperand(0);
2486 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2487 MVT::ValueType VT = N->getValueType(0);
2489 // fold (fp_round c1fp) -> c1fp
2491 return DAG.getNode(ISD::FP_ROUND, VT, N0);
2493 // fold (fp_round (fp_extend x)) -> x
2494 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
2495 return N0.getOperand(0);
2497 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
2498 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
2499 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
2500 AddToWorkList(Tmp.Val);
2501 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
2507 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
2508 SDOperand N0 = N->getOperand(0);
2509 MVT::ValueType VT = N->getValueType(0);
2510 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2511 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2513 // fold (fp_round_inreg c1fp) -> c1fp
2515 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
2516 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
2521 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
2522 SDOperand N0 = N->getOperand(0);
2523 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2524 MVT::ValueType VT = N->getValueType(0);
2526 // fold (fp_extend c1fp) -> c1fp
2528 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
2530 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
2531 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
2532 (!AfterLegalize||TLI.isOperationLegal(ISD::EXTLOAD, N0.getValueType()))) {
2533 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0),
2534 N0.getOperand(1), N0.getOperand(2),
2536 CombineTo(N, ExtLoad);
2537 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
2538 ExtLoad.getValue(1));
2539 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2546 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
2547 SDOperand N0 = N->getOperand(0);
2548 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2549 MVT::ValueType VT = N->getValueType(0);
2551 // fold (fneg c1) -> -c1
2553 return DAG.getNode(ISD::FNEG, VT, N0);
2554 // fold (fneg (sub x, y)) -> (sub y, x)
2555 if (N0.getOpcode() == ISD::SUB)
2556 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0));
2557 // fold (fneg (fneg x)) -> x
2558 if (N0.getOpcode() == ISD::FNEG)
2559 return N0.getOperand(0);
2563 SDOperand DAGCombiner::visitFABS(SDNode *N) {
2564 SDOperand N0 = N->getOperand(0);
2565 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2566 MVT::ValueType VT = N->getValueType(0);
2568 // fold (fabs c1) -> fabs(c1)
2570 return DAG.getNode(ISD::FABS, VT, N0);
2571 // fold (fabs (fabs x)) -> (fabs x)
2572 if (N0.getOpcode() == ISD::FABS)
2573 return N->getOperand(0);
2574 // fold (fabs (fneg x)) -> (fabs x)
2575 // fold (fabs (fcopysign x, y)) -> (fabs x)
2576 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
2577 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
2582 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
2583 SDOperand Chain = N->getOperand(0);
2584 SDOperand N1 = N->getOperand(1);
2585 SDOperand N2 = N->getOperand(2);
2586 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2588 // never taken branch, fold to chain
2589 if (N1C && N1C->isNullValue())
2591 // unconditional branch
2592 if (N1C && N1C->getValue() == 1)
2593 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2594 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
2596 if (N1.getOpcode() == ISD::SETCC &&
2597 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
2598 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
2599 N1.getOperand(0), N1.getOperand(1), N2);
2604 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
2606 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
2607 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2608 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2610 // Use SimplifySetCC to simplify SETCC's.
2611 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2612 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2614 // fold br_cc true, dest -> br dest (unconditional branch)
2615 if (SCCC && SCCC->getValue())
2616 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2618 // fold br_cc false, dest -> unconditional fall through
2619 if (SCCC && SCCC->isNullValue())
2620 return N->getOperand(0);
2621 // fold to a simpler setcc
2622 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2623 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2624 Simp.getOperand(2), Simp.getOperand(0),
2625 Simp.getOperand(1), N->getOperand(4));
2629 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
2630 SDOperand Chain = N->getOperand(0);
2631 SDOperand Ptr = N->getOperand(1);
2632 SDOperand SrcValue = N->getOperand(2);
2634 // If there are no uses of the loaded value, change uses of the chain value
2635 // into uses of the chain input (i.e. delete the dead load).
2636 if (N->hasNUsesOfValue(0, 0))
2637 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
2639 // If this load is directly stored, replace the load value with the stored
2641 // TODO: Handle store large -> read small portion.
2642 // TODO: Handle TRUNCSTORE/EXTLOAD
2643 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2644 Chain.getOperand(1).getValueType() == N->getValueType(0))
2645 return CombineTo(N, Chain.getOperand(1), Chain);
2647 // We can only move the load if it has a user of it's chain result. Otherwise
2648 // there is no place to attach it's old chain.
2649 if (CombinerAA && hasChainUsers(N)) {
2650 // Walk up chain skipping non-aliasing memory nodes.
2651 SDOperand BetterChain = FindBetterChain(N, Chain);
2653 // If the there is a better chain.
2654 if (Chain != BetterChain) {
2655 // Replace the chain to void dependency.
2656 SDOperand ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
2659 // Create token factor to keep chain around.
2660 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
2661 Chain, ReplLoad.getValue(1));
2663 // Replace uses with load and token factor.
2664 CombineTo(N, ReplLoad.getValue(0), Token);
2666 return SDOperand(N, 0);
2673 /// visitXEXTLOAD - Handle EXTLOAD/ZEXTLOAD/SEXTLOAD.
2674 SDOperand DAGCombiner::visitXEXTLOAD(SDNode *N) {
2675 SDOperand Chain = N->getOperand(0);
2676 SDOperand Ptr = N->getOperand(1);
2677 SDOperand SrcValue = N->getOperand(2);
2678 SDOperand EVT = N->getOperand(3);
2680 // If there are no uses of the loaded value, change uses of the chain value
2681 // into uses of the chain input (i.e. delete the dead load).
2682 if (N->hasNUsesOfValue(0, 0))
2683 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
2688 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
2689 SDOperand Chain = N->getOperand(0);
2690 SDOperand Value = N->getOperand(1);
2691 SDOperand Ptr = N->getOperand(2);
2692 SDOperand SrcValue = N->getOperand(3);
2694 // If this is a store that kills a previous store, remove the previous store.
2695 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2696 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ &&
2697 // Make sure that these stores are the same value type:
2698 // FIXME: we really care that the second store is >= size of the first.
2699 Value.getValueType() == Chain.getOperand(1).getValueType()) {
2700 // Create a new store of Value that replaces both stores.
2701 SDNode *PrevStore = Chain.Val;
2702 if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
2704 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other,
2705 PrevStore->getOperand(0), Value, Ptr,
2707 CombineTo(N, NewStore); // Nuke this store.
2708 CombineTo(PrevStore, NewStore); // Nuke the previous store.
2709 return SDOperand(N, 0);
2712 // If this is a store of a bit convert, store the input value.
2713 // FIXME: This needs to know that the resultant store does not need a
2714 // higher alignment than the original.
2715 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) {
2716 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0),
2721 // If the store ptr is a frame index and the frame index has a use of one
2722 // and this is a return block, then the store is redundant.
2723 if (Ptr.hasOneUse() && isa<FrameIndexSDNode>(Ptr) &&
2724 DAG.getRoot().getOpcode() == ISD::RET) {
2728 // Walk up chain skipping non-aliasing memory nodes.
2729 SDOperand BetterChain = FindBetterChain(N, Chain);
2731 // If the there is a better chain.
2732 if (Chain != BetterChain) {
2733 // Replace the chain to void dependency.
2734 SDOperand ReplStore = DAG.getNode(ISD::STORE, MVT::Other,
2735 BetterChain, Value, Ptr,
2737 // Create token to keep both nodes around.
2738 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
2741 // Make sure we merge token factors.
2742 AddUsersToWorkList(N);
2744 // Old chain needs to be cleaned up.
2745 AddToWorkList(Chain.Val);
2754 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
2755 SDOperand InVec = N->getOperand(0);
2756 SDOperand InVal = N->getOperand(1);
2757 SDOperand EltNo = N->getOperand(2);
2759 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
2760 // vector with the inserted element.
2761 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2762 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2763 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2764 if (Elt < Ops.size())
2766 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
2767 &Ops[0], Ops.size());
2773 SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
2774 SDOperand InVec = N->getOperand(0);
2775 SDOperand InVal = N->getOperand(1);
2776 SDOperand EltNo = N->getOperand(2);
2777 SDOperand NumElts = N->getOperand(3);
2778 SDOperand EltType = N->getOperand(4);
2780 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new
2781 // vector with the inserted element.
2782 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2783 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2784 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2785 if (Elt < Ops.size()-2)
2787 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(),
2788 &Ops[0], Ops.size());
2794 SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
2795 unsigned NumInScalars = N->getNumOperands()-2;
2796 SDOperand NumElts = N->getOperand(NumInScalars);
2797 SDOperand EltType = N->getOperand(NumInScalars+1);
2799 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT
2800 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most
2801 // two distinct vectors, turn this into a shuffle node.
2802 SDOperand VecIn1, VecIn2;
2803 for (unsigned i = 0; i != NumInScalars; ++i) {
2804 // Ignore undef inputs.
2805 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
2807 // If this input is something other than a VEXTRACT_VECTOR_ELT with a
2808 // constant index, bail out.
2809 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT ||
2810 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
2811 VecIn1 = VecIn2 = SDOperand(0, 0);
2815 // If the input vector type disagrees with the result of the vbuild_vector,
2816 // we can't make a shuffle.
2817 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
2818 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts ||
2819 *(ExtractedFromVec.Val->op_end()-1) != EltType) {
2820 VecIn1 = VecIn2 = SDOperand(0, 0);
2824 // Otherwise, remember this. We allow up to two distinct input vectors.
2825 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
2828 if (VecIn1.Val == 0) {
2829 VecIn1 = ExtractedFromVec;
2830 } else if (VecIn2.Val == 0) {
2831 VecIn2 = ExtractedFromVec;
2834 VecIn1 = VecIn2 = SDOperand(0, 0);
2839 // If everything is good, we can make a shuffle operation.
2841 SmallVector<SDOperand, 8> BuildVecIndices;
2842 for (unsigned i = 0; i != NumInScalars; ++i) {
2843 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
2844 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
2848 SDOperand Extract = N->getOperand(i);
2850 // If extracting from the first vector, just use the index directly.
2851 if (Extract.getOperand(0) == VecIn1) {
2852 BuildVecIndices.push_back(Extract.getOperand(1));
2856 // Otherwise, use InIdx + VecSize
2857 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
2858 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32));
2861 // Add count and size info.
2862 BuildVecIndices.push_back(NumElts);
2863 BuildVecIndices.push_back(DAG.getValueType(MVT::i32));
2865 // Return the new VVECTOR_SHUFFLE node.
2871 // Use an undef vbuild_vector as input for the second operand.
2872 std::vector<SDOperand> UnOps(NumInScalars,
2873 DAG.getNode(ISD::UNDEF,
2874 cast<VTSDNode>(EltType)->getVT()));
2875 UnOps.push_back(NumElts);
2876 UnOps.push_back(EltType);
2877 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
2878 &UnOps[0], UnOps.size());
2879 AddToWorkList(Ops[1].Val);
2881 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
2882 &BuildVecIndices[0], BuildVecIndices.size());
2885 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5);
2891 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
2892 SDOperand ShufMask = N->getOperand(2);
2893 unsigned NumElts = ShufMask.getNumOperands();
2895 // If the shuffle mask is an identity operation on the LHS, return the LHS.
2896 bool isIdentity = true;
2897 for (unsigned i = 0; i != NumElts; ++i) {
2898 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2899 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
2904 if (isIdentity) return N->getOperand(0);
2906 // If the shuffle mask is an identity operation on the RHS, return the RHS.
2908 for (unsigned i = 0; i != NumElts; ++i) {
2909 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2910 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
2915 if (isIdentity) return N->getOperand(1);
2917 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
2919 bool isUnary = true;
2920 bool isSplat = true;
2922 unsigned BaseIdx = 0;
2923 for (unsigned i = 0; i != NumElts; ++i)
2924 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
2925 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
2926 int V = (Idx < NumElts) ? 0 : 1;
2940 SDOperand N0 = N->getOperand(0);
2941 SDOperand N1 = N->getOperand(1);
2942 // Normalize unary shuffle so the RHS is undef.
2943 if (isUnary && VecNum == 1)
2946 // If it is a splat, check if the argument vector is a build_vector with
2947 // all scalar elements the same.
2950 if (V->getOpcode() == ISD::BIT_CONVERT)
2951 V = V->getOperand(0).Val;
2952 if (V->getOpcode() == ISD::BUILD_VECTOR) {
2953 unsigned NumElems = V->getNumOperands()-2;
2954 if (NumElems > BaseIdx) {
2956 bool AllSame = true;
2957 for (unsigned i = 0; i != NumElems; ++i) {
2958 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
2959 Base = V->getOperand(i);
2963 // Splat of <u, u, u, u>, return <u, u, u, u>
2966 for (unsigned i = 0; i != NumElems; ++i) {
2967 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
2968 V->getOperand(i) != Base) {
2973 // Splat of <x, x, x, x>, return <x, x, x, x>
2980 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
2982 if (isUnary || N0 == N1) {
2983 if (N0.getOpcode() == ISD::UNDEF)
2984 return DAG.getNode(ISD::UNDEF, N->getValueType(0));
2985 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
2987 SmallVector<SDOperand, 8> MappedOps;
2988 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
2989 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
2990 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
2991 MappedOps.push_back(ShufMask.getOperand(i));
2994 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
2995 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
2998 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
2999 &MappedOps[0], MappedOps.size());
3000 AddToWorkList(ShufMask.Val);
3001 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
3003 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
3010 SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
3011 SDOperand ShufMask = N->getOperand(2);
3012 unsigned NumElts = ShufMask.getNumOperands()-2;
3014 // If the shuffle mask is an identity operation on the LHS, return the LHS.
3015 bool isIdentity = true;
3016 for (unsigned i = 0; i != NumElts; ++i) {
3017 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3018 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
3023 if (isIdentity) return N->getOperand(0);
3025 // If the shuffle mask is an identity operation on the RHS, return the RHS.
3027 for (unsigned i = 0; i != NumElts; ++i) {
3028 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3029 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
3034 if (isIdentity) return N->getOperand(1);
3036 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
3038 bool isUnary = true;
3039 bool isSplat = true;
3041 unsigned BaseIdx = 0;
3042 for (unsigned i = 0; i != NumElts; ++i)
3043 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
3044 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
3045 int V = (Idx < NumElts) ? 0 : 1;
3059 SDOperand N0 = N->getOperand(0);
3060 SDOperand N1 = N->getOperand(1);
3061 // Normalize unary shuffle so the RHS is undef.
3062 if (isUnary && VecNum == 1)
3065 // If it is a splat, check if the argument vector is a build_vector with
3066 // all scalar elements the same.
3069 if (V->getOpcode() == ISD::VBIT_CONVERT)
3070 V = V->getOperand(0).Val;
3071 if (V->getOpcode() == ISD::VBUILD_VECTOR) {
3072 unsigned NumElems = V->getNumOperands()-2;
3073 if (NumElems > BaseIdx) {
3075 bool AllSame = true;
3076 for (unsigned i = 0; i != NumElems; ++i) {
3077 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3078 Base = V->getOperand(i);
3082 // Splat of <u, u, u, u>, return <u, u, u, u>
3085 for (unsigned i = 0; i != NumElems; ++i) {
3086 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3087 V->getOperand(i) != Base) {
3092 // Splat of <x, x, x, x>, return <x, x, x, x>
3099 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3101 if (isUnary || N0 == N1) {
3102 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3104 SmallVector<SDOperand, 8> MappedOps;
3105 for (unsigned i = 0; i != NumElts; ++i) {
3106 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3107 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3108 MappedOps.push_back(ShufMask.getOperand(i));
3111 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3112 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3115 // Add the type/#elts values.
3116 MappedOps.push_back(ShufMask.getOperand(NumElts));
3117 MappedOps.push_back(ShufMask.getOperand(NumElts+1));
3119 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(),
3120 &MappedOps[0], MappedOps.size());
3121 AddToWorkList(ShufMask.Val);
3123 // Build the undef vector.
3124 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType());
3125 for (unsigned i = 0; i != NumElts; ++i)
3126 MappedOps[i] = UDVal;
3127 MappedOps[NumElts ] = *(N0.Val->op_end()-2);
3128 MappedOps[NumElts+1] = *(N0.Val->op_end()-1);
3129 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3130 &MappedOps[0], MappedOps.size());
3132 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3133 N0, UDVal, ShufMask,
3134 MappedOps[NumElts], MappedOps[NumElts+1]);
3140 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
3141 /// a VAND to a vector_shuffle with the destination vector and a zero vector.
3142 /// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
3143 /// vector_shuffle V, Zero, <0, 4, 2, 4>
3144 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
3145 SDOperand LHS = N->getOperand(0);
3146 SDOperand RHS = N->getOperand(1);
3147 if (N->getOpcode() == ISD::VAND) {
3148 SDOperand DstVecSize = *(LHS.Val->op_end()-2);
3149 SDOperand DstVecEVT = *(LHS.Val->op_end()-1);
3150 if (RHS.getOpcode() == ISD::VBIT_CONVERT)
3151 RHS = RHS.getOperand(0);
3152 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3153 std::vector<SDOperand> IdxOps;
3154 unsigned NumOps = RHS.getNumOperands();
3155 unsigned NumElts = NumOps-2;
3156 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT();
3157 for (unsigned i = 0; i != NumElts; ++i) {
3158 SDOperand Elt = RHS.getOperand(i);
3159 if (!isa<ConstantSDNode>(Elt))
3161 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
3162 IdxOps.push_back(DAG.getConstant(i, EVT));
3163 else if (cast<ConstantSDNode>(Elt)->isNullValue())
3164 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
3169 // Let's see if the target supports this vector_shuffle.
3170 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
3173 // Return the new VVECTOR_SHUFFLE node.
3174 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32);
3175 SDOperand EVTNode = DAG.getValueType(EVT);
3176 std::vector<SDOperand> Ops;
3177 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode,
3180 AddToWorkList(LHS.Val);
3181 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
3182 ZeroOps.push_back(NumEltsNode);
3183 ZeroOps.push_back(EVTNode);
3184 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3185 &ZeroOps[0], ZeroOps.size()));
3186 IdxOps.push_back(NumEltsNode);
3187 IdxOps.push_back(EVTNode);
3188 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3189 &IdxOps[0], IdxOps.size()));
3190 Ops.push_back(NumEltsNode);
3191 Ops.push_back(EVTNode);
3192 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3193 &Ops[0], Ops.size());
3194 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) {
3195 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
3196 DstVecSize, DstVecEVT);
3204 /// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates
3205 /// the scalar operation of the vop if it is operating on an integer vector
3206 /// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD).
3207 SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
3208 ISD::NodeType FPOp) {
3209 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT();
3210 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp;
3211 SDOperand LHS = N->getOperand(0);
3212 SDOperand RHS = N->getOperand(1);
3213 SDOperand Shuffle = XformToShuffleWithZero(N);
3214 if (Shuffle.Val) return Shuffle;
3216 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold
3218 if (LHS.getOpcode() == ISD::VBUILD_VECTOR &&
3219 RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3220 SmallVector<SDOperand, 8> Ops;
3221 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
3222 SDOperand LHSOp = LHS.getOperand(i);
3223 SDOperand RHSOp = RHS.getOperand(i);
3224 // If these two elements can't be folded, bail out.
3225 if ((LHSOp.getOpcode() != ISD::UNDEF &&
3226 LHSOp.getOpcode() != ISD::Constant &&
3227 LHSOp.getOpcode() != ISD::ConstantFP) ||
3228 (RHSOp.getOpcode() != ISD::UNDEF &&
3229 RHSOp.getOpcode() != ISD::Constant &&
3230 RHSOp.getOpcode() != ISD::ConstantFP))
3232 // Can't fold divide by zero.
3233 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) {
3234 if ((RHSOp.getOpcode() == ISD::Constant &&
3235 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
3236 (RHSOp.getOpcode() == ISD::ConstantFP &&
3237 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue()))
3240 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
3241 AddToWorkList(Ops.back().Val);
3242 assert((Ops.back().getOpcode() == ISD::UNDEF ||
3243 Ops.back().getOpcode() == ISD::Constant ||
3244 Ops.back().getOpcode() == ISD::ConstantFP) &&
3245 "Scalar binop didn't fold!");
3248 if (Ops.size() == LHS.getNumOperands()-2) {
3249 Ops.push_back(*(LHS.Val->op_end()-2));
3250 Ops.push_back(*(LHS.Val->op_end()-1));
3251 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
3258 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
3259 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
3261 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
3262 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3263 // If we got a simplified select_cc node back from SimplifySelectCC, then
3264 // break it down into a new SETCC node, and a new SELECT node, and then return
3265 // the SELECT node, since we were called with a SELECT node.
3267 // Check to see if we got a select_cc back (to turn into setcc/select).
3268 // Otherwise, just return whatever node we got back, like fabs.
3269 if (SCC.getOpcode() == ISD::SELECT_CC) {
3270 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
3271 SCC.getOperand(0), SCC.getOperand(1),
3273 AddToWorkList(SETCC.Val);
3274 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
3275 SCC.getOperand(3), SETCC);
3282 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
3283 /// are the two values being selected between, see if we can simplify the
3284 /// select. Callers of this should assume that TheSelect is deleted if this
3285 /// returns true. As such, they should return the appropriate thing (e.g. the
3286 /// node) back to the top-level of the DAG combiner loop to avoid it being
3289 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
3292 // If this is a select from two identical things, try to pull the operation
3293 // through the select.
3294 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
3296 std::cerr << "SELECT: ["; LHS.Val->dump();
3297 std::cerr << "] ["; RHS.Val->dump();
3301 // If this is a load and the token chain is identical, replace the select
3302 // of two loads with a load through a select of the address to load from.
3303 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
3304 // constants have been dropped into the constant pool.
3305 if ((LHS.getOpcode() == ISD::LOAD ||
3306 LHS.getOpcode() == ISD::EXTLOAD ||
3307 LHS.getOpcode() == ISD::ZEXTLOAD ||
3308 LHS.getOpcode() == ISD::SEXTLOAD) &&
3309 // Token chains must be identical.
3310 LHS.getOperand(0) == RHS.getOperand(0) &&
3311 // If this is an EXTLOAD, the VT's must match.
3312 (LHS.getOpcode() == ISD::LOAD ||
3313 LHS.getOperand(3) == RHS.getOperand(3))) {
3314 // FIXME: this conflates two src values, discarding one. This is not
3315 // the right thing to do, but nothing uses srcvalues now. When they do,
3316 // turn SrcValue into a list of locations.
3318 if (TheSelect->getOpcode() == ISD::SELECT)
3319 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(),
3320 TheSelect->getOperand(0), LHS.getOperand(1),
3323 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(),
3324 TheSelect->getOperand(0),
3325 TheSelect->getOperand(1),
3326 LHS.getOperand(1), RHS.getOperand(1),
3327 TheSelect->getOperand(4));
3330 if (LHS.getOpcode() == ISD::LOAD)
3331 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0),
3332 Addr, LHS.getOperand(2));
3334 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0),
3335 LHS.getOperand(0), Addr, LHS.getOperand(2),
3336 cast<VTSDNode>(LHS.getOperand(3))->getVT());
3337 // Users of the select now use the result of the load.
3338 CombineTo(TheSelect, Load);
3340 // Users of the old loads now use the new load's chain. We know the
3341 // old-load value is dead now.
3342 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
3343 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
3351 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
3352 SDOperand N2, SDOperand N3,
3355 MVT::ValueType VT = N2.getValueType();
3356 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
3357 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
3358 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
3360 // Determine if the condition we're dealing with is constant
3361 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
3362 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
3364 // fold select_cc true, x, y -> x
3365 if (SCCC && SCCC->getValue())
3367 // fold select_cc false, x, y -> y
3368 if (SCCC && SCCC->getValue() == 0)
3371 // Check to see if we can simplify the select into an fabs node
3372 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
3373 // Allow either -0.0 or 0.0
3374 if (CFP->getValue() == 0.0) {
3375 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
3376 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
3377 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
3378 N2 == N3.getOperand(0))
3379 return DAG.getNode(ISD::FABS, VT, N0);
3381 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
3382 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
3383 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
3384 N2.getOperand(0) == N3)
3385 return DAG.getNode(ISD::FABS, VT, N3);
3389 // Check to see if we can perform the "gzip trick", transforming
3390 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
3391 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
3392 MVT::isInteger(N0.getValueType()) &&
3393 MVT::isInteger(N2.getValueType()) &&
3394 (N1C->isNullValue() || // (a < 0) ? b : 0
3395 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
3396 MVT::ValueType XType = N0.getValueType();
3397 MVT::ValueType AType = N2.getValueType();
3398 if (XType >= AType) {
3399 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
3400 // single-bit constant.
3401 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
3402 unsigned ShCtV = Log2_64(N2C->getValue());
3403 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
3404 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
3405 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
3406 AddToWorkList(Shift.Val);
3407 if (XType > AType) {
3408 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3409 AddToWorkList(Shift.Val);
3411 return DAG.getNode(ISD::AND, AType, Shift, N2);
3413 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3414 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3415 TLI.getShiftAmountTy()));
3416 AddToWorkList(Shift.Val);
3417 if (XType > AType) {
3418 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3419 AddToWorkList(Shift.Val);
3421 return DAG.getNode(ISD::AND, AType, Shift, N2);
3425 // fold select C, 16, 0 -> shl C, 4
3426 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
3427 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
3428 // Get a SetCC of the condition
3429 // FIXME: Should probably make sure that setcc is legal if we ever have a
3430 // target where it isn't.
3431 SDOperand Temp, SCC;
3432 // cast from setcc result type to select result type
3433 if (AfterLegalize) {
3434 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3435 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
3437 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
3438 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
3440 AddToWorkList(SCC.Val);
3441 AddToWorkList(Temp.Val);
3442 // shl setcc result by log2 n2c
3443 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
3444 DAG.getConstant(Log2_64(N2C->getValue()),
3445 TLI.getShiftAmountTy()));
3448 // Check to see if this is the equivalent of setcc
3449 // FIXME: Turn all of these into setcc if setcc if setcc is legal
3450 // otherwise, go ahead with the folds.
3451 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
3452 MVT::ValueType XType = N0.getValueType();
3453 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
3454 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3455 if (Res.getValueType() != VT)
3456 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
3460 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
3461 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
3462 TLI.isOperationLegal(ISD::CTLZ, XType)) {
3463 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
3464 return DAG.getNode(ISD::SRL, XType, Ctlz,
3465 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
3466 TLI.getShiftAmountTy()));
3468 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
3469 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
3470 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
3472 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
3473 DAG.getConstant(~0ULL, XType));
3474 return DAG.getNode(ISD::SRL, XType,
3475 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
3476 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3477 TLI.getShiftAmountTy()));
3479 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
3480 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
3481 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
3482 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3483 TLI.getShiftAmountTy()));
3484 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
3488 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
3489 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
3490 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
3491 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
3492 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
3493 MVT::ValueType XType = N0.getValueType();
3494 if (SubC->isNullValue() && MVT::isInteger(XType)) {
3495 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3496 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3497 TLI.getShiftAmountTy()));
3498 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
3499 AddToWorkList(Shift.Val);
3500 AddToWorkList(Add.Val);
3501 return DAG.getNode(ISD::XOR, XType, Add, Shift);
3509 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
3510 SDOperand N1, ISD::CondCode Cond,
3511 bool foldBooleans) {
3512 // These setcc operations always fold.
3516 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
3518 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
3521 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
3522 uint64_t C1 = N1C->getValue();
3523 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
3524 uint64_t C0 = N0C->getValue();
3526 // Sign extend the operands if required
3527 if (ISD::isSignedIntSetCC(Cond)) {
3528 C0 = N0C->getSignExtended();
3529 C1 = N1C->getSignExtended();
3533 default: assert(0 && "Unknown integer setcc!");
3534 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
3535 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
3536 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
3537 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
3538 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
3539 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
3540 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
3541 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
3542 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
3543 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
3546 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
3547 // equality comparison, then we're just comparing whether X itself is
3549 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
3550 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
3551 N0.getOperand(1).getOpcode() == ISD::Constant) {
3552 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
3553 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3554 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) {
3555 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
3556 // (srl (ctlz x), 5) == 0 -> X != 0
3557 // (srl (ctlz x), 5) != 1 -> X != 0
3560 // (srl (ctlz x), 5) != 0 -> X == 0
3561 // (srl (ctlz x), 5) == 1 -> X == 0
3564 SDOperand Zero = DAG.getConstant(0, N0.getValueType());
3565 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
3570 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
3571 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
3572 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
3574 // If the comparison constant has bits in the upper part, the
3575 // zero-extended value could never match.
3576 if (C1 & (~0ULL << InSize)) {
3577 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
3581 case ISD::SETEQ: return DAG.getConstant(0, VT);
3584 case ISD::SETNE: return DAG.getConstant(1, VT);
3587 // True if the sign bit of C1 is set.
3588 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
3591 // True if the sign bit of C1 isn't set.
3592 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
3598 // Otherwise, we can perform the comparison with the low bits.
3606 return DAG.getSetCC(VT, N0.getOperand(0),
3607 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
3610 break; // todo, be more careful with signed comparisons
3612 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3613 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3614 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
3615 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
3616 MVT::ValueType ExtDstTy = N0.getValueType();
3617 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
3619 // If the extended part has any inconsistent bits, it cannot ever
3620 // compare equal. In other words, they have to be all ones or all
3623 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
3624 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
3625 return DAG.getConstant(Cond == ISD::SETNE, VT);
3628 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
3629 if (Op0Ty == ExtSrcTy) {
3630 ZextOp = N0.getOperand(0);
3632 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
3633 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
3634 DAG.getConstant(Imm, Op0Ty));
3636 AddToWorkList(ZextOp.Val);
3637 // Otherwise, make this a use of a zext.
3638 return DAG.getSetCC(VT, ZextOp,
3639 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
3642 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
3643 (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3644 (N0.getOpcode() == ISD::XOR ||
3645 (N0.getOpcode() == ISD::AND &&
3646 N0.getOperand(0).getOpcode() == ISD::XOR &&
3647 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
3648 isa<ConstantSDNode>(N0.getOperand(1)) &&
3649 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
3650 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can
3651 // only do this if the top bits are known zero.
3652 if (TLI.MaskedValueIsZero(N1,
3653 MVT::getIntVTBitMask(N0.getValueType())-1)) {
3654 // Okay, get the un-inverted input value.
3656 if (N0.getOpcode() == ISD::XOR)
3657 Val = N0.getOperand(0);
3659 assert(N0.getOpcode() == ISD::AND &&
3660 N0.getOperand(0).getOpcode() == ISD::XOR);
3661 // ((X^1)&1)^1 -> X & 1
3662 Val = DAG.getNode(ISD::AND, N0.getValueType(),
3663 N0.getOperand(0).getOperand(0), N0.getOperand(1));
3665 return DAG.getSetCC(VT, Val, N1,
3666 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3670 uint64_t MinVal, MaxVal;
3671 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
3672 if (ISD::isSignedIntSetCC(Cond)) {
3673 MinVal = 1ULL << (OperandBitSize-1);
3674 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
3675 MaxVal = ~0ULL >> (65-OperandBitSize);
3680 MaxVal = ~0ULL >> (64-OperandBitSize);
3683 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
3684 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
3685 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
3686 --C1; // X >= C0 --> X > (C0-1)
3687 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3688 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
3691 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
3692 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
3693 ++C1; // X <= C0 --> X < (C0+1)
3694 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3695 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
3698 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
3699 return DAG.getConstant(0, VT); // X < MIN --> false
3701 // Canonicalize setgt X, Min --> setne X, Min
3702 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
3703 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3704 // Canonicalize setlt X, Max --> setne X, Max
3705 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
3706 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3708 // If we have setult X, 1, turn it into seteq X, 0
3709 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
3710 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
3712 // If we have setugt X, Max-1, turn it into seteq X, Max
3713 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
3714 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
3717 // If we have "setcc X, C0", check to see if we can shrink the immediate
3720 // SETUGT X, SINTMAX -> SETLT X, 0
3721 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
3722 C1 == (~0ULL >> (65-OperandBitSize)))
3723 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
3726 // FIXME: Implement the rest of these.
3728 // Fold bit comparisons when we can.
3729 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3730 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
3731 if (ConstantSDNode *AndRHS =
3732 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3733 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
3734 // Perform the xform if the AND RHS is a single bit.
3735 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
3736 return DAG.getNode(ISD::SRL, VT, N0,
3737 DAG.getConstant(Log2_64(AndRHS->getValue()),
3738 TLI.getShiftAmountTy()));
3740 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
3741 // (X & 8) == 8 --> (X & 8) >> 3
3742 // Perform the xform if C1 is a single bit.
3743 if ((C1 & (C1-1)) == 0) {
3744 return DAG.getNode(ISD::SRL, VT, N0,
3745 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
3750 } else if (isa<ConstantSDNode>(N0.Val)) {
3751 // Ensure that the constant occurs on the RHS.
3752 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
3755 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
3756 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
3757 double C0 = N0C->getValue(), C1 = N1C->getValue();
3760 default: break; // FIXME: Implement the rest of these!
3761 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
3762 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
3763 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
3764 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
3765 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
3766 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
3769 // Ensure that the constant occurs on the RHS.
3770 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
3774 // We can always fold X == Y for integer setcc's.
3775 if (MVT::isInteger(N0.getValueType()))
3776 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3777 unsigned UOF = ISD::getUnorderedFlavor(Cond);
3778 if (UOF == 2) // FP operators that are undefined on NaNs.
3779 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3780 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
3781 return DAG.getConstant(UOF, VT);
3782 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
3783 // if it is not already.
3784 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
3785 if (NewCond != Cond)
3786 return DAG.getSetCC(VT, N0, N1, NewCond);
3789 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3790 MVT::isInteger(N0.getValueType())) {
3791 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
3792 N0.getOpcode() == ISD::XOR) {
3793 // Simplify (X+Y) == (X+Z) --> Y == Z
3794 if (N0.getOpcode() == N1.getOpcode()) {
3795 if (N0.getOperand(0) == N1.getOperand(0))
3796 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
3797 if (N0.getOperand(1) == N1.getOperand(1))
3798 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
3799 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
3800 // If X op Y == Y op X, try other combinations.
3801 if (N0.getOperand(0) == N1.getOperand(1))
3802 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
3803 if (N0.getOperand(1) == N1.getOperand(0))
3804 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
3808 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
3809 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3810 // Turn (X+C1) == C2 --> X == C2-C1
3811 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
3812 return DAG.getSetCC(VT, N0.getOperand(0),
3813 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
3814 N0.getValueType()), Cond);
3817 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
3818 if (N0.getOpcode() == ISD::XOR)
3819 // If we know that all of the inverted bits are zero, don't bother
3820 // performing the inversion.
3821 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
3822 return DAG.getSetCC(VT, N0.getOperand(0),
3823 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
3824 N0.getValueType()), Cond);
3827 // Turn (C1-X) == C2 --> X == C1-C2
3828 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
3829 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
3830 return DAG.getSetCC(VT, N0.getOperand(1),
3831 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
3832 N0.getValueType()), Cond);
3837 // Simplify (X+Z) == X --> Z == 0
3838 if (N0.getOperand(0) == N1)
3839 return DAG.getSetCC(VT, N0.getOperand(1),
3840 DAG.getConstant(0, N0.getValueType()), Cond);
3841 if (N0.getOperand(1) == N1) {
3842 if (DAG.isCommutativeBinOp(N0.getOpcode()))
3843 return DAG.getSetCC(VT, N0.getOperand(0),
3844 DAG.getConstant(0, N0.getValueType()), Cond);
3846 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
3847 // (Z-X) == X --> Z == X<<1
3848 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
3850 DAG.getConstant(1,TLI.getShiftAmountTy()));
3851 AddToWorkList(SH.Val);
3852 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
3857 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
3858 N1.getOpcode() == ISD::XOR) {
3859 // Simplify X == (X+Z) --> Z == 0
3860 if (N1.getOperand(0) == N0) {
3861 return DAG.getSetCC(VT, N1.getOperand(1),
3862 DAG.getConstant(0, N1.getValueType()), Cond);
3863 } else if (N1.getOperand(1) == N0) {
3864 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
3865 return DAG.getSetCC(VT, N1.getOperand(0),
3866 DAG.getConstant(0, N1.getValueType()), Cond);
3868 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
3869 // X == (Z-X) --> X<<1 == Z
3870 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
3871 DAG.getConstant(1,TLI.getShiftAmountTy()));
3872 AddToWorkList(SH.Val);
3873 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
3879 // Fold away ALL boolean setcc's.
3881 if (N0.getValueType() == MVT::i1 && foldBooleans) {
3883 default: assert(0 && "Unknown integer setcc!");
3884 case ISD::SETEQ: // X == Y -> (X^Y)^1
3885 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
3886 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
3887 AddToWorkList(Temp.Val);
3889 case ISD::SETNE: // X != Y --> (X^Y)
3890 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
3892 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
3893 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
3894 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
3895 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
3896 AddToWorkList(Temp.Val);
3898 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
3899 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
3900 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
3901 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
3902 AddToWorkList(Temp.Val);
3904 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
3905 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
3906 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
3907 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
3908 AddToWorkList(Temp.Val);
3910 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
3911 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
3912 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
3913 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
3916 if (VT != MVT::i1) {
3917 AddToWorkList(N0.Val);
3918 // FIXME: If running after legalize, we probably can't do this.
3919 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
3924 // Could not fold it.
3928 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3929 /// return a DAG expression to select that will generate the same value by
3930 /// multiplying by a magic number. See:
3931 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3932 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
3933 std::vector<SDNode*> Built;
3934 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
3936 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
3942 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3943 /// return a DAG expression to select that will generate the same value by
3944 /// multiplying by a magic number. See:
3945 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3946 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
3947 std::vector<SDNode*> Built;
3948 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
3950 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
3956 /// hasChainUsers - Returns true if one of the users of a load node has the
3957 /// chain result as an operand.
3958 bool DAGCombiner::hasChainUsers(SDNode *Load) {
3959 // Don't even bother if the load only has one user (conservatively the value.)
3960 if (!Load->hasOneUse()) {
3961 SDOperand Chain(Load, 1); // The load's chain result.
3963 // For each user of the load.
3964 for (SDNode::use_iterator UI = Load->use_begin(), UE = Load->use_end();
3967 // Chain will be the first operand.
3968 if ((*UI)->getOperand(0) == Chain)
3977 /// FindBaseOffset - Return true if we can determine base and offset information
3978 /// from a given pointer operand. Provides base and offset as a result.
3979 bool DAGCombiner::FindBaseOffset(SDOperand Ptr,
3980 SDOperand &Object, int64_t &Offset) {
3982 // Is it a frame variable, global or constant.
3983 if (isa<FrameIndexSDNode>(Ptr) ||
3984 isa<ConstantPoolSDNode>(Ptr) ||
3985 isa<GlobalAddressSDNode>(Ptr)) {
3986 Object = Ptr; Offset = 0;
3988 } else if (Ptr.getOpcode() == ISD::ADD &&
3989 FindBaseOffset(Ptr.getOperand(0), Object, Offset)) {
3990 // If it's an add of an simple constant then include it in the offset.
3991 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Ptr.getOperand(1))) {
3992 Offset += C->getValue();
4000 /// isAlias - Return true if there is the possibility that the two addresses
4002 bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1,
4003 SDOperand SrcValue1,
4004 SDOperand Ptr2, int64_t Size2,
4005 SDOperand SrcValue2) {
4006 // If they are the same then they must be aliases.
4007 if (Ptr1 == Ptr2) return true;
4009 // Gather base offset information. Objects can be frame variables, globals
4011 SDOperand Object1, Object2;
4012 int64_t Offset1, Offset2;
4013 if (FindBaseOffset(Ptr1, Object1, Offset1) &&
4014 FindBaseOffset(Ptr2, Object2, Offset2)) {
4015 // If they have a different base address, then they can't alias.
4016 if (Object1 != Object2) return false;
4018 // Check to see if the addresses overlap.
4019 if ((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1)
4023 // Otherwise we don't know and have to play it safe.
4027 /// FindAliasInfo - Extracts the relevant alias information from the memory
4029 void DAGCombiner::FindAliasInfo(SDNode *N,
4030 SDOperand &Ptr, int64_t &Size, SDOperand &SrcValue) {
4031 switch (N->getOpcode()) {
4033 Ptr = N->getOperand(1);
4034 Size = MVT::getSizeInBits(N->getValueType(0)) >> 3;
4035 SrcValue = N->getOperand(2);
4038 Ptr = N->getOperand(2);
4039 Size = MVT::getSizeInBits(N->getOperand(1).getValueType()) >> 3;
4040 SrcValue = N->getOperand(3);
4043 assert(0 && "getAliasInfo expected a memory op");
4047 /// hasChain - Return true if Op has a chain. Provides chain if present.
4049 bool DAGCombiner::hasChain(SDOperand Op, SDOperand &Chain) {
4050 if (Op.getNumOperands() == 0) return false;
4051 Chain = Op.getOperand(0);
4052 return Chain.getValueType() == MVT::Other;
4055 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
4056 /// for a better chain.
4057 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand Chain) {
4058 // Get alias information for node.
4062 FindAliasInfo(N, Ptr, Size, SrcValue);
4064 // While we don't encounter any aliasing memory nodes walk up chain.
4066 switch (Chain.getOpcode()) {
4067 case ISD::EntryToken:
4068 // Entry token is ideal chain operand.
4072 // Get alias information for chain.
4075 SDOperand ChainSrcValue;
4076 FindAliasInfo(Chain.Val, ChainPtr, ChainSize, ChainSrcValue);
4078 // If chain is alias then stop here, otherwise continue up chain.
4079 if (isAlias(Ptr, Size, SrcValue, ChainPtr, ChainSize, ChainSrcValue))
4082 Chain = Chain.getOperand(0);
4086 case ISD::TokenFactor: {
4087 // Continue up each of token factor operand and accumulate results in
4088 // a new token factor. CSE will handle duplicate elimination.
4089 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
4090 bool Change = false;
4092 // For each token factor operand.
4093 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) {
4094 SDOperand Op = Chain.getOperand(i);
4095 SDOperand OpChain = FindBetterChain(N, Op);
4097 // Make sure we don't duplicate an operand.
4098 if (OpChain.getOpcode() != ISD::EntryToken &&
4099 std::find(Ops.begin(), Ops.end(), OpChain) == Ops.end()) {
4100 Ops.push_back(OpChain);
4103 // If we added a new operand.
4104 Change = Change || Op != OpChain;
4107 // If we have new operands.
4109 // Create a specialized token factor for this chain. getNode CSE will
4110 // handle duplicates. If it's a single operand, getNode will just
4111 // return the opernand instead of a new token factor.
4112 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
4115 // Leave things alone.
4118 // For all other instructions we will just have to take what we can get.
4119 default: return Chain;
4126 // SelectionDAG::Combine - This is the entry point for the file.
4128 void SelectionDAG::Combine(bool RunningAfterLegalize) {
4129 /// run - This is the main entry point to this class.
4131 DAGCombiner(*this).Run(RunningAfterLegalize);