1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/ADT/SmallPtrSet.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
41 STATISTIC(NodesCombined , "Number of dag nodes combined");
42 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
43 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
44 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
45 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
49 CombinerAA("combiner-alias-analysis", cl::Hidden,
50 cl::desc("Turn on alias analysis during testing"));
53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
54 cl::desc("Include global information in alias analysis"));
56 //------------------------------ DAGCombiner ---------------------------------//
60 const TargetLowering &TLI;
62 CodeGenOpt::Level OptLevel;
66 // Worklist of all of the nodes that need to be simplified.
68 // This has the semantics that when adding to the worklist,
69 // the item added must be next to be processed. It should
70 // also only appear once. The naive approach to this takes
73 // To reduce the insert/remove time to logarithmic, we use
74 // a set and a vector to maintain our worklist.
76 // The set contains the items on the worklist, but does not
77 // maintain the order they should be visited.
79 // The vector maintains the order nodes should be visited, but may
80 // contain duplicate or removed nodes. When choosing a node to
81 // visit, we pop off the order stack until we find an item that is
82 // also in the contents set. All operations are O(log N).
83 SmallPtrSet<SDNode*, 64> WorkListContents;
84 SmallVector<SDNode*, 64> WorkListOrder;
86 // AA - Used for DAG load/store alias analysis.
89 /// AddUsersToWorkList - When an instruction is simplified, add all users of
90 /// the instruction to the work lists because they might get more simplified
93 void AddUsersToWorkList(SDNode *N) {
94 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
99 /// visit - call the node-specific routine that knows how to fold each
100 /// particular type of node.
101 SDValue visit(SDNode *N);
104 /// AddToWorkList - Add to the work list making sure its instance is at the
105 /// back (next to be processed.)
106 void AddToWorkList(SDNode *N) {
107 WorkListContents.insert(N);
108 WorkListOrder.push_back(N);
111 /// removeFromWorkList - remove all instances of N from the worklist.
113 void removeFromWorkList(SDNode *N) {
114 WorkListContents.erase(N);
117 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
120 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
121 return CombineTo(N, &Res, 1, AddTo);
124 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
126 SDValue To[] = { Res0, Res1 };
127 return CombineTo(N, To, 2, AddTo);
130 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
134 /// SimplifyDemandedBits - Check the specified integer node value to see if
135 /// it can be simplified or if things it uses can be simplified by bit
136 /// propagation. If so, return true.
137 bool SimplifyDemandedBits(SDValue Op) {
138 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
139 APInt Demanded = APInt::getAllOnesValue(BitWidth);
140 return SimplifyDemandedBits(Op, Demanded);
143 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
145 bool CombineToPreIndexedLoadStore(SDNode *N);
146 bool CombineToPostIndexedLoadStore(SDNode *N);
148 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
149 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
150 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
151 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
152 SDValue PromoteIntBinOp(SDValue Op);
153 SDValue PromoteIntShiftOp(SDValue Op);
154 SDValue PromoteExtend(SDValue Op);
155 bool PromoteLoad(SDValue Op);
157 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
158 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
159 ISD::NodeType ExtType);
161 /// combine - call the node-specific routine that knows how to fold each
162 /// particular type of node. If that doesn't do anything, try the
163 /// target-specific DAG combines.
164 SDValue combine(SDNode *N);
166 // Visitation implementation - Implement dag node combining for different
167 // node types. The semantics are as follows:
169 // SDValue.getNode() == 0 - No change was made
170 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
171 // otherwise - N should be replaced by the returned Operand.
173 SDValue visitTokenFactor(SDNode *N);
174 SDValue visitMERGE_VALUES(SDNode *N);
175 SDValue visitADD(SDNode *N);
176 SDValue visitSUB(SDNode *N);
177 SDValue visitADDC(SDNode *N);
178 SDValue visitSUBC(SDNode *N);
179 SDValue visitADDE(SDNode *N);
180 SDValue visitSUBE(SDNode *N);
181 SDValue visitMUL(SDNode *N);
182 SDValue visitSDIV(SDNode *N);
183 SDValue visitUDIV(SDNode *N);
184 SDValue visitSREM(SDNode *N);
185 SDValue visitUREM(SDNode *N);
186 SDValue visitMULHU(SDNode *N);
187 SDValue visitMULHS(SDNode *N);
188 SDValue visitSMUL_LOHI(SDNode *N);
189 SDValue visitUMUL_LOHI(SDNode *N);
190 SDValue visitSMULO(SDNode *N);
191 SDValue visitUMULO(SDNode *N);
192 SDValue visitSDIVREM(SDNode *N);
193 SDValue visitUDIVREM(SDNode *N);
194 SDValue visitAND(SDNode *N);
195 SDValue visitOR(SDNode *N);
196 SDValue visitXOR(SDNode *N);
197 SDValue SimplifyVBinOp(SDNode *N);
198 SDValue SimplifyVUnaryOp(SDNode *N);
199 SDValue visitSHL(SDNode *N);
200 SDValue visitSRA(SDNode *N);
201 SDValue visitSRL(SDNode *N);
202 SDValue visitCTLZ(SDNode *N);
203 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
204 SDValue visitCTTZ(SDNode *N);
205 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
206 SDValue visitCTPOP(SDNode *N);
207 SDValue visitSELECT(SDNode *N);
208 SDValue visitSELECT_CC(SDNode *N);
209 SDValue visitSETCC(SDNode *N);
210 SDValue visitSIGN_EXTEND(SDNode *N);
211 SDValue visitZERO_EXTEND(SDNode *N);
212 SDValue visitANY_EXTEND(SDNode *N);
213 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
214 SDValue visitTRUNCATE(SDNode *N);
215 SDValue visitBITCAST(SDNode *N);
216 SDValue visitBUILD_PAIR(SDNode *N);
217 SDValue visitFADD(SDNode *N);
218 SDValue visitFSUB(SDNode *N);
219 SDValue visitFMUL(SDNode *N);
220 SDValue visitFMA(SDNode *N);
221 SDValue visitFDIV(SDNode *N);
222 SDValue visitFREM(SDNode *N);
223 SDValue visitFCOPYSIGN(SDNode *N);
224 SDValue visitSINT_TO_FP(SDNode *N);
225 SDValue visitUINT_TO_FP(SDNode *N);
226 SDValue visitFP_TO_SINT(SDNode *N);
227 SDValue visitFP_TO_UINT(SDNode *N);
228 SDValue visitFP_ROUND(SDNode *N);
229 SDValue visitFP_ROUND_INREG(SDNode *N);
230 SDValue visitFP_EXTEND(SDNode *N);
231 SDValue visitFNEG(SDNode *N);
232 SDValue visitFABS(SDNode *N);
233 SDValue visitFCEIL(SDNode *N);
234 SDValue visitFTRUNC(SDNode *N);
235 SDValue visitFFLOOR(SDNode *N);
236 SDValue visitBRCOND(SDNode *N);
237 SDValue visitBR_CC(SDNode *N);
238 SDValue visitLOAD(SDNode *N);
239 SDValue visitSTORE(SDNode *N);
240 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
241 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
242 SDValue visitBUILD_VECTOR(SDNode *N);
243 SDValue visitCONCAT_VECTORS(SDNode *N);
244 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
245 SDValue visitVECTOR_SHUFFLE(SDNode *N);
246 SDValue visitMEMBARRIER(SDNode *N);
248 SDValue XformToShuffleWithZero(SDNode *N);
249 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
251 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
253 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
254 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
255 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
256 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
257 SDValue N3, ISD::CondCode CC,
258 bool NotExtCompare = false);
259 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
260 DebugLoc DL, bool foldBooleans = true);
261 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
263 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
264 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
265 SDValue BuildSDIV(SDNode *N);
266 SDValue BuildUDIV(SDNode *N);
267 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
268 bool DemandHighBits = true);
269 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
270 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
271 SDValue ReduceLoadWidth(SDNode *N);
272 SDValue ReduceLoadOpStoreWidth(SDNode *N);
273 SDValue TransformFPLoadStorePair(SDNode *N);
274 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N);
275 SDValue reduceBuildVecConvertToConvertBuildVec(SDNode *N);
277 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
279 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
280 /// looking for aliasing nodes and adding them to the Aliases vector.
281 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
282 SmallVector<SDValue, 8> &Aliases);
284 /// isAlias - Return true if there is any possibility that the two addresses
286 bool isAlias(SDValue Ptr1, int64_t Size1,
287 const Value *SrcValue1, int SrcValueOffset1,
288 unsigned SrcValueAlign1,
289 const MDNode *TBAAInfo1,
290 SDValue Ptr2, int64_t Size2,
291 const Value *SrcValue2, int SrcValueOffset2,
292 unsigned SrcValueAlign2,
293 const MDNode *TBAAInfo2) const;
295 /// isAlias - Return true if there is any possibility that the two addresses
297 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1);
299 /// FindAliasInfo - Extracts the relevant alias information from the memory
300 /// node. Returns true if the operand was a load.
301 bool FindAliasInfo(SDNode *N,
302 SDValue &Ptr, int64_t &Size,
303 const Value *&SrcValue, int &SrcValueOffset,
304 unsigned &SrcValueAlignment,
305 const MDNode *&TBAAInfo) const;
307 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
308 /// looking for a better chain (aliasing node.)
309 SDValue FindBetterChain(SDNode *N, SDValue Chain);
311 /// Merge consecutive store operations into a wide store.
312 /// This optimization uses wide integers or vectors when possible.
313 /// \return True if some memory operations were changed.
314 bool MergeConsecutiveStores(StoreSDNode *N);
317 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
318 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
319 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
321 /// Run - runs the dag combiner on all nodes in the work list
322 void Run(CombineLevel AtLevel);
324 SelectionDAG &getDAG() const { return DAG; }
326 /// getShiftAmountTy - Returns a type large enough to hold any valid
327 /// shift amount - before type legalization these can be huge.
328 EVT getShiftAmountTy(EVT LHSTy) {
329 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy();
332 /// isTypeLegal - This method returns true if we are running before type
333 /// legalization or if the specified VT is legal.
334 bool isTypeLegal(const EVT &VT) {
335 if (!LegalTypes) return true;
336 return TLI.isTypeLegal(VT);
343 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
344 /// nodes from the worklist.
345 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
348 explicit WorkListRemover(DAGCombiner &dc)
349 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
351 virtual void NodeDeleted(SDNode *N, SDNode *E) {
352 DC.removeFromWorkList(N);
357 //===----------------------------------------------------------------------===//
358 // TargetLowering::DAGCombinerInfo implementation
359 //===----------------------------------------------------------------------===//
361 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
362 ((DAGCombiner*)DC)->AddToWorkList(N);
365 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
366 ((DAGCombiner*)DC)->removeFromWorkList(N);
369 SDValue TargetLowering::DAGCombinerInfo::
370 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
371 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
374 SDValue TargetLowering::DAGCombinerInfo::
375 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
376 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
380 SDValue TargetLowering::DAGCombinerInfo::
381 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
382 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
385 void TargetLowering::DAGCombinerInfo::
386 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
387 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
390 //===----------------------------------------------------------------------===//
392 //===----------------------------------------------------------------------===//
394 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
395 /// specified expression for the same cost as the expression itself, or 2 if we
396 /// can compute the negated form more cheaply than the expression itself.
397 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
398 const TargetLowering &TLI,
399 const TargetOptions *Options,
400 unsigned Depth = 0) {
401 // fneg is removable even if it has multiple uses.
402 if (Op.getOpcode() == ISD::FNEG) return 2;
404 // Don't allow anything with multiple uses.
405 if (!Op.hasOneUse()) return 0;
407 // Don't recurse exponentially.
408 if (Depth > 6) return 0;
410 switch (Op.getOpcode()) {
411 default: return false;
412 case ISD::ConstantFP:
413 // Don't invert constant FP values after legalize. The negated constant
414 // isn't necessarily legal.
415 return LegalOperations ? 0 : 1;
417 // FIXME: determine better conditions for this xform.
418 if (!Options->UnsafeFPMath) return 0;
420 // After operation legalization, it might not be legal to create new FSUBs.
421 if (LegalOperations &&
422 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
425 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
426 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
429 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
430 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
433 // We can't turn -(A-B) into B-A when we honor signed zeros.
434 if (!Options->UnsafeFPMath) return 0;
436 // fold (fneg (fsub A, B)) -> (fsub B, A)
441 if (Options->HonorSignDependentRoundingFPMath()) return 0;
443 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
444 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
448 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
454 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
459 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
460 /// returns the newly negated expression.
461 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
462 bool LegalOperations, unsigned Depth = 0) {
463 // fneg is removable even if it has multiple uses.
464 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
466 // Don't allow anything with multiple uses.
467 assert(Op.hasOneUse() && "Unknown reuse!");
469 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
470 switch (Op.getOpcode()) {
471 default: llvm_unreachable("Unknown code");
472 case ISD::ConstantFP: {
473 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
475 return DAG.getConstantFP(V, Op.getValueType());
478 // FIXME: determine better conditions for this xform.
479 assert(DAG.getTarget().Options.UnsafeFPMath);
481 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
482 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
483 DAG.getTargetLoweringInfo(),
484 &DAG.getTarget().Options, Depth+1))
485 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
486 GetNegatedExpression(Op.getOperand(0), DAG,
487 LegalOperations, Depth+1),
489 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
490 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
491 GetNegatedExpression(Op.getOperand(1), DAG,
492 LegalOperations, Depth+1),
495 // We can't turn -(A-B) into B-A when we honor signed zeros.
496 assert(DAG.getTarget().Options.UnsafeFPMath);
498 // fold (fneg (fsub 0, B)) -> B
499 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
500 if (N0CFP->getValueAPF().isZero())
501 return Op.getOperand(1);
503 // fold (fneg (fsub A, B)) -> (fsub B, A)
504 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
505 Op.getOperand(1), Op.getOperand(0));
509 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath());
511 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
512 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
513 DAG.getTargetLoweringInfo(),
514 &DAG.getTarget().Options, Depth+1))
515 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
516 GetNegatedExpression(Op.getOperand(0), DAG,
517 LegalOperations, Depth+1),
520 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
521 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
523 GetNegatedExpression(Op.getOperand(1), DAG,
524 LegalOperations, Depth+1));
528 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
529 GetNegatedExpression(Op.getOperand(0), DAG,
530 LegalOperations, Depth+1));
532 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
533 GetNegatedExpression(Op.getOperand(0), DAG,
534 LegalOperations, Depth+1),
540 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
541 // that selects between the values 1 and 0, making it equivalent to a setcc.
542 // Also, set the incoming LHS, RHS, and CC references to the appropriate
543 // nodes based on the type of node we are checking. This simplifies life a
544 // bit for the callers.
545 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
547 if (N.getOpcode() == ISD::SETCC) {
548 LHS = N.getOperand(0);
549 RHS = N.getOperand(1);
550 CC = N.getOperand(2);
553 if (N.getOpcode() == ISD::SELECT_CC &&
554 N.getOperand(2).getOpcode() == ISD::Constant &&
555 N.getOperand(3).getOpcode() == ISD::Constant &&
556 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
557 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
558 LHS = N.getOperand(0);
559 RHS = N.getOperand(1);
560 CC = N.getOperand(4);
566 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
567 // one use. If this is true, it allows the users to invert the operation for
568 // free when it is profitable to do so.
569 static bool isOneUseSetCC(SDValue N) {
571 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
576 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
577 SDValue N0, SDValue N1) {
578 EVT VT = N0.getValueType();
579 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
580 if (isa<ConstantSDNode>(N1)) {
581 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
583 DAG.FoldConstantArithmetic(Opc, VT,
584 cast<ConstantSDNode>(N0.getOperand(1)),
585 cast<ConstantSDNode>(N1));
586 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
588 if (N0.hasOneUse()) {
589 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
590 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
591 N0.getOperand(0), N1);
592 AddToWorkList(OpNode.getNode());
593 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
597 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
598 if (isa<ConstantSDNode>(N0)) {
599 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
601 DAG.FoldConstantArithmetic(Opc, VT,
602 cast<ConstantSDNode>(N1.getOperand(1)),
603 cast<ConstantSDNode>(N0));
604 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
606 if (N1.hasOneUse()) {
607 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
608 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
609 N1.getOperand(0), N0);
610 AddToWorkList(OpNode.getNode());
611 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
618 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
620 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
622 DEBUG(dbgs() << "\nReplacing.1 ";
624 dbgs() << "\nWith: ";
625 To[0].getNode()->dump(&DAG);
626 dbgs() << " and " << NumTo-1 << " other values\n";
627 for (unsigned i = 0, e = NumTo; i != e; ++i)
628 assert((!To[i].getNode() ||
629 N->getValueType(i) == To[i].getValueType()) &&
630 "Cannot combine value to value of different type!"));
631 WorkListRemover DeadNodes(*this);
632 DAG.ReplaceAllUsesWith(N, To);
634 // Push the new nodes and any users onto the worklist
635 for (unsigned i = 0, e = NumTo; i != e; ++i) {
636 if (To[i].getNode()) {
637 AddToWorkList(To[i].getNode());
638 AddUsersToWorkList(To[i].getNode());
643 // Finally, if the node is now dead, remove it from the graph. The node
644 // may not be dead if the replacement process recursively simplified to
645 // something else needing this node.
646 if (N->use_empty()) {
647 // Nodes can be reintroduced into the worklist. Make sure we do not
648 // process a node that has been replaced.
649 removeFromWorkList(N);
651 // Finally, since the node is now dead, remove it from the graph.
654 return SDValue(N, 0);
658 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
659 // Replace all uses. If any nodes become isomorphic to other nodes and
660 // are deleted, make sure to remove them from our worklist.
661 WorkListRemover DeadNodes(*this);
662 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
664 // Push the new node and any (possibly new) users onto the worklist.
665 AddToWorkList(TLO.New.getNode());
666 AddUsersToWorkList(TLO.New.getNode());
668 // Finally, if the node is now dead, remove it from the graph. The node
669 // may not be dead if the replacement process recursively simplified to
670 // something else needing this node.
671 if (TLO.Old.getNode()->use_empty()) {
672 removeFromWorkList(TLO.Old.getNode());
674 // If the operands of this node are only used by the node, they will now
675 // be dead. Make sure to visit them first to delete dead nodes early.
676 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
677 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
678 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
680 DAG.DeleteNode(TLO.Old.getNode());
684 /// SimplifyDemandedBits - Check the specified integer node value to see if
685 /// it can be simplified or if things it uses can be simplified by bit
686 /// propagation. If so, return true.
687 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
688 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
689 APInt KnownZero, KnownOne;
690 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
694 AddToWorkList(Op.getNode());
696 // Replace the old value with the new one.
698 DEBUG(dbgs() << "\nReplacing.2 ";
699 TLO.Old.getNode()->dump(&DAG);
700 dbgs() << "\nWith: ";
701 TLO.New.getNode()->dump(&DAG);
704 CommitTargetLoweringOpt(TLO);
708 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
709 DebugLoc dl = Load->getDebugLoc();
710 EVT VT = Load->getValueType(0);
711 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
713 DEBUG(dbgs() << "\nReplacing.9 ";
715 dbgs() << "\nWith: ";
716 Trunc.getNode()->dump(&DAG);
718 WorkListRemover DeadNodes(*this);
719 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
720 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
721 removeFromWorkList(Load);
722 DAG.DeleteNode(Load);
723 AddToWorkList(Trunc.getNode());
726 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
728 DebugLoc dl = Op.getDebugLoc();
729 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
730 EVT MemVT = LD->getMemoryVT();
731 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
732 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
734 : LD->getExtensionType();
736 return DAG.getExtLoad(ExtType, dl, PVT,
737 LD->getChain(), LD->getBasePtr(),
738 LD->getPointerInfo(),
739 MemVT, LD->isVolatile(),
740 LD->isNonTemporal(), LD->getAlignment());
743 unsigned Opc = Op.getOpcode();
746 case ISD::AssertSext:
747 return DAG.getNode(ISD::AssertSext, dl, PVT,
748 SExtPromoteOperand(Op.getOperand(0), PVT),
750 case ISD::AssertZext:
751 return DAG.getNode(ISD::AssertZext, dl, PVT,
752 ZExtPromoteOperand(Op.getOperand(0), PVT),
754 case ISD::Constant: {
756 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
757 return DAG.getNode(ExtOpc, dl, PVT, Op);
761 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
763 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
766 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
767 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
769 EVT OldVT = Op.getValueType();
770 DebugLoc dl = Op.getDebugLoc();
771 bool Replace = false;
772 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
773 if (NewOp.getNode() == 0)
775 AddToWorkList(NewOp.getNode());
778 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
779 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
780 DAG.getValueType(OldVT));
783 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
784 EVT OldVT = Op.getValueType();
785 DebugLoc dl = Op.getDebugLoc();
786 bool Replace = false;
787 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
788 if (NewOp.getNode() == 0)
790 AddToWorkList(NewOp.getNode());
793 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
794 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
797 /// PromoteIntBinOp - Promote the specified integer binary operation if the
798 /// target indicates it is beneficial. e.g. On x86, it's usually better to
799 /// promote i16 operations to i32 since i16 instructions are longer.
800 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
801 if (!LegalOperations)
804 EVT VT = Op.getValueType();
805 if (VT.isVector() || !VT.isInteger())
808 // If operation type is 'undesirable', e.g. i16 on x86, consider
810 unsigned Opc = Op.getOpcode();
811 if (TLI.isTypeDesirableForOp(Opc, VT))
815 // Consult target whether it is a good idea to promote this operation and
816 // what's the right type to promote it to.
817 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
818 assert(PVT != VT && "Don't know what type to promote to!");
820 bool Replace0 = false;
821 SDValue N0 = Op.getOperand(0);
822 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
823 if (NN0.getNode() == 0)
826 bool Replace1 = false;
827 SDValue N1 = Op.getOperand(1);
832 NN1 = PromoteOperand(N1, PVT, Replace1);
833 if (NN1.getNode() == 0)
837 AddToWorkList(NN0.getNode());
839 AddToWorkList(NN1.getNode());
842 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
844 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
846 DEBUG(dbgs() << "\nPromoting ";
847 Op.getNode()->dump(&DAG));
848 DebugLoc dl = Op.getDebugLoc();
849 return DAG.getNode(ISD::TRUNCATE, dl, VT,
850 DAG.getNode(Opc, dl, PVT, NN0, NN1));
855 /// PromoteIntShiftOp - Promote the specified integer shift operation if the
856 /// target indicates it is beneficial. e.g. On x86, it's usually better to
857 /// promote i16 operations to i32 since i16 instructions are longer.
858 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
859 if (!LegalOperations)
862 EVT VT = Op.getValueType();
863 if (VT.isVector() || !VT.isInteger())
866 // If operation type is 'undesirable', e.g. i16 on x86, consider
868 unsigned Opc = Op.getOpcode();
869 if (TLI.isTypeDesirableForOp(Opc, VT))
873 // Consult target whether it is a good idea to promote this operation and
874 // what's the right type to promote it to.
875 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
876 assert(PVT != VT && "Don't know what type to promote to!");
878 bool Replace = false;
879 SDValue N0 = Op.getOperand(0);
881 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
882 else if (Opc == ISD::SRL)
883 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
885 N0 = PromoteOperand(N0, PVT, Replace);
886 if (N0.getNode() == 0)
889 AddToWorkList(N0.getNode());
891 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
893 DEBUG(dbgs() << "\nPromoting ";
894 Op.getNode()->dump(&DAG));
895 DebugLoc dl = Op.getDebugLoc();
896 return DAG.getNode(ISD::TRUNCATE, dl, VT,
897 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
902 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
903 if (!LegalOperations)
906 EVT VT = Op.getValueType();
907 if (VT.isVector() || !VT.isInteger())
910 // If operation type is 'undesirable', e.g. i16 on x86, consider
912 unsigned Opc = Op.getOpcode();
913 if (TLI.isTypeDesirableForOp(Opc, VT))
917 // Consult target whether it is a good idea to promote this operation and
918 // what's the right type to promote it to.
919 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
920 assert(PVT != VT && "Don't know what type to promote to!");
921 // fold (aext (aext x)) -> (aext x)
922 // fold (aext (zext x)) -> (zext x)
923 // fold (aext (sext x)) -> (sext x)
924 DEBUG(dbgs() << "\nPromoting ";
925 Op.getNode()->dump(&DAG));
926 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0));
931 bool DAGCombiner::PromoteLoad(SDValue Op) {
932 if (!LegalOperations)
935 EVT VT = Op.getValueType();
936 if (VT.isVector() || !VT.isInteger())
939 // If operation type is 'undesirable', e.g. i16 on x86, consider
941 unsigned Opc = Op.getOpcode();
942 if (TLI.isTypeDesirableForOp(Opc, VT))
946 // Consult target whether it is a good idea to promote this operation and
947 // what's the right type to promote it to.
948 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
949 assert(PVT != VT && "Don't know what type to promote to!");
951 DebugLoc dl = Op.getDebugLoc();
952 SDNode *N = Op.getNode();
953 LoadSDNode *LD = cast<LoadSDNode>(N);
954 EVT MemVT = LD->getMemoryVT();
955 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
956 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
958 : LD->getExtensionType();
959 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
960 LD->getChain(), LD->getBasePtr(),
961 LD->getPointerInfo(),
962 MemVT, LD->isVolatile(),
963 LD->isNonTemporal(), LD->getAlignment());
964 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
966 DEBUG(dbgs() << "\nPromoting ";
969 Result.getNode()->dump(&DAG);
971 WorkListRemover DeadNodes(*this);
972 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
973 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
974 removeFromWorkList(N);
976 AddToWorkList(Result.getNode());
983 //===----------------------------------------------------------------------===//
984 // Main DAG Combiner implementation
985 //===----------------------------------------------------------------------===//
987 void DAGCombiner::Run(CombineLevel AtLevel) {
988 // set the instance variables, so that the various visit routines may use it.
990 LegalOperations = Level >= AfterLegalizeVectorOps;
991 LegalTypes = Level >= AfterLegalizeTypes;
993 // Add all the dag nodes to the worklist.
994 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
995 E = DAG.allnodes_end(); I != E; ++I)
998 // Create a dummy node (which is not added to allnodes), that adds a reference
999 // to the root node, preventing it from being deleted, and tracking any
1000 // changes of the root.
1001 HandleSDNode Dummy(DAG.getRoot());
1003 // The root of the dag may dangle to deleted nodes until the dag combiner is
1004 // done. Set it to null to avoid confusion.
1005 DAG.setRoot(SDValue());
1007 // while the worklist isn't empty, find a node and
1008 // try and combine it.
1009 while (!WorkListContents.empty()) {
1011 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates.
1012 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the
1013 // worklist *should* contain, and check the node we want to visit is should
1014 // actually be visited.
1016 N = WorkListOrder.pop_back_val();
1017 } while (!WorkListContents.erase(N));
1019 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1020 // N is deleted from the DAG, since they too may now be dead or may have a
1021 // reduced number of uses, allowing other xforms.
1022 if (N->use_empty() && N != &Dummy) {
1023 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1024 AddToWorkList(N->getOperand(i).getNode());
1030 SDValue RV = combine(N);
1032 if (RV.getNode() == 0)
1037 // If we get back the same node we passed in, rather than a new node or
1038 // zero, we know that the node must have defined multiple values and
1039 // CombineTo was used. Since CombineTo takes care of the worklist
1040 // mechanics for us, we have no work to do in this case.
1041 if (RV.getNode() == N)
1044 assert(N->getOpcode() != ISD::DELETED_NODE &&
1045 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1046 "Node was deleted but visit returned new node!");
1048 DEBUG(dbgs() << "\nReplacing.3 ";
1050 dbgs() << "\nWith: ";
1051 RV.getNode()->dump(&DAG);
1054 // Transfer debug value.
1055 DAG.TransferDbgValues(SDValue(N, 0), RV);
1056 WorkListRemover DeadNodes(*this);
1057 if (N->getNumValues() == RV.getNode()->getNumValues())
1058 DAG.ReplaceAllUsesWith(N, RV.getNode());
1060 assert(N->getValueType(0) == RV.getValueType() &&
1061 N->getNumValues() == 1 && "Type mismatch");
1063 DAG.ReplaceAllUsesWith(N, &OpV);
1066 // Push the new node and any users onto the worklist
1067 AddToWorkList(RV.getNode());
1068 AddUsersToWorkList(RV.getNode());
1070 // Add any uses of the old node to the worklist in case this node is the
1071 // last one that uses them. They may become dead after this node is
1073 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1074 AddToWorkList(N->getOperand(i).getNode());
1076 // Finally, if the node is now dead, remove it from the graph. The node
1077 // may not be dead if the replacement process recursively simplified to
1078 // something else needing this node.
1079 if (N->use_empty()) {
1080 // Nodes can be reintroduced into the worklist. Make sure we do not
1081 // process a node that has been replaced.
1082 removeFromWorkList(N);
1084 // Finally, since the node is now dead, remove it from the graph.
1089 // If the root changed (e.g. it was a dead load, update the root).
1090 DAG.setRoot(Dummy.getValue());
1091 DAG.RemoveDeadNodes();
1094 SDValue DAGCombiner::visit(SDNode *N) {
1095 switch (N->getOpcode()) {
1097 case ISD::TokenFactor: return visitTokenFactor(N);
1098 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1099 case ISD::ADD: return visitADD(N);
1100 case ISD::SUB: return visitSUB(N);
1101 case ISD::ADDC: return visitADDC(N);
1102 case ISD::SUBC: return visitSUBC(N);
1103 case ISD::ADDE: return visitADDE(N);
1104 case ISD::SUBE: return visitSUBE(N);
1105 case ISD::MUL: return visitMUL(N);
1106 case ISD::SDIV: return visitSDIV(N);
1107 case ISD::UDIV: return visitUDIV(N);
1108 case ISD::SREM: return visitSREM(N);
1109 case ISD::UREM: return visitUREM(N);
1110 case ISD::MULHU: return visitMULHU(N);
1111 case ISD::MULHS: return visitMULHS(N);
1112 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1113 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1114 case ISD::SMULO: return visitSMULO(N);
1115 case ISD::UMULO: return visitUMULO(N);
1116 case ISD::SDIVREM: return visitSDIVREM(N);
1117 case ISD::UDIVREM: return visitUDIVREM(N);
1118 case ISD::AND: return visitAND(N);
1119 case ISD::OR: return visitOR(N);
1120 case ISD::XOR: return visitXOR(N);
1121 case ISD::SHL: return visitSHL(N);
1122 case ISD::SRA: return visitSRA(N);
1123 case ISD::SRL: return visitSRL(N);
1124 case ISD::CTLZ: return visitCTLZ(N);
1125 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1126 case ISD::CTTZ: return visitCTTZ(N);
1127 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1128 case ISD::CTPOP: return visitCTPOP(N);
1129 case ISD::SELECT: return visitSELECT(N);
1130 case ISD::SELECT_CC: return visitSELECT_CC(N);
1131 case ISD::SETCC: return visitSETCC(N);
1132 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1133 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1134 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1135 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1136 case ISD::TRUNCATE: return visitTRUNCATE(N);
1137 case ISD::BITCAST: return visitBITCAST(N);
1138 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1139 case ISD::FADD: return visitFADD(N);
1140 case ISD::FSUB: return visitFSUB(N);
1141 case ISD::FMUL: return visitFMUL(N);
1142 case ISD::FMA: return visitFMA(N);
1143 case ISD::FDIV: return visitFDIV(N);
1144 case ISD::FREM: return visitFREM(N);
1145 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1146 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1147 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1148 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1149 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1150 case ISD::FP_ROUND: return visitFP_ROUND(N);
1151 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1152 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1153 case ISD::FNEG: return visitFNEG(N);
1154 case ISD::FABS: return visitFABS(N);
1155 case ISD::FFLOOR: return visitFFLOOR(N);
1156 case ISD::FCEIL: return visitFCEIL(N);
1157 case ISD::FTRUNC: return visitFTRUNC(N);
1158 case ISD::BRCOND: return visitBRCOND(N);
1159 case ISD::BR_CC: return visitBR_CC(N);
1160 case ISD::LOAD: return visitLOAD(N);
1161 case ISD::STORE: return visitSTORE(N);
1162 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1163 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1164 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1165 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1166 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1167 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1168 case ISD::MEMBARRIER: return visitMEMBARRIER(N);
1173 SDValue DAGCombiner::combine(SDNode *N) {
1174 SDValue RV = visit(N);
1176 // If nothing happened, try a target-specific DAG combine.
1177 if (RV.getNode() == 0) {
1178 assert(N->getOpcode() != ISD::DELETED_NODE &&
1179 "Node was deleted but visit returned NULL!");
1181 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1182 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1184 // Expose the DAG combiner to the target combiner impls.
1185 TargetLowering::DAGCombinerInfo
1186 DagCombineInfo(DAG, Level, false, this);
1188 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1192 // If nothing happened still, try promoting the operation.
1193 if (RV.getNode() == 0) {
1194 switch (N->getOpcode()) {
1202 RV = PromoteIntBinOp(SDValue(N, 0));
1207 RV = PromoteIntShiftOp(SDValue(N, 0));
1209 case ISD::SIGN_EXTEND:
1210 case ISD::ZERO_EXTEND:
1211 case ISD::ANY_EXTEND:
1212 RV = PromoteExtend(SDValue(N, 0));
1215 if (PromoteLoad(SDValue(N, 0)))
1221 // If N is a commutative binary node, try commuting it to enable more
1223 if (RV.getNode() == 0 &&
1224 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1225 N->getNumValues() == 1) {
1226 SDValue N0 = N->getOperand(0);
1227 SDValue N1 = N->getOperand(1);
1229 // Constant operands are canonicalized to RHS.
1230 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1231 SDValue Ops[] = { N1, N0 };
1232 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1235 return SDValue(CSENode, 0);
1242 /// getInputChainForNode - Given a node, return its input chain if it has one,
1243 /// otherwise return a null sd operand.
1244 static SDValue getInputChainForNode(SDNode *N) {
1245 if (unsigned NumOps = N->getNumOperands()) {
1246 if (N->getOperand(0).getValueType() == MVT::Other)
1247 return N->getOperand(0);
1248 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1249 return N->getOperand(NumOps-1);
1250 for (unsigned i = 1; i < NumOps-1; ++i)
1251 if (N->getOperand(i).getValueType() == MVT::Other)
1252 return N->getOperand(i);
1257 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1258 // If N has two operands, where one has an input chain equal to the other,
1259 // the 'other' chain is redundant.
1260 if (N->getNumOperands() == 2) {
1261 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1262 return N->getOperand(0);
1263 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1264 return N->getOperand(1);
1267 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1268 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1269 SmallPtrSet<SDNode*, 16> SeenOps;
1270 bool Changed = false; // If we should replace this token factor.
1272 // Start out with this token factor.
1275 // Iterate through token factors. The TFs grows when new token factors are
1277 for (unsigned i = 0; i < TFs.size(); ++i) {
1278 SDNode *TF = TFs[i];
1280 // Check each of the operands.
1281 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1282 SDValue Op = TF->getOperand(i);
1284 switch (Op.getOpcode()) {
1285 case ISD::EntryToken:
1286 // Entry tokens don't need to be added to the list. They are
1291 case ISD::TokenFactor:
1292 if (Op.hasOneUse() &&
1293 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1294 // Queue up for processing.
1295 TFs.push_back(Op.getNode());
1296 // Clean up in case the token factor is removed.
1297 AddToWorkList(Op.getNode());
1304 // Only add if it isn't already in the list.
1305 if (SeenOps.insert(Op.getNode()))
1316 // If we've change things around then replace token factor.
1319 // The entry token is the only possible outcome.
1320 Result = DAG.getEntryNode();
1322 // New and improved token factor.
1323 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
1324 MVT::Other, &Ops[0], Ops.size());
1327 // Don't add users to work list.
1328 return CombineTo(N, Result, false);
1334 /// MERGE_VALUES can always be eliminated.
1335 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1336 WorkListRemover DeadNodes(*this);
1337 // Replacing results may cause a different MERGE_VALUES to suddenly
1338 // be CSE'd with N, and carry its uses with it. Iterate until no
1339 // uses remain, to ensure that the node can be safely deleted.
1340 // First add the users of this node to the work list so that they
1341 // can be tried again once they have new operands.
1342 AddUsersToWorkList(N);
1344 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1345 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i));
1346 } while (!N->use_empty());
1347 removeFromWorkList(N);
1349 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1353 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
1354 SelectionDAG &DAG) {
1355 EVT VT = N0.getValueType();
1356 SDValue N00 = N0.getOperand(0);
1357 SDValue N01 = N0.getOperand(1);
1358 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1360 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1361 isa<ConstantSDNode>(N00.getOperand(1))) {
1362 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1363 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1364 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1365 N00.getOperand(0), N01),
1366 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1367 N00.getOperand(1), N01));
1368 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1374 SDValue DAGCombiner::visitADD(SDNode *N) {
1375 SDValue N0 = N->getOperand(0);
1376 SDValue N1 = N->getOperand(1);
1377 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1378 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1379 EVT VT = N0.getValueType();
1382 if (VT.isVector()) {
1383 SDValue FoldedVOp = SimplifyVBinOp(N);
1384 if (FoldedVOp.getNode()) return FoldedVOp;
1386 // fold (add x, 0) -> x, vector edition
1387 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1389 if (ISD::isBuildVectorAllZeros(N0.getNode()))
1393 // fold (add x, undef) -> undef
1394 if (N0.getOpcode() == ISD::UNDEF)
1396 if (N1.getOpcode() == ISD::UNDEF)
1398 // fold (add c1, c2) -> c1+c2
1400 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1401 // canonicalize constant to RHS
1403 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1404 // fold (add x, 0) -> x
1405 if (N1C && N1C->isNullValue())
1407 // fold (add Sym, c) -> Sym+c
1408 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1409 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1410 GA->getOpcode() == ISD::GlobalAddress)
1411 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1413 (uint64_t)N1C->getSExtValue());
1414 // fold ((c1-A)+c2) -> (c1+c2)-A
1415 if (N1C && N0.getOpcode() == ISD::SUB)
1416 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1417 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1418 DAG.getConstant(N1C->getAPIntValue()+
1419 N0C->getAPIntValue(), VT),
1422 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1423 if (RADD.getNode() != 0)
1425 // fold ((0-A) + B) -> B-A
1426 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1427 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1428 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1429 // fold (A + (0-B)) -> A-B
1430 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1431 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1432 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1433 // fold (A+(B-A)) -> B
1434 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1435 return N1.getOperand(0);
1436 // fold ((B-A)+A) -> B
1437 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1438 return N0.getOperand(0);
1439 // fold (A+(B-(A+C))) to (B-C)
1440 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1441 N0 == N1.getOperand(1).getOperand(0))
1442 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1443 N1.getOperand(1).getOperand(1));
1444 // fold (A+(B-(C+A))) to (B-C)
1445 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1446 N0 == N1.getOperand(1).getOperand(1))
1447 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1448 N1.getOperand(1).getOperand(0));
1449 // fold (A+((B-A)+or-C)) to (B+or-C)
1450 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1451 N1.getOperand(0).getOpcode() == ISD::SUB &&
1452 N0 == N1.getOperand(0).getOperand(1))
1453 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1454 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1456 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1457 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1458 SDValue N00 = N0.getOperand(0);
1459 SDValue N01 = N0.getOperand(1);
1460 SDValue N10 = N1.getOperand(0);
1461 SDValue N11 = N1.getOperand(1);
1463 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1464 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1465 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1466 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1469 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1470 return SDValue(N, 0);
1472 // fold (a+b) -> (a|b) iff a and b share no bits.
1473 if (VT.isInteger() && !VT.isVector()) {
1474 APInt LHSZero, LHSOne;
1475 APInt RHSZero, RHSOne;
1476 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne);
1478 if (LHSZero.getBoolValue()) {
1479 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne);
1481 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1482 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1483 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1484 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1488 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1489 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1490 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1491 if (Result.getNode()) return Result;
1493 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1494 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1495 if (Result.getNode()) return Result;
1498 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1499 if (N1.getOpcode() == ISD::SHL &&
1500 N1.getOperand(0).getOpcode() == ISD::SUB)
1501 if (ConstantSDNode *C =
1502 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1503 if (C->getAPIntValue() == 0)
1504 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1505 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1506 N1.getOperand(0).getOperand(1),
1508 if (N0.getOpcode() == ISD::SHL &&
1509 N0.getOperand(0).getOpcode() == ISD::SUB)
1510 if (ConstantSDNode *C =
1511 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1512 if (C->getAPIntValue() == 0)
1513 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1514 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1515 N0.getOperand(0).getOperand(1),
1518 if (N1.getOpcode() == ISD::AND) {
1519 SDValue AndOp0 = N1.getOperand(0);
1520 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1521 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1522 unsigned DestBits = VT.getScalarType().getSizeInBits();
1524 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1525 // and similar xforms where the inner op is either ~0 or 0.
1526 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1527 DebugLoc DL = N->getDebugLoc();
1528 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1532 // add (sext i1), X -> sub X, (zext i1)
1533 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1534 N0.getOperand(0).getValueType() == MVT::i1 &&
1535 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1536 DebugLoc DL = N->getDebugLoc();
1537 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1538 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1544 SDValue DAGCombiner::visitADDC(SDNode *N) {
1545 SDValue N0 = N->getOperand(0);
1546 SDValue N1 = N->getOperand(1);
1547 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1548 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1549 EVT VT = N0.getValueType();
1551 // If the flag result is dead, turn this into an ADD.
1552 if (!N->hasAnyUseOfValue(1))
1553 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1),
1554 DAG.getNode(ISD::CARRY_FALSE,
1555 N->getDebugLoc(), MVT::Glue));
1557 // canonicalize constant to RHS.
1559 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1561 // fold (addc x, 0) -> x + no carry out
1562 if (N1C && N1C->isNullValue())
1563 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1564 N->getDebugLoc(), MVT::Glue));
1566 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1567 APInt LHSZero, LHSOne;
1568 APInt RHSZero, RHSOne;
1569 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne);
1571 if (LHSZero.getBoolValue()) {
1572 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne);
1574 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1575 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1576 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1577 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1578 DAG.getNode(ISD::CARRY_FALSE,
1579 N->getDebugLoc(), MVT::Glue));
1585 SDValue DAGCombiner::visitADDE(SDNode *N) {
1586 SDValue N0 = N->getOperand(0);
1587 SDValue N1 = N->getOperand(1);
1588 SDValue CarryIn = N->getOperand(2);
1589 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1590 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1592 // canonicalize constant to RHS
1594 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1597 // fold (adde x, y, false) -> (addc x, y)
1598 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1599 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1);
1604 // Since it may not be valid to emit a fold to zero for vector initializers
1605 // check if we can before folding.
1606 static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT,
1607 SelectionDAG &DAG, bool LegalOperations) {
1608 if (!VT.isVector()) {
1609 return DAG.getConstant(0, VT);
1611 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1612 // Produce a vector of zeros.
1613 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
1614 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
1615 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
1616 &Ops[0], Ops.size());
1621 SDValue DAGCombiner::visitSUB(SDNode *N) {
1622 SDValue N0 = N->getOperand(0);
1623 SDValue N1 = N->getOperand(1);
1624 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1625 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1626 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 :
1627 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1628 EVT VT = N0.getValueType();
1631 if (VT.isVector()) {
1632 SDValue FoldedVOp = SimplifyVBinOp(N);
1633 if (FoldedVOp.getNode()) return FoldedVOp;
1635 // fold (sub x, 0) -> x, vector edition
1636 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1640 // fold (sub x, x) -> 0
1641 // FIXME: Refactor this and xor and other similar operations together.
1643 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
1644 // fold (sub c1, c2) -> c1-c2
1646 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1647 // fold (sub x, c) -> (add x, -c)
1649 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1650 DAG.getConstant(-N1C->getAPIntValue(), VT));
1651 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1652 if (N0C && N0C->isAllOnesValue())
1653 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1654 // fold A-(A-B) -> B
1655 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1656 return N1.getOperand(1);
1657 // fold (A+B)-A -> B
1658 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1659 return N0.getOperand(1);
1660 // fold (A+B)-B -> A
1661 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1662 return N0.getOperand(0);
1663 // fold C2-(A+C1) -> (C2-C1)-A
1664 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1665 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(),
1667 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC,
1670 // fold ((A+(B+or-C))-B) -> A+or-C
1671 if (N0.getOpcode() == ISD::ADD &&
1672 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1673 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1674 N0.getOperand(1).getOperand(0) == N1)
1675 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1676 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1677 // fold ((A+(C+B))-B) -> A+C
1678 if (N0.getOpcode() == ISD::ADD &&
1679 N0.getOperand(1).getOpcode() == ISD::ADD &&
1680 N0.getOperand(1).getOperand(1) == N1)
1681 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1682 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1683 // fold ((A-(B-C))-C) -> A-B
1684 if (N0.getOpcode() == ISD::SUB &&
1685 N0.getOperand(1).getOpcode() == ISD::SUB &&
1686 N0.getOperand(1).getOperand(1) == N1)
1687 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1688 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1690 // If either operand of a sub is undef, the result is undef
1691 if (N0.getOpcode() == ISD::UNDEF)
1693 if (N1.getOpcode() == ISD::UNDEF)
1696 // If the relocation model supports it, consider symbol offsets.
1697 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1698 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1699 // fold (sub Sym, c) -> Sym-c
1700 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1701 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1703 (uint64_t)N1C->getSExtValue());
1704 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1705 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1706 if (GA->getGlobal() == GB->getGlobal())
1707 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1714 SDValue DAGCombiner::visitSUBC(SDNode *N) {
1715 SDValue N0 = N->getOperand(0);
1716 SDValue N1 = N->getOperand(1);
1717 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1718 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1719 EVT VT = N0.getValueType();
1721 // If the flag result is dead, turn this into an SUB.
1722 if (!N->hasAnyUseOfValue(1))
1723 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1),
1724 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1727 // fold (subc x, x) -> 0 + no borrow
1729 return CombineTo(N, DAG.getConstant(0, VT),
1730 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1733 // fold (subc x, 0) -> x + no borrow
1734 if (N1C && N1C->isNullValue())
1735 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1738 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
1739 if (N0C && N0C->isAllOnesValue())
1740 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0),
1741 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1747 SDValue DAGCombiner::visitSUBE(SDNode *N) {
1748 SDValue N0 = N->getOperand(0);
1749 SDValue N1 = N->getOperand(1);
1750 SDValue CarryIn = N->getOperand(2);
1752 // fold (sube x, y, false) -> (subc x, y)
1753 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1754 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1);
1759 SDValue DAGCombiner::visitMUL(SDNode *N) {
1760 SDValue N0 = N->getOperand(0);
1761 SDValue N1 = N->getOperand(1);
1762 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1763 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1764 EVT VT = N0.getValueType();
1767 if (VT.isVector()) {
1768 SDValue FoldedVOp = SimplifyVBinOp(N);
1769 if (FoldedVOp.getNode()) return FoldedVOp;
1772 // fold (mul x, undef) -> 0
1773 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1774 return DAG.getConstant(0, VT);
1775 // fold (mul c1, c2) -> c1*c2
1777 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1778 // canonicalize constant to RHS
1780 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1781 // fold (mul x, 0) -> 0
1782 if (N1C && N1C->isNullValue())
1784 // fold (mul x, -1) -> 0-x
1785 if (N1C && N1C->isAllOnesValue())
1786 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1787 DAG.getConstant(0, VT), N0);
1788 // fold (mul x, (1 << c)) -> x << c
1789 if (N1C && N1C->getAPIntValue().isPowerOf2())
1790 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1791 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1792 getShiftAmountTy(N0.getValueType())));
1793 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1794 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1795 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1796 // FIXME: If the input is something that is easily negated (e.g. a
1797 // single-use add), we should put the negate there.
1798 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1799 DAG.getConstant(0, VT),
1800 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1801 DAG.getConstant(Log2Val,
1802 getShiftAmountTy(N0.getValueType()))));
1804 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1805 if (N1C && N0.getOpcode() == ISD::SHL &&
1806 isa<ConstantSDNode>(N0.getOperand(1))) {
1807 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1808 N1, N0.getOperand(1));
1809 AddToWorkList(C3.getNode());
1810 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1811 N0.getOperand(0), C3);
1814 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1817 SDValue Sh(0,0), Y(0,0);
1818 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1819 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1820 N0.getNode()->hasOneUse()) {
1822 } else if (N1.getOpcode() == ISD::SHL &&
1823 isa<ConstantSDNode>(N1.getOperand(1)) &&
1824 N1.getNode()->hasOneUse()) {
1829 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1830 Sh.getOperand(0), Y);
1831 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1832 Mul, Sh.getOperand(1));
1836 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1837 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1838 isa<ConstantSDNode>(N0.getOperand(1)))
1839 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1840 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1841 N0.getOperand(0), N1),
1842 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1843 N0.getOperand(1), N1));
1846 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1847 if (RMUL.getNode() != 0)
1853 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1854 SDValue N0 = N->getOperand(0);
1855 SDValue N1 = N->getOperand(1);
1856 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1857 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1858 EVT VT = N->getValueType(0);
1861 if (VT.isVector()) {
1862 SDValue FoldedVOp = SimplifyVBinOp(N);
1863 if (FoldedVOp.getNode()) return FoldedVOp;
1866 // fold (sdiv c1, c2) -> c1/c2
1867 if (N0C && N1C && !N1C->isNullValue())
1868 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1869 // fold (sdiv X, 1) -> X
1870 if (N1C && N1C->getAPIntValue() == 1LL)
1872 // fold (sdiv X, -1) -> 0-X
1873 if (N1C && N1C->isAllOnesValue())
1874 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1875 DAG.getConstant(0, VT), N0);
1876 // If we know the sign bits of both operands are zero, strength reduce to a
1877 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1878 if (!VT.isVector()) {
1879 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1880 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1883 // fold (sdiv X, pow2) -> simple ops after legalize
1884 if (N1C && !N1C->isNullValue() &&
1885 (N1C->getAPIntValue().isPowerOf2() ||
1886 (-N1C->getAPIntValue()).isPowerOf2())) {
1887 // If dividing by powers of two is cheap, then don't perform the following
1889 if (TLI.isPow2DivCheap())
1892 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
1894 // Splat the sign bit into the register
1895 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1896 DAG.getConstant(VT.getSizeInBits()-1,
1897 getShiftAmountTy(N0.getValueType())));
1898 AddToWorkList(SGN.getNode());
1900 // Add (N0 < 0) ? abs2 - 1 : 0;
1901 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1902 DAG.getConstant(VT.getSizeInBits() - lg2,
1903 getShiftAmountTy(SGN.getValueType())));
1904 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1905 AddToWorkList(SRL.getNode());
1906 AddToWorkList(ADD.getNode()); // Divide by pow2
1907 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1908 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
1910 // If we're dividing by a positive value, we're done. Otherwise, we must
1911 // negate the result.
1912 if (N1C->getAPIntValue().isNonNegative())
1915 AddToWorkList(SRA.getNode());
1916 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1917 DAG.getConstant(0, VT), SRA);
1920 // if integer divide is expensive and we satisfy the requirements, emit an
1921 // alternate sequence.
1922 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1923 SDValue Op = BuildSDIV(N);
1924 if (Op.getNode()) return Op;
1928 if (N0.getOpcode() == ISD::UNDEF)
1929 return DAG.getConstant(0, VT);
1930 // X / undef -> undef
1931 if (N1.getOpcode() == ISD::UNDEF)
1937 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1938 SDValue N0 = N->getOperand(0);
1939 SDValue N1 = N->getOperand(1);
1940 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1941 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1942 EVT VT = N->getValueType(0);
1945 if (VT.isVector()) {
1946 SDValue FoldedVOp = SimplifyVBinOp(N);
1947 if (FoldedVOp.getNode()) return FoldedVOp;
1950 // fold (udiv c1, c2) -> c1/c2
1951 if (N0C && N1C && !N1C->isNullValue())
1952 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1953 // fold (udiv x, (1 << c)) -> x >>u c
1954 if (N1C && N1C->getAPIntValue().isPowerOf2())
1955 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1956 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1957 getShiftAmountTy(N0.getValueType())));
1958 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1959 if (N1.getOpcode() == ISD::SHL) {
1960 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1961 if (SHC->getAPIntValue().isPowerOf2()) {
1962 EVT ADDVT = N1.getOperand(1).getValueType();
1963 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1965 DAG.getConstant(SHC->getAPIntValue()
1968 AddToWorkList(Add.getNode());
1969 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1973 // fold (udiv x, c) -> alternate
1974 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1975 SDValue Op = BuildUDIV(N);
1976 if (Op.getNode()) return Op;
1980 if (N0.getOpcode() == ISD::UNDEF)
1981 return DAG.getConstant(0, VT);
1982 // X / undef -> undef
1983 if (N1.getOpcode() == ISD::UNDEF)
1989 SDValue DAGCombiner::visitSREM(SDNode *N) {
1990 SDValue N0 = N->getOperand(0);
1991 SDValue N1 = N->getOperand(1);
1992 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1993 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1994 EVT VT = N->getValueType(0);
1996 // fold (srem c1, c2) -> c1%c2
1997 if (N0C && N1C && !N1C->isNullValue())
1998 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1999 // If we know the sign bits of both operands are zero, strength reduce to a
2000 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
2001 if (!VT.isVector()) {
2002 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2003 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
2006 // If X/C can be simplified by the division-by-constant logic, lower
2007 // X%C to the equivalent of X-X/C*C.
2008 if (N1C && !N1C->isNullValue()) {
2009 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
2010 AddToWorkList(Div.getNode());
2011 SDValue OptimizedDiv = combine(Div.getNode());
2012 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2013 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
2015 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
2016 AddToWorkList(Mul.getNode());
2022 if (N0.getOpcode() == ISD::UNDEF)
2023 return DAG.getConstant(0, VT);
2024 // X % undef -> undef
2025 if (N1.getOpcode() == ISD::UNDEF)
2031 SDValue DAGCombiner::visitUREM(SDNode *N) {
2032 SDValue N0 = N->getOperand(0);
2033 SDValue N1 = N->getOperand(1);
2034 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2035 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2036 EVT VT = N->getValueType(0);
2038 // fold (urem c1, c2) -> c1%c2
2039 if (N0C && N1C && !N1C->isNullValue())
2040 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
2041 // fold (urem x, pow2) -> (and x, pow2-1)
2042 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
2043 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
2044 DAG.getConstant(N1C->getAPIntValue()-1,VT));
2045 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
2046 if (N1.getOpcode() == ISD::SHL) {
2047 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2048 if (SHC->getAPIntValue().isPowerOf2()) {
2050 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
2051 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
2053 AddToWorkList(Add.getNode());
2054 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
2059 // If X/C can be simplified by the division-by-constant logic, lower
2060 // X%C to the equivalent of X-X/C*C.
2061 if (N1C && !N1C->isNullValue()) {
2062 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
2063 AddToWorkList(Div.getNode());
2064 SDValue OptimizedDiv = combine(Div.getNode());
2065 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2066 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
2068 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
2069 AddToWorkList(Mul.getNode());
2075 if (N0.getOpcode() == ISD::UNDEF)
2076 return DAG.getConstant(0, VT);
2077 // X % undef -> undef
2078 if (N1.getOpcode() == ISD::UNDEF)
2084 SDValue DAGCombiner::visitMULHS(SDNode *N) {
2085 SDValue N0 = N->getOperand(0);
2086 SDValue N1 = N->getOperand(1);
2087 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2088 EVT VT = N->getValueType(0);
2089 DebugLoc DL = N->getDebugLoc();
2091 // fold (mulhs x, 0) -> 0
2092 if (N1C && N1C->isNullValue())
2094 // fold (mulhs x, 1) -> (sra x, size(x)-1)
2095 if (N1C && N1C->getAPIntValue() == 1)
2096 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
2097 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2098 getShiftAmountTy(N0.getValueType())));
2099 // fold (mulhs x, undef) -> 0
2100 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2101 return DAG.getConstant(0, VT);
2103 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2105 if (VT.isSimple() && !VT.isVector()) {
2106 MVT Simple = VT.getSimpleVT();
2107 unsigned SimpleSize = Simple.getSizeInBits();
2108 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2109 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2110 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2111 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2112 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2113 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2114 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2115 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2122 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2123 SDValue N0 = N->getOperand(0);
2124 SDValue N1 = N->getOperand(1);
2125 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2126 EVT VT = N->getValueType(0);
2127 DebugLoc DL = N->getDebugLoc();
2129 // fold (mulhu x, 0) -> 0
2130 if (N1C && N1C->isNullValue())
2132 // fold (mulhu x, 1) -> 0
2133 if (N1C && N1C->getAPIntValue() == 1)
2134 return DAG.getConstant(0, N0.getValueType());
2135 // fold (mulhu x, undef) -> 0
2136 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2137 return DAG.getConstant(0, VT);
2139 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2141 if (VT.isSimple() && !VT.isVector()) {
2142 MVT Simple = VT.getSimpleVT();
2143 unsigned SimpleSize = Simple.getSizeInBits();
2144 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2145 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2146 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2147 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2148 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2149 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2150 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2151 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2158 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
2159 /// compute two values. LoOp and HiOp give the opcodes for the two computations
2160 /// that are being performed. Return true if a simplification was made.
2162 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2164 // If the high half is not needed, just compute the low half.
2165 bool HiExists = N->hasAnyUseOfValue(1);
2167 (!LegalOperations ||
2168 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
2169 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2170 N->op_begin(), N->getNumOperands());
2171 return CombineTo(N, Res, Res);
2174 // If the low half is not needed, just compute the high half.
2175 bool LoExists = N->hasAnyUseOfValue(0);
2177 (!LegalOperations ||
2178 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2179 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2180 N->op_begin(), N->getNumOperands());
2181 return CombineTo(N, Res, Res);
2184 // If both halves are used, return as it is.
2185 if (LoExists && HiExists)
2188 // If the two computed results can be simplified separately, separate them.
2190 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2191 N->op_begin(), N->getNumOperands());
2192 AddToWorkList(Lo.getNode());
2193 SDValue LoOpt = combine(Lo.getNode());
2194 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2195 (!LegalOperations ||
2196 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2197 return CombineTo(N, LoOpt, LoOpt);
2201 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2202 N->op_begin(), N->getNumOperands());
2203 AddToWorkList(Hi.getNode());
2204 SDValue HiOpt = combine(Hi.getNode());
2205 if (HiOpt.getNode() && HiOpt != Hi &&
2206 (!LegalOperations ||
2207 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2208 return CombineTo(N, HiOpt, HiOpt);
2214 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2215 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2216 if (Res.getNode()) return Res;
2218 EVT VT = N->getValueType(0);
2219 DebugLoc DL = N->getDebugLoc();
2221 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2223 if (VT.isSimple() && !VT.isVector()) {
2224 MVT Simple = VT.getSimpleVT();
2225 unsigned SimpleSize = Simple.getSizeInBits();
2226 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2227 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2228 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2229 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2230 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2231 // Compute the high part as N1.
2232 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2233 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2234 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2235 // Compute the low part as N0.
2236 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2237 return CombineTo(N, Lo, Hi);
2244 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2245 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2246 if (Res.getNode()) return Res;
2248 EVT VT = N->getValueType(0);
2249 DebugLoc DL = N->getDebugLoc();
2251 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2253 if (VT.isSimple() && !VT.isVector()) {
2254 MVT Simple = VT.getSimpleVT();
2255 unsigned SimpleSize = Simple.getSizeInBits();
2256 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2257 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2258 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2259 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2260 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2261 // Compute the high part as N1.
2262 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2263 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2264 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2265 // Compute the low part as N0.
2266 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2267 return CombineTo(N, Lo, Hi);
2274 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2275 // (smulo x, 2) -> (saddo x, x)
2276 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2277 if (C2->getAPIntValue() == 2)
2278 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(),
2279 N->getOperand(0), N->getOperand(0));
2284 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2285 // (umulo x, 2) -> (uaddo x, x)
2286 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2287 if (C2->getAPIntValue() == 2)
2288 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(),
2289 N->getOperand(0), N->getOperand(0));
2294 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2295 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2296 if (Res.getNode()) return Res;
2301 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2302 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2303 if (Res.getNode()) return Res;
2308 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2309 /// two operands of the same opcode, try to simplify it.
2310 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2311 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2312 EVT VT = N0.getValueType();
2313 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2315 // Bail early if none of these transforms apply.
2316 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2318 // For each of OP in AND/OR/XOR:
2319 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2320 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2321 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2322 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2324 // do not sink logical op inside of a vector extend, since it may combine
2326 EVT Op0VT = N0.getOperand(0).getValueType();
2327 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2328 N0.getOpcode() == ISD::SIGN_EXTEND ||
2329 // Avoid infinite looping with PromoteIntBinOp.
2330 (N0.getOpcode() == ISD::ANY_EXTEND &&
2331 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2332 (N0.getOpcode() == ISD::TRUNCATE &&
2333 (!TLI.isZExtFree(VT, Op0VT) ||
2334 !TLI.isTruncateFree(Op0VT, VT)) &&
2335 TLI.isTypeLegal(Op0VT))) &&
2337 Op0VT == N1.getOperand(0).getValueType() &&
2338 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2339 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2340 N0.getOperand(0).getValueType(),
2341 N0.getOperand(0), N1.getOperand(0));
2342 AddToWorkList(ORNode.getNode());
2343 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
2346 // For each of OP in SHL/SRL/SRA/AND...
2347 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2348 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2349 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2350 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2351 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2352 N0.getOperand(1) == N1.getOperand(1)) {
2353 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2354 N0.getOperand(0).getValueType(),
2355 N0.getOperand(0), N1.getOperand(0));
2356 AddToWorkList(ORNode.getNode());
2357 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
2358 ORNode, N0.getOperand(1));
2361 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
2362 // Only perform this optimization after type legalization and before
2363 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
2364 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
2365 // we don't want to undo this promotion.
2366 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
2368 if ((N0.getOpcode() == ISD::BITCAST ||
2369 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) &&
2370 Level == AfterLegalizeTypes) {
2371 SDValue In0 = N0.getOperand(0);
2372 SDValue In1 = N1.getOperand(0);
2373 EVT In0Ty = In0.getValueType();
2374 EVT In1Ty = In1.getValueType();
2375 DebugLoc DL = N->getDebugLoc();
2376 // If both incoming values are integers, and the original types are the
2378 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) {
2379 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1);
2380 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op);
2381 AddToWorkList(Op.getNode());
2386 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
2387 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
2388 // If both shuffles use the same mask, and both shuffle within a single
2389 // vector, then it is worthwhile to move the swizzle after the operation.
2390 // The type-legalizer generates this pattern when loading illegal
2391 // vector types from memory. In many cases this allows additional shuffle
2393 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
2394 N0.getOperand(1).getOpcode() == ISD::UNDEF &&
2395 N1.getOperand(1).getOpcode() == ISD::UNDEF) {
2396 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
2397 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
2399 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() &&
2400 "Inputs to shuffles are not the same type");
2402 unsigned NumElts = VT.getVectorNumElements();
2404 // Check that both shuffles use the same mask. The masks are known to be of
2405 // the same length because the result vector type is the same.
2406 bool SameMask = true;
2407 for (unsigned i = 0; i != NumElts; ++i) {
2408 int Idx0 = SVN0->getMaskElt(i);
2409 int Idx1 = SVN1->getMaskElt(i);
2417 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT,
2418 N0.getOperand(0), N1.getOperand(0));
2419 AddToWorkList(Op.getNode());
2420 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Op,
2421 DAG.getUNDEF(VT), &SVN0->getMask()[0]);
2428 SDValue DAGCombiner::visitAND(SDNode *N) {
2429 SDValue N0 = N->getOperand(0);
2430 SDValue N1 = N->getOperand(1);
2431 SDValue LL, LR, RL, RR, CC0, CC1;
2432 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2433 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2434 EVT VT = N1.getValueType();
2435 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2438 if (VT.isVector()) {
2439 SDValue FoldedVOp = SimplifyVBinOp(N);
2440 if (FoldedVOp.getNode()) return FoldedVOp;
2442 // fold (and x, 0) -> 0, vector edition
2443 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2445 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2448 // fold (and x, -1) -> x, vector edition
2449 if (ISD::isBuildVectorAllOnes(N0.getNode()))
2451 if (ISD::isBuildVectorAllOnes(N1.getNode()))
2455 // fold (and x, undef) -> 0
2456 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2457 return DAG.getConstant(0, VT);
2458 // fold (and c1, c2) -> c1&c2
2460 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2461 // canonicalize constant to RHS
2463 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
2464 // fold (and x, -1) -> x
2465 if (N1C && N1C->isAllOnesValue())
2467 // if (and x, c) is known to be zero, return 0
2468 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2469 APInt::getAllOnesValue(BitWidth)))
2470 return DAG.getConstant(0, VT);
2472 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
2473 if (RAND.getNode() != 0)
2475 // fold (and (or x, C), D) -> D if (C & D) == D
2476 if (N1C && N0.getOpcode() == ISD::OR)
2477 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2478 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2480 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2481 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2482 SDValue N0Op0 = N0.getOperand(0);
2483 APInt Mask = ~N1C->getAPIntValue();
2484 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2485 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2486 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
2487 N0.getValueType(), N0Op0);
2489 // Replace uses of the AND with uses of the Zero extend node.
2492 // We actually want to replace all uses of the any_extend with the
2493 // zero_extend, to avoid duplicating things. This will later cause this
2494 // AND to be folded.
2495 CombineTo(N0.getNode(), Zext);
2496 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2499 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
2500 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
2501 // already be zero by virtue of the width of the base type of the load.
2503 // the 'X' node here can either be nothing or an extract_vector_elt to catch
2505 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
2506 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
2507 N0.getOpcode() == ISD::LOAD) {
2508 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
2509 N0 : N0.getOperand(0) );
2511 // Get the constant (if applicable) the zero'th operand is being ANDed with.
2512 // This can be a pure constant or a vector splat, in which case we treat the
2513 // vector as a scalar and use the splat value.
2514 APInt Constant = APInt::getNullValue(1);
2515 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
2516 Constant = C->getAPIntValue();
2517 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
2518 APInt SplatValue, SplatUndef;
2519 unsigned SplatBitSize;
2521 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
2522 SplatBitSize, HasAnyUndefs);
2524 // Undef bits can contribute to a possible optimisation if set, so
2526 SplatValue |= SplatUndef;
2528 // The splat value may be something like "0x00FFFFFF", which means 0 for
2529 // the first vector value and FF for the rest, repeating. We need a mask
2530 // that will apply equally to all members of the vector, so AND all the
2531 // lanes of the constant together.
2532 EVT VT = Vector->getValueType(0);
2533 unsigned BitWidth = VT.getVectorElementType().getSizeInBits();
2535 // If the splat value has been compressed to a bitlength lower
2536 // than the size of the vector lane, we need to re-expand it to
2538 if (BitWidth > SplatBitSize)
2539 for (SplatValue = SplatValue.zextOrTrunc(BitWidth);
2540 SplatBitSize < BitWidth;
2541 SplatBitSize = SplatBitSize * 2)
2542 SplatValue |= SplatValue.shl(SplatBitSize);
2544 Constant = APInt::getAllOnesValue(BitWidth);
2545 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i)
2546 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
2550 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
2551 // actually legal and isn't going to get expanded, else this is a false
2553 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
2554 Load->getMemoryVT());
2556 // Resize the constant to the same size as the original memory access before
2557 // extension. If it is still the AllOnesValue then this AND is completely
2560 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits());
2563 switch (Load->getExtensionType()) {
2564 default: B = false; break;
2565 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
2567 case ISD::NON_EXTLOAD: B = true; break;
2570 if (B && Constant.isAllOnesValue()) {
2571 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
2572 // preserve semantics once we get rid of the AND.
2573 SDValue NewLoad(Load, 0);
2574 if (Load->getExtensionType() == ISD::EXTLOAD) {
2575 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
2576 Load->getValueType(0), Load->getDebugLoc(),
2577 Load->getChain(), Load->getBasePtr(),
2578 Load->getOffset(), Load->getMemoryVT(),
2579 Load->getMemOperand());
2580 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
2581 if (Load->getNumValues() == 3) {
2582 // PRE/POST_INC loads have 3 values.
2583 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
2584 NewLoad.getValue(2) };
2585 CombineTo(Load, To, 3, true);
2587 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
2591 // Fold the AND away, taking care not to fold to the old load node if we
2593 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
2595 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2598 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2599 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2600 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2601 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2603 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2604 LL.getValueType().isInteger()) {
2605 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2606 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2607 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2608 LR.getValueType(), LL, RL);
2609 AddToWorkList(ORNode.getNode());
2610 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2612 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2613 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2614 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
2615 LR.getValueType(), LL, RL);
2616 AddToWorkList(ANDNode.getNode());
2617 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2619 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2620 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2621 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2622 LR.getValueType(), LL, RL);
2623 AddToWorkList(ORNode.getNode());
2624 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2627 // canonicalize equivalent to ll == rl
2628 if (LL == RR && LR == RL) {
2629 Op1 = ISD::getSetCCSwappedOperands(Op1);
2632 if (LL == RL && LR == RR) {
2633 bool isInteger = LL.getValueType().isInteger();
2634 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2635 if (Result != ISD::SETCC_INVALID &&
2636 (!LegalOperations ||
2637 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
2638 TLI.isOperationLegal(ISD::SETCC,
2639 TLI.getSetCCResultType(N0.getSimpleValueType())))))
2640 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2645 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2646 if (N0.getOpcode() == N1.getOpcode()) {
2647 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2648 if (Tmp.getNode()) return Tmp;
2651 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2652 // fold (and (sra)) -> (and (srl)) when possible.
2653 if (!VT.isVector() &&
2654 SimplifyDemandedBits(SDValue(N, 0)))
2655 return SDValue(N, 0);
2657 // fold (zext_inreg (extload x)) -> (zextload x)
2658 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2659 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2660 EVT MemVT = LN0->getMemoryVT();
2661 // If we zero all the possible extended bits, then we can turn this into
2662 // a zextload if we are running before legalize or the operation is legal.
2663 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2664 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2665 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2666 ((!LegalOperations && !LN0->isVolatile()) ||
2667 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2668 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2669 LN0->getChain(), LN0->getBasePtr(),
2670 LN0->getPointerInfo(), MemVT,
2671 LN0->isVolatile(), LN0->isNonTemporal(),
2672 LN0->getAlignment());
2674 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2675 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2678 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2679 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2681 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2682 EVT MemVT = LN0->getMemoryVT();
2683 // If we zero all the possible extended bits, then we can turn this into
2684 // a zextload if we are running before legalize or the operation is legal.
2685 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2686 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2687 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2688 ((!LegalOperations && !LN0->isVolatile()) ||
2689 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2690 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2692 LN0->getBasePtr(), LN0->getPointerInfo(),
2694 LN0->isVolatile(), LN0->isNonTemporal(),
2695 LN0->getAlignment());
2697 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2698 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2702 // fold (and (load x), 255) -> (zextload x, i8)
2703 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2704 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2705 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2706 (N0.getOpcode() == ISD::ANY_EXTEND &&
2707 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2708 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2709 LoadSDNode *LN0 = HasAnyExt
2710 ? cast<LoadSDNode>(N0.getOperand(0))
2711 : cast<LoadSDNode>(N0);
2712 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2713 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2714 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2715 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2716 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2717 EVT LoadedVT = LN0->getMemoryVT();
2719 if (ExtVT == LoadedVT &&
2720 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2721 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2724 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2725 LN0->getChain(), LN0->getBasePtr(),
2726 LN0->getPointerInfo(),
2727 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2728 LN0->getAlignment());
2730 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2731 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2734 // Do not change the width of a volatile load.
2735 // Do not generate loads of non-round integer types since these can
2736 // be expensive (and would be wrong if the type is not byte sized).
2737 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2738 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2739 EVT PtrType = LN0->getOperand(1).getValueType();
2741 unsigned Alignment = LN0->getAlignment();
2742 SDValue NewPtr = LN0->getBasePtr();
2744 // For big endian targets, we need to add an offset to the pointer
2745 // to load the correct bytes. For little endian systems, we merely
2746 // need to read fewer bytes from the same pointer.
2747 if (TLI.isBigEndian()) {
2748 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2749 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2750 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2751 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2752 NewPtr, DAG.getConstant(PtrOff, PtrType));
2753 Alignment = MinAlign(Alignment, PtrOff);
2756 AddToWorkList(NewPtr.getNode());
2758 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2760 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2761 LN0->getChain(), NewPtr,
2762 LN0->getPointerInfo(),
2763 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2766 CombineTo(LN0, Load, Load.getValue(1));
2767 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2773 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
2774 VT.getSizeInBits() <= 64) {
2775 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2776 APInt ADDC = ADDI->getAPIntValue();
2777 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2778 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
2779 // immediate for an add, but it is legal if its top c2 bits are set,
2780 // transform the ADD so the immediate doesn't need to be materialized
2782 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
2783 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
2784 SRLI->getZExtValue());
2785 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
2787 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2789 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
2790 N0.getOperand(0), DAG.getConstant(ADDC, VT));
2791 CombineTo(N0.getNode(), NewAdd);
2792 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2803 /// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16
2805 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
2806 bool DemandHighBits) {
2807 if (!LegalOperations)
2810 EVT VT = N->getValueType(0);
2811 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
2813 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2816 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
2817 bool LookPassAnd0 = false;
2818 bool LookPassAnd1 = false;
2819 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2821 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
2823 if (N0.getOpcode() == ISD::AND) {
2824 if (!N0.getNode()->hasOneUse())
2826 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2827 if (!N01C || N01C->getZExtValue() != 0xFF00)
2829 N0 = N0.getOperand(0);
2830 LookPassAnd0 = true;
2833 if (N1.getOpcode() == ISD::AND) {
2834 if (!N1.getNode()->hasOneUse())
2836 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2837 if (!N11C || N11C->getZExtValue() != 0xFF)
2839 N1 = N1.getOperand(0);
2840 LookPassAnd1 = true;
2843 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2845 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2847 if (!N0.getNode()->hasOneUse() ||
2848 !N1.getNode()->hasOneUse())
2851 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2852 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2855 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
2858 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
2859 SDValue N00 = N0->getOperand(0);
2860 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
2861 if (!N00.getNode()->hasOneUse())
2863 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
2864 if (!N001C || N001C->getZExtValue() != 0xFF)
2866 N00 = N00.getOperand(0);
2867 LookPassAnd0 = true;
2870 SDValue N10 = N1->getOperand(0);
2871 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
2872 if (!N10.getNode()->hasOneUse())
2874 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
2875 if (!N101C || N101C->getZExtValue() != 0xFF00)
2877 N10 = N10.getOperand(0);
2878 LookPassAnd1 = true;
2884 // Make sure everything beyond the low halfword is zero since the SRL 16
2885 // will clear the top bits.
2886 unsigned OpSizeInBits = VT.getSizeInBits();
2887 if (DemandHighBits && OpSizeInBits > 16 &&
2888 (!LookPassAnd0 || !LookPassAnd1) &&
2889 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16)))
2892 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00);
2893 if (OpSizeInBits > 16)
2894 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res,
2895 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT)));
2899 /// isBSwapHWordElement - Return true if the specified node is an element
2900 /// that makes up a 32-bit packed halfword byteswap. i.e.
2901 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2902 static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) {
2903 if (!N.getNode()->hasOneUse())
2906 unsigned Opc = N.getOpcode();
2907 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
2910 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2915 switch (N1C->getZExtValue()) {
2918 case 0xFF: Num = 0; break;
2919 case 0xFF00: Num = 1; break;
2920 case 0xFF0000: Num = 2; break;
2921 case 0xFF000000: Num = 3; break;
2924 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
2925 SDValue N0 = N.getOperand(0);
2926 if (Opc == ISD::AND) {
2927 if (Num == 0 || Num == 2) {
2929 // (x >> 8) & 0xff0000
2930 if (N0.getOpcode() != ISD::SRL)
2932 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2933 if (!C || C->getZExtValue() != 8)
2936 // (x << 8) & 0xff00
2937 // (x << 8) & 0xff000000
2938 if (N0.getOpcode() != ISD::SHL)
2940 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2941 if (!C || C->getZExtValue() != 8)
2944 } else if (Opc == ISD::SHL) {
2946 // (x & 0xff0000) << 8
2947 if (Num != 0 && Num != 2)
2949 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2950 if (!C || C->getZExtValue() != 8)
2952 } else { // Opc == ISD::SRL
2953 // (x & 0xff00) >> 8
2954 // (x & 0xff000000) >> 8
2955 if (Num != 1 && Num != 3)
2957 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2958 if (!C || C->getZExtValue() != 8)
2965 Parts[Num] = N0.getOperand(0).getNode();
2969 /// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is
2970 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2971 /// => (rotl (bswap x), 16)
2972 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
2973 if (!LegalOperations)
2976 EVT VT = N->getValueType(0);
2979 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2982 SmallVector<SDNode*,4> Parts(4, (SDNode*)0);
2984 // (or (or (and), (and)), (or (and), (and)))
2985 // (or (or (or (and), (and)), (and)), (and))
2986 if (N0.getOpcode() != ISD::OR)
2988 SDValue N00 = N0.getOperand(0);
2989 SDValue N01 = N0.getOperand(1);
2991 if (N1.getOpcode() == ISD::OR &&
2992 N00.getNumOperands() == 2 && N01.getNumOperands() == 2) {
2993 // (or (or (and), (and)), (or (and), (and)))
2994 SDValue N000 = N00.getOperand(0);
2995 if (!isBSwapHWordElement(N000, Parts))
2998 SDValue N001 = N00.getOperand(1);
2999 if (!isBSwapHWordElement(N001, Parts))
3001 SDValue N010 = N01.getOperand(0);
3002 if (!isBSwapHWordElement(N010, Parts))
3004 SDValue N011 = N01.getOperand(1);
3005 if (!isBSwapHWordElement(N011, Parts))
3008 // (or (or (or (and), (and)), (and)), (and))
3009 if (!isBSwapHWordElement(N1, Parts))
3011 if (!isBSwapHWordElement(N01, Parts))
3013 if (N00.getOpcode() != ISD::OR)
3015 SDValue N000 = N00.getOperand(0);
3016 if (!isBSwapHWordElement(N000, Parts))
3018 SDValue N001 = N00.getOperand(1);
3019 if (!isBSwapHWordElement(N001, Parts))
3023 // Make sure the parts are all coming from the same node.
3024 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
3027 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT,
3028 SDValue(Parts[0],0));
3030 // Result of the bswap should be rotated by 16. If it's not legal, than
3031 // do (x << 16) | (x >> 16).
3032 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT));
3033 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
3034 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt);
3035 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
3036 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt);
3037 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT,
3038 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt),
3039 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt));
3042 SDValue DAGCombiner::visitOR(SDNode *N) {
3043 SDValue N0 = N->getOperand(0);
3044 SDValue N1 = N->getOperand(1);
3045 SDValue LL, LR, RL, RR, CC0, CC1;
3046 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3047 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3048 EVT VT = N1.getValueType();
3051 if (VT.isVector()) {
3052 SDValue FoldedVOp = SimplifyVBinOp(N);
3053 if (FoldedVOp.getNode()) return FoldedVOp;
3055 // fold (or x, 0) -> x, vector edition
3056 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3058 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3061 // fold (or x, -1) -> -1, vector edition
3062 if (ISD::isBuildVectorAllOnes(N0.getNode()))
3064 if (ISD::isBuildVectorAllOnes(N1.getNode()))
3068 // fold (or x, undef) -> -1
3069 if (!LegalOperations &&
3070 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
3071 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
3072 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
3074 // fold (or c1, c2) -> c1|c2
3076 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
3077 // canonicalize constant to RHS
3079 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
3080 // fold (or x, 0) -> x
3081 if (N1C && N1C->isNullValue())
3083 // fold (or x, -1) -> -1
3084 if (N1C && N1C->isAllOnesValue())
3086 // fold (or x, c) -> c iff (x & ~c) == 0
3087 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
3090 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
3091 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
3092 if (BSwap.getNode() != 0)
3094 BSwap = MatchBSwapHWordLow(N, N0, N1);
3095 if (BSwap.getNode() != 0)
3099 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
3100 if (ROR.getNode() != 0)
3102 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
3103 // iff (c1 & c2) == 0.
3104 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3105 isa<ConstantSDNode>(N0.getOperand(1))) {
3106 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
3107 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
3108 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3109 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
3110 N0.getOperand(0), N1),
3111 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
3113 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
3114 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
3115 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
3116 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
3118 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
3119 LL.getValueType().isInteger()) {
3120 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
3121 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
3122 if (cast<ConstantSDNode>(LR)->isNullValue() &&
3123 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
3124 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
3125 LR.getValueType(), LL, RL);
3126 AddToWorkList(ORNode.getNode());
3127 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
3129 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
3130 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
3131 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
3132 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
3133 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
3134 LR.getValueType(), LL, RL);
3135 AddToWorkList(ANDNode.getNode());
3136 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
3139 // canonicalize equivalent to ll == rl
3140 if (LL == RR && LR == RL) {
3141 Op1 = ISD::getSetCCSwappedOperands(Op1);
3144 if (LL == RL && LR == RR) {
3145 bool isInteger = LL.getValueType().isInteger();
3146 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
3147 if (Result != ISD::SETCC_INVALID &&
3148 (!LegalOperations ||
3149 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
3150 TLI.isOperationLegal(ISD::SETCC,
3151 TLI.getSetCCResultType(N0.getValueType())))))
3152 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
3157 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
3158 if (N0.getOpcode() == N1.getOpcode()) {
3159 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3160 if (Tmp.getNode()) return Tmp;
3163 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
3164 if (N0.getOpcode() == ISD::AND &&
3165 N1.getOpcode() == ISD::AND &&
3166 N0.getOperand(1).getOpcode() == ISD::Constant &&
3167 N1.getOperand(1).getOpcode() == ISD::Constant &&
3168 // Don't increase # computations.
3169 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3170 // We can only do this xform if we know that bits from X that are set in C2
3171 // but not in C1 are already zero. Likewise for Y.
3172 const APInt &LHSMask =
3173 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3174 const APInt &RHSMask =
3175 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
3177 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
3178 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
3179 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
3180 N0.getOperand(0), N1.getOperand(0));
3181 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
3182 DAG.getConstant(LHSMask | RHSMask, VT));
3186 // See if this is some rotate idiom.
3187 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
3188 return SDValue(Rot, 0);
3190 // Simplify the operands using demanded-bits information.
3191 if (!VT.isVector() &&
3192 SimplifyDemandedBits(SDValue(N, 0)))
3193 return SDValue(N, 0);
3198 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
3199 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
3200 if (Op.getOpcode() == ISD::AND) {
3201 if (isa<ConstantSDNode>(Op.getOperand(1))) {
3202 Mask = Op.getOperand(1);
3203 Op = Op.getOperand(0);
3209 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3217 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
3218 // idioms for rotate, and if the target supports rotation instructions, generate
3220 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
3221 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
3222 EVT VT = LHS.getValueType();
3223 if (!TLI.isTypeLegal(VT)) return 0;
3225 // The target must have at least one rotate flavor.
3226 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
3227 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
3228 if (!HasROTL && !HasROTR) return 0;
3230 // Match "(X shl/srl V1) & V2" where V2 may not be present.
3231 SDValue LHSShift; // The shift.
3232 SDValue LHSMask; // AND value if any.
3233 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
3234 return 0; // Not part of a rotate.
3236 SDValue RHSShift; // The shift.
3237 SDValue RHSMask; // AND value if any.
3238 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
3239 return 0; // Not part of a rotate.
3241 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
3242 return 0; // Not shifting the same value.
3244 if (LHSShift.getOpcode() == RHSShift.getOpcode())
3245 return 0; // Shifts must disagree.
3247 // Canonicalize shl to left side in a shl/srl pair.
3248 if (RHSShift.getOpcode() == ISD::SHL) {
3249 std::swap(LHS, RHS);
3250 std::swap(LHSShift, RHSShift);
3251 std::swap(LHSMask , RHSMask );
3254 unsigned OpSizeInBits = VT.getSizeInBits();
3255 SDValue LHSShiftArg = LHSShift.getOperand(0);
3256 SDValue LHSShiftAmt = LHSShift.getOperand(1);
3257 SDValue RHSShiftAmt = RHSShift.getOperand(1);
3259 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
3260 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
3261 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
3262 RHSShiftAmt.getOpcode() == ISD::Constant) {
3263 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
3264 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
3265 if ((LShVal + RShVal) != OpSizeInBits)
3268 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3269 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt);
3271 // If there is an AND of either shifted operand, apply it to the result.
3272 if (LHSMask.getNode() || RHSMask.getNode()) {
3273 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
3275 if (LHSMask.getNode()) {
3276 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
3277 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
3279 if (RHSMask.getNode()) {
3280 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
3281 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
3284 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
3287 return Rot.getNode();
3290 // If there is a mask here, and we have a variable shift, we can't be sure
3291 // that we're masking out the right stuff.
3292 if (LHSMask.getNode() || RHSMask.getNode())
3295 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
3296 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
3297 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
3298 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
3299 if (ConstantSDNode *SUBC =
3300 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
3301 if (SUBC->getAPIntValue() == OpSizeInBits) {
3302 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg,
3303 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
3308 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
3309 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
3310 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
3311 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
3312 if (ConstantSDNode *SUBC =
3313 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
3314 if (SUBC->getAPIntValue() == OpSizeInBits) {
3315 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, LHSShiftArg,
3316 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
3321 // Look for sign/zext/any-extended or truncate cases:
3322 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3323 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3324 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3325 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3326 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3327 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3328 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3329 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3330 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
3331 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
3332 if (RExtOp0.getOpcode() == ISD::SUB &&
3333 RExtOp0.getOperand(1) == LExtOp0) {
3334 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3336 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3337 // (rotr x, (sub 32, y))
3338 if (ConstantSDNode *SUBC =
3339 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
3340 if (SUBC->getAPIntValue() == OpSizeInBits) {
3341 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3343 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
3346 } else if (LExtOp0.getOpcode() == ISD::SUB &&
3347 RExtOp0 == LExtOp0.getOperand(1)) {
3348 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3350 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3351 // (rotl x, (sub 32, y))
3352 if (ConstantSDNode *SUBC =
3353 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
3354 if (SUBC->getAPIntValue() == OpSizeInBits) {
3355 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
3357 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
3366 SDValue DAGCombiner::visitXOR(SDNode *N) {
3367 SDValue N0 = N->getOperand(0);
3368 SDValue N1 = N->getOperand(1);
3369 SDValue LHS, RHS, CC;
3370 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3371 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3372 EVT VT = N0.getValueType();
3375 if (VT.isVector()) {
3376 SDValue FoldedVOp = SimplifyVBinOp(N);
3377 if (FoldedVOp.getNode()) return FoldedVOp;
3379 // fold (xor x, 0) -> x, vector edition
3380 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3382 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3386 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3387 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3388 return DAG.getConstant(0, VT);
3389 // fold (xor x, undef) -> undef
3390 if (N0.getOpcode() == ISD::UNDEF)
3392 if (N1.getOpcode() == ISD::UNDEF)
3394 // fold (xor c1, c2) -> c1^c2
3396 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3397 // canonicalize constant to RHS
3399 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
3400 // fold (xor x, 0) -> x
3401 if (N1C && N1C->isNullValue())
3404 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
3405 if (RXOR.getNode() != 0)
3408 // fold !(x cc y) -> (x !cc y)
3409 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3410 bool isInt = LHS.getValueType().isInteger();
3411 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3414 if (!LegalOperations ||
3415 TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) {
3416 switch (N0.getOpcode()) {
3418 llvm_unreachable("Unhandled SetCC Equivalent!");
3420 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
3421 case ISD::SELECT_CC:
3422 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
3423 N0.getOperand(3), NotCC);
3428 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
3429 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3430 N0.getNode()->hasOneUse() &&
3431 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3432 SDValue V = N0.getOperand(0);
3433 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
3434 DAG.getConstant(1, V.getValueType()));
3435 AddToWorkList(V.getNode());
3436 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
3439 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
3440 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
3441 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3442 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3443 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
3444 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3445 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3446 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3447 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3448 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3451 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
3452 if (N1C && N1C->isAllOnesValue() &&
3453 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3454 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3455 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
3456 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3457 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3458 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3459 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3460 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3463 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
3464 if (N1C && N0.getOpcode() == ISD::XOR) {
3465 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3466 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3468 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
3469 DAG.getConstant(N1C->getAPIntValue() ^
3470 N00C->getAPIntValue(), VT));
3472 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
3473 DAG.getConstant(N1C->getAPIntValue() ^
3474 N01C->getAPIntValue(), VT));
3476 // fold (xor x, x) -> 0
3478 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
3480 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
3481 if (N0.getOpcode() == N1.getOpcode()) {
3482 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3483 if (Tmp.getNode()) return Tmp;
3486 // Simplify the expression using non-local knowledge.
3487 if (!VT.isVector() &&
3488 SimplifyDemandedBits(SDValue(N, 0)))
3489 return SDValue(N, 0);
3494 /// visitShiftByConstant - Handle transforms common to the three shifts, when
3495 /// the shift amount is a constant.
3496 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
3497 SDNode *LHS = N->getOperand(0).getNode();
3498 if (!LHS->hasOneUse()) return SDValue();
3500 // We want to pull some binops through shifts, so that we have (and (shift))
3501 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
3502 // thing happens with address calculations, so it's important to canonicalize
3504 bool HighBitSet = false; // Can we transform this if the high bit is set?
3506 switch (LHS->getOpcode()) {
3507 default: return SDValue();
3510 HighBitSet = false; // We can only transform sra if the high bit is clear.
3513 HighBitSet = true; // We can only transform sra if the high bit is set.
3516 if (N->getOpcode() != ISD::SHL)
3517 return SDValue(); // only shl(add) not sr[al](add).
3518 HighBitSet = false; // We can only transform sra if the high bit is clear.
3522 // We require the RHS of the binop to be a constant as well.
3523 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
3524 if (!BinOpCst) return SDValue();
3526 // FIXME: disable this unless the input to the binop is a shift by a constant.
3527 // If it is not a shift, it pessimizes some common cases like:
3529 // void foo(int *X, int i) { X[i & 1235] = 1; }
3530 // int bar(int *X, int i) { return X[i & 255]; }
3531 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
3532 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
3533 BinOpLHSVal->getOpcode() != ISD::SRA &&
3534 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3535 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
3538 EVT VT = N->getValueType(0);
3540 // If this is a signed shift right, and the high bit is modified by the
3541 // logical operation, do not perform the transformation. The highBitSet
3542 // boolean indicates the value of the high bit of the constant which would
3543 // cause it to be modified for this operation.
3544 if (N->getOpcode() == ISD::SRA) {
3545 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
3546 if (BinOpRHSSignSet != HighBitSet)
3550 // Fold the constants, shifting the binop RHS by the shift amount.
3551 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
3553 LHS->getOperand(1), N->getOperand(1));
3555 // Create the new shift.
3556 SDValue NewShift = DAG.getNode(N->getOpcode(),
3557 LHS->getOperand(0).getDebugLoc(),
3558 VT, LHS->getOperand(0), N->getOperand(1));
3560 // Create the new binop.
3561 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
3564 SDValue DAGCombiner::visitSHL(SDNode *N) {
3565 SDValue N0 = N->getOperand(0);
3566 SDValue N1 = N->getOperand(1);
3567 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3568 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3569 EVT VT = N0.getValueType();
3570 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3572 // fold (shl c1, c2) -> c1<<c2
3574 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
3575 // fold (shl 0, x) -> 0
3576 if (N0C && N0C->isNullValue())
3578 // fold (shl x, c >= size(x)) -> undef
3579 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3580 return DAG.getUNDEF(VT);
3581 // fold (shl x, 0) -> x
3582 if (N1C && N1C->isNullValue())
3584 // fold (shl undef, x) -> 0
3585 if (N0.getOpcode() == ISD::UNDEF)
3586 return DAG.getConstant(0, VT);
3587 // if (shl x, c) is known to be zero, return 0
3588 if (DAG.MaskedValueIsZero(SDValue(N, 0),
3589 APInt::getAllOnesValue(OpSizeInBits)))
3590 return DAG.getConstant(0, VT);
3591 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
3592 if (N1.getOpcode() == ISD::TRUNCATE &&
3593 N1.getOperand(0).getOpcode() == ISD::AND &&
3594 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3595 SDValue N101 = N1.getOperand(0).getOperand(1);
3596 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3597 EVT TruncVT = N1.getValueType();
3598 SDValue N100 = N1.getOperand(0).getOperand(0);
3599 APInt TruncC = N101C->getAPIntValue();
3600 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3601 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
3602 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
3603 DAG.getNode(ISD::TRUNCATE,
3606 DAG.getConstant(TruncC, TruncVT)));
3610 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3611 return SDValue(N, 0);
3613 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
3614 if (N1C && N0.getOpcode() == ISD::SHL &&
3615 N0.getOperand(1).getOpcode() == ISD::Constant) {
3616 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3617 uint64_t c2 = N1C->getZExtValue();
3618 if (c1 + c2 >= OpSizeInBits)
3619 return DAG.getConstant(0, VT);
3620 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3621 DAG.getConstant(c1 + c2, N1.getValueType()));
3624 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
3625 // For this to be valid, the second form must not preserve any of the bits
3626 // that are shifted out by the inner shift in the first form. This means
3627 // the outer shift size must be >= the number of bits added by the ext.
3628 // As a corollary, we don't care what kind of ext it is.
3629 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
3630 N0.getOpcode() == ISD::ANY_EXTEND ||
3631 N0.getOpcode() == ISD::SIGN_EXTEND) &&
3632 N0.getOperand(0).getOpcode() == ISD::SHL &&
3633 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3635 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3636 uint64_t c2 = N1C->getZExtValue();
3637 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3638 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3639 if (c2 >= OpSizeInBits - InnerShiftSize) {
3640 if (c1 + c2 >= OpSizeInBits)
3641 return DAG.getConstant(0, VT);
3642 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT,
3643 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT,
3644 N0.getOperand(0)->getOperand(0)),
3645 DAG.getConstant(c1 + c2, N1.getValueType()));
3649 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
3650 // (and (srl x, (sub c1, c2), MASK)
3651 // Only fold this if the inner shift has no other uses -- if it does, folding
3652 // this will increase the total number of instructions.
3653 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() &&
3654 N0.getOperand(1).getOpcode() == ISD::Constant) {
3655 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3656 if (c1 < VT.getSizeInBits()) {
3657 uint64_t c2 = N1C->getZExtValue();
3658 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
3659 VT.getSizeInBits() - c1);
3662 Mask = Mask.shl(c2-c1);
3663 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3664 DAG.getConstant(c2-c1, N1.getValueType()));
3666 Mask = Mask.lshr(c1-c2);
3667 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3668 DAG.getConstant(c1-c2, N1.getValueType()));
3670 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift,
3671 DAG.getConstant(Mask, VT));
3674 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
3675 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
3676 SDValue HiBitsMask =
3677 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
3678 VT.getSizeInBits() -
3679 N1C->getZExtValue()),
3681 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3686 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
3687 if (NewSHL.getNode())
3694 SDValue DAGCombiner::visitSRA(SDNode *N) {
3695 SDValue N0 = N->getOperand(0);
3696 SDValue N1 = N->getOperand(1);
3697 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3698 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3699 EVT VT = N0.getValueType();
3700 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3702 // fold (sra c1, c2) -> (sra c1, c2)
3704 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
3705 // fold (sra 0, x) -> 0
3706 if (N0C && N0C->isNullValue())
3708 // fold (sra -1, x) -> -1
3709 if (N0C && N0C->isAllOnesValue())
3711 // fold (sra x, (setge c, size(x))) -> undef
3712 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3713 return DAG.getUNDEF(VT);
3714 // fold (sra x, 0) -> x
3715 if (N1C && N1C->isNullValue())
3717 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
3719 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
3720 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
3721 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
3723 ExtVT = EVT::getVectorVT(*DAG.getContext(),
3724 ExtVT, VT.getVectorNumElements());
3725 if ((!LegalOperations ||
3726 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
3727 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3728 N0.getOperand(0), DAG.getValueType(ExtVT));
3731 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
3732 if (N1C && N0.getOpcode() == ISD::SRA) {
3733 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3734 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
3735 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
3736 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
3737 DAG.getConstant(Sum, N1C->getValueType(0)));
3741 // fold (sra (shl X, m), (sub result_size, n))
3742 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
3743 // result_size - n != m.
3744 // If truncate is free for the target sext(shl) is likely to result in better
3746 if (N0.getOpcode() == ISD::SHL) {
3747 // Get the two constanst of the shifts, CN0 = m, CN = n.
3748 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3750 // Determine what the truncate's result bitsize and type would be.
3752 EVT::getIntegerVT(*DAG.getContext(),
3753 OpSizeInBits - N1C->getZExtValue());
3754 // Determine the residual right-shift amount.
3755 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
3757 // If the shift is not a no-op (in which case this should be just a sign
3758 // extend already), the truncated to type is legal, sign_extend is legal
3759 // on that type, and the truncate to that type is both legal and free,
3760 // perform the transform.
3761 if ((ShiftAmt > 0) &&
3762 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
3763 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
3764 TLI.isTruncateFree(VT, TruncVT)) {
3766 SDValue Amt = DAG.getConstant(ShiftAmt,
3767 getShiftAmountTy(N0.getOperand(0).getValueType()));
3768 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3769 N0.getOperand(0), Amt);
3770 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
3772 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
3773 N->getValueType(0), Trunc);
3778 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
3779 if (N1.getOpcode() == ISD::TRUNCATE &&
3780 N1.getOperand(0).getOpcode() == ISD::AND &&
3781 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3782 SDValue N101 = N1.getOperand(0).getOperand(1);
3783 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3784 EVT TruncVT = N1.getValueType();
3785 SDValue N100 = N1.getOperand(0).getOperand(0);
3786 APInt TruncC = N101C->getAPIntValue();
3787 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
3788 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
3789 DAG.getNode(ISD::AND, N->getDebugLoc(),
3791 DAG.getNode(ISD::TRUNCATE,
3794 DAG.getConstant(TruncC, TruncVT)));
3798 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2))
3799 // if c1 is equal to the number of bits the trunc removes
3800 if (N0.getOpcode() == ISD::TRUNCATE &&
3801 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3802 N0.getOperand(0).getOpcode() == ISD::SRA) &&
3803 N0.getOperand(0).hasOneUse() &&
3804 N0.getOperand(0).getOperand(1).hasOneUse() &&
3805 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) {
3806 EVT LargeVT = N0.getOperand(0).getValueType();
3807 ConstantSDNode *LargeShiftAmt =
3808 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1));
3810 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits ==
3811 LargeShiftAmt->getZExtValue()) {
3813 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(),
3814 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType()));
3815 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT,
3816 N0.getOperand(0).getOperand(0), Amt);
3817 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA);
3821 // Simplify, based on bits shifted out of the LHS.
3822 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3823 return SDValue(N, 0);
3826 // If the sign bit is known to be zero, switch this to a SRL.
3827 if (DAG.SignBitIsZero(N0))
3828 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3831 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
3832 if (NewSRA.getNode())
3839 SDValue DAGCombiner::visitSRL(SDNode *N) {
3840 SDValue N0 = N->getOperand(0);
3841 SDValue N1 = N->getOperand(1);
3842 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3843 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3844 EVT VT = N0.getValueType();
3845 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3847 // fold (srl c1, c2) -> c1 >>u c2
3849 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3850 // fold (srl 0, x) -> 0
3851 if (N0C && N0C->isNullValue())
3853 // fold (srl x, c >= size(x)) -> undef
3854 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3855 return DAG.getUNDEF(VT);
3856 // fold (srl x, 0) -> x
3857 if (N1C && N1C->isNullValue())
3859 // if (srl x, c) is known to be zero, return 0
3860 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3861 APInt::getAllOnesValue(OpSizeInBits)))
3862 return DAG.getConstant(0, VT);
3864 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3865 if (N1C && N0.getOpcode() == ISD::SRL &&
3866 N0.getOperand(1).getOpcode() == ISD::Constant) {
3867 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3868 uint64_t c2 = N1C->getZExtValue();
3869 if (c1 + c2 >= OpSizeInBits)
3870 return DAG.getConstant(0, VT);
3871 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3872 DAG.getConstant(c1 + c2, N1.getValueType()));
3875 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
3876 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
3877 N0.getOperand(0).getOpcode() == ISD::SRL &&
3878 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3880 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3881 uint64_t c2 = N1C->getZExtValue();
3882 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3883 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
3884 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3885 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
3886 if (c1 + OpSizeInBits == InnerShiftSize) {
3887 if (c1 + c2 >= InnerShiftSize)
3888 return DAG.getConstant(0, VT);
3889 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT,
3890 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
3891 N0.getOperand(0)->getOperand(0),
3892 DAG.getConstant(c1 + c2, ShiftCountVT)));
3896 // fold (srl (shl x, c), c) -> (and x, cst2)
3897 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3898 N0.getValueSizeInBits() <= 64) {
3899 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3900 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3901 DAG.getConstant(~0ULL >> ShAmt, VT));
3905 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3906 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3907 // Shifting in all undef bits?
3908 EVT SmallVT = N0.getOperand(0).getValueType();
3909 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
3910 return DAG.getUNDEF(VT);
3912 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3913 uint64_t ShiftAmt = N1C->getZExtValue();
3914 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3916 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));
3917 AddToWorkList(SmallShift.getNode());
3918 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
3922 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
3923 // bit, which is unmodified by sra.
3924 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
3925 if (N0.getOpcode() == ISD::SRA)
3926 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3929 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3930 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3931 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
3932 APInt KnownZero, KnownOne;
3933 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne);
3935 // If any of the input bits are KnownOne, then the input couldn't be all
3936 // zeros, thus the result of the srl will always be zero.
3937 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
3939 // If all of the bits input the to ctlz node are known to be zero, then
3940 // the result of the ctlz is "32" and the result of the shift is one.
3941 APInt UnknownBits = ~KnownZero;
3942 if (UnknownBits == 0) return DAG.getConstant(1, VT);
3944 // Otherwise, check to see if there is exactly one bit input to the ctlz.
3945 if ((UnknownBits & (UnknownBits - 1)) == 0) {
3946 // Okay, we know that only that the single bit specified by UnknownBits
3947 // could be set on input to the CTLZ node. If this bit is set, the SRL
3948 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3949 // to an SRL/XOR pair, which is likely to simplify more.
3950 unsigned ShAmt = UnknownBits.countTrailingZeros();
3951 SDValue Op = N0.getOperand(0);
3954 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3955 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType())));
3956 AddToWorkList(Op.getNode());
3959 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3960 Op, DAG.getConstant(1, VT));
3964 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3965 if (N1.getOpcode() == ISD::TRUNCATE &&
3966 N1.getOperand(0).getOpcode() == ISD::AND &&
3967 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3968 SDValue N101 = N1.getOperand(0).getOperand(1);
3969 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3970 EVT TruncVT = N1.getValueType();
3971 SDValue N100 = N1.getOperand(0).getOperand(0);
3972 APInt TruncC = N101C->getAPIntValue();
3973 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3974 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3975 DAG.getNode(ISD::AND, N->getDebugLoc(),
3977 DAG.getNode(ISD::TRUNCATE,
3980 DAG.getConstant(TruncC, TruncVT)));
3984 // fold operands of srl based on knowledge that the low bits are not
3986 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3987 return SDValue(N, 0);
3990 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
3991 if (NewSRL.getNode())
3995 // Attempt to convert a srl of a load into a narrower zero-extending load.
3996 SDValue NarrowLoad = ReduceLoadWidth(N);
3997 if (NarrowLoad.getNode())
4000 // Here is a common situation. We want to optimize:
4003 // %b = and i32 %a, 2
4004 // %c = srl i32 %b, 1
4005 // brcond i32 %c ...
4011 // %c = setcc eq %b, 0
4014 // However when after the source operand of SRL is optimized into AND, the SRL
4015 // itself may not be optimized further. Look for it and add the BRCOND into
4017 if (N->hasOneUse()) {
4018 SDNode *Use = *N->use_begin();
4019 if (Use->getOpcode() == ISD::BRCOND)
4021 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
4022 // Also look pass the truncate.
4023 Use = *Use->use_begin();
4024 if (Use->getOpcode() == ISD::BRCOND)
4032 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
4033 SDValue N0 = N->getOperand(0);
4034 EVT VT = N->getValueType(0);
4036 // fold (ctlz c1) -> c2
4037 if (isa<ConstantSDNode>(N0))
4038 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
4042 SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) {
4043 SDValue N0 = N->getOperand(0);
4044 EVT VT = N->getValueType(0);
4046 // fold (ctlz_zero_undef c1) -> c2
4047 if (isa<ConstantSDNode>(N0))
4048 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0);
4052 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
4053 SDValue N0 = N->getOperand(0);
4054 EVT VT = N->getValueType(0);
4056 // fold (cttz c1) -> c2
4057 if (isa<ConstantSDNode>(N0))
4058 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
4062 SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) {
4063 SDValue N0 = N->getOperand(0);
4064 EVT VT = N->getValueType(0);
4066 // fold (cttz_zero_undef c1) -> c2
4067 if (isa<ConstantSDNode>(N0))
4068 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0);
4072 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
4073 SDValue N0 = N->getOperand(0);
4074 EVT VT = N->getValueType(0);
4076 // fold (ctpop c1) -> c2
4077 if (isa<ConstantSDNode>(N0))
4078 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
4082 SDValue DAGCombiner::visitSELECT(SDNode *N) {
4083 SDValue N0 = N->getOperand(0);
4084 SDValue N1 = N->getOperand(1);
4085 SDValue N2 = N->getOperand(2);
4086 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4087 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4088 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
4089 EVT VT = N->getValueType(0);
4090 EVT VT0 = N0.getValueType();
4092 // fold (select C, X, X) -> X
4095 // fold (select true, X, Y) -> X
4096 if (N0C && !N0C->isNullValue())
4098 // fold (select false, X, Y) -> Y
4099 if (N0C && N0C->isNullValue())
4101 // fold (select C, 1, X) -> (or C, X)
4102 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
4103 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
4104 // fold (select C, 0, 1) -> (xor C, 1)
4105 if (VT.isInteger() &&
4108 TLI.getBooleanContents(false) ==
4109 TargetLowering::ZeroOrOneBooleanContent)) &&
4110 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
4113 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
4114 N0, DAG.getConstant(1, VT0));
4115 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
4116 N0, DAG.getConstant(1, VT0));
4117 AddToWorkList(XORNode.getNode());
4119 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
4120 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
4122 // fold (select C, 0, X) -> (and (not C), X)
4123 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
4124 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
4125 AddToWorkList(NOTNode.getNode());
4126 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
4128 // fold (select C, X, 1) -> (or (not C), X)
4129 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
4130 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
4131 AddToWorkList(NOTNode.getNode());
4132 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
4134 // fold (select C, X, 0) -> (and C, X)
4135 if (VT == MVT::i1 && N2C && N2C->isNullValue())
4136 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
4137 // fold (select X, X, Y) -> (or X, Y)
4138 // fold (select X, 1, Y) -> (or X, Y)
4139 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
4140 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
4141 // fold (select X, Y, X) -> (and X, Y)
4142 // fold (select X, Y, 0) -> (and X, Y)
4143 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
4144 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
4146 // If we can fold this based on the true/false value, do so.
4147 if (SimplifySelectOps(N, N1, N2))
4148 return SDValue(N, 0); // Don't revisit N.
4150 // fold selects based on a setcc into other things, such as min/max/abs
4151 if (N0.getOpcode() == ISD::SETCC) {
4153 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
4154 // having to say they don't support SELECT_CC on every type the DAG knows
4155 // about, since there is no way to mark an opcode illegal at all value types
4156 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
4157 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
4158 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
4159 N0.getOperand(0), N0.getOperand(1),
4160 N1, N2, N0.getOperand(2));
4161 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
4167 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
4168 SDValue N0 = N->getOperand(0);
4169 SDValue N1 = N->getOperand(1);
4170 SDValue N2 = N->getOperand(2);
4171 SDValue N3 = N->getOperand(3);
4172 SDValue N4 = N->getOperand(4);
4173 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
4175 // fold select_cc lhs, rhs, x, x, cc -> x
4179 // Determine if the condition we're dealing with is constant
4180 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
4181 N0, N1, CC, N->getDebugLoc(), false);
4182 if (SCC.getNode()) AddToWorkList(SCC.getNode());
4184 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
4185 if (!SCCC->isNullValue())
4186 return N2; // cond always true -> true val
4188 return N3; // cond always false -> false val
4191 // Fold to a simpler select_cc
4192 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
4193 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
4194 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
4197 // If we can fold this based on the true/false value, do so.
4198 if (SimplifySelectOps(N, N2, N3))
4199 return SDValue(N, 0); // Don't revisit N.
4201 // fold select_cc into other things, such as min/max/abs
4202 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
4205 SDValue DAGCombiner::visitSETCC(SDNode *N) {
4206 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
4207 cast<CondCodeSDNode>(N->getOperand(2))->get(),
4211 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
4212 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
4213 // transformation. Returns true if extension are possible and the above
4214 // mentioned transformation is profitable.
4215 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
4217 SmallVector<SDNode*, 4> &ExtendNodes,
4218 const TargetLowering &TLI) {
4219 bool HasCopyToRegUses = false;
4220 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
4221 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
4222 UE = N0.getNode()->use_end();
4227 if (UI.getUse().getResNo() != N0.getResNo())
4229 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
4230 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
4231 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
4232 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
4233 // Sign bits will be lost after a zext.
4236 for (unsigned i = 0; i != 2; ++i) {
4237 SDValue UseOp = User->getOperand(i);
4240 if (!isa<ConstantSDNode>(UseOp))
4245 ExtendNodes.push_back(User);
4248 // If truncates aren't free and there are users we can't
4249 // extend, it isn't worthwhile.
4252 // Remember if this value is live-out.
4253 if (User->getOpcode() == ISD::CopyToReg)
4254 HasCopyToRegUses = true;
4257 if (HasCopyToRegUses) {
4258 bool BothLiveOut = false;
4259 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
4261 SDUse &Use = UI.getUse();
4262 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
4268 // Both unextended and extended values are live out. There had better be
4269 // a good reason for the transformation.
4270 return ExtendNodes.size();
4275 void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
4276 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
4277 ISD::NodeType ExtType) {
4278 // Extend SetCC uses if necessary.
4279 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
4280 SDNode *SetCC = SetCCs[i];
4281 SmallVector<SDValue, 4> Ops;
4283 for (unsigned j = 0; j != 2; ++j) {
4284 SDValue SOp = SetCC->getOperand(j);
4286 Ops.push_back(ExtLoad);
4288 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
4291 Ops.push_back(SetCC->getOperand(2));
4292 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0),
4293 &Ops[0], Ops.size()));
4297 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
4298 SDValue N0 = N->getOperand(0);
4299 EVT VT = N->getValueType(0);
4301 // fold (sext c1) -> c1
4302 if (isa<ConstantSDNode>(N0))
4303 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
4305 // fold (sext (sext x)) -> (sext x)
4306 // fold (sext (aext x)) -> (sext x)
4307 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4308 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
4311 if (N0.getOpcode() == ISD::TRUNCATE) {
4312 // fold (sext (truncate (load x))) -> (sext (smaller load x))
4313 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
4314 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4315 if (NarrowLoad.getNode()) {
4316 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4317 if (NarrowLoad.getNode() != N0.getNode()) {
4318 CombineTo(N0.getNode(), NarrowLoad);
4319 // CombineTo deleted the truncate, if needed, but not what's under it.
4322 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4325 // See if the value being truncated is already sign extended. If so, just
4326 // eliminate the trunc/sext pair.
4327 SDValue Op = N0.getOperand(0);
4328 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
4329 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
4330 unsigned DestBits = VT.getScalarType().getSizeInBits();
4331 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
4333 if (OpBits == DestBits) {
4334 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
4335 // bits, it is already ready.
4336 if (NumSignBits > DestBits-MidBits)
4338 } else if (OpBits < DestBits) {
4339 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
4340 // bits, just sext from i32.
4341 if (NumSignBits > OpBits-MidBits)
4342 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
4344 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
4345 // bits, just truncate to i32.
4346 if (NumSignBits > OpBits-MidBits)
4347 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4350 // fold (sext (truncate x)) -> (sextinreg x).
4351 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
4352 N0.getValueType())) {
4353 if (OpBits < DestBits)
4354 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
4355 else if (OpBits > DestBits)
4356 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
4357 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
4358 DAG.getValueType(N0.getValueType()));
4362 // fold (sext (load x)) -> (sext (truncate (sextload x)))
4363 // None of the supported targets knows how to perform load and sign extend
4364 // on vectors in one instruction. We only perform this transformation on
4366 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4367 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4368 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
4369 bool DoXform = true;
4370 SmallVector<SDNode*, 4> SetCCs;
4371 if (!N0.hasOneUse())
4372 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
4374 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4375 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4377 LN0->getBasePtr(), LN0->getPointerInfo(),
4379 LN0->isVolatile(), LN0->isNonTemporal(),
4380 LN0->getAlignment());
4381 CombineTo(N, ExtLoad);
4382 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4383 N0.getValueType(), ExtLoad);
4384 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4385 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4387 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4391 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
4392 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
4393 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4394 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4395 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4396 EVT MemVT = LN0->getMemoryVT();
4397 if ((!LegalOperations && !LN0->isVolatile()) ||
4398 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
4399 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4401 LN0->getBasePtr(), LN0->getPointerInfo(),
4403 LN0->isVolatile(), LN0->isNonTemporal(),
4404 LN0->getAlignment());
4405 CombineTo(N, ExtLoad);
4406 CombineTo(N0.getNode(),
4407 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4408 N0.getValueType(), ExtLoad),
4409 ExtLoad.getValue(1));
4410 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4414 // fold (sext (and/or/xor (load x), cst)) ->
4415 // (and/or/xor (sextload x), (sext cst))
4416 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4417 N0.getOpcode() == ISD::XOR) &&
4418 isa<LoadSDNode>(N0.getOperand(0)) &&
4419 N0.getOperand(1).getOpcode() == ISD::Constant &&
4420 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
4421 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4422 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4423 if (LN0->getExtensionType() != ISD::ZEXTLOAD) {
4424 bool DoXform = true;
4425 SmallVector<SDNode*, 4> SetCCs;
4426 if (!N0.hasOneUse())
4427 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
4430 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT,
4431 LN0->getChain(), LN0->getBasePtr(),
4432 LN0->getPointerInfo(),
4435 LN0->isNonTemporal(),
4436 LN0->getAlignment());
4437 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4438 Mask = Mask.sext(VT.getSizeInBits());
4439 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4440 ExtLoad, DAG.getConstant(Mask, VT));
4441 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4442 N0.getOperand(0).getDebugLoc(),
4443 N0.getOperand(0).getValueType(), ExtLoad);
4445 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4446 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4448 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4453 if (N0.getOpcode() == ISD::SETCC) {
4454 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
4455 // Only do this before legalize for now.
4456 if (VT.isVector() && !LegalOperations) {
4457 EVT N0VT = N0.getOperand(0).getValueType();
4458 // On some architectures (such as SSE/NEON/etc) the SETCC result type is
4459 // of the same size as the compared operands. Only optimize sext(setcc())
4460 // if this is the case.
4461 EVT SVT = TLI.getSetCCResultType(N0VT);
4463 // We know that the # elements of the results is the same as the
4464 // # elements of the compare (and the # elements of the compare result
4465 // for that matter). Check to see that they are the same size. If so,
4466 // we know that the element size of the sext'd result matches the
4467 // element size of the compare operands.
4468 if (VT.getSizeInBits() == SVT.getSizeInBits())
4469 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4471 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4472 // If the desired elements are smaller or larger than the source
4473 // elements we can use a matching integer vector type and then
4474 // truncate/sign extend
4475 EVT MatchingElementType =
4476 EVT::getIntegerVT(*DAG.getContext(),
4477 N0VT.getScalarType().getSizeInBits());
4478 EVT MatchingVectorType =
4479 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4480 N0VT.getVectorNumElements());
4482 if (SVT == MatchingVectorType) {
4483 SDValue VsetCC = DAG.getSetCC(N->getDebugLoc(), MatchingVectorType,
4484 N0.getOperand(0), N0.getOperand(1),
4485 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4486 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4490 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
4491 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
4493 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
4495 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4496 NegOne, DAG.getConstant(0, VT),
4497 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4498 if (SCC.getNode()) return SCC;
4499 if (!LegalOperations ||
4500 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
4501 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4502 DAG.getSetCC(N->getDebugLoc(),
4503 TLI.getSetCCResultType(VT),
4504 N0.getOperand(0), N0.getOperand(1),
4505 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4506 NegOne, DAG.getConstant(0, VT));
4509 // fold (sext x) -> (zext x) if the sign bit is known zero.
4510 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
4511 DAG.SignBitIsZero(N0))
4512 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4517 // isTruncateOf - If N is a truncate of some other value, return true, record
4518 // the value being truncated in Op and which of Op's bits are zero in KnownZero.
4519 // This function computes KnownZero to avoid a duplicated call to
4520 // ComputeMaskedBits in the caller.
4521 static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
4524 if (N->getOpcode() == ISD::TRUNCATE) {
4525 Op = N->getOperand(0);
4526 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne);
4530 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 ||
4531 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE)
4534 SDValue Op0 = N->getOperand(0);
4535 SDValue Op1 = N->getOperand(1);
4536 assert(Op0.getValueType() == Op1.getValueType());
4538 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0);
4539 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1);
4540 if (COp0 && COp0->isNullValue())
4542 else if (COp1 && COp1->isNullValue())
4547 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne);
4549 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue())
4555 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
4556 SDValue N0 = N->getOperand(0);
4557 EVT VT = N->getValueType(0);
4559 // fold (zext c1) -> c1
4560 if (isa<ConstantSDNode>(N0))
4561 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4562 // fold (zext (zext x)) -> (zext x)
4563 // fold (zext (aext x)) -> (zext x)
4564 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4565 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
4568 // fold (zext (truncate x)) -> (zext x) or
4569 // (zext (truncate x)) -> (truncate x)
4570 // This is valid when the truncated bits of x are already zero.
4571 // FIXME: We should extend this to work for vectors too.
4574 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) {
4575 APInt TruncatedBits =
4576 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ?
4577 APInt(Op.getValueSizeInBits(), 0) :
4578 APInt::getBitsSet(Op.getValueSizeInBits(),
4579 N0.getValueSizeInBits(),
4580 std::min(Op.getValueSizeInBits(),
4581 VT.getSizeInBits()));
4582 if (TruncatedBits == (KnownZero & TruncatedBits)) {
4583 if (VT.bitsGT(Op.getValueType()))
4584 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op);
4585 if (VT.bitsLT(Op.getValueType()))
4586 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4592 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4593 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
4594 if (N0.getOpcode() == ISD::TRUNCATE) {
4595 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4596 if (NarrowLoad.getNode()) {
4597 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4598 if (NarrowLoad.getNode() != N0.getNode()) {
4599 CombineTo(N0.getNode(), NarrowLoad);
4600 // CombineTo deleted the truncate, if needed, but not what's under it.
4603 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4607 // fold (zext (truncate x)) -> (and x, mask)
4608 if (N0.getOpcode() == ISD::TRUNCATE &&
4609 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
4611 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4612 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
4613 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4614 if (NarrowLoad.getNode()) {
4615 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4616 if (NarrowLoad.getNode() != N0.getNode()) {
4617 CombineTo(N0.getNode(), NarrowLoad);
4618 // CombineTo deleted the truncate, if needed, but not what's under it.
4621 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4624 SDValue Op = N0.getOperand(0);
4625 if (Op.getValueType().bitsLT(VT)) {
4626 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
4627 AddToWorkList(Op.getNode());
4628 } else if (Op.getValueType().bitsGT(VT)) {
4629 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4630 AddToWorkList(Op.getNode());
4632 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
4633 N0.getValueType().getScalarType());
4636 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
4637 // if either of the casts is not free.
4638 if (N0.getOpcode() == ISD::AND &&
4639 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4640 N0.getOperand(1).getOpcode() == ISD::Constant &&
4641 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4642 N0.getValueType()) ||
4643 !TLI.isZExtFree(N0.getValueType(), VT))) {
4644 SDValue X = N0.getOperand(0).getOperand(0);
4645 if (X.getValueType().bitsLT(VT)) {
4646 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
4647 } else if (X.getValueType().bitsGT(VT)) {
4648 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4650 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4651 Mask = Mask.zext(VT.getSizeInBits());
4652 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4653 X, DAG.getConstant(Mask, VT));
4656 // fold (zext (load x)) -> (zext (truncate (zextload x)))
4657 // None of the supported targets knows how to perform load and vector_zext
4658 // on vectors in one instruction. We only perform this transformation on
4660 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4661 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4662 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
4663 bool DoXform = true;
4664 SmallVector<SDNode*, 4> SetCCs;
4665 if (!N0.hasOneUse())
4666 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
4668 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4669 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4671 LN0->getBasePtr(), LN0->getPointerInfo(),
4673 LN0->isVolatile(), LN0->isNonTemporal(),
4674 LN0->getAlignment());
4675 CombineTo(N, ExtLoad);
4676 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4677 N0.getValueType(), ExtLoad);
4678 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4680 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4682 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4686 // fold (zext (and/or/xor (load x), cst)) ->
4687 // (and/or/xor (zextload x), (zext cst))
4688 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4689 N0.getOpcode() == ISD::XOR) &&
4690 isa<LoadSDNode>(N0.getOperand(0)) &&
4691 N0.getOperand(1).getOpcode() == ISD::Constant &&
4692 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
4693 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4694 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4695 if (LN0->getExtensionType() != ISD::SEXTLOAD) {
4696 bool DoXform = true;
4697 SmallVector<SDNode*, 4> SetCCs;
4698 if (!N0.hasOneUse())
4699 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
4702 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT,
4703 LN0->getChain(), LN0->getBasePtr(),
4704 LN0->getPointerInfo(),
4707 LN0->isNonTemporal(),
4708 LN0->getAlignment());
4709 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4710 Mask = Mask.zext(VT.getSizeInBits());
4711 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4712 ExtLoad, DAG.getConstant(Mask, VT));
4713 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4714 N0.getOperand(0).getDebugLoc(),
4715 N0.getOperand(0).getValueType(), ExtLoad);
4717 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4718 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4720 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4725 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
4726 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
4727 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4728 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4729 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4730 EVT MemVT = LN0->getMemoryVT();
4731 if ((!LegalOperations && !LN0->isVolatile()) ||
4732 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
4733 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4735 LN0->getBasePtr(), LN0->getPointerInfo(),
4737 LN0->isVolatile(), LN0->isNonTemporal(),
4738 LN0->getAlignment());
4739 CombineTo(N, ExtLoad);
4740 CombineTo(N0.getNode(),
4741 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
4743 ExtLoad.getValue(1));
4744 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4748 if (N0.getOpcode() == ISD::SETCC) {
4749 if (!LegalOperations && VT.isVector()) {
4750 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
4751 // Only do this before legalize for now.
4752 EVT N0VT = N0.getOperand(0).getValueType();
4753 EVT EltVT = VT.getVectorElementType();
4754 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
4755 DAG.getConstant(1, EltVT));
4756 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4757 // We know that the # elements of the results is the same as the
4758 // # elements of the compare (and the # elements of the compare result
4759 // for that matter). Check to see that they are the same size. If so,
4760 // we know that the element size of the sext'd result matches the
4761 // element size of the compare operands.
4762 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4763 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4765 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4766 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4767 &OneOps[0], OneOps.size()));
4769 // If the desired elements are smaller or larger than the source
4770 // elements we can use a matching integer vector type and then
4771 // truncate/sign extend
4772 EVT MatchingElementType =
4773 EVT::getIntegerVT(*DAG.getContext(),
4774 N0VT.getScalarType().getSizeInBits());
4775 EVT MatchingVectorType =
4776 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4777 N0VT.getVectorNumElements());
4779 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4781 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4782 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4783 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT),
4784 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4785 &OneOps[0], OneOps.size()));
4788 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4790 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4791 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4792 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4793 if (SCC.getNode()) return SCC;
4796 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
4797 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
4798 isa<ConstantSDNode>(N0.getOperand(1)) &&
4799 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
4801 SDValue ShAmt = N0.getOperand(1);
4802 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
4803 if (N0.getOpcode() == ISD::SHL) {
4804 SDValue InnerZExt = N0.getOperand(0);
4805 // If the original shl may be shifting out bits, do not perform this
4807 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
4808 InnerZExt.getOperand(0).getValueType().getSizeInBits();
4809 if (ShAmtVal > KnownZeroBits)
4813 DebugLoc DL = N->getDebugLoc();
4815 // Ensure that the shift amount is wide enough for the shifted value.
4816 if (VT.getSizeInBits() >= 256)
4817 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
4819 return DAG.getNode(N0.getOpcode(), DL, VT,
4820 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
4827 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
4828 SDValue N0 = N->getOperand(0);
4829 EVT VT = N->getValueType(0);
4831 // fold (aext c1) -> c1
4832 if (isa<ConstantSDNode>(N0))
4833 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
4834 // fold (aext (aext x)) -> (aext x)
4835 // fold (aext (zext x)) -> (zext x)
4836 // fold (aext (sext x)) -> (sext x)
4837 if (N0.getOpcode() == ISD::ANY_EXTEND ||
4838 N0.getOpcode() == ISD::ZERO_EXTEND ||
4839 N0.getOpcode() == ISD::SIGN_EXTEND)
4840 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
4842 // fold (aext (truncate (load x))) -> (aext (smaller load x))
4843 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
4844 if (N0.getOpcode() == ISD::TRUNCATE) {
4845 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4846 if (NarrowLoad.getNode()) {
4847 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4848 if (NarrowLoad.getNode() != N0.getNode()) {
4849 CombineTo(N0.getNode(), NarrowLoad);
4850 // CombineTo deleted the truncate, if needed, but not what's under it.
4853 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4857 // fold (aext (truncate x))
4858 if (N0.getOpcode() == ISD::TRUNCATE) {
4859 SDValue TruncOp = N0.getOperand(0);
4860 if (TruncOp.getValueType() == VT)
4861 return TruncOp; // x iff x size == zext size.
4862 if (TruncOp.getValueType().bitsGT(VT))
4863 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
4864 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
4867 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
4868 // if the trunc is not free.
4869 if (N0.getOpcode() == ISD::AND &&
4870 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4871 N0.getOperand(1).getOpcode() == ISD::Constant &&
4872 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4873 N0.getValueType())) {
4874 SDValue X = N0.getOperand(0).getOperand(0);
4875 if (X.getValueType().bitsLT(VT)) {
4876 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
4877 } else if (X.getValueType().bitsGT(VT)) {
4878 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
4880 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4881 Mask = Mask.zext(VT.getSizeInBits());
4882 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4883 X, DAG.getConstant(Mask, VT));
4886 // fold (aext (load x)) -> (aext (truncate (extload x)))
4887 // None of the supported targets knows how to perform load and any_ext
4888 // on vectors in one instruction. We only perform this transformation on
4890 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4891 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4892 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4893 bool DoXform = true;
4894 SmallVector<SDNode*, 4> SetCCs;
4895 if (!N0.hasOneUse())
4896 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
4898 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4899 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4901 LN0->getBasePtr(), LN0->getPointerInfo(),
4903 LN0->isVolatile(), LN0->isNonTemporal(),
4904 LN0->getAlignment());
4905 CombineTo(N, ExtLoad);
4906 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4907 N0.getValueType(), ExtLoad);
4908 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4909 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4911 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4915 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
4916 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
4917 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
4918 if (N0.getOpcode() == ISD::LOAD &&
4919 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4921 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4922 EVT MemVT = LN0->getMemoryVT();
4923 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
4924 VT, LN0->getChain(), LN0->getBasePtr(),
4925 LN0->getPointerInfo(), MemVT,
4926 LN0->isVolatile(), LN0->isNonTemporal(),
4927 LN0->getAlignment());
4928 CombineTo(N, ExtLoad);
4929 CombineTo(N0.getNode(),
4930 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4931 N0.getValueType(), ExtLoad),
4932 ExtLoad.getValue(1));
4933 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4936 if (N0.getOpcode() == ISD::SETCC) {
4937 // aext(setcc) -> sext_in_reg(vsetcc) for vectors.
4938 // Only do this before legalize for now.
4939 if (VT.isVector() && !LegalOperations) {
4940 EVT N0VT = N0.getOperand(0).getValueType();
4941 // We know that the # elements of the results is the same as the
4942 // # elements of the compare (and the # elements of the compare result
4943 // for that matter). Check to see that they are the same size. If so,
4944 // we know that the element size of the sext'd result matches the
4945 // element size of the compare operands.
4946 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4947 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4949 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4950 // If the desired elements are smaller or larger than the source
4951 // elements we can use a matching integer vector type and then
4952 // truncate/sign extend
4954 EVT MatchingElementType =
4955 EVT::getIntegerVT(*DAG.getContext(),
4956 N0VT.getScalarType().getSizeInBits());
4957 EVT MatchingVectorType =
4958 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4959 N0VT.getVectorNumElements());
4961 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4963 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4964 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4968 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4970 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4971 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4972 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4980 /// GetDemandedBits - See if the specified operand can be simplified with the
4981 /// knowledge that only the bits specified by Mask are used. If so, return the
4982 /// simpler operand, otherwise return a null SDValue.
4983 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
4984 switch (V.getOpcode()) {
4986 case ISD::Constant: {
4987 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode());
4988 assert(CV != 0 && "Const value should be ConstSDNode.");
4989 const APInt &CVal = CV->getAPIntValue();
4990 APInt NewVal = CVal & Mask;
4991 if (NewVal != CVal) {
4992 return DAG.getConstant(NewVal, V.getValueType());
4998 // If the LHS or RHS don't contribute bits to the or, drop them.
4999 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
5000 return V.getOperand(1);
5001 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
5002 return V.getOperand(0);
5005 // Only look at single-use SRLs.
5006 if (!V.getNode()->hasOneUse())
5008 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
5009 // See if we can recursively simplify the LHS.
5010 unsigned Amt = RHSC->getZExtValue();
5012 // Watch out for shift count overflow though.
5013 if (Amt >= Mask.getBitWidth()) break;
5014 APInt NewMask = Mask << Amt;
5015 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
5016 if (SimplifyLHS.getNode())
5017 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
5018 SimplifyLHS, V.getOperand(1));
5024 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
5025 /// bits and then truncated to a narrower type and where N is a multiple
5026 /// of number of bits of the narrower type, transform it to a narrower load
5027 /// from address + N / num of bits of new type. If the result is to be
5028 /// extended, also fold the extension to form a extending load.
5029 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
5030 unsigned Opc = N->getOpcode();
5032 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
5033 SDValue N0 = N->getOperand(0);
5034 EVT VT = N->getValueType(0);
5037 // This transformation isn't valid for vector loads.
5041 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
5043 if (Opc == ISD::SIGN_EXTEND_INREG) {
5044 ExtType = ISD::SEXTLOAD;
5045 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
5046 } else if (Opc == ISD::SRL) {
5047 // Another special-case: SRL is basically zero-extending a narrower value.
5048 ExtType = ISD::ZEXTLOAD;
5050 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5051 if (!N01) return SDValue();
5052 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
5053 VT.getSizeInBits() - N01->getZExtValue());
5055 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
5058 unsigned EVTBits = ExtVT.getSizeInBits();
5060 // Do not generate loads of non-round integer types since these can
5061 // be expensive (and would be wrong if the type is not byte sized).
5062 if (!ExtVT.isRound())
5066 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
5067 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5068 ShAmt = N01->getZExtValue();
5069 // Is the shift amount a multiple of size of VT?
5070 if ((ShAmt & (EVTBits-1)) == 0) {
5071 N0 = N0.getOperand(0);
5072 // Is the load width a multiple of size of VT?
5073 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
5077 // At this point, we must have a load or else we can't do the transform.
5078 if (!isa<LoadSDNode>(N0)) return SDValue();
5080 // Because a SRL must be assumed to *need* to zero-extend the high bits
5081 // (as opposed to anyext the high bits), we can't combine the zextload
5082 // lowering of SRL and an sextload.
5083 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD)
5086 // If the shift amount is larger than the input type then we're not
5087 // accessing any of the loaded bytes. If the load was a zextload/extload
5088 // then the result of the shift+trunc is zero/undef (handled elsewhere).
5089 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
5094 // If the load is shifted left (and the result isn't shifted back right),
5095 // we can fold the truncate through the shift.
5096 unsigned ShLeftAmt = 0;
5097 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
5098 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
5099 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5100 ShLeftAmt = N01->getZExtValue();
5101 N0 = N0.getOperand(0);
5105 // If we haven't found a load, we can't narrow it. Don't transform one with
5106 // multiple uses, this would require adding a new load.
5107 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse())
5110 // Don't change the width of a volatile load.
5111 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5112 if (LN0->isVolatile())
5115 // Verify that we are actually reducing a load width here.
5116 if (LN0->getMemoryVT().getSizeInBits() < EVTBits)
5119 // For the transform to be legal, the load must produce only two values
5120 // (the value loaded and the chain). Don't transform a pre-increment
5121 // load, for example, which produces an extra value. Otherwise the
5122 // transformation is not equivalent, and the downstream logic to replace
5123 // uses gets things wrong.
5124 if (LN0->getNumValues() > 2)
5127 EVT PtrType = N0.getOperand(1).getValueType();
5129 if (PtrType == MVT::Untyped || PtrType.isExtended())
5130 // It's not possible to generate a constant of extended or untyped type.
5133 // For big endian targets, we need to adjust the offset to the pointer to
5134 // load the correct bytes.
5135 if (TLI.isBigEndian()) {
5136 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
5137 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
5138 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
5141 uint64_t PtrOff = ShAmt / 8;
5142 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
5143 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
5144 PtrType, LN0->getBasePtr(),
5145 DAG.getConstant(PtrOff, PtrType));
5146 AddToWorkList(NewPtr.getNode());
5149 if (ExtType == ISD::NON_EXTLOAD)
5150 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
5151 LN0->getPointerInfo().getWithOffset(PtrOff),
5152 LN0->isVolatile(), LN0->isNonTemporal(),
5153 LN0->isInvariant(), NewAlign);
5155 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr,
5156 LN0->getPointerInfo().getWithOffset(PtrOff),
5157 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
5160 // Replace the old load's chain with the new load's chain.
5161 WorkListRemover DeadNodes(*this);
5162 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
5164 // Shift the result left, if we've swallowed a left shift.
5165 SDValue Result = Load;
5166 if (ShLeftAmt != 0) {
5167 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
5168 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
5170 // If the shift amount is as large as the result size (but, presumably,
5171 // no larger than the source) then the useful bits of the result are
5172 // zero; we can't simply return the shortened shift, because the result
5173 // of that operation is undefined.
5174 if (ShLeftAmt >= VT.getSizeInBits())
5175 Result = DAG.getConstant(0, VT);
5177 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT,
5178 Result, DAG.getConstant(ShLeftAmt, ShImmTy));
5181 // Return the new loaded value.
5185 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
5186 SDValue N0 = N->getOperand(0);
5187 SDValue N1 = N->getOperand(1);
5188 EVT VT = N->getValueType(0);
5189 EVT EVT = cast<VTSDNode>(N1)->getVT();
5190 unsigned VTBits = VT.getScalarType().getSizeInBits();
5191 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
5193 // fold (sext_in_reg c1) -> c1
5194 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
5195 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
5197 // If the input is already sign extended, just drop the extension.
5198 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
5201 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
5202 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
5203 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
5204 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
5205 N0.getOperand(0), N1);
5208 // fold (sext_in_reg (sext x)) -> (sext x)
5209 // fold (sext_in_reg (aext x)) -> (sext x)
5210 // if x is small enough.
5211 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
5212 SDValue N00 = N0.getOperand(0);
5213 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
5214 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
5215 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
5218 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
5219 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
5220 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
5222 // fold operands of sext_in_reg based on knowledge that the top bits are not
5224 if (SimplifyDemandedBits(SDValue(N, 0)))
5225 return SDValue(N, 0);
5227 // fold (sext_in_reg (load x)) -> (smaller sextload x)
5228 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
5229 SDValue NarrowLoad = ReduceLoadWidth(N);
5230 if (NarrowLoad.getNode())
5233 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
5234 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
5235 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
5236 if (N0.getOpcode() == ISD::SRL) {
5237 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
5238 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
5239 // We can turn this into an SRA iff the input to the SRL is already sign
5241 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
5242 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
5243 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
5244 N0.getOperand(0), N0.getOperand(1));
5248 // fold (sext_inreg (extload x)) -> (sextload x)
5249 if (ISD::isEXTLoad(N0.getNode()) &&
5250 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5251 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5252 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5253 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5254 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5255 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
5257 LN0->getBasePtr(), LN0->getPointerInfo(),
5259 LN0->isVolatile(), LN0->isNonTemporal(),
5260 LN0->getAlignment());
5261 CombineTo(N, ExtLoad);
5262 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5263 AddToWorkList(ExtLoad.getNode());
5264 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5266 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
5267 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5269 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5270 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5271 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5272 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5273 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
5275 LN0->getBasePtr(), LN0->getPointerInfo(),
5277 LN0->isVolatile(), LN0->isNonTemporal(),
5278 LN0->getAlignment());
5279 CombineTo(N, ExtLoad);
5280 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5281 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5284 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
5285 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
5286 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
5287 N0.getOperand(1), false);
5288 if (BSwap.getNode() != 0)
5289 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
5296 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
5297 SDValue N0 = N->getOperand(0);
5298 EVT VT = N->getValueType(0);
5299 bool isLE = TLI.isLittleEndian();
5302 if (N0.getValueType() == N->getValueType(0))
5304 // fold (truncate c1) -> c1
5305 if (isa<ConstantSDNode>(N0))
5306 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
5307 // fold (truncate (truncate x)) -> (truncate x)
5308 if (N0.getOpcode() == ISD::TRUNCATE)
5309 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
5310 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
5311 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
5312 N0.getOpcode() == ISD::SIGN_EXTEND ||
5313 N0.getOpcode() == ISD::ANY_EXTEND) {
5314 if (N0.getOperand(0).getValueType().bitsLT(VT))
5315 // if the source is smaller than the dest, we still need an extend
5316 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
5318 if (N0.getOperand(0).getValueType().bitsGT(VT))
5319 // if the source is larger than the dest, than we just need the truncate
5320 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
5321 // if the source and dest are the same type, we can drop both the extend
5322 // and the truncate.
5323 return N0.getOperand(0);
5326 // Fold extract-and-trunc into a narrow extract. For example:
5327 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
5328 // i32 y = TRUNCATE(i64 x)
5330 // v16i8 b = BITCAST (v2i64 val)
5331 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8)
5333 // Note: We only run this optimization after type legalization (which often
5334 // creates this pattern) and before operation legalization after which
5335 // we need to be more careful about the vector instructions that we generate.
5336 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5337 LegalTypes && !LegalOperations && N0->hasOneUse()) {
5339 EVT VecTy = N0.getOperand(0).getValueType();
5340 EVT ExTy = N0.getValueType();
5341 EVT TrTy = N->getValueType(0);
5343 unsigned NumElem = VecTy.getVectorNumElements();
5344 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits();
5346 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem);
5347 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size");
5349 SDValue EltNo = N0->getOperand(1);
5350 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
5351 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5352 EVT IndexTy = N0->getOperand(1).getValueType();
5353 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
5355 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5356 NVT, N0.getOperand(0));
5358 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
5359 N->getDebugLoc(), TrTy, V,
5360 DAG.getConstant(Index, IndexTy));
5364 // Fold a series of buildvector, bitcast, and truncate if possible.
5366 // (2xi32 trunc (bitcast ((4xi32)buildvector x, x, y, y) 2xi64)) to
5367 // (2xi32 (buildvector x, y)).
5368 if (Level == AfterLegalizeVectorOps && VT.isVector() &&
5369 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
5370 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
5371 N0.getOperand(0).hasOneUse()) {
5373 SDValue BuildVect = N0.getOperand(0);
5374 EVT BuildVectEltTy = BuildVect.getValueType().getVectorElementType();
5375 EVT TruncVecEltTy = VT.getVectorElementType();
5377 // Check that the element types match.
5378 if (BuildVectEltTy == TruncVecEltTy) {
5379 // Now we only need to compute the offset of the truncated elements.
5380 unsigned BuildVecNumElts = BuildVect.getNumOperands();
5381 unsigned TruncVecNumElts = VT.getVectorNumElements();
5382 unsigned TruncEltOffset = BuildVecNumElts / TruncVecNumElts;
5384 assert((BuildVecNumElts % TruncVecNumElts) == 0 &&
5385 "Invalid number of elements");
5387 SmallVector<SDValue, 8> Opnds;
5388 for (unsigned i = 0, e = BuildVecNumElts; i != e; i += TruncEltOffset)
5389 Opnds.push_back(BuildVect.getOperand(i));
5391 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, &Opnds[0],
5396 // See if we can simplify the input to this truncate through knowledge that
5397 // only the low bits are being used.
5398 // For example "trunc (or (shl x, 8), y)" // -> trunc y
5399 // Currently we only perform this optimization on scalars because vectors
5400 // may have different active low bits.
5401 if (!VT.isVector()) {
5403 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
5404 VT.getSizeInBits()));
5405 if (Shorter.getNode())
5406 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
5408 // fold (truncate (load x)) -> (smaller load x)
5409 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
5410 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
5411 SDValue Reduced = ReduceLoadWidth(N);
5412 if (Reduced.getNode())
5415 // fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)),
5416 // where ... are all 'undef'.
5417 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) {
5418 SmallVector<EVT, 8> VTs;
5421 unsigned NumDefs = 0;
5423 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
5424 SDValue X = N0.getOperand(i);
5425 if (X.getOpcode() != ISD::UNDEF) {
5430 // Stop if more than one members are non-undef.
5433 VTs.push_back(EVT::getVectorVT(*DAG.getContext(),
5434 VT.getVectorElementType(),
5435 X.getValueType().getVectorNumElements()));
5439 return DAG.getUNDEF(VT);
5442 assert(V.getNode() && "The single defined operand is empty!");
5443 SmallVector<SDValue, 8> Opnds;
5444 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
5446 Opnds.push_back(DAG.getUNDEF(VTs[i]));
5449 SDValue NV = DAG.getNode(ISD::TRUNCATE, V.getDebugLoc(), VTs[i], V);
5450 AddToWorkList(NV.getNode());
5451 Opnds.push_back(NV);
5453 return DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
5454 &Opnds[0], Opnds.size());
5458 // Simplify the operands using demanded-bits information.
5459 if (!VT.isVector() &&
5460 SimplifyDemandedBits(SDValue(N, 0)))
5461 return SDValue(N, 0);
5466 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
5467 SDValue Elt = N->getOperand(i);
5468 if (Elt.getOpcode() != ISD::MERGE_VALUES)
5469 return Elt.getNode();
5470 return Elt.getOperand(Elt.getResNo()).getNode();
5473 /// CombineConsecutiveLoads - build_pair (load, load) -> load
5474 /// if load locations are consecutive.
5475 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
5476 assert(N->getOpcode() == ISD::BUILD_PAIR);
5478 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
5479 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
5480 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
5481 LD1->getPointerInfo().getAddrSpace() !=
5482 LD2->getPointerInfo().getAddrSpace())
5484 EVT LD1VT = LD1->getValueType(0);
5486 if (ISD::isNON_EXTLoad(LD2) &&
5488 // If both are volatile this would reduce the number of volatile loads.
5489 // If one is volatile it might be ok, but play conservative and bail out.
5490 !LD1->isVolatile() &&
5491 !LD2->isVolatile() &&
5492 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
5493 unsigned Align = LD1->getAlignment();
5494 unsigned NewAlign = TLI.getDataLayout()->
5495 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5497 if (NewAlign <= Align &&
5498 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
5499 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
5500 LD1->getBasePtr(), LD1->getPointerInfo(),
5501 false, false, false, Align);
5507 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
5508 SDValue N0 = N->getOperand(0);
5509 EVT VT = N->getValueType(0);
5511 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
5512 // Only do this before legalize, since afterward the target may be depending
5513 // on the bitconvert.
5514 // First check to see if this is all constant.
5516 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
5518 bool isSimple = true;
5519 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
5520 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
5521 N0.getOperand(i).getOpcode() != ISD::Constant &&
5522 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
5527 EVT DestEltVT = N->getValueType(0).getVectorElementType();
5528 assert(!DestEltVT.isVector() &&
5529 "Element type of vector ValueType must not be vector!");
5531 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
5534 // If the input is a constant, let getNode fold it.
5535 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
5536 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0);
5537 if (Res.getNode() != N) {
5538 if (!LegalOperations ||
5539 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
5542 // Folding it resulted in an illegal node, and it's too late to
5543 // do that. Clean up the old node and forego the transformation.
5544 // Ideally this won't happen very often, because instcombine
5545 // and the earlier dagcombine runs (where illegal nodes are
5546 // permitted) should have folded most of them already.
5547 DAG.DeleteNode(Res.getNode());
5551 // (conv (conv x, t1), t2) -> (conv x, t2)
5552 if (N0.getOpcode() == ISD::BITCAST)
5553 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT,
5556 // fold (conv (load x)) -> (load (conv*)x)
5557 // If the resultant load doesn't need a higher alignment than the original!
5558 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
5559 // Do not change the width of a volatile load.
5560 !cast<LoadSDNode>(N0)->isVolatile() &&
5561 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
5562 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5563 unsigned Align = TLI.getDataLayout()->
5564 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5565 unsigned OrigAlign = LN0->getAlignment();
5567 if (Align <= OrigAlign) {
5568 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
5569 LN0->getBasePtr(), LN0->getPointerInfo(),
5570 LN0->isVolatile(), LN0->isNonTemporal(),
5571 LN0->isInvariant(), OrigAlign);
5573 CombineTo(N0.getNode(),
5574 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5575 N0.getValueType(), Load),
5581 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
5582 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
5583 // This often reduces constant pool loads.
5584 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) ||
5585 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) &&
5586 N0.getNode()->hasOneUse() && VT.isInteger() &&
5587 !VT.isVector() && !N0.getValueType().isVector()) {
5588 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT,
5590 AddToWorkList(NewConv.getNode());
5592 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5593 if (N0.getOpcode() == ISD::FNEG)
5594 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
5595 NewConv, DAG.getConstant(SignBit, VT));
5596 assert(N0.getOpcode() == ISD::FABS);
5597 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
5598 NewConv, DAG.getConstant(~SignBit, VT));
5601 // fold (bitconvert (fcopysign cst, x)) ->
5602 // (or (and (bitconvert x), sign), (and cst, (not sign)))
5603 // Note that we don't handle (copysign x, cst) because this can always be
5604 // folded to an fneg or fabs.
5605 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
5606 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
5607 VT.isInteger() && !VT.isVector()) {
5608 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
5609 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
5610 if (isTypeLegal(IntXVT)) {
5611 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5612 IntXVT, N0.getOperand(1));
5613 AddToWorkList(X.getNode());
5615 // If X has a different width than the result/lhs, sext it or truncate it.
5616 unsigned VTWidth = VT.getSizeInBits();
5617 if (OrigXWidth < VTWidth) {
5618 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
5619 AddToWorkList(X.getNode());
5620 } else if (OrigXWidth > VTWidth) {
5621 // To get the sign bit in the right place, we have to shift it right
5622 // before truncating.
5623 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
5624 X.getValueType(), X,
5625 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
5626 AddToWorkList(X.getNode());
5627 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
5628 AddToWorkList(X.getNode());
5631 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5632 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
5633 X, DAG.getConstant(SignBit, VT));
5634 AddToWorkList(X.getNode());
5636 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5637 VT, N0.getOperand(0));
5638 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
5639 Cst, DAG.getConstant(~SignBit, VT));
5640 AddToWorkList(Cst.getNode());
5642 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
5646 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
5647 if (N0.getOpcode() == ISD::BUILD_PAIR) {
5648 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
5649 if (CombineLD.getNode())
5656 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
5657 EVT VT = N->getValueType(0);
5658 return CombineConsecutiveLoads(N, VT);
5661 /// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector
5662 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
5663 /// destination element value type.
5664 SDValue DAGCombiner::
5665 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
5666 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
5668 // If this is already the right type, we're done.
5669 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
5671 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
5672 unsigned DstBitSize = DstEltVT.getSizeInBits();
5674 // If this is a conversion of N elements of one type to N elements of another
5675 // type, convert each element. This handles FP<->INT cases.
5676 if (SrcBitSize == DstBitSize) {
5677 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5678 BV->getValueType(0).getVectorNumElements());
5680 // Due to the FP element handling below calling this routine recursively,
5681 // we can end up with a scalar-to-vector node here.
5682 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
5683 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5684 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5685 DstEltVT, BV->getOperand(0)));
5687 SmallVector<SDValue, 8> Ops;
5688 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5689 SDValue Op = BV->getOperand(i);
5690 // If the vector element type is not legal, the BUILD_VECTOR operands
5691 // are promoted and implicitly truncated. Make that explicit here.
5692 if (Op.getValueType() != SrcEltVT)
5693 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
5694 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5696 AddToWorkList(Ops.back().getNode());
5698 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5699 &Ops[0], Ops.size());
5702 // Otherwise, we're growing or shrinking the elements. To avoid having to
5703 // handle annoying details of growing/shrinking FP values, we convert them to
5705 if (SrcEltVT.isFloatingPoint()) {
5706 // Convert the input float vector to a int vector where the elements are the
5708 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
5709 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
5710 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
5714 // Now we know the input is an integer vector. If the output is a FP type,
5715 // convert to integer first, then to FP of the right size.
5716 if (DstEltVT.isFloatingPoint()) {
5717 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
5718 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
5719 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
5721 // Next, convert to FP elements of the same size.
5722 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
5725 // Okay, we know the src/dst types are both integers of differing types.
5726 // Handling growing first.
5727 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
5728 if (SrcBitSize < DstBitSize) {
5729 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
5731 SmallVector<SDValue, 8> Ops;
5732 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
5733 i += NumInputsPerOutput) {
5734 bool isLE = TLI.isLittleEndian();
5735 APInt NewBits = APInt(DstBitSize, 0);
5736 bool EltIsUndef = true;
5737 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
5738 // Shift the previously computed bits over.
5739 NewBits <<= SrcBitSize;
5740 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
5741 if (Op.getOpcode() == ISD::UNDEF) continue;
5744 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
5745 zextOrTrunc(SrcBitSize).zext(DstBitSize);
5749 Ops.push_back(DAG.getUNDEF(DstEltVT));
5751 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
5754 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
5755 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5756 &Ops[0], Ops.size());
5759 // Finally, this must be the case where we are shrinking elements: each input
5760 // turns into multiple outputs.
5761 bool isS2V = ISD::isScalarToVector(BV);
5762 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
5763 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5764 NumOutputsPerInput*BV->getNumOperands());
5765 SmallVector<SDValue, 8> Ops;
5767 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5768 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
5769 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
5770 Ops.push_back(DAG.getUNDEF(DstEltVT));
5774 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
5775 getAPIntValue().zextOrTrunc(SrcBitSize);
5777 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
5778 APInt ThisVal = OpVal.trunc(DstBitSize);
5779 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
5780 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
5781 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
5782 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5784 OpVal = OpVal.lshr(DstBitSize);
5787 // For big endian targets, swap the order of the pieces of each element.
5788 if (TLI.isBigEndian())
5789 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
5792 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5793 &Ops[0], Ops.size());
5796 SDValue DAGCombiner::visitFADD(SDNode *N) {
5797 SDValue N0 = N->getOperand(0);
5798 SDValue N1 = N->getOperand(1);
5799 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5800 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5801 EVT VT = N->getValueType(0);
5804 if (VT.isVector()) {
5805 SDValue FoldedVOp = SimplifyVBinOp(N);
5806 if (FoldedVOp.getNode()) return FoldedVOp;
5809 // fold (fadd c1, c2) -> c1 + c2
5811 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
5812 // canonicalize constant to RHS
5813 if (N0CFP && !N1CFP)
5814 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
5815 // fold (fadd A, 0) -> A
5816 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5817 N1CFP->getValueAPF().isZero())
5819 // fold (fadd A, (fneg B)) -> (fsub A, B)
5820 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5821 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
5822 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
5823 GetNegatedExpression(N1, DAG, LegalOperations));
5824 // fold (fadd (fneg A), B) -> (fsub B, A)
5825 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5826 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
5827 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
5828 GetNegatedExpression(N0, DAG, LegalOperations));
5830 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
5831 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5832 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
5833 isa<ConstantFPSDNode>(N0.getOperand(1)))
5834 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
5835 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5836 N0.getOperand(1), N1));
5838 // If allow, fold (fadd (fneg x), x) -> 0.0
5839 if (DAG.getTarget().Options.UnsafeFPMath &&
5840 N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) {
5841 return DAG.getConstantFP(0.0, VT);
5844 // If allow, fold (fadd x, (fneg x)) -> 0.0
5845 if (DAG.getTarget().Options.UnsafeFPMath &&
5846 N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0) {
5847 return DAG.getConstantFP(0.0, VT);
5850 // In unsafe math mode, we can fold chains of FADD's of the same value
5851 // into multiplications. This transform is not safe in general because
5852 // we are reducing the number of rounding steps.
5853 if (DAG.getTarget().Options.UnsafeFPMath &&
5854 TLI.isOperationLegalOrCustom(ISD::FMUL, VT) &&
5856 if (N0.getOpcode() == ISD::FMUL) {
5857 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
5858 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
5860 // (fadd (fmul c, x), x) -> (fmul c+1, x)
5861 if (CFP00 && !CFP01 && N0.getOperand(1) == N1) {
5862 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5864 DAG.getConstantFP(1.0, VT));
5865 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5869 // (fadd (fmul x, c), x) -> (fmul c+1, x)
5870 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) {
5871 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5873 DAG.getConstantFP(1.0, VT));
5874 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5878 // (fadd (fmul c, x), (fadd x, x)) -> (fmul c+2, x)
5879 if (CFP00 && !CFP01 && N1.getOpcode() == ISD::FADD &&
5880 N1.getOperand(0) == N1.getOperand(1) &&
5881 N0.getOperand(1) == N1.getOperand(0)) {
5882 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5884 DAG.getConstantFP(2.0, VT));
5885 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5886 N0.getOperand(1), NewCFP);
5889 // (fadd (fmul x, c), (fadd x, x)) -> (fmul c+2, x)
5890 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD &&
5891 N1.getOperand(0) == N1.getOperand(1) &&
5892 N0.getOperand(0) == N1.getOperand(0)) {
5893 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5895 DAG.getConstantFP(2.0, VT));
5896 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5897 N0.getOperand(0), NewCFP);
5901 if (N1.getOpcode() == ISD::FMUL) {
5902 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
5903 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1));
5905 // (fadd x, (fmul c, x)) -> (fmul c+1, x)
5906 if (CFP10 && !CFP11 && N1.getOperand(1) == N0) {
5907 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5909 DAG.getConstantFP(1.0, VT));
5910 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5914 // (fadd x, (fmul x, c)) -> (fmul c+1, x)
5915 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) {
5916 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5918 DAG.getConstantFP(1.0, VT));
5919 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5924 // (fadd (fadd x, x), (fmul c, x)) -> (fmul c+2, x)
5925 if (CFP10 && !CFP11 && N1.getOpcode() == ISD::FADD &&
5926 N1.getOperand(0) == N1.getOperand(1) &&
5927 N0.getOperand(1) == N1.getOperand(0)) {
5928 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5930 DAG.getConstantFP(2.0, VT));
5931 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5932 N0.getOperand(1), NewCFP);
5935 // (fadd (fadd x, x), (fmul x, c)) -> (fmul c+2, x)
5936 if (CFP11 && !CFP10 && N1.getOpcode() == ISD::FADD &&
5937 N1.getOperand(0) == N1.getOperand(1) &&
5938 N0.getOperand(0) == N1.getOperand(0)) {
5939 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5941 DAG.getConstantFP(2.0, VT));
5942 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5943 N0.getOperand(0), NewCFP);
5947 if (N0.getOpcode() == ISD::FADD) {
5948 ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
5949 // (fadd (fadd x, x), x) -> (fmul 3.0, x)
5950 if (!CFP && N0.getOperand(0) == N0.getOperand(1) &&
5951 (N0.getOperand(0) == N1)) {
5952 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5953 N1, DAG.getConstantFP(3.0, VT));
5957 if (N1.getOpcode() == ISD::FADD) {
5958 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
5959 // (fadd x, (fadd x, x)) -> (fmul 3.0, x)
5960 if (!CFP10 && N1.getOperand(0) == N1.getOperand(1) &&
5961 N1.getOperand(0) == N0) {
5962 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5963 N0, DAG.getConstantFP(3.0, VT));
5967 // (fadd (fadd x, x), (fadd x, x)) -> (fmul 4.0, x)
5968 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
5969 N0.getOperand(0) == N0.getOperand(1) &&
5970 N1.getOperand(0) == N1.getOperand(1) &&
5971 N0.getOperand(0) == N1.getOperand(0)) {
5972 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5974 DAG.getConstantFP(4.0, VT));
5978 // FADD -> FMA combines:
5979 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast ||
5980 DAG.getTarget().Options.UnsafeFPMath) &&
5981 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) &&
5982 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) {
5984 // fold (fadd (fmul x, y), z) -> (fma x, y, z)
5985 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) {
5986 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT,
5987 N0.getOperand(0), N0.getOperand(1), N1);
5990 // fold (fadd x, (fmul y, z)) -> (fma y, z, x)
5991 // Note: Commutes FADD operands.
5992 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) {
5993 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT,
5994 N1.getOperand(0), N1.getOperand(1), N0);
6001 SDValue DAGCombiner::visitFSUB(SDNode *N) {
6002 SDValue N0 = N->getOperand(0);
6003 SDValue N1 = N->getOperand(1);
6004 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6005 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6006 EVT VT = N->getValueType(0);
6007 DebugLoc dl = N->getDebugLoc();
6010 if (VT.isVector()) {
6011 SDValue FoldedVOp = SimplifyVBinOp(N);
6012 if (FoldedVOp.getNode()) return FoldedVOp;
6015 // fold (fsub c1, c2) -> c1-c2
6017 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
6018 // fold (fsub A, 0) -> A
6019 if (DAG.getTarget().Options.UnsafeFPMath &&
6020 N1CFP && N1CFP->getValueAPF().isZero())
6022 // fold (fsub 0, B) -> -B
6023 if (DAG.getTarget().Options.UnsafeFPMath &&
6024 N0CFP && N0CFP->getValueAPF().isZero()) {
6025 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options))
6026 return GetNegatedExpression(N1, DAG, LegalOperations);
6027 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6028 return DAG.getNode(ISD::FNEG, dl, VT, N1);
6030 // fold (fsub A, (fneg B)) -> (fadd A, B)
6031 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options))
6032 return DAG.getNode(ISD::FADD, dl, VT, N0,
6033 GetNegatedExpression(N1, DAG, LegalOperations));
6035 // If 'unsafe math' is enabled, fold
6036 // (fsub x, x) -> 0.0 &
6037 // (fsub x, (fadd x, y)) -> (fneg y) &
6038 // (fsub x, (fadd y, x)) -> (fneg y)
6039 if (DAG.getTarget().Options.UnsafeFPMath) {
6041 return DAG.getConstantFP(0.0f, VT);
6043 if (N1.getOpcode() == ISD::FADD) {
6044 SDValue N10 = N1->getOperand(0);
6045 SDValue N11 = N1->getOperand(1);
6047 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI,
6048 &DAG.getTarget().Options))
6049 return GetNegatedExpression(N11, DAG, LegalOperations);
6050 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI,
6051 &DAG.getTarget().Options))
6052 return GetNegatedExpression(N10, DAG, LegalOperations);
6056 // FSUB -> FMA combines:
6057 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast ||
6058 DAG.getTarget().Options.UnsafeFPMath) &&
6059 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) &&
6060 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) {
6062 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
6063 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) {
6064 return DAG.getNode(ISD::FMA, dl, VT,
6065 N0.getOperand(0), N0.getOperand(1),
6066 DAG.getNode(ISD::FNEG, dl, VT, N1));
6069 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
6070 // Note: Commutes FSUB operands.
6071 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) {
6072 return DAG.getNode(ISD::FMA, dl, VT,
6073 DAG.getNode(ISD::FNEG, dl, VT,
6075 N1.getOperand(1), N0);
6078 // fold (fsub (-(fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
6079 if (N0.getOpcode() == ISD::FNEG &&
6080 N0.getOperand(0).getOpcode() == ISD::FMUL &&
6081 N0->hasOneUse() && N0.getOperand(0).hasOneUse()) {
6082 SDValue N00 = N0.getOperand(0).getOperand(0);
6083 SDValue N01 = N0.getOperand(0).getOperand(1);
6084 return DAG.getNode(ISD::FMA, dl, VT,
6085 DAG.getNode(ISD::FNEG, dl, VT, N00), N01,
6086 DAG.getNode(ISD::FNEG, dl, VT, N1));
6093 SDValue DAGCombiner::visitFMUL(SDNode *N) {
6094 SDValue N0 = N->getOperand(0);
6095 SDValue N1 = N->getOperand(1);
6096 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6097 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6098 EVT VT = N->getValueType(0);
6099 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6102 if (VT.isVector()) {
6103 SDValue FoldedVOp = SimplifyVBinOp(N);
6104 if (FoldedVOp.getNode()) return FoldedVOp;
6107 // fold (fmul c1, c2) -> c1*c2
6109 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
6110 // canonicalize constant to RHS
6111 if (N0CFP && !N1CFP)
6112 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
6113 // fold (fmul A, 0) -> 0
6114 if (DAG.getTarget().Options.UnsafeFPMath &&
6115 N1CFP && N1CFP->getValueAPF().isZero())
6117 // fold (fmul A, 0) -> 0, vector edition.
6118 if (DAG.getTarget().Options.UnsafeFPMath &&
6119 ISD::isBuildVectorAllZeros(N1.getNode()))
6121 // fold (fmul A, 1.0) -> A
6122 if (N1CFP && N1CFP->isExactlyValue(1.0))
6124 // fold (fmul X, 2.0) -> (fadd X, X)
6125 if (N1CFP && N1CFP->isExactlyValue(+2.0))
6126 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
6127 // fold (fmul X, -1.0) -> (fneg X)
6128 if (N1CFP && N1CFP->isExactlyValue(-1.0))
6129 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6130 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
6132 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
6133 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
6134 &DAG.getTarget().Options)) {
6135 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI,
6136 &DAG.getTarget().Options)) {
6137 // Both can be negated for free, check to see if at least one is cheaper
6139 if (LHSNeg == 2 || RHSNeg == 2)
6140 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
6141 GetNegatedExpression(N0, DAG, LegalOperations),
6142 GetNegatedExpression(N1, DAG, LegalOperations));
6146 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
6147 if (DAG.getTarget().Options.UnsafeFPMath &&
6148 N1CFP && N0.getOpcode() == ISD::FMUL &&
6149 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
6150 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
6151 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
6152 N0.getOperand(1), N1));
6157 SDValue DAGCombiner::visitFMA(SDNode *N) {
6158 SDValue N0 = N->getOperand(0);
6159 SDValue N1 = N->getOperand(1);
6160 SDValue N2 = N->getOperand(2);
6161 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6162 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6163 EVT VT = N->getValueType(0);
6164 DebugLoc dl = N->getDebugLoc();
6166 if (DAG.getTarget().Options.UnsafeFPMath) {
6167 if (N0CFP && N0CFP->isZero())
6169 if (N1CFP && N1CFP->isZero())
6172 if (N0CFP && N0CFP->isExactlyValue(1.0))
6173 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N2);
6174 if (N1CFP && N1CFP->isExactlyValue(1.0))
6175 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N2);
6177 // Canonicalize (fma c, x, y) -> (fma x, c, y)
6178 if (N0CFP && !N1CFP)
6179 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, N1, N0, N2);
6181 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2)
6182 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
6183 N2.getOpcode() == ISD::FMUL &&
6184 N0 == N2.getOperand(0) &&
6185 N2.getOperand(1).getOpcode() == ISD::ConstantFP) {
6186 return DAG.getNode(ISD::FMUL, dl, VT, N0,
6187 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1)));
6191 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y)
6192 if (DAG.getTarget().Options.UnsafeFPMath &&
6193 N0.getOpcode() == ISD::FMUL && N1CFP &&
6194 N0.getOperand(1).getOpcode() == ISD::ConstantFP) {
6195 return DAG.getNode(ISD::FMA, dl, VT,
6197 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)),
6201 // (fma x, 1, y) -> (fadd x, y)
6202 // (fma x, -1, y) -> (fadd (fneg x), y)
6204 if (N1CFP->isExactlyValue(1.0))
6205 return DAG.getNode(ISD::FADD, dl, VT, N0, N2);
6207 if (N1CFP->isExactlyValue(-1.0) &&
6208 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) {
6209 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0);
6210 AddToWorkList(RHSNeg.getNode());
6211 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg);
6215 // (fma x, c, x) -> (fmul x, (c+1))
6216 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && N0 == N2) {
6217 return DAG.getNode(ISD::FMUL, dl, VT,
6219 DAG.getNode(ISD::FADD, dl, VT,
6220 N1, DAG.getConstantFP(1.0, VT)));
6223 // (fma x, c, (fneg x)) -> (fmul x, (c-1))
6224 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
6225 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) {
6226 return DAG.getNode(ISD::FMUL, dl, VT,
6228 DAG.getNode(ISD::FADD, dl, VT,
6229 N1, DAG.getConstantFP(-1.0, VT)));
6236 SDValue DAGCombiner::visitFDIV(SDNode *N) {
6237 SDValue N0 = N->getOperand(0);
6238 SDValue N1 = N->getOperand(1);
6239 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6240 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6241 EVT VT = N->getValueType(0);
6242 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6245 if (VT.isVector()) {
6246 SDValue FoldedVOp = SimplifyVBinOp(N);
6247 if (FoldedVOp.getNode()) return FoldedVOp;
6250 // fold (fdiv c1, c2) -> c1/c2
6252 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
6254 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable.
6255 if (N1CFP && DAG.getTarget().Options.UnsafeFPMath) {
6256 // Compute the reciprocal 1.0 / c2.
6257 APFloat N1APF = N1CFP->getValueAPF();
6258 APFloat Recip(N1APF.getSemantics(), 1); // 1.0
6259 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven);
6260 // Only do the transform if the reciprocal is a legal fp immediate that
6261 // isn't too nasty (eg NaN, denormal, ...).
6262 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty
6263 (!LegalOperations ||
6264 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM
6265 // backend)... we should handle this gracefully after Legalize.
6266 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) ||
6267 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) ||
6268 TLI.isFPImmLegal(Recip, VT)))
6269 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0,
6270 DAG.getConstantFP(Recip, VT));
6273 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
6274 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
6275 &DAG.getTarget().Options)) {
6276 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI,
6277 &DAG.getTarget().Options)) {
6278 // Both can be negated for free, check to see if at least one is cheaper
6280 if (LHSNeg == 2 || RHSNeg == 2)
6281 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
6282 GetNegatedExpression(N0, DAG, LegalOperations),
6283 GetNegatedExpression(N1, DAG, LegalOperations));
6290 SDValue DAGCombiner::visitFREM(SDNode *N) {
6291 SDValue N0 = N->getOperand(0);
6292 SDValue N1 = N->getOperand(1);
6293 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6294 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6295 EVT VT = N->getValueType(0);
6297 // fold (frem c1, c2) -> fmod(c1,c2)
6299 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
6304 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
6305 SDValue N0 = N->getOperand(0);
6306 SDValue N1 = N->getOperand(1);
6307 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6308 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6309 EVT VT = N->getValueType(0);
6311 if (N0CFP && N1CFP) // Constant fold
6312 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
6315 const APFloat& V = N1CFP->getValueAPF();
6316 // copysign(x, c1) -> fabs(x) iff ispos(c1)
6317 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
6318 if (!V.isNegative()) {
6319 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
6320 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
6322 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6323 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
6324 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
6328 // copysign(fabs(x), y) -> copysign(x, y)
6329 // copysign(fneg(x), y) -> copysign(x, y)
6330 // copysign(copysign(x,z), y) -> copysign(x, y)
6331 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
6332 N0.getOpcode() == ISD::FCOPYSIGN)
6333 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6334 N0.getOperand(0), N1);
6336 // copysign(x, abs(y)) -> abs(x)
6337 if (N1.getOpcode() == ISD::FABS)
6338 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
6340 // copysign(x, copysign(y,z)) -> copysign(x, z)
6341 if (N1.getOpcode() == ISD::FCOPYSIGN)
6342 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6343 N0, N1.getOperand(1));
6345 // copysign(x, fp_extend(y)) -> copysign(x, y)
6346 // copysign(x, fp_round(y)) -> copysign(x, y)
6347 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
6348 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6349 N0, N1.getOperand(0));
6354 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
6355 SDValue N0 = N->getOperand(0);
6356 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
6357 EVT VT = N->getValueType(0);
6358 EVT OpVT = N0.getValueType();
6360 // fold (sint_to_fp c1) -> c1fp
6362 // ...but only if the target supports immediate floating-point values
6363 (!LegalOperations ||
6364 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
6365 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
6367 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
6368 // but UINT_TO_FP is legal on this target, try to convert.
6369 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
6370 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
6371 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
6372 if (DAG.SignBitIsZero(N0))
6373 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
6376 // The next optimizations are desireable only if SELECT_CC can be lowered.
6377 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
6378 // having to say they don't support SELECT_CC on every type the DAG knows
6379 // about, since there is no way to mark an opcode illegal at all value types
6380 // (See also visitSELECT)
6381 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) {
6382 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
6383 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
6385 (!LegalOperations ||
6386 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6388 { N0.getOperand(0), N0.getOperand(1),
6389 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT),
6391 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5);
6394 // fold (sint_to_fp (zext (setcc x, y, cc))) ->
6395 // (select_cc x, y, 1.0, 0.0,, cc)
6396 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
6397 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
6398 (!LegalOperations ||
6399 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6401 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1),
6402 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT),
6403 N0.getOperand(0).getOperand(2) };
6404 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5);
6411 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
6412 SDValue N0 = N->getOperand(0);
6413 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
6414 EVT VT = N->getValueType(0);
6415 EVT OpVT = N0.getValueType();
6417 // fold (uint_to_fp c1) -> c1fp
6419 // ...but only if the target supports immediate floating-point values
6420 (!LegalOperations ||
6421 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
6422 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
6424 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
6425 // but SINT_TO_FP is legal on this target, try to convert.
6426 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
6427 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
6428 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
6429 if (DAG.SignBitIsZero(N0))
6430 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
6433 // The next optimizations are desireable only if SELECT_CC can be lowered.
6434 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
6435 // having to say they don't support SELECT_CC on every type the DAG knows
6436 // about, since there is no way to mark an opcode illegal at all value types
6437 // (See also visitSELECT)
6438 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) {
6439 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
6441 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
6442 (!LegalOperations ||
6443 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6445 { N0.getOperand(0), N0.getOperand(1),
6446 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT),
6448 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5);
6455 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
6456 SDValue N0 = N->getOperand(0);
6457 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6458 EVT VT = N->getValueType(0);
6460 // fold (fp_to_sint c1fp) -> c1
6462 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
6467 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
6468 SDValue N0 = N->getOperand(0);
6469 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6470 EVT VT = N->getValueType(0);
6472 // fold (fp_to_uint c1fp) -> c1
6474 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
6479 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
6480 SDValue N0 = N->getOperand(0);
6481 SDValue N1 = N->getOperand(1);
6482 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6483 EVT VT = N->getValueType(0);
6485 // fold (fp_round c1fp) -> c1fp
6487 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
6489 // fold (fp_round (fp_extend x)) -> x
6490 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
6491 return N0.getOperand(0);
6493 // fold (fp_round (fp_round x)) -> (fp_round x)
6494 if (N0.getOpcode() == ISD::FP_ROUND) {
6495 // This is a value preserving truncation if both round's are.
6496 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
6497 N0.getNode()->getConstantOperandVal(1) == 1;
6498 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
6499 DAG.getIntPtrConstant(IsTrunc));
6502 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
6503 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
6504 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
6505 N0.getOperand(0), N1);
6506 AddToWorkList(Tmp.getNode());
6507 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6508 Tmp, N0.getOperand(1));
6514 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
6515 SDValue N0 = N->getOperand(0);
6516 EVT VT = N->getValueType(0);
6517 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
6518 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6520 // fold (fp_round_inreg c1fp) -> c1fp
6521 if (N0CFP && isTypeLegal(EVT)) {
6522 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
6523 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
6529 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
6530 SDValue N0 = N->getOperand(0);
6531 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6532 EVT VT = N->getValueType(0);
6534 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
6535 if (N->hasOneUse() &&
6536 N->use_begin()->getOpcode() == ISD::FP_ROUND)
6539 // fold (fp_extend c1fp) -> c1fp
6541 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
6543 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
6545 if (N0.getOpcode() == ISD::FP_ROUND
6546 && N0.getNode()->getConstantOperandVal(1) == 1) {
6547 SDValue In = N0.getOperand(0);
6548 if (In.getValueType() == VT) return In;
6549 if (VT.bitsLT(In.getValueType()))
6550 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
6551 In, N0.getOperand(1));
6552 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
6555 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
6556 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
6557 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6558 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
6559 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6560 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
6562 LN0->getBasePtr(), LN0->getPointerInfo(),
6564 LN0->isVolatile(), LN0->isNonTemporal(),
6565 LN0->getAlignment());
6566 CombineTo(N, ExtLoad);
6567 CombineTo(N0.getNode(),
6568 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
6569 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
6570 ExtLoad.getValue(1));
6571 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6577 SDValue DAGCombiner::visitFNEG(SDNode *N) {
6578 SDValue N0 = N->getOperand(0);
6579 EVT VT = N->getValueType(0);
6581 if (VT.isVector()) {
6582 SDValue FoldedVOp = SimplifyVUnaryOp(N);
6583 if (FoldedVOp.getNode()) return FoldedVOp;
6586 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(),
6587 &DAG.getTarget().Options))
6588 return GetNegatedExpression(N0, DAG, LegalOperations);
6590 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
6591 // constant pool values.
6592 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST &&
6594 N0.getNode()->hasOneUse() &&
6595 N0.getOperand(0).getValueType().isInteger()) {
6596 SDValue Int = N0.getOperand(0);
6597 EVT IntVT = Int.getValueType();
6598 if (IntVT.isInteger() && !IntVT.isVector()) {
6599 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
6600 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
6601 AddToWorkList(Int.getNode());
6602 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
6607 // (fneg (fmul c, x)) -> (fmul -c, x)
6608 if (N0.getOpcode() == ISD::FMUL) {
6609 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
6611 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
6613 DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
6621 SDValue DAGCombiner::visitFCEIL(SDNode *N) {
6622 SDValue N0 = N->getOperand(0);
6623 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6624 EVT VT = N->getValueType(0);
6626 // fold (fceil c1) -> fceil(c1)
6628 return DAG.getNode(ISD::FCEIL, N->getDebugLoc(), VT, N0);
6633 SDValue DAGCombiner::visitFTRUNC(SDNode *N) {
6634 SDValue N0 = N->getOperand(0);
6635 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6636 EVT VT = N->getValueType(0);
6638 // fold (ftrunc c1) -> ftrunc(c1)
6640 return DAG.getNode(ISD::FTRUNC, N->getDebugLoc(), VT, N0);
6645 SDValue DAGCombiner::visitFFLOOR(SDNode *N) {
6646 SDValue N0 = N->getOperand(0);
6647 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6648 EVT VT = N->getValueType(0);
6650 // fold (ffloor c1) -> ffloor(c1)
6652 return DAG.getNode(ISD::FFLOOR, N->getDebugLoc(), VT, N0);
6657 SDValue DAGCombiner::visitFABS(SDNode *N) {
6658 SDValue N0 = N->getOperand(0);
6659 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6660 EVT VT = N->getValueType(0);
6662 if (VT.isVector()) {
6663 SDValue FoldedVOp = SimplifyVUnaryOp(N);
6664 if (FoldedVOp.getNode()) return FoldedVOp;
6667 // fold (fabs c1) -> fabs(c1)
6669 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
6670 // fold (fabs (fabs x)) -> (fabs x)
6671 if (N0.getOpcode() == ISD::FABS)
6672 return N->getOperand(0);
6673 // fold (fabs (fneg x)) -> (fabs x)
6674 // fold (fabs (fcopysign x, y)) -> (fabs x)
6675 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
6676 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
6678 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
6679 // constant pool values.
6680 if (!TLI.isFAbsFree(VT) &&
6681 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
6682 N0.getOperand(0).getValueType().isInteger() &&
6683 !N0.getOperand(0).getValueType().isVector()) {
6684 SDValue Int = N0.getOperand(0);
6685 EVT IntVT = Int.getValueType();
6686 if (IntVT.isInteger() && !IntVT.isVector()) {
6687 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
6688 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
6689 AddToWorkList(Int.getNode());
6690 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
6691 N->getValueType(0), Int);
6698 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
6699 SDValue Chain = N->getOperand(0);
6700 SDValue N1 = N->getOperand(1);
6701 SDValue N2 = N->getOperand(2);
6703 // If N is a constant we could fold this into a fallthrough or unconditional
6704 // branch. However that doesn't happen very often in normal code, because
6705 // Instcombine/SimplifyCFG should have handled the available opportunities.
6706 // If we did this folding here, it would be necessary to update the
6707 // MachineBasicBlock CFG, which is awkward.
6709 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
6711 if (N1.getOpcode() == ISD::SETCC &&
6712 TLI.isOperationLegalOrCustom(ISD::BR_CC,
6713 N1.getOperand(0).getValueType())) {
6714 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
6715 Chain, N1.getOperand(2),
6716 N1.getOperand(0), N1.getOperand(1), N2);
6719 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
6720 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
6721 (N1.getOperand(0).hasOneUse() &&
6722 N1.getOperand(0).getOpcode() == ISD::SRL))) {
6724 if (N1.getOpcode() == ISD::TRUNCATE) {
6725 // Look pass the truncate.
6726 Trunc = N1.getNode();
6727 N1 = N1.getOperand(0);
6730 // Match this pattern so that we can generate simpler code:
6733 // %b = and i32 %a, 2
6734 // %c = srl i32 %b, 1
6735 // brcond i32 %c ...
6740 // %b = and i32 %a, 2
6741 // %c = setcc eq %b, 0
6744 // This applies only when the AND constant value has one bit set and the
6745 // SRL constant is equal to the log2 of the AND constant. The back-end is
6746 // smart enough to convert the result into a TEST/JMP sequence.
6747 SDValue Op0 = N1.getOperand(0);
6748 SDValue Op1 = N1.getOperand(1);
6750 if (Op0.getOpcode() == ISD::AND &&
6751 Op1.getOpcode() == ISD::Constant) {
6752 SDValue AndOp1 = Op0.getOperand(1);
6754 if (AndOp1.getOpcode() == ISD::Constant) {
6755 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
6757 if (AndConst.isPowerOf2() &&
6758 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
6760 DAG.getSetCC(N->getDebugLoc(),
6761 TLI.getSetCCResultType(Op0.getValueType()),
6762 Op0, DAG.getConstant(0, Op0.getValueType()),
6765 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6766 MVT::Other, Chain, SetCC, N2);
6767 // Don't add the new BRCond into the worklist or else SimplifySelectCC
6768 // will convert it back to (X & C1) >> C2.
6769 CombineTo(N, NewBRCond, false);
6770 // Truncate is dead.
6772 removeFromWorkList(Trunc);
6773 DAG.DeleteNode(Trunc);
6775 // Replace the uses of SRL with SETCC
6776 WorkListRemover DeadNodes(*this);
6777 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
6778 removeFromWorkList(N1.getNode());
6779 DAG.DeleteNode(N1.getNode());
6780 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6786 // Restore N1 if the above transformation doesn't match.
6787 N1 = N->getOperand(1);
6790 // Transform br(xor(x, y)) -> br(x != y)
6791 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
6792 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
6793 SDNode *TheXor = N1.getNode();
6794 SDValue Op0 = TheXor->getOperand(0);
6795 SDValue Op1 = TheXor->getOperand(1);
6796 if (Op0.getOpcode() == Op1.getOpcode()) {
6797 // Avoid missing important xor optimizations.
6798 SDValue Tmp = visitXOR(TheXor);
6799 if (Tmp.getNode()) {
6800 if (Tmp.getNode() != TheXor) {
6801 DEBUG(dbgs() << "\nReplacing.8 ";
6803 dbgs() << "\nWith: ";
6804 Tmp.getNode()->dump(&DAG);
6806 WorkListRemover DeadNodes(*this);
6807 DAG.ReplaceAllUsesOfValueWith(N1, Tmp);
6808 removeFromWorkList(TheXor);
6809 DAG.DeleteNode(TheXor);
6810 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6811 MVT::Other, Chain, Tmp, N2);
6814 // visitXOR has changed XOR's operands.
6815 Op0 = TheXor->getOperand(0);
6816 Op1 = TheXor->getOperand(1);
6820 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
6822 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
6823 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
6824 Op0.getOpcode() == ISD::XOR) {
6825 TheXor = Op0.getNode();
6829 EVT SetCCVT = N1.getValueType();
6831 SetCCVT = TLI.getSetCCResultType(SetCCVT);
6832 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
6835 Equal ? ISD::SETEQ : ISD::SETNE);
6836 // Replace the uses of XOR with SETCC
6837 WorkListRemover DeadNodes(*this);
6838 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
6839 removeFromWorkList(N1.getNode());
6840 DAG.DeleteNode(N1.getNode());
6841 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6842 MVT::Other, Chain, SetCC, N2);
6849 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
6851 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
6852 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
6853 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
6855 // If N is a constant we could fold this into a fallthrough or unconditional
6856 // branch. However that doesn't happen very often in normal code, because
6857 // Instcombine/SimplifyCFG should have handled the available opportunities.
6858 // If we did this folding here, it would be necessary to update the
6859 // MachineBasicBlock CFG, which is awkward.
6861 // Use SimplifySetCC to simplify SETCC's.
6862 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
6863 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
6865 if (Simp.getNode()) AddToWorkList(Simp.getNode());
6867 // fold to a simpler setcc
6868 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
6869 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
6870 N->getOperand(0), Simp.getOperand(2),
6871 Simp.getOperand(0), Simp.getOperand(1),
6877 /// canFoldInAddressingMode - Return true if 'Use' is a load or a store that
6878 /// uses N as its base pointer and that N may be folded in the load / store
6879 /// addressing mode.
6880 static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
6882 const TargetLowering &TLI) {
6884 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) {
6885 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
6887 VT = Use->getValueType(0);
6888 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) {
6889 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
6891 VT = ST->getValue().getValueType();
6895 TargetLowering::AddrMode AM;
6896 if (N->getOpcode() == ISD::ADD) {
6897 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
6900 AM.BaseOffs = Offset->getSExtValue();
6904 } else if (N->getOpcode() == ISD::SUB) {
6905 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
6908 AM.BaseOffs = -Offset->getSExtValue();
6915 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext()));
6918 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
6919 /// pre-indexed load / store when the base pointer is an add or subtract
6920 /// and it has other uses besides the load / store. After the
6921 /// transformation, the new indexed load / store has effectively folded
6922 /// the add / subtract in and all of its other uses are redirected to the
6923 /// new load / store.
6924 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
6925 if (Level < AfterLegalizeDAG)
6931 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6932 if (LD->isIndexed())
6934 VT = LD->getMemoryVT();
6935 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
6936 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
6938 Ptr = LD->getBasePtr();
6939 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6940 if (ST->isIndexed())
6942 VT = ST->getMemoryVT();
6943 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
6944 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
6946 Ptr = ST->getBasePtr();
6952 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
6953 // out. There is no reason to make this a preinc/predec.
6954 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
6955 Ptr.getNode()->hasOneUse())
6958 // Ask the target to do addressing mode selection.
6961 ISD::MemIndexedMode AM = ISD::UNINDEXED;
6962 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
6965 // Backends without true r+i pre-indexed forms may need to pass a
6966 // constant base with a variable offset so that constant coercion
6967 // will work with the patterns in canonical form.
6968 bool Swapped = false;
6969 if (isa<ConstantSDNode>(BasePtr)) {
6970 std::swap(BasePtr, Offset);
6974 // Don't create a indexed load / store with zero offset.
6975 if (isa<ConstantSDNode>(Offset) &&
6976 cast<ConstantSDNode>(Offset)->isNullValue())
6979 // Try turning it into a pre-indexed load / store except when:
6980 // 1) The new base ptr is a frame index.
6981 // 2) If N is a store and the new base ptr is either the same as or is a
6982 // predecessor of the value being stored.
6983 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
6984 // that would create a cycle.
6985 // 4) All uses are load / store ops that use it as old base ptr.
6987 // Check #1. Preinc'ing a frame index would require copying the stack pointer
6988 // (plus the implicit offset) to a register to preinc anyway.
6989 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
6994 SDValue Val = cast<StoreSDNode>(N)->getValue();
6995 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
6999 // If the offset is a constant, there may be other adds of constants that
7000 // can be folded with this one. We should do this to avoid having to keep
7001 // a copy of the original base pointer.
7002 SmallVector<SDNode *, 16> OtherUses;
7003 if (isa<ConstantSDNode>(Offset))
7004 for (SDNode::use_iterator I = BasePtr.getNode()->use_begin(),
7005 E = BasePtr.getNode()->use_end(); I != E; ++I) {
7007 if (Use == Ptr.getNode())
7010 if (Use->isPredecessorOf(N))
7013 if (Use->getOpcode() != ISD::ADD && Use->getOpcode() != ISD::SUB) {
7018 SDValue Op0 = Use->getOperand(0), Op1 = Use->getOperand(1);
7019 if (Op1.getNode() == BasePtr.getNode())
7020 std::swap(Op0, Op1);
7021 assert(Op0.getNode() == BasePtr.getNode() &&
7022 "Use of ADD/SUB but not an operand");
7024 if (!isa<ConstantSDNode>(Op1)) {
7029 // FIXME: In some cases, we can be smarter about this.
7030 if (Op1.getValueType() != Offset.getValueType()) {
7035 OtherUses.push_back(Use);
7039 std::swap(BasePtr, Offset);
7041 // Now check for #3 and #4.
7042 bool RealUse = false;
7044 // Caches for hasPredecessorHelper
7045 SmallPtrSet<const SDNode *, 32> Visited;
7046 SmallVector<const SDNode *, 16> Worklist;
7048 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
7049 E = Ptr.getNode()->use_end(); I != E; ++I) {
7053 if (N->hasPredecessorHelper(Use, Visited, Worklist))
7056 // If Ptr may be folded in addressing mode of other use, then it's
7057 // not profitable to do this transformation.
7058 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI))
7067 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
7068 BasePtr, Offset, AM);
7070 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
7071 BasePtr, Offset, AM);
7074 DEBUG(dbgs() << "\nReplacing.4 ";
7076 dbgs() << "\nWith: ";
7077 Result.getNode()->dump(&DAG);
7079 WorkListRemover DeadNodes(*this);
7081 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
7082 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
7084 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
7087 // Finally, since the node is now dead, remove it from the graph.
7091 std::swap(BasePtr, Offset);
7093 // Replace other uses of BasePtr that can be updated to use Ptr
7094 for (unsigned i = 0, e = OtherUses.size(); i != e; ++i) {
7095 unsigned OffsetIdx = 1;
7096 if (OtherUses[i]->getOperand(OffsetIdx).getNode() == BasePtr.getNode())
7098 assert(OtherUses[i]->getOperand(!OffsetIdx).getNode() ==
7099 BasePtr.getNode() && "Expected BasePtr operand");
7102 cast<ConstantSDNode>(Offset)->getAPIntValue();
7103 if (AM == ISD::PRE_DEC)
7106 ConstantSDNode *CN =
7107 cast<ConstantSDNode>(OtherUses[i]->getOperand(OffsetIdx));
7108 APInt CNV = CN->getAPIntValue();
7109 if (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1)
7114 SDValue NewOp1 = Result.getValue(isLoad ? 1 : 0);
7115 SDValue NewOp2 = DAG.getConstant(CNV, CN->getValueType(0));
7117 std::swap(NewOp1, NewOp2);
7119 SDValue NewUse = DAG.getNode(OtherUses[i]->getOpcode(),
7120 OtherUses[i]->getDebugLoc(),
7121 OtherUses[i]->getValueType(0), NewOp1, NewOp2);
7122 DAG.ReplaceAllUsesOfValueWith(SDValue(OtherUses[i], 0), NewUse);
7123 removeFromWorkList(OtherUses[i]);
7124 DAG.DeleteNode(OtherUses[i]);
7127 // Replace the uses of Ptr with uses of the updated base value.
7128 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0));
7129 removeFromWorkList(Ptr.getNode());
7130 DAG.DeleteNode(Ptr.getNode());
7135 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
7136 /// add / sub of the base pointer node into a post-indexed load / store.
7137 /// The transformation folded the add / subtract into the new indexed
7138 /// load / store effectively and all of its uses are redirected to the
7139 /// new load / store.
7140 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
7141 if (Level < AfterLegalizeDAG)
7147 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7148 if (LD->isIndexed())
7150 VT = LD->getMemoryVT();
7151 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
7152 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
7154 Ptr = LD->getBasePtr();
7155 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7156 if (ST->isIndexed())
7158 VT = ST->getMemoryVT();
7159 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
7160 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
7162 Ptr = ST->getBasePtr();
7168 if (Ptr.getNode()->hasOneUse())
7171 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
7172 E = Ptr.getNode()->use_end(); I != E; ++I) {
7175 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
7180 ISD::MemIndexedMode AM = ISD::UNINDEXED;
7181 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
7182 // Don't create a indexed load / store with zero offset.
7183 if (isa<ConstantSDNode>(Offset) &&
7184 cast<ConstantSDNode>(Offset)->isNullValue())
7187 // Try turning it into a post-indexed load / store except when
7188 // 1) All uses are load / store ops that use it as base ptr (and
7189 // it may be folded as addressing mmode).
7190 // 2) Op must be independent of N, i.e. Op is neither a predecessor
7191 // nor a successor of N. Otherwise, if Op is folded that would
7194 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
7198 bool TryNext = false;
7199 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
7200 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
7202 if (Use == Ptr.getNode())
7205 // If all the uses are load / store addresses, then don't do the
7207 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
7208 bool RealUse = false;
7209 for (SDNode::use_iterator III = Use->use_begin(),
7210 EEE = Use->use_end(); III != EEE; ++III) {
7211 SDNode *UseUse = *III;
7212 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI))
7227 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
7228 SDValue Result = isLoad
7229 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
7230 BasePtr, Offset, AM)
7231 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
7232 BasePtr, Offset, AM);
7235 DEBUG(dbgs() << "\nReplacing.5 ";
7237 dbgs() << "\nWith: ";
7238 Result.getNode()->dump(&DAG);
7240 WorkListRemover DeadNodes(*this);
7242 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
7243 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
7245 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
7248 // Finally, since the node is now dead, remove it from the graph.
7251 // Replace the uses of Use with uses of the updated base value.
7252 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
7253 Result.getValue(isLoad ? 1 : 0));
7254 removeFromWorkList(Op);
7264 SDValue DAGCombiner::visitLOAD(SDNode *N) {
7265 LoadSDNode *LD = cast<LoadSDNode>(N);
7266 SDValue Chain = LD->getChain();
7267 SDValue Ptr = LD->getBasePtr();
7269 // If load is not volatile and there are no uses of the loaded value (and
7270 // the updated indexed value in case of indexed loads), change uses of the
7271 // chain value into uses of the chain input (i.e. delete the dead load).
7272 if (!LD->isVolatile()) {
7273 if (N->getValueType(1) == MVT::Other) {
7275 if (!N->hasAnyUseOfValue(0)) {
7276 // It's not safe to use the two value CombineTo variant here. e.g.
7277 // v1, chain2 = load chain1, loc
7278 // v2, chain3 = load chain2, loc
7280 // Now we replace use of chain2 with chain1. This makes the second load
7281 // isomorphic to the one we are deleting, and thus makes this load live.
7282 DEBUG(dbgs() << "\nReplacing.6 ";
7284 dbgs() << "\nWith chain: ";
7285 Chain.getNode()->dump(&DAG);
7287 WorkListRemover DeadNodes(*this);
7288 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
7290 if (N->use_empty()) {
7291 removeFromWorkList(N);
7295 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7299 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
7300 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) {
7301 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
7302 DEBUG(dbgs() << "\nReplacing.7 ";
7304 dbgs() << "\nWith: ";
7305 Undef.getNode()->dump(&DAG);
7306 dbgs() << " and 2 other values\n");
7307 WorkListRemover DeadNodes(*this);
7308 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef);
7309 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
7310 DAG.getUNDEF(N->getValueType(1)));
7311 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain);
7312 removeFromWorkList(N);
7314 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7319 // If this load is directly stored, replace the load value with the stored
7321 // TODO: Handle store large -> read small portion.
7322 // TODO: Handle TRUNCSTORE/LOADEXT
7323 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
7324 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
7325 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
7326 if (PrevST->getBasePtr() == Ptr &&
7327 PrevST->getValue().getValueType() == N->getValueType(0))
7328 return CombineTo(N, Chain.getOperand(1), Chain);
7332 // Try to infer better alignment information than the load already has.
7333 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
7334 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
7335 if (Align > LD->getMemOperand()->getBaseAlignment()) {
7337 DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
7338 LD->getValueType(0),
7339 Chain, Ptr, LD->getPointerInfo(),
7341 LD->isVolatile(), LD->isNonTemporal(), Align);
7342 return CombineTo(N, NewLoad, SDValue(NewLoad.getNode(), 1), true);
7348 // Walk up chain skipping non-aliasing memory nodes.
7349 SDValue BetterChain = FindBetterChain(N, Chain);
7351 // If there is a better chain.
7352 if (Chain != BetterChain) {
7355 // Replace the chain to void dependency.
7356 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
7357 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
7358 BetterChain, Ptr, LD->getPointerInfo(),
7359 LD->isVolatile(), LD->isNonTemporal(),
7360 LD->isInvariant(), LD->getAlignment());
7362 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
7363 LD->getValueType(0),
7364 BetterChain, Ptr, LD->getPointerInfo(),
7367 LD->isNonTemporal(),
7368 LD->getAlignment());
7371 // Create token factor to keep old chain connected.
7372 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
7373 MVT::Other, Chain, ReplLoad.getValue(1));
7375 // Make sure the new and old chains are cleaned up.
7376 AddToWorkList(Token.getNode());
7378 // Replace uses with load result and token factor. Don't add users
7380 return CombineTo(N, ReplLoad.getValue(0), Token, false);
7384 // Try transforming N to an indexed load.
7385 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
7386 return SDValue(N, 0);
7391 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
7392 /// load is having specific bytes cleared out. If so, return the byte size
7393 /// being masked out and the shift amount.
7394 static std::pair<unsigned, unsigned>
7395 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
7396 std::pair<unsigned, unsigned> Result(0, 0);
7398 // Check for the structure we're looking for.
7399 if (V->getOpcode() != ISD::AND ||
7400 !isa<ConstantSDNode>(V->getOperand(1)) ||
7401 !ISD::isNormalLoad(V->getOperand(0).getNode()))
7404 // Check the chain and pointer.
7405 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
7406 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
7408 // The store should be chained directly to the load or be an operand of a
7410 if (LD == Chain.getNode())
7412 else if (Chain->getOpcode() != ISD::TokenFactor)
7413 return Result; // Fail.
7416 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
7417 if (Chain->getOperand(i).getNode() == LD) {
7421 if (!isOk) return Result;
7424 // This only handles simple types.
7425 if (V.getValueType() != MVT::i16 &&
7426 V.getValueType() != MVT::i32 &&
7427 V.getValueType() != MVT::i64)
7430 // Check the constant mask. Invert it so that the bits being masked out are
7431 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
7432 // follow the sign bit for uniformity.
7433 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
7434 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask);
7435 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
7436 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask);
7437 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
7438 if (NotMaskLZ == 64) return Result; // All zero mask.
7440 // See if we have a continuous run of bits. If so, we have 0*1+0*
7441 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
7444 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
7445 if (V.getValueType() != MVT::i64 && NotMaskLZ)
7446 NotMaskLZ -= 64-V.getValueSizeInBits();
7448 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
7449 switch (MaskedBytes) {
7453 default: return Result; // All one mask, or 5-byte mask.
7456 // Verify that the first bit starts at a multiple of mask so that the access
7457 // is aligned the same as the access width.
7458 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
7460 Result.first = MaskedBytes;
7461 Result.second = NotMaskTZ/8;
7466 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
7467 /// provides a value as specified by MaskInfo. If so, replace the specified
7468 /// store with a narrower store of truncated IVal.
7470 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
7471 SDValue IVal, StoreSDNode *St,
7473 unsigned NumBytes = MaskInfo.first;
7474 unsigned ByteShift = MaskInfo.second;
7475 SelectionDAG &DAG = DC->getDAG();
7477 // Check to see if IVal is all zeros in the part being masked in by the 'or'
7478 // that uses this. If not, this is not a replacement.
7479 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
7480 ByteShift*8, (ByteShift+NumBytes)*8);
7481 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
7483 // Check that it is legal on the target to do this. It is legal if the new
7484 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
7486 MVT VT = MVT::getIntegerVT(NumBytes*8);
7487 if (!DC->isTypeLegal(VT))
7490 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
7491 // shifted by ByteShift and truncated down to NumBytes.
7493 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
7494 DAG.getConstant(ByteShift*8,
7495 DC->getShiftAmountTy(IVal.getValueType())));
7497 // Figure out the offset for the store and the alignment of the access.
7499 unsigned NewAlign = St->getAlignment();
7501 if (DAG.getTargetLoweringInfo().isLittleEndian())
7502 StOffset = ByteShift;
7504 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
7506 SDValue Ptr = St->getBasePtr();
7508 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
7509 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
7510 NewAlign = MinAlign(NewAlign, StOffset);
7513 // Truncate down to the new size.
7514 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
7517 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr,
7518 St->getPointerInfo().getWithOffset(StOffset),
7519 false, false, NewAlign).getNode();
7523 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
7524 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
7525 /// of the loaded bits, try narrowing the load and store if it would end up
7526 /// being a win for performance or code size.
7527 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
7528 StoreSDNode *ST = cast<StoreSDNode>(N);
7529 if (ST->isVolatile())
7532 SDValue Chain = ST->getChain();
7533 SDValue Value = ST->getValue();
7534 SDValue Ptr = ST->getBasePtr();
7535 EVT VT = Value.getValueType();
7537 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
7540 unsigned Opc = Value.getOpcode();
7542 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
7543 // is a byte mask indicating a consecutive number of bytes, check to see if
7544 // Y is known to provide just those bytes. If so, we try to replace the
7545 // load + replace + store sequence with a single (narrower) store, which makes
7547 if (Opc == ISD::OR) {
7548 std::pair<unsigned, unsigned> MaskedLoad;
7549 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
7550 if (MaskedLoad.first)
7551 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
7552 Value.getOperand(1), ST,this))
7553 return SDValue(NewST, 0);
7555 // Or is commutative, so try swapping X and Y.
7556 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
7557 if (MaskedLoad.first)
7558 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
7559 Value.getOperand(0), ST,this))
7560 return SDValue(NewST, 0);
7563 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
7564 Value.getOperand(1).getOpcode() != ISD::Constant)
7567 SDValue N0 = Value.getOperand(0);
7568 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7569 Chain == SDValue(N0.getNode(), 1)) {
7570 LoadSDNode *LD = cast<LoadSDNode>(N0);
7571 if (LD->getBasePtr() != Ptr ||
7572 LD->getPointerInfo().getAddrSpace() !=
7573 ST->getPointerInfo().getAddrSpace())
7576 // Find the type to narrow it the load / op / store to.
7577 SDValue N1 = Value.getOperand(1);
7578 unsigned BitWidth = N1.getValueSizeInBits();
7579 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
7580 if (Opc == ISD::AND)
7581 Imm ^= APInt::getAllOnesValue(BitWidth);
7582 if (Imm == 0 || Imm.isAllOnesValue())
7584 unsigned ShAmt = Imm.countTrailingZeros();
7585 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
7586 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
7587 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
7588 while (NewBW < BitWidth &&
7589 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
7590 TLI.isNarrowingProfitable(VT, NewVT))) {
7591 NewBW = NextPowerOf2(NewBW);
7592 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
7594 if (NewBW >= BitWidth)
7597 // If the lsb changed does not start at the type bitwidth boundary,
7598 // start at the previous one.
7600 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
7601 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt,
7602 std::min(BitWidth, ShAmt + NewBW));
7603 if ((Imm & Mask) == Imm) {
7604 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
7605 if (Opc == ISD::AND)
7606 NewImm ^= APInt::getAllOnesValue(NewBW);
7607 uint64_t PtrOff = ShAmt / 8;
7608 // For big endian targets, we need to adjust the offset to the pointer to
7609 // load the correct bytes.
7610 if (TLI.isBigEndian())
7611 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
7613 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
7614 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
7615 if (NewAlign < TLI.getDataLayout()->getABITypeAlignment(NewVTTy))
7618 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
7619 Ptr.getValueType(), Ptr,
7620 DAG.getConstant(PtrOff, Ptr.getValueType()));
7621 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
7622 LD->getChain(), NewPtr,
7623 LD->getPointerInfo().getWithOffset(PtrOff),
7624 LD->isVolatile(), LD->isNonTemporal(),
7625 LD->isInvariant(), NewAlign);
7626 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
7627 DAG.getConstant(NewImm, NewVT));
7628 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
7630 ST->getPointerInfo().getWithOffset(PtrOff),
7631 false, false, NewAlign);
7633 AddToWorkList(NewPtr.getNode());
7634 AddToWorkList(NewLD.getNode());
7635 AddToWorkList(NewVal.getNode());
7636 WorkListRemover DeadNodes(*this);
7637 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1));
7646 /// TransformFPLoadStorePair - For a given floating point load / store pair,
7647 /// if the load value isn't used by any other operations, then consider
7648 /// transforming the pair to integer load / store operations if the target
7649 /// deems the transformation profitable.
7650 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
7651 StoreSDNode *ST = cast<StoreSDNode>(N);
7652 SDValue Chain = ST->getChain();
7653 SDValue Value = ST->getValue();
7654 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
7655 Value.hasOneUse() &&
7656 Chain == SDValue(Value.getNode(), 1)) {
7657 LoadSDNode *LD = cast<LoadSDNode>(Value);
7658 EVT VT = LD->getMemoryVT();
7659 if (!VT.isFloatingPoint() ||
7660 VT != ST->getMemoryVT() ||
7661 LD->isNonTemporal() ||
7662 ST->isNonTemporal() ||
7663 LD->getPointerInfo().getAddrSpace() != 0 ||
7664 ST->getPointerInfo().getAddrSpace() != 0)
7667 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
7668 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
7669 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
7670 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
7671 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
7674 unsigned LDAlign = LD->getAlignment();
7675 unsigned STAlign = ST->getAlignment();
7676 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
7677 unsigned ABIAlign = TLI.getDataLayout()->getABITypeAlignment(IntVTTy);
7678 if (LDAlign < ABIAlign || STAlign < ABIAlign)
7681 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(),
7682 LD->getChain(), LD->getBasePtr(),
7683 LD->getPointerInfo(),
7684 false, false, false, LDAlign);
7686 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(),
7687 NewLD, ST->getBasePtr(),
7688 ST->getPointerInfo(),
7689 false, false, STAlign);
7691 AddToWorkList(NewLD.getNode());
7692 AddToWorkList(NewST.getNode());
7693 WorkListRemover DeadNodes(*this);
7694 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1));
7702 /// Returns the base pointer and an integer offset from that object.
7703 static std::pair<SDValue, int64_t> GetPointerBaseAndOffset(SDValue Ptr) {
7704 if (Ptr->getOpcode() == ISD::ADD && isa<ConstantSDNode>(Ptr->getOperand(1))) {
7705 int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue();
7706 SDValue Base = Ptr->getOperand(0);
7707 return std::make_pair(Base, Offset);
7710 return std::make_pair(Ptr, 0);
7713 /// Holds a pointer to an LSBaseSDNode as well as information on where it
7714 /// is located in a sequence of memory operations connected by a chain.
7716 MemOpLink (LSBaseSDNode *N, int64_t Offset, unsigned Seq):
7717 MemNode(N), OffsetFromBase(Offset), SequenceNum(Seq) { }
7718 // Ptr to the mem node.
7719 LSBaseSDNode *MemNode;
7720 // Offset from the base ptr.
7721 int64_t OffsetFromBase;
7722 // What is the sequence number of this mem node.
7723 // Lowest mem operand in the DAG starts at zero.
7724 unsigned SequenceNum;
7727 /// Sorts store nodes in a link according to their offset from a shared
7729 struct ConsecutiveMemoryChainSorter {
7730 bool operator()(MemOpLink LHS, MemOpLink RHS) {
7731 return LHS.OffsetFromBase < RHS.OffsetFromBase;
7735 bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
7736 EVT MemVT = St->getMemoryVT();
7737 int64_t ElementSizeBytes = MemVT.getSizeInBits()/8;
7738 bool NoVectors = DAG.getMachineFunction().getFunction()->getAttributes().
7739 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
7741 // Don't merge vectors into wider inputs.
7742 if (MemVT.isVector() || !MemVT.isSimple())
7745 // Perform an early exit check. Do not bother looking at stored values that
7746 // are not constants or loads.
7747 SDValue StoredVal = St->getValue();
7748 bool IsLoadSrc = isa<LoadSDNode>(StoredVal);
7749 if (!isa<ConstantSDNode>(StoredVal) && !isa<ConstantFPSDNode>(StoredVal) &&
7753 // Only look at ends of store sequences.
7754 SDValue Chain = SDValue(St, 1);
7755 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE)
7758 // This holds the base pointer and the offset in bytes from the base pointer.
7759 std::pair<SDValue, int64_t> BasePtr =
7760 GetPointerBaseAndOffset(St->getBasePtr());
7762 // We must have a base and an offset.
7763 if (!BasePtr.first.getNode())
7766 // Do not handle stores to undef base pointers.
7767 if (BasePtr.first.getOpcode() == ISD::UNDEF)
7770 // Save the LoadSDNodes that we find in the chain.
7771 // We need to make sure that these nodes do not interfere with
7772 // any of the store nodes.
7773 SmallVector<LSBaseSDNode*, 8> AliasLoadNodes;
7775 // Save the StoreSDNodes that we find in the chain.
7776 SmallVector<MemOpLink, 8> StoreNodes;
7778 // Walk up the chain and look for nodes with offsets from the same
7779 // base pointer. Stop when reaching an instruction with a different kind
7780 // or instruction which has a different base pointer.
7782 StoreSDNode *Index = St;
7784 // If the chain has more than one use, then we can't reorder the mem ops.
7785 if (Index != St && !SDValue(Index, 1)->hasOneUse())
7788 // Find the base pointer and offset for this memory node.
7789 std::pair<SDValue, int64_t> Ptr =
7790 GetPointerBaseAndOffset(Index->getBasePtr());
7792 // Check that the base pointer is the same as the original one.
7793 if (Ptr.first.getNode() != BasePtr.first.getNode())
7796 // Check that the alignment is the same.
7797 if (Index->getAlignment() != St->getAlignment())
7800 // The memory operands must not be volatile.
7801 if (Index->isVolatile() || Index->isIndexed())
7805 if (StoreSDNode *St = dyn_cast<StoreSDNode>(Index))
7806 if (St->isTruncatingStore())
7809 // The stored memory type must be the same.
7810 if (Index->getMemoryVT() != MemVT)
7813 // We do not allow unaligned stores because we want to prevent overriding
7815 if (Index->getAlignment()*8 != MemVT.getSizeInBits())
7818 // We found a potential memory operand to merge.
7819 StoreNodes.push_back(MemOpLink(Index, Ptr.second, Seq++));
7821 // Find the next memory operand in the chain. If the next operand in the
7822 // chain is a store then move up and continue the scan with the next
7823 // memory operand. If the next operand is a load save it and use alias
7824 // information to check if it interferes with anything.
7825 SDNode *NextInChain = Index->getChain().getNode();
7827 if (StoreSDNode *STn = dyn_cast<StoreSDNode>(NextInChain)) {
7828 // We found a store node. Use it for the next iteration.
7831 } else if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(NextInChain)) {
7832 // Save the load node for later. Continue the scan.
7833 AliasLoadNodes.push_back(Ldn);
7834 NextInChain = Ldn->getChain().getNode();
7843 // Check if there is anything to merge.
7844 if (StoreNodes.size() < 2)
7847 // Sort the memory operands according to their distance from the base pointer.
7848 std::sort(StoreNodes.begin(), StoreNodes.end(),
7849 ConsecutiveMemoryChainSorter());
7851 // Scan the memory operations on the chain and find the first non-consecutive
7852 // store memory address.
7853 unsigned LastConsecutiveStore = 0;
7854 int64_t StartAddress = StoreNodes[0].OffsetFromBase;
7855 for (unsigned i = 0, e = StoreNodes.size(); i < e; ++i) {
7857 // Check that the addresses are consecutive starting from the second
7858 // element in the list of stores.
7860 int64_t CurrAddress = StoreNodes[i].OffsetFromBase;
7861 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
7866 // Check if this store interferes with any of the loads that we found.
7867 for (unsigned ld = 0, lde = AliasLoadNodes.size(); ld < lde; ++ld)
7868 if (isAlias(AliasLoadNodes[ld], StoreNodes[i].MemNode)) {
7872 // We found a load that alias with this store. Stop the sequence.
7876 // Mark this node as useful.
7877 LastConsecutiveStore = i;
7880 // The node with the lowest store address.
7881 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;
7883 // Store the constants into memory as one consecutive store.
7885 unsigned LastLegalType = 0;
7886 unsigned LastLegalVectorType = 0;
7887 bool NonZero = false;
7888 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
7889 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
7890 SDValue StoredVal = St->getValue();
7892 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(StoredVal)) {
7893 NonZero |= !C->isNullValue();
7894 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) {
7895 NonZero |= !C->getConstantFPValue()->isNullValue();
7901 // Find a legal type for the constant store.
7902 unsigned StoreBW = (i+1) * ElementSizeBytes * 8;
7903 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
7904 if (TLI.isTypeLegal(StoreTy))
7905 LastLegalType = i+1;
7907 // Find a legal type for the vector store.
7908 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
7909 if (TLI.isTypeLegal(Ty))
7910 LastLegalVectorType = i + 1;
7913 // We only use vectors if the constant is known to be zero and the
7914 // function is not marked with the noimplicitfloat attribute.
7915 if (NonZero || NoVectors)
7916 LastLegalVectorType = 0;
7918 // Check if we found a legal integer type to store.
7919 if (LastLegalType == 0 && LastLegalVectorType == 0)
7922 bool UseVector = (LastLegalVectorType > LastLegalType) && !NoVectors;
7923 unsigned NumElem = UseVector ? LastLegalVectorType : LastLegalType;
7925 // Make sure we have something to merge.
7929 unsigned EarliestNodeUsed = 0;
7930 for (unsigned i=0; i < NumElem; ++i) {
7931 // Find a chain for the new wide-store operand. Notice that some
7932 // of the store nodes that we found may not be selected for inclusion
7933 // in the wide store. The chain we use needs to be the chain of the
7934 // earliest store node which is *used* and replaced by the wide store.
7935 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum)
7936 EarliestNodeUsed = i;
7939 // The earliest Node in the DAG.
7940 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode;
7941 DebugLoc DL = StoreNodes[0].MemNode->getDebugLoc();
7945 // Find a legal type for the vector store.
7946 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
7947 assert(TLI.isTypeLegal(Ty) && "Illegal vector store");
7948 StoredVal = DAG.getConstant(0, Ty);
7950 unsigned StoreBW = NumElem * ElementSizeBytes * 8;
7951 APInt StoreInt(StoreBW, 0);
7953 // Construct a single integer constant which is made of the smaller
7955 bool IsLE = TLI.isLittleEndian();
7956 for (unsigned i = 0; i < NumElem ; ++i) {
7957 unsigned Idx = IsLE ?(NumElem - 1 - i) : i;
7958 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[Idx].MemNode);
7959 SDValue Val = St->getValue();
7960 StoreInt<<=ElementSizeBytes*8;
7961 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val)) {
7962 StoreInt|=C->getAPIntValue().zext(StoreBW);
7963 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) {
7964 StoreInt|= C->getValueAPF().bitcastToAPInt().zext(StoreBW);
7966 assert(false && "Invalid constant element type");
7970 // Create the new Load and Store operations.
7971 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
7972 StoredVal = DAG.getConstant(StoreInt, StoreTy);
7975 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), DL, StoredVal,
7976 FirstInChain->getBasePtr(),
7977 FirstInChain->getPointerInfo(),
7979 FirstInChain->getAlignment());
7981 // Replace the first store with the new store
7982 CombineTo(EarliestOp, NewStore);
7983 // Erase all other stores.
7984 for (unsigned i = 0; i < NumElem ; ++i) {
7985 if (StoreNodes[i].MemNode == EarliestOp)
7987 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
7988 // ReplaceAllUsesWith will replace all uses that existed when it was
7989 // called, but graph optimizations may cause new ones to appear. For
7990 // example, the case in pr14333 looks like
7992 // St's chain -> St -> another store -> X
7994 // And the only difference from St to the other store is the chain.
7995 // When we change it's chain to be St's chain they become identical,
7996 // get CSEed and the net result is that X is now a use of St.
7997 // Since we know that St is redundant, just iterate.
7998 while (!St->use_empty())
7999 DAG.ReplaceAllUsesWith(SDValue(St, 0), St->getChain());
8000 removeFromWorkList(St);
8007 // Below we handle the case of multiple consecutive stores that
8008 // come from multiple consecutive loads. We merge them into a single
8009 // wide load and a single wide store.
8011 // Look for load nodes which are used by the stored values.
8012 SmallVector<MemOpLink, 8> LoadNodes;
8014 // Find acceptable loads. Loads need to have the same chain (token factor),
8015 // must not be zext, volatile, indexed, and they must be consecutive.
8017 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
8018 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
8019 LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue());
8022 // Loads must only have one use.
8023 if (!Ld->hasNUsesOfValue(1, 0))
8026 // Check that the alignment is the same as the stores.
8027 if (Ld->getAlignment() != St->getAlignment())
8030 // The memory operands must not be volatile.
8031 if (Ld->isVolatile() || Ld->isIndexed())
8034 // We do not accept ext loads.
8035 if (Ld->getExtensionType() != ISD::NON_EXTLOAD)
8038 // The stored memory type must be the same.
8039 if (Ld->getMemoryVT() != MemVT)
8042 std::pair<SDValue, int64_t> LdPtr =
8043 GetPointerBaseAndOffset(Ld->getBasePtr());
8045 // If this is not the first ptr that we check.
8046 if (LdBasePtr.getNode()) {
8047 // The base ptr must be the same.
8048 if (LdPtr.first != LdBasePtr)
8051 // Check that all other base pointers are the same as this one.
8052 LdBasePtr = LdPtr.first;
8055 // We found a potential memory operand to merge.
8056 LoadNodes.push_back(MemOpLink(Ld, LdPtr.second, 0));
8059 if (LoadNodes.size() < 2)
8062 // Scan the memory operations on the chain and find the first non-consecutive
8063 // load memory address. These variables hold the index in the store node
8065 unsigned LastConsecutiveLoad = 0;
8066 // This variable refers to the size and not index in the array.
8067 unsigned LastLegalVectorType = 0;
8068 unsigned LastLegalIntegerType = 0;
8069 StartAddress = LoadNodes[0].OffsetFromBase;
8070 SDValue FirstChain = LoadNodes[0].MemNode->getChain();
8071 for (unsigned i = 1; i < LoadNodes.size(); ++i) {
8072 // All loads much share the same chain.
8073 if (LoadNodes[i].MemNode->getChain() != FirstChain)
8076 int64_t CurrAddress = LoadNodes[i].OffsetFromBase;
8077 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
8079 LastConsecutiveLoad = i;
8081 // Find a legal type for the vector store.
8082 EVT StoreTy = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
8083 if (TLI.isTypeLegal(StoreTy))
8084 LastLegalVectorType = i + 1;
8086 // Find a legal type for the integer store.
8087 unsigned StoreBW = (i+1) * ElementSizeBytes * 8;
8088 StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
8089 if (TLI.isTypeLegal(StoreTy))
8090 LastLegalIntegerType = i + 1;
8093 // Only use vector types if the vector type is larger than the integer type.
8094 // If they are the same, use integers.
8095 bool UseVectorTy = LastLegalVectorType > LastLegalIntegerType && !NoVectors;
8096 unsigned LastLegalType = std::max(LastLegalVectorType, LastLegalIntegerType);
8098 // We add +1 here because the LastXXX variables refer to location while
8099 // the NumElem refers to array/index size.
8100 unsigned NumElem = std::min(LastConsecutiveStore, LastConsecutiveLoad) + 1;
8101 NumElem = std::min(LastLegalType, NumElem);
8106 // The earliest Node in the DAG.
8107 unsigned EarliestNodeUsed = 0;
8108 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode;
8109 for (unsigned i=1; i<NumElem; ++i) {
8110 // Find a chain for the new wide-store operand. Notice that some
8111 // of the store nodes that we found may not be selected for inclusion
8112 // in the wide store. The chain we use needs to be the chain of the
8113 // earliest store node which is *used* and replaced by the wide store.
8114 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum)
8115 EarliestNodeUsed = i;
8118 // Find if it is better to use vectors or integers to load and store
8122 JointMemOpVT = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
8124 unsigned StoreBW = NumElem * ElementSizeBytes * 8;
8125 JointMemOpVT = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
8128 DebugLoc LoadDL = LoadNodes[0].MemNode->getDebugLoc();
8129 DebugLoc StoreDL = StoreNodes[0].MemNode->getDebugLoc();
8131 LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode);
8132 SDValue NewLoad = DAG.getLoad(JointMemOpVT, LoadDL,
8133 FirstLoad->getChain(),
8134 FirstLoad->getBasePtr(),
8135 FirstLoad->getPointerInfo(),
8136 false, false, false,
8137 FirstLoad->getAlignment());
8139 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), StoreDL, NewLoad,
8140 FirstInChain->getBasePtr(),
8141 FirstInChain->getPointerInfo(), false, false,
8142 FirstInChain->getAlignment());
8144 // Replace one of the loads with the new load.
8145 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[0].MemNode);
8146 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1),
8147 SDValue(NewLoad.getNode(), 1));
8149 // Remove the rest of the load chains.
8150 for (unsigned i = 1; i < NumElem ; ++i) {
8151 // Replace all chain users of the old load nodes with the chain of the new
8153 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[i].MemNode);
8154 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Ld->getChain());
8157 // Replace the first store with the new store.
8158 CombineTo(EarliestOp, NewStore);
8159 // Erase all other stores.
8160 for (unsigned i = 0; i < NumElem ; ++i) {
8161 // Remove all Store nodes.
8162 if (StoreNodes[i].MemNode == EarliestOp)
8164 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
8165 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain());
8166 removeFromWorkList(St);
8173 SDValue DAGCombiner::visitSTORE(SDNode *N) {
8174 StoreSDNode *ST = cast<StoreSDNode>(N);
8175 SDValue Chain = ST->getChain();
8176 SDValue Value = ST->getValue();
8177 SDValue Ptr = ST->getBasePtr();
8179 // If this is a store of a bit convert, store the input value if the
8180 // resultant store does not need a higher alignment than the original.
8181 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
8182 ST->isUnindexed()) {
8183 unsigned OrigAlign = ST->getAlignment();
8184 EVT SVT = Value.getOperand(0).getValueType();
8185 unsigned Align = TLI.getDataLayout()->
8186 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
8187 if (Align <= OrigAlign &&
8188 ((!LegalOperations && !ST->isVolatile()) ||
8189 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
8190 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
8191 Ptr, ST->getPointerInfo(), ST->isVolatile(),
8192 ST->isNonTemporal(), OrigAlign);
8195 // Turn 'store undef, Ptr' -> nothing.
8196 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
8199 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
8200 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
8201 // NOTE: If the original store is volatile, this transform must not increase
8202 // the number of stores. For example, on x86-32 an f64 can be stored in one
8203 // processor operation but an i64 (which is not legal) requires two. So the
8204 // transform should not be done in this case.
8205 if (Value.getOpcode() != ISD::TargetConstantFP) {
8207 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
8208 default: llvm_unreachable("Unknown FP type");
8209 case MVT::f16: // We don't do this for these yet.
8215 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
8216 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
8217 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
8218 bitcastToAPInt().getZExtValue(), MVT::i32);
8219 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
8220 Ptr, ST->getPointerInfo(), ST->isVolatile(),
8221 ST->isNonTemporal(), ST->getAlignment());
8225 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
8226 !ST->isVolatile()) ||
8227 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
8228 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
8229 getZExtValue(), MVT::i64);
8230 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
8231 Ptr, ST->getPointerInfo(), ST->isVolatile(),
8232 ST->isNonTemporal(), ST->getAlignment());
8235 if (!ST->isVolatile() &&
8236 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
8237 // Many FP stores are not made apparent until after legalize, e.g. for
8238 // argument passing. Since this is so common, custom legalize the
8239 // 64-bit integer store into two 32-bit stores.
8240 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
8241 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
8242 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
8243 if (TLI.isBigEndian()) std::swap(Lo, Hi);
8245 unsigned Alignment = ST->getAlignment();
8246 bool isVolatile = ST->isVolatile();
8247 bool isNonTemporal = ST->isNonTemporal();
8249 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
8250 Ptr, ST->getPointerInfo(),
8251 isVolatile, isNonTemporal,
8252 ST->getAlignment());
8253 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
8254 DAG.getConstant(4, Ptr.getValueType()));
8255 Alignment = MinAlign(Alignment, 4U);
8256 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
8257 Ptr, ST->getPointerInfo().getWithOffset(4),
8258 isVolatile, isNonTemporal,
8260 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
8269 // Try to infer better alignment information than the store already has.
8270 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
8271 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
8272 if (Align > ST->getAlignment())
8273 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
8274 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
8275 ST->isVolatile(), ST->isNonTemporal(), Align);
8279 // Try transforming a pair floating point load / store ops to integer
8280 // load / store ops.
8281 SDValue NewST = TransformFPLoadStorePair(N);
8282 if (NewST.getNode())
8286 // Walk up chain skipping non-aliasing memory nodes.
8287 SDValue BetterChain = FindBetterChain(N, Chain);
8289 // If there is a better chain.
8290 if (Chain != BetterChain) {
8293 // Replace the chain to avoid dependency.
8294 if (ST->isTruncatingStore()) {
8295 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
8296 ST->getPointerInfo(),
8297 ST->getMemoryVT(), ST->isVolatile(),
8298 ST->isNonTemporal(), ST->getAlignment());
8300 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
8301 ST->getPointerInfo(),
8302 ST->isVolatile(), ST->isNonTemporal(),
8303 ST->getAlignment());
8306 // Create token to keep both nodes around.
8307 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
8308 MVT::Other, Chain, ReplStore);
8310 // Make sure the new and old chains are cleaned up.
8311 AddToWorkList(Token.getNode());
8313 // Don't add users to work list.
8314 return CombineTo(N, Token, false);
8318 // Try transforming N to an indexed store.
8319 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
8320 return SDValue(N, 0);
8322 // FIXME: is there such a thing as a truncating indexed store?
8323 if (ST->isTruncatingStore() && ST->isUnindexed() &&
8324 Value.getValueType().isInteger()) {
8325 // See if we can simplify the input to this truncstore with knowledge that
8326 // only the low bits are being used. For example:
8327 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
8329 GetDemandedBits(Value,
8330 APInt::getLowBitsSet(
8331 Value.getValueType().getScalarType().getSizeInBits(),
8332 ST->getMemoryVT().getScalarType().getSizeInBits()));
8333 AddToWorkList(Value.getNode());
8334 if (Shorter.getNode())
8335 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
8336 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
8337 ST->isVolatile(), ST->isNonTemporal(),
8338 ST->getAlignment());
8340 // Otherwise, see if we can simplify the operation with
8341 // SimplifyDemandedBits, which only works if the value has a single use.
8342 if (SimplifyDemandedBits(Value,
8343 APInt::getLowBitsSet(
8344 Value.getValueType().getScalarType().getSizeInBits(),
8345 ST->getMemoryVT().getScalarType().getSizeInBits())))
8346 return SDValue(N, 0);
8349 // If this is a load followed by a store to the same location, then the store
8351 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
8352 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
8353 ST->isUnindexed() && !ST->isVolatile() &&
8354 // There can't be any side effects between the load and store, such as
8356 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
8357 // The store is dead, remove it.
8362 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
8363 // truncating store. We can do this even if this is already a truncstore.
8364 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
8365 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
8366 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
8367 ST->getMemoryVT())) {
8368 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
8369 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
8370 ST->isVolatile(), ST->isNonTemporal(),
8371 ST->getAlignment());
8374 // Only perform this optimization before the types are legal, because we
8375 // don't want to perform this optimization on every DAGCombine invocation.
8377 bool EverChanged = false;
8380 // There can be multiple store sequences on the same chain.
8381 // Keep trying to merge store sequences until we are unable to do so
8382 // or until we merge the last store on the chain.
8383 bool Changed = MergeConsecutiveStores(ST);
8384 EverChanged |= Changed;
8385 if (!Changed) break;
8386 } while (ST->getOpcode() != ISD::DELETED_NODE);
8389 return SDValue(N, 0);
8392 return ReduceLoadOpStoreWidth(N);
8395 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
8396 SDValue InVec = N->getOperand(0);
8397 SDValue InVal = N->getOperand(1);
8398 SDValue EltNo = N->getOperand(2);
8399 DebugLoc dl = N->getDebugLoc();
8401 // If the inserted element is an UNDEF, just use the input vector.
8402 if (InVal.getOpcode() == ISD::UNDEF)
8405 EVT VT = InVec.getValueType();
8407 // If we can't generate a legal BUILD_VECTOR, exit
8408 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
8411 // Check that we know which element is being inserted
8412 if (!isa<ConstantSDNode>(EltNo))
8414 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
8416 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
8417 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
8419 SmallVector<SDValue, 8> Ops;
8420 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
8421 Ops.append(InVec.getNode()->op_begin(),
8422 InVec.getNode()->op_end());
8423 } else if (InVec.getOpcode() == ISD::UNDEF) {
8424 unsigned NElts = VT.getVectorNumElements();
8425 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
8430 // Insert the element
8431 if (Elt < Ops.size()) {
8432 // All the operands of BUILD_VECTOR must have the same type;
8433 // we enforce that here.
8434 EVT OpVT = Ops[0].getValueType();
8435 if (InVal.getValueType() != OpVT)
8436 InVal = OpVT.bitsGT(InVal.getValueType()) ?
8437 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
8438 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
8442 // Return the new vector
8443 return DAG.getNode(ISD::BUILD_VECTOR, dl,
8444 VT, &Ops[0], Ops.size());
8447 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
8448 // (vextract (scalar_to_vector val, 0) -> val
8449 SDValue InVec = N->getOperand(0);
8450 EVT VT = InVec.getValueType();
8451 EVT NVT = N->getValueType(0);
8453 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
8454 // Check if the result type doesn't match the inserted element type. A
8455 // SCALAR_TO_VECTOR may truncate the inserted element and the
8456 // EXTRACT_VECTOR_ELT may widen the extracted vector.
8457 SDValue InOp = InVec.getOperand(0);
8458 if (InOp.getValueType() != NVT) {
8459 assert(InOp.getValueType().isInteger() && NVT.isInteger());
8460 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
8465 SDValue EltNo = N->getOperand(1);
8466 bool ConstEltNo = isa<ConstantSDNode>(EltNo);
8468 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
8469 // We only perform this optimization before the op legalization phase because
8470 // we may introduce new vector instructions which are not backed by TD
8471 // patterns. For example on AVX, extracting elements from a wide vector
8472 // without using extract_subvector.
8473 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
8474 && ConstEltNo && !LegalOperations) {
8475 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
8476 int NumElem = VT.getVectorNumElements();
8477 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
8478 // Find the new index to extract from.
8479 int OrigElt = SVOp->getMaskElt(Elt);
8481 // Extracting an undef index is undef.
8483 return DAG.getUNDEF(NVT);
8485 // Select the right vector half to extract from.
8486 if (OrigElt < NumElem) {
8487 InVec = InVec->getOperand(0);
8489 InVec = InVec->getOperand(1);
8493 EVT IndexTy = N->getOperand(1).getValueType();
8494 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT,
8495 InVec, DAG.getConstant(OrigElt, IndexTy));
8498 // Perform only after legalization to ensure build_vector / vector_shuffle
8499 // optimizations have already been done.
8500 if (!LegalOperations) return SDValue();
8502 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
8503 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
8504 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
8507 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
8508 bool NewLoad = false;
8509 bool BCNumEltsChanged = false;
8510 EVT ExtVT = VT.getVectorElementType();
8513 // If the result of load has to be truncated, then it's not necessarily
8515 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT))
8518 if (InVec.getOpcode() == ISD::BITCAST) {
8519 // Don't duplicate a load with other uses.
8520 if (!InVec.hasOneUse())
8523 EVT BCVT = InVec.getOperand(0).getValueType();
8524 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
8526 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
8527 BCNumEltsChanged = true;
8528 InVec = InVec.getOperand(0);
8529 ExtVT = BCVT.getVectorElementType();
8533 LoadSDNode *LN0 = NULL;
8534 const ShuffleVectorSDNode *SVN = NULL;
8535 if (ISD::isNormalLoad(InVec.getNode())) {
8536 LN0 = cast<LoadSDNode>(InVec);
8537 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
8538 InVec.getOperand(0).getValueType() == ExtVT &&
8539 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
8540 // Don't duplicate a load with other uses.
8541 if (!InVec.hasOneUse())
8544 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
8545 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
8546 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
8548 // (load $addr+1*size)
8550 // Don't duplicate a load with other uses.
8551 if (!InVec.hasOneUse())
8554 // If the bit convert changed the number of elements, it is unsafe
8555 // to examine the mask.
8556 if (BCNumEltsChanged)
8559 // Select the input vector, guarding against out of range extract vector.
8560 unsigned NumElems = VT.getVectorNumElements();
8561 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
8562 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
8564 if (InVec.getOpcode() == ISD::BITCAST) {
8565 // Don't duplicate a load with other uses.
8566 if (!InVec.hasOneUse())
8569 InVec = InVec.getOperand(0);
8571 if (ISD::isNormalLoad(InVec.getNode())) {
8572 LN0 = cast<LoadSDNode>(InVec);
8573 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
8577 // Make sure we found a non-volatile load and the extractelement is
8579 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
8582 // If Idx was -1 above, Elt is going to be -1, so just return undef.
8584 return DAG.getUNDEF(LVT);
8586 unsigned Align = LN0->getAlignment();
8588 // Check the resultant load doesn't need a higher alignment than the
8592 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
8594 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
8600 SDValue NewPtr = LN0->getBasePtr();
8601 unsigned PtrOff = 0;
8604 PtrOff = LVT.getSizeInBits() * Elt / 8;
8605 EVT PtrType = NewPtr.getValueType();
8606 if (TLI.isBigEndian())
8607 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
8608 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
8609 DAG.getConstant(PtrOff, PtrType));
8612 // The replacement we need to do here is a little tricky: we need to
8613 // replace an extractelement of a load with a load.
8614 // Use ReplaceAllUsesOfValuesWith to do the replacement.
8615 // Note that this replacement assumes that the extractvalue is the only
8616 // use of the load; that's okay because we don't want to perform this
8617 // transformation in other cases anyway.
8620 if (NVT.bitsGT(LVT)) {
8621 // If the result type of vextract is wider than the load, then issue an
8622 // extending load instead.
8623 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT)
8624 ? ISD::ZEXTLOAD : ISD::EXTLOAD;
8625 Load = DAG.getExtLoad(ExtType, N->getDebugLoc(), NVT, LN0->getChain(),
8626 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff),
8627 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align);
8628 Chain = Load.getValue(1);
8630 Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
8631 LN0->getPointerInfo().getWithOffset(PtrOff),
8632 LN0->isVolatile(), LN0->isNonTemporal(),
8633 LN0->isInvariant(), Align);
8634 Chain = Load.getValue(1);
8635 if (NVT.bitsLT(LVT))
8636 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load);
8638 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load);
8640 WorkListRemover DeadNodes(*this);
8641 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) };
8642 SDValue To[] = { Load, Chain };
8643 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
8644 // Since we're explcitly calling ReplaceAllUses, add the new node to the
8645 // worklist explicitly as well.
8646 AddToWorkList(Load.getNode());
8647 AddUsersToWorkList(Load.getNode()); // Add users too
8648 // Make sure to revisit this node to clean it up; it will usually be dead.
8650 return SDValue(N, 0);
8656 // Simplify (build_vec (ext )) to (bitcast (build_vec ))
8657 SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) {
8658 // We perform this optimization post type-legalization because
8659 // the type-legalizer often scalarizes integer-promoted vectors.
8660 // Performing this optimization before may create bit-casts which
8661 // will be type-legalized to complex code sequences.
8662 // We perform this optimization only before the operation legalizer because we
8663 // may introduce illegal operations.
8664 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes)
8667 unsigned NumInScalars = N->getNumOperands();
8668 DebugLoc dl = N->getDebugLoc();
8669 EVT VT = N->getValueType(0);
8671 // Check to see if this is a BUILD_VECTOR of a bunch of values
8672 // which come from any_extend or zero_extend nodes. If so, we can create
8673 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR
8674 // optimizations. We do not handle sign-extend because we can't fill the sign
8676 EVT SourceType = MVT::Other;
8677 bool AllAnyExt = true;
8679 for (unsigned i = 0; i != NumInScalars; ++i) {
8680 SDValue In = N->getOperand(i);
8681 // Ignore undef inputs.
8682 if (In.getOpcode() == ISD::UNDEF) continue;
8684 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
8685 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
8687 // Abort if the element is not an extension.
8688 if (!ZeroExt && !AnyExt) {
8689 SourceType = MVT::Other;
8693 // The input is a ZeroExt or AnyExt. Check the original type.
8694 EVT InTy = In.getOperand(0).getValueType();
8696 // Check that all of the widened source types are the same.
8697 if (SourceType == MVT::Other)
8700 else if (InTy != SourceType) {
8701 // Multiple income types. Abort.
8702 SourceType = MVT::Other;
8706 // Check if all of the extends are ANY_EXTENDs.
8707 AllAnyExt &= AnyExt;
8710 // In order to have valid types, all of the inputs must be extended from the
8711 // same source type and all of the inputs must be any or zero extend.
8712 // Scalar sizes must be a power of two.
8713 EVT OutScalarTy = VT.getScalarType();
8714 bool ValidTypes = SourceType != MVT::Other &&
8715 isPowerOf2_32(OutScalarTy.getSizeInBits()) &&
8716 isPowerOf2_32(SourceType.getSizeInBits());
8718 // Create a new simpler BUILD_VECTOR sequence which other optimizations can
8719 // turn into a single shuffle instruction.
8723 bool isLE = TLI.isLittleEndian();
8724 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits();
8725 assert(ElemRatio > 1 && "Invalid element size ratio");
8726 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType):
8727 DAG.getConstant(0, SourceType);
8729 unsigned NewBVElems = ElemRatio * VT.getVectorNumElements();
8730 SmallVector<SDValue, 8> Ops(NewBVElems, Filler);
8732 // Populate the new build_vector
8733 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
8734 SDValue Cast = N->getOperand(i);
8735 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
8736 Cast.getOpcode() == ISD::ZERO_EXTEND ||
8737 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
8739 if (Cast.getOpcode() == ISD::UNDEF)
8740 In = DAG.getUNDEF(SourceType);
8742 In = Cast->getOperand(0);
8743 unsigned Index = isLE ? (i * ElemRatio) :
8744 (i * ElemRatio + (ElemRatio - 1));
8746 assert(Index < Ops.size() && "Invalid index");
8750 // The type of the new BUILD_VECTOR node.
8751 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems);
8752 assert(VecVT.getSizeInBits() == VT.getSizeInBits() &&
8753 "Invalid vector size");
8754 // Check if the new vector type is legal.
8755 if (!isTypeLegal(VecVT)) return SDValue();
8757 // Make the new BUILD_VECTOR.
8758 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], Ops.size());
8760 // The new BUILD_VECTOR node has the potential to be further optimized.
8761 AddToWorkList(BV.getNode());
8762 // Bitcast to the desired type.
8763 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
8766 SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) {
8767 EVT VT = N->getValueType(0);
8769 unsigned NumInScalars = N->getNumOperands();
8770 DebugLoc dl = N->getDebugLoc();
8772 EVT SrcVT = MVT::Other;
8773 unsigned Opcode = ISD::DELETED_NODE;
8774 unsigned NumDefs = 0;
8776 for (unsigned i = 0; i != NumInScalars; ++i) {
8777 SDValue In = N->getOperand(i);
8778 unsigned Opc = In.getOpcode();
8780 if (Opc == ISD::UNDEF)
8783 // If all scalar values are floats and converted from integers.
8784 if (Opcode == ISD::DELETED_NODE &&
8785 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) {
8792 EVT InVT = In.getOperand(0).getValueType();
8794 // If all scalar values are typed differently, bail out. It's chosen to
8795 // simplify BUILD_VECTOR of integer types.
8796 if (SrcVT == MVT::Other)
8803 // If the vector has just one element defined, it's not worth to fold it into
8804 // a vectorized one.
8808 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP)
8809 && "Should only handle conversion from integer to float.");
8810 assert(SrcVT != MVT::Other && "Cannot determine source type!");
8812 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars);
8814 if (!TLI.isOperationLegalOrCustom(Opcode, NVT))
8817 SmallVector<SDValue, 8> Opnds;
8818 for (unsigned i = 0; i != NumInScalars; ++i) {
8819 SDValue In = N->getOperand(i);
8821 if (In.getOpcode() == ISD::UNDEF)
8822 Opnds.push_back(DAG.getUNDEF(SrcVT));
8824 Opnds.push_back(In.getOperand(0));
8826 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT,
8827 &Opnds[0], Opnds.size());
8828 AddToWorkList(BV.getNode());
8830 return DAG.getNode(Opcode, dl, VT, BV);
8833 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
8834 unsigned NumInScalars = N->getNumOperands();
8835 DebugLoc dl = N->getDebugLoc();
8836 EVT VT = N->getValueType(0);
8838 // A vector built entirely of undefs is undef.
8839 if (ISD::allOperandsUndef(N))
8840 return DAG.getUNDEF(VT);
8842 SDValue V = reduceBuildVecExtToExtBuildVec(N);
8846 V = reduceBuildVecConvertToConvertBuildVec(N);
8850 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
8851 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
8852 // at most two distinct vectors, turn this into a shuffle node.
8854 // May only combine to shuffle after legalize if shuffle is legal.
8855 if (LegalOperations &&
8856 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT))
8859 SDValue VecIn1, VecIn2;
8860 for (unsigned i = 0; i != NumInScalars; ++i) {
8861 // Ignore undef inputs.
8862 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
8864 // If this input is something other than a EXTRACT_VECTOR_ELT with a
8865 // constant index, bail out.
8866 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
8867 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
8868 VecIn1 = VecIn2 = SDValue(0, 0);
8872 // We allow up to two distinct input vectors.
8873 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
8874 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
8877 if (VecIn1.getNode() == 0) {
8878 VecIn1 = ExtractedFromVec;
8879 } else if (VecIn2.getNode() == 0) {
8880 VecIn2 = ExtractedFromVec;
8883 VecIn1 = VecIn2 = SDValue(0, 0);
8888 // If everything is good, we can make a shuffle operation.
8889 if (VecIn1.getNode()) {
8890 SmallVector<int, 8> Mask;
8891 for (unsigned i = 0; i != NumInScalars; ++i) {
8892 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
8897 // If extracting from the first vector, just use the index directly.
8898 SDValue Extract = N->getOperand(i);
8899 SDValue ExtVal = Extract.getOperand(1);
8900 if (Extract.getOperand(0) == VecIn1) {
8901 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
8902 if (ExtIndex > VT.getVectorNumElements())
8905 Mask.push_back(ExtIndex);
8909 // Otherwise, use InIdx + VecSize
8910 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
8911 Mask.push_back(Idx+NumInScalars);
8914 // We can't generate a shuffle node with mismatched input and output types.
8915 // Attempt to transform a single input vector to the correct type.
8916 if ((VT != VecIn1.getValueType())) {
8917 // We don't support shuffeling between TWO values of different types.
8918 if (VecIn2.getNode() != 0)
8921 // We only support widening of vectors which are half the size of the
8922 // output registers. For example XMM->YMM widening on X86 with AVX.
8923 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits())
8926 // If the input vector type has a different base type to the output
8927 // vector type, bail out.
8928 if (VecIn1.getValueType().getVectorElementType() !=
8929 VT.getVectorElementType())
8932 // Widen the input vector by adding undef values.
8933 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8934 VecIn1, DAG.getUNDEF(VecIn1.getValueType()));
8937 // If VecIn2 is unused then change it to undef.
8938 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
8940 // Check that we were able to transform all incoming values to the same
8942 if (VecIn2.getValueType() != VecIn1.getValueType() ||
8943 VecIn1.getValueType() != VT)
8946 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes.
8947 if (!isTypeLegal(VT))
8950 // Return the new VECTOR_SHUFFLE node.
8954 return DAG.getVectorShuffle(VT, dl, Ops[0], Ops[1], &Mask[0]);
8960 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
8961 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
8962 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
8963 // inputs come from at most two distinct vectors, turn this into a shuffle
8966 // If we only have one input vector, we don't need to do any concatenation.
8967 if (N->getNumOperands() == 1)
8968 return N->getOperand(0);
8970 // Check if all of the operands are undefs.
8971 if (ISD::allOperandsUndef(N))
8972 return DAG.getUNDEF(N->getValueType(0));
8977 SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
8978 EVT NVT = N->getValueType(0);
8979 SDValue V = N->getOperand(0);
8981 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
8982 // Handle only simple case where vector being inserted and vector
8983 // being extracted are of same type, and are half size of larger vectors.
8984 EVT BigVT = V->getOperand(0).getValueType();
8985 EVT SmallVT = V->getOperand(1).getValueType();
8986 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits())
8989 // Only handle cases where both indexes are constants with the same type.
8990 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
8991 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2));
8993 if (InsIdx && ExtIdx &&
8994 InsIdx->getValueType(0).getSizeInBits() <= 64 &&
8995 ExtIdx->getValueType(0).getSizeInBits() <= 64) {
8997 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx)
8999 // indices are equal => V1
9000 // otherwise => (extract_subvec V1, ExtIdx)
9001 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue())
9002 return V->getOperand(1);
9003 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT,
9004 V->getOperand(0), N->getOperand(1));
9008 if (V->getOpcode() == ISD::CONCAT_VECTORS) {
9010 // (extract_subvec (concat V1, V2, ...), i)
9013 // Only operand 0 is checked as 'concat' assumes all inputs of the same type.
9014 if (V->getOperand(0).getValueType() != NVT)
9016 unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
9017 unsigned NumElems = NVT.getVectorNumElements();
9018 assert((Idx % NumElems) == 0 &&
9019 "IDX in concat is not a multiple of the result vector length.");
9020 return V->getOperand(Idx / NumElems);
9026 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
9027 EVT VT = N->getValueType(0);
9028 unsigned NumElts = VT.getVectorNumElements();
9030 SDValue N0 = N->getOperand(0);
9031 SDValue N1 = N->getOperand(1);
9033 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG");
9035 // Canonicalize shuffle undef, undef -> undef
9036 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
9037 return DAG.getUNDEF(VT);
9039 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
9041 // Canonicalize shuffle v, v -> v, undef
9043 SmallVector<int, 8> NewMask;
9044 for (unsigned i = 0; i != NumElts; ++i) {
9045 int Idx = SVN->getMaskElt(i);
9046 if (Idx >= (int)NumElts) Idx -= NumElts;
9047 NewMask.push_back(Idx);
9049 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT),
9053 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
9054 if (N0.getOpcode() == ISD::UNDEF) {
9055 SmallVector<int, 8> NewMask;
9056 for (unsigned i = 0; i != NumElts; ++i) {
9057 int Idx = SVN->getMaskElt(i);
9059 if (Idx < (int)NumElts)
9064 NewMask.push_back(Idx);
9066 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT),
9070 // Remove references to rhs if it is undef
9071 if (N1.getOpcode() == ISD::UNDEF) {
9072 bool Changed = false;
9073 SmallVector<int, 8> NewMask;
9074 for (unsigned i = 0; i != NumElts; ++i) {
9075 int Idx = SVN->getMaskElt(i);
9076 if (Idx >= (int)NumElts) {
9080 NewMask.push_back(Idx);
9083 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]);
9086 // If it is a splat, check if the argument vector is another splat or a
9087 // build_vector with all scalar elements the same.
9088 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
9089 SDNode *V = N0.getNode();
9091 // If this is a bit convert that changes the element type of the vector but
9092 // not the number of vector elements, look through it. Be careful not to
9093 // look though conversions that change things like v4f32 to v2f64.
9094 if (V->getOpcode() == ISD::BITCAST) {
9095 SDValue ConvInput = V->getOperand(0);
9096 if (ConvInput.getValueType().isVector() &&
9097 ConvInput.getValueType().getVectorNumElements() == NumElts)
9098 V = ConvInput.getNode();
9101 if (V->getOpcode() == ISD::BUILD_VECTOR) {
9102 assert(V->getNumOperands() == NumElts &&
9103 "BUILD_VECTOR has wrong number of operands");
9105 bool AllSame = true;
9106 for (unsigned i = 0; i != NumElts; ++i) {
9107 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
9108 Base = V->getOperand(i);
9112 // Splat of <u, u, u, u>, return <u, u, u, u>
9113 if (!Base.getNode())
9115 for (unsigned i = 0; i != NumElts; ++i) {
9116 if (V->getOperand(i) != Base) {
9121 // Splat of <x, x, x, x>, return <x, x, x, x>
9127 // If this shuffle node is simply a swizzle of another shuffle node,
9128 // and it reverses the swizzle of the previous shuffle then we can
9129 // optimize shuffle(shuffle(x, undef), undef) -> x.
9130 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
9131 N1.getOpcode() == ISD::UNDEF) {
9133 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
9135 // Shuffle nodes can only reverse shuffles with a single non-undef value.
9136 if (N0.getOperand(1).getOpcode() != ISD::UNDEF)
9139 // The incoming shuffle must be of the same type as the result of the
9141 assert(OtherSV->getOperand(0).getValueType() == VT &&
9142 "Shuffle types don't match");
9144 for (unsigned i = 0; i != NumElts; ++i) {
9145 int Idx = SVN->getMaskElt(i);
9146 assert(Idx < (int)NumElts && "Index references undef operand");
9147 // Next, this index comes from the first value, which is the incoming
9148 // shuffle. Adopt the incoming index.
9150 Idx = OtherSV->getMaskElt(Idx);
9152 // The combined shuffle must map each index to itself.
9153 if (Idx >= 0 && (unsigned)Idx != i)
9157 return OtherSV->getOperand(0);
9163 SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) {
9164 if (!TLI.getShouldFoldAtomicFences())
9167 SDValue atomic = N->getOperand(0);
9168 switch (atomic.getOpcode()) {
9169 case ISD::ATOMIC_CMP_SWAP:
9170 case ISD::ATOMIC_SWAP:
9171 case ISD::ATOMIC_LOAD_ADD:
9172 case ISD::ATOMIC_LOAD_SUB:
9173 case ISD::ATOMIC_LOAD_AND:
9174 case ISD::ATOMIC_LOAD_OR:
9175 case ISD::ATOMIC_LOAD_XOR:
9176 case ISD::ATOMIC_LOAD_NAND:
9177 case ISD::ATOMIC_LOAD_MIN:
9178 case ISD::ATOMIC_LOAD_MAX:
9179 case ISD::ATOMIC_LOAD_UMIN:
9180 case ISD::ATOMIC_LOAD_UMAX:
9186 SDValue fence = atomic.getOperand(0);
9187 if (fence.getOpcode() != ISD::MEMBARRIER)
9190 switch (atomic.getOpcode()) {
9191 case ISD::ATOMIC_CMP_SWAP:
9192 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
9193 fence.getOperand(0),
9194 atomic.getOperand(1), atomic.getOperand(2),
9195 atomic.getOperand(3)), atomic.getResNo());
9196 case ISD::ATOMIC_SWAP:
9197 case ISD::ATOMIC_LOAD_ADD:
9198 case ISD::ATOMIC_LOAD_SUB:
9199 case ISD::ATOMIC_LOAD_AND:
9200 case ISD::ATOMIC_LOAD_OR:
9201 case ISD::ATOMIC_LOAD_XOR:
9202 case ISD::ATOMIC_LOAD_NAND:
9203 case ISD::ATOMIC_LOAD_MIN:
9204 case ISD::ATOMIC_LOAD_MAX:
9205 case ISD::ATOMIC_LOAD_UMIN:
9206 case ISD::ATOMIC_LOAD_UMAX:
9207 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
9208 fence.getOperand(0),
9209 atomic.getOperand(1), atomic.getOperand(2)),
9216 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
9217 /// an AND to a vector_shuffle with the destination vector and a zero vector.
9218 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
9219 /// vector_shuffle V, Zero, <0, 4, 2, 4>
9220 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
9221 EVT VT = N->getValueType(0);
9222 DebugLoc dl = N->getDebugLoc();
9223 SDValue LHS = N->getOperand(0);
9224 SDValue RHS = N->getOperand(1);
9225 if (N->getOpcode() == ISD::AND) {
9226 if (RHS.getOpcode() == ISD::BITCAST)
9227 RHS = RHS.getOperand(0);
9228 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
9229 SmallVector<int, 8> Indices;
9230 unsigned NumElts = RHS.getNumOperands();
9231 for (unsigned i = 0; i != NumElts; ++i) {
9232 SDValue Elt = RHS.getOperand(i);
9233 if (!isa<ConstantSDNode>(Elt))
9236 if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
9237 Indices.push_back(i);
9238 else if (cast<ConstantSDNode>(Elt)->isNullValue())
9239 Indices.push_back(NumElts);
9244 // Let's see if the target supports this vector_shuffle.
9245 EVT RVT = RHS.getValueType();
9246 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
9249 // Return the new VECTOR_SHUFFLE node.
9250 EVT EltVT = RVT.getVectorElementType();
9251 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
9252 DAG.getConstant(0, EltVT));
9253 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
9254 RVT, &ZeroOps[0], ZeroOps.size());
9255 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
9256 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
9257 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
9264 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
9265 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
9266 assert(N->getValueType(0).isVector() &&
9267 "SimplifyVBinOp only works on vectors!");
9269 SDValue LHS = N->getOperand(0);
9270 SDValue RHS = N->getOperand(1);
9271 SDValue Shuffle = XformToShuffleWithZero(N);
9272 if (Shuffle.getNode()) return Shuffle;
9274 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
9276 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
9277 RHS.getOpcode() == ISD::BUILD_VECTOR) {
9278 SmallVector<SDValue, 8> Ops;
9279 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
9280 SDValue LHSOp = LHS.getOperand(i);
9281 SDValue RHSOp = RHS.getOperand(i);
9282 // If these two elements can't be folded, bail out.
9283 if ((LHSOp.getOpcode() != ISD::UNDEF &&
9284 LHSOp.getOpcode() != ISD::Constant &&
9285 LHSOp.getOpcode() != ISD::ConstantFP) ||
9286 (RHSOp.getOpcode() != ISD::UNDEF &&
9287 RHSOp.getOpcode() != ISD::Constant &&
9288 RHSOp.getOpcode() != ISD::ConstantFP))
9291 // Can't fold divide by zero.
9292 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
9293 N->getOpcode() == ISD::FDIV) {
9294 if ((RHSOp.getOpcode() == ISD::Constant &&
9295 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
9296 (RHSOp.getOpcode() == ISD::ConstantFP &&
9297 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
9301 EVT VT = LHSOp.getValueType();
9302 EVT RVT = RHSOp.getValueType();
9304 // Integer BUILD_VECTOR operands may have types larger than the element
9305 // size (e.g., when the element type is not legal). Prior to type
9306 // legalization, the types may not match between the two BUILD_VECTORS.
9307 // Truncate one of the operands to make them match.
9308 if (RVT.getSizeInBits() > VT.getSizeInBits()) {
9309 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp);
9311 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp);
9315 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT,
9317 if (FoldOp.getOpcode() != ISD::UNDEF &&
9318 FoldOp.getOpcode() != ISD::Constant &&
9319 FoldOp.getOpcode() != ISD::ConstantFP)
9321 Ops.push_back(FoldOp);
9322 AddToWorkList(FoldOp.getNode());
9325 if (Ops.size() == LHS.getNumOperands())
9326 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
9327 LHS.getValueType(), &Ops[0], Ops.size());
9333 /// SimplifyVUnaryOp - Visit a binary vector operation, like FABS/FNEG.
9334 SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) {
9335 assert(N->getValueType(0).isVector() &&
9336 "SimplifyVUnaryOp only works on vectors!");
9338 SDValue N0 = N->getOperand(0);
9340 if (N0.getOpcode() != ISD::BUILD_VECTOR)
9343 // Operand is a BUILD_VECTOR node, see if we can constant fold it.
9344 SmallVector<SDValue, 8> Ops;
9345 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
9346 SDValue Op = N0.getOperand(i);
9347 if (Op.getOpcode() != ISD::UNDEF &&
9348 Op.getOpcode() != ISD::ConstantFP)
9350 EVT EltVT = Op.getValueType();
9351 SDValue FoldOp = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), EltVT, Op);
9352 if (FoldOp.getOpcode() != ISD::UNDEF &&
9353 FoldOp.getOpcode() != ISD::ConstantFP)
9355 Ops.push_back(FoldOp);
9356 AddToWorkList(FoldOp.getNode());
9359 if (Ops.size() != N0.getNumOperands())
9362 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
9363 N0.getValueType(), &Ops[0], Ops.size());
9366 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
9367 SDValue N1, SDValue N2){
9368 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
9370 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
9371 cast<CondCodeSDNode>(N0.getOperand(2))->get());
9373 // If we got a simplified select_cc node back from SimplifySelectCC, then
9374 // break it down into a new SETCC node, and a new SELECT node, and then return
9375 // the SELECT node, since we were called with a SELECT node.
9376 if (SCC.getNode()) {
9377 // Check to see if we got a select_cc back (to turn into setcc/select).
9378 // Otherwise, just return whatever node we got back, like fabs.
9379 if (SCC.getOpcode() == ISD::SELECT_CC) {
9380 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
9382 SCC.getOperand(0), SCC.getOperand(1),
9384 AddToWorkList(SETCC.getNode());
9385 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
9386 SCC.getOperand(2), SCC.getOperand(3), SETCC);
9394 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
9395 /// are the two values being selected between, see if we can simplify the
9396 /// select. Callers of this should assume that TheSelect is deleted if this
9397 /// returns true. As such, they should return the appropriate thing (e.g. the
9398 /// node) back to the top-level of the DAG combiner loop to avoid it being
9400 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
9403 // Cannot simplify select with vector condition
9404 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
9406 // If this is a select from two identical things, try to pull the operation
9407 // through the select.
9408 if (LHS.getOpcode() != RHS.getOpcode() ||
9409 !LHS.hasOneUse() || !RHS.hasOneUse())
9412 // If this is a load and the token chain is identical, replace the select
9413 // of two loads with a load through a select of the address to load from.
9414 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
9415 // constants have been dropped into the constant pool.
9416 if (LHS.getOpcode() == ISD::LOAD) {
9417 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
9418 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
9420 // Token chains must be identical.
9421 if (LHS.getOperand(0) != RHS.getOperand(0) ||
9422 // Do not let this transformation reduce the number of volatile loads.
9423 LLD->isVolatile() || RLD->isVolatile() ||
9424 // If this is an EXTLOAD, the VT's must match.
9425 LLD->getMemoryVT() != RLD->getMemoryVT() ||
9426 // If this is an EXTLOAD, the kind of extension must match.
9427 (LLD->getExtensionType() != RLD->getExtensionType() &&
9428 // The only exception is if one of the extensions is anyext.
9429 LLD->getExtensionType() != ISD::EXTLOAD &&
9430 RLD->getExtensionType() != ISD::EXTLOAD) ||
9431 // FIXME: this discards src value information. This is
9432 // over-conservative. It would be beneficial to be able to remember
9433 // both potential memory locations. Since we are discarding
9434 // src value info, don't do the transformation if the memory
9435 // locations are not in the default address space.
9436 LLD->getPointerInfo().getAddrSpace() != 0 ||
9437 RLD->getPointerInfo().getAddrSpace() != 0 ||
9438 !TLI.isOperationLegalOrCustom(TheSelect->getOpcode(),
9439 LLD->getBasePtr().getValueType()))
9442 // Check that the select condition doesn't reach either load. If so,
9443 // folding this will induce a cycle into the DAG. If not, this is safe to
9444 // xform, so create a select of the addresses.
9446 if (TheSelect->getOpcode() == ISD::SELECT) {
9447 SDNode *CondNode = TheSelect->getOperand(0).getNode();
9448 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
9449 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
9451 // The loads must not depend on one another.
9452 if (LLD->isPredecessorOf(RLD) ||
9453 RLD->isPredecessorOf(LLD))
9455 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
9456 LLD->getBasePtr().getValueType(),
9457 TheSelect->getOperand(0), LLD->getBasePtr(),
9459 } else { // Otherwise SELECT_CC
9460 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
9461 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
9463 if ((LLD->hasAnyUseOfValue(1) &&
9464 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
9465 (RLD->hasAnyUseOfValue(1) &&
9466 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS))))
9469 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
9470 LLD->getBasePtr().getValueType(),
9471 TheSelect->getOperand(0),
9472 TheSelect->getOperand(1),
9473 LLD->getBasePtr(), RLD->getBasePtr(),
9474 TheSelect->getOperand(4));
9478 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
9479 Load = DAG.getLoad(TheSelect->getValueType(0),
9480 TheSelect->getDebugLoc(),
9481 // FIXME: Discards pointer info.
9482 LLD->getChain(), Addr, MachinePointerInfo(),
9483 LLD->isVolatile(), LLD->isNonTemporal(),
9484 LLD->isInvariant(), LLD->getAlignment());
9486 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
9487 RLD->getExtensionType() : LLD->getExtensionType(),
9488 TheSelect->getDebugLoc(),
9489 TheSelect->getValueType(0),
9490 // FIXME: Discards pointer info.
9491 LLD->getChain(), Addr, MachinePointerInfo(),
9492 LLD->getMemoryVT(), LLD->isVolatile(),
9493 LLD->isNonTemporal(), LLD->getAlignment());
9496 // Users of the select now use the result of the load.
9497 CombineTo(TheSelect, Load);
9499 // Users of the old loads now use the new load's chain. We know the
9500 // old-load value is dead now.
9501 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
9502 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
9509 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
9510 /// where 'cond' is the comparison specified by CC.
9511 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
9512 SDValue N2, SDValue N3,
9513 ISD::CondCode CC, bool NotExtCompare) {
9514 // (x ? y : y) -> y.
9515 if (N2 == N3) return N2;
9517 EVT VT = N2.getValueType();
9518 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
9519 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
9520 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
9522 // Determine if the condition we're dealing with is constant
9523 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
9524 N0, N1, CC, DL, false);
9525 if (SCC.getNode()) AddToWorkList(SCC.getNode());
9526 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
9528 // fold select_cc true, x, y -> x
9529 if (SCCC && !SCCC->isNullValue())
9531 // fold select_cc false, x, y -> y
9532 if (SCCC && SCCC->isNullValue())
9535 // Check to see if we can simplify the select into an fabs node
9536 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
9537 // Allow either -0.0 or 0.0
9538 if (CFP->getValueAPF().isZero()) {
9539 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
9540 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
9541 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
9542 N2 == N3.getOperand(0))
9543 return DAG.getNode(ISD::FABS, DL, VT, N0);
9545 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
9546 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
9547 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
9548 N2.getOperand(0) == N3)
9549 return DAG.getNode(ISD::FABS, DL, VT, N3);
9553 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
9554 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
9555 // in it. This is a win when the constant is not otherwise available because
9556 // it replaces two constant pool loads with one. We only do this if the FP
9557 // type is known to be legal, because if it isn't, then we are before legalize
9558 // types an we want the other legalization to happen first (e.g. to avoid
9559 // messing with soft float) and if the ConstantFP is not legal, because if
9560 // it is legal, we may not need to store the FP constant in a constant pool.
9561 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
9562 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
9563 if (TLI.isTypeLegal(N2.getValueType()) &&
9564 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
9565 TargetLowering::Legal) &&
9566 // If both constants have multiple uses, then we won't need to do an
9567 // extra load, they are likely around in registers for other users.
9568 (TV->hasOneUse() || FV->hasOneUse())) {
9569 Constant *Elts[] = {
9570 const_cast<ConstantFP*>(FV->getConstantFPValue()),
9571 const_cast<ConstantFP*>(TV->getConstantFPValue())
9573 Type *FPTy = Elts[0]->getType();
9574 const DataLayout &TD = *TLI.getDataLayout();
9576 // Create a ConstantArray of the two constants.
9577 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
9578 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
9579 TD.getPrefTypeAlignment(FPTy));
9580 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9582 // Get the offsets to the 0 and 1 element of the array so that we can
9583 // select between them.
9584 SDValue Zero = DAG.getIntPtrConstant(0);
9585 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
9586 SDValue One = DAG.getIntPtrConstant(EltSize);
9588 SDValue Cond = DAG.getSetCC(DL,
9589 TLI.getSetCCResultType(N0.getValueType()),
9591 AddToWorkList(Cond.getNode());
9592 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
9594 AddToWorkList(CstOffset.getNode());
9595 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
9597 AddToWorkList(CPIdx.getNode());
9598 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
9599 MachinePointerInfo::getConstantPool(), false,
9600 false, false, Alignment);
9605 // Check to see if we can perform the "gzip trick", transforming
9606 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
9607 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
9608 (N1C->isNullValue() || // (a < 0) ? b : 0
9609 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
9610 EVT XType = N0.getValueType();
9611 EVT AType = N2.getValueType();
9612 if (XType.bitsGE(AType)) {
9613 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
9614 // single-bit constant.
9615 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
9616 unsigned ShCtV = N2C->getAPIntValue().logBase2();
9617 ShCtV = XType.getSizeInBits()-ShCtV-1;
9618 SDValue ShCt = DAG.getConstant(ShCtV,
9619 getShiftAmountTy(N0.getValueType()));
9620 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
9622 AddToWorkList(Shift.getNode());
9624 if (XType.bitsGT(AType)) {
9625 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
9626 AddToWorkList(Shift.getNode());
9629 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
9632 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
9634 DAG.getConstant(XType.getSizeInBits()-1,
9635 getShiftAmountTy(N0.getValueType())));
9636 AddToWorkList(Shift.getNode());
9638 if (XType.bitsGT(AType)) {
9639 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
9640 AddToWorkList(Shift.getNode());
9643 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
9647 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
9648 // where y is has a single bit set.
9649 // A plaintext description would be, we can turn the SELECT_CC into an AND
9650 // when the condition can be materialized as an all-ones register. Any
9651 // single bit-test can be materialized as an all-ones register with
9652 // shift-left and shift-right-arith.
9653 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
9654 N0->getValueType(0) == VT &&
9655 N1C && N1C->isNullValue() &&
9656 N2C && N2C->isNullValue()) {
9657 SDValue AndLHS = N0->getOperand(0);
9658 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
9659 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
9660 // Shift the tested bit over the sign bit.
9661 APInt AndMask = ConstAndRHS->getAPIntValue();
9663 DAG.getConstant(AndMask.countLeadingZeros(),
9664 getShiftAmountTy(AndLHS.getValueType()));
9665 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt);
9667 // Now arithmetic right shift it all the way over, so the result is either
9668 // all-ones, or zero.
9670 DAG.getConstant(AndMask.getBitWidth()-1,
9671 getShiftAmountTy(Shl.getValueType()));
9672 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt);
9674 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
9678 // fold select C, 16, 0 -> shl C, 4
9679 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
9680 TLI.getBooleanContents(N0.getValueType().isVector()) ==
9681 TargetLowering::ZeroOrOneBooleanContent) {
9683 // If the caller doesn't want us to simplify this into a zext of a compare,
9685 if (NotExtCompare && N2C->getAPIntValue() == 1)
9688 // Get a SetCC of the condition
9689 // NOTE: Don't create a SETCC if it's not legal on this target.
9690 if (!LegalOperations ||
9691 TLI.isOperationLegal(ISD::SETCC,
9692 LegalTypes ? TLI.getSetCCResultType(N0.getValueType()) : MVT::i1)) {
9694 // cast from setcc result type to select result type
9696 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
9698 if (N2.getValueType().bitsLT(SCC.getValueType()))
9699 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(),
9702 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
9703 N2.getValueType(), SCC);
9705 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
9706 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
9707 N2.getValueType(), SCC);
9710 AddToWorkList(SCC.getNode());
9711 AddToWorkList(Temp.getNode());
9713 if (N2C->getAPIntValue() == 1)
9716 // shl setcc result by log2 n2c
9717 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
9718 DAG.getConstant(N2C->getAPIntValue().logBase2(),
9719 getShiftAmountTy(Temp.getValueType())));
9723 // Check to see if this is the equivalent of setcc
9724 // FIXME: Turn all of these into setcc if setcc if setcc is legal
9725 // otherwise, go ahead with the folds.
9726 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
9727 EVT XType = N0.getValueType();
9728 if (!LegalOperations ||
9729 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
9730 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
9731 if (Res.getValueType() != VT)
9732 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
9736 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
9737 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
9738 (!LegalOperations ||
9739 TLI.isOperationLegal(ISD::CTLZ, XType))) {
9740 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
9741 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
9742 DAG.getConstant(Log2_32(XType.getSizeInBits()),
9743 getShiftAmountTy(Ctlz.getValueType())));
9745 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
9746 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
9747 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
9748 XType, DAG.getConstant(0, XType), N0);
9749 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
9750 return DAG.getNode(ISD::SRL, DL, XType,
9751 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
9752 DAG.getConstant(XType.getSizeInBits()-1,
9753 getShiftAmountTy(XType)));
9755 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
9756 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
9757 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
9758 DAG.getConstant(XType.getSizeInBits()-1,
9759 getShiftAmountTy(N0.getValueType())));
9760 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
9764 // Check to see if this is an integer abs.
9765 // select_cc setg[te] X, 0, X, -X ->
9766 // select_cc setgt X, -1, X, -X ->
9767 // select_cc setl[te] X, 0, -X, X ->
9768 // select_cc setlt X, 1, -X, X ->
9769 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
9771 ConstantSDNode *SubC = NULL;
9772 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
9773 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
9774 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
9775 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
9776 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
9777 (N1C->isOne() && CC == ISD::SETLT)) &&
9778 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
9779 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
9781 EVT XType = N0.getValueType();
9782 if (SubC && SubC->isNullValue() && XType.isInteger()) {
9783 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
9785 DAG.getConstant(XType.getSizeInBits()-1,
9786 getShiftAmountTy(N0.getValueType())));
9787 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
9789 AddToWorkList(Shift.getNode());
9790 AddToWorkList(Add.getNode());
9791 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
9798 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
9799 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
9800 SDValue N1, ISD::CondCode Cond,
9801 DebugLoc DL, bool foldBooleans) {
9802 TargetLowering::DAGCombinerInfo
9803 DagCombineInfo(DAG, Level, false, this);
9804 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
9807 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
9808 /// return a DAG expression to select that will generate the same value by
9809 /// multiplying by a magic number. See:
9810 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
9811 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
9812 std::vector<SDNode*> Built;
9813 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built);
9815 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
9821 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
9822 /// return a DAG expression to select that will generate the same value by
9823 /// multiplying by a magic number. See:
9824 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
9825 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
9826 std::vector<SDNode*> Built;
9827 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built);
9829 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
9835 /// FindBaseOffset - Return true if base is a frame index, which is known not
9836 // to alias with anything but itself. Provides base object and offset as
9838 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
9839 const GlobalValue *&GV, const void *&CV) {
9840 // Assume it is a primitive operation.
9841 Base = Ptr; Offset = 0; GV = 0; CV = 0;
9843 // If it's an adding a simple constant then integrate the offset.
9844 if (Base.getOpcode() == ISD::ADD) {
9845 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
9846 Base = Base.getOperand(0);
9847 Offset += C->getZExtValue();
9851 // Return the underlying GlobalValue, and update the Offset. Return false
9852 // for GlobalAddressSDNode since the same GlobalAddress may be represented
9853 // by multiple nodes with different offsets.
9854 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
9855 GV = G->getGlobal();
9856 Offset += G->getOffset();
9860 // Return the underlying Constant value, and update the Offset. Return false
9861 // for ConstantSDNodes since the same constant pool entry may be represented
9862 // by multiple nodes with different offsets.
9863 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
9864 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal()
9865 : (const void *)C->getConstVal();
9866 Offset += C->getOffset();
9869 // If it's any of the following then it can't alias with anything but itself.
9870 return isa<FrameIndexSDNode>(Base);
9873 /// isAlias - Return true if there is any possibility that the two addresses
9875 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
9876 const Value *SrcValue1, int SrcValueOffset1,
9877 unsigned SrcValueAlign1,
9878 const MDNode *TBAAInfo1,
9879 SDValue Ptr2, int64_t Size2,
9880 const Value *SrcValue2, int SrcValueOffset2,
9881 unsigned SrcValueAlign2,
9882 const MDNode *TBAAInfo2) const {
9883 // If they are the same then they must be aliases.
9884 if (Ptr1 == Ptr2) return true;
9886 // Gather base node and offset information.
9887 SDValue Base1, Base2;
9888 int64_t Offset1, Offset2;
9889 const GlobalValue *GV1, *GV2;
9890 const void *CV1, *CV2;
9891 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
9892 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
9894 // If they have a same base address then check to see if they overlap.
9895 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
9896 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
9898 // It is possible for different frame indices to alias each other, mostly
9899 // when tail call optimization reuses return address slots for arguments.
9900 // To catch this case, look up the actual index of frame indices to compute
9901 // the real alias relationship.
9902 if (isFrameIndex1 && isFrameIndex2) {
9903 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9904 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
9905 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
9906 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
9909 // Otherwise, if we know what the bases are, and they aren't identical, then
9910 // we know they cannot alias.
9911 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
9914 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
9915 // compared to the size and offset of the access, we may be able to prove they
9916 // do not alias. This check is conservative for now to catch cases created by
9917 // splitting vector types.
9918 if ((SrcValueAlign1 == SrcValueAlign2) &&
9919 (SrcValueOffset1 != SrcValueOffset2) &&
9920 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
9921 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
9922 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
9924 // There is no overlap between these relatively aligned accesses of similar
9925 // size, return no alias.
9926 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
9930 if (CombinerGlobalAA) {
9931 // Use alias analysis information.
9932 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
9933 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
9934 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
9935 AliasAnalysis::AliasResult AAResult =
9936 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1),
9937 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2));
9938 if (AAResult == AliasAnalysis::NoAlias)
9942 // Otherwise we have to assume they alias.
9946 bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) {
9948 int64_t Size0, Size1;
9949 const Value *SrcValue0, *SrcValue1;
9950 int SrcValueOffset0, SrcValueOffset1;
9951 unsigned SrcValueAlign0, SrcValueAlign1;
9952 const MDNode *SrcTBAAInfo0, *SrcTBAAInfo1;
9953 FindAliasInfo(Op0, Ptr0, Size0, SrcValue0, SrcValueOffset0,
9954 SrcValueAlign0, SrcTBAAInfo0);
9955 FindAliasInfo(Op1, Ptr1, Size1, SrcValue1, SrcValueOffset1,
9956 SrcValueAlign1, SrcTBAAInfo1);
9957 return isAlias(Ptr0, Size0, SrcValue0, SrcValueOffset0,
9958 SrcValueAlign0, SrcTBAAInfo0,
9959 Ptr1, Size1, SrcValue1, SrcValueOffset1,
9960 SrcValueAlign1, SrcTBAAInfo1);
9963 /// FindAliasInfo - Extracts the relevant alias information from the memory
9964 /// node. Returns true if the operand was a load.
9965 bool DAGCombiner::FindAliasInfo(SDNode *N,
9966 SDValue &Ptr, int64_t &Size,
9967 const Value *&SrcValue,
9968 int &SrcValueOffset,
9969 unsigned &SrcValueAlign,
9970 const MDNode *&TBAAInfo) const {
9971 LSBaseSDNode *LS = cast<LSBaseSDNode>(N);
9973 Ptr = LS->getBasePtr();
9974 Size = LS->getMemoryVT().getSizeInBits() >> 3;
9975 SrcValue = LS->getSrcValue();
9976 SrcValueOffset = LS->getSrcValueOffset();
9977 SrcValueAlign = LS->getOriginalAlignment();
9978 TBAAInfo = LS->getTBAAInfo();
9979 return isa<LoadSDNode>(LS);
9982 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
9983 /// looking for aliasing nodes and adding them to the Aliases vector.
9984 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
9985 SmallVector<SDValue, 8> &Aliases) {
9986 SmallVector<SDValue, 8> Chains; // List of chains to visit.
9987 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
9989 // Get alias information for node.
9992 const Value *SrcValue;
9994 unsigned SrcValueAlign;
9995 const MDNode *SrcTBAAInfo;
9996 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
9997 SrcValueAlign, SrcTBAAInfo);
10000 Chains.push_back(OriginalChain);
10001 unsigned Depth = 0;
10003 // Look at each chain and determine if it is an alias. If so, add it to the
10004 // aliases list. If not, then continue up the chain looking for the next
10006 while (!Chains.empty()) {
10007 SDValue Chain = Chains.back();
10010 // For TokenFactor nodes, look at each operand and only continue up the
10011 // chain until we find two aliases. If we've seen two aliases, assume we'll
10012 // find more and revert to original chain since the xform is unlikely to be
10015 // FIXME: The depth check could be made to return the last non-aliasing
10016 // chain we found before we hit a tokenfactor rather than the original
10018 if (Depth > 6 || Aliases.size() == 2) {
10020 Aliases.push_back(OriginalChain);
10024 // Don't bother if we've been before.
10025 if (!Visited.insert(Chain.getNode()))
10028 switch (Chain.getOpcode()) {
10029 case ISD::EntryToken:
10030 // Entry token is ideal chain operand, but handled in FindBetterChain.
10035 // Get alias information for Chain.
10038 const Value *OpSrcValue;
10039 int OpSrcValueOffset;
10040 unsigned OpSrcValueAlign;
10041 const MDNode *OpSrcTBAAInfo;
10042 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
10043 OpSrcValue, OpSrcValueOffset,
10047 // If chain is alias then stop here.
10048 if (!(IsLoad && IsOpLoad) &&
10049 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
10051 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
10052 OpSrcValueAlign, OpSrcTBAAInfo)) {
10053 Aliases.push_back(Chain);
10055 // Look further up the chain.
10056 Chains.push_back(Chain.getOperand(0));
10062 case ISD::TokenFactor:
10063 // We have to check each of the operands of the token factor for "small"
10064 // token factors, so we queue them up. Adding the operands to the queue
10065 // (stack) in reverse order maintains the original order and increases the
10066 // likelihood that getNode will find a matching token factor (CSE.)
10067 if (Chain.getNumOperands() > 16) {
10068 Aliases.push_back(Chain);
10071 for (unsigned n = Chain.getNumOperands(); n;)
10072 Chains.push_back(Chain.getOperand(--n));
10077 // For all other instructions we will just have to take what we can get.
10078 Aliases.push_back(Chain);
10084 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
10085 /// for a better chain (aliasing node.)
10086 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
10087 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
10089 // Accumulate all the aliases to this node.
10090 GatherAllAliases(N, OldChain, Aliases);
10092 // If no operands then chain to entry token.
10093 if (Aliases.size() == 0)
10094 return DAG.getEntryNode();
10096 // If a single operand then chain to it. We don't need to revisit it.
10097 if (Aliases.size() == 1)
10100 // Construct a custom tailored token factor.
10101 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
10102 &Aliases[0], Aliases.size());
10105 // SelectionDAG::Combine - This is the entry point for the file.
10107 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
10108 CodeGenOpt::Level OptLevel) {
10109 /// run - This is the main entry point to this class.
10111 DAGCombiner(*this, AA, OptLevel).Run(Level);